SP 507 Course Contents

Usman Institute of Technology UIT
Usman Institute of Technology

Course Specification
Course Code: SP 507

Course Title: Advance Digital Electronics
Scheme: Postgraduate
Credit Rating: 3 + 0 credits
Delivery method: Lectures: 48 hrs
Discipline involved: Communication & Signal Processing
Course Tutors: Engr. Atif Fareed (AF)
(Asst. Professor)
Recommended prior learning: Revision of the Logic Families and Fundamental Architecture
of the digital circuits.
Course aims: The objective of Advanced Digital Electronics courses is to

bridge logic gates (combinational circuits) with technical topics
related to topologies (Asynchronous & Synchronous), DSP
(Digital Signal Processors) which fall under the sequential
devices umbrella. The fundamental design tools of using how
combinational circuits can assist in the construction of such
sequential digital devices mentioned. To provide a synthesis of
how these digital building blocks are used in the creation of
industrial equipment and consumer products,
Course synopsis: This Course will enable you to develop strong design skills for
the seamless integration of hardware subsystems and the
emphasis will be on hardware co-design methodologies.
These design skills will be developed by studying a range of
specialist processor architectures and acceleration
mechanisms. You will be taught by experienced research and
teaching staff with expertise in this field and you will be
learning about the latest theories, techniques and
technologies.
Learning Outcomes
Knowledge and Understanding
 The main building blocks of digital circuits.
 Microprocessor systems, in particular microcontrollers.
 The practical aspects of digital electronics.
Intellectual Skills
Having successfully completed the module, you will be able to:
 Design combinational logic circuits.
 Design sequential logic systems such as binary counters.
 Understand the basic philosophy of microcontrollers.
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Practical Skills
Having successfully completed the module, you will be able to:
 Construct digital electronic circuits.
 De-bug hardware faults within digital electronic circuits.
 Assemble and test digital integrated circuits (ICs), configured into functional systems.
Outline syllabus of topics to be covered:
Lectures / Lecture Topics

Week
INTRODUCTION TO SUBJECT, ANALOG AND DIGITAL SYSTEMS,
LOGIC FAMILIES GENERAL CLASSIFICATION,APPROACHES OF DIGITAL CIRCUIT
Week # 01 DESIGN,SALIENT FEATURES OF KEY LOGICAL FAMILIES (CMOS FAMILY,BIPOLAR
FAMILY, BiCMOS FAMILY,GaAs FAMILY, BIPOLAR & ADVANCED TECHNOLOGY
CIRCUITS)
SWITCHING STATES OF A DEVICE (BIPOLAR TRANSISTOR) RTL, DTL, REASONS OF
SLOW RESPONSE OF DTL, EVOLUTION OF TTL FROM DTL, DTL INTEGRATED
Week # 02 APPROACH, TTL INPUT CIRCUIT
TTL INPUT CIRCUIT,TTL OUTPUT CIRCUIT, OUTPUT STAGES, TOTEM-POLE OUTPUT

STAGE,COMPLETE CIRCUIT OF TTL, FUNCTION OF 130 OHM COLLECTOR
Week # 03 RESISTOR,TRANSFER CHARACTERISTICS OF STANDARD TTL,MANUFACTURER'S
SPECS, PROPAGATION DELAY, DYNAMIC POWER DISSIPATION, TTL NAND GATE
PROPAGATION DELAY, DYNAMIC POWER DISSIPATION,TTL NAND GATE,TTL AND

OR INVERT FUNCTION, TRI-STATE TTL,TTL FAMILIES WITH IMPROVED
Week # 04 PERFORMANCE: SCHOTTKY TTL INTRO.,SCHOTTKY TTL (CONTD.) ACTIVE PULL
DOWN NETWORK
LOW POWER SCHOTTKY TTL, THE LOW POWER SCHOTTKY TTL: 74LS,
TTL OTHER IMPROVED FAMILIES AND THEIR COMPARISON, BASICS OF EMITTER
Week # 05 COUPLED LOGIC (ECL),TRANSMISSION LINES AND RINGING, VOLTAGE TRANSFER
CHARACTERISTICS, THE OR TRANSFER CURVE
NOISE MARGINS, THE NOR TRANSFER CURVE, MANUFACTURER'S SPECS: FAN OUT,
SPEED, SIGNAL TRANSMISSION, POWER DISSIPATION, THERMAL EFFECTS, WIRED
Week # 06 OR CAPABILITY.
THE CMOS LOGIC FAMILY , BASIC CMOS INVERTER, STATIC OPERATION,THE

BASIC CMOS INVERTER DYNAMIC OPERATION, DYNAMIC POWER DISSIPATION,
Week # 07 CMOS LOGIC GATES: TWO INPUT NOR GATE, TWO INPUT NAND GATE
A COMPLEX CMOS GATE, OBTAINING THE PUN NETWORK FROM THE PDN
Week # 08 NETWORK AND VICE VERSA, THE EXCLUSIVE OR FUNCTION, TRANSISTOR SIZING
EFFECTS OF FAN IN AND FAN OUT ON PROPAGATION DELAY OF CMOS,

Week # 09 PSEUDO NMOS LOGIC CIRCUITS, PASS TRANSISTOR LOGIC CIRCUITS
DYNAMIC LOGIC CIRCUITS, CHARGE SHARING, CASCADING DYNAMIC LOGIC

Week # 10 CIRCUITS, DOMINO LOGIC
BiCMOS TECHNOLOGY,BASIC BiCMOS INVERTER AND ITS DYNAMIC OPERATION,

Week # 11 GALLIUM ARENIDE (GaAs) DIGITAL CIRCUITS ,
LOGIC FAMILY INTERFACING SWITCH DE-BOUNCING TECHNIQUES, DRIVING

Week # 12 LOGIC FROM COMPARATORS & OP AMPS.
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DRIVING DIFFERENT LOADS FROM TTL AND CMOS, PROGRAMMABLE LOGIC

Week # 13 DEVICES PLDs ,GENERAL STRUCTURE OF PLA
PROGRAMMABLE LOGIC DEVICES PLDs ,GENERAL STRUCTURE OF PLA,

Week # 14 IMPLEMENTATION DETAILS FOR SPLDs, CPLDs AND FPGAs
EEPROM BASED PROGRAMMABLE SWITCHES/TRANSISTOR

Week # 15
PROGRAMMABLE VERSION OF THE NOR-NOR PLA: POS VERSION,
Week # 16 IMPLEMENTATION IN FPGAs
Indicative learning strategy:

Lectures will provide an introduction to the syllabus topics as well as discussing the theoretical aspects
of the course. A series of labs will explore a range of issues relevant to the field of subject. Students are
required to take an active role in the preparation and delivery of certain lab materials.
Indicative references/learning materials:

TEXT BOOKS
1. MICROELECTRONIC CIRCUITS
by Adel S. Sedra & Kenneth C. Smith (4th Edition)
Resources required:
Multimedia presentations will be given in theoretical lectures.
Assessment Strategy:
Assessment method Number % contribution to final mark
Written examination [exam] 01 70
Mid Term 01 20
Quiz Minimum 05 05
Assignment Minimum 05 05
Students must demonstrate basic competency in all the outcomes, listed above, in order to receive a passing grade
for the course. Basic competency will be assessed based on a specific set of exam questions, for which a passing
threshold of a minimum of 40% will be required. Two opportunities will be provided for students to demonstrate
these outcomes: (1) the primary assessment exams; and (2) the final assessment exam. A score equal to or
greater than the passing threshold on either of these evaluation instruments will be sufficient to establish basic
competency but students must have successfully demonstrated at least one of the three outcomes on the primary
assessment exams and have a passing grade (based on the results of the homework, labs, and primary
assessment exams) in order to qualify for the final.
INSTRUCTION TO THE STUDENTS:

- CELLULAR PHONES SHALL REMAIN MUTE/UNDER VIBRATION MODE IN
THE CLASS.
- ASSIGNMENT DUE DATE AND TIME SHALL BE STRICTLY FOLLOWED.
- PROPER CONSULTATION FOR INDIVIDUAL PROBLEMS CAN BE
OBTAINED BY SIMPLY WALKING INTO MY OFFICE AND DISCUSSING.
FEEL FREE TO TALK WHENEVER YOU LIKE AND I AM FREE!
- ATTENDANCE SHALL BE STRICTLY MONITORED AND WILL BE
SUBMITTED TO THE ACADEMIC ADMINISTRATION DEPARTMENT ON
WEEKLY BASIS. NO COMPENSATION WHATSOEVER IN THIS REGARD
SHALL BE CONSIDERED.
- REGULAR REVISION OF THE CLASS ROOM TEACHING IS HIGHLY
RECOMMENDED IN THIS COURSE.
ALL THE BEST!
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Usman Institute of Technology UIT

Usman Institute of Technology

Course Code: SP 507

Course aims: The objective of Advanced Digital Electronics courses is to

Lectures / Lecture Topics

TTL INPUT CIRCUIT,TTL OUTPUT CIRCUIT, OUTPUT STAGES, TOTEM-POLE OUTPUT

PROPAGATION DELAY, DYNAMIC POWER DISSIPATION,TTL NAND GATE,TTL AND

THE CMOS LOGIC FAMILY , BASIC CMOS INVERTER, STATIC OPERATION,THE

EFFECTS OF FAN IN AND FAN OUT ON PROPAGATION DELAY OF CMOS,

DYNAMIC LOGIC CIRCUITS, CHARGE SHARING, CASCADING DYNAMIC LOGIC

BiCMOS TECHNOLOGY,BASIC BiCMOS INVERTER AND ITS DYNAMIC OPERATION,

LOGIC FAMILY INTERFACING SWITCH DE-BOUNCING TECHNIQUES, DRIVING

DRIVING DIFFERENT LOADS FROM TTL AND CMOS, PROGRAMMABLE LOGIC

PROGRAMMABLE LOGIC DEVICES PLDs ,GENERAL STRUCTURE OF PLA,

EEPROM BASED PROGRAMMABLE SWITCHES/TRANSISTOR

Indicative learning strategy:

Indicative references/learning materials:

INSTRUCTION TO THE STUDENTS:

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