155 Lic Part 1

18ECC202J – Linear Integrated Circuits
ACADEMIC YEAR:2020-2021
NAME: SHASHIKANT GOSWAMI
REG.NO: RA1911004010155
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
FACULTY OF ENGINEERING AND

TECHNOLOGY SRM INSTITUTE OF SCIENCE
AND TECHNOLOGY
(Under SECTION 3 of the UGC Act, 1956)
S.R.M. NAGAR, KATTANKULATHUR –
603203. CHENGALPET
DISTRICT.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
COLLEGE OF ENGINEERING & TECHNOLOGY
SRM INSTITUTE OF SCIENCE AND TECHNOLOGY
BONAFIDE CERTIFICATE
Register No.:
Certified to be the bonafide record of work done by ___SHASHIKANT GOSWAMI_____

__________of _____E.C.E______ B.Tech. Degree course in the Practical 18ECE202J-
Linear Integrated Circuits in SRM Institute of Science and Technology, Kattankulathur
during the academic year 2020-2021
Staff In-Charge:
Date: 24/05/2021 Head of the Department
Submitted for University Examination held on ____________________ at SRM

Institute of Science and Technology, Kattankulathur.

Date: 24/05/21 Internal Examiner I Internal Examiner II
Name:SHASHIKANT GOSWAMI Class: ECE-C
Reg.No: RA1011004010155 Branch: ECE
Exp. Date of Title of Experiment Marks

No. Performan Obtain
ce ed (40)
1 22/01/21 BASIC OP AMP CIRCUIT 31
2 01/02/21 INTEGRATOR AND DIFFERENTIATOR 36

3 08/02/21 RECTIFIERS 32
4 15/02/21 COMPARATOR AND SCHMITT TRIGGER 30
5 22/02/21 WAVE SHAPING CIRCUIT USING OP AMP 36
6 01/03/21 SINE WAVE USING OP AMP 35

7 08/03/21 SQUARE WAVE GENERATOR USING OP AMP 37
8 15/03/21 DESIGN OF MONOSTABLE AND ASTABLE 36

MULTIVIBRATOR
9 22/03/21 DESIGN OF LOW PASS AND HIGH PASS FILTER 40
10 29/03/21 DESIGN OF BAND PASS AND BAND REJECT 40
FILTER
11 07/04/21 SERIES VOLTAGE REGULATOR 40
12 15/04/21 R-2R LADDER DAC 40

22/04/21 FLASH ADC 40
13
14 29/04/22 Mini Project 5

1. BASIC OP-AMP CIRCUITS

NAME – SHASHIKANT GOSWAMI (RA1911004010155) 1.1 OBJECTIVE
1. To design the following basic op-amp circuits and explain the operation of each:
a. Inverting amplifier
b. Non-inverting amplifier
c. Voltage follower
1.2 HARDWARE REQUIRED
S.No Equipment/Component name Specifications/Value Quantity
1 IC 741 Refer data sheet in 1

appendix
2 Cathode Ray Oscilloscope (0 – 20MHz) 1 1
3 Resistors 1.5K Ω 2
4 Dual Regulated power supply (0 -30V), 1A 1
5 Function Generator (0-2) MHz 1
6 ASLK PRO Kit Refer data sheet in 1

appendix
1.3.7. Design Constraints

• The output signal is limited by the IC's power sources: the output signal cannot be greater than
+15V.
1.4 PRE LAB QUESTIONS

1. Identify each of the op-amp configurations
Fig.(a)
Ans) i)Voltage follower ii)Non inverting amplifier iii) Inverting amplifier
2. A non-inverting amplifier has R1 of 2K & Rf of 200K . Determine Vf and

(Feedback voltage and feedback fraction), if V O = 5V
Ans) B=Ri/Ri+Rf=9.90*10^-3
Vf=BVo=49.5mV
3. For the amplifier in Fig.(b) determine the following: (a) ACL(NI) (b) VO
(c) Vf
Fig.(b)
ANS) i)Acl=1/B=374 ii)Vo=Acl*Vin=3.74Vrms iii)Vf=B*Vo=9.99mV
1.5 SIMULATION (1) Non-Inverting amplifier
(2) Voltage follower

.
(3) Inverting amplifier
op-amp Input signal Output signal Voltage gain

configuration /
circuit
Amplitude Frequency Amplitude Frequency Designed Observed
value value
Non-inverting 1V 100Hz 10V 100Hz 10 10

amplifier
Voltage 5V 0.83Hz 5V 0.83Hz 1 1

follower
Inverting 1V 1kHz 10V 1kHz 10 10

amplifier
1.8. POST LAB QUESTIONS

1. What is the relationship, if any, between the polarity of the output and input
voltages in your experimental op-amp? Refer to your data.
Ans)The polarity of the op-amp output depends on the polarity of the difference
between the V+ and V– inputs. Thus, if V+ is greater than V–, the output will be a
positive voltage, but if V+ is less than V–, the output will be a negative voltage. In
many op-amp circuits, one input is connected to ground.
2. Comment on the statement: “The closed-loop gain-bandwidth product is a

constant for a given op-amp”.
The closed-loop voltage gain is the voltage gain of an op-amp with external
feedback. The amplifier configuration consists of the op-amp and an external –
ve feedback circuit that connects the o/p to the inverting input. The closed
loop voltage gain is determined by the external component values and can
be precisely controlled by them.
3. Find the value of Rf that will produce closed-loop gain of 300 in each amplifier in
fig.(i)
Fig.(i)
4. Determine the approximate values for each of the following quantities in Fig.(j).
5. If a signal voltage of 10mV is applied to each amplifier in Fig.(k), what are the
output voltages?
Laboratory Report Cover Sheet
SRM Institute of Science and Technology
Faculty of Engineering and Technology
Department of Electronics and Communication
Engineering
18ECC202J LINEAR INTEGRATED CIRCUITS
Fourth Semester, 2020-21 (Even semester)
Name : shashikant goswami

Register No. :RA1911004010155
Day / Session : 4/AN
Title of Experiment : INTEGRATOR AND DIFFERENTIATOR
Date of Conduction :28/01/2021
Date of Submission :5/01/2021

Max. Marks Marks
Particulars Obtained
Pre lab and Post lab 10
Simulation and results 10
Report 10
Viva 10
Total 40
REPORT VERIFICATION
Staff Name : Kalimuthu K

Signature :
2. INTEGRATOR AND DIFFERENTIATOR

2.1 OBJECTIVE
1. Design an integrator for a frequency of 500 Hz, given R=1KΩ ,
C=0.1 µF and
Rf = 1MΩ. Conduct the experiment and plot integrated output waveforms for
various input waveforms and analyse
2. Design an differentiator for a frequency of 500 Hz, given R=1KΩ , and C=0.1µf
and R1 = 470Ω. Conduct the experiment and plot integrated output waveforms
for various input waveforms and analyse

1 IC 741 Refer data sheet in appendix 1
3 Resistors 1K Ω 1
1M Ω 1
10 K Ω 1
1
470 Ω
4 Capacitors 0.1µf 2
7 ASLK PRO Kit 1
2.3 THEORY
In this laboratory experiment, you will learn several basic ways in which an op-amp
can be connected using negative feedback to stabilize
the gain and increase the frequency response. The extremely high openloop gain of an op-
amp creates an unstable situation because a small noise voltage on the input can be amplified
to a point where the amplifier in driven out of its linear region. Also unwanted oscillations
can occur. In addition, the open-loop gain parameter of an op-amp can vary greatly from one
device to the next. Negative feedback takes a portion of output and applies it back out of
phase with the input, creating an effective reduction in gain. This closed-loop gain is usually
much less than the open-loop gain and independent of it.
2.3.1 Integrator
An op-amp integrator simulates mathematical integration which is basically a summing
process that determines the total area under the curve of a function ie., the integrator does
integration of the input voltage waveform. Here the input element is resistor and the
feedback element is capacitor as shown in fig.2-1.
Fig.2-1 Basic op-amp integrator The output

voltage is given by
-1 t
V0 = RC ∫0 Vsdt + Vc(t = 0)
Where VC (t=0) is the initial voltage on the capacitor. For proper integration, R C has to be
much greater than the time period of the input signal.
It can be seen that the gain of the integrator decreases with the increasing frequency
so, the integrator circuit does not have any high frequency problem unlike a differentiator
circuit. However, at low frequencies such as at dc, the gain becomes infinite. Hence the op-
amp saturates (ie., the capacitor is fully charged and it behaves like an open circuit). A
practical integrator circuit is shown in Fig. 2-2.
Fig. 2-2 Practical op-amp integrator

2.3.2 Differentiator
An op-amp differentiator simulates mathematical differentiation, which is a process
of determining the instantaneous rate of change of a function. Differentiator performs the
reverse of integration function. The output waveform is derivative of the input waveform.
Here, the input element is a capacitor and the feedback element is a resistor. An ideal
differentiation is shown in fig. 2-3.
Fig.2-3 Basic op-amp

differentiator The output voltage is given by
VO =−RC dVs dt
For proper differentiation, RC has to be much smaller than the time period of the input signal.
It can be seen that at high frequencies a differentiator may become unstable and break into
oscillation. Also, the input impedance of the differentiator decreases with increase in
frequency, thereby making the circuit sensitive to high frequency noise. So, in order to limit
the gain of the differentiator at high frequencies, the input capacitor is connected in series
with a resistance R1 and hence avoiding high frequency noise and stability problems. A
practical differentiator circuit is shown in fig. 2-4.
Fig. 2-4 Practical op-amp differentiator

2.3.3. Design Constraints
Integrator circuit
• The output of the integrator cannot rise indefinitely as the output will be limited.
• The output of the op amp integrator will be limited by supply voltage.
• When designing one of these circuits, it may be necessary to limit the gain or increase
the supply voltage to accommodate the likely output voltage swings.
• While small input voltages and for short times may be acceptable, care must be taken
when designing circuits where the input voltages are maintained over longer periods of
time.
Differentiator circuit
• Output rises with frequency: One of the key facts of having a series capacitor is that it
has an increased frequency response at higher frequencies. The differentiator output
rises linearly with frequency, although at some stage the limitations of the op amp will
mean this does not hold good. Accordingly precautions may need to be made to account
for this. The circuit, for example will be very susceptible to high frequency noise, stray
pick-up, etc.
• Component value limits: It is always best to keep the values of the capacitor and
particularly the resistor within sensible limits. Often values of less than 100kΩ for the
resistor are best. In this way the input impedance of the op amp should have no effect
on the operation of the circuit.\

1. Determine the input and output impedances for each amplifier configuration, (Zin=10M ,
ZO=75 , AOL = 175,000) in fig.(a)
2. Determine the BW of each of the amplifiers in fig(b). The op-amps have an open-loop
gain of 90dB and a unity gain bound width of 2MHz.
)
3. Determine the output voltage of each amplifier in Fig (c).

Fig.(c)
2.5 EXPERIMENT (1) Integrator
1.1 Assemble an integrator circuit with R=1KΩ and C=0.1µf. Connect R f of value 1MΩ across
the capacitor.
1.2 Feed +1V, 500Hz square wave input.
1.3 Observe the input and output voltages on a CRO.
1.4 Determine the gain of the circuit and tabulate the readings in table.
Model waveform is shown.
1.5 Similarly Feed +1V, 1KHz sine wave input.
(2) Differentiator
2.1 Assemble a differentiator circuit with R=1KΩ and C=0.1µf. Connect a resistor R1 of value
470Ω between the source and the capacitor. 2.2 Feed +1V, 500Hz square wave input.
2.3 Observe the input and output voltages on a CRO.
2.4 Determine the gain of the circuit and tabulate the readings in table.
Model waveform is shown.
2.5 Similarly Feed +1V, 1KHz sine wave input.
TABULATION
op-amp Wavefor m Input signal Output signal
configurati on / Amplitud Frequenc Amplitud Frequenc
circuit e y e y
Integrator Square 1V 1KHz 2.5 1KHz

Integrator Sine 1V 1KHz 1.5V 1KHz
Differentiato r Square 1V 1KHz 4.085V 1KHz
Differentiato r Sine 0.9V 1KHz 0.6V 1KHz
a)
(b)
Fig.2.5 Waveform for (a) op-amp integrator, (b) op-amp differentiator
2.6. Simulation (1)

Integrator
Fig. 2.6. (a) Integrator

Fig. 2.6 (b) Input and output curve of integrator
Fig. 2.6. (c) Differentiator

Fig. 2.6 (d) Input and output curve of differentiator
STIMULATION
POSTLAB QUESTIONS
1.Determine the gain-bandwidth product of each amplifier.
2.Determine the input and output

3.What is the normal output voltage in fig. 2-14?
4
2.8. Conclusion: Hence the integrated and differentiator are verified using
LTspice tool and obtained the required.
Name : SHASHIKANT GOSWAMI
Register No. : RA1911004010155
Branch/section : ECE-c
Title : OPERATIONAL AMPLIFIER COMPARATOR
Date of Conduction :
Date of Submission :
Particulars Max. Marks Marks Obtained

Report 10
Viva 10
Total 40
REPORT VERIFICATION
Staff Name:
Signature:
4. OPERATIONAL AMPLIFIER COMPARATOR
4.1 OBJECTIVE:
1. Design the comparator for a frequency of 1 KHz sine wave with 5 Vpp at the non-
inverting input terminal and apply 1V dc voltage as reference voltage at the inverting
terminal of IC741
2. Design a Schmitt Trigger and conduct an experiment to obtain VUTP and V LTP
for various values of R1 and R 2 for the specified design constraint with
upper and lower threshold should be ±1V, for the frequency range of 100 Hz to
10KHz.
4.2 COMPARATOR
4.2.1 Apparatus required:
1 IC 741 Refer data sheet 1
3 Multimeter 1
4 Resistors 10 kΩ 2
4.2.2 Theory:
A Comparator is a non-linear signal processor. It is an open loop mode application of
Op-amp operated in saturation mode. Comparator compares a signal voltage at one input with
a reference voltage at the other input. Here the Op-amp is operated in open loop mode and hence
the output is ±Vsat. It is basically classified as inverting and non-inverting comparator. In a
non-inverting comparator Vin is given to +ve terminal and Vref to –ve terminal. When Vin <
Vref, the output is –Vsat and when Vin > Vref, the output is +Vsat (see expected waveforms).
In an inverting comparator input is given to the inverting terminal and reference voltage is given
to the non inverting terminal. The output of the inverting comparator is the inverse of the output
of non-inverting comparator. The comparator can be used as a zero crossing detector, window
detector, time marker generator and phase meter
4.2.3 Experiment
1. Connect the components/equipment as shown in the circuit diagram.
2. Switch ON the power supply.
3. Apply 1 KHz sine wave with 5 Vpp at the non-inverting input terminal of IC741 using
a function generator.
4. Apply 1V dc voltage as reference voltage at the inverting terminal of IC741.
5. Connect the channel-1 of CRO at the input terminals and channel-2 of CRO at the
output terminals.
6. Observe the input sinusoidal signal at channel-1 and the corresponding output square
wave at channel-2 of CRO. Note down their amplitude and time period.
7. Overlap both the input and output waves and note down voltages at positions on sine
wave where the output changes its state. These voltages denote the Reference voltage.
8. Plot the output square wave corresponding to the sine input with Vref = 1V.
4.2.4 Expected Waveforms: Comparator Input & Output Waveforms
Observations
Theoretical Reference voltage (From the circuit) 1V
Practical Reference voltage (From output waveform) 1V
4.2.5 PSpice Simulation

a) Circuit Diagram And Simulation Output ( for positive reference voltage)
b) Circuit Diagram and Simulation Output ( for negative reference voltage)
4.2.6 Pre Lab Question:

4.2.7 Post Lab Question:
Result: The positive and negative reference voltage is verified using LTspice
4.3 SCHMITT TRIGGER CIRCUITS
4.3.1 Apparatus required:
1 IC 741 Refer data sheet 1
3 Multimeter 1
4 Resistors 10K Ω 2
1
56 K Ω
6` Function Generator (0-2) MHz 1
4.3.2 Theory:
Circuit shows an inverting comparator with positive feedback. This circuit converts an irregular
shaped waveform to square wave or pulse. This circuit is known as Schmitt trigger or
Regenerative comparator or Squaring circuit. The input voltage Vin triggers (changes the state
of ) the output Vo every time it exceeds certain voltage levels called Upper threshold voltage,
VUT and Lower threshold voltage, VLT . The hysteresis width is the difference between these
two threshold voltages i.e. VUT – VLT . These threshold voltages are calculated as follows.
VUT = (R2/R1+R2) Vsat when Vo= Vsat
VLT = (R2/R1+R2) (-Vsat) when Vo= -Vsat
The output of Schmitt trigger is a square wave when the input is sine wave or triangular wave, where
as if the input is a saw tooth wave then the output is a pulse wave.
Schmitt trigger circuit using IC 741
Design Equations:
R
2 ( + )
V = V
UTP
R +R Sat
V = R2 (V − )
LTP R +RSat
V =V -V = R2 −V
− )
(V +
R +R
Hyst UTP LTP 1 2 Sat Sat
1.3.3 Design Constraints

● Minimum Input voltage is 1v and maximum output voltage is 10v.
● Biasing voltage is ±12v
● Frequency range is 100 Hz up to 10kHz
4.3.4 Experiment:
1. Connect the components / equipment as shown in the circuit diagram.
3. Apply 5 Vpp and 1KHz input sine wave using function generator.
4. Connect the channel - 1 of CRO at the input terminals and Channel-2 at the output
terminals.
5. Observe the output square waveform corresponding to input sinusoidal signal.
6. Overlap both the input and output waves and note down voltages at positions on sine
wave where output changes its state. These voltages denote the Upper threshold voltage
and the Lower threshold voltage (see EXPECTED WAVEFORMS below).
7. Verify that these practical threshold voltages are almost same as the theoretical
threshold voltages calculated using formulas given in the THEORY section above.
8. Sketch the waveforms by noting down the amplitude and the time period of the input
Vin and the output Vo.
1.3.4 Model output Schmitt trigger input and output Waveforms:
Observation Table
Theoretical Values Practical Value

Sl R1 R2 R R V V
(V ) (V )
UTP LTP
no. V = 2 + V = 2 −
R +R1 2 Sat
UTP LTPR +R1 2 Sat
[10k/(10k+56k)]*15 [10k/(10k+56k)]*-15
1 56k 10k
= 2.2727 = -2.2727 2.27 -2.27
1.3.5 LTspice Simulation

a) Circuit diagram and Simulation Output
4.3.6 Pre Lab Question:

4.3.7 Post Lab Question:
Result: The Schmitt trigger is verified using LTspice.
Department of Electronics and Communication Engineering

Branch/section : ECE-C
Title : SINE WAVE GENERATOR USING OPERATIONAL AMPLIFIER
Date of Conduction : 01/03/21
Date of Submission : 08/03/21

Report 10
Viva 10
Total 40
REPORT VERIFICATION
Signature :
5. WAVE SHAPING CIRCUIT USING OPERATIONAL
AMPLIFIER - CLIPPER AND CLAMPER
OBJECTIVE
a. To study the operation ofwave shaping circuits (clipper and clamper) using op-amps, such as
half wave rectifier and full wave rectifier
HARDWARE REQUIRED
1 r 741 Refer data sheet in
appendix
2 Cathode Ray Oscilloscope (0 - 20MHz) 1
3 Resistors 2.2 K Q, 4.7K, 3

IOKPOT
4 Semiconductor(Diode) IN4002 2
5 Dual Regulated power supply (0 -30V), IA
6 Function Generator (0-2) MHz
7 ASLKPRO Kit Refer data sheet in 1

appendix
THEORY
ACTIVE CLIPPER
Clipper is a circuit that is used to clip off (remove) a certain portion of the input signal
to obtain a desired output wave shape. In op-amp clipper circuits, a rectified diode ma be used
to clip off certain parts of the input signal. Fig. 2-2-4 (a) shows an active positive clipper, a
circuit that removes positive parts of the input signal. The clipping level is determined by the
reference voltage
Vin
Fig 3(a) Active clipper
(b) (c)
Fig 4 (b) input & output wavefonns mth + Vr.f, (c) mput & output waveforms with -Vref
With the wiper all the way to the left, Vref is o and the non-inverting input is grounded. When
Vin goes positive, the error voltage drives the op-amp output negative and turns on the diode.
This means the final output Vo is 0 (same as Vref) for any positive value of Vin.
When Vin goes negative, the op-amp output is positive, which turns off the diode and
opens the loop. When this happens, the final output Vo is free to follow the negative half cycle
of the input voltage. This is why the negative half cycle appears at the output. To change the
clipping level, all we do is adjust Vref as needed.
Active clamper
In clamper circuits, a predetermined dc level is added to the input voltage. In other
words, the output is clamped to a desired dc level. If the clamped dc level is positive, the
clamper is called a positive clamper. On the other hand, if the clamped dc level is negative, it
is called a negative clamper. The other equivalent terms for clamper are dc inserter or dc
restorer.
A clamper circuit with a variable dc level is shown in fig (a). Here the input wave form
is clamped at +Vref and hence the circuit is called a positive clamper.
luF
_i_VCC
R=4.7k, Rp=10k
Fig S (a) Peak clamper circuit
The output voltage of the clamper is a net result of ac and dc input voltages applied to the
inverting and non-inverting input terminals respectively. Therefore, to understand the circuit
operation, each input must be considered separately. First, consider Vref at the non-inverting
input. Since this voltage is positive, is +Vo is positive, which forward biases diode DI. This
closes the feedback loop and the op-amp operates as a voltage follower. This is possible
because Cl is an open circuit for dc voltage. Therefore Vo = Vref. As for as voltage Vin at the
inverting input is concerned during its negative half-cycle DI conducts, charging Cl to the
negative peak value of the Vp. However, during the positive half-cycle of Vin diode DI is
reverse biased and hence the voltage Vp across the capacitor acquired during the negative half-
cycle is retained. Since this voltage Vp is in series with the positive peak voltage Vp, the output
peak voltage Vo—2Vp. Thus the net output is Vref +Vp, so the negative peak of 2Vp is at
Vref. For precision clamping where Rd is the forward resistance of the diode DI
(IOOQ typically) and T is the time period Of Vin. The input and output wave forms are shown
in figure.
a Ut(R1_) u u'(RL)
(i) (ii)
UI(RL (iii)
)
Fig 6(b) Input and output waveforms (i) with Vref=OV, (ii) with +Vref; (iii) with -Vref
Resistor R is used to protect the op-amp against excessive discharge currents from capacitor Cl
especially when the dc supply voltages are switched off. Negative clamping at a negative voltage
is accomplished by reversing diode DI and using the negative reference voltage —Vref.
Experiment
l. Connect the components/equipment R=2.2KQ use N4002 diode. Sinusoidal input amplitude 3v
and frequency I Khz.as shown in the circuit diagram.
3. Apply I V dc voltage as reference voltage at the inverting terminal ofIC741.
4. Connect the channel-I of CRO at the input terminals and channel-2 of CRO at the output
terminals.
5. Observe the input sinusoidal signal at channel-I and the corresponding output square wave
at channel-2 of CRO. Note down their amplitude and time period.
6. Overlap both the input and output waves and note down voltages at positions on sine wave
where the output changes its state. These voltages denote the Reference voltage.
7. Plot the output wave form.
Active clamper
1. Connect the components/equipment clamping level at zero as shown in fig.5 (a). Note that
Vref- W. Consider - 0.1gF, R = 4.7 and = 10 . Use IN4002
diode. Feed 5Vpp, 10 KHz sinusoidal inputs.

3. Apply IV dc voltage as reference voltage at the inverting terminal of IC741.
4. Connect the channel-I of CRO at the input terminals and channel-2 of CRO at the output
terminals.
5. Observe the input sinusoidal signal at channel-I and the cotTesponding output square wave
at channel-2 of CRO. Note down their amplitude and time period.
6. Overlap both the input and output waves and note down voltages at positions on sine wave
where the output changes its state. These voltages denote the Reference voltage.
7. Plot the output wave form.
Observation Clipper
Clipping level= 3.5V

Amplitude Time Period Frequency
10 I ms 50
Input Voltage
6.5 I ms 50
Output Voltage
Observation Clamper
Clamping level= 2.5V

Amplitude Time Period Frequency
10 I ms 50
Input Voltage
22.5 I ms 50
Output Voltage
PITIab
1. Find the output waveform for when Vu < Vref
2. Determine the output waveform for a clamper with input =4Vpsinewave and Vrer=IV.
Postlab
l. If the diode is reversed in fig. 3 (a), what would the output be like?
2. If the diode is reversed in fig. 5(a), what would be the output?
Result: The operation of wave shaping circuits (clipper and clamper) using op-amps is
successfully carried out using LTSpice.

Title : SINE WAVE GENERATOR USING OPERATIONAL AMPLIFIER

Report 10
Viva 10
Total 40
REPORT VERIFICATION
Staff Name : KALIMUTHU K
Signature :
6. SINE WAVE GENERATOR USING OPERATIONAL
AMPLIFIER
6.1 OBJECTIVE
Design a sine wave oscillator using operational amplifier
1. RC phase shift oscillator
2. Wein bridge oscillator

appendix
3 Resistors 330 Ω 1
1.5K Ω 15K 4
Ω 1
1
1M Ω
1
4.7K Ω
1
18K Ω
2
10K Ω
1
15K Ω 1
18K Ω
.001µf 2
5 Regulated power supply 15 V 1
6.3.1 RC phase shift oscillator
The feedback network consists of three identical RC sections. Each section produces a
phase shift of 60o Therefore, the net phase shift of the feedback is 180 o The amplifier stage
introduces a phase shift of 180 o Therefore, the total phase shift between the input and output is
o
360 or 0 o. When the circuit is energized, by switching on the supply, the circuit starts
oscillating. The oscillations will be maintained if the loop gain is at least equal to unity.
Feedback fraction of the RC phase shift network
=1/29
The frequency of oscillation f0=1/2
πRC 6.
Circuit diagram
C=0.001µF, R=10K , R1=10K , RF=560K pot Design:
f0=1/2 πRC 6
Rf ≥ 29R1
β = 10K/ Rf
β = 1/29 Rf
= 290K f0=
6.5kHz LT
Spice
simulation
:
(a) Circuit Diagram
(b) Output waveform
6.3.2 Wein Bridge Oscillator

It is commonly used in audio frequency oscillator. The feedback signal is connected in the
input terminal so that the output amplifier is working as a non-inverting amplifier. The Wien
bridge circuit is connected between amplifier input terminal and output terminal. The bridge
has a series R network, in one arm and a parallel RC network in the adjoining arm. In the
remaining two arms of the bridge, resistor R1 and Rf are connected. the phase angle criterion
for oscillation is that the total phase shift around the circuit must be zero. This condition occurs
when bridge is balanced. At resonance frequency of oscillation is exactly the resonance
frequency of balanced Wien bridge and is given by f0 = 1/ (2πfC).assuming that the resistors
are input impedance value and capacitance are equal to the value in the reactive stage of Wien
bridge. At this frequency, the gain required for sustained.
Design
R1C1 --- Lag
R2C2 --- Lead
R1 = R2 = R
C1 = C2 = C
Vo/Vin = 1/3, Gain = 1+ (R4/R3)
Rf = 2R3
R = 10.2k, C = 3nF
Design Constraints
● The loading effect of the amplifier on the feedback network has an effect on the
frequency of oscillations and can cause the oscillator frequency to be up to 25% higher
than calculated. Then the feedback network should be driven from a high impedance
output source and fed into a low impedance load such as a common emitter transistor
amplifier but better still is to use an Operational Amplifier as it satisfies these conditions
perfectly.
● The voltage gain of the Wein bridge oscillator circuit must be equal to or greater than
three “Gain = 3″ for oscillations to start.
● Due to the open-loop gain limitations of operational amplifiers, frequencies above 1MHz
are unachievable without the use of special high frequency op-amps.
● D1 and D2 for automatic gain control.
LT Spice simulation:
(a) Circuit Diagram
(b) Output waveform
6.3 PRE-LAB
Give the condition which determines the frequency of oscillation
3. Give the formula to calculate frequency of oscillation for RC and Wein bridge oscillator.
4. Where do you use IC oscillators?
6.4 POST-LAB
1. What are the merits and Demerits of RC phase shift oscillator?
2. Why do we need three RC networks for a phase shift oscillator?
3. Explain the main difference between an amplifier and an oscillator.
PRE- LAB ANSWERS
POST LAB ANSWERS
RESULT:
The sine wave oscillator using operational amplifier is designed and verified using LTSpice.
Name : SHASHIKANT
Day / Session : 2020-2021
Venue :
Title of Experiment : Square Wave Generator using Operational Amplifier.
Date of Conduction : 04-02-21
Date of Submission : 09-02-21

Marks
Particulars Max. Marks Obtained
Report 10
Viva 10
Total 40
REPORT VERIFICATION
Signature :
7. SQUARE WAVE GENERATOR
USING OPERATIONAL AMPLIFIER
7.1 OBJECTIVE
Design a square wave generator using operational amplifier.

appendix
3 Resistors 10k 2
8.2k 1
5 Capacitors 1
0.1µf
7.3 SQUARE WAVE GENERATOR

The square wave generator circuit is forced to operate in the saturated region.
That is, the o/p of the Op-Amp is forced to swing between positive saturation (+Vsat)
and negative saturation (-Vsat), resulting in the square wave output. This square wave
generator is also called free running or astable multivibrator.
R2/[R1+R2]Vout = βVout
Rf=10k R1=10k R2=8.2k C=0.1µf
A fraction of the output (βV◦) is feedback to the input non-inverting terminal.

Thus the Vref is βV◦ and may take values as + βVsat or – βVsat. The output is also
feedback to the negative i/p terminal after integrating by means of a low pass RC
combination. Whenever the i/p at the negative terminal exceeds V ref switching takes
place resulting in a square wave output. Time period of square wave is given as
for
R1 = 1.16 R2, it can be seen that T = 2RC.
T = 1.6 ms
V◦ = 24 V
Vsat = 12V; βVsat = 4v
Theoretical O/P Practical O/P

TOTAL TIME 10ms TOTAL TIME 10ms
TON 1ms TON 1ms
TOFF 1ms TOFF 1ms
AMPLITUDE of Close to VCC AMPLITUDE of 13.13044
Square . Square .
Charg& Discharging βVsat = 4V Charg& Discharging βVsat= =
13.13044*0.333=4.372V
Of Capcitor by Of Capcitor by
measuring Amplitude measuring Amplitude
7.4 PROCEDURE:
1. Connect the circuit as shown in the figure with the designed values.
2. Switch on the power supply and observe the waveform.
3. Note down the amplitude and time period.
4. Plot the waveforms on a graph sheet.
7.5 LTspice Simulation a. Circuit Diagram
Fig.6. Schematic diagram of Second order High pass filter

7.6 PRE-LAB
1. Where do you use IC oscillators?
2. Explain the operation of square wave generator with respect to voltage across capacitor
and output waveform.
7.7 POST-LAB
1. Explain the main difference between an amplifier and an oscillator.
2. if R2=10kΩ, R1=11.kΩ, Rf=100kΩ, C=0.01μf.
RESULT: : The circuit of square wave generator is constructed and the output
waveform is verified via LTspice.

Laboratory Report Cover
Sheet
Title : SQUARE WAVE GENERATOR USING OPERATIONAL AMPLIFIER
Particular Max. Marks Obtained

s Marks
Report 10
Viva 10
Total 40
REPORT VERIFICATION
Signature :
8. DESIGN OF MONOSTABLE AND ASTABLE MULTIVIBRATOR
USING IC555
8.1 OBJECTIVE
1. Design a Monostable multivibrator for an ON- time of ki, with capacitor value of 1 µF.
Conduct the experiment and plot appropriate graphs
2. Design an Astable multivibrator for a frequency of 1KHz with 60% duty cylcle using
555 timer

1 IC 555 Timer Refer data sheet in 1
appendix
330 Ω 1
15K Ω 1
3 Resistors 10 M Ω 1
6.8 K Ω 1
1K Ω 1
1µf 2
5 Regulated power supply (1 -5V), 1A 1
8.3 THEORY
The 555 Timer is a monolithic timing circuit that can produce accurate and highly stable
time delays or oscillations. The timer basically operates in one of the two modes—
monostable(one-shot) multivibrator or as an as table(free-running) multivibrator. In the
monostable mode, it can produce accurate time delays from microseconds to hours. In the
astable mode, it can produce rectangular waves with a variable duty cycle. Frequently, the 555
is used in astable mode to generate a continuous series of pulses, but you can also use the 555
to make a one-shot or monostable circuit.
Functional block diagram of IC 555
In astable or free running mode, the 555 can operate as an oscillator. The uses include LED and
lamp flashers, logic clocks, security alarms, pulse generation, tone generation, pulse position
modulation, etc. In the bistable mode, the 555 can operate as a flip-flop and is used to make
bounce-free latched switches, etc.
Pin diagram of IC55

8.3.1 MONOSTABLE MULTIVIBRATOR
The circuit has an external resistor and capacitor. The voltage across the capacitor is
used for the threshold to pin 6. When the trigger arrives at pin 2, the circuit produces output
pulse at pin 3. Initially, if the output of the timer is low, that is, the circuit is in a stable state,
transistor Q1 is on and the external capacitor C is shorted to ground. Upon application of a
negative trigger pulse to pin 2, transistor Q1 is turned off, which releases the short circuit across
the capacitor and as a result, the output becomes high. The capacitor now starts charging up
towards vcc through RA. When the voltage across the capacitor equals 2/3vcc the output of
comparator 1 switches from low to high, which in turn makes the output low via the output of
the flip-flop. Also, the output of the flip-flop turns transistor Q1 on and hence the capacitor
rapidly discharges through the transistor. The output of the monostable multivibrator remains
low until a trigger pulse is again applied. The cycle then repeats. Below figure shows the trigger
input, output voltage, and capacitor voltage waveforms. As shown, the pulse width of the trigger
input must be smaller than the expected pulse width of the output waveform. Moreover, the
trigger pulse must be a negative-going input signal with an amplitude larger than 1/3 vcc. The
time for which the output remains high is given by time period = 1.1RAC
Where RA is in ohms, C in farads and time period in seconds. Once the circuit is triggered, the
output will remain high for the time interval time period. It will not change even if an input
trigger is applied during this time interval. In other words, the circuit is said to be non-
retriggerable. However, the timing can be interrupted by the application of a negative signal at
the reset input on pin 4. A voltage level going from +vcc to ground at the reset input will cause
the timer to immediately switch back to its stable state with the output low.
The trigger input may be driven by the output of astable multivibrator with high duty
cycle. If the desired pulse width is of the order of seconds, the output can be seen using a
LED and the resistance value used will be of the order of MΩ. In this case the trigger can be
supplied manually by grounding the trigger input for a fraction of a second.
Input and output waveform
Design
Time period of
pulse=T=1.1RC=11s
Let C=100f T=1.1RC
11s=1.1*R*1uf
R=10M
8.3.2 ASTABLE MULTIVIBRATOR
An astable multivibrator is a wave-generating circuit in which neither of the output
levels is stable. The output keeps on switching between the two unstable states and is a periodic,
rectangular waveform. The circuit is therefore known as an ‘astable multivibrator’. Also, no
external trigger is required to change the state of the output, hence it is also called
‘free-running multivibrator’. The time for which the output remains in one particular state is
determined by the two resistors and a capacitor externally connected to the 555 timer.
If the output is high initially, capacitor C starts charging towards vcc through RA and
RB. As soon as the voltage across the capacitor becomes equal to 2/3 vcc, the upper comparator
triggers the flip-flop, and the output becomes low. The capacitor now starts discharging through
RB and transistor Q1. When the voltage across the capacitor becomes 1/3vcc, the output of the
lower comparator triggers the flip-flop, and the output becomes high.
The cycle then repeats.
The output voltage and capacitor voltage waveforms are shown in Figure below.
Output voltage waveform the time during which the capacitor charges from 1/3vcc to 2/3
vcc is equal to the time the output is high and is given by
ton =0.69(RA + RB)C
the time during which the capacitor discharges from 2/3vcc to 1/3vcc is equal to the time the
output is low and is given by
toff =0.69RBC
the total period of the output wave form is
T=ton+toff=0.69(RA+2RB)C
Thus the frequency of oscillation is
fo=1/T=(1.45/(RA+2RB)C)
Design Constraints
● The 555 Timer is a very versatile low cost timing IC that can produce a very accurate
timing periods with good stability of around 1%
● Duty cycle should be greater than 50% to 80%
● Single RC network connected to a single positive supply of between 4.5 and 16 volts.
● Load resistance minimum value is 1KΩ
Theoretical O/P Practical O/P
TOTAL TIME 5s TOTAL TIME 5s
TON 0.339s TON 0.33s
TOFF 0.229s TOFF 0.23s
AMPLITUDE of AMPLITUDE of
5V
Square . Square . 4.9973V
Charge & Discharging 2/3 VCC – 1/3 VCC Charge & Discharging
Of Capacitor by 3.3 – 1.6 = 1.7 v Of Capacitor by 3.32-1.68=1.64V

measuring Amplitude measuring Amplitude
8.4
PRE-LAB
8.5
8.6
LTSPICE STIMULATION
(a) MONOSTABLE MULTIVIBRATOR

8.7
8.8
(b) ASTABLE MULTIVIBRATOR
8.7 RESULT:
Designing and implementation of monostable and astable multivibration using IC555 is successfully
carried out in LTSpice.
Name : SHASHIKANT
Day / Session : 2020-2021
Venue :
Title of Experiment : Design of Low Pass and High Pass Filter
Marks
Report 10
Viva 10
Total 40
REPORT VERIFICATION
Signature :
9. DESIGN OF LOWPASS AND HIGHPASS FILTER
9.1 OBJECTIVE
To design a low pass, high pass filter and plot the frequency response.

appendix
2 Resistor 3.3kΩ 2
5.8kΩ 1
10kΩ 1
3 Capacitor 0.047uf 2
6 Dual power supply 15v 1
9.2 THEORY
A filter is a circuit that lets certain frequencies pass and blocks other frequencies. This selective
nature can be done two ways, either with passive filters or with active filters. Passive filters
completely comprised of passive elements; namely resistors, capacitors and/or inductors.
Active filters use active devices, i.e. an op-amp, to filter out unwanted signals.
Active filters have the following advantages over passive filters.

• Gain and frequency adjustment and tuning.
• No inductors (reduces cost and size).
• No loading effects.
Some disadvantages of active filters.

• Bandwidth limitations
• Fabrication tolerances
• Can only respond to a specific range of signal magnitudes.
Figure 1 shows the performance of an ideal low-pass, band-pass, and high pass circuit. Active
filters can be classified as; low-pass, high-pass, band-pass, notch, or all pass circuit. These
circuits are all used for different purposes, but this lab will focus on the design of second order
low pass and high pass Filters using PSPICE.
Fig 1.Graph of practical (a) low pass and (b) high pass filter (c) Band Pass filter (d)
Band Stop filter
SECOND ORDER LOW PASS FILTER
Fig.2.Second-Order Low-Pass Filter
Design:
Given fc=2khz,
Choose C1=C2=0.047uf fc=1/2πRC R1=R2=3.3kΩ Rx=5.8kΩ, Ry=10kΩ α=3-A
Α=1.414 A=1.586 A=1+Rf/R1
SECOND ORDER HIGH PASS FILTER
Fig.3.Second-Order High-Pass Filter
9.3 PRE-LAB
1. Compute the transfer function of the amplifier in Figure assuming an ideal op-amp. Use
the PSPICE model of an op-amp and verify your results in PSPICE using the following
values: Vcc=+12V, Vee=-12V, R1=1kΩ, and VS being a sin wave with a frequency of
10 kHz and amplitude of 1mV.
9.4 EXPERIMENT
9.4.1 Low pass filter

Design a Second order low pass filter as shown in figure 2 for the values R1 =R4 =1.59 K
R2=100K Ω, R3= 200KΩ C1=C2=0.1uF, Rx=5.8KΩ, Ry-10KΩ and sinusoidal input of
amplitude 1V and frequency 10KHz.
9.4.2 High pass filter

Design a Second order High pass filter as shown in figure 3 for the values R1 = R2=3.3KΩ,
C2=C4=0.047uF, Rx=5.8KΩ, Ry=10KΩ and sinusoidal input of amplitude 1V and frequency
10KHz.
9.5 SIMULATION AND RESULT

Fig,4. Schematic diagram of Second order Low pass filter
Fig.5.Schematic diagram of Second order High pass filter

9.6 POST LAB QUESTION
1. Derive the transfer function of the circuit in Figure. By observing the transfer function,
what is the purpose of this topology? Verify your results in PSPICE with an “AC”
simulation using R1=500 Ω, R2=2.5kΩ, a source with a 0.5V magnitude, and C=0.01 F.
Do the PSPICE results agree with what you derived?
9.6 RESULT: The design of low pass and high pass filter is verified by using LTSPICE.
Laboratory Report Cover
Sheet
Title : DESIGN OF BAND PASS AND BAND STOP FILTER
Particular Max. Marks Obtained

s Marks
Report 10
Viva 10
Total 40
REPORT VERIFICATION
Signature :
10. DESIGN OF BAND PASS FILTER AND BAND REJECT FILTER.
10.1 OBJECTIVE
To design a low pass, high pass, Band pass and Band stop filter and plot the frequency response.
S.No Equipment/Component name Specifications/ Value Quantity

appendix
2 Resistor 100KΩ,7.95KΩ 2
3 Capacitor 0.01uf 2
10.2 THEORY BAND PASS FILTER

The bandpass filter passes one set of frequencies while rejecting all others. The band-stop filter
does just the opposite. It rejects a band of frequencies, while passing all others. This is also called
a band-reject or band-elimination filter. Like bandpass filters, band-stop filters may also be
classified as (i) wide-band and (ii) narrow band reject filters.
The narrow band reject filter is also called a notch filter. Because of its higher Q, which
exceeds 10, the bandwidth of the narrow band reject filter is much smaller than that of a wide
band reject filter.
This cascading together of the individual low and high pass passive filters produces a low
“Q-factor” type filter circuit which has a wide pass band. The first stage of the filter will be the
high pass stage that uses the capacitor to block any DC biasing from the source. This design has
the advantage of producing a relatively flat asymmetrical pass band frequency response with one
half representing the low pass response and the other half representing high pass response as
shown.
The higher corner point ( ƒH ) as well as the lower corner frequency cut-off point ( ƒL ) are
calculated the same as before in the standard first-order low and high pass filter circuits.
Obviously, a reasonable separation is required between the two cut-off points to prevent any
interaction between the low pass and high pass stages. The amplifier also provides isolation
between the two stages and defines the overall voltage gain of the circuit.
The bandwidth of the filter is therefore the difference between these upper and lower -
3dB points. For example, if the -3dB cut-off points are at 200Hz and 600Hz then the bandwidth
of the filter would be given as: Bandwidth (BW) = 600 – 200 = 400Hz. The normalized frequency
response and phase shift for an active band pass filter will be as follows.
While the above passive tuned filter circuit will work as a band pass filter, the pass band
(bandwidth) can be quite wide and this may be a problem if we want to isolate a small band of
frequencies. Active band pass filter can also be made using inverting operational amplifier. So by
rearranging the positions of the resistors and capacitors within the filter we can produce a much
better filter circuit as shown below. For an active band pass filter, the lower cut-off -3dB point is
given by ƒC2 while the upper cut-off -3dB point is given by ƒC1.
BAND-STOP (OR REJECT) FILTER.

A wide band-stop filter using a low-pass filter, a high-pass filter and a summing amplifier
is shown in figure. For a proper band reject response, the low cut-off frequency fL of high-pass
filter must be larger than the high cutoff frequency f H of the low-pass filter. In addition, the pass
band gain of both the high-pass and low-pass sections must be equal.
This is also called a notch filter. It is commonly used for attenuation of a single frequency such
as 60 Hz power line frequency hum. The most widely used notch filter is the twin-T network
illustrated in fig. (a). This is a passive filter composed of two T-shaped networks. One T-network
is made up of two resistors and a capacitor, while the other is made of two capacitors and a
resistor. One drawback of above notch filter (passive twin-T network) is that it has relatively low
figure of merit Q. However, Q of the network can be increased significantly if it is used with the
voltage follower. Here the output of the voltage follower is supplied back to the junction of R/2
and 2 C.
Design: f1=1Khz
f’=10Khz
R1=10K c1=c2=0.04uf fc=1/2πRC
A=1+Rf/R1
Band Pass Filter
LT Spice Simulation for Band Pass Filter
Steps to run the simulation:
Right: Input signal as sine wave, DC offset – 0, AC amplitude – 1. Left: Run - AC Analysis
Band Stop Filter

10.3.1 Band Pass Filter
Design a Band Pass Filter as shown in figure 4 keep the same values of low pass and high pass
filter values and sinusoidal input of amplitude 1V and frequency 10KHz.
10.3.2 Band Stop Filter

Design a Band Stop filter as shown in figure 5 for the corresponding values as in figure and
sinusoidal input of amplitude 1V and frequency 10KHz
10.4 TEST PROCEDURE
1. Open the LT spice AD Lite software by double clicking its icon.
2. After few moments Command window will appear.
2. Go to the File Menu and select a New text file. (File New text file)
3. A blank text file will appear with a title ‘untitled’
4. Now start typing your program. After completing, save the text file as .cir with appropriate
name. To execute the program, go to Debug Menu and select Run.
5. After execution output will appear in the Command window. If there is an error then with
an alarm, type of error will appear.
6. If the results contain errors, start up the text editing program again and modify the net list.
7. Rectify the error if any and go to Debug Menu and select Run.
8. If there is no errors go to Trace menu and click add trace. Enter the output node voltage
and click ok then the output will display.
10.5 PRELAB
1. Design a band pass filter for f0=2khz Q=20 and A0=10. Choose C=1µf.
2. An ideal LPF having fh=5khz is cascaded with HPF having fl=4.8khz. Sketch the
frequency response of the cascaded filter.
10.6 POST LAB
1. Design a notch filter for f0=8khz and Q=10. Choose C=500pF

RESULT- The circuits were designed and required output is obtained.
Conclusion: The band pass and band reject filter circuits are stimulated using LTspice and
output waveforms are verified.
Department of Electronics and
Communication Engineering

Day / Session :
Venue :
Title of Experiment : SERIES VOLTAGE REGULATOR
Date of conduction :
Marks
Particulars Max. Marks
Obtained
Report 10
Viva 10
Total 40
REPORT VERIFICATION Staff
Name : KALIMUTHU Signature :
11. SERIES VOLTAGE REGULATOR

11.1 OBJECTIVES
Design a voltage regulator using op amp IC741.
S.No Equipment/Component name Specifications/ Quantity

Value

appendix
2 Resistors 24K Ω 2
100 Ω 1
12K Ω 1
3 Transistor Q2N2222 1
4 Diode DIN746 1
6 Multimeter 1
11.3 THEORY
A voltage regulator is a voltage stabilizer that is designed to automatically stabilize a
constant voltage level. A voltage regulator circuit is also used to change or stabilize the voltage
level according to the necessity of the circuit. Thus, a voltage regulator is used for two reasons:
1. To regulate or vary the output voltage of the circuit.
2. To keep the output voltage constant at the desired value in-spite of variations in the
supply voltage or in the load current.
All electronic voltage regulators will have a stable voltage reference source which is
provided by the reverse breakdown voltage operating diode called zener diode. The main
reason to use a voltage regulator is to maintain a constant dc output voltage. It also blocks
the ac ripple voltage that cannot be blocked by the filter. A good voltage regulator may also
include additional circuits for protection like short circuits, current limiting circuit, thermal
shutdown, and over voltage protection. Electronic voltage regulators are designed by any of
the three or a combination of any of the three regulators given below.
A zener controlled voltage regulator is used when the efficiency of a regulated power
supply becomes very low due to high current. There are two kinds of zener controlled
transistor voltage regulators. Zener Controlled Transistor Series Voltage Regulator is a circuit
is also named an emitter follower voltage regulator. It is called so because the transistor
used is connected in an emitter follower configuration. The circuit consists of an N-P-N
transistor and a zener diode. As shown in the figure below, the collector and emitter
terminals of the transistor are in series with the load. Thus this regulator has the name series
in. The output of the rectifier that is filtered is then given to the input terminals and
regulated output voltage Vload is obtained across the load resistor Rload. The reference
voltage is provided by the zener diode and the transistor acts as a variable resistor, whose
resistance varies with the operating conditions of base current, Ibase. The main principle
behind the working of such a regulator is that a large proportion of the change in supply or
input voltage appears across the transistor and thus the output voltage tends to remain
constant.
The output voltage can thus be written as Vout = Vzener –
Vbe
The transistor base voltage Vbase and the zener diode voltage Vzener are equal and thus the
value of Vbase remains almost constant.
Operation
When the input supply voltage Vin increases the output voltage Vload also increases. This
increase in Vload will cause a reduced voltage of the transistor base emitter voltage Vbe as
the zener voltage Vzener is constant. This reduction in Vbe causes a decrease in the level of
conduction which will further increase the collector-emitter resistance of the transistor and
thus causing an increase in the transistor collectoremitter voltage and all of this causes the
output voltage Vout to reduce. Thus, the output voltage remains constant. The operation is
similar when the input supply voltage decreases. The next condition would be the effect of
the output load change in regard to the output voltage. Let us consider a case where the
current is increased by the decrease in load resistance Rload. This causes a decrease in the
value of output voltage and thus causes the transistor base emitter voltage to increase. This
causes the collector emitter resistance value to decrease due to an increase in the conduction
level of the transistor. This causes the input current to increase slightly and thus compensates
for the decrease in the load resistance Rload. The biggest advantage of this circuit is that the
changes in the zener current are reduced by a factor β and thus the zener effect is greatly
reduced and a much more stabilized output is obtained. The output voltage of the series
regulator is Vout = Vzener – Vbe. The load current Iload of the circuit will be the maximum
emitter current that the transistor can pass. For a normal transistor like the 2N3055, the load
current can go upto 15A. If the load current is zero or has no value, then the current drawn
from the supply can be written as Izener + Ic(min). Such an emitter follower voltage regulator
is more efficient than a normal zener regulator. A normal zener regulator that has only a
resistor and a zener diode has to supply the base current of the transistor.
Limitations
The limitations listed below has proved the use of this series voltage regulator only suitable
for low output voltages.
1. With the increase in room temperature, the values of Vbe and Vzener tend to decrease.
Thus the output voltage cannot be maintained a constant. This will further increase the
transistor base emitter voltage and thus the load.
2. There is no option to change the output voltage in the circuit.
3. Due to the small amplification process provided by only one transistor, the circuit cannot
provide good regulation at high currents.
4. When compared to other regulators, this regulator has poor regulation and ripple
suppression with respect to input variations.
5. The power dissipation of a pass transistor is large because it is equal to Vcc Ic and almost
all variation appears at Vce and the load current is approximately equal to collector
current. Thus for heavy load currents pass transistor has to dissipate a lot of power and,
therefore, becoming hot.
Fig 1
RZ=1k RL =100 RF1=12K RF2=24kK
EXPERIMENT
1. Setup the circuit as shown in Figure-1.
2. For Line Regulation, set RL at 100 Ω. Vary the input voltage (V1) from 5v to25v. For each
setting, find the output enter in the table.
Plot the graph of Vo vs Vi.
3. For Load Regulation, set V1 at 10 v. Vary the load resistance RL from 100Ω to 1000Ω. For
each setting, find the output enter in the table. Plot the graph of Vo vs RL.
SERIES VOLTAGE REGULATOR
.
Experimental data and observations
TABLES
Load Regulation VIN= 10 Volt
S.NO. RL(Ω) VOUT(V)
1 10 6.9409642
2 30 6.9409647
3 50 6.9409661
4 100 6.9409661
5 200 6.9409661
6 400 6.9409661
7 600 6.9409661
8 800 6.9409661
9 1000 6.9409661
10 1500 6.9409661
Line Regulation RL= 100 Ω
S.NO. VIN(V) VOUT(V)
1 1 0.99862206
2 2 1.9900266
3 5 4.9658208
4 8 6.8954511
5 10 6.9409647
6 15 6.9971819
7 18 7.0177002
8 20 7.0288382
9 23 7.0430374
10 25 7.05127
PRE LAB QUESTIONS

1. A voltage regulator with a no-load output dc voltage of 12v is connected to a load with a
resistance of 10Ω. If the load resistance decreases to 7.5Ω, the load voltage will decrease
to 10.9v. Calculate load current and the percent load regulation.
2. The ________ regulator is less efficient than the ________ type, but offers inherent
short-circuit protection.
POST LAB QUESTIONS
1. Calculate the voltage regulation of a power supply having VNL = 50 V and VFL = 48 V.
2. What is the purpose of an additional RC filter section in a power supply circuit?
Result: The given circuit is stimulated and obtained the required.
Conclusion: The circuit of series voltage regulator is stimulated LTSpice software and the
output waveforms and required values are verified for both Line and Load Regulators.
Department of Electronics and Communication
Engineering
18ECC202J LINEAR INTEGRATED
CIRCUITS

Day / Session : 2/4
Venue : Google classroom
Title of Experiment : R-2R LADDER DAC
Marks
Report 10
Viva 10
Total 40
REPORT VERIFICATION
Staff Name : KALIMUTHU K
Signature :
12.R-2R LADDER DAC
12.1 OBJECTIVES
1. Design a D to A Convertor with a resolution of 0.3125V using R-2R network.
Assume the logic 1 to be 5V and logic 0 to be 0V.
2. Design a D to A Convertor with a resolution of 0.3125V using binary weighted
resistors. Assume the logic 1 to be 5V and logic 0 to be 0V.

appendix
3 Resistors 4K Ω 1
2K Ω 7
1K Ω 4
6 Multimeter 1
12.3 THEORY
In electronics, a digital-to- analog converter (DAC or D-to-A) is a device for converting a
digital (usually binary) code to an analog signal (current, voltage or electric charge). Digitalto-
analog converters are the interface between the abstract digital world and the analog real life.
An analog-to-digital converter (abbreviated ADC, A/D or A to D) is an electronic circuit that
converts continuous signals to discrete digital numbers. Most of the real world physical
quantities such as voltage, current, temperature, pressure and time are available in analog form.
Even though an analog signal represent a real physical parameter with accuracy, it is difficult
to process, store or transmit the analog signal without introducing considerable error because
of the superimposition of noise as in the case of amplitude modulation. Therefore, for
processing, transmission and storage purposes, it is often convenient to express these variable
in digital form. It gives better accuracy and reduces noise.
D/A conversion is an important interface process for converting digital signals to analog
(linear) signals. An example is a voice signal that is digitized for storage processing, or
transmission and must be changed back into an approximation of the original audio signal in
order to drive a speaker.
Figure-1: A basic DAC

D/A Conversion fundamentals
The DAC fundamentally converts finite-precision numbers (usually fixed-point binary
numbers) into a physical quantity, usually an electrical voltage. Normally the output voltage is
a linear function of the input number.
Figure-2: Block Schematic of a basic DAC
Figure-2 shows the basic configuration for digital-to-analog (D/A) conversion. The
input is an n-bit binary word D and is combined with a reference voltage VR to give an analog
output signal. The output of a DAC can be either a voltage or current. For a voltage output
DAC, the D/A converter is mathematically described as
Vo = K VFS (d12-1+ d22-2+….+dn2-n)
Where, Vo =output voltage
VFS= full scale output voltage
K=scaling factor usually adjusted to unity
d1 d2... dn=n-bit binary fractional word with the decimal point located at the
left d1 = most significant bit (MSB) with a weight of VFS / 2
dn=least significant bit (ISB) with a weight of VFs / 2n
Since the input to the D/A converter has a finite number of digital combinations, the resulting
analog output also has a limited number of possible values (unlike pure analog signals, which
may have an infinite number of values). The greater the number of possible values, the closer
the analog output will be to the ideal value. The number of possible levels is determined by the
number of lines or bits in the digital number. More specifically, the number of states is
computed as 2N where N is the number of bits in the digital number. For example, an 8-bit D/A
converter could be expected to produce 28, or 256, discrete output steps. If the full-scale range
of the converter is 0 to 10 volts, then each step will be 10/256, or about 39 millivolts. If finer
resolution is required, we need more bits in the digital number. Thus, a converter with 10-bit
resolution would provide 210, or 1024, steps with each step being equivalent to 10/1024, or
about 9.8 millivolts. Accuracy of a D/A converter describes the amount of error between the
actual output of the converter and the theoretical output for a given input number. This rating
inherently includes several other sources of error.
A certain amount of time is required for the output of a D/A converter to be correct once
a particular digital number has been applied at the input. Two major factors cause this delay.
First, it takes time for the changes to pass through the converter circuitry; this is called
propagation time. Second, the output of the D/A converter has a maximum rate of change called
slew rate, which is identical to the slew rate problems discussed with reference to op amps. The
delays caused by slew rate limiting and propagation time are collectively referred to as settling
time--the total time required for the analog output to stabilize after a new digital number has
been applied to the input.
The overall operating range of a D/A converter can be shifted up or down from the
optimum point. This DC offset is called offset error. In a somewhat similar manner, one end of
the range can be correct but the other extreme too high or too low. This is called a gain error or
scaling error.
As with A/D converters, we normally want a monotonic output. In other words, the
output should increase whenever the input number increases. However, it is possible for a D/A
converter to have a reduction in analog output at a particular point in its range, even though the
digital input is increasing uniformly.
Figure-3: Oscilloscope display showing several imperfections in a low-quality D/A converter.
Figure-3 shows the performance of a low-quality D/A converter. Several of the potential
problems described are present in the converted waveform. The input to the converter is a 4-bit
down counter (e.g., 15, 14, 13... 2, 1, 0, 15), and the analog output should be 16 equally spaced,
decreasing steps for each cycle, producing a reverse saw tooth waveform. If you examine the
waveform carefully, you can see the 16 distinct output levels; however, the steps are not equal in
amplitude (linearity problems)--the midpoint level actually increases instead of decreasing (non
monotonic), and there are several glitches caused by switching transients.
R-2R LADDER D/A CONVERTER
One of the most popular methods for D/A conversion is shown in Figure-5. It is called
an R2R ladder D/A converter, since the input network resembles the rungs on a ladder and the
resistors in the input network are either equal (R) or have a 2:1 ratio (2R). One advantage of
the R2R converter over the weighted converter previously discussed is immediately apparent;
the resistors have a 2:1 ratio regardless of the number of bits being converted. This makes
matching resistors much easier and even makes the use of integrated resistors practical.
An easy way to analyze the operation of the circuit is to Thevenize the input circuit for
one or more digital input numbers. Once the input circuit has been simplified with the venin’s
Theorem, you will be left with a simple inverting amplifier circuit whose input voltage is the
Thevenin equivalent voltage and whose gain is determined by the ratio of feedback resistance
to The venin equivalent input resistance. By performing several analyses with different input
numbers, you will discover that the least significant input (b0) produces the least effect on
output voltage, and the next input (bl) has twice as much effect on output voltage. Similarly,
bit b2 has twice the effect of b1, but only half the effect onoutput voltage of b3. These variable
effects are identical to the relative weights of the digits in a binary number.
Figure-5: A 3-bit R2R ladder D/A converter utilizing a 741 op amp
Calculations: Output Voltage is given by

Vo = - VR * (Rf / 2R) * ( b2/2 + b1/4 + b0/8 )
where, VR = 5V , Rf = 2R , b2(MSB bit ) and b0 (LSB bit )
Design Constraints
• Resistance should be use ±1 to ±5 tolerance
• Input voltage should be 5V for high and 0V for low.
EXPERIMENT
(a) R-2R LADDER DAC

1. Setup the circuit as shown in Figure-5. Select the approximate value of R and 2R
2. Set the approximate value of R and 2R.
3. Reference voltage VR is set as 5V
4. Find the output voltage Vo for different combinations of digital binaryinputs from
000 to 111.
5. Compare the calculated values with observed values and plot DAC characteristics
(b) Experimental data and observations
R-2R LADDER DAC
b2 b1 b0 Vo ( observed) Vo ( Calculated)
0 0 0 0V 0V
0 0 1 0.624V 0.625V
0 1 0 1.249V 1.25V
0 1 1 1.874V 1.875V
1 0 0 2.50V 2.5V
1 0 1 3.1249V 3.125V
1 0 1 3.1249V 3.125V
1 1 0 3.7499V 3.75V
1 1 1 4.3749V 4.375V
PRE LAB QUESTIONS
POST LAB QUESTIONS
1. Determine the output voltage of the DAC in Figure-7(a). The sequence of four-digit binary codes
represented by the waveforms in Figure-7(b) are applied to the inputs. A high level is a binary l,
and low level is a binary 0. The least significant binary digit is D0.
Figure-7
2. The R-2R ladder DAC shown in Figure-8 below consists of 10K & 20KΩ resistors, VREF =
2V and R1 = 10KΩ. Determine the values required for RF such that VFS = 10V.
Figure-8
R-2R Ladder DAC:
Graph for b2=1, b1=0, b0=0
Similarly perform all the inputs as in below table and note down the values
Vo ( Calculated) = - VR * (Rf / 2R) * ( b2/2 + b1/4 + b0/8 )
where, VR = 5V , Rf = 2R , b2(MSB bit ) and b0 (LSB bit )
= -(-5)*(10K/10K)*(1/2) For b2=1, b1=0, b0=0
= 2.5V
Similarly perform all the inputs as in below table and note down the values
R-2R LADDER DAC
b2 b1 b0 Vo ( observed) Vo ( Calculated)
0 0 0 0V 0V
0 0 1 0.62499V 0.625V
0 1 0 1.2499975V 1.25V
0 1 1 1.8749962V 1.875V
1 0 0 2.50V 2.5V
1 0 1 3.1249938V 3.125V
1 0 1 3.1249938V 3.125V
1 1 0 3.7499924V 3.75V
1 1 1 4.3749914V 4.375V
Results: The R-2R LADDER DAC is successfully designed and implemented using LTSpice.
Department of Electronics and
Communication Engineering

Day / Session : 4/AN
Venue : Google classroom

Title of Experiment. : FLASH TYPE ADC
Date of Conduction :19/04/2021

Marks
Particulars Max. Marks
Obtained
Report 10
Viva 10
Total 40
REPORT VERIFICATION
Staff Name : KALIMUTHU K Signature :
13. FLASH TYPE ADC
13.1 OBJECTIVES
To construct a FLASH type A to D Convertor using LTspice simulation.
1 LM324 Refer data sheet in 1

appendix
3 Resistors 1K Ω 8
6 Multimeter 1
13.3 THEORY
A flash ADC (also known as a direct-conversion ADC) is a type of analog-to-digital
converter that uses a linear voltage ladder with a comparator at each "rung" of the ladder to
compare the input voltage to successive reference voltages. Often these reference ladders
are constructed of many resistors; however, modern implementations show that capacitive
voltage division is also possible. The output of these comparators is generally fed into a digital
encoder, which converts the inputs into a binary value (the collected outputs from the
comparators can be thought of as a unary value).Flash converters are extremely fast
compared to many other types of ADCs, which usually narrow in on the "correct" answer over
a series of stages. Compared to these, a flash converter is also quite simple and, apart from
the analog comparators, only requires logic for the final conversion to binary. For best
accuracy, often a track-and-hold circuit is inserted in front of the ADC input. This is needed
for many ADC types (like successive approximation ADC), but for flash ADCs there is no real
need for this, because the comparators are the sampling devices.
A flash converter requires a huge number of comparators compared to other ADCs,

especially as the precision increases. A flash converter requires comparators for an n-bit
conversion. The size, power consumption and cost of all those comparators makes flash
converters generally impractical for precisions much greater than 8 bits (255 comparators). In
place of these comparators, most other ADCs substitute more complex logic and/or analog
circuitry that can be scaled more easily for increased precision. Flash ADCs have been
implemented in many technologies, varying from silicon-based bipolar (BJT) and
complementary metal–oxide FETs (CMOS) technologies to rarely used III-V technologies.
Often this type of ADC is used as a first medium-sized analog circuit verification.
The earliest implementations consisted of a reference ladder of well matched resistors
connected to a reference voltage. Each tap at the resistor ladder is used for one comparator,
possibly preceded by an amplification stage, and thus generates a logical 0 or 1 depending on
whether the measured voltage is above or below the reference voltage of the resistor tap.
The reason to add an amplifier is twofold: it amplifies the voltage difference and therefore
suppresses the comparator offset, and the kick-back noise of the comparator towards the
reference ladder is also strongly suppressed. Typically designs from 4-bit up to 6-bit and
sometimes 7-bit are produced.
Designs with power-saving capacitive reference ladders have been demonstrated. In
addition to clocking the comparator(s), these systems also sample the reference value on the
input stage. As the sampling is done at a very high rate, the leakage of the capacitors is
negligible. Recently offset calibration has been introduced into flash ADC designs. Instead of
high-precision analog circuits (which increase component size to suppress variation)
comparators with relatively large offset errors are measured and adjusted. A test signal is
applied, and the offset of each comparator is calibrated to below the LSB value of the ADC.
Another improvement to many flash ADCs is the inclusion of digital error correction. When
the ADC is used in harsh environments or constructed from very small integrated circuit
processes, there is a heightened risk that a single comparator will randomly change state
resulting in a wrong code. Bubble error correction is a digital correction mechanism that
prevents a comparator that has, for example, tripped high from reporting logic high if it is
surrounded by comparators that are reporting logic low.
Fig 1 Flash type ADC
Fig 2 IC pin configuration LM324

Fig 3 IC pin configuration 74LS148
13.4 EXPERIMENT Flash type ADC

Setup the circuit as shown in Figure-1. Select the approximate value of R=1K ohm.
Reference voltage Vref is set as 5V
Find the output voltage Vo by adjusting Vin and obtain digital output.
Compare the analog input values with observed Digital output.
Experimental data and observations
Analo Comparator o/p Digital o/p Analog i/p
g i/p Observe d
_ I7 _ I6 _ I5 _ I4 _ I3 _ I2 _ I1 _ I0 _ _ _
(0-5v) (v)
A2 A1 A0
0-0.5 1 1 1 1 1 1 1 0 0 0 0
0.5- 1 1 1 1 1 1 0 1 0 0 1
1.0
1.0- 1 1 1 1 1 0 1 1 0 1 0
1.5
1.5- 1 1 1 1 0 1 1 1 0 1 1
2.0
2.0- 1 1 1 0 1 1 1 1 1 0 0
2.5
2.5- 1 1 0 1 1 1 1 1 1 0 1
3.0
3.-3.5 1 0 1 1 1 1 1 1 1 1 0
3.5- 0 1 1 1 1 1 1 1 1 1 1
4.0
Design Constraints
• Resistance should be use ±1 to ±5 tolerance
• Input voltage should be 5V for high and 0V for low.
13.5 LTspice Simulation Circuit Diagram :
Input and Output:
Fill the table Observation:
Input voltage range Output
Y1 Y0
0 to 1.25 V 0 0
1.25 V to 2.5 V 0 1
2.5 V to 3.75 V 1 0
3.75 V to 5 V 1 1

1. Classify ADCs on the basis of their output.
2. Mention the control lines present in ADC.
3. Which type of ADC follows conversion technique of changing the analog input voltage as a
function of frequency?
13.7 POST LAB QUESTIONS
1. Calculate the conversion time of a 12-bit counter type ADC with
1MHz clock frequent to convert a full scale input?
2. How many comparators are required for 4-bit ADC?
Result: The required output is obtained and the waveform is verified.
Conclusion: The Fash Type ADC has successfully designed ,implemented and verified using
LTspice.
College of Engineering and Technology
18ECC202J Linear Integrated Circuits

Topic : WATER LEVEL INDICATOR
Team Members:
NAME Registration No. Marks obtained
NIDHISH PILLAI RA1911004010146
VISHNU SHAJU RA1911004010154
SHASHIKANT GOSWAMI RA1911004010155
REPORT VERIFICATION
Date :
Staff name : Dr.K.Kalimuthu
Signature :
Experiment : Minor project
Title : WATER LEVEL INDICATOR

Objective : WATER LEVEL INDICATOR USING TRANSISTOR
DESCRIPTION:-
We can consider this whole circuit as 4 small circuits, each one for
indicating/alarming, when a particular level of water have been
reached. When water level reaches to a particular level, then the Led
corresponding to that level will start glowing. And finally, when tank
gets full, circuit with buzzer gets completed and buzzer starts beeping
Components Required: -
1) BC 547C Transistors – 4pcs
2) 2.2kΩ Resistors – 4pcs
3) 100Ω Resistors – 4pcs
4) LEDs– 3pcs
5) Buzzer – 1pc
6) Voltage Source – 5V
WORKING:-
Here we are using transistor (of NPN type) as a switch. Initially there
is no voltage applied to the base of the Transistors and the transistors
are in OFF state and no current is flowing through collector and
emitter so LEDs are also OFF.
When the water level reaches to Point 1 in the tank, the positive side
of the battery gets connected to the base of the Transistor Q1 through
the water. So when a positive voltage has been applied to the base of
the Transistor Q1, it gets into ON state and current starts flowing from
collector to emitter and LED-1 glows.
You can see resistors (R4, R5, R6, R7) at the base of each transistor,
which is used to limit the maximum Base current. Generally, a
transistor gets its ON state fully when voltage of 0.7 V is applied to
the base. There are also resistors (R1, R2, R3) with each of the LEDs,
to drop the voltage across LEDs, otherwise LED may blow up.
Same phenomenon happens when water level reaches to Point 2. As
soon as water level reaches to Point 2, a positive voltage gets applied
to the Transistor Q2, it gets ON and current started flowing through
LED-2, and LED-2 glows. With same principle, LED-3 glows when
water level reaches to Point 3 and finally Buzzer beeps when water
level reaches to 4.
Simulation Using LTspice :-

• We have performed the transient analysis for a stop time of 10
sec. using LTspice.
• I have used 4 ac-pulse voltage sources each having a time
delay of 2 sec with respect to the previous one to indicate the
water level in the tank.
• For the simulation of Buzzer, I have used a 100 Ω resistor. The
main power supply voltage is 5V.
Circuit Diagram:
OUTPUT:
This displays that as the water reaches at each level after a fixed
interval of 2 seconds each the current begins to flow through the LED
belonging to that particular level, and therefore it starts glowing.
Finally after 7 seconds when water reach to the top level the branch
having buzzer becomes conducting and as a result the buzzer starts
beeping
Observations at definite intervals: -
1) At t = 0 seconds:
- Water level starts rising in the tank.
- Water level reaches the 1st mark. So LED1 starts glowing.
- Water level continues to rise.
- Water level reaches the 2nd mark. So LED2 also starts glowing.
- Water level reaches the 3rd mark. So LED3 also starts glowing.
- Water level reaches up to the brim. So buzzer starts
beeping.
The buzzer beeps continuously until the water level reduces or the
power supply is switched off
Advantages:
1. Power Saver
Living in an age where we need to be more conscious of the energy
that we use, a water level controller is ideal at saving power.
Normally, regulating water levels can consume electricity and
wastewater. However, with automatic controllers, the electricity usage
is limited as well as less water needed to regulate supply.
2. Money Saver
A water level controller helps save money by limiting the waste of
water and electricity. These devices accurately regulate how much
energy is used to protect against any unnecessary water/electricity
usage. Over time, the money saved is quite substantial.
3. Automatic
Another notable advantage with these devices is that they regulate on
their own. Eliminating manual operations with a timer switch, the
frustrations of manual monitoring water tanks are minimized. Water
levels are maintained at the appropriate levels thanks to the automatic
operations of these devices.
4. Water Maximization
On average, water pumps are used more during midday. A water level
controller can maximize the water usage provided during midday
while automatically lessening the water usage at night. This results in
an appropriate level of water at all times being maintained, while
providing you with the maximum use of your water at the appropriate
times.
5. Reliable Electronic Design
Addressing the durability problems found in earlier designs, the solid-
state electronics in the newer models help to eliminate them. Not only
do they help to eliminate the durability issues, but they also create
considerable savings of the life span of the unit with an advanced
modular design. In order to minimize problem areas of these designs,
the only moving parts are the relays. These relays are easily replaced
and tested by any skilled operator or electrician while being an
inexpensive part.
6. New Control Minimize Fouling & Deterioration
Proving to be less costly, over time, than the original float design for
the ‘toilet tank’. The solid-state electronics are designed to minimize
volt usage (less than 1 volt). This directly minimizes the mineral
fouling, plating, rusting, and deterioration of probes, proving to be
safer and more efficient. These factors extend the life span of the
controllers significantly, which saves money and energy.
7. Easy Installation with LED Monitoring
These new solid-state electronics and integrated electronics offer
superior performance, hassle-free installation, and lower cost to
operate over time when compared to the lifespan of the original
design. For continuous monitoring, the integrated firmware and
digital dry-contact circuitry easily and quickly connect to the
automation systems of a building. Each function of the integrated
electronics and relays use LED lights to offer operators the ability to
visually scan them in order to verify proper operations.
Applications:
The purpose of a water level indicator is to gauge and manage water
levels in a water tank. The control panel can also be programmed to
automatically turn on a water pump once levels get too low and refill
the water back to the adequate level
Result: The required output is obtained and verified

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18ECC202J – Linear Integrated Circuits

NAME: SHASHIKANT GOSWAMI

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

FACULTY OF ENGINEERING AND

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

COLLEGE OF ENGINEERING & TECHNOLOGY

SRM INSTITUTE OF SCIENCE AND TECHNOLOGY

Certified to be the bonafide record of work done by ___SHASHIKANT GOSWAMI_____

Date: 24/05/2021 Head of the Department

Submitted for University Examination held on ____________________ at SRM

Date: 24/05/21 Internal Examiner I Internal Examiner II

Name:SHASHIKANT GOSWAMI Class: ECE-C

Reg.No: RA1011004010155 Branch: ECE

Exp. Date of Title of Experiment Marks

2 01/02/21 INTEGRATOR AND DIFFERENTIATOR 36

4 15/02/21 COMPARATOR AND SCHMITT TRIGGER 30

5 22/02/21 WAVE SHAPING CIRCUIT USING OP AMP 36

6 01/03/21 SINE WAVE USING OP AMP 35

8 15/03/21 DESIGN OF MONOSTABLE AND ASTABLE 36

12 15/04/21 R-2R LADDER DAC 40

14 29/04/22 Mini Project 5

1. BASIC OP-AMP CIRCUITS

1.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer data sheet in 1

2 Cathode Ray Oscilloscope (0 – 20MHz) 1 1

4 Dual Regulated power supply (0 -30V), 1A 1

5 Function Generator (0-2) MHz 1

6 ASLK PRO Kit Refer data sheet in 1

1.3.7. Design Constraints

1.4 PRE LAB QUESTIONS

2. A non-inverting amplifier has R1 of 2K & Rf of 200K . Determine Vf and

(2) Voltage follower

op-amp Input signal Output signal Voltage gain

Non-inverting 1V 100Hz 10V 100Hz 10 10

Voltage 5V 0.83Hz 5V 0.83Hz 1 1

Inverting 1V 1kHz 10V 1kHz 10 10

1.8. POST LAB QUESTIONS

2. Comment on the statement: “The closed-loop gain-bandwidth product is a

Name : shashikant goswami

Day / Session : 4/AN

Title of Experiment : INTEGRATOR AND DIFFERENTIATOR

Date of Conduction :28/01/2021

Date of Submission :5/01/2021

Pre lab and Post lab 10

Simulation and results 10

Staff Name : Kalimuthu K

2. INTEGRATOR AND DIFFERENTIATOR

2.2 HARDWARE REQUIRED

1 IC 741 Refer data sheet in appendix 1

2 Cathode Ray Oscilloscope (0 – 20MHz) 1 1

5 Dual Regulated power supply (0 -30V), 1A 1

6 Function Generator (0-2) MHz 1

7 ASLK PRO Kit 1

Fig.2-1 Basic op-amp integrator The output

Fig. 2-2 Practical op-amp integrator

Fig.2-3 Basic op-amp

Fig. 2-4 Practical op-amp differentiator

2.4 PRE LAB QUESTIONS

Certified to be the bonafide record of work done by _SHASHIKANT GOSWAMI___