A 90 nm Logic Technology Featuring 50nm Strained Silicon Channel

Transistors, 7 layers of.Cu Interconnects, Low k ILD, and 1 urnz SRAM Cell
S. Thompson, N.Anand, M. Armstrong, C. Auth, B. &cot, M. Alavi”, P. Bai, I. Bielefeld, R. Bigwood, 1. Brandenburg, M. Buehler, S. Cea, V.
Chikarmane,C. Choi, R. Frankovic,T. Ghani, G. Glass, W. Han, T. Hoffmann*, M. Hussein, P. Jacob, A. lain. C. Jan, S . Joshi, C. Kenyon, I.
Klaus, S Klopcic, I. Luce, 2.Ma, B. Mcintyre, K .Misty, A. Munhy, P. Nguyen. H.Pearson, T. Sandford, R. Schweinfunh,R. Shah&*, S .
Siv&mar, M. Taylor, B. Tufts, C. Wallace, P. Wang, C. Weber*, and M. Bohr
Portland Technology Development, * TCAD,’ QRE, Intel Corporation, Hillsbro, OR 97124, USA.

Abstract 193 nm lithography is used to pattern the poly-silicon

A leading edge 90 nm technology with 1.2 nm physical gate layer down to a gate dimension of SO nm as shown in
gate oxide, SO nm gate length, strained silicon, NiSi, 7 lay- Figure 2. The minimum pitches and thicknesses for the
ers of Cu interconnects, and low k CDO for high perform- technology layers are summarized in Table 1. The result is a
ance dense logic is presented. Strained silicon is used to I.0pm2 6-T SRAM cell without the use of a local intercon-
increase saturated NMOS and PMOS drive currents by 10- nect layer. Figure 3 shows a top-down SEM image of the
20% and mobility by > 50%. Aggressive design rules and polysilicon gate conductor. The interconnect technology
unlanded contacts offer a l.0pm2 6-T S R A M cell using uses dual damascene copper to reduce the resistances of the
193nm lithography. 7 layers of interconnects. Carbon-doped oxide (CDO) is
Introduction used as inter-level dielectric (ILD) to reduce the dielectric
The power dissipation of modern microprocessors has been constant. The dielectric constant k is measured to be 2.9.
rapidly increasing, driven by increasing transistor count and
clock frequencies. The rapidly increasing power has occurred
z
even though the power per gate switching transition has de-
creased approximately (0.7)’ per technology node due to volt-
age scaling and device area scaling. Figure 1 shows these
trends for Intel’s microprocessors and CMOS logic technology
;.>I& .- 50nm
generations. In this paper we describe a 90 nm generation 1.2 nm Gate p!:’,,.. , I I;.
technology designed for high speed and low power operation.
Strained silicon channel transistors are used to obtain the de- Oxide
sired performance at 1.0V to 1.2V operation.
10000~
renw Figure 2: TEM of S0nm transistor.

5
B
n0 Pentiud
U)
E

1.5 1 0.8 0.6 0.35 0.25 0.18 0.13

Technology (pm)
Figure 1: Power and transistor switching energy trends.
Figure
- 3: 1 . . silicon gate
-
procesS Flow and Technology Features conductor of 1.OHmz6-T S R A M bit.
Front-end technology features include shallow trench
isolation, retrograde wells, shallow abrupt sourceldrain ex-
tensions, halo implants, deep sourcddrain, and nickel salici-
dation. N-wells and P-wells are formed with deep phosphw
rous and shallow arsenic implants, and boron implants respec-
tively. The trench isolation is 400 nm deep to provide robust
inma- and inter-well isolation for N+ to P+ spacing below 240
nm while maintaining low junction capacitance. Sidewall
spacers are formed with CVD Si,N4 deposition, followed by
etch-back. Shallow sourcedrain extension regions are
formed with arsenic for NMOS and boron for PMOS. Nisi
is formed on poly-silicon gate and source-drain regions to Metal 7 I 1080 1
972 1.81
provide low contact resistance. Table 1: Layer pitch, thickness (nm) and aspect ratio
3.2.1
IEDM 61
 Transistor 1000
Gate length and gate oxide scaling have been the domi- 1.0Vstrain channel
nant factors to improve transistor performance [ 1-31. In this
technology, we continue with gate length and oxide scaling ...

-
but also use Si& to strain the silicon channel for improved
mobility. To control short channel effects, a thin 1.2 nm
physical oxide is used as shown in Figure 4. The thin oxide Y
0
enables MOSFETs with well-controlled short channel char- - 1
acteristics down to a physical gate of 50 nm, which is a 0 . 7 ~ 1.2V strain channel
scaling of our previous generation on a two-year offset L31
0.1
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
( m M 4
IDSAT
Figure 6: NMOS ION vs. ION at 1.OV and 1.2V
1000

-1 00
E
Figure 4: TEM of I .?nm gate oxide.
-a= 10
Strained silicon channels have been shown experimen-
-
$ 1
tally 141 and theoretically [ 5 ] to offer large mobility en-
hancement (greater than 2X), thus, giving strong motivation
for incorporation into future CMOS technologies. Yield 0.1
considerations and CMOS flow integration issues place con-
0.3 0.4 0.5 0.6 0.7 0.8
straints on the magnitude of silicon strain and hence mobility
enhancement. In this work, strained silicon channels with IDSAT(m4m)
greater than 50% mobility enhancement are inserted into an Figure 7: PMOS ION vs. ION at 1.OV and 1.2V.
integrated process flow with equivalent yield. Due to elec- Three techniques to strain the silicon channel have been
tron and hole velocity saturation, the benefit strained en- previously reported (Figure 8): (a) biaxial in-plane tensile
hanced mobility on short channel device performance has strain using epitaxial Si& [4-6,9-12], (b) strain by a tensile
been the subject of some debate. The first confirmation that film [ 13,141, and (c) strain by mechanical force [71. Strained
strain-enhanced mobility improves saturated drive current silicon channel CMOS obtained by a tensile film (without
for short O.lum devices was shown in 1998 161 and again implant relaxation) provides small to no net gain since it
recently in 2001 [7]. For the first time we show that for sub- improves electron mobility but degrades hole mobility 1131.
100 nm transistors with gate lengths as small as 50 nm, the Implant relaxation is also difficult to implement due to close
enhanced mobility still improves the saturated drive current. proximity of n and pchannel transistors [ 141. It is interest-
Also, we observe that for the same magnitude of electron ing that large hole mobility enhancement is predicted theo-
and hole mobility improvement, a larger saturation current retically [ 5 ] but much smaller improvements have been o b
gain is observed for p channel transistors due to velocity

lpx]
served experimentally [4]. Many publications have reported
saturation being less important for holes than electrons. on large electron mobility enhancement for biaxial in-plane
Figures 6 and 7 show the saturated drive currents for tensile straining using Si&, however, the magnitude of en-
strained silicon surface n and p channel MOSFETs, which hanced hole mobility has varied [4,9]. Also phonon-limited
are improved IO - 20 % over our best 50 nm non-strained mobility enhancement is predicted theoretically [8] to be
channel control device (Iom = 40 nNwm). present at both low and high effective vertical fields but ex-
perimental data have been inconclusive [4,9], possibly due
Technology Feature Size to increased surface roughness scattering at high effective
9 k m l field in some of the samples.
180nrn Mechankal
l8Onm 130nm
;E, 0.1
.s
v) loonm
70nm....50
.n; .......
Gate

0.01
1980 1990 2000 2010
(8) (b) (e)
Figure 5 : Transistor size and technology trend. Figure 8: Techniques to strain the silicon channel.
3.2.2
62-1EDM
This work, while having some similarities with the above- better narrow gate polyicide resistance compared to cobalt
discussed approaches, is unique and uses epitaxial SiGe to silicide with raised source/drdins.
strain the silicon channel. High mobility is achieved by
making devices with equivalent fixed oxide charge and sur-
face roughness compared to bulk. In this work, both the
electron and hole mobility gains are present at both low and
high effective vertical fields. The enhanced hole mobility
versus effective field is shown in Figure 9 and compared to
other recent publications. By varying the Ge concentration,
the strain in the silicon can be increased or decreased. Fig-
ure IO shows the hole mobility enhancement versus strain.
In this work with high yield, we target > 50% improved mo-
bility.
5 6 7 8 9 1 0 1 1 1 2
'Ei 140 E, / (MV/cm)

y-
0
Figure I I : I .2 nm gate oxide time to fail vs. electric field.

-.
E0
120
100
80
P
B
60
0 2002
I 40
0 0.2 0.4 0.6 0.8 1 1.2
EWFI (MV/cm)
Figure 9: Hole mobility as a function of effective field.

75 0 0.1 0.2 0.3

g
0
m
U) 5 0
Hole Mobility D i
Gate size I pm

-c Maiii e1 al. 1997

Figure 12: Resistance vs. gate size for Nisi and COS2.
.-
-
5
.- 25 Miruno et al. 2001
Interconnects
n Rim et al. 2002
Rim et al.
This process technology uses dual damascene copper
I " 0 interconnects and CDO (k=2.9) inter-level dielectric to
z -25
1995
achieve reliable, high performance wiring. Figure 13 is a
cross-section SEM image showing the dual damascene in-
0 10 20 30 terconnects. Metal pitches are 220 nm at the first metal
% Ge layer and increase to l080'nm at the top layer. Contacts to
Figure I O Low field hole mobility vs. Ge concentration. the substrate use tungsten plugs. CDO is used for all layers
except M 1 and M7.
Saturation drive currents are 1.26 mA/pm for N and 0.63 I ----.-
mA/pm for P-channel high VT devices with 40 nA/um off-
state leakage (Figures 6 and 7). Low threshold devices are
also offered with 10X higher leakage and 15% higher drive
current. Subthreshold slopes for both N and P-channel
high and low V, devices remain well controlled at less than
85 mV/decade at ~ , , T E = 50 nm. The dielectric time to fail
for the 1.2 nm oxide on the strained silicon channel meets
the requirements for 1.2 V operation including tolerances
(Figure 1 I).
Since the SiGe in the source/drain regions inhibits cobalt
silicide transition to the low resistivity disilicide phase,
nickel silicide or cobalt silicide with a silicon buffer layer in
the source drains is needed. Both approaches can support
low resistance polycide down to < 50 nm as shown in Figure
. A
12. However, nickel silicide is the primarily approach since
it provides lower cost, improved interface resistance and Fieure 13: Cross-section SEM imaee of a orocessed wafer.
L L

3.2.3
IEDM 63
 Vias are etched first before the trenches without using Conclusion
two etch-stop layers I IS I. The single thin SIN provides 15% A 90 nm generation logic technology has been demon-
lower line to line capacitance over the two etch stop ap- strated with low power high performance strained silicon
proach. The low K ILD reduces the line-to-line capacitances channel transistors. Excellent interconnect performance is
on average 22% over fluorinated SiOz used on the 130 nm achieved by using 7 layers of dual damascene Cu with CDO
technology 12,31 as shown in Figure 14. Metal aspect ratios dielectrics. The technology performance capabilities are
are optimized for minimum RC delay. and range from I .6 to demonstrated with a strained silicon channel 5 2 Mbit SRAM
I .8. To benchmark the performance of interconnects, Figure operating at 2.0 GHz.
IS shows the RC delay in picoseconds per millimeter of
wire. Data for each metal layer is shown as a function of the
minimum pitch at that layer. For a given pitch, a 70% reduc-
tion in RC is achieved by using Cu interconnects and CDO
ILD over aluminum and fluorinated SiOl [ I I.

.
-
v
I
0.13

0.11
1- % <<za
9
l.l98

Cu ,SiOF
J! Tyagi et al. 2000
5 0.09
c
I

0
$ 0.07 - U, CDO (This Work)
I Figure 16: Die photo of 52 Mbit SRAM with Ipm2 6-T cell.
0 200 400 600 800 1000 1200 1400
Pitch I (nm)

Figure 14: Line-to-line capacitance as a function of layer

pitch.
-L 1.1
1.7 Ghz
at 1.OV

P
-- 140
120
100
1.05

1
2
-
2
80
60
40
0.5
Cycle Time (ns)
Figure 17: Schmoo plot for the 52 Mbit SRAM.
0.6

a 20
0 References
[ I I S . Yangetal.,lEDMTech. Dig.,pp. 197-200,(lW8)
200 400 600 800 1000 1200 1400
121 S . Tyagi et al., IEDM Tech. Dig., pp. 567-71, (2000)
Pitch I (nrn) [31 S. Thompson et al.. IEDM Tech. Dig., pp. 257-61, (2001)
Figure 15: RC delay for a wire length of Imm as a func- [4] K. Rim et al., Symposium on VLSl Technol. Dig. Tech. Pa-
tion of layer pitch. pers, pp. 98-9.2CO2
151 M.V. Fischetti and S. E. Laux. I. Appl. Phys. 80, p. 2234,
(1996)
SRAM Test Vehicle [6] K. Rimetal., IEDM Tech. Dig., pp. 707-11, (1998)
A yielding 52 Mbit CMOS SRAM has been designed and
[7] A. Lochtefeld and D. A. Antnoniddis IEEE Electron Device
fabricated on this technology incorporating the strained sili- Lett.. EDL-22, pp. 59 1-3, (2001)
con channel transistors and 7 metal layers with CDO. A die 181 S . Takagi, et al., J. Appl. Phys., pp. 1567-77, (1996)
photo of the 52 Mbit SRAM is shown in Figure 16. The 5 2 [9] D. Hisamoto et al., IEDM Tech. Dig.. pp. 737-41, (2001)
Mbit SRAM die size is 109 mm2 and contains 330 millions [10]K.Rimetal.,lEDMTech.Dig.,pp.517-21,(199S)
transistors. All 330 million transistors have a strained sili- [I I ] C . Maiti et al., Solid-StateElectron, p. 1863, (1997)
con channel and are used as a yield and reliability test vehi- (121T. Mizuno et al., Trans. Elec. Devices pp. 1612-18, (2001)
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schmoo plot for the SRAM, i.e. the Fmax as a function of [I41 A. Shimizu et al., IEDM Tech. Dig., pp. 433-37, (2001)
voltage. The SRAM operates at > 2.0 Ghz at 1.2 V. 1151 A. H. Perera et al., IEDM Tech. Dig., pp. 571-575, (2000)

3.2.4
64-IEDM