DM74LS181 4-Bit Arithmetic Logic Unit

October 1988
Revised April 2000

DM74LS181
4-Bit Arithmetic Logic Unit
General Description Features
The DM74LS181 is a 4-bit Arithmetic Logic Unit (ALU) ■ Provides 16 arithmetic operations: add, subtract, com-
which can perform all the possible 16 logic operations on pare, double, plus twelve other arithmetic operations
two variables and a variety of arithmetic operations. ■ Provides all 16 logic operations of two variables:
exclusive-OR, compare, AND, NAND, OR, NOR, plus
ten other logic operations
■ Full lookahead for high speed arithmetic operation on
long words

Ordering Code:
Order Number Package Number Package Description
DM74LS181N N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide

Logic Symbols Connection Diagram

Active High Operands

Active Low Operands

Pin Descriptions
Pin Names Description
A0–A3 Operand Inputs (Active LOW)
B0–B3 Operand Inputs (Active LOW)
S0–S3 Function Select Inputs
M Mode Control Input
Cn Carry Input
F0–F3 Function Outputs (Active LOW)
A=B Comparator Output
VCC = Pin 24
G Carry Generate Output (Active LOW)
GND = Pin 12
P Carry Propagate Output (Active LOW)
Cn+4 Carry Output

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DM74LS181
Functional Description
The DM74LS181 is a 4-bit high speed parallel Arithmetic DM74LS181 devices. Carry lookahead can be provided at
Logic Unit (ALU). Controlled by the four Function Select various levels and offers high speed capability over
inputs (S0–S3) and the Mode Control input (M), it can per- extremely long word lengths.
form all the 16 possible logic operations or 16 different The A = B output from the device goes HIGH when all four
arithmetic operations on active HIGH or active LOW oper- F outputs are HIGH and can be used to indicate logic
ands. The Function Table lists these operations equivalence over four bits when the unit is in the subtract
When the Mode Control input (M) is HIGH, all internal car- mode. The A = B output is open-collector and can be wired-
ries are inhibited and the device performs logic operations AND with other A = B outputs to give a comparison for
on the individual bits as listed. When the Mode Control more than four bits. The A = B signal can also be used with
input is LOW, the carries are enabled and the device per- the Cn+4 signal to indicate A > B and A < B.
forms arithmetic operations on the two 4-bit words. The The Function Table lists the arithmetic operations that are
device incorporates full internal carry lookahead and pro- performed without a carry in. An incoming carry adds a one
vides for either ripple carry between devices using the Cn+4 to each operation. Thus, select code LHHL generates A
output, or for carry lookahead between packages using the minus B minus 1 (2s complement notation) without a carry
signals P (Carry Propagate) and G (Carry Generate). In the in and generates A minus B when a carry is applied.
ADD mode, P indicates that F is 15 or more, while G indi- Because subtraction is actually performed by complemen-
cates that F is 16 or more. In the SUBTRACT mode, P indi- tary addition (1s complement), a carry out means borrow;
cates that F is zero or less, while G indicates that F is less thus a carry is generated when there is no underflow and
than zero. P and G are not affected by carry in. When no carry is generated when there is underflow. As indi-
speed requirements are not stringent, it can be used in a cated, this device can be used with either active LOW
simple ripple carry mode by connecting the Carry output inputs producing active LOW outputs or with active HIGH
(Cn+4) signal to the Carry input (Cn) of the next unit. For inputs producing active HIGH outputs. For either case the
high speed operation the device is used in conjunction with table lists the operations that are performed to the oper-
the 9342 or 93S42 carry lookahead circuit. One carry loo- ands labeled inside the logic symbol.
kahead package is required for each group of four

Function Table
Mode Select Active LOW Operands Active HIGH Operands
Inputs & Fn Outputs & Fn Outputs
Logic Arithmetic Logic Arithmetic
(Note 2) (Note 2)
S3 S2 S1 S0 (M = H) (M = L) (Cn = L) (M = H) (M = L) (Cn = H)

L L L L A A minus 1 A A
L L L H AB AB minus 1 A+B A+B
L L H L A+B AB minus 1 AB A+B
L L H H Logic 1 minus 1 Logic 0 minus 1
L H L L A+B A plus (A + B) AB A plus AB
L H L H B AB plus (A + B) B (A + B) plus AB
L H H L A⊕B A minus B minus 1 A⊕B A minus B minus 1
L H H H A+B A+B AB AB minus 1
H L L L AB A plus (A + B) A+B A plus AB
H L L H A⊕B A plus B A⊕B A plus B
H L H L B AB plus (A + B) B (A + B) plus AB
H L H H A+B A+B AB AB minus 1
H H L L Logic 0 A plus A (Note 1) Logic 1 A plus A (Note 1)
H H L H AB AB plus A A+B (A + B) plus A
H H H L AB AB minus A A+B (A + B) plus A
H H H H A A A A minus 1
Note 1: Each bit is shifted to the next most significant position.
Note 2: Arithmetic operations expressed in 2s complement notation.

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 DM74LS181
Logic Diagram

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DM74LS181
Absolute Maximum Ratings(Note 3)
Note 3: The “Absolute Maximum Ratings” are those values beyond which
Supply Voltage 7V the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Input Voltage 7V Characteristics tables are not guaranteed at the absolute maximum ratings.
Operating Free Air Temperature Range 0°C to +70°C The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Storage Temperature Range −65°C to +150°C

Recommended Operating Conditions

Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −0.4 mA
IOL LOW Level Output Current 8 mA
TA Free Air Operating Temperature 0 70 °C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 4)
VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max,
2.7 V
Output Voltage VIL = Max
VOL LOW Level VCC = Min, IOL = Max,
0.35 0.5
Output Voltage VIH = Min V
IOL = 4 mA, VCC = Min 0.25 0.4
II Input Current @ Max VCC = Max, VI = 7V M input 0.1
Input Voltage An, Bn 0.3
mA
Sn 0.4
Cn 0.5
IIH HIGH Level VCC = Max, VI = 2.7V M input 20
Input Current An, Bn 60
µA
Sn 80
Cn 100
IIL LOW Level VCC = Max, VI = 0.4V M input −0.4
Input Current An, Bn −1.2
mA
Sn −1.6
Cn −2.0
IOS Short Circuit VCC = Max
−20 −100 mA
Output Current (Note 5)

ICC Supply Current VCC = Max, Bn, Cn = GND

37 mA
Sn, M, An = 4.5V
Note 4: All typicals are at VCC = 5V, TA = 25°C.
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.

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 DM74LS181
Switching Characteristics
VCC = 5V, TA = 25°C
CL = 15 pF
Symbol Parameter Conditions Units
Min Max
tPLH Propagation Delay M = GND 27
ns
tPHL Cn to Cn+4 20
tPLH Propagation Delay M = GND 26
ns
tPHL Cn to F 20
tPLH Propagation Delay M, S1, S2 = GND; 29
ns
tPHL A or B to G (Sum) S1, S3 = 4.5V 23
tPLH Propagation Delay M, S0, S3 = GND; 32
ns
tPHL A or B to G (Diff) S1, S2 = 4.5V 26
tPLH Propagation Delay M, S1, S2 = GND; 30
ns
tPHL A or B to P (Sum) S0, S3 = 4.5V 30
tPLH Propagation Delay M, S0, S3 = GND; 30
ns
tPHL A or B to P (Diff) S1, S2 = 4.5V 33
tPLH Propagation Delay M, S1, S2 = GND; 32
ns
tPHL Ai or Bi to Fi(Sum) S0, S3 = 4.5V 25
tPLH Propagation Delay M, S0, S3 = GND; 32
ns
tPHL Ai or Bi to Fi(Diff) S1, S2 = 4.5V 33
tPLH Propagation Delay M = 4.5V 33
ns
tPHL A or B to F (Logic) 29
tPLH Propagation Delay M, S1, S2 = GND; 38
ns
tPHL A or B to Cn+4 (Sum) S0, S3 = 4.5V 38
tPLH Propagation Delay M, S0, S3 = GND; 41
ns
tPHL A or B to Cn+4 (Diff) S1, S2 = 4.5V 41
tPLH Propagation Delay M, S0, S3 = GND; 50
ns
tPHL A or B to A = B S1, S2 = 4.5V; 62
RL = 2 kΩ to 5.0V

Sum Mode Test Table 1 Function Inputs

S0 = S3 = 4.5V, S1 = S2 = M = 0V
Input Other Input Other Data Inputs Output
Symbol Under Same Bit Under
Test Apply Apply Apply Apply Test
4.5V GND 4.5V GND
tPLH Ai Bi None Remaining Cn Fi
tPHL A and B
tPLH Bi Ai None Remaining Cn Fi
tPHL A and B
tPLH A B None None Remaining P
tPHL A and B, Cn
tPLH B A None None Remaining P
tPHL A and B, Cn
tPLH A None B Remaining Remaining G
tPHL B A, Cn
tPLH B None A Remaining Remaining G
tPHL B A, Cn
tPLH A None B Remaining Remaining Cn+4
tPHL B A, Cn
tPLH B None A Remaining Remaining Cn+4
tPHL B A, Cn
tPLH Cn None None All All Any F
tPHL A B or Cn+4

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DM74LS181
Diff Mode Test Table 2 Function Inputs
S1 = S2 = 4.5V, S0 = S3 = M = 0V
Input Other Input Other Data Inputs Output
Symbol Under Same Bit Under
Test Apply Apply Apply Apply Test
4.5V GND 4.5V GND
tPLH A None B Remaining Remaining Fi
tPHL A B, Cn
tPLH B A None Remaining Remaining Fi
tPHL A B, Cn
tPLH A None B None Remaining P
tPHL A and B, Cn
tPLH B A None None Remaining P
tPHL A and B, Cn
tPLH A B None None Remaining G
tPHL A and B, Cn
tPLH B None A None Remaining G
tPHL A and B, Cn
tPLH A None B Remaining Remaining A=B
tPHL A B, Cn
tPLH B A None Remaining Remaining A=B
tPHL A B, Cn
tPLH A B None None Remaining Cn+4
tPHL A and B, Cn
tPLH B None A None Remaining Cn+4
tPHL A and B, Cn
tPLH Cn None None All None Cn+4
tPHL A and B

Logic Mode Test Table 3 Function Inputs

S1 = S2 = M = 4.5V, S0 = S3 = 0V
Input Other Input Other Data Inputs Output
Symbol Under Same Bit Under
Test Apply Apply Apply Apply Test
4.5V GND 4.5V GND
tPLH A B None None Remaining Any F
tPHL A and B, Cn
tPLH B A None None Remaining Any F
tPHL A and B, Cn

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 DM74LS181 4-Bit Arithmetic Logic Unit
Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide

Package Number N24A

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Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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