06 So Emb Simulation - Key

Embedded System
Simulation
Peter Thorwartl
06_so_emb_simulation.odp Date Oct 31, 2009 Page
SO-LOGIC electronic consulting Lustkandlg 52, Vienna, Austria, Europe, World www.so-logic.net +43-1-315 77 77
Objectives: Simulation
After completing this module, you will be able to:

 Describe the functionality of SimGen
 Describe the integration of SimGen within XPS
 Describe the simulation process
 Describe SmartModel Libraries and how to use them
 Set up for hardware simulation with the Xilinx ISIM hardware simulator
SimGen
 The Simulation Model Generator (SimGen) tool generates and configures
various simulation models for the specified hardware
 SimGen generates simulation models by using a Microprocessor Hardware
Specification (MHS) file
 SimGen searches for input files in the following directories located in the project
directory
 <project_directory>/hdl
 system_name.[vhd|v]
 peripheral_wrapper.[vhd|v]
 <project_directory>/implementation (if any of the peripherals are black box)
 peripheral_wrapper.ngc
 system_name.ngc
 system_name.ncd
SimGen creates and configures various VHDL and Verilog simulation models for a specified hardware. SimGen takes an MHS
file as input that describes the hardware. SimGen is also capable of creating scripts for a specified vendor simulation tool. The
scripts compile the generated simulation models.
SimGen
• SimGen-generated directories  SimGen produces
 <peripheral_wrapper>.[vhd|v] ***
project_directory  <system_name>.[vhd|v]
 <system_name>.do
simulation directory  <system_name>_sim.bmm
<Sim_model>*
 <system_name>.sdf **
* <Sim_model> = behavioral/structural/timing
** <system_name>.sdf in timing simulation
*** <peripheral_wrapper>.[vhd\v] in behavioral or structural simulation
peripheral_wrapper.[vhd|v]: Post-synthesis simulation files.

system_name.[vhd|v]: The top-level HDL file of the processor and its peripherals.
system_name.do: The compilation script for the specified simulator.
Memory Initialization
 To initialize memory in the system.bmm executable.elf
simulation models created
by SimGen, you need system.[vhd|v]
 The compiled executable
 executable.elf Data2MEM
The simulation hardware model
generated by executing SimGen
 system.vhd or system.v
 The BMM file generated by PlatGen system_init.[vhd|v]
 <project_directory>/implementation directory
 Data2MEM uses these files and generates a
system_init.vhd file that contains block memory
initialization content
If a design contains banks of memory for a system, the corresponding memory simulation models can be initialized with data.
The compiled executable files are generated with the appropriate gcc compiler or assembler from corresponding C or assembly
source code.
The system.bmm file is created by the PlatGen tool and carries block memory-related information (see the next page), including
the following:
• Number of block memories
• Address range for each set of block memory
• Data indexing for each block memory in a set
The executable.elf file is generated by the compiler and carries data variables and code.
The system.vhd file is generated by the SimGen tool and carries a hardware model of the system.
The Data2MEM program uses these files, extracts data code information, and generates a system_init.vhd file that contains
block memory initialization content.
Simulation Libraries: XILINX
 UNISIM library
Used for behavioral simulation and contains default unit delays
Includes all of the Xilinx Unified Library components that are inferred by most
popular synthesis tools
 SIMPRIM library
Used for structural and timing simulation
Includes all of the Xilinx Primitives Library components that are used by Xilinx
implementation tools
 XilinxCoreLib library
Contains pre-optimized modules for taking advantage of architectural resources
Includes Library models used for behavioral simulation
May be used for your own defined IPs
 Structural and timing simulation models generated by SimGen instantiate the

SIMPRIM library components
The HDL code must refer to the appropriate compiled library. The HDL simulator must map the logical library to the physical
location of the compiled library.
The following libraries are provided by Xilinx for simulation. These libraries can be compiled by using COMPXLIB.
UNISIM library: This is a library of functional models used for behavioral and structural simulation. It contains default unit
delays and includes all of the Xilinx Unified Library components that are inferred by most popular synthesis tools. The UNISIM
library also includes components that are commonly instantiated, such as I/Os and memory cells. You can instantiate the
UNISIM library components in your design (VHDL or Verilog) and simulate them during behavioral and structural simulation.
SIMPRIM library: This is a library used for timing simulation. This library includes all of the Xilinx Primitives Library
components that are used by the Xilinx implementation tools. Structural and timing simulation models generated by SimGen
instantiate SIMPRIM library components.
XilinxCoreLib library: The Xilinx CORE Generator™ software utility is a graphical intellectual property design tool for
creating high-level modules such as FIR filters, FIFOs, or CAMs as well as other advanced IP. You can customize and pre-
optimize modules to take advantage of the inherent architectural features of Xilinx FPGA devices, such as block multipliers,
SRLs, fast-carry logic, and on-chip single-port or dual-port RAM. The HDL library models in the CORE Generator software
tool are used for behavioral simulation. You can select the appropriate HDL model to integrate into your HDL design. The
models do not use library components for global signals.
Simulation Libraries: EDK
 EDK library
Used for behavioral simulation
Contains models of all the EDK IP components
PowerPC® 440 processor models are not available for the ModelSim XE
simulator
VHDL and Verilog support
Must be compiled for the target simulator
Compile the EDK library using the GUI from XPS (see next slide)
 Library can also be compiled by using the following command (not recommended by
Xilinx)
 compedklib [ -h ] [ -o output-dir-name ] [ -lp repository-dir-name ]
[ -X compxlib-output-dir-name ] [ -E compedklib-output-dir-name ]
The HDL code must refer to the appropriate compiled library. The HDL simulator must map the logical library to the physical
location of the compiled library. Before starting behavioral simulation of your design, you must compile the EDK simulation
libraries for the target simulator. For this purpose, Xilinx provides a tool called COMPEDKLIB for compiling EDK HDL-based
simulation libraries by using the tools provided by the simulator vendor. This tool compiles the HDL in EDK pcore libraries for
simulation by using the simulators supported by the EDK. Currently, the only supported simulator is MTI PE/SE.
The most common case is as follows:
• compedklib -o <compedklib-output-dir-name> -X <compxlib-output-dir-name>
In this case, the pcores available in the EDK install are compiled and then stored in <compedklib-output-dir-name>. The value
of the “-X” option indicates the directory containing the models outputted by COMPXLIB, such as the UNISIM, SIMPRIM,
and XilinxCoreLib compiled libraries.
If you had your own repository of EDK style pcores, you may need to compile them into <compedklib-output-dir-name> as
follows:
• compedklib -o <compedklib-output-dir-name> -X <compxlib-output-dir-name> -E <compedklib-output-dir-name> -lp <Your-
Repository-Dir>
In this form, the “-E” value accounts for the possibility that some of the pcores in your repository may need to access the
compiled models generated by Use Case I. This is probably because the pcores in your repository may refer to HDL sources in
the EDK built-in repositories.
Compiling Simulation Libraries
 With the XPS project open
Select Edit → Preferences
Select Application
Preferences
–In the Simulation Libraries
Path area, select the EDK
and Xilinx libraries to
compile
Click Compile
Before you perform this step, make sure that the modelsim.ini file is set to read and write permission (that is, not set to read only
permission).
Specify the Simulation Flow
 With the XPS project open
Select Project → Project
Options
Select the HDL and
Simulation tab
Specify your supported
simulator and the type of

simulation
Before you perform this step, make sure that the modelsim.ini file is set to read and write permission (that is, not set to read only
permission).
Apply Your Knowledge
 Which three items are required to initialize memory in the simulation models
created by SimGen?
Integration within XPS
 Open the ISE® software project 1
Start ISE and XPS
by using Project Navigator
 Add system_i.xmp as a source
to the project
 Make sure that Sources view is
set for synthesis/implementation
 Select system_i in the Sources
window and double-click
Manage Processor Design to
open XPS
 Specify simulation parameters by 2 Set up library paths by using
Project Options
selecting Project → Project
Options
 HDL and Simulation tab
 HDL
 Simulator Compile Script
 Simulation Libraries Path
– EDK Library
– XILINX Library
 Simulation Models
 Generate the simulation models 3
Generate the simulation model
Generation of simulation
models: Select Simulation →
Generate Simulation HDL Files
Use within the
Project Navigator
 VHDL
4 Create/add the testbench file
Project → New Source →
VHDL Testbench
Project → Add Source; add the testbench to the project
 Verilog
Project → New Source → Verilog Test Fixture
Project → Add Source; add the testbench to the project
Use within the
Project Navigator
 VHDL 5 Copy the .do files to the
You must copy over the <project_file>.do ProjNav directory
simulation file
Testbench.vhd must be added to the .do file
Testbench.vhd must include a configuration statement to load the RAM
initialization strings included in <project_file>_init.vhd

 Verilog
You must copy over the <project_file>.do simulation file
Testbench.v must be added to the .do file
Testbench.v must include a #include statement to load the RAM initialization
strings included in <project_file>_init.v

 Alternatively, write your own .do script (lab exercise)
Opening the Third-Party
Simulator
 In the Sources window, select the 6
Run the third-party simulator
Behavioral Simulation view
 In the Sources window, select
the testbench
 In the Processes window,
double-click Simulate
Behavioral Model
SmartModel Libraries
 SmartModel Libraries are compiled simulation models that represent integrated
circuits and system buses as black boxes
 SmartModel Libraries
Accept an input stimulus and respond with an appropriate output behavior
Provide improved performance over gate-level models
Protect proprietary designs
Can be used with any simulation tool that supports the SWIFT interface
SmartModel Libraries represent integrated circuits and system buses as black boxes that accept an input stimulus and respond
with an appropriate output behavior. These behavioral models provide improved performance over gate-level models and
protect the proprietary designs created by semiconductor vendors. SmartModel Libraries connect to hardware simulators
through the SWIFT interface, which is integrated with over 30 commercial simulators, including Synopsys VCS, Cadence
Verilog-XL, and Mentor Graphics ModelSim simulators.
In Windows, select System in the Windows Control Panel to open the System Properties dialog box. Select the Advanced tab
and select Environment Variables. The Environment Variables dialog box appears. Set the variables to the following values (if
not already set):
• LMC_HOME %Xilinx%\smartmodel\nt\installed_nt
• PATH %LMC_HOME%\bin;%LMC_HOME%\lib\pcnt.lib;%PATH%
Note that %PATH% represents what your PATH variable had before the changes. Make sure you keep this.
Running a Simulation
Using SmartModel Libraries
 The SWIFT interface provides access to SmartModel Libraries

 Changes required in the modelsim.ini file
Resolution = ps
Comment out the "PathSeparator" = / using “;”
Veriuser = $MODEL_TECH/libswiftpli.dll (SWIFT Interface)
Uncomment the following lines for the appropriate OS
 libsm = $MODEL_TECH/libsm.dll
 libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
 set MODELSIM=<path_to_modelsim.ini_script>\modelsim.ini
 Instantiate the appropriate MGT or PowerPC processor primitive
The Xilinx simulation flow in the Virtex®-II Pro, Virtex-4, and Virtex-5 devices uses VMC models from Synopsys to simulate
the PowerPC microprocessor and RocketIO™ multi-gigabit transceiver.
VMC models are simulator-independent models that are derived from the actual design and are, therefore, accurate evaluation
models. To simulate these models, a simulator that supports the SWIFT interface must be used. SmartModel Libraries are
included in the implementation tools.
Although ModelSim PE and SE simulators support the SWIFT interface, certain modifications must be made to the default
ModelSim simulator setup to enable this feature.
In the modelsim.ini initialization file, you can edit GUI and simulator settings so that they default to your preferences. You must
edit parts of this modelsim.ini file for it to work properly with the simulation models in the Virtex-II Pro, Virtex-4, Virtex-5
devices.
The following changes should be made to the modelsim.ini file located in the MODEL_TECH directory. (An alternative to
making these edits is changing the MODELSIM environment variable setting in the MTI setup script so that it points to the
modelsim.ini file located in the project design directory.)
1. Change the "Resolution = ns" statement to "Resolution = ps"
2. Comment the statement called "PathSeparator = /" by adding a ";" at the start of the line
3. For Verilog designs, enable SmartModel Libraries by changing the variable "Veriuser" to:
Veriuser = $MODEL_TECH/libswiftpli.dll
4. Search for the [lmc] section and uncomment the libsm and libswift definitions according to the operating system. In
Windows, uncomment the following lines:
libsm = $MODEL_TECH/libsm.dll
libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
Supported Simulators and
Platforms
 Solaris Operating System (2.8, 2.9)
MTI ModelSim SE simulator (6.1e or newer)
Cadence NC-Verilog simulator (5.8 or newer)
Cadence NC-VHDL simulator (5.8 or newer)
Synopsys VCS simulator (X2006.06 or newer)
 Windows XP
MTI ModelSim SE simulator (6.1e or newer)
 Linux (RHEL 4.0)
MTI ModelSim SE simulator (6.1e or later)
 Check the Synthesis and Simulation Design Guide (ISE) and the Xilinx EDK
home page (Installation and Setup link)
Simulation with ISIM
 EDK simulation with ISIM is not supported by Xilinx
Technical support will not support EDK/ISIM simulation
Because of the costs associated with third-party simulation tools for training, Xilinx
Education Services has chosen to provide an ISIM version of this lab for your edification
 Currently it works only with a script and is not supported with the GUI
 Because many designers want this, Xilinx Education Services is providing you the
opportunity to run it now in lab
 This is not mainstream and is considered an “on-your-own” option
 This flow requires you to
 Employ a TCL script to simulate the design (isim_run-mb.tcl or isim_run-ppc.tcl)
 Run a batch file to compile all the necessary libraries (doSimulationStuff-mb.bat or
doSimulationStuff-ppc.bat)
 No special installation or license of the ISE tools is required
Remember that you can download the lab files after class.
doSimulationStuff.bat
Batch File
 The batch file used in the lab
Compiles the necessary libraries
Specifies the input files to ISIM
Compiles the custom IP cores
Builds the simulation models
Runs ISIM and loads the waveform into the viewer
Calls the isim_run TCL script
Can be customized to call the testbench that is automatically made by SimGen
 @fuse -prj %simDir%\system.prj -top system_tb_conf -o isim_system -jobs 4

– Replace system_tb_conf in this line from the batch file
– Note that the 4 allows up to four processors to be used to speed simulation
 You are encouraged to copy the batch file for your own use
 In the “Performing System Simulation” lab, you will open the batch file to identify some
of its contents
isim_run TCL script
 The TCL scripting language is known by many designers
 You are encouraged to improve your skill set by learning this language
 However, this course cannot teach you all you need to know to write an original script in
this class
 Feel free to copy the included script for your use
 The isim_run TCL script
Creates the clock, reset, and input stimulus
Selects signals to be displayed in the waveform viewer
Generates the waveform stimulus
 In the “Performing System Simulation” lab, you will open this script to identify
some of the language basics
Summary: Simulation
 The Embedded Development Kit (EDK) includes all the tools, documentation, and IP
necessary for building embedded systems
 The Software Development Kit (SDK) is a comprehensive software development
environment for simple software and firmware for complex applications
 The Base System Builder (BSB) makes it easy to build a full hardware design targeting
an available demo board
 Merging hardware and software bitstreams in an FPGA flow is completed with the
Data2MEM utility
 Hardware netlists for an embedded design must still be implemented with the ISE tools
 Hardware simulation is most frequently done with third-party simulation tools other than
ISIM
Currently, support is only accomplished with the use of a TCL script and a batch file
BFM Simulation
 List various bus-based system verification methods

 Describe what a Bus Functional Model (BFM) is and how it helps in verification
 List various BFM simulation components
 State the steps involved in performing BFM simulation
Typical Bus Peripherals
 Three components
Bus interface
Core
I/O interface
Bus Peripheral I/O

Interface Core Interface
Xilinx Bus Implementation
 Fixed bus-width sizes (smaller bus size devices can be used with addressing
restrictions)
 Devices use byte-enable architecture (no conversion cycles for dynamic bus
sizing)
 No data mirroring (byte enables and least significant address bits from masters
must be consistent)
 Devices required to output logic zero when inactive
 See the Processor IP Reference Guide for details
Bus-Based Device
Functionality Verification
 Testbench-driven verification
Create a testbench which describes extensive (all different) combinations of bus
transactions
 Very time consuming
 System verification
Describe the connections done to the Device Under Test (DUT) and program the
other components to generate the desired bus transactions that the DUT will
respond to or the DUT generates the bus transactions
 Involves developing, compiling, and storing code in memory
 Bus Functional Model (BFM) simulation
Useful for a bus-based device
Provides the ability to generate bus stimulus without needing the above two
methods
Creating a testbench, which will be very large in size, is a time-consuming task and involves describing the connections and test
vectors for all different combinations of bus transactions.
Creating a system with other components requires describing the connections done to the device under test and programming
the other components to generate the desired bus transactions that the device under test will respond to or to respond to bus
transactions that the device under test is generating. Programming this device usually involves creating some code, compiling
and storing it in some memory for the components to read, and generating the right bus transactions.
Bus functional simulation simplifies the verification of hardware components that attach to a bus. It provides the ability for
generating bus stimulus without the need for undergoing the above approaches.
Why Platform Studio BFM?
• Take advantage of the EDK connecting engine and
HDL writer
– MHS-defined system
– No need to write HDL
• Replace any number of IP components with “wrapped”
BFM models or add new to your MHS
• Compilation is very quick
• Simulation time reduced significantly
< 5 minutes to
set up the debugging
platform
What is BFM Simulation?
 BFM simulation is a type of simulation that uses bus functional models to verify
hardware components that have a bus interface
 BFMs provide the capability for easily generating, responding to, and analyzing
bus transactions
 BFMs verify that hardware components meet bus architecture specifications
Using BFM Simulation
 BFM simulation can be used for
 Verifying IP
 Slave IP verification
– The master BFM is used to generate bus transactions and the DUT responds
 Master IP verification
– The master DUT generates transactions and a slave BFM responds
 Only care about the internals of the IP design and the bus interactions, not the rest of the
system
 Speeding up simulation
 Do not care about the internals of the IP design, only the bus interactions
 Two sources
 IBM CoreConnect Toolkit
 Xilinx Platform Studio BFM Package
There are two main use cases for bus functional models:
• Verifying IP: When verifying a single piece of IP that has a bus interface, you are mainly concerned
about the internal details of the IP design and the bus interactions. Attaching the IP to a large system only to verify that it is
functioning properly is inefficient.
• Speeding up simulation: When verifying a large system design, simulating the internal details of
each IP component that attaches to a bus is sometimes very time consuming. There are certain very complex pieces of IP
that take a long time to simulate and could be easily replaced by a bus functional model, especially when the internal details
of the IP are not of interest. Some of these IP components are not even simple to program for generating the desired
bus transactions.
IBM CoreConnect Toolkit
 Collection of three toolkits
OPB toolkit
PLB toolkit
DCR toolkit
 Each toolkit includes a collection of HDL files that represent predefined systems
 You can manually modify to connect the hardware components to be tested
Modifications can be time consuming
 Free download after registering and obtaining a license
www.xilinx.com/ipcenter/processor_central/register_coreconnect.htm
Xilinx Platform Studio BFM
Package
 Not included as part of the EDK installation
 Collection of bus functional models, compiler, and documentation
 Capability for specifying bus connections through the MHS file
 Time and effort required to set up the testing environment is reduced
 Free download after registering and obtaining a license
 www.xilinx.com/coreconnect
 After installing the package, check the installation from the command prompt by
executing
 C:\>xilbfc -check
 A “Success!” message should display
BFM Simulation Components
 BFM: Bus Functional Model
 Different models for different buses
 OPB bus
 PLB bus
 BFM synchronization bus
 BFL: Bus Functional Language
 Describes the behavior of the BFM
 BFC: Bus Functional Compiler
Translates the BFL file to simulator commands that change the behavior of the
BFM
Bus Functional Models (BFM) are hardware components that include and model a bus interface. There are different bus
functional models for different buses. For example, there are OPB BFM components and PLB BFM components. Each is used
to connect to its own respective bus. For each bus, there are different types of models. For example, there are OPB Master, OPB
Slave, and OPB Monitor BFM components. The same, or even more, could exist for different buses and sometimes the
functionality of various BFM components is combined into a single one.
Bus Functional Language (BFL) is used to describe the behavior of the BFM components. You can specify how to initiate or
respond to bus transactions by using simple commands in a BFL file.
The Bus Functional Compiler (BFC) translates a BFL file into the commands that actually program the selected bus functional
model.
Bus Models
 OPB device BFM
Can act as a master, slave, or both
Maintains internal memory which can be initialized through BFL
 OPB monitor BFM

Connects to the OPB and continuously samples the bus signals
 PLB master BFM
Contains logic to initiate bus transactions automatically
Maintains internal memory which can be initialized through BFL
OPB device BFM (opb_device_bfm): The OPB device model can act as a master, slave, or both. The master contains logic for
automatically initiating bus transactions on the bus. The slave contains logic for responding to bus transactions based on an
address decode operation. The model maintains internal memory which can be initialized through bus functional language and
can be dynamically checked during simulation or when all bus transactions have completed.
OPB monitor BFM (opb_monitor_bfm): The OPB monitor is a model which connects to the OPB and continuously samples the
bus signals. It checks for bus compliance or violations of the OPB architectural specifications and reports warnings and errors.
PLB master BFM (plb_master_bfm): The PLB master model contains logic for automatically initiating bus transactions on the
bus. The model maintains internal memory which can be initialized through bus functional language and can be dynamically
checked during simulation or when all bus transactions have completed.
PLB slave BFM (plb_slave_bfm): The PLB slave contains logic for responding to bus transactions based on an address decode
operation. The model maintains internal memory which can be initialized through bus functional language and can be
dynamically checked during simulation or when all bus transactions have completed.
PLB monitor (plb_monitor_bfm): The PLB monitor is a model which connects to the PLB and continuously samples the bus
signals. It checks for bus compliance or violations of the PLB architectural specifications and reports warnings and errors.
BFM synchronization bus (bfm_synch): The BFM synchronization bus is not a bus functional model, but a simple bus that
connects the various bus functional models in a design and allows communication among them. This bus is required whenever
BFM devices are used.
Bus Functional Language
 Bus Functional Language (BFL) is not case sensitive
 Comments are delineated using -- or //
 General command form
 command(parameters)
 parameters can be one or more parameter=value pairs, separated by comma
 parameters can be specified in order
 Value can be scalar or enumerated type (string)
 Commands can be categorized as the following types
Configure
Alias
Monitor
Master
Slave
BFL Commands
 Device Configure
 set_device(path=string,device_type=string)
 Within a BFL fiIe (test case), there can be only one set_device () command used per
model initialization
e.g., set_device(path=/system/my_device/my_device/device,device_type=opb_device)
 Alias
An optional command which sets up an alias to be used for string substitution in
the command parameters
e.g., set_alias(TARGET_REG = 01020304)
 Monitor
 Several commands useful for monitoring bus activities
 Configure, read, write, configure_write_report, and configure_read_report
Study the files generated in the lab.

BFL Commands
 Master
 Several commands for configuring and operating a device in master mode
 Configure, read bus cycle, write bys cycle configure, ALU, and restart commands
e.g., read (addr, be, req_size)
e.g., write (addr, be, req_size, data)
 Slave
 Several commands for configuring and operating a device in slave mode
mem_init, configure, response, and mem_check commands

e.g., mem_init(addr, data)

e.g., mem_check(signal_to_synchronize_with, addr, data)
Refer to documentation for detailed explanation of enriched commands
BFM Simulation Flow
 Two approaches
Create a peripheral device by using the Create or Import Peripheral Wizard and
selecting the Generate BFM Simulation Platform option
 Add additional peripherals which can interact with the created peripheral
 Create a blank project in XPS*
 Use BFM models and create a system
 Add the peripheral to be tested
* Rarely used because the Create or Import Peripheral Wizard provides the project
Create or Import Peripheral
Wizard
Start the wizard and select the Go through the various steps of the peripheral
appropriate peripheral creation and select the Generate BFM
Simulation Platform option
Create or Import Peripheral
Wizard
 Go to the directory where the peripheral is created
Either the <current project directory>\pcores or repository directory
 Go to the hdl\vhdl directory
 Edit the user_logic.vhd file to incorporate the peripheral functionality
Instantiate top-level of your user logic
 Go to the devl\bfmsim directory under the created peripheral directory
 Double-click bfm_system.xmp to start XPS
 Add any other peripheral to the system if desired
 Follow the simulation steps as described next
BFM Simulation Set Up
 From XPS, select Project → Project Options and click the HDL and
Simulation tab
 Select the ModelSim simulator
 Select Edit → Preference and set up library paths for the EDK and Xilinx
libraries
 Select Simulation → Generate Simulation HDL Files
 Develop a simulation command file (e.g., sample.bfl – see next slide) in the
behavioral simulation directory
 Click the User Commands button ( ) in XPS
 Compiles the commands file
 e.g., C:\>xilbfc sample.bfl
 Runs the ModelSim simulator
 Compile all HDL files and use DO files
BFL File Snippet
-- Initialize my_device
-- The instance name for my_device is duplicated in the path as the wrapper level inserted by the
tools
set_device (path=/system/my_device/my_device/device,device_type=opb_device)
-- Write and read some 32-bit data using byte-enable architecture
-- The CoreConnect opb_device is a 64-bit device; the 8-bit byte enables are aligned accordingly
write (addr=ffff0100,be=11110000,data=00112233)
read (addr=ffff0100,be=11110000,data=00000033)
-- Write and read some 16-bit data using byte-enable architecture
The CoreConnect opb_device is a 64-bit device; hence, the 8-bit byte enables are aligned accordingly (shifted by 0s). You can
also list 64-bit data in the data field, but make sure that 32-bit 0s are inserted at appropriate positions.
For example:
Summary
 A BFM package includes BFM models and a compiler
 BFM simulation allows verification of bus-based device functionality using BFM
 BFM simulation is fast and does not involve adding devices to a complete
system
 BFL provides commands to initialize and configure devices, generate bus
transactions, and monitor responses
 BFC compiles BFL-based commands output, which is used by the ModelSim
simulator
Knowledge Check
What are the two flows for BFM simulation?
What is BFM simulation? What is it used for?
What does the Xilinx Platform Studio BFM support package include?
Answer
What are the two flows for BFM simulation?
 Create a peripheral device by using the Create or Import Peripheral Wizard
 Add additional peripherals which can interact with the created peripheral
Create an empty project in XPS and build a system using BFMs and the
peripheral to be tested
What is BFM simulation? What is it used for?
BFM simulation is a type of simulation that uses bus functional models to verify
hardware components that have a bus interface
BFM simulation helps to verify that hardware components meet bus architecture
specifications
Answers
What does the Xilinx Platform Studio BFM support package include?
BFM: Bus Functional Models for OPB, PLB, bus synchronization
BFL: Bus Functional Language constructs for modeling bus behavior
BFC: Bus Functional Compiler for compiling BFL-based constructs

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Embedded System

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After completing this module, you will be able to:

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peripheral_wrapper.[vhd|v]: Post-synthesis simulation files.

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May be used for your own defined IPs

 Structural and timing simulation models generated by SimGen instantiate the

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Must be compiled for the target simulator

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simulator and the type of

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Testbench.vhd must include a configuration statement to load the RAM

initialization strings included in <project_file>_init.vhd

strings included in <project_file>_init.v

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Protect proprietary designs

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 The SWIFT interface provides access to SmartModel Libraries

Veriuser = $MODEL_TECH/libswiftpli.dll (SWIFT Interface)

Uncomment the following lines for the appropriate OS

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Cadence NC-VHDL simulator (5.8 or newer)

Synopsys VCS simulator (X2006.06 or newer)

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Compiles the custom IP cores

Builds the simulation models

Runs ISIM and loads the waveform into the viewer

Calls the isim_run TCL script

Can be customized to call the testbench that is automatically made by SimGen

 @fuse -prj %simDir%\system.prj -top system_tb_conf -o isim_system -jobs 4

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Generates the waveform stimulus

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 List various bus-based system verification methods

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Bus Peripheral I/O

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 OPB monitor BFM