Gated or Clocked SR Flip Flop

It is sometimes desirable in sequential logic circuits to have a bistable SR flip-flop that only changes state when
certain conditions are met regardless of the condition of either the Set or the Reset inputs.

Flip flops are basically memory devices and clocks are used so that they respond to external stimuli. When the clock
is active only then the changes in the input will be registered. So, if you permanently disable the clock,  the flip flop
will permanently retain the previous input.

The main drawback of s-r flip flop is invalid output when both the inputs are high, which is referred to as Invalid State.

The NAND gate SR flip flop is a basic flip flop which provides feedback from both of its outputs back to its opposing input. This
circuit is used to store the single data bit in the memory circuit. So, the SR flip flop has a total of three inputs, i.e., 'S' and 'R',
and current output 'Q'.

No Change state[S = 0, R = 0]
When the clock pulse is applied, the output of NAND gates A and B will be S’ = 1, R’ = 1.

For this case, if Q = 0, Q’ = 1, then both the inputs for NAND gate C are 1 and the output thus produced by gate C is
Q+1 =0. The present state output is Q = 0 and the next state output is Q’ = 0. Thus the state has no change.

For the same SR inputs, if Q = 1, Q’ = 0, the inputs for NAND gate C will be 0 and 1. For these inputs, the output
produced by the NAND gate is Q+1 = 1, hence there is no change in the state.

RESET state[S = 0, R = 1]
Upon the application of the clock pulse, the output of NAND gate A and B are S’ = 1, R’ = 0.

Let the present state output be Q = 0 or Q = 1. For any of these inputs at the NAND gate D, the next state output
produced is Q’+1 = 1. Now, the tw0 inputs for NAND gate C are S’ = 1, Q’ = 1, which produces an output at next state
as Q+1 = 0.

For this case, whether the present state is either 0 or 1, it will produce an output 0, which will RESET the flip flop.

SET state[S = 1, R = 0]
When the clock pulse is applied, the output from the NAND gate A and B are S’ = 0, R’ = 1.
For this condition, irrespective of the present state input Q’, the next state output produced by the NAND gate C is
Q+1 = 1. Thus the two inputs of NAND gate D are R’ = 1 and Q = 1, which produces an output Q’+1 = 0.

So, in this case, whether the present state output is either 0 or 1, the next state output is logic 1, which will SET the
flip flop.

Indeterminate or Invalid state[S = 1, R = 1]

Now, if Q = 0 and Q’ = 1, the inputs for NAND gate C will be S’ = 0 and Q’ = 1. The output produced from NAND
gate C is Q+1 = 1. Similarly, the two inputs for NAND gate D will be R’ = 0 and Q = 0. The output produced from the
NAND gate D is Q’+1 = 1.

If Q = 1 and Q’ = 0, the output produced from the NAND gate C is Q +1 = 1 for the inputs S’ = 0 and Q’ = 0. For the
same value of Q and Q’, output produced from NAND gate D is Q’+1 = 1, where the inputs are R’ = 0 and Q = 1.

For this case, it is observed that the next state output Q +1 = 1 and Q’+1 = 1. This is an impossible output because Q and
Q’ should be complement with each other. So it is an indeterminate or invalid state.

Switching diagram of clocked SR Flip flop

SR flip flop is the basic building block of D flip flop. As we know, SR flip flop has two inputs (S, R) and
two outputs(Q and Q’).

When you look at the truth table of SR flip flop, you can observe the following. The S input is made high to
store logic 1 or to SET the flip flop. Similarly R input is made high to store logic 0 or to RESET the flip
flop. When both the inputs are the same, the output either does not change or it is invalid.

The states obtained for the same input are not necessary for most of the applications. Such applications
require only SET and RESET states. For those applications, we can use the S and R inputs which are
always complement to each other. The flip flop with such functionality is called as Data flip-flop or Delay
flip-flop or D flip-flop.

Circuit of D flip-flop
D Flip Flop is the most important of all the clocked flip-flops as it ensures that both the inputs S and R are
never the same at the same time. It is constructed by joining the S and R inputs with an inverter in between
them, as shown below. Thus the D flip flop has single input(D).

Replacing the NOT gate with single input NAND gate, the D flip flop circuit becomes
As you can observe from the circuit above, the input D is applied to the input of SR flip flop. The ‘Set’ input
of the SR flip flop receives the D input and the ‘Reset’ input receives the complement of D input(D’).

Operation and truth table of D flip-flop

When D = 0, the inputs of SR flip flop will become, S = 0, R = 1. This input combination for the SR flip lop
will produce logic LOW value, which will RESET the flip flop. The truth table of the D flip-flop is shown
below.

In simple words, we can say that, when the clock pulse is given, the output Q follows the D input of the flip
flop.