INTRODUCTION TO

I DDQ TESTING
 FRONTIERS IN ELECTRONIC TESTING

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 INTRODUCTION TO
IDDQ TESTING

by

Sreejit Chakravarty
State University of New York at Buffalo

and

Paul J. Thadikaran
Intel Corporation

SPRINGER SCIENCE+BUSINESS MEDIA, LLC

Library of Congress Cataloging-in-Publication

Introduction to IDDQ Testing

by Sreejit Chakravarty and Paul J. Thadikaran

ISBN 978-1-4613-7812-9 ISBN 978-1-4615-6137-8 (eBook)

DOI 10.1007/978-1-4615-6137-8

Copyright <ro 1997 Springer Science+Business Media New York. Second Printing 2002.
Originally published by Kluwer Academic Publishers in 1997
Softcover reprint of the hardcover 1st edition 1997
This printing is a digital duplication of the original edition.

AII rights reserved. No part of this publication may be reproduced, stored in a retrieval
system or transmitted in any form or by any means, mechanical, photo-copying, recording,
or otherwise, without the prior written permission of the publisher, with the exception of
any material supplied specificaIly for the purpose of being entered and executed on a
computer system, for exclusive use by the purchaser of the work.

Printed on acid-free paper.

To the loving memory of my father (Prof. Sunil Chakrabarti), my mother
(Maya), Kohinoor and Ayush for their love and understanding.

sc

To my father (T. P. Joseph), mother (Mary) and Lini for support and encour-
agement.

PJT
 CONTENTS

FOREWORD xi

PREFACE xv

1 INTRODUCTION 1
1.1 What is IDDQ Testing? 1
1.2 Why IDDQ Testing? 4
1.3 Outline of the Book 6

2 WHY I DDQ TESTING? 9

2.1 Dollars and Cents 10
2.2 Area, Coverage and Quality 15
2.3 Empirical Data on Quality 16
2.4 Empirical Data on Reliability 20
2.5 IDDQ and High Voltage Stress Screens 24

3 PUTTING I DDQ TESTING TO WORK 27

3.1 IDDQ Threshold 28
3.2 IDDQ Testing of Deep Submicron Devices 36
3.3 Current Signature 39
3.4 Speed and Number of IDDQ Measurements 42
3.5 IDDQ Testing Related Design Issues 45
3.6 Summary 58

4 PHYSICAL DEFECTS 59
4.1 Gate-Oxide Shorts 60
4.2 Shorts 63

vii
viii INTRODUCTION TO I DDQ TESTING

4.3 Opens 70
4.4 Anomalies in Detecting Bridges Using IDDQ 77
4.5 IDDQ DFT for flip-flops and scan-chains 82
4.6 IDDQ Testing of RAMs 91
4.7 Summary 97

5 TEST SUITES, FAULT MODELS, TEST SETS

AND DEFECTS 99
5.1 Test Suites 100
5.2 Fault Models for Slow Speed Testing 102
5.3 Fault Models for High Speed Testing 106
5.4 Fault Models for IDDQ Testing 114
5.5 Defects and Fault Models 132

6 EVALUATING I DDQ TESTS 145

6.1 Simulation of Extracted BFs 145
6.2 Simulation of Metal BFs and All BFs 147
6.3 Simulation of Leakage Faults 169
6.4 Simulation of Weak Faults 171
6.5 Summary 172

7 SELECTING I DDQ TESTS 175

7.1 Every Vector Method 176
7.2 IDDQ Test Selection 177
7.3 Selecting IDDQ Tests for Extracted BFs 181
7.4 Selecting IDDQ Tests for Leakage and Weak Faults 184
7.5 Selecting IDDQ Tests for Metal BF and All BF 187
7.6 Summary 198

8 COMPUTING I DDQ TESTS 201

8.1 Fault Collapsing 201
8.2 TC..ATPG for Combinational Circuits 207
8.3 CURRENT for Extracted BFs 212
8.4 ATPG for Leakage and Metal BFs using CUTEGEN 217
8.5 Analysis of ATPG for Combinational Circuits 217
8.6 ATPG for Sequential Circuits 225
Contents ix

8.7 Summary 226

9 FAULT DIAGNOSIS 227

9.1 Fault Location 228
9.2 Diagnostic Test Generation 238
9.3 Diagnostic Fault Simulation 240
9.4 Dynamic diagnosis 254

10 INSTRUMENTATION FOR I DDQ

MEASUREMENT 263
(Contributed by: Kenneth M. Wallquist)
10.1 Introduction 264
10.2 The Instrumentation Puzzle 264
10.3 Things to Consider 266
10.4 Degrading Factors 267
10.5 IDDQ vs. ISSQ Measurement 269
10.6 Historical Methods of Measuring IDDQ 270
10.7 Advanced Tester-Based Instrumentation 278
10.8 Loadboard-Mounted Instrumentation 280
10.9 Conclusion 286

REFERENCES 287

INDEX 317
 FOREWORD

The completeness of this book signals a maturity for that innovation in elec-
tronic testing of CMOS integrated circuits (ICs) called IDDQ testing. Today
we recognize the IDDQ test as the single most sensitive method for detecting
defects in CMOS ICs. IDDQ testing has a simple concept; the quiescent or
steady state portion of a CMOS circuit clock period should have a very low
power current since there are no continuous circuit paths between the VDD
power rail and the VSS ground. Quiescent currents of good circuits are at the
sub microAmp level and typically can be tens of nanoAmps. If high J.1-A or rnA
currents exist at a particular vector state, then the circuit isn't correct. Frank
Wanlass, who patented the CMOS technology in 1963, described CMOS cir-
cuits as a nanoWatt logic. One could extrapolate from Wanlass that if a CMOS
circuit didn't measure low quiescent currents, then it must have a defect, or a
design or fabrication error.

Early in the history of CMOS Ie development in the 1960's, RCA practiced

IDDQ testing on its CD4000 line of SSI/MSI parts. Philips Labs, Rome Labs,
and Sandia National Labs actively used this technique in the 1970s, despite the
fact that an electronic basis for the IDDQ test practice had yet to be demon-
strated. Except for George Nelson, E. King, and William Boggs of the US
Naval Research Labs, publications in the 1970's were rare and little exchange
among people occurred. That changed around 1980 when CMOS began to re-
place nMOS as the dominant IC technology. The International Test Conference
(ITC) attracted an initially small, but growing number of test engineers inter-
ested in the topic. Mark Levi in 1981, and Yashwant Malaiya and Stephen Su in
1982, presented aggressive papers at ITC outlining the benefits of IDDQ testing.
Around 1981, Toshio Maruyama of Advantest Corp. designed the first IDDQ
monitor for ATE that was fast and sensitive. His IDDQ Bit Current Option
could read a 1 J.1-A sensitivity at a 3-5 kHz measurement rate. Activity picked
up in the mid-1980's. John Zasio's (then at AIDA Corp.) succinct COMPCON
paper in 1985 was a precursor to modern thinking about defect-based testing,
IDDQ, and stuck-at faults. In a series of papers from 1985-91, Jerry Soden of
Sandia National Labs and Chuck Hawkins of the University of New Mexico and

xi
XlI INTRODUCTION TO I DDQ TESTING

colleagues at Sandia presented data showing the effectiveness of IDDQ testing

for specific CMOS defects. Mircille Jacomino, Jean Luc Rainard, and Rene
David of the Lab d'Automatique de Grenoble and Centre Nat. d'Etudes des
Telecom. also made comprehensive conclusions on varieties of test methods
including IDDQ'

In the 1990 era, major contributions to understanding the IDDQ technique

have come from Peter Maxwell, Rob Aitken, and Doug Josephson of Hewlett-
Packard, Keith Baker, Manoj Sachdev, Eric Bruls, and Bas Verhelst of Philips
Labs, Wociech Maly and Anne Gattiker of Carnegie Mellon University, Alan
Righter, Chris Henderson, Ron Fritzemeier, and Dick Beagle of Sandia Na-
tional Labs, Phil Nigh of IBM, Steve McEuen, Ravi Gulati, and Weiwei Mao
of Ford Microelectronics, Sreejit Chakravarty of the State University of New
York at Buffalo, Ken Wallquist and Grayson Garrett of Philips Semiconductors,
Keiichi Sawada of Mitsubishi, Roger Perry of Storagetek, Ric Gayle of NCR,
Joan Figueras, Antonio Rubio, Jaume Segura, Rosa Rodriguez-Montanes, Vic-
tor Champac, and Eugene Isern from the Universitat Politecnica de Catelonia,
Paul Wiscombe of VLSI Technology, Carol Tong of Sunrise, Ben Bennetts of
LogicVision, Michael Keating of GenRad, Dan Burns of Rome Lab, Ed Mc-
Cluskey and Hong Hao of Stanford University, Tom Storey of Loral Federal
Systems, Vic Kulkarni of Crosscheck, Rochit Rajsuman of LSI Logic, Simon
Johnson of the University of Durham, Hans Manhaeve at the University of
Oostende, Jacob Abraham of the University of Texas, Wayne Needham, Tony
Miller, Wendy Whitman, John Acken, Tim Henry, and Thomas Soo of Intel,
Joel Ferguson and Tracey Larabee of the University of California-Santa Cruz,
Anura Jayasumana of Colorado State University, H. Vierhaus of the German
National Research Center for CS, Sankaran Menon of the South Dakota School
of Mines & Technology, Jos van Sas and colleagues from Alcatel, Adit Singh of
Auburn University, Kozo Kinoshita of Osaka University, Andrew Richardson
of Lancaster University, Bob Gruebel, Ken Butler and Theo Powell of Texas
Instruments, M. Renovell and G. Cambon of the Universite des Sciences et
Techniques du Languedoc, Scott Davidson at AT&T, Jim Frenzel ofthe Univer-
sity of Idaho, Jeff Beasley of New Mexico State University, Shobha Mallarapu,
Albert Hoffman, S. Duey, and colleagues from Delco Electronics, and Rinya
Kawahara, Osamu Nakayama, and Tatsuru Kurasawa from Kawasaki Steel.

These collective studies from around the world showed the following. IDDQ is
presently the only practical and guaranteed method of detecting the dominant
defect in IC manufacturing, namely the bridging defect, and certain forms
of CMOS open circuit defects are only detected by IDDQ testing. Several
Foreword Xlll

manufacturers reported that defect levels at next stages of assembly dropped

by factors of 10 to over 100 when IDDQ testing was added to the normal voltage
based IC testing. Advances followed in IDDQ instrumentation and commercial
software tools that would select vectors or generate IDDQ vectors from a netlist.
The targeting of specific defects by IDDQ has led to a defect-based test approach
that also includes those defects detected by voltage based testing. Refinements
are now occurring in optimizing the roles of the various test methods such as
IDDQ, delay fault, at-speed functional, and stuck-at fault testing.

IDDQ testing has a peculiar property of occasionally engaging people in intense

debate. Two items are debated. The first is the implication of the reduced
yield when ICs that fail only the IDDQ test are rejected. This has stimulated
an increase in failure analysis for these classes of defects. The second concern is
what to do about the increase in transistor off-state leakage that accompanies
deep submicron transistors. Several IDDQ design for test approaches are being
studied in response to this challenge.

The original, simple, IDDQ idea that measuring current instead ofvoltage might
produce better test results has extended to other base manufacturing activi-
ties. Studies of large numbers of CMOS ICs have shown that lower reliability
failure rates are achieved if ICs that fail only the IDDQ test are removed from
the population of shipped product. Recent studies have also made progress
in determining under what conditions burn-in can be eliminated when IDDQ
measurements are used as a screen. Millions of dollars in savings and lowered
failure rates are reported.

Failure analysis is another beneficiary of IDDQ measurements. An IC with a sin-

gle defect related leakage path against a low quiescent background of current in
the other paths is significantly easier to failure analyze. Recently, noninvasive
analysis of ICs using IDDQ and voltage based test vectors has been demon-
strated to localize the site of a defect with high probability. This supports a
trend in failure analysis called "lids-on" diagnosis that seeks to identify the
defect site from noninvasive test data.

The authors of this work, Sreejit Chakravarty and Paul Thadikaran, have
blended the best of academic and manufacturing styles. The book is direct
in describing the process, particularly with its emphasis on defect-based test-
ing, IDDQ test pattern generation, and the instrumentation chapter by Ken
Wallquist. The academic discipline is noticeable for its in-depth and painstak-
xiv INTRODUCTION TO I DDQ TESTING

ing work by the authors in review of all relevant literature. They have done a
service for all of us and the result is a book written for any engineer or manager
interested in this intriguing test technique.

Chuck Hawkins
University of New Mexico
 PREFACE

Testing techniques for VLSI circuits are undergoing many exciting changes.
The predomionant method for testing digital circuits consists of applying a set
of input stimuli to the IC and monitoring the logic levels at primary outputs.
If, for one or more inputs, there is a discrepancy between the observed output
and the expected output then the IC is declared to be defective.

A new approach to testing digital circuits, which has come to be known as

IDDQ testing, has been actively researched for the last fifteen years. In IDDQ
testing, the steady state supply current, rather than the logic levels at the pri-
mary outputs, is monitored. Years of research suggests that IDDQ testing can
significantly improve the quality and reliability of fabricated circuits. This has
prompted many semiconductor manufacturers to adopt this testing technique.
Philips Semiconductors, Ford Microelectronics, Intel, Texas Instruments, LSI
Logic, Hewlett-Packard, SUN microsystems, Alcatel, SGS Thomson, are a few
of them.

This increase in the use of IDDQ testing should be of interest to three groups
of individuals associated with the IC business.

Product Managers and Test Engineers. Quality and reliability have im-
portant business implications. Since IDDQ testing can play an important
role in meeting quality and reliability goals, product managers and test
engineers must understand the important issues of IDDQ testing.
CAD Tool Vendors. Since more and more semiconductor manufacturers are
using IDDQ testing to test their products, there is an increase in the need
for Computer Aided Design (CAD) tools for IDDQ testing. This makes it
important for CAD tool vendors to understand the fundamental issues of
IDDQ testing.

Circuit Designers. The advantages of IDDQ testing can best be harnessed if

some design techniques are followed. Another important issue to be ad-
dressed during design is the instrumentation to be used for IDDQ measure-

xv
XVI INTRODUCTION TO I DDQ TESTING

ment. Thus it is important that circuit designers have a good knowledge

of these aspects of IDDQ testing.

The purpose of this book is to educate the community of product managers, test
engineers, designers and CAD tool developers. We have tried to summarize,
under one title, the main findings of more than fifteen years of research in this
area. We tried hard to include all the research contributions but some may
have missed our attention. Our apologies to researchers whose work we may
have missed. We will be grateful if such omissions are brought to our attention.

Besides IDDQ testing this book has another dimension. Testing attempts to de-
tect defective ICs. However, all testing tools use fault models. Defect detection
has been ignored in the context of logic testing. Researchers in IDDQ testing
have paid considerable attention to it. While discussing IDDQ testing we will
study what is known about commonly occuring defects. We will investigate
the correlation between fault models in use and the commonly occuring defect
mechanism. This investigation, which will bring out the inadequacy of fault
models to model defective ICs, will suggest that research in testing ought to
shift focus from fault models to defects. We believe that all educators in testing
owe it to the testing community to train students to think "defects" and not
"fault models". We hope that this book will help you achieve that goal and
help foster research in making testing more "defect-oriented".

We have to thank many of our professional colleagues. First, we thank Carl

Harris of Kluwer Academic Publishers for providing us with the opportunity
to write this book. Dr. Vishwani Agrawal of Bell Labs provided valuable
feedback on the manuscript. Prof. Charles Hawkins of University of New
Mexico deserves special thanks for writing a foreword to the book. His words
of advice on many aspects of the book is greatly appreciated. Ken Wallquist,
of Philips Semiconductors, contributed the chapter on IDDQ monitors. His
industrial experience in building current monitors adds v-ery significantly to the
quality of the book. We are very grateful to him for writing the chapter. The
support from the National Science Foundation, administered by Dr. Robert
Grafton, for our research on IDDQ testing is gratefully acknowledged. We are
grateful to Prof. Janak Patel, University of Illinois at Urbana-Champaign,
for supporting our work during our visit to the Center for Reliable and High-
Performance Computing.

An initial draft of this book was used in a seminar on VLSI testing at the
State University of New York at Buffalo. Graduate students in the seminar
(daringly) pointed out many mistakes in our examples and suggested several
Preface xvii

changes to the manuscript. We thank Vinodh Gopal, Sreenivas Mandava and

Sujit Zachariah for their suggestions and many lively discussion. Our thanks
to Dr. Robert Aitken (HP Design Center, Palo Alto, CA), Dr. Warren Debany
(Rome Laboratories, NY), Prof. Joel Ferguson (UC Santa Cruz, CA) and Prof.
Joan Figueras (UPC, Barcelona, Spain) for their feedback.

Finally, we hope that you will enjoy reading this book and benefit from it as
much as we did.

Sreejit Chakravarty Paul J. Thadikaran

State University of New York Intel Corp.
Buffalo, NY Santa Clara, CA
INTRODUCTION TO
I DDQ TESTING
 1
INTRODUCTION

IDDQ Testing is a modern, high interest testing technique for CMOS digital
ICs whose roots go back to the first CMOS process. We start by understanding
what is meant by IDDQ testing and then briefly address the resurgent moti-
vation for using IDDQ testing. This will lead us into a discussion of why the
conventional method for testing ICs, logic testing, is inadequate. We conclude
this chapter by giving a brief overview of the book.

1.1 WHAT IS IDDQ TESTING?

To answer this question we first explain what fully complementary static
CMOS circuits are. Henceforth the term CMOS is used to refer to this class of
circuits. Next the fundamental idea of IDDQ testing is presented. This section
ends with a brief history of IDDQ testing.

1.1.1 CMOS Circuits

Figure 1.1(a) depicts a NAND gate with two inputs a, b and one output c.
This logic gate is implemented in CMOS using nFETs and pFETs as shown in
Figure 1.1 (b) .

If a and b are both assigned the logic value 1 then the two nFETs conduct
and c is connected to GND. Thus, c is set to logic value O. Note that, for
this assignment of values to inputs, none of the two pFETs conduct and there
is no conducting path from VDD to GND. During steady state (quiescent

1
S. Chakravarty et al., Introduction to I DDQ Testing
© Springer Science+Business Media New York 1997
2 CHAPTER 1

(a)

VDD

INPUTS pFET
(PULLUP)

OUTPUTS

GND
(b)

GND
(e)

Figure 1.1 Static CMOS circuits.

state) current is drawn from the power supply. This quiescent current, from
VDD to GND, is referred to as IDDQ' Only leakage current through the FETs
contributes to IDDQ. Thus, in fault free circuits, IDDQ is very small.

The assignment (a = 0 1 ,b = 1) creates a conducting path from VDD to c, via

the pFET driven by a, and no conducting path from c to GND. Thus, c = 1
and IDDQ is very small.

Make a note of the following important points from this example. As shown
in Figure 1.1(c), every CMOS gate consists of two networks: a pFET network
(pullup) and an nFET network (pulldown). For any assignment of logic
values to the inputs of the gate, in the fault free case, there are conducting
paths either from VDD to the gate output or from the gate output to GND.
Thus, for any input assignment, IDDQ is negligible. This also implies that
power consumption during the quiescent state of CMOS circuits is very small.
1 From now on we drop the phrase "a is assigned logic value 0(1)" and simply use "a = 0(1)"
to denote the same.
INTRODUCTION 3

VDD
-!..q ~
VDD
~ d

~
":" ':"
(a) GND
GND
(b)

i: Steady State
~~
& b
.B e o ..../ : :

~ a -I"'L.L..._..._..._.._.
~, ; Faulty
c "" '

e !\, i Fault Free

! "...~._----------------_.

Time
(c)

Figure 1.2 Example illustrating IDDQ testing.

1.1.2 IDDQ Testing

Consider the circuit in Figure 1.2(a). If (a = 1, b = 0), as explained above, in
the fault free circuit IDDQ is negligible. Consider a defect that causes linesc
and d to be "connected". The switch level circuit is shown in Figure 1.2(b). If
(a = 1, b = 0), paths PI in the pullup network of the NAND gate and P2 in
the pulldown network of the NOT gate create a conducting path from VDD to
GND. Consequently, in the presence of the above fault 'and on application of
(a = 1, b = 0), there will be a large IDDQ. This large IDDQ signals the presence
of a defect in the circuit. That is the basic idea behind IDDQ testing.

The nature of the current waveform is shown in Figure 1.2(c). Note that there is
a transient period when both good and faulty circuits will have high IDD. It is
important that the current measurements be made, after the transients
die down, in the region marked as steady state.
4 CHAPTER 1

To summarize, in IDDQ testing, a set of input vectors is applied to the circuit.

After some preselected vectors, or after each input vector, IDDQ is measured.
If any of the IDDQ measurements register a higher than some expected reading
the circuit is declared to be faulty.

What we discussed above has become known as single threshold IDDQ test-
ing [101, 102]. A related technique, known as current signatures [101, 102]'
also monitors IDDQ. We will discuss it in Section 3.3.

1.2 WHY IDDQ TESTING?

To understand the need for IDDQ testing we have to understand: the limitations
of the conventional testing method, usually referred to as logic testing;
and how IDDQ testing overcomes these limitations. We hasten to add that, our
present knowledge about IDDQ testing suggests that it will not replace logic
testing but will be used in conjunction with it. Here we present, very briefly,
the main points and leave the elaboration to later chapters.

Logic testing assumes that every physical defect can be modeled as a fault
at the logic gate level description of the circuit. In the most widely used form
of logic testing, it is assumed that faults are such that only one line in the
circuit is either permanently stuck-at 0 or 1. This is known as the single line
stuck-at fault model. It is often referred to as the stuck-at fault model.

Stuck-at faults can be detected by an input vector (or a sequence of input vectors
for sequential circuits). For example, in Figure 1.3 assume: line a is stuck-at
o (henceforth abbreviated a s-a-O); and input vector (a = 1,b = 1,e = 0) is
applied. In the presence (absence) of the fault 9 = 1(0). This change in the
logic value at 9 indicates the presence of the fault.

Logic testing consists of computing a set of tests T. Tests used with logic testing
are henceforth referred to as logic tests and the tests used in IDDQ testing are
referred to as IDDQ tests. When logic tests are applied to fabricated chips, the
logic values at the output(s) are monitored. If there is a discrepancy between
the expected logic value at the output(s) of the chip and the observed value,
the chip is declared to be faulty.

If the logic test set T is such that it is computed by targeting stuck-at faults
we refer to the test strategy as stuck-at testing. This is the predominant