Propeller™ P8X32A Datasheet

8-Cog Multiprocessor Microcontroller

1.0 PRODUCT OVERVIEW

1.1. Introduction
The Propeller chip is designed to provide high-speed processing for embedded systems while maintaining low current
consumption and a small physical footprint. In addition to being fast, the Propeller chip provides flexibility and power
through its eight processors, called cogs, that can perform simultaneous tasks independently or cooperatively, all while
maintaining a relatively simple architecture that is easy to learn and utilize. Two programming languages are available: Spin
(a high-level object-based language) and Propeller Assembly. Both include custom commands to easily manage the
Propeller chip’s unique features.
Figure 1: Propeller P8X32A Block Diagram

1.2. Stock Codes

Table 1: Propeller Chip Stock Codes
Device Power External Internal
I/O Internal RC Global
Package Type Clock Execution Cog RAM
Stock # Pins Requirements Oscillator ROM/RAM
Speed Speed
P8X32A-D40 40-pin DIP 64 K bytes;
32 DC to 80 12 MHz or 0 to 160 MIPS 32768 bytes 512 x 32 bits
P8X32A-Q44 44-pin LQFP 3.3 volts DC
CMOS MHz 20 kHz* (20 MIPS/cog) ROM / 32768 per cog
P8X32A-M44 44-pin QFN bytes RAM
*Approximate; may range from 8 MHz – 20 MHz, or 13 kHz – 33 kHz, respectively.

Parallax, Propeller, Spin, and the Parallax and Propeller logos are trademarks of Parallax, Inc. All other trademarks are the property of their respective holders.
Copyright © Parallax Inc. Page 1 of 37 Rev 1.1 9/12/2008
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Table of Contents
5.2. Cog RAM................................................................................. 16
1.0 Product Overview......................................................... 1
1.1. Introduction ................................................................................1 6.0 Programming Languages ..........................................17
1.2. Stock Codes...............................................................................1 6.1. Reserved Word List ................................................................. 17
1.3. Key Features..............................................................................3 6.1.1. Words Reserved for Future Use ......................................................... 17
1.4. Programming Advantages..........................................................3 6.2. Math and Logic Operators ....................................................... 18
1.5. Applications................................................................................3 6.3. Spin Language Summary Table .............................................. 19
1.6. Programming Platform Support..................................................3 6.3.1. Constants ........................................................................................... 21
1.7. Corporate and Community Support............................................3 6.4. Propeller Assembly Instruction Table....................................... 22
6.4.1. Assembly Conditions .......................................................................... 24
2.0 Connection Diagrams .................................................. 4 6.4.2. Assembly Directives ........................................................................... 24
2.1. Pin Assignments ........................................................................4 6.4.3. Assembly Effects ................................................................................ 24
6.4.4. Assembly Operators ........................................................................... 24
2.2. Pin Descriptions .........................................................................4
2.3. Typical Connection Diagrams ....................................................5 7.0 Propeller Demo Board Schematic.............................25
2.3.1. Propeller Clip or Propeller Plug Connection - Recommended...............5
2.3.2. Alternative Serial Port Connection.........................................................5
8.0 Electrical Characteristics...........................................26
3.0 Operating Procedures ................................................. 6 8.1. Absolute Maximum Ratings ..................................................... 26
3.1. Boot-Up Procedure ....................................................................6 8.2. DC Characteristics................................................................... 26
3.2. Run-Time Procedure..................................................................6 8.3. AC Characteristics ................................................................... 26
3.3. Shutdown Procedure..................................................................6
9.0 Current Consumption Characteristics .....................27
4.0 System Organization ................................................... 6 9.1. Typical Current Consumption of 8 Cogs .................................. 27
4.1. Shared Resources .....................................................................6 9.2. Typical Current of a Cog vs. Operating Frequency .................. 28
4.2. System Clock .............................................................................6 9.3. Typical PLL Current vs. VCO Frequency ................................. 28
4.3. Cogs (processors)......................................................................7 9.4. Typical Crystal Drive Current ................................................... 29
4.4. Hub ............................................................................................7 9.5. Cog and I/O Pin Relationship................................................... 29
4.5. I/O Pins ......................................................................................8 9.6. Current Profile at Various Startup Conditions .......................... 30
4.6. System Counter .........................................................................8
4.7. Locks .........................................................................................8
10.0 Temperature Characteristics.....................................31
10.1. Internal Oscillator Frequency as a Function of Temperature.... 31
4.8. Assembly Instruction Execution Stages .....................................9
10.2. Fastest Operating Frequency as a Function of Temperature ... 32
4.9. Cog Counters...........................................................................10
4.9.1. CTRA / CTRB – Control register .........................................................10 10.3. Current Consumption as a Function of Temperature ............... 33
4.9.2. FRQA / FRQB – Frequency register....................................................10
4.9.3. PHSA / PHSB – Phase register...........................................................10 11.0 Package Dimensions..................................................34
4.10. Video Generator.......................................................................11 11.1. P8X32A-D40 (40-pin DIP)........................................................ 34
4.10.1. VCFG – Video Configuration Register.................................................11 11.2. P8X32A-Q44 (44-pin LQFP) .................................................... 35
4.10.2. VSCL – Video Scale Register..............................................................12 11.3. P8X32A-M44 (44-pin QFN)...................................................... 35
4.10.3. WAITVID Command/Instruction ..........................................................12
4.11. CLK Register............................................................................14 12.0 Manufacturing Info .....................................................37
12.1. Reflow Peak Temperature ....................................................... 37
5.0 Memory Organization ................................................ 15 12.2. Green/RoHS Compliance ........................................................ 37
5.1. Main Memory ...........................................................................15
5.1.1. Main RAM............................................................................................15 13.0 Revision History .........................................................37
5.1.2. Main ROM ...........................................................................................15 13.1.1. Changes for Version 1.1: .................................................................... 37
5.1.3. Character Definitions...........................................................................15
5.1.4. Math Function Tables..........................................................................16

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1.3. Key Features

1.6. Programming Platform Support
The design of the Propeller chip frees application
developers from common complexities of embedded Parallax Inc. supports the Propeller chip with a variety of
systems programming. For example: hardware tools and boards:
• Eight processors (cogs) perform simultaneous • Propeller Clip (#32200) and Propeller Plug
processes independently or cooperatively, sharing (#32201). These boards provide convenient
common resources through a central hub. The programming port connections, see the Typical
Propeller application designer has full control over Connection Diagrams on Page 5.
how and when each cog is employed; there is no • The Propeller Demo Board (#32100) provides a
compiler-driven or operating system-driven splitting convenient means to test-drive the Propeller chip's
of tasks among multiple cogs. This method varied capabilities through a host of device
empowers the developer to deliver absolutely interfaces on one compact board. The schematic is
deterministic timing, power consumption, and provided on page 25. Main features:
response to the embedded application. o P8X32A-Q44 Propeller Chip
• Asynchronous events are easier to handle than with o 24LC256-I/ST EEPROM for program storage
devices that use interrupts. The Propeller has no o Replaceable 5.000 MHz crystal
need for interrupts; just assign some cogs to o 3.3 V and 5 V regulators with on/off switch
individual, high-bandwidth tasks and keep other o USB-to-serial interface for programming and
cogs free and unencumbered. The result is a more communication
responsive application that is easier to maintain. o VGA and TV output
• A shared System Clock allows each cog to maintain o Stereo output with 16 Ω headphone amplifier
the same time reference, allowing true synchronous o Electret microphone input
execution. o Two PS/2 mouse and keyboard I/O connectors
o 8 LEDs (share VGA pins)
1.4. Programming Advantages o Pushbutton for reset
o Big ground post for scope hookup
• The object-based high-level Spin language is easy to o I/O pins P0-P7 are free and brought out to header
learn, with special commands that allow developers o Breadboard for custom circuits
to quickly exploit the Propeller chip’s unique and • The Propeller Proto Board (#32212) features a
powerful features. surface-mount Propeller chip with the necessary
• Propeller Assembly instructions provide conditional components to achieve a programming interface,
execution and optional flag and result writing for with pads ready for a variety of I/O connectors and
each individual instruction. This makes critical, DIP/SIP chips, and a generous through-hole
multi-decision blocks of code more consistently prototyping area.
timed; event handlers are less prone to jitter and • The PropStick USB (#32210) features a Propeller
developers spend less time padding, or squeezing, chip, EEPROM, 3.3 VDC and 5 VDC regulators,
cycles. reset button, crystal and USB connection on a 0.6”
wide DIP package for easy prototyping on perfboard
1.5. Applications and breadboard.
The Propeller chip is particularly useful in projects that
can be vastly simplified with simultaneous processing, 1.7. Corporate and Community Support
including: • Parallax provides technical support free of charge.
• Industrial control systems In the Continental US, call toll free (888) 512-1024;
• Sensor integration, signal processing, and data from outside please call (916) 624-8333. Or, email:
acquisition support@parallax.com.
• Handheld portable human-interface terminals • Parallax hosts a moderated public user’s forum just
• Motor and actuator control for the Propeller: http://forums.parallax.com/forums.
• User interfaces requiring NTSC, PAL, or VGA • Browse through community-created Propeller
output, with PS/2 keyboard and mouse input objects and share yours with others via Parallax-
• Low-cost video game systems hosted Propeller Object Exchange Library:
• Industrial, educational or personal-use robotics http://obex.parallax.com.
• Wireless video transmission (NTSC or PAL)

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2.0 CONNECTION DIAGRAMS

2.1. Pin Assignments

LQFP and QFN Packages

DIP Package

2.2. Pin Descriptions

Table 2: Pin Descriptions
Pin Name Direction Description
General purpose I/O Port A. Can source/sink 40 mA each at 3.3 VDC. CMOS level logic with threshold
of ≈ ½ VDD or 1.6 VDC @ 3.3 VDC.

The pins shown below have a special purpose upon power-up/reset but are general purpose I/O
P0 – P31 I/O afterwards.
P28 - I2C SCL connection to optional, external EEPROM.
P29 - I2C SDA connection to optional, external EEPROM.
P30 - Serial Tx to host.
P31 - Serial Rx from host.

VDD --- 3.3 volt power (2.7 – 3.6 VDC)

VSS --- Ground

Brown Out Enable (active low). Must be connected to either VDD or VSS. If low, RESn becomes a
BOEn I weak output (delivering VDD through 5 kΩ) for monitoring purposes but can still be driven low to cause
reset. If high, RESn is CMOS input with Schmitt Trigger.
Reset (active low). When low, resets the Propeller chip: all cogs disabled and I/O pins floating.
RESn I/O
Propeller restarts 50 ms after RESn transitions from low to high.
Crystal Input. Can be connected to output of crystal/oscillator pack (with XO left disconnected), or to
XI I one leg of crystal (with XO connected to other leg of crystal or resonator) depending on CLK Register
settings. No external resistors or capacitors are required.
Crystal Output. Provides feedback for an external crystal, or may be left disconnected depending on
XO O
CLK Register settings. No external resistors or capacitors are required.

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2.3. Typical Connection Diagrams

2.3.1. Propeller Clip or Propeller Plug Connection - Recommended
Note that the connections to the external oscillator and EEPROM, which are enclosed in dashed lines, are optional.
Propeller Clip, Stock #32200; Propeller Plug, Stock #32201. The Propeller Clip/Plug schematic is available for download
from www.parallax.com.

2.3.2. Alternative Serial Port Connection

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3.0 OPERATING PROCEDURES

I/O pin usage, configuration registers, and when, what
3.1. Boot-Up Procedure and how many cogs are running at any given time. All of
Upon power-up, or reset: this is variable at run time, as controlled by the
1. The Propeller chip’s internal RC oscillator begins application.
running at 20 kHz, then after a 50 ms reset delay,
switches to 12 MHz. Then the first processor (Cog 0) 3.3. Shutdown Procedure
loads and runs the built-in Boot Loader program. When the Propeller goes into shutdown mode, the internal
2. The Boot Loader performs one or more of the clock is stopped causing all cogs to halt and all I/O pins
following tasks, in order: are set to input direction (high impedance). Shutdown
mode is triggered by one of the three following events:
a. Detects communication from a host, such as a
PC, on pins P30 and P31. If communication 1. VDD falling below the brown-out threshold (~2.7
from a host is detected, the Boot Loader VDC), when the brown out circuit is enabled,
converses with the host to identify the Propeller 2. the RESn pin going low, or
chip and possibly download a program into 3. the application requests a reboot (see the REBOOT
global RAM and optionally into an external 32 command in the Propeller Manual).
KB EEPROM.
Shutdown mode is discontinued when the voltage level
b. If no host communication was detected, the Boot rises above the brown-out threshold and the RESn pin is
Loader looks for an external 32 KB EEPROM on high.
pins P28 and P29. If an EEPROM is detected,
the entire 32 KB data image is loaded into the
Propeller chip’s global RAM. 4.0 SYSTEM ORGANIZATION
c. If no EEPROM was detected, the boot loader
4.1. Shared Resources
stops, Cog 0 is terminated, the Propeller chip
goes into shutdown mode, and all I/O pins are set There are two types of shared resources in the Propeller:
to inputs. 1) common, and 2) mutually-exclusive. Common
resources can be accessed at any time by any number of
3. If either step 2a or 2b was successful in loading a
cogs. Mutually-exclusive resources can also be accessed
program into the global RAM, and a suspend
by any number of cogs, but only by one cog at a time.
command was not given by the host, then Cog 0 is
The common resources are the I/O pins and the System
reloaded with the built-in Spin Interpreter and the
Counter. All other shared resources are mutually-
user code is run from global RAM.
exclusive by nature and access to them is controlled by
the Hub. See Section 4.4 on page 7.
3.2. Run-Time Procedure
A Propeller Application is a user program compiled into 4.2. System Clock
its binary form and downloaded to the Propeller chip’s
The System Clock (shown as “CLOCK” in Figure 1, page
RAM or external EEPROM. The application consists of
1) is the central clock source for nearly every component
code written in the Propeller chip’s Spin language (high-
of the Propeller chip. The System Clock’s signal comes
level code) with optional Propeller Assembly language
from one of three possible sources:
components (low-level code). Code written in the Spin
language is interpreted during run time by a cog running • The internal RC oscillator (~12 MHz or ~20 kHz)
the Spin Interpreter while code written in Propeller • The XI input pin (either functioning as a high-
Assembly is run in its pure form directly by a cog. Every impedance input or a crystal oscillator in
Propeller Application consists of at least a little Spin code conjunction with the XO pin)
and may actually be written entirely in Spin or with • The Clock PLL (phase-locked loop) fed by the XI
various amounts of Spin and assembly. The Propeller input
chip’s Spin Interpreter is started in Step 3 of the Boot Up The source is determined by the CLK register’s settings,
Procedure, above, to get the application running. which is selectable at compile time and reselectable at run
Once the boot-up procedure is complete and an time. The Hub and internal Bus operate at half the
application is running in Cog 0, all further activity is System Clock speed.
defined by the application itself. The application has
complete control over things like the internal clock speed,

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It takes up to 15 cycles (16 minus 1, if we just missed it)

4.3. Cogs (processors) to synchronize to the Hub Access Window plus 7 cycles
The Propeller contains eight (8) identical, independent to execute the hub instruction, so hub instructions take
processors, called cogs, numbered 0 to 7. Each cog from 7 to 22 cycles to complete.
contains a Processor block, local 2 KB RAM configured Figure 2 and Figure 3 show examples where Cog 0 has a
as 512 longs (512 x 32 bits), two advanced counter hub instruction to execute. Figure 2 shows the best-case
modules with PLLs, a Video Generator, I/O Output scenario; the hub instruction was ready right at the start of
Register, I/O Direction Register, and other registers not that cog’s access window. The hub instruction executes
shown in the Block Diagram. immediately (7 cycles) leaving an additional 9 cycles for
All eight cogs are driven from the System Clock; they other instructions before the next Hub Access Window
each maintain the same time reference and all active cogs arrives.
execute instructions simultaneously. They also all have Figure 3 shows the worst-case scenario; the hub
access to the same shared resources. instruction was ready on the cycle right after the start of
Cogs can be started and stopped at run time and can be Cog 0’s access window; it just barely missed it. The cog
programmed to perform tasks simultaneously, either waits until the next Hub Access Window (15 cycles later)
independently or with coordination from other cogs then the hub instruction executes (7 cycles) for a total of
through Main RAM. Each cog has its own RAM, called 22 cycles for that hub instruction. Again, there are 9
Cog RAM, which contains 512 registers of 32 bits each. additional cycles after the hub instruction for other
The Cog RAM is all general purpose RAM except for the instructions to execute before the next Hub Access
last 16 registers, which are special purpose registers, as Window arrives. To get the most efficiency out of
described in Table 15 on page 16. Propeller Assembly routines that have to frequently
access mutually-exclusive resources, it can be beneficial
4.4. Hub to interleave non-hub instructions with hub instructions to
lessen the number of cycles waiting for the next Hub
To maintain system integrity, mutually-exclusive
Access Window. Since most Propeller Assembly
resources must not be accessed by more than one cog at a
instructions take 4 clock cycles, two such instructions can
time. The Hub controls access to mutually-exclusive
be executed in between otherwise contiguous hub
resources by giving each cog a turn in a “round robin”
instructions.
fashion from Cog 0 through Cog 7 and back to Cog 0
again. The Hub and its bus run at half the System Clock Keep in mind that a particular cog’s hub instructions do
rate, giving a cog access to mutually-exclusive resources not, in any way, interfere with other cogs’ instructions
once every 16 System Clock cycles. Hub instructions, the because of the Hub mechanism. Cog 1, for example, may
Propeller Assembly instructions that access mutually- start a hub instruction during System Clock cycle 2, in
exclusive resources, require 7 cycles to execute but they both of these examples, possibly overlapping its execution
first need to be synchronized to the start of the Hub with that of Cog 0 without any ill effects. Meanwhile, all
Access Window. other cogs can continue executing non-hub instructions,
or awaiting their individual hub access windows
regardless of what the others are doing.

Figure 2: Cog-Hub
Interaction – Best Case
Scenario

Figure 3: Cog-Hub
Interaction – Worst Case
Scenario

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4.5. I/O Pins

The Propeller has 32 I/O pins, 28 of which are general A. A pin is an input only if no active cog sets it to
purpose. I/O Pins 28 - 31 have a special purpose at boot an output.
up and are available for general purpose use afterwards; B. A pin outputs low only if all active cogs that set
see section 2.2, page 4. After boot up, any I/O pins can it to output also set it to low.
be used by any cogs at any time. It is up to the C. A pin outputs high if any active cog sets it to an
application developer to ensure that no two cogs try to use output and also sets it high.
the same I/O pin for different purposes during run time. Table 3 demonstrates a few possible combinations of the
Each cog has its own 32-bit I/O Direction Register and collective cogs’ influence on a particular I/O pin, P12 in
32-bit I/O Output Register. The state of each cog’s this example. For simplification, these examples assume
Direction Register is OR’d with that of the previous cogs’ that bit 12 of each cog’s I/O hardware, other than its I/O
Direction Registers, and each cog’s output states is OR’d Output Register, is cleared to zero (0).
with that of the previous cogs’ output states. Note that Any cog that is shut down has its Direction Register and
each cog’s output states are made up of the OR’d states of output states cleared to zero, effectively removing it from
its internal I/O hardware and that is all AND’d with its influencing the final state of the I/O pins that the
Direction Register’s states. The result is that each I/O remaining active cogs are controlling.
pin’s direction and output state is the “wired-OR” of the Each cog also has its own 32-bit Input Register. This
entire cog collective. No electrical contention between input register is really a pseudo-register; every time it is
cogs is possible, yet they can all still access the I/O pins read, the actual states of the I/O pins are read, regardless
simultaneously. The result of this I/O pin wiring of their input or output direction.
configuration can be described in the following rules:

Table 3: I/O Sharing Examples

Bit 12 of Cogs’ I/O Direction Register Bit 12 of Cogs’ I/O Output Register State of Rule
Cog ID 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 I/O Pin P12 Followed

Example 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Input A
Example 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Output Low B
Example 3 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Output High C
Example 4 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Output Low B
Example 5 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Output High C
Example 6 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 Output High C
Example 7 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 Output High C
Example 8 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 0 Output Low B
Note: For the I/O Direction Register, a 1 in a bit location sets the corresponding I/O pin to the output direction; a 0 sets it to an input direction.

4.6. System Counter 4.7. Locks

The System Counter is a global, read-only, 32-bit counter There are eight lock bits (semaphores) available to
that increments once every System Clock cycle. Cogs can facilitate exclusive access to user-defined resources
read the System Counter (via their CNT registers, see among multiple cogs. If a block of memory is to be used
Table 15 on page 16) to perform timing calculations and by two or more cogs at once and that block consists of
can use the WAITCNT command (see section 6.3 on page more than one long (four bytes), the cogs will each have
19 and section 6.4 on page 22) to create effective delays to perform multiple reads and writes to retrieve or update
within their processes. The System Counter is a common that memory block. This leads to the likely possibility of
resource which every cog can read simultaneously. The read/write contention on that memory block where one
System Counter is not cleared upon startup since its cog may be writing while another is reading, resulting in
practical use is for differential timing. If a cog needs to misreads and/or miswrites.
keep track of time from a specific, fixed moment in time, The locks are global bits accessed through the Hub via
it simply needs to read and save the initial counter value LOCKNEW, LOCKRET, LOCKSET, and LOCKCLR. Because
at that moment in time, and compare subsequent counter locks are accessed only through the Hub, only one cog at
values against that initial value. a time can affect them, making this an effective control
mechanism. The Hub maintains an inventory of which
locks are in use and their current states; cogs can check
out, return, set, and clear locks as needed during run time.

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4.8. Assembly Instruction Execution Stages

Figure 4: Assembly Instruction Execution Stages

Stage 1 2 3 4 5

(Execute N- 1) (Execute N)
Fetch Write Fetch Fetch Fetch Write
Instruction Result Source Destination Instruction Result
N N-1 N N N+1 N

clock cycle M M+1 M+2 M+3 M+4 M+5

The Propeller executes assembly instructions in five accessed by instruction N. To speed up the throughput of
stages. While an entire instruction takes six cycles to program execution, the next instruction to be executed is
execute, two of those clock cycles are dedicated to the fetched from cog memory while the current instruction is
two adjacent instructions. This results in an overall executed in the ALU.
throughput of four clock cycles per instruction. Finally at clock cycle M+5 the result of the current
instruction N is written back to cog memory, completing
Stage 5.
The partial interleaving of instructions has a couple
implications to program flow. First, when code
Instruction N-1
Figure 5 Program
modification occurs through MOVI, MOVS, MOVD or any
Instruction N operations which modifies an assembly instruction, there
Cog Memory counter
Instruction N+1 must be at least one instruction executed before the
modified instruction is executed. If the modification is
done on the immediately following instruction (N+1), the
unmodified version of instruction N+1 will be loaded a
clock cycle before the modified version of instruction
In Stage 1, instruction N, pointed to by the Program N+1 is written to cog memory.
Counter, is fetched from cog memory during clock cycle Second, conditional jumps do not know for certain if they
M. During cycle M+1 the result from the previous will jump until the end of clock cycle M+4. Since the next
instruction is written to memory. The reason the previous instruction has already been fetched, only one of the two
instruction result is written after the current instruction is possible branches can be predicted. In the Propeller,
fetched will be explained shortly. conditional branches are always predicted to take the
During Stage 2, if the immediate flag of Instruction N is jump. For loops using DJNZ where the jump is taken every
set, the 9 bit source field is saved as the source value. If time except the final loop, a tighter execution time of the
the value is not immediate, the location specified by the loop is achieved.
source field is fetched from cog memory during clock In the event the jump is not taken, the cog takes no action
cycle M+2. During clock cycle M+3 the location until the next instruction is fetched. This is equivalent to a
specified in the destination field is fetched from cog NOP being inserted before the next instruction is executed.
memory (Stage 3). Unconditional jumps always take four clock cycles to
At this point in time (Stage 4) the Arithmetic Logic Unit execute since the Propeller can always accurately predict
(ALU) has all the information needed to execute the what address needs to be loaded into the Program Counter
instruction. Executing the instruction takes some amount for the next instruction to execute. Examples of
of time before the result is available. The amount of time unconditional jumps include JMP, JMPRET, CALL and RET.
required for execution is dictated by the slowest operation If an instruction needs to access any Hub resource, Stage
the ALU performs. To provide enough time for the ALU 4 is extended until the Hub becomes available, increasing
to execute the instruction, a full clock cycle (M+4) is execution time to at least 7 and potentially up to 22 clock
provided to the ALU for the result to settle into its final cycles. See Section 4.4: Hub on page 7.
state. During this execution, the cog memory is not

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4.9. Cog Counters

Each cog has two counter modules: CTRA and CTRB. Each The CTRMODE field selects one of 32 operating modes
counter module can control or monitor up to two I/O pins for the counter, conveniently written (along with
and perform conditional 32-bit accumulation of its FRQ PLLDIV) using the MOVI instruction. These modes of
register into its PHS register on every clock cycle. operation are listed in Table 6 on page 11.
Each counter module also has its own phase-locked loop
(PLL) which can be used to synthesize frequencies up to
Table 5: PLLDIV Field
128 MHz.
With a little setup or oversight from the cog, a counter can PLLDIV %000 %001 %010 %011 %100 %101 %110 %111
be used for: VCO VCO VCO VCO VCO VCO VCO VCO
Output
128 64 32 16 8 4 2 1
• frequency synthesis
• frequency measurement
• pulse counting PLLDIV selects a PLL output tap and may be ignored if
• pulse measurement not used.
• multi-pin state measurement The PLL modes (%00001 to %00011) cause FRQ-to-PHS
• pulse-width modulation accumulation to occur every clock cycle. This creates a
• duty-cycle measurement numerically-controlled oscillator (NCO) in PHS[31],
• digital-to-analog conversion which feeds the counter PLL's reference input. The PLL
• analog-to-digital conversion will multiply this frequency by 16 using its voltage-
controlled oscillator (VCO). For stable operation, it is
recommended that the VCO frequency be kept within 64
For some of these operations, the cog can be set up and
MHz to 128 MHz. This translates to an NCO frequency of
left in a free-running mode. For others, it may use
4 MHz to 8 MHz.
WAITCNT to time-align counter reads and writes within a
loop, creating the effect of a more complex state machine. The PLLDIV field of the CTR register selects which
power-of-two division of the VCO frequency will be used
Note that for a cog clock frequency of 80 MHz, the
as the final PLL output. This affords a PLL range of 500
counter update period is a mere 12.5 ns. This high speed,
kHz to 128 MHz.
combined with 32-bit precision, allows for very dynamic
signal generation and measurement. BPIN selects a pin to be the secondary I/O. It may be
ignored if not used and may be written using the MOVD
The design goal for the counter was to create a simple and
instruction.
flexible subsystem which could perform some repetitive
task on every clock cycle, thereby freeing the cog to APIN selects a pin to be the primary I/O. It may be
perform some computationally richer super-task. While ignored if not used and may be written using the MOVS
the counters have only 32 basic operating modes, there is instruction.
no limit to how they might be used dynamically through
4.9.2. FRQA / FRQB – Frequency register
software. Integral to this concept is the use of the
WAITPEQ, WAITPNE, and WAITCNT instructions, which can FRQ (FRQA and FRQB) holds the value that will be
event-align or time-align a cog with its counters. accumulated into the PHS register. For some applications,
FRQ may be written once, and then ignored. For others, it
Each counter has three registers:
may be rapidly modulated.
4.9.1. CTRA / CTRB – Control register
4.9.3. PHSA / PHSB – Phase register
The CTR (CTRA and CTRB) register selects the counter's
The PHS (PHSA and PHSB) register can be written and
operating mode. As soon as this register is written, the
read via cog instructions, but it also functions as a free-
new operating mode goes into effect. Writing a zero to
running accumulator, summing the FRQ register into
CTR will immediately disable the counter, stopping all
itself on potentially every clock cycle. Any instruction
pin output and PHS accumulation.
writing to PHS will override any accumulation for that
clock cycle. PHS can only be read through the source
Table 4: CTRA and CTRB Registers operand (same as PAR, CNT, INA, and INB). Beware
31 30..26 25..23 22..15 14..9 8..6 5..0 that doing a read-modify-write instruction on PHS, like
"ADD PHSA, #1", will cause the last-written value to be
- CTRMODE PLLDIV - BPIN - APIN
used as the destination operand input, rather than the
current accumulation.

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Table 6: Counter Modes (CTRMODE Field Values)

Accumulate APIN BPIN
CTRMODE Description
FRQx to PHSx Output* Output*
%00000 Counter disabled (off) 0 (never) 0 (none) 0 (none)
%00001 PLL internal (video mode) 1 (always) 0 0
%00010 PLL single-ended 1 PLLx 0
%00011 PLL differential 1 PLLx !PLLx
%00100 NCO single-ended 1 PHSx[31] 0
%00101 NCO differential 1 PHSx[31] !PHSx[31]
%00110 DUTY single-ended 1 PHSx-Carry 0
%00111 DUTY differential 1 PHSx-Carry !PHSx-Carry
1
%01000 POS detector A 0 0
1
%01001 POS detector with feedback A 0 !A1
1 2
%01010 POSEDGE detector A & !A 0 0
1 2
%01011 POSEDGE detector w/ feedback A & !A 0 !A1
1
%01100 NEG detector !A 0 0
1
%01101 NEG detector with feedback !A 0 !A1
1 2
%01110 NEGEDGE detector !A & A 0 0
1 2
%01111 NEGEDGE detector w/ feedback !A & A 0 !A1
%10000 LOGIC never 0 0 0
1 1
%10001 LOGIC !A & !B !A & !B 0 0
1 1
%10010 LOGIC A & !B A & !B 0 0
1
%10011 LOGIC !B !B 0 0
1 1
%10100 LOGIC !A & B !A & B 0 0
1
%10101 LOGIC !A !A 0 0
1 1
%10110 LOGIC A <> B A <> B 0 0
1 1
%10111 LOGIC !A | !B !A | !B 0 0
1 1
%11000 LOGIC A & B A &B 0 0
1 1
%11001 LOGIC A == B A == B 0 0
1
%11010 LOGIC A A 0 0
1 1
%11011 LOGIC A | !B A | !B 0 0
1
%11100 LOGIC B B 0 0
1 1
%11101 LOGIC !A | B !A | B 0 0
1 1
%11110 LOGIC A | B A |B 0 0
%11111 LOGIC always 1 0 0
*Must set corresponding DIR bit to affect pin. A1 = APIN input delayed by 1 clock. A2 = APIN input delayed by 2 clocks. B1 = BPIN input delayed by 1 clock.

4.10. Video Generator

Each cog has a video generator module that facilitates Video Configuration Register, then finally providing data
transmitting video image data at a constant rate. There are via the WAITVID instruction. Failure to properly initialize
two registers and one instruction which provide control the Video Generator by first starting PLLA will cause the
and access to the video generator. Counter A of the cog cog to indefinitely hang when the WAITVID instruction is
must be running in a PLL mode and is used to generate executed.
the timing signal for the Video Generator. The Video
Scale Register specifies the number of Counter A PLL 4.10.1. VCFG – Video Configuration Register
(PLLA) clock cycles for each pixel and number of clock The Video Configuration Register contains the
cycles before fetching another frame of data provided by configuration settings of the video generator and is shown
the WAITVID instruction which is executed within the cog. in Table 7.
The Video Configuration Register establishes the mode In Propeller Assembly, the VMode through AuralSub
the Video Generator should operate, and can generate fields can conveniently be written using the MOVI
VGA or composite video (NTSC or PAL). instruction, the VGroup field can be written with the MOVD
The Video Generator should be initialized by first starting instruction, and the VPins field can be written with the
Counter A, setting the Video Scale Register, setting the MOVS instruction.

Table 7: VCFG Register

31 30..29 28 27 26 25..23 22..12 11..9 8 7..0

- VMode CMode Chroma1 Chroma0 AuralSub - VGroup - VPins

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The 2-bit VMode (video mode) field selects the type and The VPins (video output pins) field is a mask applied to
orientation of video output, if any, according to Table 8. the pins of VGroup that indicates which pins to output
video signals on.
Table 8: The Video Mode Field
Table 11: The VPins Field
VMode Video Mode
VPins Effect
00 Disabled, no video generated. Drive Video on lower 4 pins only; composite
00001111
01 VGA mode; 8-bit parallel output on VPins 7:0 11110000 Drive Video on upper 4 pins only; composite
Composite Mode 1; broadcast on VPins 7:4, baseband 11111111 Drive video on all 8 pins; VGA
10
on VPins 3:0 Any value is valid for this field; the above
XXXXXXXX
Composite Mode 2; baseband on VPins 7:4, broadcast values are the most common.
11
on VPins 3:0

The CMode (color mode) field selects two or four color 4.10.2. VSCL – Video Scale Register
mode. 0 = two-color mode; pixel data is 32 bits by 1 bit The Video Scale Register sets the rate at which video data
and only colors 0 or 1 are used. 1 = four-color mode; is generated, and is shown in Table 12.
pixel data is 16 bits by 2 bits, and colors 0 through 3 are
used.
Table 12: VSCL Register
The Chroma1 (broadcast chroma) bit enables or disables
VSCL Bits
chroma (color) on the broadcast signal. 0 = disabled, 1 =
enabled. 31..20 19..12 11..0

The Chroma0 (baseband chroma) bit enables or disables − PixelClocks FrameClocks

chroma (color) on the baseband signal. 0 = disabled, 1 =
enabled. The 8-bit PixelClocks field indicates the number of clocks
The AuralSub (aural sub-carrier) field selects the source per pixel; the number of clocks that should elapse before
of the FM aural (audio) sub-carrier frequency to be each pixel is shifted out by the video generator module.
modulated on. The source is the PLLA of one of the These clocks are the PLLA clocks, not the System Clock.
cogs, identified by AuralSub’s value. This audio must A value of 0 for this field is interpreted as 256.
already be modulated onto the 4.5 MHz sub-carrier by the The 12-bit FrameClocks field indicates the number of
source PLLA. clocks per frame; the number of clocks that will elapse
before each frame is shifted out by the video generator
Table 9: The AuralSub Field module. These clocks are the PLLA clocks, not the
AuralSub Sub-Carrier Frequency Source
System Clock. A frame is one long of pixel data
(delivered via the WAITVID command). Since the pixel
000 Cog 0’s PLLA
data is either 16 bits by 2 bits, or 32 bits by 1 bit (meaning
001 Cog 1’s PLLA 16 pixels wide with 4 colors, or 32 pixels wide with 2
010 Cog 2’s PLLA colors, respectively), the FrameClocks is typically 16 or
011 Cog 3’s PLLA 32 times that of the PixelClocks value. A value of 0 for
100 Cog 4’s PLLA this field is interpreted as 4096.
101 Cog 5’s PLLA
4.10.3. WAITVID Command/Instruction
110 Cog 6’s PLLA
The WAITVID instruction is the delivery mechanism for
111 Cog 7’s PLLA data to the cog’s Video Generator hardware. Since the
Video Generator works independently from the cog itself,
The VGroup (video output pin group) field selects which the two must synchronize each time data is needed for the
group of 8 I/O pins to output video on. display device. The frequency at which this occurs is
dictated by the frequency of PLLA and the Video Scale
Register. The cog must have new data available before the
Table 10: The VGroup Field moment the Video Generator needs it. The cog uses
VGroup Pin Group WAITVID to wait for the right time and then “hand off”
000 Group 0: P7..P0 this data to the Video Generator.
001 Group 1: P15..P8 Two longs of data are passed to the Video Generator by
010 Group 2: P23..P16 with the syntax WAITVID Colors, Pixels.
011 Group 3: P31..P24 The Colors parameter is a 32-bit value containing either
100-111 <reserved for future use> four 8-bit color values (for 4 color mode) or two 8-bit
color values in the lower 16 bits (for 2 color mode). For

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VGA mode, each 8-bit color value is written to the pins When the FrameClocks value is greater than 16 times the
specified by the VGroup and VPins field. For VGA PixelClocks value and 4-color mode is specified, the two
typically the 8 bits are grouped into 2 bits per primary most significant bits are repeated until FrameClocks
color and Horizontal and Vertical Sync control lines, but PLLA cycles have occurred. When FrameClocks value is
this is up to the software and application of how these bits greater than 32 times PixelClocks value and 2-color mode
are used. For composite video each 8-bit color value is is specified, the most significant bit is repeated until
composed of 3 fields. Bits 0-2 are the luminance value of FrameClocks PLLA cycles have occurred. When
the generated signal. Bit 3 is the modulation bit which FrameClocks cycles occur and the cog is not in a WAITVID
dictates whether the chroma information will be generated instruction, whatever data is on the source and destination
and bits 4-7 indicate the phase angle of the chroma value. busses at the time will be fetched and used. So it is
When the modulation bit is set to 0, the chroma important to be in a WAITVID instruction before this
information is ignored and only the luminance value is occurs.
output to pins. When the modulation bit is set to 1 the While the Video Generator was created to display video
luminance value is modulated ± 1 with a phase angle set signals, its potential applications are much more diverse.
by bits 4-7. In order to achieve the full resolution of the The Composite Video mode can be used to generate
chroma value, PLLA should be set to 16 times the phase-shift keying communications of a granularity of 16
modulation frequency (in composite video this is called or less and the VGA mode can be used to generate any bit
the color-burst frequency). The PLLB of the cog is used pattern with a fully settable and predictable rate.
to generate the broadcast frequency; whether this is
Figure 6 is a block diagram of how the VGA mode is
generated depends on if PLLB is running and the values
organized. The two inverted triangles are the load
of VMode and VPins.
mechanism for Pixels and Colors; n is 1 or 2 bits
The Pixels parameter describes the pixel pattern to depending on the value of CMode. The inverted trapezoid
display, either 16 pixels or 32 pixels depending on the is a 4-way 8-bit multiplexer that chooses which byte of
color depth configuration of the Video Generator. When Colors to output. When in composite video mode the
four-color mode is specified, Pixels is a 16x2 bit pattern Modulator transforms the byte into the luminance and
where each 2-bit pixel is an index into Colors on which chroma signal and outputs the broadcast signal. VGroup
data pattern should be presented to the pins. When two- steers the 8 bits to a block of output pins and outputs to
color mode is specified, Pixels is a 32x1 bit pattern where those pins which are set to 1 in VPins; this combined
each bit specifies which of the two color patterns in the functionality is represented by the hexagon.
lower 16 bits of Colors should be output to the pins. The
Pixel data is shifted out least significant bits (LSB) first.

Figure 6: Video Generator

Source Destination

PLLA/FrameClocks
n
Colors
Pixels 3 2 1 0
n
Shift by n
PLLA/PixelClocks

8 Modulator

VGroup VPins

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Use Spin's CLKSET command when possible (see sections

4.11. CLK Register 6.3 and 6.4) since it automatically updates all the above-
The CLK register is the System Clock configuration mentioned locations with the proper information.
control; it determines the source and characteristics of the Table 13: Valid Clock Modes
System Clock. It configures the RC Oscillator, Clock
PLL, Crystal Oscillator, and Clock Selector circuits (See Valid Expression CLK Reg. Value Valid Expression CLK Reg. Value
the Block Diagram, page 1). It is configured at compile RCFAST 0_0_0_00_000 XTAL1 + PLL1X 0_1_1_01_011
time by the _CLKMODE declaration and is writable at run XTAL1 + PLL2X 0_1_1_01_100
RCSLOW 0_0_0_00_001 XTAL1 + PLL4X 0_1_1_01_101
time through the CLKSET command. Whenever the CLK XTAL1 + PLL8X 0_1_1_01_110
register is written, a global delay of ~75 µs occurs as the XINPUT 0_0_1_00_010 XTAL1 + PLL16X 0_1_1_01_111
clock source transitions. XTAL2 + PLL1X 0_1_1_10_011
XTAL1 0_0_1_01_010 XTAL2 + PLL2X 0_1_1_10_100
Whenever this register is changed, a copy of the value XTAL2 0_0_1_10_010 XTAL2 + PLL4X 0_1_1_10_101
written should be placed in the Clock Mode value XTAL3 0_0_1_11_010 XTAL2 + PLL8X 0_1_1_10_110
location (which is BYTE[4] in Main RAM) and the XTAL2 + PLL16X 0_1_1_10_111
resulting master clock frequency should be written to the XINPUT + PLL1X 0_1_1_00_011 XTAL3 + PLL1X 0_1_1_11_011
XINPUT + PLL2X 0_1_1_00_100 XTAL3 + PLL2X 0_1_1_11_100
Clock Frequency value location (which is LONG[0] in XINPUT + PLL4X 0_1_1_00_101 XTAL3 + PLL4X 0_1_1_11_101
Main RAM) so that objects which reference this data will XINPUT + PLL8X 0_1_1_00_110 XTAL3 + PLL8X 0_1_1_11_110
have current information for their timing calculations. XINPUT + PLL16X 0_1_1_00_111 XTAL3 + PLL16X 0_1_1_11_111

Table 14: CLK Register Fields

Bit 7 6 5 4 3 2 1 0
Name RESET PLLENA OSCENA OSCM1 OSCM2 CLKSEL2 CLKSEL1 CLKSEL0
RESET Effect
0 Always write ‘0’ here unless you intend to reset the chip.
1 Same as a hardware reset – reboots the chip.
PLLENA Effect
0 Disables the PLL circuit.
Enables the PLL circuit. The PLL internally multiplies the XIN pin frequency by 16. OSCENA must be ‘1’ to propagate the
XIN signal to the PLL. The PLL’s internal frequency must be kept within 64 MHz to 128 MHz – this translates to an XIN
1 frequency range of 4 MHz to 8 MHz. Allow 100 µs for the PLL to stabilize before switching to one of its outputs via the
CLKSEL bits. Once the OSC and PLL circuits are enabled and stabilized, you can switch freely among all clock sources by
changing the CLKSEL bits.
OSCENA Effect
0 Disables the OSC circuit
Enables the OSC circuit so that a clock signal can be input to XIN, or so that XIN and XOUT can function together as a
feedback oscillator. The OSCM bits select the operating mode of the OSC circuit. Note that no external resistors or
1 capacitors are required for crystals and resonators. Allow a crystal or resonator 10 ms to stabilize before switching to an
OSC or PLL output via the CLKSEL bits. When enabling the OSC circuit, the PLL may be enabled at the same time so that
they can share the stabilization period.
OSCM1 OSCM2 XOUT Resistance XIN and XOUT Capacitance Frequency Range
0 0 Infinite 6 pF (pad only) DC to 80 MHz Input
0 1 2000 Ω 36 pF 4 MHz to 16 MHz Crystal/Resonator
1 0 1000 Ω 26 pF 8 MHz to 32 MHz Crystal/Resonator
1 1 500 Ω 16 pF 20 MHz to 60 MHz Crystal/Resonator
CLKSEL2 CLKSEL1 CLKSEL0 Master Clock Source Notes
0 0 0 ~12 MHz Internal No external parts (8 to 20 MHz)
0 0 1 ~20 kHz Internal No external parts, very low power (13-33 kHz)
0 1 0 XIN OSC OSCENA must be ‘1’
0 1 1 XIN × 1 OSC+PLL OSCENA and PLLENA must be ‘1’
1 0 0 XIN × 2 OSC+PLL OSCENA and PLLENA must be ‘1’
1 0 1 XIN × 4 OSC+PLL OSCENA and PLLENA must be ‘1’
1 1 0 XIN × 8 OSC+PLL OSCENA and PLLENA must be ‘1’
1 1 1 XIN × 16 OSC+PLL OSCENA and PLLENA must be ‘1’

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5.0 MEMORY ORGANIZATION

5.1. Main Memory 5.1.2. Main ROM
The Main Memory is a block of 64 K bytes (16 K longs) The 32 KB of Main ROM contains all the code and data
that is accessible by all cogs as a mutually-exclusive resources vital to the Propeller chip’s function: character
resource through the Hub. It consists of 32 KB of RAM definitions, log, anti-log and sine tables, and the Boot
and 32 KB of ROM. Main memory is byte, word and long Loader and Spin Interpreter.
addressable. 5.1.3. Character Definitions
The first half of ROM is dedicated to a set of 256
character definitions. Each character definition is 16
pixels wide by 32 pixels tall. These character definitions
can be used for video generation, graphical LCD's,
printing, etc.
The character set is based on a North American / Western
European layout, with many specialized characters added
and inserted. There are connecting waveform and
schematic building-block characters, Greek characters
commonly used in electronics, and several arrows and
bullets. (A corresponding Parallax True-Type Font is
installed with and used by the Propeller Tool software,
and is available to other Windows applications.)
The character definitions are numbered 0 to 255 from left-
to-right, then top-to-bottom, per Figure 7 below. They are
5.1.1. Main RAM arranged as follows: Each pair of adjacent even-odd
characters is merged together to form 32 longs. The first
The 32 KB of Main RAM is general purpose and is the character pair is located in $8000-$807F. The second pair
destination of a Propeller Application either downloaded occupies $8080-$80FF, and so on, until the last pair fills
from a host or from the external 32 KB EEPROM. $BF80-$BFFF.

Figure 7: Propeller Font Character Set

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Figure 8
Propeller Character
Interleaving

As shown in Figure 8, The character pairs are merged

5.1.4. Math Function Tables
row-by-row such that each character's 16 horizontal pixels
are spaced apart and interleaved with their neighbors' so Base-2 Log and Anti-Log tables, each with 2048 unsigned
that the even character takes bits 0, 2, 4, ...30, and the odd words, facilitate converting values to and from exponent
character takes bits 1, 3, 5, ...31. The leftmost pixels are in form to facilitate some operations; see the Propeller
the lowest bits, while the rightmost pixels are in the Manual for access instructions. Also, a sine table
highest bits. This forms a long for each row of pixels in provides 2049 unsigned 16-bit sine samples spanning 0°
the character pair. 32 such longs, building from top row to 90° inclusively (0.0439° resolution).
down to bottom, make up the complete merged-pair
definition. The definitions are encoded in this manner so 5.2. Cog RAM
that a cog’s video hardware can handle the merged longs As stated in Section 4.3, the Cog RAM is used for
directly, using color selection to display either the even or executable code, data, and variables, and the last 16
the odd character. locations serve as interfaces to the System Counter, I/O
Some character codes have inescapable meanings, such as pins, and local cog peripherals (see Table 15).
9 for Tab, 10 for Line Feed, and 13 for Carriage Return. When a cog is booted up, locations 0 ($000) through 495
These character codes invoke actions and do not equate to ($1EF) are loaded sequentially from Main RAM / ROM
static character definitions. For this reason, their character and its special purpose locations, 496 ($1F0) through 511
definitions have been used for special four-color ($1FF), are cleared to zero. Each Special Purpose register
characters. These four-color characters are used for may be accessed via its physical address, its predefined
drawing 3-D box edges at run-time and are implemented name, or indirectly in Spin via a register array variable
as 16 x 16 pixel cells, as opposed to the normal 16 x 32 SPR with an index of 0 to 15, the last four bits of the
pixel cells. They occupy even-odd character pairs 0-1, 8- register's address.
9, 10-11, and 12-13.

Table 15: Cog RAM Special Purpose Registers

Cog RAM Map Address Name Type Description
1
$1F0 PAR Read-Only Boot Parameter
1
$1F1 CNT Read-Only System Counter
1
$1F2 INA Read-Only Input States for P31 - P0
1 3
$1F3 INB Read-Only Input States for P63- P32
$1F4 OUTA Read/Write Output States for P31 - P0
3
$1F5 OUTB Read/Write Output States for P63 – P32
$1F6 DIRA Read/Write Direction States for P31 - P0
3
$1F7 DIRB Read/Write Direction States for P63 - P32
$1F8 CTRA Read/Write Counter A Control
$1F9 CTRB Read/Write Counter B Control
$1FA FRQA Read/Write Counter A Frequency
$1FB FRQB Read/Write Counter B Frequency
2
$1FC PHSA Read/Write Counter A Phase:
2
$1FD PHSB Read/Write Counter B Phase
$1FE VCFG Read/Write Video Configuration
$1FF VSCL Read/Write Video Scale
Note 1: Only accessible as a source register (i.e. MOV Dest, Source).
Note 2: Only readable as a Source Register (i.e. MOV Dest, Source); read-modify-write not possible as a Destination Register.
Note 3: Reserved for future use.

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6.0 PROGRAMMING LANGUAGES

The Propeller chip is programmed using two languages designed specifically for it: 1) Spin, a high-level object-based
language, and 2) Propeller Assembly, a low-level, highly-optimized assembly language. There are many hardware-based
commands in Propeller Assembly that have direct equivalents in the Spin language.
The Spin language is compiled by the Propeller Tool software into tokens that are interpreted at run time by the Propeller
chip’s built-in Spin Interpreter. The Propeller Assembly language is assembled into pure machine code by the Propeller Tool
and is executed in its pure form at run time.
Propeller Objects can be written entirely in Spin or can use various combinations of Spin and Propeller Assembly. It is often
advantageous to write objects almost entirely in Propeller Assembly, but at least two lines of Spin code are required to launch
the final application.

6.1. Reserved Word List

All words listed are always reserved, whether programming in Spin or in Propeller Assembly. As of Propeller Tool v1.05:
Table 16: Reserved Word List
s d a d a s d
_CLKFREQ COGINIT IF_C_AND_NZ LOCKNEW NOP REPEAT TRUE
s s a d s a s
_CLKMODE COGNEW IF_C_AND_Z LOCKRET NOT RES TRUNC
s d a d a s s
_FREE COGSTOP IF_C_EQ_Z LOCKSET NR RESULT UNTIL
s s a s s a s
_STACK CON IF_C_NE_Z LONG OBJ RET VAR
s s a s a# s d
_XINFREQ CONSTANT IF_C_OR_NZ LONGFILL ONES RETURN VCFG
s d a s d a d
ABORT CTRA IF_C_OR_Z LONGMOVE OR REV VSCL
a d a s a a d
ABS CTRB IF_E LOOKDOWN ORG ROL WAITCNT
a s a s s a d
ABSNEG DAT IF_NC LOOKDOWNZ OTHER ROR WAITPEQ
a d a s d s d
ADD DIRA IF_NC_AND_NZ LOOKUP OUTA ROUND WAITPNE
a d# a s d# a d
ADDABS DIRB IF_NC_AND_Z LOOKUPZ OUTB SAR WAITVID
a a a a d a a
ADDS DJNZ IF_NC_OR_NZ MAX PAR SHL WC
a s a a d a s
ADDSX ELSE IF_NC_OR_Z MAXS PHSA SHR WHILE
a s a a d s s
ADDX ELSEIF IF_NE MIN PHSB SPR WORD
d s a a d s s
AND ELSEIFNOT IF_NEVER MINS PI STEP WORDFILL
a a# a a s s s
ANDN ENC IF_NZ MOV PLL1X STRCOMP WORDMOVE
s d a a s s a
BYTE FALSE IF_NZ_AND_C MOVD PLL2X STRING WR
s s a a s s a
BYTEFILL FILE IF_NZ_AND_NC MOVI PLL4X STRSIZE WRBYTE
s a a a s a a
BYTEMOVE FIT IF_NZ_OR_C MOVS PLL8X SUB WRLONG
a s a a# s a a
CALL FLOAT IF_NZ_OR_NC MUL PLL16X SUBABS WRWORD
s s a a# d a a
CASE FROM IF_Z MULS POSX SUBS WZ
s d a a s a s
CHIPVER FRQA IF_Z_AND_C MUXC PRI SUBSX XINPUT
s d a a s a a
CLKFREQ FRQB IF_Z_AND_NC MUXNC PUB SUBX XOR
s a a a s a s
CLKMODE HUBOP IF_Z_EQ_C MUXNZ QUIT SUMC XTAL1
d s a a s a s
CLKSET IF IF_Z_NE_C MUXZ RCFAST SUMNC XTAL2
a s a a a a s
CMP IFNOT IF_Z_OR_C NEG RCL SUMNZ XTAL3
a a a a a a
CMPS IF_A IF_Z_OR_NC NEGC RCR SUMZ
a a d a s a
CMPSUB IF_AE INA NEGNC RCSLOW TEST
a a d# a a a
CMPSX IF_ALWAYS INB NEGNZ RDBYTE TESTN
a a a d a a
CMPX IF_B JMP NEGX RDLONG TJNZ
d a a a a a
CNT IF_BE JMPRET NEGZ RDWORD TJZ
d a d s s s
COGID IF_C LOCKCLR NEXT REBOOT TO
a = Assembly element; s = Spin element; d = dual (available in both languages); # = reserved for future use

6.1.1. Words Reserved for Future Use

• DIRB, INB, and OUTB: Reserved for future use with a possible 64 I/O pin model. When used with the P8X32A, these
labels can be used to access Cog RAM at those locations for general-purpose use.
• ENC, MUL, MULS, ONES: Use with the current P8X32A architecture yields indeterminate results.

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6.2. Math and Logic Operators

Table 17: Math and Logic Operators
Operator Constant
3
Level
1 Expressions Is Unary Description
2
Normal Assign
Integer Float
-- always 9 Pre-decrement (--X) or post-decrement (X--).
++ always 9 Pre-increment (++X) or post-increment (X++).
~ always 9 Sign-extend bit 7 (~X) or post-clear to 0 (X~).
Highest
~~ always 9 Sign-extend bit 15 (~~X) or post-set to -1 (X~~).
(0)
? always 9 Random number forward (?X) or reverse (X?).
@ never 9 9 Symbol address.
@@ never 9 Object address plus symbol.
+ never 9 9 9 Positive (+X); unary form of Add.
- if solo 9 9 9 Negate (-X); unary form of Subtract.
^^ if solo 9 9 9 Square root.
1 || if solo 9 9 9 Absolute value.
|< if solo 9 9 Bitwise: Decode 0 – 31 to long w/single-high-bit.
>| if solo 9 9 Bitwise: Encode long to 0 – 32; high-bit priority.
! if solo 9 9 Bitwise: NOT.
<- <-= 9 Bitwise: Rotate left.
-> ->= 9 Bitwise: Rotate right.
<< <<= 9 Bitwise: Shift left.
2
>> >>= 9 Bitwise: Shift right.
~> ~>= 9 Shift arithmetic right.
>< ><= 9 Bitwise: Reverse.
3 & &= 9 Bitwise: AND.
| |= 9 Bitwise: OR.
4
^ ^= 9 Bitwise: XOR.
* *= 9 9 Multiply and return lower 32 bits (signed).
** **= 9 Multiply and return upper 32 bits (signed).
5
/ /= 9 9 Divide (signed).
// //= 9 Modulus (signed).
+ += 9 9 Add.
6
- -= 9 9 Subtract.
#> #>= 9 9 Limit minimum (signed).
7
<# <#= 9 9 Limit maximum (signed).
< <= 9 9 Boolean: Is less than (signed).
> >= 9 9 Boolean: Is greater than (signed).
<> <>= 9 9 Boolean: Is not equal.
8
== === 9 9 Boolean: Is equal.
=< =<= 9 9 Boolean: Is equal or less (signed).
=> =>= 9 9 Boolean: Is equal or greater (signed).
9 NOT if solo 9 9 9 Boolean: NOT (promotes non-0 to -1).
10 AND AND= 9 9 Boolean: AND (promotes non-0 to -1).
11 OR OR= 9 9 Boolean: OR (promotes non-0 to -1).
3 3
Lowest = always n/a n/a Constant assignment (CON blocks).
(12) := always n/a
3
n/a
3
Variable assignment (PUB/PRI blocks).
1 Precedence level: higher-level operators evaluate before lower-level operators. Operators in same level are commutable; evaluation order does not matter.
2 Assignment forms of binary (non-unary) operators are in the lowest precedence (level 12).
3 Assignment forms of operators are not allowed in constant expressions.

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6.3. Spin Language Summary Table

Returns
Spin Command Value Description
ABORT 〈Value〉 9 Exit from PUB/PRI method using abort status with optional return value.
BYTE Symbol 〈[Count]〉 Declare byte-sized symbol in VAR block.
〈Symbol〉 BYTE Data 〈[Count]〉 Declare byte-aligned and/or byte-sized data in DAT block.
BYTE [BaseAddress] 〈[Offset]〉 9 Read/write byte of main memory.
Symbol.BYTE 〈[Offset]〉 9 Read/write byte-sized component of word/long-sized variable.
BYTEFILL (StartAddress, Value, Count) Fill bytes of main memory with a value.
BYTEMOVE (DestAddress, SrcAddress, Count) Copy bytes from one region to another in main memory.
CASE CaseExpression
Compare expression against matching expression(s), execute code block
MatchExpression :
if match found.
Statement(s)
〈 MatchExpression : MatchExpression can contain a single expression or multiple comma-
Statement(s)〉
delimited expressions. Expressions can be a single value (ex: 10) or a
〈 OTHER : range of values (ex: 10..15).
Statement(s)〉
CHIPVER 9 Version number of the Propeller chip (Byte at $FFFF)
CLKFREQ 9 Current System Clock frequency, in Hz (Long at $0000)
CLKMODE 9 Current clock mode setting (Byte at $0004)
CLKSET (Mode, Frequency) Set both clock mode and System Clock frequency at run time.
CNT 9 Current 32-bit System Counter value.
COGID 9 Current cog’s ID number; 0-7.
COGINIT (CogID, SpinMethod 〈(ParameterList)〉, StackPointer) Start or restart cog by ID to run Spin code.
COGINIT (CogID, AsmAddress, Parameter) Start or restart cog by ID to run Propeller Assembly code.
COGNEW (SpinMethod 〈(ParameterList)〉, StackPointer) 9 Start new cog for Spin code and get cog ID; 0-7 = succeeded, -1 = failed.
Start new cog for Propeller Assembly code and get cog ID; 0-7 =
COGNEW (AsmAddress, Parameter) 9
succeeded, -1 = failed.
COGSTOP (CogID) Stop cog by its ID.
CON
Declare symbolic, global constants.
Symbol = Expr 〈((,┆ )) Symbol = Expr〉…
CON
Declare global enumerations (incrementing symbolic constants).
#Expr ((,┆ )) Symbol 〈[Offset]〉 〈((,┆ )) Symbol 〈[Offset]〉 …
CON
Declare global enumerations (incrementing symbolic constants).
Symbol 〈[Offset]〉 〈((,┆ )) Symbol 〈[Offset]〉 〉…
Declare in-line constant expression to be completely resolved at compile
CONSTANT (ConstantExpression) 9
time.
CTRA 9 Counter A Control register.
CTRB 9 Counter B Control register.
DAT
Declare table of data, aligned and sized as specified.
〈Symbol〉 Alignment 〈Size〉 〈Data〉 〈[Count]〉 〈,〈Size〉 Data 〈[Count]〉〉…
DAT
Denote Propeller Assembly instruction.
〈Symbol〉 〈Condition〉 Instruction 〈Effect(s)〉
DIRA 〈[Pin(s)]〉 9 Direction register for 32-bit port A. Default is 0 (input) upon cog startup.
FILE "FileName" Import external file as data in DAT block.
Convert integer constant expression to compile-time floating-point value in
FLOAT (IntegerConstant) 9
any block.
FRQA 9 Counter A Frequency register.
FRQB 9 Counter B Frequency register.

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Returns
Spin Command Value Description
((IF ┆ IFNOT)) Condition(s)
IfStatement(s)
〈ELSEIF Condition(s) Test condition(s) and execute block of code if valid.
ElseIfStatement(s)〉…
〈ELSEIFNOT Condition(s) IF and ELSEIF each test for TRUE. IFNOT and ELSEIFNOT each test for
ElseIfStatement(s)〉… FALSE.
〈ELSE
ElseStatement(s)〉
INA 〈[Pin(s)]〉 9 Input register for 32-bit ports A.
LOCKCLR (ID) 9 Clear semaphore to false and get its previous state; TRUE or FALSE.
LOCKNEW 9 Check out new semaphore and get its ID; 0-7, or -1 if none were available.
Return semaphore back to semaphore pool, releasing it for future
LOCKRET (ID)
LOCKNEW requests.
LOCKSET (ID) 9 Set semaphore to true and get its previous state; TRUE or FALSE.
LONG Symbol 〈[Count]〉 Declare long-sized symbol in VAR block.
〈Symbol〉 LONG Data 〈[Count]〉 Declare long-aligned and/or long-sized data in DAT block.
LONG [BaseAddress] 〈[Offset]〉 9 Read/write long of main memory.
LONGFILL (StartAddress, Value, Count) Fill longs of main memory with a value.
LONGMOVE (DestAddress, SrcAddress, Count) Copy longs from one region to another in main memory.
LOOKDOWN (Value:ExpressionList) 9 Get the one-based index of a value in a list.
LOOKDOWNZ (Value:ExpressionList) 9 Get the zero-based index of a value in a list.
LOOKUP (Index:ExpressionList) 9 Get value from a one-based index position of a list.
LOOKUPZ (Index:ExpressionList) 9 Get value from a zero-based index position of a list.
Skip remaining statements of REPEAT loop and continue with the next
NEXT
loop iteration.
OBJ
Declare symbol object references.
Symbol 〈[Count]〉:"Object" 〈 Symbol 〈[Count]〉: "Object"〉…
OUTA 〈[Pin(s)]〉 9 Output register for 32-bit port A. Default is 0 (ground) upon cog startup.
PAR 9 Cog Boot Parameter register.
PHSA 9 Counter A Phase Lock Loop (PLL) register.
PHSB 9 Counter B Phase Lock Loop (PLL) register.
PRI Name 〈(Par 〈,Par〉…)〉 〈:RVal〉 〈| LVar 〈[Cnt]〉〉 〈,LVar 〈[Cnt]〉〉… Declare private method with optional parameters, return value and local
SourceCodeStatements variables.
PUB Name 〈(Par 〈,Par〉…)〉 〈:RVal〉 〈| LVar 〈[Cnt]〉〉 〈,LVar 〈[Cnt]〉〉… Declare public method with optional parameters, return value and local
SourceCodeStatements variables.
QUIT Exit from REPEAT loop immediately.
REBOOT Reset the Propeller chip.
REPEAT 〈Count〉 Execute code block repetitively, either infinitely, or for a finite number of
Statement(s) iterations.
REPEAT Variable FROM Start TO Finish 〈STEP Delta〉
Execute code block repetitively, for finite, counted iterations.
Statement(s)
REPEAT ((UNTIL┆ WHILE)) Condition(s)
Execute code block repetitively, zero-to-many conditional iterations.
Statement(s)
REPEAT
Statement(s) Execute code block repetitively, one-to-many conditional iterations.
((UNTIL┆ WHILE)) Condition(s)
RESULT 9 Return value variable for PUB/PRI methods.
RETURN 〈Value〉 9 Exit from PUB/PRI method with optional return Value.
Round floating-point constant to the nearest integer at compile-time, in any
ROUND (FloatConstant) 9
block.
SPR [Index] 9 Special Purpose Register array.
STRCOMP (StringAddress1, StringAddress2) 9 Compare two strings for equality.
STRING (StringExpression) 9 Declare in-line string constant and get its address.

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Returns
Spin Command Value Description
STRSIZE (StringAddress) 9 Get size, in bytes, of zero-terminate string.
Remove fractional portion from floating-point constant at compile-time, in
TRUNC (FloatConstant) 9
any block.
VAR
Declare symbolic global variables.
Size Symbol 〈[Count]〉 〈((,┆ Size )) Symbol 〈[Count]〉〉…
VCFG 9 Video Configuration register.
VSCL 9 Video Scale register.
WAITCNT (Value) Pause cog’s execution temporarily.
WAITPEQ (State, Mask, Port) Pause cog’s execution until I/O pin(s) match designated state(s).
WAITPNE (State, Mask, Port) Pause cog’s execution until I/O pin(s) do not match designated state(s).
WAITVID (Colors, Pixels) Pause cog’s execution until its Video Generator is available for pixel data.
WORD Symbol 〈[Count]〉 Declare word-sized symbol in VAR block.
〈Symbol〉 WORD Data 〈[Count]〉 Declare word-aligned and/or word-sized data in DAT block.
WORD [BaseAddress] 〈[Offset]〉 9 Read/write word of main memory.
Symbol.WORD 〈[Offset]〉 9 Read/write word-sized component of long-sized variable.
WORDFILL (StartAddress, Value, Count) Fill words of main memory with a value.
WORDMOVE (DestAddress, SrcAddress, Count) Copy words from one region to another in main memory.

6.3.1. Constants
Constants (pre-defined)
1
Constant Description
_CLKFREQ Settable in Top Object File to specify System Clock frequency.
_CLKMODE Settable in Top Object File to specify application’s clock mode.
_XINFREQ Settable in Top Object File to specify external crystal frequency.
_FREE Settable in Top Object File to specify application’s free space.
_STACK Settable in Top Object File to specify application’s stack space.
TRUE Logical true: -1 ($FFFFFFFF)
FALSE Logical false: 0 ($00000000)
POSX Max. positive integer: 2,147,483,647 ($7FFFFFFF)
NEGX Max. negative integer: -2,147,483,648 ($80000000)
PI Floating-point PI: ≈ 3.141593 ($40490FDB)
RCFAST Internal fast oscillator: $00000001 (%00000000001)
RCSLOW Internal slow oscillator: $00000002 (%00000000010)
XINPUT External clock/oscillator: $00000004 (%00000000100)
XTAL1 External low-speed crystal: $00000008 (%00000001000)
XTAL2 External medium-speed crystal: $00000010 (%00000010000)
XTAL3 External high-speed crystal: $00000020 (%00000100000)
PLL1X External frequency times 1: $00000040 (%00001000000)
PLL2X External frequency times 2: $00000080 (%00010000000)
PLL4X External frequency times 4: $00000100 (%00100000000)
PLL8X External frequency times 8: $00000200 (%01000000000)
PLL16X External frequency times 16: $00000400 (%10000000000)
1 “Settable” constants are defined in Top Object File’s CON block. See Valid Clock Modes for _CLKMODE. Other settable constants use whole numbers.

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6.4. Propeller Assembly Instruction Table

The Propeller Assembly Instruction Table lists the instruction’s 32-bit opcode, outputs and number of clock cycles. The
opcode consists of the instruction bits (iiiiii), the “effect” status for the Z flag, C flag, result and indirect/immediate status
(zcri), the conditional execution bits (cccc), and the destination and source bits (ddddddddd and sssssssss). The meaning of the
Z and C flags, if any, is shown in the Z Result and C Result fields; indicating the meaning of a 1 in those flags. The Result field
(R) shows the instruction’s default behavior for writing (1) or not writing (0) the instruction’s result value. The Clocks field
shows the number of clocks the instruction requires for execution.
0 1 Zeros (0) and ones (1) mean binary 0 and 1.
i Lower case “i” denotes a bit that is affected by immediate status.
d s Lower case “d” and “s” indicate destination and source bits.
? Question marks denote bits that are dynamically set by the compiler.
--- Hyphens indicate items that are not applicable or not important.
.. Double-periods represent a range of contiguous values.

iiiiii zcri cccc ddddddddd sssssssss Instruction Description Z Result C Result R Clocks
000000 000i 1111 ddddddddd sssssssss WRBYTE D,S Write D[7..0] to main memory byte S[15..0] - - 0 7..22 *
Read main memory byte S[15..0] into D (0-
000000 001i 1111 ddddddddd sssssssss RDBYTE D,S Result = 0 - 1 7..22 *
extended)
000001 000i 1111 ddddddddd sssssssss WRWORD D,S Write D[15..0] to main memory word S[15..1] - - 0 7..22 *
Read main memory word S[15..1] into D (0-
000001 001i 1111 ddddddddd sssssssss RDWORD D,S Result = 0 - 1 7..22 *
extended)
000010 000i 1111 ddddddddd sssssssss WRLONG D,S Write D to main memory long S[15..2] - - 0 7..22 *
000010 001i 1111 ddddddddd sssssssss RDLONG D,S Read main memory long S[15..2] into D Result = 0 - 1 7..22 *
000011 000i 1111 ddddddddd sssssssss HUBOP D,S Perform hub operation according to S Result = 0 - 0 7..22 *
000011 0001 1111 ddddddddd ------000 CLKSET D Set the global CLK register to D[7..0] - - 0 7..22 *
000011 0011 1111 ddddddddd ------001 COGID D Get this cog number (0..7) into D Result = 0 - 1 7..22 *
000011 0001 1111 ddddddddd ------010 COGINIT D Initialize a cog according to D Result = 0 No cog free 0 7..22 *
000011 0001 1111 ddddddddd ------011 COGSTOP D Stop cog number D[2..0] - - 0 7..22 *
000011 0011 1111 ddddddddd ------100 LOCKNEW D Checkout a new LOCK number (0..7) into D Result = 0 No lock free 1 7..22 *
000011 0001 1111 ddddddddd ------101 LOCKRET D Return lock number D[2..0] - - 0 7..22 *
000011 0001 1111 ddddddddd ------110 LOCKSET D Set lock number D[2..0] - Prior lock state 0 7..22 *
000011 0001 1111 ddddddddd ------111 LOCKCLR D Clear lock number D[2..0] - Prior lock state 0 7..22 *
000100 001i 1111 ddddddddd sssssssss MUL D,S Multiply unsigned D[15..0] by S[15..0] Result = 0 - 1 future
000101 001i 1111 ddddddddd sssssssss MULS D,S Multiply signed D[15..0] by S[15..0] Result = 0 - 1 future
000110 001i 1111 ddddddddd sssssssss ENC D,S Encode magnitude of S into D, result = 0..31 Result = 0 - 1 future
000111 001i 1111 ddddddddd sssssssss ONES D,S Get number of 1's in S into D, result = 0..31 Result = 0 - 1 future
001000 001i 1111 ddddddddd sssssssss ROR D,S Rotate D right by S[4..0] bits Result = 0 D[0] 1 4
001001 001i 1111 ddddddddd sssssssss ROL D,S Rotate D left by S[4..0] bits Result = 0 D[31] 1 4
001010 001i 1111 ddddddddd sssssssss SHR D,S Shift D right by S[4..0] bits, set new MSB to 0 Result = 0 D[0] 1 4
001011 001i 1111 ddddddddd sssssssss SHL D,S Shift D left by S[4..0] bits, set new LSB to 0 Result = 0 D[31] 1 4
001100 001i 1111 ddddddddd sssssssss RCR D,S Rotate carry right into D by S[4..0] bits Result = 0 D[0] 1 4
001101 001i 1111 ddddddddd sssssssss RCL D,S Rotate carry left into D by S[4..0] bits Result = 0 D[31] 1 4
001110 001i 1111 ddddddddd sssssssss SAR D,S Shift D arithmetically right by S[4..0] bits Result = 0 D[0] 1 4
Reverse 32–S[4..0] bottom bits in D and 0-
001111 001i 1111 ddddddddd sssssssss REV D,S Result = 0 D[0] 1 4
extend
010000 001i 1111 ddddddddd sssssssss MINS D,S Set D to S if signed (D < S) D=S Signed (D < S) 1 4
010001 001i 1111 ddddddddd sssssssss MAXS D,S Set D to S if signed (D => S) D=S Signed (D < S) 1 4
010010 001i 1111 ddddddddd sssssssss MIN D,S Set D to S if unsigned (D < S) D=S Unsigned (D < S) 1 4
010011 001i 1111 ddddddddd sssssssss MAX D,S Set D to S if unsigned (D => S) D=S Unsigned (D < S) 1 4
010100 001i 1111 ddddddddd sssssssss MOVS D,S Insert S[8..0] into D[8..0] Result = 0 - 1 4
010101 001i 1111 ddddddddd sssssssss MOVD D,S Insert S[8..0] into D[17..9] Result = 0 - 1 4
010110 001i 1111 ddddddddd sssssssss MOVI D,S Insert S[8..0] into D[31..23] Result = 0 - 1 4
010111 001i 1111 ddddddddd sssssssss JMPRET D,S Insert PC+1 into D[8..0] and set PC to S[8..0] Result = 0 - 1 4
010111 000i 1111 --------- sssssssss JMP S Set PC to S[8..0] Result = 0 - 0 4

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iiiiii zcri cccc ddddddddd sssssssss Instruction Description Z Result C Result R Clocks
010111 0011 1111 ????????? sssssssss CALL #S Like JMPRET, but assembler handles details Result = 0 - 1 4
010111 0001 1111 --------- --------- RET Like JMP, but assembler handles details Result = 0 - 0 4
011000 000i 1111 ddddddddd sssssssss TEST D,S AND S with D to affect flags only Result = 0 Parity of Result 0 4
011001 000i 1111 ddddddddd sssssssss TESTN D,S AND !S into D to affect flags only Result = 0 Parity of Result 0 4
011000 001i 1111 ddddddddd sssssssss AND D,S AND S into D Result = 0 Parity of Result 1 4
011001 001i 1111 ddddddddd sssssssss ANDN D,S AND !S into D Result = 0 Parity of Result 1 4
011010 001i 1111 ddddddddd sssssssss OR D,S OR S into D Result = 0 Parity of Result 1 4
011011 001i 1111 ddddddddd sssssssss XOR D,S XOR S into D Result = 0 Parity of Result 1 4
011100 001i 1111 ddddddddd sssssssss MUXC D,S Copy C to bits in D using S as mask Result = 0 Parity of Result 1 4
011101 001i 1111 ddddddddd sssssssss MUXNC D,S Copy !C to bits in D using S as mask Result = 0 Parity of Result 1 4
011110 001i 1111 ddddddddd sssssssss MUXZ D,S Copy Z to bits in D using S as mask Result = 0 Parity of Result 1 4
011111 001i 1111 ddddddddd sssssssss MUXNZ D,S Copy !Z to bits in D using S as mask Result = 0 Parity of Result 1 4
100000 001i 1111 ddddddddd sssssssss ADD D,S Add S into D Result = 0 Unsigned Carry 1 4
100001 001i 1111 ddddddddd sssssssss SUB D,S Subtract S from D Result = 0 Unsigned Borrow 1 4
100001 000i 1111 ddddddddd sssssssss CMP D,S Compare D to S D=S Unsigned Borrow 0 4
100010 001i 1111 ddddddddd sssssssss ADDABS D,S Add absolute S into D Result = 0 Unsigned Carry 1 1 4
100011 001i 1111 ddddddddd sssssssss SUBABS D,S Subtract absolute S from D Result = 0 Unsigned Borrow 2 1 4
100100 001i 1111 ddddddddd sssssssss SUMC D,S Sum either –S if C or S if !C into D Result = 0 Signed Overflow 1 4
100101 001i 1111 ddddddddd sssssssss SUMNC D,S Sum either S if C or –S if !C into D Result = 0 Signed Overflow 1 4
100110 001i 1111 ddddddddd sssssssss SUMZ D,S Sum either –S if Z or S if !Z into D Result = 0 Signed Overflow 1 4
100111 001i 1111 ddddddddd sssssssss SUMNZ D,S Sum either S if Z or –S if !Z into D Result = 0 Signed Overflow 1 4
101000 001i 1111 ddddddddd sssssssss MOV D,S Set D to S Result = 0 S[31] 1 4
101001 001i 1111 ddddddddd sssssssss NEG D,S Set D to –S Result = 0 S[31] 1 4
101010 001i 1111 ddddddddd sssssssss ABS D,S Set D to absolute S Result = 0 S[31] 1 4
101011 001i 1111 ddddddddd sssssssss ABSNEG D,S Set D to –absolute S Result = 0 S[31] 1 4
101100 001i 1111 ddddddddd sssssssss NEGC D,S Set D to either –S if C or S if !C Result = 0 S[31] 1 4
101101 001i 1111 ddddddddd sssssssss NEGNC D,S Set D to either S if C or –S if !C Result = 0 S[31] 1 4
101110 001i 1111 ddddddddd sssssssss NEGZ D,S Set D to either –S if Z or S if !Z Result = 0 S[31] 1 4
101111 001i 1111 ddddddddd sssssssss NEGNZ D,S Set D to either S if Z or –S if !Z Result = 0 S[31] 1 4
110000 000i 1111 ddddddddd sssssssss CMPS D,S Compare-signed D to S D=S Signed Borrow 0 4
110001 000i 1111 ddddddddd sssssssss CMPSX D,S Compare-signed-extended D to S+C Z & (D = S+C) Signed Borrow 0 4
110010 001i 1111 ddddddddd sssssssss ADDX D,S Add-extended S+C into D Z & (Result = 0) Unsigned Carry 1 4
110011 001i 1111 ddddddddd sssssssss SUBX D,S Subtract-extended S+C from D Z & (Result = 0) Unsigned Borrow 1 4
110011 000i 1111 ddddddddd sssssssss CMPX D,S Compare-extended D to S+C Z & (D = S+C) Unsigned Borrow 0 4
110100 001i 1111 ddddddddd sssssssss ADDS D,S Add-signed S into D Result = 0 Signed Overflow 1 4
110101 001i 1111 ddddddddd sssssssss SUBS D,S Subtract-signed S from D Result = 0 Signed Overflow 1 4
110110 001i 1111 ddddddddd sssssssss ADDSX D,S Add-signed-extended S+C into D Z & (Result = 0) Signed Overflow 1 4
110111 001i 1111 ddddddddd sssssssss SUBSX D,S Subtract-signed-extended S+C from D Z & (Result = 0) Signed Overflow 1 4
111000 001i 1111 ddddddddd sssssssss CMPSUB D,S Subtract S from D if D => S D=S Unsigned (D => S) 1 4
Dec D, jump if not zero to S (no jump = 8
111001 001i 1111 ddddddddd sssssssss DJNZ D,S Result = 0 Unsigned Borrow 1 4 or 8
clocks)
Test D, jump if not zero to S (no jump = 8
111010 000i 1111 ddddddddd sssssssss TJNZ D,S Result = 0 0 0 4 or 8
clocks)
111011 000i 1111 ddddddddd sssssssss TJZ D,S Test D, jump if zero to S (no jump = 8 clocks) Result = 0 0 0 4 or 8
111100 000i 1111 ddddddddd sssssssss WAITPEQ D,S Wait for pins equal - (INA & S) = D - - 0 5+
111101 000i 1111 ddddddddd sssssssss WAITPNE D,S Wait for pins not equal - (INA & S) != D - - 0 5+
111110 001i 1111 ddddddddd sssssssss WAITCNT D,S Wait for CNT = D, then add S into D - Unsigned Carry 1 5+
111111 000i 1111 ddddddddd sssssssss WAITVID D,S Wait for video peripheral to grab D and S - - 0 5+
------ ---- 0000 --------- --------- NOP No operation, just elapses 4 clocks - - - 4
* See Hub, section 4.4 on page 7.
1. ADDABS C out: If S is negative, C = the inverse of unsigned borrow (for D-S).
2. SUBABS C out: If S is negative, C = the inverse of unsigned carry (for D+S).

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6.4.1. Assembly Conditions 6.4.4. Assembly Operators

Condition Instruction Executes Propeller Assembly code can contain constant
IF_ALWAYS always expressions, which may use any operators that are
allowed in constant expressions. The table (a subset of
IF_NEVER never
Table 17) lists the operators allowed in Propeller
IF_E if equal (Z)
Assembly.
IF_NE if not equal (!Z)
Operator Description
IF_A if above (!C & !Z)
+ Add
IF_B if below (C)
+ Positive (+X); unary form of Add
IF_AE if above/equal (!C)
- Subtract
IF_BE if below/equal (C | Z)
- Negate (-X); unary form of Subtract
IF_C if C set
* Multiply and return lower 32 bits (signed)
IF_NC if C clear
** Multiply and return upper 32 bits (signed)
IF_Z if Z set
/ Divide (signed)
IF_NZ if Z clear
// Modulus (signed)
IF_C_EQ_Z if C equal to Z
#> Limit minimum (signed)
IF_C_NE_Z if C not equal to Z
<# Limit maximum (signed)
IF_C_AND_Z if C set and Z set
^^ Square root; unary
IF_C_AND_NZ if C set and Z clear
|| Absolute value; unary
IF_NC_AND_Z if C clear and Z set
~> Shift arithmetic right
IF_NC_AND_NZ if C clear and Z clear
Bitwise: Decode value (0-31) into single-high-bit
IF_C_OR_Z if C set or Z set |< long; unary
IF_C_OR_NZ if C set or Z clear Bitwise: Encode long into value (0 - 32) as high-
>| bit priority; unary
IF_NC_OR_Z if C clear or Z set
<< Bitwise: Shift left
IF_NC_OR_NZ if C clear or Z clear
>> Bitwise: Shift right
IF_Z_EQ_C if Z equal to C
<- Bitwise: Rotate left
IF_Z_NE_C if Z not equal to C
-> Bitwise: Rotate right
IF_Z_AND_C if Z set and C set
>< Bitwise: Reverse
IF_Z_AND_NC if Z set and C clear
& Bitwise: AND
IF_NZ_AND_C if Z clear and C set
| Bitwise: OR
IF_NZ_AND_NC if Z clear and C clear
^ Bitwise: XOR
IF_Z_OR_C if Z set or C set
! Bitwise: NOT; unary
IF_Z_OR_NC if Z set or C clear
AND Boolean: AND (promotes non-0 to -1)
IF_NZ_OR_C if Z clear or C set
OR Boolean: OR (promotes non-0 to -1)
IF_NZ_OR_NC if Z clear or C clear
NOT Boolean: NOT (promotes non-0 to -1); unary
6.4.2. Assembly Directives == Boolean: Is equal

Directive Description <> Boolean: Is not equal

Validate previous instr/data fit below an < Boolean: Is less than (signed)
FIT 〈Address〉
address. > Boolean: Is greater than (signed)
Adjust compile-time cog address =< Boolean: Is equal or less (signed)
ORG 〈Address〉
pointer.
=> Boolean: Is equal or greater (signed)
〈Symbol〉 RES 〈Count〉 Reserve next long(s) for symbol.
@ Symbol address; unary

6.4.3. Assembly Effects

Effect Results In
WC C Flag modified
WZ Z Flag modified
WR Destination Register modified
NR Destination Register not modified

Copyright © Parallax Inc. Page 24 of 37 Rev 1.1 9/12/2008

Propeller™ P8X32A Datasheet www.parallax.com

7.0 PROPELLER DEMO BOARD SCHEMATIC

The Propeller Demo Board (Stock #32100) provides convenient connections to 32K EEPROM, replaceable 5 MHz crystal,
3. 3V and 5 V regulators, USB-to-serial programming/communication interface, VGA and NTSC video output, stereo output
with 16 Ω headphone amplifier, microphone input, two PS2 mouse and keyboard jacks, eight LEDs, eight free I/O pins
brought to a header for breadboard for prototyping, and a ground post for an oscilloscope probe. Overall PCB size: 3" x 3".

Copyright © Parallax Inc. Page 25 of 37 Rev 1.1 9/12/2008

Propeller™ P8X32A Datasheet www.parallax.com

8.0 ELECTRICAL CHARACTERISTICS

8.1. Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress
ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the
remainder of Section 7.0. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.

Table 18: Absolute Maximum Ratings

Ambient temperature under bias -55 °C to +125 °C
Storage temperature -65 °C to +150 °C
Voltage on Vdd with respect to Vss -0.3 V to +4.0 V
Voltage on all other pins with respect to Vss -0.3 V to (Vdd + 0.3 V)
Total power dissipation 1W
Max. current out of Vss pins 300 mA
Max. current into Vdd pins 300 mA
Max. DC current into an input pin with internal protection diode forward biased ±500 µA
Max. allowable current per I/O pin 40 mA
ESD (Human Body Model) Supply pins 3 kV
ESD (Human Body Model) all non-supply pins 8 kV

8.2. DC Characteristics
(Operating temperature range: -55° C < Ta < +125° C unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

-
Vdd Supply Voltage 2.7 3.6 V

Logic High 0.6 Vdd Vdd V

Vih, Vil Logic Low V
Vss 0.3 Vdd
Iil Input Leakage Current Vin = Vdd or Vss -1.0 +1.0 µA

Voh Output High Voltage Ioh = 10 mA, Vdd = 3.3 V 2.85 V

Vol Output Low Voltage Iol = 10 mA, Vdd = 3.3 V 0.4 V

IBO Brownout Detector Current 3.8 µA
I Quiescent Current RESn = 0V, BOEn = Vdd, P0-P31=0V 600 nA
Note: Data in the Typical (“Typ”) column is Ta = 25 °C unless otherwise stated.

8.3. AC Characteristics
(Operating temperature range: -55°C < Ta < +125°C unless otherwise noted)

Symbol Parameter Min Typ Max Units Condition

Fosc External XI Frequency DC - 80 MHz
Oscillator Frequency DC - 80 MHz Direct drive (no PLL)
13 20 33 kHz RCSLOW
8 12 20 MHz RCFAST
4 - 8 MHz Crystal using PLL
Cin Input Capacitance 6 - pF
Note: Data in the Typical (“Typ”) column is Ta = 25 °C unless otherwise stated.

Copyright © Parallax Inc. Page 26 of 37 Rev 1.1 9/12/2008

Propeller™ P8X32A Datasheet www.parallax.com

9.0 CURRENT CONSUMPTION CHARACTERISTICS

9.1. Typical Current Consumption of 8 Cogs
This figure shows the typical current consumption of the Propeller under various operating conditions duplicated across all
cogs. Brown out circuitry and the Phase-Locked Loop were disabled for the duration of the test. Current consumption is
substantially constant over the operational temperature range.

Current (A)
10

10

10

10

10

10

10
-6

-5

-4

-3

-2

-1

0
10
2

Hub Only
WAIT(CNT/PEQ/PNE)
Assembly Loops (JMP)
Spin Loops (REPEAT)

Typical Current Consumption of 8 cogs vs. Operating Frequency (3.3V, Ta = 25°C)

10
3
10
4
Frequency (Hz)

10
5
10
6
10
7
10
8

Copyright © Parallax Inc. Page 27 of 37 Rev 1.1 9/12/2008

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9.2. Typical Current of a Cog vs. Operating Frequency

This graph shows a cog’s typical current consumption under various conditions, in isolation of other sources of current within
the Propeller chip.
Typical Current of a Cog vs. Operating Frequency (Vdd = 3.3 V, Ta = 25° C)

14
Spin Loop (REPEAT)
Assembly Loop (JMP)
12
WAIT(CNT/PEQ/PNE)

10
Current (mA)

0
0 10 20 30 40 50 60 70 80 90 100
Frequency (MHz)

9.3. Typical PLL Current vs. VCO Frequency

This graph shows the typical amount of current consumed by a Phase-Locked Loop as a function of the frequency of the
Voltage Controlled Oscillator which is 16 times the frequency of the input clock.

Typical PLL Current vs. VCO Frequency (Vdd = 3.3 V, Ta = 25° C)

1.4

1.3

1.2

1.1
Current (mA)

1.0

0.9

0.8

0.7

0.6

0.5

0.4
20 40 60 80 100 120 140 160

Frequency (MHz)

Copyright © Parallax Inc. Page 28 of 37 Rev 1.1 9/12/2008

Propeller™ P8X32A Datasheet www.parallax.com

9.4. Typical Crystal Drive Current

This graph shows the current consumption of the crystal driver over a range of crystal frequencies and crystal settings, all
data points above 25 MHz were obtained by using a resonator since the driver does not perform 3rd harmonic overtone
driving required for crystals over 25 MHz.

Typical Crystal Drive Current (Vdd = 3.3 V, Ta = 25° C)

1.4
xtal1
xtal2
1.2 xtal3

1.0
Current (mA)

0.8

0.6

0.4

0.2
0 5 10 15 20 25 30 35 40 45 50
Frequency (MHz)

9.5. Cog and I/O Pin Relationship

The figure below illustrates the physical relationship between the cogs and I/O pins. While there can be a 1 to 1.5 ns
propagation delay in output transitions between the shortest and longest paths, the purpose of the figure is to illustrate the
length of leads and their associated parasitic capacitance. This capacitance increases the amount of energy required to
transition a pin’s state and therefore increases the current draw for toggling a pin. So, the current consumed by Cog 7
toggling P0 at 20 MHz will be greater than Cog 0 toggling P7 at 20 MHz. The amount of current consumed by transitioning a
pin’s state is dependent on many factors including: temperature, frequency of transitions, external load, and internal load. As
mentioned, the internal load is dependent upon which cog and pin are used. Internal load current for room temperature
toggling of a pin at 20 MHz for a Propeller in a DIP package varies on the order of 300 µA.

P0
P31

P5

P6 P26

cog 0 cog 1 cog 2 cog 3 cog 4 cog 5 cog 6 cog 7 P25

P7

P24
P8

P9 P23

P10 P22

P21

P15

P16

Copyright © Parallax Inc. Page 29 of 37 Rev 1.1 9/12/2008

Propeller™ P8X32A Datasheet www.parallax.com

9.6. Current Profile at Various Startup Conditions

The diagrams below show the current profile for various startup conditions of the Propeller chip dependent upon the presence
of an EEPROM and PC.

Figure 9
Boot Sequence Current Profile for
no PC and no EEPROM (P31
held low and P29 not connected
(same as held low)).

Figure 10
Boot Sequence Current Profile for
PC (connected but idle) and no
EEPROM. (P31 held high and
P29 not connected).

Figure 11
Boot Sequence Current Profile for
no PC and no EEPROM (P31
held low and P29 held high).

Figure 12
Boot Sequence Current Profile for
no PC and EEPROM (P31 held
low and P29 connected to
EEPROM SDA).

Figure 13
Boot Sequence Current Profile for
PC (connected but idle) and
EEPROM (P31 held high and P29
connected to EEPROM SDA).

Copyright © Parallax Inc. Page 30 of 37 Rev 1.1 9/12/2008

Propeller™ P8X32A Datasheet www.parallax.com

10.0 TEMPERATURE CHARACTERISTICS

10.1. Internal Oscillator Frequency as a Function of Temperature
While the internal oscillator frequency is variable due to process variation, the rate of change as a function of temperature
when normalized provides a chip invariant ratio which can be used to calculate the oscillation frequency when the ambient
temperature is other than 25 °C (the temperature to which the graph was normalized). The absolute frequency at 25 °C varied
from 13.26 to 13.75 MHz in the sample set. The section of the graph which has a white background is the military range of
temperature; the sections in grey represent data which is beyond military temperature specification.

Copyright © Parallax Inc. Page 31 of 37 Rev 1.1 9/12/2008

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10.2. Fastest Operating Frequency as a Function of Temperature

The following graph represents a small sample average of a Propeller chip’s fastest operating range. The test was performed
in a forced air chamber using code run on all eight cogs, multiple video generators, and counter modules. A frequency was
considered successful if the demo ran without fault for one minute. The curves represent an aggressive testing procedure
(averaged, forced air, one minute time limit); therefore the designer must de-rate the curve to arrive at a stable frequency for a
particular application. Again the grayed regions represent temperatures beyond the military temperature range.

Copyright © Parallax Inc. Page 32 of 37 Rev 1.1 9/12/2008

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10.3. Current Consumption as a Function of Temperature

The following graph demonstrates the current consumption of the Propeller as a function of temperature. It is clear from the
graph that current consumption is nearly independent of temperature over the entire military temperature range.

Current Consumption vs Temperature

90

80
Spin
Waitloop
Assembly

70 waitloop
Spin

60
Current (mA)

50

40

30

20

10

0
-40 -20 0 20 40 60 80 100 120

Temperature (C)

Copyright © Parallax Inc. Page 33 of 37 Rev 1.1 9/12/2008

Propeller™ P8X32A Datasheet www.parallax.com

11.0 PACKAGE DIMENSIONS

11.1. P8X32A-D40 (40-pin DIP)

Copyright © Parallax Inc. Page 34 of 37 Rev 1.1 9/12/2008

Propeller™ P8X32A Datasheet www.parallax.com

11.2. P8X32A-Q44 (44-pin LQFP)

11.3. P8X32A-M44 (44-pin QFN)

Copyright © Parallax Inc. Page 35 of 37 Rev 1.1 9/12/2008

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Copyright © Parallax Inc. Page 36 of 37 Rev 1.1 9/12/2008

Propeller™ P8X32A Datasheet www.parallax.com

12.0 MANUFACTURING INFO 13.0 REVISION HISTORY

12.1. Reflow Peak Temperature 13.1.1. Changes for Version 1.1:
Section 11.3: P8X32A-M44 (44-pin QFN). Image
Package Type Reflow Peak Temp.
replaced to add stencil pattern diagram. New section
DIP 255+5/-0 °C inserted: 4.8 Assembly Instruction Execution Stages.
LQFP 255+5/-0 °C Contact Information updated.
QFN 255+5/-0 °C

12.2. Green/RoHS Compliance

All Parallax Propeller chip models are certified
Green/RoHS Compliant. The Certificate of Compliance
is available upon request and may be obtained by
contacting the Parallax Sales Team.

Parallax Sales and Tech Support Contact Information

For the latest information on Propeller chips and programming tools, development boards, instructional materials, and
application examples, please visit www.parallax.com/propeller.

Parallax, Inc. Phone: (916) 624-8333 Sales: sales@parallax.com

599 Menlo Drive Fax: (916) 624-8003 Tech Support: support@parallax.com
Rocklin, CA 95765 Sales: 1-888-512-1024 Web: http://forums.parallax.com
USA Tech Support: 1-888-997-8267 Object Exchange: http://obex.parallax.com

Copyright © Parallax Inc. Page 37 of 37 Rev 1.1 9/12/2008