Synchronization for QDPSK —Costas loop and Gardner

algorithm Using FPGAs

Jie Hua, Lingyun Zhou, Chang Chen, Lin Jiang

Key Laboratory of Electromagnetic Space Information, Chinese Academy of Sciences

University of Science and Technology of China
Hefei, China
jhua@mail.ustc.edu.cn

Abstract—This paper discusses the mathematical model and front-end. The entire design is completed by Verilog code
implements the physical verification when Carrier with IP core as few as possible to improve its portability.
synchronization (carrier loop) and Timing synchronization Corresponding design and optimization are made to achieve
(Gardner algorithm) working simultaneously. Firstly, a brief speed optimism. This paper is organized as follow. Section 2
analysis of the above mentioned systems is completed, and the provides an overview of carrier synchronization and timing
functional simulation is accomplished by Verilog HDL code on synchronization. Systematic analysis of the interaction
ModelSim platform. In addition, a systematic analysis is done for between carrier synchronization and timing synchronization
the workflow and interrelation of Carrier synchronization and when working simultaneously is shown in Section 3. In
Timing synchronization when both of them are active. Finally,
Section 4, veneer verification and practical demonstration of
we implement the hardware verification on the Stratix series
system-level are described. Finally, in Section 5 we draw the
field programmable gate array (FPGA) device
EP3SL150F1152C2N of Altera Company, and give the conclusions.
engineering results through the RF part and space transmission.
II. THE FUNCTIONAL VERIFICATION OF COSTAS
Keywords—Carrier synchronization, Timing synchronization, LOOP AND GARDNER ALGORITHM
FPGA For a digital communication system without pilot signal,
such as the QDPSK system, many ways can be used to
I. INTRODUCTION complete carrier and timing synchronization. All of them
In digital communication, in order to recover the utilize non-linear operations to extract synchronization
information from the received signal correctly, carrier and information based on the basic PLL model.
symbol timing recovery should be completed first of all.
A. Costas model and its functional verification
Analog, mixed or digital mode can be utilized in receiver.
But no matter analog mode or mixed mode, the imbalance In order to separate the corresponding carrier information
between in-phase branch and quadrature branch and the from the QDPSK received signal, the measure of non-linear
disadvantage of direct current zero excursions are existed [1]. processing and filtering is necessary. The common means
These problems can be avoided by using all-digital mode [2]. includes quadratic loop, in-phase and quadrature loop and
Due to the excellent performance, low power consumption decision feedback loop [5]. In-phase and quadrature loop can
and configurability, FPGAs have been widely used in many also be called Costas loop, which owns the advantage that it
sophisticated signal processing tasks [3]. can be easily implemented and the static phase error of the
recovered carrier wave is smaller. Its structure is shown in
The traditional model of Costas loop is analysed and Fig.1.
realized in [3] and [4] based on the situation that the decision
value is optimal. For Gardner algorithm, related analysis and Multi-stage Matched
Dataout _ I
8
verifications are proposed in [5] and [6] with no carrier wave Decimation filter filter
frequency offset or a stable phase offset. A corresponding Datain
solution is given in [7] to eliminate the impact of fixed carrier NCO Loop filter Phase detector

wave frequency offset. The output signals of carrier and Dataout _ Q

Multi-stage Matched
symbol timing synchronization are not ideal in the tracking Decimation filter filter
8

process when both of them working simultaneously, the

analyses in the above mentioned aren’t suitable. The related Fig. 1. Block diagram of Costas loop
mathematical analysis for this solution will be discussed in
The relevant content of mathematical analysis can be
this paper.
found in [4]. The detailed discussion of numerically
In this paper, we complete the functional verification in controlled oscillator (NCO) is provided both in [4] and [5].
Modelsim and physical verification in FPGA with X-band RF

978-1-4799-4860-4/14/$31.00 copyright 2014 IEEE

ICIS 2014, June 4-6, 2014, Taiyuan, China
 In view of the speed requirement of the system and the filter is 0.25, and the interpolation factor is 8. The structure is
limitation of the FPGA resources, the ordinary serial or shown in Fig.3.
parallel FIR filter isn’t suitable. Shift operation can be used as
a feasible solution to complete the multiplication of the filter Data_I Matched
Interpolator 2
Detect_I
coefficient and the input data. Every coefficient is converted filter

into the sum of 2i .

Timing Loop Timing Error
Controller filter Detector
N N
 Nk 
 n
y  h x n
k  k    2  x n  k 
i
(1) Data_Q
Matched Detect_Q
k 0  
k 0i 0  filter
Interpolator 2

Parameters of the signal model are listed in table 1 shown Fig. 3. Structure of Gardner algorithm
below.
Fig.4 shows the simulation result on the platform of
TABLE I. SIGNAL MODEL Modelsim. The impact of the loop bandwidth’s changing to
Gardner algorithm is identical to Costas loop. Due to the
carrier frequency 50MHz clock skew can’t be simulated in Modelsim, the relevant
content is introduced in the subsequent sections.
frequency offset 5 KHz
symbol rate 2Mbps
roll-off factor 0.25
sampling rate 200MHz

The functional simulation of Costas loop by Modelsim is

shown in Fig.2.
Fig. 4. Waveform of Gardner algorithm

III. THE ANALYSIS OF THE CORRELATION OF

CARRIER AND TIMING SYNCHRONIZATION
Each of carrier synchronization and timing
synchronization is analyzed based on the situation that the
other is ideal, however, this assumption doesn’t exist in reality.
The decision value isn’t the optimal one when the error signal
of timing loop isn’t stable, so we can’t get the accurate
Fig. 2. Waveform of Costas loop correction value of FCW. Similarly, the output signal of
Costas loop includes a time-varying frequency offset
On the basis of ignoring timing synchronization, Costas component. Although Gardner algorithm is insensitive to
loop’s tracking time is decided by the signal to noise ratio fixed carrier phase [6], the performance will significantly
(SNR) of input signal, loop filter’s parameters and the gain of deteriorate owing to a time-varying one. The structure of
NCO. The tracking time is proportional to the loop bandwidth, QDPSK synchronization is shown in Fig.5.
and the stability of loop filter output is inversely proportional
to the loop bandwidth. A detailed discussion of loop filter’s
parameters is included in [9]. Multi-stage
Decimation filter
Matched
filter
Interpolator 2
Data_I

B. Gardenr model and its functional verification Datain

NCO Loop filter
Phase Timing Loop Timing Error
detector Controller filter Detector
In order to decide which symbol was most likely to have
Data_Q
been sent, the accurate judgment clock should be extracted Multi-stage
Decimation filter
Matched
filter
Interpolator 2
correctly. Due to its simplicity and the characteristic
insensitive to phase offset, Gardner algorithm has been widely
used. Fig. 5. Structure of QDPSK synchronization

Similarly, the detailed mathematical analysis for Gardner Different with the general structure of QDPSK system, the
algorithm is given in [6]-[8]. An improved interpolator based output signals of timing synchronization instead of that of
on Farrow structure is proposed in [10] to improve the matched filters are used as the input signals of phase detector.
performance of cubic interpolator. In our simulation which is The error signal of the recovered carrier wave can be reduced
completed on the platform of Modelsim, the output signal of effectively, also the influence of the residual frequency offset
the matched filter is used as the input signal of our system. to Gardner algorithm.
The influence of frequency offset doesn’t exist in this moment. The equivalent representation of the signal prior to Costas
The symbol rate is 2Mbps, the roll-off factor of the shaping loop can be written as
    1       T  k   k 1 
r  t    I k g r  t  kT     cos ct 
 eG ideal
   I k h  T   k 1       I k h      
 k    4  k    k   2 2 
(2)
        T   
   Qk g r  t  kT     sin ct     Qk h  T   k 1       Qk h    k k 1    
 k     k    k   2 2 
(7)
     T  k   k 1 
   I k h  k       I k h      
where I k  and Qk  are the sequences of transmitted symbols,  k    k   2 2 
and c is the frequency of the carrier wave. A square-root      T     
raised-cosine pulse with the roll-off factor  is employed    Qk h  k       Qk h    k k 1     
 k    k   2 2   
for the baseband pulse g r  t  . T and  denote the symbol
period and the un-known time delay through the channel. In formula 8 we can find that each part of the error signal
is multiplied by a factor, and two additional units are
The FCW of both Costas loop and Gardner algorithm are
included.
updated for every T .The frequency associated with the k th
symbol is c  k . The signals after down-conversion and
matched filter are given by

1   
yI  t      I k h  t  kT     cos  k t 
2  k   
(3)
1   
    Qk h  t  kT     sin  k t 
2  k   

1    Fig. 6. Waveform of QDPSK synchronization

yQ  t      I k h  t  kT     sin  k t 
2  k   
(4) Fig.6 shows the functional simulation result of QDPSK
1    when carrier and timing synchronization working
    Qk h  t  kT     cos  k t 
2  k    simultaneously. As can be seen, there is a significant addition
to the tracking time of both carrier and timing synchronization,
where the pulse of h  t  becomes a raised-cosine one. and an apparentdecreasing to the stability of the two error
signals. The phenomenon also verifies the correctness of the
The ideal output error signal of the Costas phase detector
above mentioned analysis.
can be written as
IV. PHYSICAL IMPLEMENTATION OF QDPSK
1     
eC     I k h  0    Qk h  0   cos  2k  kT    (5) COMMUNICATION SYSTEM
ideal
4  k     k   
In Section 3, the interaction of carrier and timing
the value is only decided by the frequency offset k . synchronization is given when they working simultaneously,
However, the recovered time delay  k isn’t equal to  when also the functional simulation by Verilog HDL code on
Gardner algorithm is in the state of tracking, which leads to Modelsim platform. In the following paragraphs, we give both
the phenomenon that the feedback of NCO is far away from veneer and system-level physical implementation.
the ideal one eC ideal . It reduces the convergence speed of Costas
A. Veneer implementation
loop even leads to divergence. The actual output is shown in
formula 6. Under the circumstance of veneer implementation, the
modulation and demodulation algorithm of QDPSK are
1   
2
    
2
working simultaneously in a same FPGA development board
eCostas     I k h  k       Qk h  k     sin  2k  kT   k  
8   k    k    without clock skew.
(6)
1     
     I k h  k      Qk h  k     cos  2k  kT   k  
4   k    k  

Formula 7 shows the ideal output signal of Gardner

timing-error detector. In which the estimated time delay is the
unique variable. The phase of the recovered carrier wave isn’t
fixed when Costas loop is in the process of tracking in
practice. The situation that the carrier frequency offset of the
k th symbol isn’t equal to that of the k  1 th symbol will
leads to a great modification to the ideal error signal eG ideal .
Similarly, the convergence speed of Gardner algorithm is Fig. 7. Structure of veneer verification
substantially slowed down.
 1       T  k   k 1       T    k 1      T   
eGardner
   I k h  T   k 1       I k h           Qk h  T   k 1      Qk h    k       cos  k 1   k 1 k 
4   k    k   2 2    k    k   2 2     2 2 
1       T    k 1       T    k 1      T   
    I k h  k       I k h    k        Qk h  k       Qk h    k       cos  k  k 1  kT  k   k  k 1   k 1 k 
4   k    k   2 2    k    k   2 2     2 2 
(8)
1       T  k   k 1       T  k   k 1      T  k 1   k  
    I k h  T   k 1       Qk h           Qk h  T   k 1       I k h          sin  k 1  
4   k    k   2 2    k    k   2 2     2 2  
1       T    k 1       T    k 1      T    
    I k h  k       Qk h    k        Qk h  k       I k h    k       sin  k  k 1  kT  k   k  k 1   k 1 k  
4  k    k   2 2    k    k   2 2     2 2 

The structure of veneer verification is shown in Fig.7. The Here, we also use the same parameters to those in table 1.
output digital signal of modulation is converted to an analog In order to estimate the quality of received signal, its
one through D/A, and then through A/D to be the input digital time-domain waveform and constellation diagram are
signal of demodulation. measured by specialized instruments as shown in Fig.10 and
Fig.11.
The parameters used in this section are same with those
used in Section 3. Fig.8 shows the simulation result of veneer
implementation.
In this system, only phase offset is existed between the
baseband clock of modulation and demodulation which means
that the time delay  is constant. A frequency offset of 5 KHz
is added to initial carrier wave artificially. With only the
influence of quantization noise, the bit error rate (BER) is low
to 0. At the same time, the frequency jitter of the recovered
signal of carrier wave and baseband clock is 0.0023% and
0.0007% respectively. Fig. 10. Time-domain waveform

B. System-level implementation
In order to build a similar model with the actual
communication system, X-band RF front-end circuits are
introduced in our system-level implementation. The structure
is shown in Fig.9.

Fig. 11. Constellation

Due to that the signal is transmitted through X-Band

front-end and free-space channel, there is a great degeneracy
to the quality of the received signal. The signal to noise ratio
(SNR) is about 20dB, the value of error vector magnitude
(EVM) is increased to 9.49%, and the frequency offset is up
Fig. 9. Structure of system-level verification to 5.2 KHz.

Fig. 8. Waveform of veneer verification

 Fig. 12. Waveform of system-level verification

Fig.12 shows the system-level implementation result. Due REFERENCES

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