Sr. IC Layout Designer

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7217 Lady Luck Ct.

Colorado Springs, CO 80923-5821


Home: 719-488-9957 Cell: 719-238-7734
Objective: I am interested in opportunities for a contract as a Senior Mask Desi
gn Specialist..
Experience: Twenty six years designing full custom analog, mixed signal, high sp
eed, and memory layout. More than a decade of experience in using Cadence Virtuo
so, Virtuoso XL, and Assura.
Senior Mask Design Specialist March 2007 to November 2008
Linear Technologies Inc, Colorado Springs, CO.
Full custom analog and mixed signal layout on Cadence Virtuoso and Cadence Virt
uoso XL tools. DRC and LVS verification using Dracula and Assura tools.
Senior Mask Design Specialist March 2006 to March 2007
Agilent Technologies, Colorado Springs, CO.
Performing full custom Bi-CMOS and CMOS layout design for high speed IC test te
chnology using Cadence Virtuoso XL, Mentor Calibre, and Assura tools.
Senior Mask Design Specialist July 1996 to March 2006
Microchip Technologies Inc., Mountain View, CA
Full custom analog and mixed signal layout on Cadence tools. DRC and LVS verifi
cation using Avanti/Hercules tools. Train junior layout designers.
Senior Layout Designer October 1995 to July 1996
National Semiconductor, Santa Clara, CA
Full custom analog and mixed signal layout on Cadence tools. DRC and LVS verifi
cation using Dracula.
Senior Layout Designer December 1993 to October 1996
Media Vision, Fremont, CA
I was instrumental in starting the IC design division at Media Vision, designin
g full custom analog and mixed signal layout on Cadence tools. DRC and L VS veri
fication using Dracula.
Graphic Design Manager May 1992 to December 1993
Sierra Semiconductor, San Jose, CA
I supervised two senior layout designers while producing exceptional and innova
tive full custom mixed signal layout design in support of the Analog Design Grou
p using Compass tools for layout, DRC and L VS verification.
Senior Layout Designer May 1986 to May 1992
Sierra Semiconductor, San Jose, CA
Full custom analog and mixed layout designs from schematic to tapeout. Many des
igns in support of R&D or product development efforts.
Layout Designer October 1982 to May 1986
Teledyne Semiconductor, Mountain View, CA
I was hired by Teledyne after graduating from the Institute for Business and Te
chnology in San Jose, CA. at the top of my class. While at Teledyne, I progresse
d to a senior skill level.

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