Scribd
Upload
162 views5 pages

NMOS Fabrication: Step 1: Processing The Substrate

The NMOS fabrication process involves 8 steps: 1) Creating a p-type silicon substrate with boron impurities. 2) Growing a silicon dioxide layer on the substrate to prevent contamination. 3) Applying a photoresist material on the silicon dioxide layer to enable patterning. 4) Etching exposed regions of the photoresist to pattern the layers. 5) Forming a polysilicon gate structure through chemical vapor deposition. 6) Creating n-type source and drain terminals through diffusion of impurities. 7) Depositing more silicon dioxide and photoresist to protect the terminals. 8) Depositing an aluminum metal layer to form interconnects.

Uploaded by

chinthala santhosh srk
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
162 views5 pages

NMOS Fabrication: Step 1: Processing The Substrate

The NMOS fabrication process involves 8 steps: 1) Creating a p-type silicon substrate with boron impurities. 2) Growing a silicon dioxide layer on the substrate to prevent contamination. 3) Applying a photoresist material on the silicon dioxide layer to enable patterning. 4) Etching exposed regions of the photoresist to pattern the layers. 5) Forming a polysilicon gate structure through chemical vapor deposition. 6) Creating n-type source and drain terminals through diffusion of impurities. 7) Depositing more silicon dioxide and photoresist to protect the terminals. 8) Depositing an aluminum metal layer to form interconnects.

Uploaded by

chinthala santhosh srk
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 5

NMOS Fabrication

The doping on the NMOS will be a Pentavalent (five valence electrons) impurity, such
as boron and antimony. It has a p-substrate on which the n-type channel is created.
As the name implies, the majority carriers participating in the current are electrons.
The movement of electrons is fast as compared to the holes. Thus, NMOS is faster
than the PMOS.

The NMOS fabrication includes eight steps, which are listed as follows:

Step 1: Processing the substrate


The first step is to create a p-type substrate. The p-type has trivalent impurities
(three valence electrons), such as boron with a concentration upto 1016/cm 3. A pure
thin film of the silicon wafer is selected on which the p-type impurities are applied as
crystals. The diameter of the wafer can be upto 0.15m or 150mm. The chosen wafer
material is silicon because it is a clean and high-quality semiconductor material
preferred for fabrication.

Step 2: Silicon dioxide layer


Silicon dioxide is made up of two materials silicon (Si) and oxygen (O 2). It is also
known as oxide. Silicon has a stable structure and is considered as the most
abundant metal available on the Earth. It is combined with oxygen that acts as an
insulator or conductor under various conditions.
SiO2 layer is grown over the surface of the p-type substrate to prevent it from
external factors. It also acts as a barrier to the dopants applied on the layer during
the processing. The silicon dioxide thickness is very small, around 0.000001m or 1um.

Step 3: Photoresist material is applied on the SiO2 layer


The silicon dioxide layer is covered with the photoresist material. It is a light-
sensitive material that forms the coating over the surface of the SiO 2 layer. It is
useful in reducing the size of the transistors.

After the photoresist is applied on the silicon dioxide layer, a mask with the desired
pattern is used as a medium to expose UV (Ultra-Violet) lights. The UV light through
the mask reaches the photoresist material. The exposed resist remains on the surface
and the unexposed part is removed from the surface.

Step 4: Etching the regions


The unexposed window is removed from the surface and the regions are etched
together to form a clean wafer surface. It is shown below:
Step 5: Formation of Gate
The remaining photoresist layer is removed from the wafer. A thin silicon dioxide
layer of 0.0000001m or 0.1 um is grown over the surface. The polysilicon is further
added to the surface that forms a gate structure, which is deposited by CVD process.
The Chemical Vapor Deposition produces solid materials of high quality. The
polysilicon is preferred for the gate because of its high melting point. Its properties
are also similar to that of SiO2.

Note: The number of doping concentrations, the thickness of the layer, and the resistivity
are the three essential elements to be considered for the fabrication process.

Step 6: Creating the area for drain and source terminals


The thin oxide layer on the surface of the silicon wafer is removed and the n-type
impurities are inserted with the help of the diffusion process in the specified exposed
area. It forms the n-channel at the source and drain terminals. The wafer is first
heated at a very high temperature and the gas in passed into it. The area exposed is
filled with the gas containing n-type impurities, such as phosphorous.

Step 7: SiO2 and photoresist is again deposited on the source


and drain terminals
The same process is again carried to protect the S and D terminals. The oxide layer
was removed from the surface of the wafer to create the two terminals, as discussed
in step 6. The silicon dioxide and the photoresist are deposited, etched, and masked
to protect it. The contact holes are left exposed for the connections.

Step 8: Making of the metal layer


It is almost the last step of the NMOS fabrication process. The metal layer of
aluminum is deposited on the surface of wafer including the contact holes. The
thickness of the aluminum is around 1um. The metal layer is further masked and
etched to form the required interconnection pattern.

The layer of different materials was applied to the silicon wafer at each step. Thus,
the NMOS fabrication process involves the deposition of four major layers. It includes
silicon dioxide, photoresist, polysilicon, and the aluminum metal layer.

Let's discuss some terms used above in detail.

Masking: The masking term was used after the layers SiO 2, photoresist, and the
aluminum layer. Making is defined as a process of converting the 3D CAD design to
the actual layer deposited on a material. It transfers the 3D design to the layer, which
is deposited on the surface of the silicon wafer. It is also used to create a pattern on
the surface. The CAD (Computer Aided Design) allows the deposition of layers on
various wafers with accurate design and length. It is useful in large chip
manufacturing processes.

Etching: Etching is also used to create a pattern on the substrate or the surface of


the wafer. But, it first removes the material from the layer, and creates a pattern from
the same material. It enhances the contrast or context of the surface.
We know that different layers of SiO 2, photoresist, polysilicon, and metal were
deposited on the surface of the substrate. The etching process removes the
unwanted or extra material from the surface to from holes. The holes can be used for
diffusion or for electrical interconnections.

You might also like