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Sl No. Contents Page Number

1. What is FPGA? 3

2. History of Evolution 3

3. FPGA Programmability 6

4. FPGA Architecture 9

5. Why FPGA 14

6. FPGA Drawbacks 15

7. Application 15

8. Conclusion 15

9 Referrences 16

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What is FPGA?

Ans. It is an IC(Integrated Circuit)

with a very high logic capacity
Completely programmable even after the a product is shipped or in the
“field” so the name is given.

FPGAs belong to a class of devices named as

FPD(field programmable device) or
PLD(programmable logic devices)

This paper provides a tutorial survey of architectures of commercially available high-capacity

field-programmable devices (FPDs). We first define the relevant terminology in the field and
then describe the recent evolution of FPDs. The three main categories of FPDs are delineated:
Simple PLDs (SPLDs), Complex PLDs (CPLDs) and Field-Programmable Gate Arrays
(FPGAs). We then give details of the architectures of FPGA.

Before proceeding, we provide definitions of the terminology in this field. This is necessary
because the technical jargon has become somewhat inconsistent over the past few years as
companies have attempted to compare and contrast their products in literature.

• Interconnect — the wiring resources in an FPD.

• Programmable Switch — a user-programmable switch that can connect a logic element to an
interconnect wire, or one interconnect wire to another
• Logic Block — a relatively small circuit block that is replicated in an array in an FPD. When a
circuit is implemented in an FPD, it is first decomposed into smaller sub-circuits that can each
be mapped into a logic block. The term logic block is mostly used in the context of FPGAs, but
it could also refer to a block of circuitry in a CPLD.
• Logic Capacity — the amount of digital logic that can be mapped into a single FPD. This is
usually measured in units of “equivalent number of gates in a traditional gate array”. In other
words, the capacity of an FPD is measured by the size of gate array that it is comparable to. In
simpler terms, logic capacity can be thought of as “number of 2-input NAND gates”.
• Logic Density—the amount of logic per unit area in an FPD.
• Speed-Performance — measures the maximum operable speed of a circuit when implemented
in an FPD. For combinational circuits, it is set by the longest delay through any path, and for
sequential circuits it is the maximum clock frequency for which the circuit functions properly.

History of Evolution:

The evolution of FPGA goes like this

PROM PLA PAL CPLD FPGA

Programmable Read Only Memory (PROM)

The first type of user-programmable chip that could implement logic circuits was the
Programmable Read-Only Memory (PROM), in which address lines can be used as logic circuit

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inputs and data lines as outputs. Logic functions, however,

rarely require more than a few product terms, and a PROM contains a full decoder for its address
inputs.

Problem
large area is required due to the decoder used.

PROMS are thus an inefficient architecture for realizing logic circuits, and so are rarely used in
practice for that purpose.

The first device developed later specifically for implementing logic circuits was the Field
Programmable Logic Array (FPLA), or simply PLA for short.
Programmable Logic Array (PLA)

A PLA consists of two levels of logic gates: a programmable “wired” AND-plane followed by a
programmable “wired” OR-plane. A PLA is structured so that any of its inputs (or their
complements) can be AND’ed together in the AND-plane; each AND-plane output can thus
correspond to any product term of the inputs. Similarly, each ORplane output can be configured
to produce the logical sum of any of the AND-plane outputs. With this structure, PLAs are well-

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suited for implementing logic functions in sum-of-products form. They are also quite versatile,
since both the AND terms and OR terms can have many inputs (this feature is often referred to as
wide AND and OR gates).
Advantage
No decoder required
Problem
Two levels of programming adds delay and increases cost.

To overcome these weaknesses, Programmable Array Logic (PAL) devices were developed.

Programmable Array Logic (PAL)

As Figure 1 illustrates, PALs feature only a single level of programmability, consisting of a
programmable “wired” ANDplane that feeds fixed OR-gates. To compensate for lack of
generality incurred because the OR plane is fixed, several variants of PALs are produced, with
different numbers of inputs and outputs, and various sizes of OR-gates. PALs usually contain
flip-flops connected to the OR-gate outputs so that sequential circuits can be realized.

Advantage
Low cost and size.
Problem
Less flexible than PLA

All these PLA and PAL are Simple Programmable Logic Devices (SPLD). whose most
important characteristics are low cost and very high pin-to-pin speed-performance.

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Common Problem:
As technology has advanced, it has become possible to produce devices with higher capacity
than SPLDs. The difficulty with increasing capacity of a strict SPLD architecture is that the
structure of the programmable logic-planes grow too quickly in size as the number of inputs is
increased.

The only feasible way to provide large capacity devices based on SPLD architectures is
then to integrate multiple SPLDs onto a single chip and provide interconnect to programmably
connect the SPLD blocks together. Many commercial FPD products exist on the market today
with this basic structure, and are collectively referred to as Complex PLDs (CPLDs).

Structure
programmably interconnect multiple SPLDs.
advantage
logic capacity up to the equivalent of about 50 typical
SPLD devices
Problem :
Extending to higher density difficult

All the previous devices indicates that the complte solution would be a
Very high capacity device with wide range of programmability.

Then FPGA came into the picture.

FPGA PROGRAMMABILITY

Programmability of FPGA is achieved in three ways

 Antifuse programming methodology
 SRAM programming technology
 Floating Gate Programming

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Antifuse programming methodology

Here Antifuse systems(eg. amorphous Si,ONO) are placed at the junctions of different
connecting paths.
These systems(built of special materials normally have high resistance(effectively open
circuits)
Upon application of programming voltage across them resistance drop to a
few ohms and thus define a connection.

Many antifuse systems are based on amorphous silicon, which has high
resistivity, but which, after heating, recrystallizes and drops its resistivity
substantially. An example of this type of antifuse is given by Roesner (U.S.
Pat. No. 4,796,074 January 1989). Other types of material mentioned by
Roesner include germanium, carbon and tin and all depend on a change in
grain size from amorphous, or very small crystallites, to relatively large
grains. An additional drop in resistivity is achieved by the activation of
interstitial dopant atoms (such as might be introduced through ion
implantation). Thus Roesner teaches that the maximum temperature to
which antifuse material may be exposed during processing must be less than
about 600° C.

t should also be mentioned that there is at least one alternative antifuse

system to the amorphous semiconductor variety discussed above. This is one
that is based on oxide-nitride-oxide (ONO). ONO comprises a structure of
three layers--silicon oxide, silicon nitride, and silicon oxide. When such a
structure is subjected to a suitable applied voltage (typically about 16 volts)
its resistance changes from about 1012 ohms to about 500 ohms.
Advantage:
Small size
Low series resistance and low parasitic capacitance
Disadvantage:

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 Interconnect is not reprogrammable .Once the antifuse is programmed it is not available
for programming again.

SRAM programming technology

Loads and stores values in SRAMs to facilitate programmability.For example if the sram cell
shown in figure 1 stores the value of 1 the MOS gate is ON and in the 2nd case the two SRAM
cells together selects a particular i/p to the MUX as its

o/p.
In short ,
to control pass gates.
1= closed switch connection
0= open
For mux, SRAM determines
the mux input selection
process.
Advantage
• Fast re-programmability.As reprogramming only require the write operation to the
SRAM.
• Standard IC fabrication Tech. is used by using predesigned standard for SRAM.
Disadvantage
• SRAM volatile so every time when the device starts SRAM needs to be loaded.
• Requires large area

Floating Gate Programming

Technology used used in EPROM and EEPROM devices is used here Switch is disable by
applying high voltage to gate-2 between gate-1 and drain.This process stores an amount of
charge on the floating gate.As it is surrounded by an insulating layer of SiO2 so the charge
deposited remains there.
For reprogramming the charge is removed by applying UV light.Tat supplies enough
energy to the charge stored to escape through the oxide layer.
Advantage:-

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 No external permanent memory is needed to program it at power-up

Disadvantage:-
 Extra processing steps as floating gate is involved.
 Static power loss due to pull up resistor and high on resistance

FPGA architecture

There are three primary configurable elements in FPGA

1) Configurable Logic Block(CLB)
-implement different functions.

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2) Input/Output Block(IOB)
- provides the interface between external pins and internal signal lines
3)Programmable Routing
Channel
-controls the connections among different blocks

Configurable Logic Block(CLB)

CLBs contain
• 3 Look Up Table(F,G &H function generator)
• Two D Flip-Flops
And
• A group of MUXs
• Look Up Table
• Can perform any function on its i/p depending on the values stored in the
memory location.
• Combination of F,G & H allows to implement a function of upto 9 variables.
• Advantage:
• Minimizes no. of blocks required
• Thereby increases speed and density
•

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 • D Flip-Flop
• 2 edge triggered Flip-Flops are having common clock & clock enable i/ps
• Clock may be inverted before driving Flip-Flops thus configuring them as
either positive or negative edge triggered.
• Clock enable i/p to Flip-Flop is active high.
• Set-Reset i/p allows to set or reset Flip-Flops asynchronously.
MUX
Used to allow the intended signal to go to the next stage.
Allows the combinational functions o/p that is F,G or H o/p to be o/p of the
CLB through X or Y
Controls the D Flip-Flop i/p (allows F,G or H o/p or a direct input to CLB as
DIN to go to the i/p of d Flip-Flop)
Determines triggering edge of the clock.

Input/Output Block(IOB)

Two types of IOBs are there

1)Dedicated for configuration of FPGA
2)User Configurable
User configurable IOBs can be configured as i/p,o/p or bidirectional for providing
connections of internal CLBs to external package pins
INPUT BLOCK
 The i/p signal can directly go to routing channel or it can go via i/p register
 I/P register can be level or edge sensative
 Clock can be direct or inverted
 Registered data path has one tap delay element to adjust set up or hold time
of Flip-Flops.

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The global tri state signal puts the out put drive to tri state so that while programming the
selected unit does not effects the others .

OUTPUT BLOCK
• CLB o/ps can be inverted and go directly or via a register to the o/p buffer
• user controlled T i/p ORing with GTS(Global Tri Sate)signal controls o/p buffer(e.g-if
high ,places buffer in high impedence state)
• GTS which is common to all user IOBs is made high during configuration
• Programmable pull up or down netwrk is there for connecting unused pin to Vcc or GND.
Programmable Routing Channel

Routing Channel-metallic conductor used to make connection

Three types are there
CLB Routing Channel:-runs along each row and columns of CLBs.
IOB Routing Channel:-forms Versa Ring outside CLB array & connects IOB with CLB
routing channels.
Global Routing Channel:-routs global signals (eg. Clock) with minimum delay.
Programmability in routing channels is obtained by using :- (a)connection box and
(b)switch box

Connection Box:- The C boxes connect the channel wires with the input and output pins of the CLBs. It
has two major properties that can affect the routability of a design: its flexibility, Fc, which is the number
of wires that each logic block pin can connect to; and its topology, which
is the pattern of switches2 that make the connection (especially if Fc is low).

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Switch Box:- The S boxes allow wires to switch between vertical and horizontal wires. Its flexibility,
Fs, defines for a wiring segment entering the S block the number of other wiring segments it can be
connected to. The topology of the S blocks is very important since it is possible to
choose two different topologies with the same flexibility Fs that result in very different routabilitiesallow
wires to switch between vertical and horizontal wires.

Routing channels may be of three types

(a)Single length,(b)double length & (c)long lines

 Single length lines span through one CLB & provide short connections among CLBs

 Double length line spans two CLBs,offers low routing delay.

Long lines run along entire length or width of the array . They are appropriate for connections that
require reaching several CLBs with low-skew.

Thye basic structure of connection box and switching boxes are same as illustrated next.

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 Interconnect Point in both switching and connection box –implemented through 6 pass
transistors. Depending on the values provided by the particular type of programming
technique used the i/p to the pass gates control the routiong of the signals through the
boxes.

Why FPGA??

 In the field FPGA has strong opponent in the form of ASIC(application Specific IC).
 ASICs are designed to perform a particular function using custom design technique.

FPGA Advantages
 FPGAs are flexible,can be used for prototyping. That is it can be used for prototype
making of large devices and ICs.
 Offers less time-to-market.That is the time required to deliver an ordered FPGA is
smaller than ASICs as it only requires programming.
 NRE cost is low.
 Design cycle is simple
 Easy upgrades like software as it provides a provision for reprogramming so depending
on the need it can be upgraded like softwares.

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 FPGA drawbacks

 FPGAs are lagging in some fields while compared to ASICs

1) ASICs are specifically designed for some purpose, so are faster than FPGAs.As they are
made to the task in the most efficient way
2) ASICs require less power than FPGAs.
3) ASICs are cost effective for very large volume design. As if we use FPGAs here it would
in would increase both delay and cost,More over many of the available sections of
FPGAs would not be used as they may not be required.So it will result in inefficiency.

Application

 Applications of FPGAs include

(a)digital signal processing,
(b)aerospace and defense systems,
(c)ASIC prototyping,
(d)medical imaging,
(e)metal detection
and a growing range of other areas.
The inherent parallelism of the logic resources on an FPGA allows for considerable
computational throughput. This has driven a new type of processing called reconfigurable
computing, where time intensive tasks are offloaded from software to FPGAs
Reconfigurable computing is a computing paradigm combining some of the
flexibility of software with the high performance of hardware by processing with
very flexible high speed computing fabrics like FPGAs. The principal difference when
compared to using ordinary microprocessors is the ability to make substantial
changes to the datapath itself in addition to the control flow. On the other hand, the
main difference with custom hardware (ASICs) is the possibility to adapt the
hardware during runtime by "loading" a new circuit on the reconfigurable fabric..

Conclusion

 Choice of ASICs or FPGAs are completely case dependent

 For a good design technique and implementation a perfect mixture of both will ensure the
optimum profitability and performance.

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Referrences

 Books
CMOS VLSI DESIGN
-by NEIL H.E. WESTE
DAVID HARRIS
AYAN BANERJEE
FPGA-Based System Design
-by WAYNE WOLF
 Websites
1.http://www.wikipedia.org
2.http://searchcio-midmarket.techtarget.com
3.http://www.vlsibank.com
4.http://web.ukonline.co.uk
5.http://www.electronicsweekly.com

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