Third national Conference on Modern Trends in Electronic Communication & Signal processing 2013

Implementation of BIST Structure using

VERILOG for VLSI Circuits
Susha C Baby1, Denna Markose2, Lincy George3
P.G Scholar ,BPC College Piravom1,2, Assistant Professor Dept. of Electronics BPC College Piravom3
Sushababy3@gmail.com1,dennaam@gmail.com2,lincyshibupaul@gmail.com3

Abstract— Very Large Scale Integration (VLSI) has made a dramatic impact on the growth of
integrated circuit technology. It has not only reduced the size and the cost but also increased the
complexity of the circuits. The positive improvements have resulted in significant performance/cost
advantages in VLSI systems. There are, however, potential problems which may retard the effective
use and growth of future VLSI technology. Among these is the problem of circuit testing, which
becomes increasingly difficult as the scale of integration grows. Because of the high device counts
and limited input/output access that characterize VLSI circuits, conventional testing approaches
are often ineffective and insufficient for VLSI circuits. Built-in self-test (BIST) is a commonly used
design technique that allows a circuit to test itself. BIST has gained popularity as an effective
solution over circuit test cost, test quality and test reuse problems. In this paper we are presenting
an implementation of a tester using VERILOG.

Keywords – VLSI, BIST

I. Introduction a linear feedback shift register (LFSR) to

generate the test vectors and multiple input
BIST is a DFT technique in which testing is
signature register (MISR) to verify the output
accomplished through built in hardware. The
against the correct response of the circuit under
basic idea is to have a VLSI chip that tests
test.
itself. The typical BIST architecture is
composed of three hardware modules in A. BIST Architecture
addition to the circuit under test (CUT), as
shown in Figure 1. The Test Pattern Generator
(TPG) generates the test patterns for the CUT.
The Output Response Analyzer (ORA)
compares or analyzes the test responses to
determine correctness of the CUT. The BIST
controller is the central unit to control all the
BIST operations including initialization and
length of the BIST sequence. In a BIST system
hierarchy, often there are BIST controllers at
each level of the circuit hierarchy, such as
module, chip, board, and system levels. Each
BIST controller is responsible for the self-test
in that particular level, the control of BIST
operations for the lower level BIST, and the
reporting of the test results to the upper level. Figure1: Block Diagram OfBist
The design of a TPG is determined by the test
A. Linear Feedback Shift Register
strategy being deployed. The test strategy being
selected is determined by the fault coverage, LFSR is an n-bit shift register which pseudo-
test hardware overhead, and testing time Fig.1 randomly scrolls between 2n-1 values, but does
shows a simple BIST block diagram which uses it very quickly because there is minimal

Department of Electronics, BPC College, Piravom

 Third national Conference on Modern Trends in Electronic Communication & Signal processing 2013

combinational logic involved. The all zeros tick

case is not possible in this type of LFSR, but 1 1 1 1 1 1
the probability of any bit being "1" or "0" is 2 0 1 1 1 1
3 0 0 1 1 1
50% except for that. Therefore, the sequence is 4 0 0 0 1 1
pseudorandom in the sense that the probability 5 1 0 0 0 1
of a "1" or "0" is approximately 50%, but the 6 1 1 0 0 0
sequence is repeatable. Like a binary counter, 7 0 1 1 0 0
all 2n -1 states are generated, but in a “random” 8 1 0 1 1 0
order that is repeatable. The exclusive-OR gates 9 1 1 0 1 1
10 1 1 1 0 1
and shift register act to produce a
11 0 1 1 1 0
pseudorandom binary sequence (PRBS) at each 12 1 0 1 1 1
of the flip-flop outputs. By correctly choosing 13 0 1 0 1 1
the points at which we take the feedback from 14 1 0 1 0 1
an n -bit shift register we can produce a PRBS 15 0 1 0 1 0
of length 2n – 1, a maximal-length sequence 16 0 0 1 0 1
that includes all possible patterns (or vectors) of 17 0 0 0 1 0
18 0 0 0 0 1
n bits, excluding the all-zeros pattern. In an 19 1 0 0 0 0
LFSR, the bits contained in selected positions 20 0 1 0 0 0
in the shift register are combined in some sort 21 0 0 1 0 0
of function and the result is fed back into the 22 1 0 0 1 0
register's input bit. 23 0 1 0 0 1
24 1 0 1 0 0
Register bits that do not need an input tap, 25 1 1 0 1 0
operate as a standard shift register. It is this 26 0 1 1 0 1
feedback that causes the register to loop 27 0 0 1 1 0
through repetitive sequences of pseudo-random 28 1 0 0 1 1
value. The choice of taps determines how many 29 1 1 0 0 1
30 1 1 1 0 0
values there are in a given sequence before the 31 1 1 1 1 0
sequence repeats. The implemented LFSR uses 32 1 1 1 1 1
a one-to-many structure, rather than a many-to-
one structure, since this structure always has the B. Signature Analysis
shortest clock-to-clock delay path. The
feedback is done so as to make the system more Signature Analysis is a compression technique
stable and free from errors. Specific taps are based on the concept of cyclic redundancy
taken from the tapping points and then by using checking. The good and faulty circuits produce
the XOR operation on them they are feedback different signatures. Test Patterns for BIST can
into the registers. Here is an illustration using 5 be generated at-speed by an LFSR with only a
bit LFSR. clock input. The outputs of the circuit-under-
test must be compared to the known good
response. In general, collecting each output
response and of loloadingit from the circuit
under test for comparison is too inefficient to be
practical. The general solution is to compress
the entire output stream into a single signature
Figure 2 :5 Bit Lfsr value. The commonly seen test strategies are,

Table 1: Output Of A 5 Bit Lfsr a.Stored Patterns

Clock Out[0] Out[1] Out[2] Out[3] Out[4]

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 Third national Conference on Modern Trends in Electronic Communication & Signal processing 2013

Stored-pattern approach stores the pre- of a serial input signature register can be
generated test patterns to achieve certain test extended to multiple-input signature register
goals. It is often found in system level testing (MISR). There are several ways to connect the
such as the power-on self test of a computer and inputs of LFSRs to form an MISR..Since the
microprocessor functional testing using micro XOR operation is linear and associative, (A
programs. xorB) xorC = A xor(B xorC), as long as the
result of the additions are the same then the
b.Exhaustive Testing
different representations are equivalent. If we
Exhaustive testing applies all possible input have an n -bit long MISR we can accommodate
combinations to the circuit under test (CUT). It up to n inputs to form the signature. If we use m
guarantees that all detectable faults that do not < n inputs we do not need the extra XOR gates
produce sequential behaviour will be detected. in the last n– m positions of the MISR. MISR
The strategies are often applied to complicated reduce the amount of hardware required to
and well isolated small modules such as PLAs. compress a multiple bit stream. LFSR and/or
c.Pseudorandom Testing: MISR circuit is implemented using a memory
already existing in a circuit to be tested.
Pseudorandom testing applies a certain length
of test patterns with certain randomness
property. The sequences of test patterns are in a
deterministic order. The fault coverage is
determined by the test length and the contents
of the patterns.
d.Weighted Pseudorandom Testing:
Weighted pseudorandom testing applied Figure 3:5bit:misr
pseudorandom patterns with certain 0s and 1s
distribution to handle the random pattern B. Fault Detection Using Misr
resistant faults undetectable by the Consider the circuit shown in figure. Here we
pseudorandom testing. It can effectively shorten consider a gray to binary converter as circuit
the test length. under test. We have five input bits and five
e.Pseudo exhaustive Testing: output bits for the given circuit to be tested. So
we design an LFSR with five output bits to
Pseudo exhaustive testing partitions the CUT generate the test vectors. The output of the
into several smaller sub circuits and tests each LFSR is given to the circuit under test and the
of them exhaustively. All detectable faults output is recorded.
within the sub circuits can be detected.
However, such a method requires extra design
effort to partition the circuits and deliver the
test patterns and test responses. BIST is a set of
structured-test techniques for combinational
and sequential logic, memories, multipliers, and
other embedded logic blocks. BIST is the
commonly used design technique that allows a
circuit to test itself.
A. MISR - Multiple-Input Signature
Register
Figure 4:circuit under test
A serial-input signature register can only be
used to test logic with a single output. The idea

Department of Electronics, BPC College, Piravom

 Third national Conference on Modern Trends in Electronic Communication & Signal processing 2013

18 00001 00001 01101

Table 2:Response of fault free circuit 19 10000 11110 11001
Clock LFSR CUT MISR Signature 20 01000 01110 01100
tick output output output 21 00100 00110 01000
1 11111 10101 00000 22 10010 11100 00010
2 01111 01010 10101 23 01001 01111 11101
3 00111 00101 11110 24 10100 11000 11111
4 00011 00010 01010 25 11010 10010 01001
5 10001 11110 00111 26 01101 01001 01000
6 11000 10000 00011 27 00110 00100 01101
7 01100 01000 01111 28 10011 11101 11100
8 10110 11011 10001 29 11001 10001 10011
9 11011 10010 01101 30 11100 10110 00110
10 11101 10110 01010 31 11110 10100 10101
11 01110 01011 10011
12 10111 11010 11100
13 01011 01101 10100 We can see that the signature values computed
14 10101 11001 00111 for correct and faulty circuit are different.
15 01010 01100 00100 Hence we can conclude that verifying the
16 00101 00110 01110 10101 signature of a circuit, on applying the complete
17 00010 00011 00001 pseudo random binary sequence, to the
18 00001 00001 11101
signature value computed earlier or generated
19 10000 11111 10001
20 01000 01111 01001 by a fault free circuit is sufficient to determine
21 00100 00111 10101 whether the circuit is faulty or operating
22 10010 11100 10011 correctly. The MISR propagates the fault from
23 01001 01110 01011 the clock cycle where it appeared first till the
24 10100 11000 10101 end of the input sequence with the help of the
25 11010 10011 01100 feedback. The test pattern can be repeated after
26 01101 01001 10101
resetting the multiple input signature register.
27 00110 00100 11101
28 10011 11101 10100 When the test pattern is repeated, the responses
29 11001 10001 10111 remain the same as long as the fault is present.
30 11100 10111 00100 When fault is detected in an IC right after
31 11110 10100 10101 manufacturing, we can easily remove it. But if
the fault is to be detected after integrating the
Table 3:Response of faulty circuit IC to a PCB, the cost of finding the fault as well
Clock LFSR CUT MISR Signature as correcting it is higher. This cost keeps
tick output output output increasing as the fault detection stage is later in
1 11111 10101 00000 the production procedure.
2 01111 01011 10101
3 00111 00101 11111
4 00011 00011 10100 I. APPLICATIONS
5 10001 11111 01001
6 11000 10000 00101 BIST is commonplace in weapons, avionics,
7 01100 01000 01100 medical devices, automotive electronics,
8 10110 11010 01110 complex machinery of all types, unattended
9 11011 10011 11101 machinery of all types, and integrated circuits.
10 11101 10111 00011
11 01110 01010 01000 A. Automotive
2 10111 11011 01110
Automotive tests itself to enhance safety and
13 01011 01101 11100
14 10101 11001 00011 reliability. For example, most vehicles with
15 01010 01100 00110 antilock brakes test them once per safety
16 00101 00111 01111 10101
interval. If the antilock brake system has a
17 00010 00010 11110 broken wire or other fault, the brake system
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 Third national Conference on Modern Trends in Electronic Communication & Signal processing 2013

reverts to operating as a normal brake system. self-tests of their computer, memory and
Most automotive engine controllers incorporate software.
a "limp mode" for each sensor, so that the
E. Unattended Machinery
engine will continue to operate if the sensor or
its wiring fails. Another, more trivial example Unattended machinery performs self-tests to
of a limp mode is that some cars test door discover whether it needs maintenance or
switches, and automatically turn lights on using repair. Typical tests are for temperature,
seat-belt occupancy sensors if the door switches humidity, bad communications, burglars, or a
fail. bad power supply. For example, power systems
or batteries are often under stress, and can
B. Aviation
easily overheat or fail. So, they are often tested.
Almost all avionics now incorporate BIST. In
Often the communication test is a critical item
avionics, the purpose is to isolate failing line-
in a remote system. One of the most common,
replaceable units, which are then removed and
and unsung unattended system is the humble
repaired elsewhere, usually in depots or at the
telephone concentrator box. This contains
manufacturer. Commercial aircraft only make
complex electronics to accumulate telephone
money when they fly, so they use BIST to
lines or data and route it to a central switch.
minimize the time on the ground needed for
Telephone concentrators test for
repair and to increase the level of safety of the
communications continuously, by verifying the
system which contains BIST. Similar
presence of periodic data patterns called frames
arguments apply to military aircraft. When
(See SONET). Frames repeat about 8,000 times
BIST is used in flight, a fault causes the system
per second.
to switch to an alternative mode or equipment
that still operates. Critical flight equipment is Remote systems often have tests to loop-back
normally duplicated, or redundant. Less critical the communications locally, to test transmitter
flight equipment, such as entertainment and receiver, and remotely, to test the
systems, might have a "limp mode" that communication link without using the computer
provides some functions. or software at the remote unit. Where electronic
loop-backs are absent, the software usually
C. Electronics
provides the facility. For example, IP defines a
BIST is used to make faster, less-expensive local address which is a software loopback (IP-
integrated circuit manufacturing tests. The IC Address 127.0.0.1, usually locally mapped to
has a function that verifies all or a portion of name "local host").
the internal functionality of the IC. In some
Many remote systems have automatic reset
cases, this is valuable to customers, as well. For
features to restart their remote computers.
example, a BIST mechanism is provided in
These can be triggered by lack of
advanced field bus systems to verify
communications, improper software operation
functionality. At a high level this can be viewed
or other critical events. Satellites have
similar to the PC BIOS's power-on self-test
automatic reset, and add automatic restart
(POST) that performs a self-test of the RAM
systems for power and attitude control, as well.
and buses on power-up.
F. Medicine
D. Computers
Medical devices test themselves to assure their
The typical personal computer tests itself at
continued safety. Normally there are two tests.
start-up (called POST) because it's a very
A power-on self-test (POST) will perform a
complex piece of machinery. Since it includes a
comprehensive test. Then, a periodic test will
computer, a computerized self-test was an
assure that the device has not become unsafe
obvious, inexpensive feature. Most modern
since the power-on self test. Safety-critical
computers, including embedded systems, have

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 Third national Conference on Modern Trends in Electronic Communication & Signal processing 2013

devices normally define a "safety interval", a  Possible issues with the correctness of
period of time too short for injury to occur. The BIST results, since the on-chip testing
self test of the most critical functions normally hardware itself can fail.
is completed at least once per safety interval.
The periodic test is normally a subset of the III. CONCLUSION
power-on self test.
In this paper we have illustrated an
G. Military implementation of BIST logic using VHDL.
One of the first computer-controlled BIST LFSR is used as a pseudorandom sequence
systems was in the U.S.'s Minuteman Missile. generator. Signature analysis is used to make
Using an internal computer to control the verification of the circuit. Signature mismatch
testing reduced the weight of cables and with the reference signature means that the
connectors for testing. The Minuteman was one circuit is faulty. However, there is a small
of the first major weapons systems to field a probability that the signature of a bad circuit
permanently installed computer-controlled will be the same as a good circuit. When longer
selftest. sequences are used , signature analysis gives
high fault coverage.
II. ADVANTAGES AND
DISADVANTAGES V. REFERENCES
A. Advantages 1.http://en.wikipedia.org/wiki/built-in_self-test
 Lower cost of test, since the need for 2.http://ieeexplore.ieee.org/xpl/articleDetails.js
external electrical testing using an ATE p?tp=&arnumber=4167 999
will be reduced, if not eliminated.

3.http://ieeexplore.ieee.org/xpl/articleDetails.js
Better fault coverage, since special test p?tp=&arnumber=1402 683
structures can be incorporated onto the 4. Implementation of BIST structure using
chips.

VHDL for VLSI circuits
Shorter test times if the BIST can be Mrs.Jamuna.SProfessor, department of ECE,
designed to test more structures in Bangalore Dr. V.K. Agrawal Group director,
parallel. ISRO, Bangalore
 Easier customer support. 5.Built-inselftest,AbdelRashid Linkoping

University, Sweden
Capability to perform tests outside the
production electrical testing
environment.
 Allows the consumers themselves to test
the chips prior to mounting or even after
these are in the application boards.

 Additional silicon area and fabrication

B. Disadvantages

processing requirements for the BIST

 Reduced access times.

circuits;

 Additional pin (and possibly bigger

package size) requirements, since the
BIST circuitry need a way to interface
with the outside world to be effective.

Department of Electronics, BPC College, Piravom