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    Izak Nel 209 324 067 DIT101T JK Flip-Flop

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    Zack Nel
    The document describes the construction and testing of a JK flip-flop circuit using common digital logic chips. It provides details on: 1. The components used including an IC, resistors, LEDs, switches and a voltage regulator to power the circuit. 2. The circuit setup including how the chips are connected and configured on a breadboard. 3. Tests performed on the circuit to observe its behavior under different input conditions and understand the internal functioning of the JK flip-flop.

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    Attribution Non-Commercial (BY-NC)
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    Izak Nel 209 324 067 DIT101T JK Flip-Flop

    Uploaded by

    Zack Nel
    167 views10 pages
    The document describes the construction and testing of a JK flip-flop circuit using common digital logic chips. It provides details on: 1. The components used including an IC, resistors, LEDs, switches and a voltage regulator to power the circuit. 2. The circuit setup including how the chips are connected and configured on a breadboard. 3. Tests performed on the circuit to observe its behavior under different input conditions and understand the internal functioning of the JK flip-flop.

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    Flip Flop

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    The document describes the construction and testing of a JK flip-flop circuit using common digital logic chips. It provides details on: 1. The components used including an IC, resistors, LEDs, switches and a voltage regulator to power the circuit. 2. The circuit setup including how the chips are connected and configured on a breadboard. 3. Tests performed on the circuit to observe its behavior under different input conditions and understand the internal functioning of the JK flip-flop.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    167 views10 pages

    Izak Nel 209 324 067 DIT101T JK Flip-Flop

    Uploaded by

    Zack Nel
    The document describes the construction and testing of a JK flip-flop circuit using common digital logic chips. It provides details on: 1. The components used including an IC, resistors, LEDs, switches and a voltage regulator to power the circuit. 2. The circuit setup including how the chips are connected and configured on a breadboard. 3. Tests performed on the circuit to observe its behavior under different input conditions and understand the internal functioning of the JK flip-flop.

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    Izak Nel

    209 324 067

    DIT101T

    JK Flip-Flop
    Illustrate the working of a JK flip flop with a negative edge trigger, display all the
    functions and ascertain the full intimate knowledge of internal functioning and
    application of the flip flop. Connect flip flop to pulse, alter J and K values to every
    possible combination and note changes in JK configuration in reference to the clock
    pulse.

    1. Rubber anti – static mat


    2. Magnifying glass + light
    3. Multi – meter
    4. Continuity tester
    5. Oscilloscope
    6. Terminal screwdriver set
    7. Breadboard
    8. Needle nose pliers
    9. Side cutter
    10. Wire stripper
    1. Red LED’s
    2. Ethernet cable cores ( jumper wires )
    3. 9V Duracell Battery
    4. 74LS00 NAND Gate
    5. 74LS112 Negative-Edge-Triggered Master-Slave J-K Flip-Flop
    6. 7805 Voltage Regulator
    7. Assorted Resistors
    8. SPDT Switch
    9. 4 channel/4 input dip switch
    10.9 v two pole battery connecter
    Logic Diagram
     Set up

    regulated 5 volt supply


     Fit SPDT switch
     Fit IC across breadboard isolator channel
     Connect Vcc and GND
     Connect two 5k7 Ω resistors to the two selected switch channels
    (A,B) i.e. one per channel.
     Parallel one resistor/switch junction to input A of NAND 1
     Parallel the other resistor/switch junction with input B of NAND 2
     Connect NAND 1 Output input A of NAND 2
     Connect NAND 2 Output to input B of NAND 1
     Connect 100 Ω resistor and LED in series with NAND 1 Output to
    ground
     Connect 100 Ω resistor and LED in series with NAND 2 Output to
    ground
     Fits and connect IC 74LS112
     Connect two 5k7 Ω resistors to the two selected dip switch
    channels in series with pins 2 and 3 separately
     Ground opposite side pins of dipswitches
     Parallel pins 4 and 13 and connect to Vcc
     Connect pin 8 of 74LS00 to pin 1 of 74LS112
     Connect two 100 ohm resistor in series with two LED’s to pins 5
    and 6 separately
    The JK flip flop functions in a very similar fashion than that of the RS Latch, it
    has a set and clear function that once latched does not change its output
    even when the inputs have been removed – i.e. Example of switch bounce
    comes to mind. Only when the complimentary part of the latch receives its
    input that allows it to give a high output does the original output change.

    BUT – the JK Flip flop only changes states when the input clock pulse is on a
    negative edge of its input clock pulse - also known as the trailing edge – this
    means that if the inputs change states and they allow for a condition change
    of Q but the input edge of the clock pulse is Positive the output will not
    change states.

    The JK flip flop also has two additional inputs i.e. Preset and Clear. When One
    of these inputs receive a low input (active low functioning) the will Set or
    Clear the output regardless of the edge state concerning the input clock
    pulse.
    a) Physical size of instrument
    Instrument built on a standard issue breadboard that has a
    dimension spec of 150 mm x 5 mm x 10 mm

    b) Supply voltage to the instrument


    9 volt battery enters a 7805 voltage regulator and delivers a 5 volt
    Parallel output to the IC.

    c) Power consumption of the instrument

    20.55 mA at 5 volts

    0.02055 x 5 = 0.1027 watts

    = 102.7 mW
    In most ways, the JK flip-flop behaves just like the RS flip-flop. The Q and Qc
    outputs will only change state on the falling edge of the CLK signal, and the J
    and K inputs will control the future output state pretty much as before.
    However, there are some important differences.

    Since one of the two logic inputs is always disabled according to the output
    state of the overall flip-flop, the master latch cannot change state back and
    forth while the CLK input is at logic 1. Instead, the enabled input can change
    the state of the master latch once, after which this latch will not change
    again. This was not true of the RS flip-flop.

    If both the J and K inputs are held at logic 1 and the CLK signal continues to
    change, the Q and Q' outputs will simply change state with each falling edge
    of the CLK signal. (The master latch circuit will change state with each rising
    edge of CLK.) We can use this characteristic to advantage in a number of
    ways. A flip-flop built specifically to operate this way is typically designated
    as a T (for Toggle) flip-flop. The lone T input is in fact the CLK input for other
    types of flip-flops.

    The JK flip-flop must be edge triggered in this manner. Any level-triggered JK


    latch circuit will oscillate rapidly if all three inputs are held at logic 1. This is
    not very useful. For the same reason, the T flip-flop must also be edge
    triggered. For both types, this is the only way to ensure that the flip-flop will
    change state only once on any given clock pulse.
    Timing Diagram

    Cloc J K Q Qc
    k
    ↓ 0 0 NC NC
    ↓ 0 1 0 1
    ↓ 1 0 1 0
    ↓ 1 1 Toggle

    Truth Table
    The Objective was achieved, the internal workings of a JK flip-Flop were
    investigated, examined and understood.

    The J-K flip-flop is the most versatile of the basic flip-flops. It has the input-
    following character of the clocked D flip-flop but has two inputs, traditionally
    labelled J and K. If J and K are different then the output Q takes the value of J
    at the next clock edge.

    If J and K are both low then no change occurs. If J and K are both high at the
    clock edge then the output will toggle from one state to the other. It can
    perform the functions of the set/reset flip-flop and has the advantage that
    there are no ambiguous states. It can also act as a T flip-flop to accomplish
    toggling action if J and K are tied together. This toggle application finds
    extensive use in binary counters.

    This Flip Flop is truly a giant in the industry and finds application in almost
    any digital system conceivable it is used in counters, shift registers, frequency
    counters, frequency dividers and many other arbitrary and novel hobby
    applications.

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