256K X 16 4Mb Asynchronous SRAM

GS74116AGP/X
8, 10, 12 ns
TSOP, FP-BGA 256K x 16 3.3 V VDD
Commercial Temp
Industrial Temp 4Mb Asynchronous SRAM Center VDD and VSS
Features FP-BGA 256K x 16 Bump Configuration (Package X)

• Fast access time: 8, 10, 12 ns
1 2 3 4 5 6
• CMOS low power operation: 130/105/95 mA at minimum
cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible A LB OE A0 A1 A2 NC
• Byte control
B DQ16 UB A3 A4 CE DQ1
• Fully static operation
• Industrial Temperature Option: –40° to 85°C C DQ14 DQ15 A5 A6 DQ2 DQ3
• Package line up
GP: RoHS-compliant 400 mil, 44-pin TSOP Type II D VSS DQ13 A17 A7 DQ4 VDD
package
E VDD DQ12 NC A16 DQ5 VSS
X: 6 mm x 10 mm Fine Pitch Ball Grid Array package
GX: RoHS-compliant 6 mm x 10 mm Fine Pitch Ball Grid F DQ11 DQ10 A8 A9 DQ7 DQ6
Array package
• RoHS-compliant TSOP-II, and FP-BGA packages available G DQ9 NC A10 A11 WE DQ8
H NC A12 A13 A14 A15 NC

Description
The GS74116A is a high speed CMOS Static RAM organized
as 262,144 words by 16 bits. Static design eliminates the need 6 x 10 mm Substrate
for external clocks or timing strobes. The GS operates on a Top View
single 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS74116A is available in a 6 x 10 mm Fine
Pitch BGA package and 400 mil TSOP Type-II packages. TSOP-II 256K x 16 Pin Configuration (Package GP)
A4 1 44 A5
A3 2 43 A6
Pin Descriptions A2 3 42 A7
A1 4 Top view 41 OE
Symbol Description A0 5 40 UB
CE 6 39 LB
A0–A17 Address input
DQ1 7 38 DQ16
DQ1–DQ16 Data input/output DQ2 8 37 DQ15
CE Chip enable input DQ3 9 36 DQ14
DQ4 10 35
Lower byte enable input 44 pin DQ13
LB VDD 11 34
(DQ1 to DQ8) VSS
VSS 12 33
VDD
Upper byte enable input 13 TSOP II 32
UB DQ5 DQ12
(DQ9 to DQ16) 14 31
DQ6 DQ11
DQ7 15 30 DQ10
WE Write enable input 29
DQ8 16 DQ9
OE Output enable input WE 17 28 NC
18 27
VDD +3.3 V power supply A15 A8
A14 19 26 A9
VSS Ground A13 20 25 A10
A12 21 24 A11
NC No connect
A16 22 23 A17
Rev: 1.10 1/2013 1/13 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116AGP/X
Block Diagram
A0
Row Memory Array
Decoder
Address
Input
Buffer
Column
A17 Decoder
CE
WE I/O Buffer
OE Control
UB _____
DQ1 DQ16
Truth Table
CE OE WE LB UB DQ1 to DQ8 DQ9 to DQ16 VDD Current

H X X X X Not Selected Not Selected ISB1, ISB2
L L Read Read
L L H L H Read High Z
H L High Z Read
L L Write Write
IDD
L X L L H Write Not Write, High Z
H L Not Write, High Z Write
L H H X X High Z High Z
L X X H H High Z High Z
Note:
X: “H” or “L”

GS74116AGP/X
Absolute Maximum Ratings
Parameter Symbol Rating Unit

Supply Voltage VDD –0.5 to +4.6 V
–0.5 to VDD +0.5

Input Voltage VIN V
(≤ 4.6 V max.)
–0.5 to VDD +0.5

Output Voltage VOUT V
(≤ 4.6 V max.)
Allowable power dissipation PD 0.7 W
Storage temperature TSTG –55 to 150 oC
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended
Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit

Supply Voltage for -8/-10/-12 VDD 3.0 3.3 3.6 V
Input High Voltage VIH 2.0 — VDD +0.3 V
Input Low Voltage VIL –0.3 — 0.8 V
Ambient Temperature, o
TAc 0 — 70 C
Commercial Range
Ambient Temperature, o
TAI –40 — 85 C
Industrial Range
Notes:
1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Capacitance
Parameter Symbol Test Condition Max Unit

Input Capacitance CIN VIN = 0 V 5 pF
Output Capacitance COUT VOUT = 0 V 7 pF
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.

GS74116AGP/X
DC I/O Pin Characteristics
Parameter Symbol Test Conditions Min Max

Input Leakage Current IIL VIN = 0 to VDD – 1 uA 1 uA
Output High Z
Output Leakage Current ILO –1 uA 1 uA
VOUT = 0 to VDD
Output High Voltage VOH IOH = –4 mA 2.4 —
Output Low Voltage VOL ILO = +4 mA — 0.4 V
Power Supply Currents

0 to 70°C –40 to 85°C
Parameter Symbol Test Conditions Unit
8 ns 10 ns 12 ns 8 ns 10 ns 12 ns
CE ≤ VIL
Operating All other inputs
Supply IDD ≥ VIH or ≤ VIL 130 105 90 140 115 100 mA
Current Min. cycle time
IOUT = 0 mA
CE ≥ VIH
Standby All other inputs
ISB1 30 25 25 40 35 35 mA
Current ≥ VIH or ≤ VIL
Min. cycle time
CE ≥ VDD – 0.2V
Standby
ISB2 All other inputs 10 20 mA
Current
≥ VDD – 0.2 V or ≤ 0.2 V

GS74116AGP/X
AC Test Conditions
Output Load 1
Parameter Conditions DQ
Input high level VIH = 2.4 V
Input low level VIL = 0.4 V 50Ω 30pF1
Input rise time tr = 1 V/ns VT = 1.4 V

Input fall time tf = 1 V/ns
Input reference level 1.4 V Output Load 2

Output reference level 1.4 V 3.3 V
Output load Fig. 1& 2 589Ω
DQ
Notes:
1. Include scope and jig capacitance. 5pF1 434Ω
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ

GS74116AGP/X
AC Characteristics
Read Cycle
-8 -10 -12
Parameter Symbol Unit
Min Max Min Max Min Max
Read cycle time tRC 8 — 10 — 12 — ns
Address access time tAA — 8 — 10 — 12 ns
Chip enable access time (CE) tAC — 8 — 10 — 12 ns
Byte enable access time (UB, LB) tAB — 3.5 — 4 — 5 ns
Output enable to output valid (OE) tOE — 3.5 — 4 — 5 ns
Output hold from address change tOH 3 — 3 — 3 — ns
Chip enable to output in low Z (CE) tLZ* 3 — 3 — 3 — ns
Output enable to output in low Z (OE) tOLZ* 0 — 0 — 0 — ns
Byte enable to output in low Z (UB, LB) tBLZ* 0 — 0 — 0 — ns
Chip disable to output in High Z (CE) tHZ* — 4 — 5 — 6 ns
Output disable to output in High Z (OE) tOHZ* — 3.5 — 4 — 5 ns
Byte disable to output in High Z (UB, LB) tBHZ* — 3.5 — 4 — 5 ns
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL
tRC
Address
tAA
tOH
Data Out Previous Data Data valid

GS74116AGP/X
Read Cycle 2: WE = VIH
tRC
Address
tAA
CE
tAC
tHZ
tLZ
tAB
UB, LB
tBLZ tBHZ
OE
tOE
tOHZ
Data Out tOLZ Data valid
High impedance
Write Cycle
-8 -10 -12
Parameter Symbol Unit
Min Max Min Max Min Max
Write cycle time tWC 8 — 10 — 12 — ns
Address valid to end of write tAW 5.5 — 7 — 8 — ns
Chip enable to end of write tCW 5.5 — 7 — 8 — ns
Byte enable to end of write tBW 5.5 — 7 — 8 — ns
Data set up time tDW 4 — 4.5 — 6 — ns
Data hold time tDH 0 — 0 — 0 — ns
Write pulse width tWP 5.5 — 7 — 8 — ns
Address set up time tAS 0 — 0 — 0 — ns
Write recovery time (WE) tWR 0 — 0 — 0 — ns
Write recovery time (CE) tWR1 0 — 0 — 0 — ns
Output Low Z from end of write tWLZ* 3 — 3 — 3 — ns
Write to output in High Z tWHZ* — 3.5 — 4 — 5 ns
* These parameters are sampled and are not 100% tested.

GS74116AGP/X
Write Cycle 1: WE control

tWC
Address
tAW tWR
OE
tCW
CE
tBW
UB, LB
tAS tWP
WE
tDW tDH
Data In Data valid
tWHZ tWLZ
Data Out
High impedance
Write Cycle 2: CE control

tWC
Address
tAW tWR1
OE
tAS tCW
CE
tBW
UB, LB
tWP
WE
tDW tDH
Data In Data valid
Data Out
High impedance

GS74116AGP/X
Write Cycle 3: UB, LB control
tWC
Address
tAW tWR1
OE
tAS tCW
CE
tBW
UB, LB
tWP
WE
tDW tDH
Data In Data valid
Data Out
High impedance

GS74116AGP/X
44-Pin, 400 mil TSOP-II
Dimension in inch Dimension in mm

D c Symbol min nom max min nom max
44 23
A — — 0.047 — — 1.20
A1 0.002 — — 0.05 — —
A2 0.037 0.039 0.041 0.95 1.00 1.05
A
HE
E
B 0.01 0.014 0.018 0.25 0.35 0.45
c — 0.006 — — 0.15 —
D 0.721 0.725 0.729 18.31 18.41 18.51
1 22
e B E 0.396 0.400 0.404 10.06 10.16 10.26
e — 0.031 — — 0.80 —
A2
HE 0.455 0.463 0.471 11.56 11.76 11.96

A
L 0.016 0.020 0.024 0.40 0.50 0.60

y
A1
L1 — 0.031 — — 0.80 —
L1
L
y — — 0.004 — — 0.10
Q Q 0o — 5o 0o — 5o
Detail A
Notes:
1. Dimension D& E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Controlling dimension: mm

GS74116AGP/X
6 mm x 10 mm FP-BGA
Symbol Unit: mm
D
A 1.10±0.10
A1 0.20~0.30
fb f0.30~0.40
E c 0.36(TYP)
D 10.0±0.05
Pin A1
Index D1 5.25
E 6.0±0.05
E1 3.75
Top View e 0.75(TYP)
A aaa 0.10
c
A1 Side View
aaa
Pin A1 A B C D E F G H
Index fb Solder Ball
1
2
3
e
4 E1
5
6
e
D1
Bottom View

GS74116AGP/X
Ordering Information
Part Number* Package Access Time Temp. Range

GS74116AGP-8 RoHS-compliant 400 mil TSOP-II 8 ns Commercial
GS74116AGP-8I RoHS-compliant 400 mil TSOP-II 8 ns Industrial
GS74116AX-8 Fine Pitch BGA 8 ns Commercial
GS74116AX-8I Fine Pitch BGA 8 ns Industrial
GS74116AGX-8 RoHS-compliant Fine Pitch BGA 8 ns Commercial
GS74116AGX-8I RoHS-compliant Fine Pitch BGA 8 ns Industrial
Note:
Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS74116AGP-8T

GS74116AGP/X
4Mb Asynchronous Datasheet Revision History
Rev. Code: Old; Types of Changes

Page #/Revisions/Reason
New Format or Content
74116A_r1 Format/Content • Created new datasheet
• Added 6 ns and 7 ns speed bins

• Updated power numbers
74116A_r1; 74116A_r1_01 Content • Changed FPBGA package size from 7.2 x 11.65 mm to 6 x 10 mm
• Changed package designator from “U” to “X” for FPBGA
• Changed D3 on FPBGA pinout to A17 and E3 to NC
• Updated Recommended Operating Conditions on page 4
74116A_r1_01; 74116A_r1_02 Content
• Updated Read Cycle and Write Cycle AC Characteristics tables
74116A_r1_02; 74116A_r1_03 Content • Removed 6 ns speed bin from entire document
74116A_r1_03; 74116A_r1_04 Content • Removed 7 ns speed bin from entire document
• Updated format
74116A_r1_04; 74116A_r1_05 Content/Format
• Added Pb-free information for TSOP
74116A_r1_05; 74116A_r1_06 Content/Format • Added Pb-free information for FP-BGA
• Changed Pb-free references to RoHS-compliant

74116A_r1_06; 74116A_r1_07 Content • Added RoHS-compliant SOJ part
• Added status to Ordering Information table
74116A_r1_07; 74116A_r1_08 Content • Removed status from Ordering Information table (all parts MP)
• Removed SOJ references (part is EOL)

74116A_r1_08; 74116A_r1_09 Content • (Rev1.09a: Changed 6 x 10 mm Ball Pitch reference on page 1 to 6 x 10
mm Substrate)
74116A_r1_09; 74116A_r1_10 Content • Removed TSOP-II 5/6 RoHS-compliant references (part is EOL)

Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
GSI Technology:
GS74116AX-12I GS74116AGP-12 GS74116AGP-8 GS74116AGP-8I GS74116AGX-10 GS74116AX-12
GS74116AX-10 GS74116AGX-12I GS74116AGP-12I GS74116AX-8I GS74116AX-10I GS74116AGX-10I
GS74116AGP-10I GS74116AGX-12 GS74116AGX-8 GS74116AGP-10 GS74116AX-8 GS74116AGX-8I
GS74116AGX-12E GS74116AX-8E GS74116AGP-8E GS74116AX-12E GS74116AGX-10E GS74116AGP-10E
GS74116AGX-8E GS74116AGP-12E GS74116AX-10E

256K X 16 4Mb Asynchronous SRAM

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256K X 16 4Mb Asynchronous SRAM

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GS74116AGP/X

Features FP-BGA 256K x 16 Bump Configuration (Package X)

H NC A12 A13 A14 A15 NC

Rev: 1.10 1/2013 1/13 © 2001, GSI Technology

CE OE WE LB UB DQ1 to DQ8 DQ9 to DQ16 VDD Current

H L Not Write, High Z Write

Rev: 1.10 1/2013 2/13 © 2001, GSI Technology

Absolute Maximum Ratings

Parameter Symbol Rating Unit

–0.5 to VDD +0.5

–0.5 to VDD +0.5

Allowable power dissipation PD 0.7 W

Storage temperature TSTG –55 to 150 oC

Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit

Input High Voltage VIH 2.0 — VDD +0.3 V

Input Low Voltage VIL –0.3 — 0.8 V

Parameter Symbol Test Condition Max Unit

Output Capacitance COUT VOUT = 0 V 7 pF

Rev: 1.10 1/2013 3/13 © 2001, GSI Technology

DC I/O Pin Characteristics

Parameter Symbol Test Conditions Min Max

Output High Voltage VOH IOH = –4 mA 2.4 —

Output Low Voltage VOL ILO = +4 mA — 0.4 V

Power Supply Currents

Rev: 1.10 1/2013 4/13 © 2001, GSI Technology

Input low level VIL = 0.4 V 50Ω 30pF1

Input rise time tr = 1 V/ns VT = 1.4 V

Input reference level 1.4 V Output Load 2

Rev: 1.10 1/2013 5/13 © 2001, GSI Technology

Read cycle time tRC 8 — 10 — 12 — ns

Address access time tAA — 8 — 10 — 12 ns

Chip enable access time (CE) tAC — 8 — 10 — 12 ns

Byte enable access time (UB, LB) tAB — 3.5 — 4 — 5 ns

Output enable to output valid (OE) tOE — 3.5 — 4 — 5 ns

Output hold from address change tOH 3 — 3 — 3 — ns

Chip enable to output in low Z (CE) tLZ* 3 — 3 — 3 — ns

Output enable to output in low Z (OE) tOLZ* 0 — 0 — 0 — ns

Byte enable to output in low Z (UB, LB) tBLZ* 0 — 0 — 0 — ns

Chip disable to output in High Z (CE) tHZ* — 4 — 5 — 6 ns

Output disable to output in High Z (OE) tOHZ* — 3.5 — 4 — 5 ns

Byte disable to output in High Z (UB, LB) tBHZ* — 3.5 — 4 — 5 ns

* These parameters are sampled and are not 100% tested.

Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL

Data Out Previous Data Data valid

Rev: 1.10 1/2013 6/13 © 2001, GSI Technology

Read Cycle 2: WE = VIH

Write cycle time tWC 8 — 10 — 12 — ns

Address valid to end of write tAW 5.5 — 7 — 8 — ns

Chip enable to end of write tCW 5.5 — 7 — 8 — ns

Byte enable to end of write tBW 5.5 — 7 — 8 — ns

Data set up time tDW 4 — 4.5 — 6 — ns

Data hold time tDH 0 — 0 — 0 — ns

Write pulse width tWP 5.5 — 7 — 8 — ns

Address set up time tAS 0 — 0 — 0 — ns

Write recovery time (WE) tWR 0 — 0 — 0 — ns

Write recovery time (CE) tWR1 0 — 0 — 0 — ns

Output Low Z from end of write tWLZ* 3 — 3 — 3 — ns

Write to output in High Z tWHZ* — 3.5 — 4 — 5 ns