TPIC46L01, TPIC46L02, TPIC46L03 6-Channel Serial and Parallel Low-Side Pre-Fet Driver

TPIC46L01, TPIC46L02, TPIC46L03
6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS055B – NOVEMBER 1996 – REVISED AUGUST 2001
D 6-Channel Serial-In/Parallel-In Low-side DB PACKAGE

Pre-FET Driver (TOP VIEW)
D Device Can Be Cascaded FLT 1 28 VBAT

D Internal 55-V Inductive Load Clamp and VCOMPEN 2 27 GATE0
VGS Protection Clamp for External Power VCOMP 3 26 DRAIN0
FETs IN0 4 25 GATE1
D Independent Shorted-Load/Short-to-Battery IN1 5 24 DRAIN1
Fault Detection on All Drain Terminals IN2 6 23 DRAIN2
D Independent Off-State Open-Load Fault IN3 7 22 GATE2
Sense IN4 8 21 GATE3
D Over-Battery-Voltage Lockout Protection IN5 9 20 DRAIN3
and Fault Reporting CS 10 19 DRAIN4
D Under-Battery Voltage Lockout Protection

SDO
SDI
11
12
18
17
GATE4
DRAIN5
for TPIC46L01 and TPIC46L02
SCLK 13 16 GATE5
D Asynchronous Open-Drain Fault Flag VCC 14 15 GND
D Device Output Can Be Wire-ORed With
Multiple External Devices
D Fault Status Returned Through Serial
Output Terminal
D Internal Global Power-On Reset of Device
D High-Impedance CMOS Compatible Inputs
With Hysteresis
D TPIC46L01 and TPIC46L03 Disables the
Gate Output When a Shorted-Load Fault
Occurs
D TPIC46L02 Transitions the Gate Output to a
Low-Duty Cycle PWM Mode When a
Shorted-Load Fault Occurs
description
The TPIC46L01, TPIC46L02, and TPIC46L03 are low-side predrivers that provide serial input interface and
parallel input interface to control six external field-effect transistor(FET) power switches such as offered in the
Texas Instruments TPIC family of power arrays. These devices are designed primarily for low-frequency
switching, inductive load applications such as solenoids and relays. Fault status for each channel is available
in a serial-data format. Each driver channel has independent off-state open-load detection and on-state
shorted-load/short-to-battery detection. Battery overvoltage and undervoltage detection and shutdown are
provided. Battery and output load faults provide real-time fault reporting to the controller. Each channel also
provides inductive-voltage-transient protection for the external FET.
These devices provide control of output channels through a serial input interface or a parallel input interface.
A command to enable the output from either interface enables the respective channel GATE output to the
external FET. The serial input interface is recommended when the number of signals between the control device
and the predriver must be minimized, and the speed of operation is not critical. In applications where the
predriver must respond very quickly or asynchronously, the parallel input interface is recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright  2001, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

description (continued)
For serial operation, the control device must transition CS from high to low to activate the serial input interface.
When this occurs, SDO is enabled, fault data is latched into the serial input interface, and the FLT flag is
refreshed.
Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must
consist of 8 bits of data. In applications where multiple devices are cascaded together, the string of data must
consist of 8 bits for each device. A high data bit turns the respective output channel on and a low data bit turns
it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data
consists of fault flags for the over-battery voltage (bit 8), under-battery voltage (bit 7) (not on TPIC46L03), and
shorted/open-load flags (bits 1-6) for each of the six output channels. A logic-high bit in the fault data indicates
a fault and a logic-low bit indicates that no fault is present on that channel. Fault register bits are set or cleared
asynchronously to reflect the current state of the hardware. The fault must be present when CS is transitioned
from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial
register when CS is low. CS must be transitioned high after all of the serial data has been clocked into the device.
A low-to-high transition of CS transfers the last 6 bits of serial data to the output buffer, puts SDO in a
high-impedance state, and clears and reenables the fault register. The TPIC46L01/L02/L03 was designed to
allow the serial input interfaces of multiple devices to be cascaded together to simplify the serial interface to the
controller. Serial input data flows through the device and is transferred out SDO following the fault data in
cascaded configurations.
For parallel operation, data is asynchronously transferred directly from the parallel input interface (IN0-IN5) to
the respective GATE output. SCLK or CS are not required for parallel control. A 1 on the parallel input turns the
respective channel on, where a 0 turns it off. Note that either the serial interface or the parallel interface can
enable a channel. Under parallel operation, fault data must still be collected through the serial data interface.
The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions
in the on and off states respectively. These devices offer the option of using an internally generated
fault-reference voltage or an externally supplied VCOMP for fault detection. The internal fault reference is
selected by connecting VCOMPEN to GND and the external reference is selected by connecting VCOMPEN
to VCC. The drain voltage is compared to the fault-reference voltage when the channel is turned on to detect
shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted-load fault
occurs using the TPIC46L01 or TPIC46L03, the channel is turned off and a fault signal is sent to FLT as well
as to the serial fault-register bit. When a shorted-load fault occurs while using the TPIC46L02, the channel
transitions into a low-duty cycle, pulse-width-modulated (PWM) signal as long as the fault is present.
Shorted-load conditions must be present for at least the shorted-load deglitch time, t(STBDG), in order to be
flagged as a fault. A fault signal is sent to FLT as well as the serial fault register bit. More detail on fault detection
operation is presented in the device operation section of this data sheet.
The TPIC46L01 and TPIC46L02 provide protection from over-battery voltage and under-battery voltage
conditions irrespective of the state of the output channels. The TPIC46L03 provides protection from over-battery
voltage conditions irrespective of the state of the output channels When the battery voltage is greater than the
overvoltage threshold or less than the undervoltage threshold (except for the TPIC46L03, which has no
undervoltage threshold), all channels are disabled and a fault signal is sent to FLT as well as to the respective
fault register bits. The outputs return to normal operation once the battery voltage fault has been corrected.
When an over-battery/under-battery voltage condition occurs, the device reports the battery fault, but disables
fault reporting for open and shorted-load conditions. Fault reporting for open and shorted-load conditions are
reenabled after the battery fault condition has been corrected.
These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect
the FET. This clamp voltage is defined by the sum of VCC and turn-on voltage of the external FET. The predriver
also provides a gate-to-source voltage (VGS) clamp to protect the GATE-source terminals of the power FET from
exceeding their rated voltages.
These devices provide pulldown resistors on all inputs except CS. A pullup resistor is used on CS.
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

schematic diagram
8
Fault Logic UVLO† OVLO
SDI
Serial Register SDO
SCLK
VCC
CS Parallel Register
IN 0 FLT
IN 1 PREZ
IN 2 GND D
IN 3 Q
IN 4
IN 5
DRAIN 0
DRAIN 1
8 DRAIN 2
DRAIN 3
DRAIN 4
DRAIN 5
6 VCOMPEN
STB and Open-Load Fault
Protection OSC S
2 BIAS VCOMP
B
A
Gate
Drive Block
Vbg
OVLO GATE 0
VBAT UVLO† GATE 1
GATE 2
GATE 3
GATE 4
GATE 5
† UVLO is not in TPIC46L03

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
CS 10 I Chip select. A high-to-low transition on the CS enables SDO, latches fault data into the serial interface, and
refreshes the fault flag. When CS is high, the fault registers can change fault status. On the falling edge of CS, fault
data is latched into the serial output register and transferred using SDO and SCLK. On a low-to-high transition of
CS, serial data is latched in to the output control register.
DRAIN0 26 I FET drain inputs. DRAIN0 through DRAIN5 are used for both open-load and short-circuit fault detection at the drain
DRAIN1 24 of the external FETs. They are also used for inductive transient protection.
DRAIN2 23
DRAIN3 20
DRAIN4 19
DRAIN5 17
FLT 1 O Fault flag. FLT is an open-drain output that provides a real-time fault flag for shorted-load/open-load/over-battery
voltage/under-battery voltage faults. The device can be ORed with FLT on other devices for interrupt handling. FLT
requires an external pullup resistor.
GATE0 27 O Gate drive output. GATE0 through GATE5 outputs are derived from the VBAT supply. Internal clamps prevent the
GATE1 25 voltages on these nodes from exceeding the VGS rating on most FETs.
GATE2 22
GATE3 21
GATE4 18
GATE5 16
GND 15 I Ground and substrate
IN0 4 I Parallel gate driver inputs. IN0 through IN5 are real-time controls for the gate predrive circuitry. They are CMOS
IN1 5 compatible with hysteresis.
IN2 6
IN3 7
IN4 8
IN5 9
SCLK 13 I Serial clock. SCLK clocks the shift register. Serial data is clocked into SDI and serial fault data is clocked out of
SDO on the falling edge of the serial clock.
SDI 12 I Serial data input. Output control data is clocked into the serial register through SDI. A 1 on SDI commands a
particular gate output on and a 0 turns it off.
SDO 11 O Serial data output. SDO is a 3-state output that transfers fault data to the controlling device. It also passes serial
input data to the next stage for cascaded operation. SDO is taken to a high-impedance state when CS is in a high
state.
VBAT 28 I Battery supply voltage input
VCC 14 I Logic supply voltage
VCOMPEN 2 I Fault reference voltage select. VCOMPEN selects the internally generated fault reference voltage (0) or an
external fault reference (1) to be used in the shorted- and open-load fault detection circuitry.
VCOMP 3 I Fault reference voltage. VCOMP provides an external fault reference voltage for the shorted- and open-load fault
detection circuitry.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Battery supply voltage range, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 60 V
Input voltage range,VI (at any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range, VO (SDO and FLT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Drain-to-source input voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 60 V
Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Thermal resistance, junction to ambient, RθJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112°C/W
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions

MIN NOM MAX UNIT
Logic supply voltage, VCC 4.5 5 5.5 V
Battery supply voltage, VBAT 8 24 V
High-level input voltage, VIH 0.85 VCC VCC V
Low-level input voltage, VIL 0 0.15 VCC V
Setup time, SDI high before SCLK rising edge, tsu (see Figure 5) 10 ns
Hold time, SDI high after SCLK rising edge, th (see Figure 5) 10 ns
Case temperature, TC –40 125 °C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IBAT Supply current, VBAT All outputs off, VBAT = 12 V 300 500 700 µA
ICC Supply current, VCC All outputs off, VBAT = 5.5 V 1 2.6 4.2 mA
VBAT = 5.5 V,
V(turnon) Turnon voltage, logic operational, VCC 2.6 3.5 4.4 V
Check output functionality
V(ovsd) Over-battery voltage shutdown 32 34 36 V
Gate disabled,
disabled See Figure 16
Vhys(ov) Over-battery voltage reset hysteresis 0.5 1 1.5 V
Under-battery voltage shutdown,
V(uvsd) 4.1 4.8 5.4 V
(TPIC46L01, L02 only)
disabled
Gate disabled, See Figure 17
Under-battery-voltage reset hysteresis,
Vhys(uv) 100 200 300 mV
8 V < VBAT < 24 V, IO = 100 µA 7 13.5 V
VG Gate drive voltage
5.5 V < VBAT < 8 V, IO = 100 µA 5 7 V
Maximum current output for drive terminals,
IO(H) VO = GND 0.5 1.2 2.5 mA
pullup
IO(L) VO = 7 V 0.5 1.2 2.5 mA
pulldown
Short-to-battery/shorted-load/open-load
V(stb) VCOMPEN = L 1.1 1.25 1.4 V
detection voltage
Vhys(stb) Short-to-battery hysteresis 40 100 150 mV
Open-load off-state detection drain voltage
VD(open) VCOMPEN = L 1.1 1.25 1.4 V
threshold
Vhys(open) Open-load hysteresis 40 100 150 mV
II(open) Open-load off-state detection current 30 60 80 µA
II(PU) Input pullup current (CS) VCC = 5 V, VIN = 0 V 10 µA
II(PD) Input pulldown current VCC = 5 V, VIN = 5 V 10 µA
VI(hys) Input voltage hysteresis VCC = 5 V 0.6 0.85 1.1 V
VO(SH) High-level serial output voltage IO = 1 mA 0.8 VCC V
VO(SL) Low-level serial output voltage IO = 1 mA 0.1 0.4 V
IOZ(SD) 3-state current serial-data output VCC = 0 V to 5.5 V -10 1 10 µA
VO(CFLT) Fault-interrupt output voltage IO = 1 mA 0.1 0.5 V
Fault-external reference voltage, (TPIC46L01,
VI(COMP) VCOMPEN = H 0.25 3 V
L02 only)
Fault-external reference voltage, (TPIC46L03
VI(COMP) VCOMPEN = H 1 3 V
only)
VC Output clamp voltage, (TPIC46L01, L02 only) dc < 1%, tw = 100 µs 47 55 63 V
VC Output clamp voltage, (TPIC46L03 only) dc < 1%, tw = 100 µs 47 60 V

switching characteristics, VCC = 5 V, VBAT = 12 V, TC = 25°C

Mask time, short-to-battery/shorted-load/open-
t(STBFM) See Figures 14 and 15 60 µs
load fault
t(STBDG) Deglitch time, short-to-battery/shorted-load See Figure 14 8 µs
Propagation turnon delay time, CS or IN0-IN5
tPLH C(gate) = 400 pF, See Figure 1 4 µs
to GATE0–GATE5
Propagation turnoff delay time, CS or IN0-IN5
tPHL C(gate) = 400 pF, See Figure 2 3.5 µs
to GATE0–GATE5
tr(1) Rise time, GATE0–GATE5 C(gate) = 400 pF, See Figure 3 3.5 µs
tf(1) Fall time, GATE0–GATE5 C(gate) = 400 pF, See Figure 4 3 µs
f(SCLK) Serial clock frequency 10 MHz
trf(SB) Refresh time, short-to-battery TPIC46L02 only, See Figure 14 10 ms
tw Short-to-battery refresh pulse width TPIC46L02 only, See Figure 14 68 µs
tsu(1) Setup time, CS↓ to ↑SCLK See Figure 5 10 ns
RL = 10 kΩ, CL = 200 pF,
tpd(1) Propagation delay time, CS↓ to SDI valid 40 ns
See Figure 6
tpd(2) Propagation delay time, SCLK↓ to SDI valid See Figure 6 20 ns
RL = 10 kΩ, CL = 50 pF,
tpd(3) Propagation delay time, CS↑ to SDO 3-state 2 µs
See Figure 7
RL = 10 kΩ to GND, Over-battery fault,
tr(2) Rise time, SDO 3-state to SDO valid 30 ns
CL = 200 pF, See Figure 8
RL = 10 kΩ to VCC, No faults,
tf(2) Fall time, SDO 3-state to SDO valid 20 ns
RL = 10 kΩ, CL = 50 pF,
tr(3) Rise time, FLT 1.2 µs
See Figure 10
RL = 10 kΩ, CL = 50 pF,
tf(3) Fall time, FLT 15 ns
See Figure 11
IN0 – IN5 50%
CS or IN0 –IN 5 50% CS 50%

tPLH
tPHL
90%
GATE0 – GATE5
GATE0–GATE5 10%
Figure 1 Figure 2
tr(1) tf(1)
90% 90%
GATE0–GATE5
GATE0–GATE5 10%
10%
Figure 3 Figure 4

SCLK
SCLK
tsu(1)
CS CS
th tpd(1) tpd(2)
tsu
SDI SDI 3-STATE
Figure 5 Figure 6
CS 50%
90%
tpd(3) SDO 3-STATE
10%
SDO 3-STATE tr(2)
Figure 7 Figure 8
tr(3)
tf(2)
FLT 90%
90%
SDO 3-STATE 10%
10%
Figure 9 Figure 10
tf(3)
FLT
90%
10%
Figure 11

PRINCIPLES OF OPERATION
serial data operation

The TPIC46L01, TPIC46L02, and TPIC46L03 offer serial input interfaces to the microcontroller to transfer
control data to the predriver and output fault data back to the controller. The serial input interface consists of:
D SCLK – Serial clock
D CS – Chip select
D SDI – Serial data input
D SDO – Serial data outpu
Serial data is shifted into the least significant bit (LSB) of the SDI shift register on the rising edge of the first SCLK
after CS has transitioned from 1 to 0. Eight clock cycles are required to shift the first bit from the LSB to the most
significant bit (MSB) of the shift register. Less than eight clock cycles result in fault data being latched into the
output control buffer. The first two bits are unused and the last six bits are the output control data. A low-to-high
transition on CS latches the contents of the serial shift register into the output control register. A 0 input to SDI
turns the corresponding parallel output off and a 1 turns the output on (see Figure 12).
1 2 3 4 5 6 7 8
SCLK
CS
SDI Don’t Care
New Data GATE5 OFF

GATE4 ON
GATE3 ON
GATE2 OFF
GATE1 OFF
GATE0 ON
Output Control Present Output Data New Data

Register Data
Figure 12

serial data operation (continued)

Data is shifted out of SDO on the falling edge of SCLK. The MSB of fault data is available when CS is transitioned
low. The remaining 7 bits of fault data are shifted out on the following seven clock cycles. Fault data is latched
into the serial register when CS is transitioned low. Fault data must be present on the high-to-low transition of
CS to be captured by the device. The CS input must be transitioned to a high state after the last bit of serial data
has been clocked into the device. CS puts SDO in a high-impedance state, inhibits SDI, latches the 6 bits of
serial data into the output control register, and clears and reenables the serial fault registers (see Figure 13).
When a shorted-load condition occurs with the TPIC46L01 or TPIC46L03, the controller must disable and
reenable the channel to clear the fault register and fault flag. The TPIC46L02 automatically retries the output
and FLT clears after the fault condition has been corrected.
1 2 3 4 5 6 7 8
SCLK
CS
SDO 3-State OV UV FLT5 FLT4 FLT3 FLT2 FLT1 FLT0 N/A
bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1

OV Over-Battery-Voltage Fault Bit
UV Under-Battery-Voltage Fault Bit
FLT5 Shorted- or Open-Load Fault on Channel 5
N/A Unknown Data
Figure 13
parallel input data operation

In addition to the serial input interface, the TPIC46L01 and TPIC46L02 also provides a parallel input interface
to the microcontroller. The output turns on if either the parallel or the serial interface commands it to turn on.
The parallel data pins are real-time control inputs for the output drivers. SCLK and CS are not required to transfer
parallel input data to the output buffer. Fault data must be read over the serial data bus as described in the serial
data operation section of this data sheet. The parallel input must be transitioned low and then high to clear and
reenable a gate output that has been disabled due to a shorted-load fault condition.

chipset performance under fault conditions

The TPIC46L01, TPIC46L02, TPIC46L03, and power FET array’s are designed for normal operation over a
battery-voltage range of 8 V to 24 V with load fault detection from 4.8 V to 34 V. The TPIC46L01, TPIC46L02,
and TPIC46L03 offer onboard fault detection to handle a variety of faults that may occur within a system. The
circuits primary function is to prevent damage to the load and the power FETs in the event that a fault occurs.
Unused DRAIN0–DRAIN5 inputs must be connected to VBAT through a pullup resistor to prevent false reporting
of open-load fault conditions. This circuitry detects the fault, shuts off the output to the FET, and reports the fault
to the microcontroller. The primary faults under consideration are:
1. Shorted load
2. Open load
3. Over-battery voltage shutdown
4. Under-battery voltage shutdown
NOTE:
On the TPIC46L01 and TPIC46L02, an undervoltage fault may be detected when VCC and VBAT are
applied to the device. The controller should initialize the fault register after power up to clear any
false fault reports.
shorted-load fault condition

The TPIC46L01 and TPIC46L02 monitor the drain voltage of each channel to detect shorted-load conditions.
The onboard deglitch timer starts running when the gate output to the power FET transitions from the off state
to the on state. The timer provides a 60-µs deglitch time, t(STBFM), to allow the drain voltage to stabilize after
the power FET has been turned on. The deglitch time is only enabled for the first 60 µs after the FET has been
turned on. After the deglitch delay time, the drain voltage is checked to verify that it is less than the fault reference
voltage. When it is greater than the reference voltage for at least the short-to-battery deglitch time, t(STBDG), then
FLT flags the microcontroller that a fault condition exists and the gate output is automatically shut off
(TPIC46L01 and TPIC46L03) until the error condition has been corrected.
An overheating condition on the FET occurs when the controller continually tries to reenable the output under
shorted-load fault conditions. When a shorted-load fault is detected while using the TPIC46L02, the gate output
is transitioned into a low-duty cycle PWM signal to protect the FET from overheating. The PWM rate is defined
as t(SB) and the pulse with is defined as tw. It remains in this low-duty cycle pulse state until the fault has been
corrected or until the controller disables the gate output.
The microcontroller can read the serial port on the predriver to isolate which channel reported the fault condition.
Fault bits 0–5 distinguish faults for each of the output channels. When a shorted-load condition occurs with the
TPIC46L01, the controller must disable and reenable the channel to clear the fault register and fault flag. The
TPIC46L02 automatically retries the output and the fault clears after the fault condition has been corrected.
Figure 14 illustrates operation after a gate output has been turned on. The gate to the power FET is turned on
and the deglitch timer starts running. Under normal operation T1 turns on and the drain operates below the
reference point set at U1. The output of U1 is low and a fault condition is not flagged.

External TPIC46L01/L02
VBAT
Load
U1
+
T1 _ FLT
1.25 V
Input From
TPIC46L01/L02 N-Channel Deglitch
NORMAL SHORTED-LOAD TPIC46L01 AND TPIC46L03
Input Input
GATE0– GATE0–
GATE5 GATE5
Glitches
Glitches
DRAIN0– DRAIN0–
DRAIN5 DRAIN5
FLT t(STBFM) FLT
t(STBDG)
t(STBFM)
SHORTED-LOAD TPIC46L02
Input
GATE0–
GATE5
Glitches
t(SB)
DRAIN0– tw
DRAIN5
GATE0–
GATE5
FLT
t(STBDG)
t(STBFM)
Figure 14

open load
The TPIC46L01, TPIC46L02, and TPIC46L03 monitor the drain of each power FET for open-circuit conditions
that may exist. The 60-µA current source is provided to monitor open-load fault conditions. Open-load faults are
detected when the power FET is turned off. When load impedance is open or substantially high, then the 60-µA
current source has adequate drive to pull the drain of T1 below the fault reference threshold on the detection
circuit. Unused DRAIN0–DRAIN5 inputs must be connected to VBAT through a pullup resistor to prevent false
reporting of open-load fault conditions. The onboard deglitch timer starts running when the TPIC46L01,
TPIC46L02, and TPIC46L03 gate output to the power FET transitions to the off state. The timer provides a 60-µs
deglitch time, t(STBFM), to allow the drain voltage to stabilize after the power FET has been turned off. The
deglitch time is only enabled for the first 60 µs after the FET has been turned off. After the deglitch delay time,
the drain is checked to verify that it is greater than the fault reference voltage. When it is less than the reference
voltage, a fault is flagged to the microcontroller through FLT that an open-load fault condition exists. The
microcontroller can then read the serial port on the TPIC46L01, TPIC46L02, and TPIC46L03 to isolate which
channel reported the fault condition. Fault bits 0–5 distinguish faults for each of the output channels. Figure 15
illustrates the operation of the open-load detection circuit. This feature provides useful information to the
microcontroller to isolate system failures and warn the operator that a problem exists. Examples of such
applications would be warning that a light bulb filament may be open, solenoid coils may be open, etc.
External TPIC46L01/L02/L03
VBAT
Load
U1
+
60 µA _
T1 FLT
1.25 V
Input From
TPIC46L01/L02/L03 N-Channel Deglitch
NORMAL OPEN-LOAD
Input NORMAL Input
GATE0– GATE0–
GATE5 GATE5
Glitches
DRAIN0– DRAIN0–
DRAIN5 DRAIN5
FLT FLT
t(STBFM)
t(STBFM)
Figure 15

over-battery-voltage shutdown
The TPIC46L01, TPIC46L02, and TPIC46L03 monitor the battery voltage to prevent the power FETs from being
turned on in the event that the battery voltage is too high. This condition may occur due to voltage transients
resulting from a loose battery connection. The TPIC46L01/L02/L03 turns the power FETs off when the battery
voltage is above 34 V, to prevent possible damage to the load and the FETs. The gate output goes back to normal
operation after the overvoltage condition has been corrected. An over-battery voltage fault is flagged to the
controller through the fault flag. Bit 8 of the serial-data fault word is set whenever an over-battery voltage
condition is present. When an overvoltage condition occurs the device reports the battery fault, but disables fault
reporting for open and shorted-load conditions. Fault reporting for open and shorted-load conditions reenables
after the battery-fault condition has been corrected. When the fault condition is removed before the CS signal
transitions low, then the fault condition is not captured in the serial fault register. FLT resets on the high-to-low
transition of CS provided no other faults are present in the device. Figure 16 illustrates the operation of the
over-battery voltage detection circuit.
VBAT
+
_ Output Disable
34 V
VBAT 34 V
12 V 33 V
GATE0 – GATE5
Figure 16

under-battery-voltage shutdown (TPIC46L01, and TPIC46L02 only)

The TPIC46L01 and TPIC46L02 monitor the battery voltage to prevent the power FETs from being turned on
in the event that the battery voltage is too low. When the battery voltage is below 4.8 V, then GATE0–GATE5
outputs may not provide sufficient gate voltage to the power FETs to minimize the on-resistance that could result
in a thermal stress on the FET. The output resumes normal operation after the under-voltage condition has been
corrected. An under-battery voltage fault flags the controller through the fault flag. Bit 7 of the serial-data fault
word is set whenever an under-battery voltage condition is present. When an under-battery voltage condition
occurs the device reports the battery fault, but disables fault reporting for open- and shorted-load conditions.
When the fault condition is removed before CS signal transitions low, the fault condition is not captured in the
serial fault register. FLT resets on the high-to-low transition of CS provided no other faults are present in the
device. Figure 17 illustrates the operation of the under-battery voltage detection circuit.
VBAT
U1
_
Output Disable
4.8 V +
12 V
VBAT 5V
4.8 V
GATE0–GATE5
Figure 17

Inductive voltage transients

A typical application for the predriver/power FET circuit is to switch inductive loads. When an inductive load is
switched off, a large voltage spike can occur. These spikes can exceed the maximum VDS rating for the external
FET and damage the device when proper protection is not in place. The FET can be protected from these
transients through a variety of methods using external components. The TPIC46L01 and TPIC46L02 offer that
protection in the form of a Zener diode stack connected between the drain input and GATE output (see
Figure 18). Zener diode (Z1) turns the FET on to dissipate the transient energy. GATE diode (Z2) is provided
to prevent the gate voltage from exceeding 13 V during normal operation and transient protection.
TPIC46L01/02 External
DRAIN LOAD VBAT
Z1 55 V
GATE
Power FET
Z2 13 V
Figure 18

external fault reference input

The TPIC46L01, TPIC46L02, and TPIC46L03 compare each channel drain voltage to a fault reference to detect
shorted-load and open-load conditions. The user has the option of using the internally generated 1.25-V fault
reference or providing an external reference voltage through VCOMP. The internal reference voltage is selected
by connecting VCOMPEN to GND and VCOMP is selected by connecting VCOMPEN to VCC (see Figure 19).
Proper layout techniques should be used in the grounding network for the VCOMP circuit and the
TPIC46L01/L02/L03. The ground for the predriver and the VCOMP network should be connected to a Kelvin
ground if available; otherwise, a single point connection should be maintained to the power ground of the FET
array. Improper grounding techniques may result in inaccuracies in detecting faults.
DRAIN5 +
_
U1
DRAIN0 +
_ FLT
1.25 V A
M
U
VCOMP X
VCOMPEN Deglitch
VCOMPEN
1.25 V 0
VCOMP 1
Figure 19

MECHANICAL DATA
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,65 0,15 M
0,22
28 15
0,15 NOM
5,60 8,20
5,00 7,40
Gage Plane
1 14 0,25
A 0°– 8° 1,03
0,63
Seating Plane
2,00 MAX 0,05 MIN 0,10
PINS **
8 14 16 20 24 28 30 38
DIM
A MAX 3,30 6,50 6,50 7,50 8,50 10,50 10,50 12,90
A MIN 2,70 5,90 5,90 6,90 7,90 9,90 9,90 12,30
4040065 / C 10/95
NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

D 6-Channel Serial-In/Parallel-In Low-side DB PACKAGE

Pre-FET Driver (TOP VIEW)
D Device Can Be Cascaded FLT 1 28 VBAT

D Internal 55-V Inductive Load Clamp and VCOMPEN 2 27 GATE0
VGS Protection Clamp for External Power VCOMP 3 26 DRAIN0
FETs IN0 4 25 GATE1
D Independent Shorted-Load/Short-to-Battery IN1 5 24 DRAIN1
Fault Detection on All Drain Terminals IN2 6 23 DRAIN2
D Independent Off-State Open-Load Fault IN3 7 22 GATE2
Sense IN4 8 21 GATE3
D Over-Battery-Voltage Lockout Protection IN5 9 20 DRAIN3
and Fault Reporting CS 10 19 DRAIN4
D Under-Battery Voltage Lockout Protection

SDO
SDI
11
12
18
17
GATE4
DRAIN5
for TPIC46L01 and TPIC46L02
SCLK 13 16 GATE5
D Asynchronous Open-Drain Fault Flag VCC 14 15 GND
D Device Output Can Be Wire-ORed With
Multiple External Devices
D Fault Status Returned Through Serial
Output Terminal
D Internal Global Power-On Reset of Device
D High-Impedance CMOS Compatible Inputs
With Hysteresis
D TPIC46L01 and TPIC46L03 Disables the
Gate Output When a Shorted-Load Fault
Occurs
D TPIC46L02 Transitions the Gate Output to a
Low-Duty Cycle PWM Mode When a
Shorted-Load Fault Occurs
description
The TPIC46L01, TPIC46L02, and TPIC46L03 are low-side predrivers that provide serial input interface and
parallel input interface to control six external field-effect transistor(FET) power switches such as offered in the
Texas Instruments TPIC family of power arrays. These devices are designed primarily for low-frequency
switching, inductive load applications such as solenoids and relays. Fault status for each channel is available
in a serial-data format. Each driver channel has independent off-state open-load detection and on-state
shorted-load/short-to-battery detection. Battery overvoltage and undervoltage detection and shutdown are
provided. Battery and output load faults provide real-time fault reporting to the controller. Each channel also
provides inductive-voltage-transient protection for the external FET.
These devices provide control of output channels through a serial input interface or a parallel input interface.
A command to enable the output from either interface enables the respective channel GATE output to the
external FET. The serial input interface is recommended when the number of signals between the control device
and the predriver must be minimized, and the speed of operation is not critical. In applications where the
predriver must respond very quickly or asynchronously, the parallel input interface is recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright  2001, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

description (continued)
For serial operation, the control device must transition CS from high to low to activate the serial input interface.
When this occurs, SDO is enabled, fault data is latched into the serial input interface, and the FLT flag is
refreshed.
Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must
consist of 8 bits of data. In applications where multiple devices are cascaded together, the string of data must
consist of 8 bits for each device. A high data bit turns the respective output channel on and a low data bit turns
it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data
consists of fault flags for the over-battery voltage (bit 8), under-battery voltage (bit 7) (not on TPIC46L03), and
shorted/open-load flags (bits 1-6) for each of the six output channels. A logic-high bit in the fault data indicates
a fault and a logic-low bit indicates that no fault is present on that channel. Fault register bits are set or cleared
asynchronously to reflect the current state of the hardware. The fault must be present when CS is transitioned
from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial
register when CS is low. CS must be transitioned high after all of the serial data has been clocked into the device.
A low-to-high transition of CS transfers the last 6 bits of serial data to the output buffer, puts SDO in a
high-impedance state, and clears and reenables the fault register. The TPIC46L01/L02/L03 was designed to
allow the serial input interfaces of multiple devices to be cascaded together to simplify the serial interface to the
controller. Serial input data flows through the device and is transferred out SDO following the fault data in
cascaded configurations.
For parallel operation, data is asynchronously transferred directly from the parallel input interface (IN0-IN5) to
the respective GATE output. SCLK or CS are not required for parallel control. A 1 on the parallel input turns the
respective channel on, where a 0 turns it off. Note that either the serial interface or the parallel interface can
enable a channel. Under parallel operation, fault data must still be collected through the serial data interface.
The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions
in the on and off states respectively. These devices offer the option of using an internally generated
fault-reference voltage or an externally supplied VCOMP for fault detection. The internal fault reference is
selected by connecting VCOMPEN to GND and the external reference is selected by connecting VCOMPEN
to VCC. The drain voltage is compared to the fault-reference voltage when the channel is turned on to detect
shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted-load fault
occurs using the TPIC46L01 or TPIC46L03, the channel is turned off and a fault signal is sent to FLT as well
as to the serial fault-register bit. When a shorted-load fault occurs while using the TPIC46L02, the channel
transitions into a low-duty cycle, pulse-width-modulated (PWM) signal as long as the fault is present.
Shorted-load conditions must be present for at least the shorted-load deglitch time, t(STBDG), in order to be
flagged as a fault. A fault signal is sent to FLT as well as the serial fault register bit. More detail on fault detection
operation is presented in the device operation section of this data sheet.
The TPIC46L01 and TPIC46L02 provide protection from over-battery voltage and under-battery voltage
conditions irrespective of the state of the output channels. The TPIC46L03 provides protection from over-battery
voltage conditions irrespective of the state of the output channels When the battery voltage is greater than the
overvoltage threshold or less than the undervoltage threshold (except for the TPIC46L03, which has no
undervoltage threshold), all channels are disabled and a fault signal is sent to FLT as well as to the respective
fault register bits. The outputs return to normal operation once the battery voltage fault has been corrected.
When an over-battery/under-battery voltage condition occurs, the device reports the battery fault, but disables
fault reporting for open and shorted-load conditions. Fault reporting for open and shorted-load conditions are
reenabled after the battery fault condition has been corrected.
These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect
the FET. This clamp voltage is defined by the sum of VCC and turn-on voltage of the external FET. The predriver
also provides a gate-to-source voltage (VGS) clamp to protect the GATE-source terminals of the power FET from
exceeding their rated voltages.
These devices provide pulldown resistors on all inputs except CS. A pullup resistor is used on CS.

schematic diagram
8
Fault Logic UVLO† OVLO
SDI
Serial Register SDO
SCLK
VCC
CS Parallel Register
IN 0 FLT
IN 1 PREZ
IN 2 GND D
IN 3 Q
IN 4
IN 5
DRAIN 0
DRAIN 1
8 DRAIN 2
DRAIN 3
DRAIN 4
DRAIN 5
6 VCOMPEN
STB and Open-Load Fault
Protection OSC S
2 BIAS VCOMP
B
A
Gate
Drive Block
Vbg
OVLO GATE 0
VBAT UVLO† GATE 1
GATE 2
GATE 3
GATE 4
GATE 5
† UVLO is not in TPIC46L03

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
CS 10 I Chip select. A high-to-low transition on the CS enables SDO, latches fault data into the serial interface, and
refreshes the fault flag. When CS is high, the fault registers can change fault status. On the falling edge of CS, fault
data is latched into the serial output register and transferred using SDO and SCLK. On a low-to-high transition of
CS, serial data is latched in to the output control register.
DRAIN0 26 I FET drain inputs. DRAIN0 through DRAIN5 are used for both open-load and short-circuit fault detection at the drain
DRAIN1 24 of the external FETs. They are also used for inductive transient protection.
DRAIN2 23
DRAIN3 20
DRAIN4 19
DRAIN5 17
FLT 1 O Fault flag. FLT is an open-drain output that provides a real-time fault flag for shorted-load/open-load/over-battery
voltage/under-battery voltage faults. The device can be ORed with FLT on other devices for interrupt handling. FLT
requires an external pullup resistor.
GATE0 27 O Gate drive output. GATE0 through GATE5 outputs are derived from the VBAT supply. Internal clamps prevent the
GATE1 25 voltages on these nodes from exceeding the VGS rating on most FETs.
GATE2 22
GATE3 21
GATE4 18
GATE5 16
GND 15 I Ground and substrate
IN0 4 I Parallel gate driver inputs. IN0 through IN5 are real-time controls for the gate predrive circuitry. They are CMOS
IN1 5 compatible with hysteresis.
IN2 6
IN3 7
IN4 8
IN5 9
SCLK 13 I Serial clock. SCLK clocks the shift register. Serial data is clocked into SDI and serial fault data is clocked out of
SDO on the falling edge of the serial clock.
SDI 12 I Serial data input. Output control data is clocked into the serial register through SDI. A 1 on SDI commands a
particular gate output on and a 0 turns it off.
SDO 11 O Serial data output. SDO is a 3-state output that transfers fault data to the controlling device. It also passes serial
input data to the next stage for cascaded operation. SDO is taken to a high-impedance state when CS is in a high
state.
VBAT 28 I Battery supply voltage input
VCC 14 I Logic supply voltage
VCOMPEN 2 I Fault reference voltage select. VCOMPEN selects the internally generated fault reference voltage (0) or an
external fault reference (1) to be used in the shorted- and open-load fault detection circuitry.
VCOMP 3 I Fault reference voltage. VCOMP provides an external fault reference voltage for the shorted- and open-load fault
detection circuitry.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Battery supply voltage range, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 60 V
Input voltage range,VI (at any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range, VO (SDO and FLT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Drain-to-source input voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 60 V
Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Thermal resistance, junction to ambient, RθJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112°C/W
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions

MIN NOM MAX UNIT
Logic supply voltage, VCC 4.5 5 5.5 V
Battery supply voltage, VBAT 8 24 V
High-level input voltage, VIH 0.85 VCC VCC V
Low-level input voltage, VIL 0 0.15 VCC V
Setup time, SDI high before SCLK rising edge, tsu (see Figure 5) 10 ns
Hold time, SDI high after SCLK rising edge, th (see Figure 5) 10 ns
Case temperature, TC –40 125 °C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
IBAT Supply current, VBAT All outputs off, VBAT = 12 V 300 500 700 µA
ICC Supply current, VCC All outputs off, VBAT = 5.5 V 1 2.6 4.2 mA
VBAT = 5.5 V,
V(turnon) Turnon voltage, logic operational, VCC 2.6 3.5 4.4 V
Check output functionality
V(ovsd) Over-battery voltage shutdown 32 34 36 V
Gate disabled,
disabled See Figure 16
Vhys(ov) Over-battery voltage reset hysteresis 0.5 1 1.5 V
Under-battery voltage shutdown,
V(uvsd) 4.1 4.8 5.4 V
disabled
Gate disabled, See Figure 17
Under-battery-voltage reset hysteresis,
Vhys(uv) 100 200 300 mV
8 V < VBAT < 24 V, IO = 100 µA 7 13.5 V
VG Gate drive voltage
5.5 V < VBAT < 8 V, IO = 100 µA 5 7 V
IO(H) VO = GND 0.5 1.2 2.5 mA
pullup
IO(L) VO = 7 V 0.5 1.2 2.5 mA
pulldown
Short-to-battery/shorted-load/open-load
V(stb) VCOMPEN = L 1.1 1.25 1.4 V
detection voltage
Vhys(stb) Short-to-battery hysteresis 40 100 150 mV
Open-load off-state detection drain voltage
VD(open) VCOMPEN = L 1.1 1.25 1.4 V
threshold
Vhys(open) Open-load hysteresis 40 100 150 mV
II(open) Open-load off-state detection current 30 60 80 µA
II(PU) Input pullup current (CS) VCC = 5 V, VIN = 0 V 10 µA
II(PD) Input pulldown current VCC = 5 V, VIN = 5 V 10 µA
VI(hys) Input voltage hysteresis VCC = 5 V 0.6 0.85 1.1 V
VO(SH) High-level serial output voltage IO = 1 mA 0.8 VCC V
VO(SL) Low-level serial output voltage IO = 1 mA 0.1 0.4 V
IOZ(SD) 3-state current serial-data output VCC = 0 V to 5.5 V -10 1 10 µA
VO(CFLT) Fault-interrupt output voltage IO = 1 mA 0.1 0.5 V
Fault-external reference voltage, (TPIC46L01,
VI(COMP) VCOMPEN = H 0.25 3 V
L02 only)
Fault-external reference voltage, (TPIC46L03
VI(COMP) VCOMPEN = H 1 3 V
only)
VC Output clamp voltage, (TPIC46L01, L02 only) dc < 1%, tw = 100 µs 47 55 63 V
VC Output clamp voltage, (TPIC46L03 only) dc < 1%, tw = 100 µs 47 60 V

switching characteristics, VCC = 5 V, VBAT = 12 V, TC = 25°C

Mask time, short-to-battery/shorted-load/open-
t(STBFM) See Figures 14 and 15 60 µs
load fault
t(STBDG) Deglitch time, short-to-battery/shorted-load See Figure 14 8 µs
Propagation turnon delay time, CS or IN0-IN5
tPLH C(gate) = 400 pF, See Figure 1 4 µs
to GATE0–GATE5
Propagation turnoff delay time, CS or IN0-IN5
tPHL C(gate) = 400 pF, See Figure 2 3.5 µs
to GATE0–GATE5
tr(1) Rise time, GATE0–GATE5 C(gate) = 400 pF, See Figure 3 3.5 µs
tf(1) Fall time, GATE0–GATE5 C(gate) = 400 pF, See Figure 4 3 µs
f(SCLK) Serial clock frequency 10 MHz
trf(SB) Refresh time, short-to-battery TPIC46L02 only, See Figure 14 10 ms
tw Short-to-battery refresh pulse width TPIC46L02 only, See Figure 14 68 µs
tsu(1) Setup time, CS↓ to ↑SCLK See Figure 5 10 ns
RL = 10 kΩ, CL = 200 pF,
tpd(1) Propagation delay time, CS↓ to SDI valid 40 ns
See Figure 6
tpd(2) Propagation delay time, SCLK↓ to SDI valid See Figure 6 20 ns
RL = 10 kΩ, CL = 50 pF,
tpd(3) Propagation delay time, CS↑ to SDO 3-state 2 µs
See Figure 7
RL = 10 kΩ to GND, Over-battery fault,
tr(2) Rise time, SDO 3-state to SDO valid 30 ns
RL = 10 kΩ to VCC, No faults,
tf(2) Fall time, SDO 3-state to SDO valid 20 ns
RL = 10 kΩ, CL = 50 pF,
tr(3) Rise time, FLT 1.2 µs
See Figure 10
RL = 10 kΩ, CL = 50 pF,
tf(3) Fall time, FLT 15 ns
See Figure 11
IN0 – IN5 50%
CS or IN0 –IN 5 50% CS 50%

tPLH
tPHL
90%
GATE0 – GATE5
GATE0–GATE5 10%
Figure 1 Figure 2
tr(1) tf(1)
90% 90%
GATE0–GATE5
GATE0–GATE5 10%
10%
Figure 3 Figure 4

SCLK
SCLK
tsu(1)
CS CS
th tpd(1) tpd(2)
tsu
SDI SDI 3-STATE
Figure 5 Figure 6
CS 50%
90%
tpd(3) SDO 3-STATE
10%
SDO 3-STATE tr(2)
Figure 7 Figure 8
tr(3)
tf(2)
FLT 90%
90%
SDO 3-STATE 10%
10%
Figure 9 Figure 10
tf(3)
FLT
90%
10%
Figure 11

serial data operation

The TPIC46L01, TPIC46L02, and TPIC46L03 offer serial input interfaces to the microcontroller to transfer
control data to the predriver and output fault data back to the controller. The serial input interface consists of:
D SCLK – Serial clock
D CS – Chip select
D SDI – Serial data input
D SDO – Serial data outpu
Serial data is shifted into the least significant bit (LSB) of the SDI shift register on the rising edge of the first SCLK
after CS has transitioned from 1 to 0. Eight clock cycles are required to shift the first bit from the LSB to the most
significant bit (MSB) of the shift register. Less than eight clock cycles result in fault data being latched into the
output control buffer. The first two bits are unused and the last six bits are the output control data. A low-to-high
transition on CS latches the contents of the serial shift register into the output control register. A 0 input to SDI
turns the corresponding parallel output off and a 1 turns the output on (see Figure 12).
1 2 3 4 5 6 7 8
SCLK
CS
SDI Don’t Care
New Data GATE5 OFF

GATE4 ON
GATE3 ON
GATE2 OFF
GATE1 OFF
GATE0 ON
Output Control Present Output Data New Data

Register Data
Figure 12

serial data operation (continued)

Data is shifted out of SDO on the falling edge of SCLK. The MSB of fault data is available when CS is transitioned
low. The remaining 7 bits of fault data are shifted out on the following seven clock cycles. Fault data is latched
into the serial register when CS is transitioned low. Fault data must be present on the high-to-low transition of
CS to be captured by the device. The CS input must be transitioned to a high state after the last bit of serial data
has been clocked into the device. CS puts SDO in a high-impedance state, inhibits SDI, latches the 6 bits of
serial data into the output control register, and clears and reenables the serial fault registers (see Figure 13).
When a shorted-load condition occurs with the TPIC46L01 or TPIC46L03, the controller must disable and
reenable the channel to clear the fault register and fault flag. The TPIC46L02 automatically retries the output
and FLT clears after the fault condition has been corrected.
1 2 3 4 5 6 7 8
SCLK
CS
SDO 3-State OV UV FLT5 FLT4 FLT3 FLT2 FLT1 FLT0 N/A
bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1

OV Over-Battery-Voltage Fault Bit
UV Under-Battery-Voltage Fault Bit
N/A Unknown Data
Figure 13
parallel input data operation

In addition to the serial input interface, the TPIC46L01 and TPIC46L02 also provides a parallel input interface
to the microcontroller. The output turns on if either the parallel or the serial interface commands it to turn on.
The parallel data pins are real-time control inputs for the output drivers. SCLK and CS are not required to transfer
parallel input data to the output buffer. Fault data must be read over the serial data bus as described in the serial
data operation section of this data sheet. The parallel input must be transitioned low and then high to clear and
reenable a gate output that has been disabled due to a shorted-load fault condition.

chipset performance under fault conditions

The TPIC46L01, TPIC46L02, TPIC46L03, and power FET array’s are designed for normal operation over a
battery-voltage range of 8 V to 24 V with load fault detection from 4.8 V to 34 V. The TPIC46L01, TPIC46L02,
and TPIC46L03 offer onboard fault detection to handle a variety of faults that may occur within a system. The
circuits primary function is to prevent damage to the load and the power FETs in the event that a fault occurs.
Unused DRAIN0–DRAIN5 inputs must be connected to VBAT through a pullup resistor to prevent false reporting
of open-load fault conditions. This circuitry detects the fault, shuts off the output to the FET, and reports the fault
to the microcontroller. The primary faults under consideration are:
1. Shorted load
2. Open load
3. Over-battery voltage shutdown
4. Under-battery voltage shutdown
NOTE:
On the TPIC46L01 and TPIC46L02, an undervoltage fault may be detected when VCC and VBAT are
applied to the device. The controller should initialize the fault register after power up to clear any
false fault reports.
shorted-load fault condition

The TPIC46L01 and TPIC46L02 monitor the drain voltage of each channel to detect shorted-load conditions.
The onboard deglitch timer starts running when the gate output to the power FET transitions from the off state
to the on state. The timer provides a 60-µs deglitch time, t(STBFM), to allow the drain voltage to stabilize after
the power FET has been turned on. The deglitch time is only enabled for the first 60 µs after the FET has been
turned on. After the deglitch delay time, the drain voltage is checked to verify that it is less than the fault reference
voltage. When it is greater than the reference voltage for at least the short-to-battery deglitch time, t(STBDG), then
FLT flags the microcontroller that a fault condition exists and the gate output is automatically shut off
(TPIC46L01 and TPIC46L03) until the error condition has been corrected.
An overheating condition on the FET occurs when the controller continually tries to reenable the output under
shorted-load fault conditions. When a shorted-load fault is detected while using the TPIC46L02, the gate output
is transitioned into a low-duty cycle PWM signal to protect the FET from overheating. The PWM rate is defined
as t(SB) and the pulse with is defined as tw. It remains in this low-duty cycle pulse state until the fault has been
corrected or until the controller disables the gate output.
The microcontroller can read the serial port on the predriver to isolate which channel reported the fault condition.
Fault bits 0–5 distinguish faults for each of the output channels. When a shorted-load condition occurs with the
TPIC46L01, the controller must disable and reenable the channel to clear the fault register and fault flag. The
TPIC46L02 automatically retries the output and the fault clears after the fault condition has been corrected.
Figure 14 illustrates operation after a gate output has been turned on. The gate to the power FET is turned on
and the deglitch timer starts running. Under normal operation T1 turns on and the drain operates below the
reference point set at U1. The output of U1 is low and a fault condition is not flagged.

VBAT
Load
U1
+
T1 _ FLT
1.25 V
Input From
TPIC46L01/L02 N-Channel Deglitch
NORMAL SHORTED-LOAD TPIC46L01 AND TPIC46L03
Input Input
GATE0– GATE0–
GATE5 GATE5
Glitches
Glitches
DRAIN0– DRAIN0–
DRAIN5 DRAIN5
FLT t(STBFM) FLT
t(STBDG)
t(STBFM)
SHORTED-LOAD TPIC46L02
Input
GATE0–
GATE5
Glitches
t(SB)
DRAIN0– tw
DRAIN5
GATE0–
GATE5
FLT
t(STBDG)
t(STBFM)
Figure 14

open load
The TPIC46L01, TPIC46L02, and TPIC46L03 monitor the drain of each power FET for open-circuit conditions
that may exist. The 60-µA current source is provided to monitor open-load fault conditions. Open-load faults are
detected when the power FET is turned off. When load impedance is open or substantially high, then the 60-µA
current source has adequate drive to pull the drain of T1 below the fault reference threshold on the detection
circuit. Unused DRAIN0–DRAIN5 inputs must be connected to VBAT through a pullup resistor to prevent false
reporting of open-load fault conditions. The onboard deglitch timer starts running when the TPIC46L01,
TPIC46L02, and TPIC46L03 gate output to the power FET transitions to the off state. The timer provides a 60-µs
deglitch time, t(STBFM), to allow the drain voltage to stabilize after the power FET has been turned off. The
deglitch time is only enabled for the first 60 µs after the FET has been turned off. After the deglitch delay time,
the drain is checked to verify that it is greater than the fault reference voltage. When it is less than the reference
voltage, a fault is flagged to the microcontroller through FLT that an open-load fault condition exists. The
microcontroller can then read the serial port on the TPIC46L01, TPIC46L02, and TPIC46L03 to isolate which
channel reported the fault condition. Fault bits 0–5 distinguish faults for each of the output channels. Figure 15
illustrates the operation of the open-load detection circuit. This feature provides useful information to the
microcontroller to isolate system failures and warn the operator that a problem exists. Examples of such
applications would be warning that a light bulb filament may be open, solenoid coils may be open, etc.
External TPIC46L01/L02/L03
VBAT
Load
U1
+
60 µA _
T1 FLT
1.25 V
Input From
TPIC46L01/L02/L03 N-Channel Deglitch
NORMAL OPEN-LOAD
Input NORMAL Input
GATE0– GATE0–
GATE5 GATE5
Glitches
DRAIN0– DRAIN0–
DRAIN5 DRAIN5
FLT FLT
t(STBFM)
t(STBFM)
Figure 15

over-battery-voltage shutdown
The TPIC46L01, TPIC46L02, and TPIC46L03 monitor the battery voltage to prevent the power FETs from being
turned on in the event that the battery voltage is too high. This condition may occur due to voltage transients
resulting from a loose battery connection. The TPIC46L01/L02/L03 turns the power FETs off when the battery
voltage is above 34 V, to prevent possible damage to the load and the FETs. The gate output goes back to normal
operation after the overvoltage condition has been corrected. An over-battery voltage fault is flagged to the
controller through the fault flag. Bit 8 of the serial-data fault word is set whenever an over-battery voltage
condition is present. When an overvoltage condition occurs the device reports the battery fault, but disables fault
reporting for open and shorted-load conditions. Fault reporting for open and shorted-load conditions reenables
after the battery-fault condition has been corrected. When the fault condition is removed before the CS signal
transitions low, then the fault condition is not captured in the serial fault register. FLT resets on the high-to-low
transition of CS provided no other faults are present in the device. Figure 16 illustrates the operation of the
over-battery voltage detection circuit.
VBAT
+
_ Output Disable
34 V
VBAT 34 V
12 V 33 V
GATE0 – GATE5
Figure 16

under-battery-voltage shutdown (TPIC46L01, and TPIC46L02 only)

The TPIC46L01 and TPIC46L02 monitor the battery voltage to prevent the power FETs from being turned on
in the event that the battery voltage is too low. When the battery voltage is below 4.8 V, then GATE0–GATE5
outputs may not provide sufficient gate voltage to the power FETs to minimize the on-resistance that could result
in a thermal stress on the FET. The output resumes normal operation after the under-voltage condition has been
corrected. An under-battery voltage fault flags the controller through the fault flag. Bit 7 of the serial-data fault
word is set whenever an under-battery voltage condition is present. When an under-battery voltage condition
occurs the device reports the battery fault, but disables fault reporting for open- and shorted-load conditions.
When the fault condition is removed before CS signal transitions low, the fault condition is not captured in the
serial fault register. FLT resets on the high-to-low transition of CS provided no other faults are present in the
device. Figure 17 illustrates the operation of the under-battery voltage detection circuit.
VBAT
U1
_
Output Disable
4.8 V +
12 V
VBAT 5V
4.8 V
GATE0–GATE5
Figure 17

Inductive voltage transients

A typical application for the predriver/power FET circuit is to switch inductive loads. When an inductive load is
switched off, a large voltage spike can occur. These spikes can exceed the maximum VDS rating for the external
FET and damage the device when proper protection is not in place. The FET can be protected from these
transients through a variety of methods using external components. The TPIC46L01 and TPIC46L02 offer that
protection in the form of a Zener diode stack connected between the drain input and GATE output (see
Figure 18). Zener diode (Z1) turns the FET on to dissipate the transient energy. GATE diode (Z2) is provided
to prevent the gate voltage from exceeding 13 V during normal operation and transient protection.
TPIC46L01/02 External
DRAIN LOAD VBAT
Z1 55 V
GATE
Power FET
Z2 13 V
Figure 18

external fault reference input

The TPIC46L01, TPIC46L02, and TPIC46L03 compare each channel drain voltage to a fault reference to detect
shorted-load and open-load conditions. The user has the option of using the internally generated 1.25-V fault
reference or providing an external reference voltage through VCOMP. The internal reference voltage is selected
by connecting VCOMPEN to GND and VCOMP is selected by connecting VCOMPEN to VCC (see Figure 19).
Proper layout techniques should be used in the grounding network for the VCOMP circuit and the
TPIC46L01/L02/L03. The ground for the predriver and the VCOMP network should be connected to a Kelvin
ground if available; otherwise, a single point connection should be maintained to the power ground of the FET
array. Improper grounding techniques may result in inaccuracies in detecting faults.
DRAIN5 +
_
U1
DRAIN0 +
_ FLT
1.25 V A
M
U
VCOMP X
VCOMPEN Deglitch
VCOMPEN
1.25 V 0
VCOMP 1
Figure 19

MECHANICAL DATA
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,65 0,15 M
0,22
28 15
0,15 NOM
5,60 8,20
5,00 7,40
Gage Plane
1 14 0,25
A 0°– 8° 1,03
0,63
Seating Plane
2,00 MAX 0,05 MIN 0,10
PINS **
8 14 16 20 24 28 30 38
DIM
A MAX 3,30 6,50 6,50 7,50 8,50 10,50 10,50 12,90
A MIN 2,70 5,90 5,90 6,90 7,90 9,90 9,90 12,30
4040065 / C 10/95
NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its products to the specifications applicable at the time of sale in accordance with
TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary
to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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Copyright  2001, Texas Instruments Incorporated

TPIC46L01, TPIC46L02, TPIC46L03 6-Channel Serial and Parallel Low-Side Pre-Fet Driver

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TPIC46L01, TPIC46L02, TPIC46L03 6-Channel Serial and Parallel Low-Side Pre-Fet Driver

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TPIC46L01, TPIC46L02, TPIC46L03

6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

D 6-Channel Serial-In/Parallel-In Low-side DB PACKAGE

D Device Can Be Cascaded FLT 1 28 VBAT

D Under-Battery Voltage Lockout Protection

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Fault Logic UVLO† OVLO

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

electrical characteristics over recommended operating free-air temperature range (unless

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics, VCC = 5 V, VBAT = 12 V, TC = 25°C

IN0 – IN5 50%

CS or IN0 –IN 5 50% CS 50%

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

SDI SDI 3-STATE

SDO 3-STATE tr(2)

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

serial data operation

SDI Don’t Care

New Data GATE5 OFF

Output Control Present Output Data New Data

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

serial data operation (continued)

SDO 3-State OV UV FLT5 FLT4 FLT3 FLT2 FLT1 FLT0 N/A

bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1

parallel input data operation

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

chipset performance under fault conditions

shorted-load fault condition

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

NORMAL SHORTED-LOAD TPIC46L01 AND TPIC46L03

FLT t(STBFM) FLT

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Input NORMAL Input

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

under-battery-voltage shutdown (TPIC46L01, and TPIC46L02 only)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

Inductive voltage transients

DRAIN LOAD VBAT

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

external fault reference input

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

2,00 MAX 0,05 MIN 0,10

A MAX 3,30 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 2,70 5,90 5,90 6,90 7,90 9,90 9,90 12,30

NOTES: A. All linear dimensions are in millimeters.

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 6-Channel Serial-In/Parallel-In Low-side DB PACKAGE

D Device Can Be Cascaded FLT 1 28 VBAT

D Under-Battery Voltage Lockout Protection

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Fault Logic UVLO† OVLO

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3