Paper Code : 1MCA3

Title : Computer Organization & Architecture

TOTAL TEACHING HOURS : 52

NO. OF HOURS/ WEEK : 04
CREDITS : 04
IA : 30
Exam :70
Total : 100
Instruction Codes
A program is a set of instructions that specify the operations, operands, and the
sequence by which processing has to occur

A computer instruction is a binary code that specifies a sequence of microoperations

Instruction codes together with data are stored in memory

The computer reads each instruction from memory and places it in a control register

Every computer has its own unique instruction set

The ability to store and execute instructions, the stored program concept, is the most
important property of a general-purpose computer
• An instruction code is a group of bits that instruct the computer to perform
a specific operation.
It is usually divided into parts
operation part
• The operation code of an instruction is a group of bits that define such
operations as add, subtract, multiply, shift, and complement
• The number of bits required for the operation code of an instruction
depends on the total number of operations available in the computer
• Consider a computer with 64 (26) distinct operations, one of them being an
ADD operation. The operation code consists of six bits, with a bit
configuration 110010 assigned to the ADD operation.
•Operation code is decoded in the control unit
•Computer issues control signals to read an operand from memory
•Add the operand to a processor register.
Stored Program Organization
• Organize a computer is to have one processor register and an instruction
code format with two parts.
• The first part specifies => operation to be performed
• The second specifies => an address
• The memory address tells the control where to find an operand in memory
• This operand is read from memory
• The data to be operated on together with the data stored in the processor
register.
• Instructions are stored in one section of
memory and data in another.
• For a memory unit with 4096 words we
need 12 bits to specify an address since
212 = 4096.
• one 16-bit memory word, we have
available four bits for the operation code
(opcode) to specify one out of 16 possible
operations, and 12 bits to specify the
address of an operand.
• The control reads a 16-bit instruction
from the program portion of memory.
• It uses the 12-bit address part of the
instruction to read a 16-bit operand from
the data portion of memory.
• It then executes the operation specified
by the operation code
• Computers that have a single-processor register usually use
accumulator (AC).
• The operation is performed with the memory operand and the
content of AC.
• Sometimes the instruction code not need an operand from memory
• For example, operations such as clear AC, complement AC, and
increment AC operate on data stored in the AC register.
• They do not need an operand from memory. For these types of
operations, the second part of the instruction code (bits 0 through
11) is not needed for specifying a memory address and can be used to
specify other operations for the computer.
Instruction Format
There are three parts of the Instruction Format which are as follows −
Addressing Modes
• Instructions that define the address of a definite memory location are
known as memory reference instructions.
• The method in which a target address or effective address is recognized
within the instruction is known as addressing mode.
The address field for instruction can be represented in two different ways are
as follows −
• Direct Addressing − It uses the address of the operand.
• Indirect Addressing − It facilitates the address as a pointer to the
operand.
• The address of the operand or the target address is called the effective
address.
• Effective Address (EA) − An absolute address that is either a direct
address or has been computed by one of the addressing schemes such as
augmenting, relative addressing, or indexing
Opcodes
• An opcode is a collection of bits that represents the basic operations
including add, subtract, multiply, complement, and shift.
• The total number of operations provided through the computer
determines the number of bits needed for the opcode.
• The minimum bits accessible to the opcode should be n for 2n
operations.
• These operations are implemented on information that is saved in
processor registers or memory.
• It consists of 12 bits of memory that
are required to define the address as
the memory includes (212) 4096
words.
• The 15th bit of the instruction
determines the addressing mode
0 for direct addressing
1 for indirect addressing

The instruction format includes 12 bits of address and 1 bit for the
addressing mode, 3 bits are left for Opcodes.
Address
• The address is the location where a
specific instruction is constructed in the
memory.
• The address bits of an instruction code
is used as an operand and not as an
address. In such methods, the
instruction has an immediate operand.
If the second part has an address, the
instruction is referred to have a direct
address.
• There is another possibility in the
second part including the address of
the operand. This is referred to as an
indirect address.
1. Direct Addressing Mode:
In direct addressing mode, address field in the instruction contains the
effective address of the operand and no intermediate memory access is
required.

Example:
Add the content of R1 and 1001 and store back to R1:
Add R1, (1001) Here 1001 is the address where operand is stored.
2. Indirect Addressing Mode:
In Indirect addressing mode, address field in the instruction contains
the memory location or register where effective address of operand is
present. It requires two memory access. It is further classified into two
categories: Register Indirect, and Memory Indirect.
Example:
LOAD R1, @500
• Above instruction is used to load the content of memory location
stored at memory location 500 to register R1. In other words we can
say, effective address is stored at memory location 500.
• This is the mode of addressing where the instruction contains the
address of the location where the target address is stored. So in this
way it is Indirectly storing the address of the target location in
another memory location. So it is called Indirect Addressing mode.
Difference between Direct and Indirect Addressing Modes:

S.NO Direct Addressing Mode Indirect Addressing Mode

Address field contains the Address field contains reference of

1.
effective address of operand effective address
Requires only one memory
2. Requires two memory references
reference

3. Fast addressing Slower than direct addressing mode

4. No further classification Further classified into two categories

No further calculation is
Require further calculation to find the
5. required to perform the
effective address
operation
There are 2 types(or versions) of Indirect Addressing Mode: Memory
Indirect, and Register Indirect.
1. Memory Indirect –
Directly mention the address of the memory location in the instruction
either enclosed by parenthesis or preceded by ‘@’ character.
Example :
LOAD R1, (1005) or LOAD R1, @1005
2. Register Indirect –
In this type the address of the target memory location will be stored in
the register and the register will be mentioned in the instruction.
Example :
MOV R@, 1005 LOAD R1, (R2)
Computer Registers / Processor Registers
• Registers are a type of computer memory used to quickly accept,
store, and transfer data and instructions that are being used
immediately by the CPU.
• The registers used by the CPU are often termed as Processor
registers.
• A processor register may hold an instruction, a storage address, or
any data (such as bit sequence or individual characters).
• The memory unit has a capacity of 4096 words and each word
contains 16 bits.
• Twelve bits of an instruction word are needed to specify the address
of an operand.
• This leaves three bits for the operation part of the instruction and a
bit to specify a direct or indirect address.
• The data register (DR) holds the operand read from memory.
• The accumulator (AC) register is a general purpose processing
register.
• The instruction read from memory is placed in the instruction register
(IR).
• The temporary register (TR) is used for holding temporary data during
the processing.
• The memory address register (AR) has 12 bits since this is the width of a memory
address.
• The program counter (PC) also has 12 bits and it holds the address of the next
instruction to be executed
• The PC goes through a counting sequence and causes the computer to read
sequential instructions previously stored in memory.
• Instruction words are read and executed in sequence unless a branch instruction
is encountered.
• A branch instruction calls for a transfer to a non-consecutive instruction in the
program.
• The address part of a branch instruction is transferred to PC to become the
address of the next instruction.
• To read an instruction, the content of PC is taken as the address for memory and
a memory read cycle is initiated.
• PC is then incremented by one, so it holds the address of the next instruction in
sequence.
• Two registers are used for input and output. The input register (INPR) receives an
8-bit character from an input device.
• The output register (OUTR) holds an 8-bit character for an output device.
 Computer Instructions
• Computer instructions are a set of machine language instructions which processor
understands and executes.
• A computer will perform tasks based on the instruction provided.
• An instruction comprises of groups called fields.

These fields include:

• The Operation code (Opcode) field which specifies the operation to be performed.
• The Address field which contains the location of the operand, i.e., register or memory
location.
• The Mode field which specifies how the operand will be located.

A basic computer has three instruction code formats which are:

• Memory - reference instruction
• Register - reference instruction
• Input-Output instruction
1) Memory - reference instruction

• 12 bits of memory is used to specify an address

• one bit to specify the addressing mode 'I'.
2) Register-reference instructions
• It is represented by the Opcode 111 with a 0 in the leftmost
bit (bit 15) of the instruction.
3) Input-Output instruction
• Does not need a reference to memory
• It is recognized by the operation code 111 with a 1 in the leftmost bit
of the instruction.
• The remaining 12 bits are used to specify the type of the input-output
operation or test performed.
Basic Computer Instructions
Instruction Set Completeness
A set of instructions is said to be complete if the computer includes a
sufficient number of instructions in each of the following categories:
• Arithmetic, logical and shift instructions
• A set of instructions for moving information to and from memory and
processor registers.
• Instructions which controls the program together with instructions
that check status conditions.
• Input and Output instructions
• Arithmetic, logical, and shift instructions provide computational capabilities

• The bulk of the binary information is stored in memory, but all computations are
done in processor registers
• Therefore, the user must have the capability of moving information between
these two units.

• Decision making capabilities are an important aspect of digital computers.

• For example, two numbers can be compared, and if the first is greater than the
second, it may be necessary to proceed differently than if the second is greater
than the first.

• Program control instructions such as branch instructions are used to change the
sequence in which the program is executed.

• Input and output instructions are needed for communication between the
computer
 Timing and Control
• The timing for all registers in the basic computer is controlled by a master
clock generator.
• The clock pulses are applied to all flip-flops and registers in the system,
including the flip-flops and registers in the control unit.
• The control signals are generated in the control unit and provide control
inputs for the multiplexers in the common bus, control inputs in processor
registers, and microoperations for the accumulator.
The Control Unit is classified into two major categories:
• Hardwired Control [Hardware]
• Microprogrammed Control [software]
Hardwired Control
• The Hardwired Control
organization involves
the control logic to be
implemented with
gates, flip-flops,
decoders, and other
digital circuits.
A Hard-wired Control consists of two decoders, a sequence counter, and a
number of logic gates.

An instruction fetched from the memory unit is placed in the instruction register
(IR).
The component of an instruction register includes; I bit, the operation code, and
bits 0 through 11.

The operation code in bits 12 through 14 are coded with a 3 x 8 decoder.

The outputs of the decoder are designated by the symbols D0 through D7.
The operation code at bit 15 is transferred to a flip-flop designated by the
symbol I.
The operation codes from Bits 0 through 11 are applied to the control logic
gates.
The Sequence counter (SC) can count in binary from 0 through 15.
The outputs of the counter are decoded into 16 timing signals T0 through T15
Micro-programmed Control
• The Microprogrammed Control organization is implemented by using the
programming approach.
• In Microprogrammed Control, the micro-operations are performed by
executing a program consisting of micro-instructions.
• The following image shows the block diagram of a Microprogrammed Control
organization.
• The Control memory address register specifies the address of the micro-
instruction.
• The Control memory is assumed to be a ROM, within which all control
information is permanently stored.
• The control register holds the microinstruction fetched from the memory.
• The micro-instruction contains a control word that specifies one or more
micro-operations for the data processor.
• While the micro-operations are being executed, the next address is computed
in the next address generator circuit and then transferred into the control
address register to read the next microinstruction.
• The next address generator is often referred to as a micro-program sequencer,
as it determines the address sequence that is read from control memory.
Instruction Cycle
• A program residing in the memory unit of a computer consists of a sequence
of instructions.
• These instructions are executed by the processor by going through a cycle for
each instruction.
In a basic computer, each instruction cycle consists of the following phases:
1. Fetch instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory.
4. Execute the instruction.

• This process continues indefinitely unless

a HALT instruction is encountered.
Fetch and Decode
• The program counter PC is loaded with the address of the first instruction in
the program.
• The sequence counter SC is cleared to 0, providing a decoded timing signal
To.
• After each clock pulse, SC is incremented by one, so that the timing signals go
through a sequence T0, T1, T2, and so on.
• The micro-operations for the fetch and decode phases can be specified by
the following register transfer statements.
• T0: AR PC
T1: IRM[AR], PCPC + 1
T2: 1IR(15) , D0,•••,D7DecodeIR(12-14), ARIR(0-11)
• Only AR is connected to the address inputs of memory, it is necessary to
transfer the address from PC to AR during the clock transition T0
T0: AR PC
• The instruction read from memory is then placed in the instruction register
IR with the clock transition associated with timing signal T1; same time PC
is incremented by one to prepare it for the address of the next instruction
in the program
T1: IRM[AR], PCPC + 1
• At time T2, the operation code in IR is decoded, the indirect bit is
transferred to flip-flop I, and the address part of the instruction is
transferred to AR . Note that SC is incremented after each clock pulse to
produce the sequence To, T1, and T2
T2: D0,•••,D7DecodeIR(12-14), ARIR(0-11), 1IR(15)
Memory Reference Instructions
• The seven memory-reference instructions.
• The decoded output D; for i = 0, 1, 2, 3, 4, 5, and 6 from the operation
decoder that belongs to each instruction
• The effective address of the instruction is in the address register AR
placed during timing signal T2 when I=0,or during timing signal T3 when
I= 1.
• The execution of the memory-reference instructions starts with timing
signal T4
Memory Reference Instructions
AND to AC
• Performs the AND logic operation on pairs of bits in AC and the memory word
specified by the effective address.
• The result of the operation is transferred to AC. The microoperations that
execute this
Instruction are:
D0T4: DR M[AR]
D0T5: AC AC /\ DR, SC 0
• The decoder binary code value is 000.
• Two timing signals are needed to execute the instruction
• In T4: transfers the operand from memory into DR.
• In T5: transfers to AC the result of the AND logic operation between the
contents of DR and AC. Same time The same time SC to 0
ADD to AC
• It adds the content of the memory word specified by the effective address
to the value of AC .
• The sum is transferred into AC
• The output carry Cout, is transferred to the E (extended accumulator) flip-
flop.
The microoperations are
DIT4: DR  M[AR]
D1T5: AC AC+DR, ECout, SC 0
LDA: Load to AC
• This instruction transfers the memory word specified by the effective
address to AC.
The microoperations are
D2T4: DR  M[AR]
D2T5: AC DR, SC 0
STA: Store AC
• It stores the content of AC into the memory word specified by the effective address.
The microoperation is:
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally
• This instruction transfers the program to the instruction specified by the effective
address.
• PC holds the address of the instruction to be read from memory in the next instruction
cycle.
• PC is incremented at time T1 to prepare it for the address of the next instruction in the
program sequence.
• The BUN instruction allows the programmer to specify an instruction out of sequence
and the program branches (or jumps) unconditionally.
The microoperation is:
D4T4: PC AR, SC 0
• The effective address from AR is transferred through the common bus to PC.
• The next instruction is then fetched and executed from the memory address given by the
new value in PC.
BSA: Branch and Save Return Address
• This instruction is useful for branching to a portion of the program
called a subroutine or procedure.
• When executed, the BSA instruction stores the address of the next
instruction in sequence (which is available in PC) into a memory
location specified by the effective address.
• The effective address plus one is then transferred to PC to serve as
the address of the first instruction in the subroutine.
2000 BSA 4000
2001 ………
2002 ………
This operation was specified in the following register transfer:
• M[AR] PC, PC AR+1
• The BSA instruction is assumed to be in memory at address 20.
• The I bit is 0 and the address part of the instruction has the binary
equivalent of 135.
• After the fetch and decode phases, PC contains 21, which is the
address of the next instruction in the program (referred to as the
return address).
• AR holds the effective address 135.
• The BSA instruction performs the following numerical operation:
M[135]21, PC135+1=136
The result of this operation is shown in the figure.
• The return address 21 is stored in memory location 135 and control
continues with the subroutine program starting from address 136.
• The return to the original program (at address 21) is accomplished by
means of an indirect BUN instruction placed at the end of the
subroutine.
• When this instruction is executed, control goes to the indirect phase
to read the effective address at location 135, where it finds the
previously saved address 21.
• When the BUN instruction is executed, the effective address 21 is
transferred to PC.
• The next instruction cycle finds PC with the value 21, so control
continues to execute the instruction at the return address.
• The BSA instruction performs the
function usually referred to as a sub
routine call.
• The indirect BUN instruction at the end
of the subroutine performs the
function referred to as a subroutine
return.
• To use the memory and the bus
properly, the BSA instruction must be
executed With a sequence of two
microoperations:
D5T4: M[AR] PC, AR AR+1
D5T5: PC AR, SC 0

Timing signal T4 initiates a memory write operation, places the content of PC onto the bus,
and enables the INR input of AR .
The memory write operation is completed and AR is incremented by the time the next
clock transition occurs.
The bus is used at T5 to transfer the content of AR to PC.
ISZ: Increment and Skip if Zero
• This instruction increments the word specified by the effective address, and
if the incremented value is equal to 0, PC is incremented by 1.
• As this negative number is repeatedly incremented by one, it eventually
reaches the value of zero. At that time PC is incremented by one in order to
skip the next instruction in the program.
• Since it is not possible to increment a word inside the memory, it is
necessary to read the word into DR, increment DR, and store the word back
into memory. This is done with the following sequence of microoperations:
D6T4: DR  M[AR]
D6T5: DR DR+1
D6T: M[AR] DR, if(DR=0)then(PC PC+1), SC 0
 Input-Output and Interrupt
• Instructions and data stored in memory must come from some input device.
Computed results must be transmitted to the user through some output device.
Input-Output Configuration
• The terminal sends and receives serial information has eight bits of an
alphanumeric code.
• The serial information from the keyboard is shifted into the input register INPR .
• The serial information for the printer is stored in the output register OUTR .
• These two registers communicate with a communication interface serially and
with the AC in parallel.
• The transmitter interface receives serial information from the keyboard and
transmits it to INPR.
• The receiver interface receives information from OUTR and sends it to the printer
serially.
• The input register INPR consists of eight bits and holds an alphanumeric input
information.
• The 1-bit input flag FGI is a control flip-flop.
• The flag bit is set to 1 when new information is available in the input device and is
cleared to 0 when the information is accepted by the computer.
• The flag is needed to synchronize the timing rate difference between the input
device and the computer.
The process of information transfer is as follows.
• Initially, the input flag FGI is cleared to 0 .
• When a key is pressed in the keyboard, an 8-bit alpha-numeric code is shifted into
INPR and the input flag FGI is set to 1.
• If the flag is set, the information in INPR cannot be changed
• computer checks the flag bit;
• if it is 1, the information from INPR is transferred in parallel into AC and FGI is
cleared to 0.
• Once the flag is cleared, new information can be shifted into INPR by striking
another key.
• The output register OUTR works similarly but the direction of information flow
is reversed.
• Initially, the output flag FGO is set to 1.
• The computer checks the flag bit;
• if it is 1, the information from AC is transferred in parallel to OUTR and FGO is
cleared to 0
• The output device accepts the coded information, prints the corresponding
character, and when the operation is completed, it sets FGO to 1
• The computer does not load a new character into OUTR when FGO is 0 which
indicates that the output device is in the process of printing the character.
Input-Output Instructions
• Input and output instructions are needed for transferring information to and
from AC register, for checking the flag bits, and for controlling the interrupt
facility.
• Input-output instructions have an operation code 1111 and are recognized by
the control when D7 = 1 and I = 1.
• The remaining bits of the instruction specify the particular operation.
• These instructions are executed with the clock transition associated with timing
signal T3.
• Each control function needs a Boolean relation D7IT3 (p)
• The control function is distinguished by one of the bits in IR(6-11).
Input Output Instructions
The INP instruction transfers the input information from lNPR into the eight low-order
bits of AC and also clears the input flag to 0.

The OUT instruction transfers the eight least significant bits of AC into the output
register OUTR and clears the output flag to 0.

The next two instructions check the status of the flags and cause a skip of the next
instruction if the flag is I. The instruction that is skipped will normally be a branch
instruction to return and check the flag again.

The branch instruction is not skipped if the flag is 0.

If the flag is I, the branch instruction is skipped and an input or output instruction is
executed

The last two instructions set and clear an interrupt enable flip flop lEN
Program Interrupt
• The computer is wasting time while checking the flag (FGI/FGO) instead of doing
some other useful processing task.
• An alternative way is the programmed controlled procedure; here the external device
inform the computer when it is ready for the transfer. Meantime the computer can be
busy with other tasks. This type of transfer uses the interrupt facility.
When a interrupt_flag is set, the computer is interrupted the current program
Computer deviates from current process and take care of the input or output transfer.
It then returns to the current program after I/O transfer
• When lEN =0 (with the IOF instruction), the flags cannot interrupt the computer.
• When lEN = 1 (with the ION instruction), the computer can be interrupted.
These two instructions provide the programmer with the capability of making a
decision, whether to use the interrupt facility or not.
Interrupt Cycle
An interrupt flip-flop R is included in the computer.
When R = 0, the computer goes through an instruction cycle.
During the execute phase of the instruction cycle lEN is checked by the control.
If IEN is 0, it indicates that the programmer does not want to use the interrupt,
so control continues with the next instruction cycle.
If lEN is 1, control checks the flag bits. If both flags are 0, it indicates that neither
the input nor the output registers are ready for transfer of information. In this
case, control continues with the next instruction cycle.
If either flag is set to 1 while lEN = 1, flip-flop R is set to 1.
At the end of the execute phase, control checks the value of R, and if it is equal
to 1 , it goes to an interrupt cycle instead of an instruction cycle.
• The interrupt cycle is a hardware implementation of a branch and save return
address operation. The return address available in PC is stored in a specific
location where it can be found later when the program returns to the
instruction at which it was interrupted.
• The memory location at address 0 is used for storing the return address.
• Control then inserts address 1 into PC and clears IEN and R so that no more interruptions
can occur until the interrupt request from the flag has been serviced.

• Suppose that an interrupt occurs and R is set to 1 while the control is executing the
instruction at address 255.
• At this time, the return address 256 is in PC.
• The input-output service program in memory starting from address 1120 and a BUN 1120
instruction at address 1.

When the interrupt cycle occurs;

• The content of PC (256) is stored in memory location 0, PC is set to 1, and R is cleared to 0.
• At the beginning of the next instruction cycle, the instruction that is read from memory is in
address 1 since this is the content of PC.
• The branch instruction at address 1 causes the program to transfer to the input-output
service program at address 1120. This program checks the flags, determines which flag is
set , and then transfers the required input or output information. Once this is done, the
instruction ION is executed to set lEN to 1
• The instruction that returns the computer to the original place in the main
program is a branch indirect instruction with an address part of 0.
• This instruction is placed at the end of the IO service program.
• After this instruction is read from memory during the fetch phase, control
goes to the indirect phase (because I = 1) to read the effective address.
• The effective address is in location 0 and is the return address that was stored
there during the previous interrupt cycle.
• The execution of the indirect BUN instruction results in placing into PC the
return address from location 0.
Demonstration
of
Interrupt Cycle
Interrupt Cycle
• The interrupt cycle is initiated after the last execute phase if the interrupt
flip-flop R is equal to 1. This flip-flop is set to 1 if lEN = 1 and either FGI or
FGO are equal to 1.
• This can happen with any clock transition except when timing signals T0, T1
or T2 are active. The condition for setting flip-flop R to 1 can be expressed
with the following register transfer statement:
To’T1’T2’(IEN)(FGI + FGO): R  1
• The symbol + designates a logic OR operation.
• This is ANDed with lEN and T0’T1’T2’.
The sequence of microoperations:
• RT0: AR0, TRPC
• RT1: M[AR] TR, PC 0
• RT2: PCPC + 1, IEN0, R0, SC0
• The first timing signal AR is cleared to 0, and the content o f PC is
transferred to the temporary register TR .
• The second timing signal, the return address is stored in memory at
location 0 and PC is cleared to 0.
• The third timing signal increments PC to 1, clears lEN and R, and
control goes back to T0 by clearing SC to 0.
• The beginning of the next instruction cycle has the condition R'T0 and
the content of PC is equal to 1.
• The control then goes through an instruction cycle that fetches and
executes the BUN instruction in location 1.
CPU: Stack Organization
• Stack is also known as the Last In First Out (LIFO) list. It is the most
important feature in the CPU.
• It saves data such that the element stored last is retrieved first. A
stack is a memory unit with an address register.
• This register influence the address for the stack, which is known as
Stack Pointer (SP). The stack pointer continually influences the
address of the element that is located at the top of the stack.
• It can insert an element into or delete an element from the stack.
• The insertion operation is known as push operation
• The deletion operation is known as pop operation
• In a computer stack, these operations are simulated by incrementing
or decrementing the SP register.
Register Stack
• The stack can be arranged as a set of memory words or registers.
• The stack pointer register includes a binary number, which is the
address of the element present at the top of the stack.
• The three-element A, B, and C are located in the stack.
• The element C is at the top of the stack and the stack pointer holds
the address of C that is 3.
• The top element is popped from the stack through reading memory
word at address 3 and decrementing the stack pointer by 1.
• Then, B is at the top of the stack and the SP holds the address of B
that is 2.
• It can insert a new word, the stack is pushed by incrementing the
stack pointer by 1 and inserting a word in that incremented location.
The stack pointer includes 6 bits, because 26 = 64,
and the SP cannot exceed 63 (111111 in binary).
After all, if 63 is incremented by 1, therefore the
result is 0(111111 + 1 = 1000000). SP holds only the
six least significant bits. If 000000 is decremented by
1 thus the result is 111111.

when the stack is full, the one-bit register ‘FULL’ is

set to 1.
If the stack is null, then the one-bit register ‘EMTY’ is
set to 1.
The data register DR holds the binary information
which is composed into or readout of the stack.

First, the SP is set to 0, EMTY is set to 1, and FULL is

set to 0. Now, as the stack is not full (FULL = 0), a new
element is inserted using the push operation.
The push operation
• The stack pointer is incremented by 1 and the address of the next word is
saved in the SP.
• The word from DR is inserted into the stack using the memory write
operation.
• The first element is saved at address 1 and the final element is saved at
address 0. If the stack pointer is at 0, then the stack is full and ‘FULL’ is set to
1. This is the condition when the SP was in location 63 and after
incrementing SP, the final element is saved at address 0. During an element
is saved at address 0, there are no more empty registers in the stack. The
stack is full and the ‘EMTY’ is set to 0.
SP←SP + 1 It can increment stack pointer
M[SP] ← DR It can write element on top of the stack
If (SP = 0) then (FULL ← 1) Check if stack is full
EMTY ← 0 Mark the stack not empty
pop operation
• A new element is deleted from the stack if the stack is not empty (if EMTY = 0)
• The top element from the stack is read and transfer to DR and thus the stack
pointer is decremented.
• If the stack pointer reaches 0, then the stack is empty and ‘EMTY’ is set to 1.
• This is the condition when the element in location 1 is read out and the SP is
decremented by 1.

DR←M[SP] It can read an element from the top of the stack

SP ← SP – 1 It can decrement the stack pointer
If (SP = 0) then (EMTY ← 1) Check if stack is empty
FULL ← 0 Mark the stack not full
 Memory Stack
• A stack can be executed in the CPU by analyzing an area of the computer
memory to a stack operation and utilizing a processor register as a stack
pointer. In this method, it is performed in a random access memory
connected to the CPU.
• Computer memory area is broken into three segments such as program,
data, and stack.
• The address of the next instruction in the program is saved in the pointer
Program Counter (PC). The Address Register (AR) points to an array of the
information. SP continually influences the address of the element present at
the top of the stack.
• The three registers that are linked to the common bus are PC, AR, and SP. PC
can read the instruction during the fetch stage. An operand is read during
execute stage using the address register. An element is pushed into or
popped from the stack using a stack pointer.
In the figure, the SP points to a beginning value
‘2001’. Therefore, the stack increase with
decreasing addresses. The first element is saved
at address 2000, the next element is saved at
address 1999 and the last element is saved at
address 1000.
• The data register can read an element into or from the stack. It can use push
operation to insert a new element into the stack.
SP ← SP – 1
M[SP] ← DR
• It can insert another element into the stack, the stack pointer is decremented by 1. It
can point to the address of the next location/word. A word from DR is inserted into
the top of the stack using memory write operation.
• It can delete an element from the stack. It can use the pop operation which is as
follows −
DR ← M [SP]
SP ← SP + 1
• The top element is read into the DR and then the stack pointer is decremented to
point to the next element in the stack.
• Two processor registers can check the stack limits. One processor register influence
the upper limit (1000) and the other influence the lower limit (2001). During push
operation, the SP is compared with the upper limit to check if the stack is full. During
pop operation, the SP is compared with the lower limit to check if the stack is empty.
Instruction format
The most common fields found in instruction formats are:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor
register.
3. A mode field that specifies the way the operand or the effective address is
determined.
• Operations specified by computer instructions are executed on some data
stored in memory or processor registers.
• Operands residing in memory are specified by their memory address
• Operands residing in processor registers are specified with a register
address.
• A register address is a binary number of k bits that defines one of 2k
registers in the CPU.
Most computers fall into one of three types of CPU organizations:

1. Single accumulator organization.

2. General register organization.

3. Stack organization.
Single accumulator organization.

• All operations are performed with an implied accumulator register

• The instruction format in this type of computer uses one address field.

For example, the instruction that specifies an arithmetic addition is defined

by an assembly language instruction as
ADD X
• where X is the address of the operand. The ADD instruction in this case
results in the operation AC AC + M[X].
• AC is the accumulator register and M[X] symbolizes the memory word
located at address X.
General register type of organization
• The instruction format in this type of computer needs three register
address fields. Thus the instruction for an arithmetic addition may be
written in an assembly language as
ADD R1, R2, R3
• To denote the operation R1  R2 + R3. The number of address fields in the
instruction can be reduced from three to two if the destination register is
the same as one of the source registers. Thus the instruction
ADD R1,R2
• Would denote the operation R 1  R 1 + R 2 . Only register addresses for R
1 and R2 need be specified in this instruction.
• Computers with multiple processor registers use the move instruction with
a mnemonic MOV to symbolize a transfer instruction. Thus the instruction
MOV R1,R2
• Denotes the transfer R1 R2 (or R2<--R1, depending on the particular
computer). Thus transfer-type instructions need two address fields to
specify the source and the destination.
• General register-type computers employ two or three address fields
in their instruction format. Each address field may specify a processor
register or a memory word. An instruction symbolized by
ADD R1, X
• would specify the operation R1 R1 + M[X]. It has two address fields,
one for register R1 and the other for the memory address X.
The stack-organized
• Computers with stack organization would have PUSH and POP instructions
which require an address field. Thus the instruction
PUSH X
• will push the word at address X to the top of the stack. The stack pointer is
updated automatically. Operation-type instructions do not need an address
field in stack-organized computers. This is because the operation is
performed on the two items that are on top of the stack. The instruction
ADD
• in a stack computer consists of an operation code only with n o address
field. This operation has the effect of popping the two top numbers from
the stack, adding the numbers, and pushing the sum into the stack. There is
no need to specify operands with an address field since all operands are
implied to be in the stack.
Three-Address Instructions Instruction addressfield1, addressfield2, addressfield3
• Computers with three-address instruction
formats can use each address field to
specify either a processor register or a
memory operand.
• The program in assembly language that
evaluates X = (A + B) * (C + D)
• It is assumed that the computer has two
processor registers, R1 and R2. The symbol
M[A] denotes the operand at memory
address symbolized by A.
Advantages
Results in short programs when evaluating arithmetic expressions.
Disadvantage
is that the binary-coded instructions require too many bits to specify three addresses.
 Instruction addressfield1, addressfield2
Two-Address Instructions
• Two-address instructions are the most common in commercial computers.
Here again each address field can specify either a processor register or a
memory word.
• The program to evaluate X = (A + B) * (C + D) is as follows:
The MOV instruction moves or transfers the
operands to and from memory and
processor registers.
The first symbol listed in an instruction is
assumed to be both a source and the
destination where the result of the
operation is transferred.
 Instruction addressfield1
One-Address Instructions
It use an implied accumulator (AC) register
for all data manipulation

Here we will neglect the second register

and assume that the AC contains the
result of all operations.

The program to evaluate X = (A + B) * (C + D) is as follows:

All operations are done between the AC register and a memory operand. T is the
address of a temporary memory location required for storing the intermediate
result.
Zero Address Instruction Instruction

The "zero-address" means ‘absence of an address field’ in the instructions

A stack-organized computer does not use an address field for the instructions

The PUSH and POP instructions (specify an address field of the operand)
communicates with the stack.
X = (A + B)*(C + D) will be written for a
stack organized computer. (TOS stands for
top of stack.)

Convert the expression into reverse Polish

notation & Apply Stack Operations
 RISC Instructions
• Reduced instruction set computer
(RISC)
• The instruction set of a typical RISC
processor is restricted to the use of
load and store instructions when
communicating between memory
and CPU.
• All other instructions are executed
within the registers of the CPU
without referring to memory.
To evaluate X = (A + B) * (C + D)
• The load instructions transfer the operands from memory to CPU registers.
• The add and multiply operations are executed with data in the registers
without accessing memory.
• The result is then stored in memory with a store instruction.
Addressing Mode
• Computers use addressing mode techniques for the purpose of
accommodating one or both of the following provisions:
1. To give different programming styles to the user by providing such facilities
as pointers to memory, counters for loop control, indexing of data, and
program relocation
2. To reduce the number of bits in the addressing field of the instruction
• The control unit of a computer is designed to go through an instruction cycle
that is divided into three major phases:
1. Fetch the instruction from memory.
2. Decode the instruction.
3. Execute the instruction.
• There are two modes that not required any need address field. These are the
implied and immediate modes.
Implied Mode:
• operands are specified implicitly in the instruction.
• For example, the instruction "complement accumulator" is an implied-mode
instruction because the operand in the accumulator register is implied in the
definition of the instruction.
Eg: CLC (used to reset Carry flag to 0)
• All register reference instructions that use an accumulator are implied-mode
instructions.
• Zero-address instructions in a stack-organized computer are implied-mode
instructions since the operands are implied to be on top of the stack.
Immediate Mode
• Operand is specified in the instruction itself.
• In other words, an immediate-mode instruction has an operand field rather
than an address field.
• The operand field contains the actual operand to be used in conjunction
with the operation specified in the instruction.
• Immediate-mode instructions are useful for initializing registers to a
constant value.
• It was mentioned previously that the address field of an instruction may
specify either a memory word or a processor register.
• When the address field specifies a processor register, the instruction is said
to be in the register mode.
MOV AL, 35H (move the data 35H into AL register)
S.No. Implied Addressing Mode Immediate Addressing Mode

In Implied addressing mode, no operand is In Immediate addressing mode, operand is

1.
specified in the instruction . specified in the instruction itself .

Basically, the operands are specified implicitly Here, the operands are contained in an operand
2.
in the definition of instruction . field rather than address field .

This type of mode can be used in all register This type of mode is quite useful for initializing
3.
reference instructions . the registers to a constant value .

It requires 8 bits or 16 bits long data and is the

4. It requires more bits than the address.
part of instruction.

5. There is no need to acquire a operand . It is fast in acquiring an operand .

Zero-address instructions in a stack-organized The address field of an instruction may specify

6.
computer are implied-mode instructions . either a memory word or a processor register.

7. Example: CMA (Complement Accumulator) Example: MVI A 45

Register Mode:
• The data is in the register that is specified by the instruction.
• In this mode the operands are in registers that reside within the CPU.
• The particular register is selected from a register field in the instruc-
tion.
• A k-bit field can specify any one of 2k registers
• In register addressing the operand is placed in one of 8 bit or 16 bit
general purpose registers.
• Here one register reference is required to access the data.

MOV AX,CX (move the contents of CX register to AX register)

Register Indirect Mode:
• The instruction specifies a register in the CPU whose contents give the address of
the operand in memory.
• The selected register contains the address of the operand rather than the operand
itself.
• The programmer must ensure that the memory address of the operand is placed in
the processor register; ie. Programmer can access memory indirectly through a
register
• A reference to the register is then equivalent to specifying a memory address.
• The advantage: address field of the instruction uses fewer bits to select a register
than specifying a memory address directly.
• MOV AX, [BX](move the contents of memory location s addressed by the register BX
to the register AX)
Autoincrement or Autodecrement Mode:
• Here value of the register is incremented or decremented after (or before)
memory access
• The address field of an instruction is used by the control unit in the CPU to
obtain the operand from memory.
• The effective address is the address of the operand based on addressing mode
Direct addressing/ Absolute addressing Mode (symbol [ ]):
• The operand’s offset is given in the instruction as an 8 bit or 16 bit
displacement element.
• Here the 16 bit effective address of the data is the part of the instruction
• Here only one memory reference operation is required to access the data
• The operand resides in memory and its address is given directly by the
address field of the instruction
• In a branch-type instruction the address field specifies the actual branch
address

• Example: ADD AL,[0301] //add the contents of offset address 0301 to AL

Indirect Address Mode:
• The address field of the instruction gives the address where the effective
address is stored in memory.
• Control fetches the instruction from memory and uses its address part to
access memory again to read the effective address.
• In some addressing modes, the address field of the instruction is added with
the content of a specific register in the CPU
The effective address in these modes is obtained from the following
computation:
effective address = address part of instruction + content of CPU register
• The CPU register used in the computation may be the program counter, an
index register, or a base register.
Relative Address Mode:
• The content of the program counter is added to the address part of the instruction gives
the effective address.
• The address part of the instruction is usually a signed number (in 2's complement
representation) which can be either positive or negative.
• When this number is added to the content of the program counter, the result pro duces
an effective address whose position in memory is relative to the address of the next
instruction.
• To clarify with an example, assume that the program counter contains the number 825
and the address part of the instruction contains the number 24.
• The instruction at location 825 is read from memory during the fetch phase and the
program counter is then incremented by one to 826.
• The effective address computation for the relative address mode is 826 + 24 = 850. This is
24 memory locations forward from the address of the next instruction.
• Relative addressing is often used with branch-type instructions when the branch address
is in the area surrounding the instruction word itself.
• It results in a shorter address field in the instruction format since the relative address can
be specified with a smaller number of bits compared to the number of bits required to
designate the entire memory address.
• Indexed Addressing Mode: In this mode the content of an index register is added
to the address part of the instruction to obtain the effective address. The
• index register is a special CPU register that contains an index value. The address
field of the instruction defines the beging address of a data array in memory. Each
operand in the array is stored in memory relative to the beginning address. The
distance between the beginning address and the address of the operand is the
index value stored in the index register. Any operand in the array can be accessed
with the same instruction provided that the index register contains the correct
index value. The index register can be incremented to facilitate access to
consecutive operands. Note that if an index type instruction does not include an
address field in its format, the instruction converts to the register indirect mode
of operation.
• Some computers dedicate one CPU register to function solely as an index register.
This register is involved implicitly when the index-mode instruction is used. In
computers with many processor registers, any one of the CPU registers can
contain the index number. In such a case the register must be specified explicitly
in a register field within the instruction format.
• Base Register Addressing Mode: In this mode the content of a base register
is added to the address part of the instruction to obtain the effective
address. This is similar to the indexed addressing mode except that the
register is now called a base register instead of an index register. The
difference between the two modes is in the way they are used rather than in
the way that they are computed. An index register is assumed to hold an
index number that is relative to the address part of the instruction. A base
register is assumed to hold a base address and the address field of the
instruction gives a displacement relative to this base address. The base
register addressing mode is used in computers to facilitate the relocation of
programs in memory. When programs and data are moved from one
segment of memory to another, as required in multiprogramming systems,
the address values of instructions must reflect this change of position. With
a base register, the displacement values of instructions do not have to
change. Only the value of the base register requires updating to reflect the
beginning of a new memory segment.
Numerical Example
To show the differences between the various modes, we
will show the effect of the addressing modes on the
instruction defined in Fig. 8-7. The two-word instruction at
address 200 and 201 is a "load to AC" instruction with an
address field equal to 500. The first word of the instruction
specifies the operation code and mode, and the second
word specifies the address part. PC has the value 200 for
fetching this instruction. The content of processor register
R1 is 400, and the content of an index register XR is 100.
AC receives the operand after the instruction is executed.
The figure lists a few pertinent addresses and shows the
memory content at each of these addresses.
• The mode field of the instruction can specify any one of a number of modes. For each possible
mode we calculate the effective address and the operand that must be loaded into AC .
• In the direct address mode the effective address is the address part of the instruction 500 and the
operand to be loaded into AC is 800.
• In the immediate mode the second word of the instruction is taken as the operand rather than an
address, so 500 is loaded into AC. (The effective address in this case is 201 . )
• In the indirect mode the effective address is stored in memory at address 500. Therefore, the
effective address is 800 and the operand is 300.
• In the relative mode the effective address is 500 + 202 = 702 and the operand is 325. (Note that the
value in PC after the fetch phase and during the execute phase is 202.)
• In the index mode the effective address is XR + 500 = 100 + 500 = 600 and the operand is 900. In
the register mode the operand is in R1 and 400 is loaded into AC. (There is no effective address in
this case.)
• In the register indirect mode the effective address is 400, equal to the content of R 1 and the
operand loaded into AC is 700.
• The autoincrement mode is the same as the register indirect mode except that R1 is incremented
to 401 after the execution of the instruction.
• The autodecrement mode decrements R1 to 399 prior to the execution of the instruction.
• The operand loaded into AC is now 450.
• Table 8-4 lists the values of the effective address and the operand loaded into AC for the nine
addressing modes.