SED1530 Series

DOT MATRIX LCD DRIVER-CONTROLLER

■ DESCRIPTION

The SED1530 Series are intelligent CMOS LCD controller-drivers with the ability to drive alphanumeric and
graphic displays. The LSI communicates with a high-speed microprocessor, such as the Intel 80xx and 68xx
family, through either a serial or 8-bit parallel interface. It stores the data sent from the microprocessor in the
built-in display data RAM (65 × 132 bits) and generates an LCD drive signal.

■ FEATURES

• Low-power CMOS technology • 32-level contrast adjustment by software

• Direct interface to both 80xx and 68xx MPU • 2.4V to 6.0V supply voltage
• Support 8-bit parallel and serial interface • –4.5V to –16V LCD voltage
• On-chip display data RAM ............ 132 × 65 bits • Operating temperature ................... –40 to 85°C
• On-chip DC/DC converter for LCD voltage • Low power consumption ............................ 80µA
• On-chip CR oscillator circuit • Package
• Supports master/slave mode TAB ................................... T**
• Voltage regulator, low-power voltage follower Al pad Die ....................... D*A
• –.17%/°C temperature gradient Au bump Die ................... D*B

■ AVAILABLE MODELS

Name Duty LCD Bias SEG Driver COM Driver Display Area Remarks
SED1530D0* 1⁄33 1⁄5,1⁄6 100 33 33 × 100 COM single-side assignment
SED1530DA* 1⁄33 1⁄5,1⁄6 100 33 33 × 100 COM dual-side assignment
SED1531D0* 1⁄65 1⁄6,1⁄8 132 0 65 × 132 SED1635 is used for COM
SED1532D0* 1⁄65 1⁄6,1⁄8 100 33 65 × 200 COM single-side right assignment
SED1532DB* 1⁄65 1⁄6,1⁄8 100 33 65 × 200 COM single-side left assignment

■ SYSTEM BLOCK DIAGRAM

65 COM
26 CHAR X 4 LINES

132 SEG

Data
YSCL
FR
CPU SED1531 SED1635
DYO
Control

V1
V4
V5

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SED1530 Series

■ BLOCK DIAGRAM

COMS
O 100

O 131
O 99
O0
VSS
VDD
V1 C
V2 O
V3 Segment Common
M
V4 Driver Driver
V5
S
CAP1+ Shift
CAP1– Power Register
CAP2+ Supply
CAP2– Circuits
CAP3–
Display Data Latch
Output Mode Select Circuits

VOUT

Display Start Line Register

Line Address Decoder
VR
I/O Buffer Circuits

Line Counter
Display Data RAM
(132 x 65)

Column Address Decoder (132)

Page Address
Register FRS
Column Address Counter (8 bit) Display FR
Timing CL
Generation DYO
Column Address Register (8 bit) Circuit DOF
M/S

Command Oscillator
Bus Holder Status VS1
Decoder Circuit

MPU Interface I/O Buffer

CS1 CS2 A0 RD WR C86 P/S RES D7 D6 D5 D4 D3 D2 D1 D0

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 SED1530 Series

■ PINOUT

O0

V5
V4
V3
V2
V1
VDD
VR
V5
CAP2–
CAP2+
CAP1–
CAP1+
CAPS–
VOUT
VSS
D7 (SI)
D6 (SCL)
D5
D4
D3
D2
D1
D0
VDD
RD (E)
WR (R/W)
A0
C86
CS2
CS1
P/S
RES
M/S
VS1
DOF
CL
DYO
FR
FRS
COMS

O131

■ PINOUT TABLE

Model Output O0 to O15 O15 to O31 O32 ----------------------------- O99 O100 to O115 O116 to O131
0 SEG0 --------------------------------------------------------- SEG99 COM0 -------------------- 31
SED1530*0*
1 COM31 -------------------- 0
0 COM15 -- 0 SEG0 --------------------------------------------------------- SEG99 COM16 31
SED1530*A*
1 COM16 31 COM15 -- 0
SED1531*0* SEG0 ------------------------------------------------------------------------------------------- SEG131
0 SEG99 --------------------------------------------------------------------------- SEG0 COM31 -- 0
SED1532*0*
1 COM0 -- 31
0 COM0 -- 31 SEG0 --------------------------------------------------------------------------- SEG99
SED1532*B*
1 COM31 -- 0
Note: * “0” and “1” indicate the mode of the D3 output mode select register.

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SED1530 Series

■ PIN DESCRIPTION
• Power Signals

Number
Pin I/O Function
of Pins
VDD Power Connected to +5V power. Connected with MPU power supply VCC pin. 2
VSS Power 0V, connected to system GND. 1
V1 ~ V5 Power Multi-level power for LC driver. Transforms impedance using 6
resistive voltage divider or op amps in order to apply the voltage
determined for each LC cell. The voltage levels are based on VDD, and
must conform to the relationship below:
VDD ≥ V0 ≥ V2 ≥ V3 ≥ V4 ≥ V5
When the master operation power supply is ON, the internal power
supply circuitry supplies the V1 ~ V4 voltages shown below. The
voltage levels are selected using the LCD bias set command.

SED1530D0* SED1530DA*, SED1531D0*, SED1532D**

V1 1/5 × V5 1/6 × V5 1/5 × V5 1/6 × V5
V2 2/5 × V5 2/6 × V5 2/5 × V5 2/6 × V5
V3 3/5 × V5 4/6 × V5 3/5 × V5 4/6 × V5
V4 4/5 × V5 5/6 × V5 4/5 × V5 5/6 × V5

• LCD Power Circuit Pins

Number
Pin I/O Function
of Pins
CAP1+ O Voltage step-up capacitor, positive side connection pin. 1
Connect the capacitor between this pin and CAP1–.
CAP1– O Voltage step-up capacitor, negative side connection pin. 1
Connect the capacitor between this pin and CAP1+.
CAP2+ O Voltage step-up capacitor, positive side connection pin. 1
Connect the capacitor between this pin and CAP2–.
CAP2– O Voltage step-up capacitor, negative side connection pin. 1
Connect the capacitor between this pin and CAP2+.
CAP3– O Voltage step-up capacitor, negative side connection pin. 1
Connect the capacitor between this pin and CAP1+.
VOUT O Voltage step-up output pin. Connect the capacitor between this 1
terminal and VSS.
VR I Voltage regulator pin. Use a resistive voltage divider to provide voltage 1
between VDD and V5.

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 SED1530 Series

• System Bus Interface Signals

Number
Pin I/O Function
of Pins
D7 ~ D0 I/O 8-bit bi-directional data bus, normally connected to a standard 8-bit or 8
(SI) 16-bit MPU data bus.
(SCL) When serial interface is selected:
D7: Serial Data Input Pin (SI)
D6: Serial Clock Input Pin (SCL)
A0 I Normally the LSB of the MPU address bus is connected to this pin to 1
provide data/command selection:
0: D0 ~ D7 indicate display control data
1: D0 ~ D7 indicate display data
RES I Reset to initial settings by setting RES to “L”. 1
The reset operation is performed according to the RES signal level.
CS1 I Chip Select input pins. Data I/O is enabled by the combination below: 2
CS2
Pin Name CS1 CS2
State “L” “H”

RD (E) I * When connected to an 80-series MPU: 1

Active “L”
This pin is connected to the RD signal from the MPU. When this
signal is “L” the SED1530 Series data bus is in output mode.
* When connected to a 68-series MPU:
Active “H”
This is the 68-series MPU enable clock input pin.
WR (R/W) I * When connected to an 80-series MPU: 1
Active “L”
This pin is connected to the WR signal from the MPU. The data
bus signals are retrieved at the rising edge of the WR signal.
* When connected to a 68-series MPU:
This is the read/write control signal input pin.
R/W = “H”: Read
R/W = “L”: Write
C86 I MPU interface select pin: 1
C86 = “H”: the 68-series MPU interface
C86 = “L”: the 80-series MPU interface
P/S I Serial data input/parallel data input selection pin: 1
P/S Chip Select Data/Command Data Read/Write Serial Clock
“H” CS1/CS2 A0 D0 ~ D7 RD/WR —
“L” CS1/CS2 A0 SI (D7) Write only SCL (D6)

Note: RAM data read cannot be performed by serial data input. When
P/S = L, fix D0 ~ D5 to HZ RD, and fix WR to either “H” or “L”.

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SED1530 Series

• LCD Drive Circuit Signals

Number
Pin I/O Function
of Pins
M/S I This pin selects the master/slave operation of the SED1530 series 1
chips. The master operation outputs the signals necessary for the LCD
display. The slave operations input the signals necessary to synchro-
nize the LCD display.
CL I/O This is the display clock I/O terminal. 1
When using the SED1530 Series chips in master/slave, the CL pins of
the chips must be connected.
When using in combination with a dedicated common driver, the
common driver YSCL pin must be connected to this pin.
M/S = “H”: Output
M/S = “L”: Input
FR I/O This is the LCD alternating current signal I/O pin. 1
When using the SED1530 Series chips in master/slave, the FR pins of
the chips must be connected. When using an SED1530 Series chip in
master mode, this pin must be connected to the FR pin of the dedicated
common driver.
M/S = “H”: Output
M/S = “L”: Input
DYO O This is the common activation output pin. 1
This pin is used only when the SED1530 Series chip is in master mode.
This pin must be connected to the common driver DIO pin. This pin is
HZ in slave mode.
VS1 O This pin is used to monitor the voltage of the internal power supply. 1
DOF I/O This is the LCD display blanking control pin. 1
When using the SED1530 Series chips in master/slave, the DOF pins
of the chips must be connected.
When using in combination with a dedicated common driver (SED1635),
the common driver DOFF pin must be connected to this pin.
M/S = “H”: Output
M/S = “L”: Input
FRS O Static drive output pin. 1
This is effective only when in master mode, and is used with the FR pin.
This pin is HZ in slave mode.

(continued)

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 SED1530 Series

• LCD Drive Circuit Signals (continued)

Number
Pin I/O Function
of Pins
On O LC driver output 133
(SEG n) This output depends on the model type, as shown below:
(COM n)
Segment Column
SED1530*0* O0 ~ O99 O100 ~ O131
O0 ~ O15,
SED1530*A* O16 ~ O115
O116 ~ O131
SED1531*0* O0 ~ O131 \
SED1530*0* O0 ~ O99 O100 ~ O131
SED1532*B* O32 ~ O131 O0 ~ O31

Segment Output Terminal

This is the output for driving the LC segments. Through combin-
ing the contents of the display RAM with the FR signal, a single
level can be selected from VDD, V2, V3, and V5:

On Output Voltage
RAM Data FR
Positive Display Negative Display
H VDD V2
H
L V5 V3
H V2 VDD
L
L V3 V5
Power Save — VDD

Common Output Terminal

This is the output for driving the LC commons. Through combin-
ing the scan data with the FR signal, a single level can be selected
from VDD, V1, V4, and V5:

Scan Data FR On Output Voltage

H V5
H
L VDD
H V1
L
L V4
Power Save — VDD

COMS O This is a common output pin dedicated for the indicator. 1

Leave open if not used. This pin is functional only for the SED1530 and
SED1532. It is HZ for the SED1531.

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SED1530 Series

■ ELECTRICAL CHARACTERISTICS
• Absolute Maximum Ratings

Parameter Symbol Rating Unit

–0.3 to +7.0 V
Power supply voltage (at 3× step-up) VDD –0.3 to +6.0 V
(at 4× step-up) –0.3 to +4.5 V
Power supply voltage (2) (VDD reference) V5 –18.0 to +0.3 V
Power supply voltage (3) (VDD reference) V1, V2, V3, V4 V5 to +0.3 V
Input voltage VIN –0.3 to VDD + 0.3 V
Output voltage V0 –0.3 to VDD + 0.3 V
Operating temperature Topr –30 to +85 °C
TCP –55 to +100 °C
Storage temperature TSTR
Bare chip –55 to +125 °C

VCC VDD VDD

GND VSS

VREG
V1~V5, VOUT
System Side SED1530 Series Chip

Notes:
1. V1 ~ V5, VOUT, and the V5 voltage are all values based on VDD = 0V.

2. The voltages of V1, V2, V3 and V4 must always fulfill the relationship VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5.
3. Permanent damage to the LSI may result if the absolute maximum ratings are exceeded during use. Under normal operation,
use should be within the range of the electrical characteristics listed. Violations of these conditions may cause the LSI to
malfunction or may cause loss of reliability in the LSI.

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 SED1530 Series

• DC Characteristics
VSS = 0V, VDD = 5V ±10%, Ta = –40 to 85°C
Parameter Symbol Condition Min Typ Max Unit Pin
Power Recommended VDD 4.5 5.0 5.5 V VSS *1
supply operation
voltage Possible VDD 2.4 — 6.0
(1) operation
Operating Possible V5 VDD reference (VDD = 0V) –16.0 — –4.0 V V5 *2
voltage operation
(2) Possible V1, V2 VDD reference (VDD = 0V) 0.4 × V5 — VDD V V1, V2
operation
Possible V3, V4 VDD reference (VDD = 0V) V5 — 0.6 × V5 V V3, V4
operation
High-level input voltage VIHC 0.7 × VDD — VDD V *3
VDD = 2.7V 0.8 × VDD — VDD
Low-level input voltage VILC VSS — 0.3 × VDD V *3
CMOS

VDD = 2.7V VSS — 0.2 × VDD

High-level output voltage VOHC IOH = 1mA 0.8 × VDD — VDD V *5
VDD = 2.7V IOH = –0.5mA 0.8 × VDD — VDD
Low-level output voltage VOLC IOL = 1mA VSS — 0.2 × VDD V *5
VDD = 2.7V IOL = 0.5mA VSS — 0.2 × VDD
High-level input voltage VIHS 0.85 × VDD — VDD V *4
Schmidt

VDD = 2.7V 0.8 × VDD — VDD

Low-level input voltage VILS VSS — 0.15 × VDD V *4
VDD = 2.7V VSS — 0.2 × VDD
Input leak current ILI VIN = VDD or VSS –1.0 — 1.0 µA *6
Output leak current ILO –3.0 — 3.0 µA *7
LC driver ON resistance RON Ta = 25°C V5 = –14.0V — 2.0 3.0 kΩ SEGn
VDD ref. V5 = –8.0V — 3.0 4.5 kΩ COMn
Static consumption current I SSQ VIN = VDD or VSS — 0.01 5.0 µA VSS
I5Q V5 = –18.0V VDD ref. — 0.01 15.0 µA V5
Input terminal capacitance C IN Ta = 25°C f = 1MHz — 5.0 8.0 pF *3, *4
Oscillator frequency fOSC Ta = 25°C VDD = 5.0V 19 22 25 kHz
VDD = 2.7V 19 22 25
Input voltage VDD When 3× step-up 2.4 — 6.0 V
When 4× step-up 2.4 — 4.5
Booster output voltage VOUT When 3× VDD Ref. –18.0 — — V VOUT
set-up
Internal Power
Supply Circuit

Voltage regulator cir- VOUT VDD Ref. –18.0 — –6.0 V VOUT

cuit operating voltage
Voltage follower V5 (1) When applied VDD Ref. –16.0 — –6.0 V
operating voltage to the SED1530
V5 (2) When applied VDD Ref. –16.0 — –4.6 V
to the SED1531
Reference voltage VREG Ta = 25°C VDD Ref. –2.65 –2.5 –2.35 V

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SED1530 Series

• Dynamic consumption current value (1) in display, internal power supply ON

Unless otherwise specified, Ta = –40 to 85°C

Parameter Symbol Condition Min Typ Max Unit Remarks
SED1530 IDD (1) VDD = 5.0V, V5 – VDD = –8.0V, 2× Step-up — 41 70 µA
VDD = 3.0V, V5 – VDD = –8.0V, 3× Step-up — 48 80 µA
SED1531 V DD = 5.0V, V5 – VDD = –11.0V, 3× Step-up — 96 160 µA
V DD = 3.0V, V5 – VDD = –11.0V, 4× Step-up — 118 190 µA
SED1532 V DD = 5.0V, V5 – VDD = –11.0V, 3× Step-up — 96 160 µA
V DD = 3.0V, V5 – VDD = –11.0V, 4× Step-up — 114 190 µA

• Current consumption in power save mode

(VSS = 0V, VDD = 2.7 to 5.5V, Ta = 25°C)

Characteristic Symbol Condition Min Typ Max Unit
Standby I DDS1 SED1530, SED1531, SED1532 — 0.01 1.0 µA
I DDS2 SED1530, SED1531, SED1532 — 1.0 2.0 µA

Typical current consumption characteristics:

Dynamic current consumption (1)

LCD display status using an external power supply

• Notes
*1. Although a broad operating voltage range is guaranteed, *3. The A0, D0 to D5, D6, D7 (SI), RD (E), WR (R/W), CS1,
this does not guarantee against sudden voltage changes CS2, FR, M/S, C86, P/S and DOF pins.
during MPU access. *4. The CL, SCL (D6) and RES pins.
*2. The range of operating voltages of the VDD system and V5 *5. The D0 to D5, D6, D7 (SI), FR, FRS, DYO, DOF and CL
system. See the figure below. The range of operating pins.
voltages applies when the external power supply is used.
*6. The A0, RD, (E), WR (R/W), CS1, CS2, M/S, RES, C86
and P/S pins.
The Range of Operating Voltages *7. Applicable when the D0 to D7, FR, CL, DYO and DOF
of the VSS and V5 Systems pins are in a high impedance state.

–20
–16
–15
(V) –13
Operating
–10
Range
V5 – VDD
–5
2.4 3.0
0 2 4 6 8
VDD (V)

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SED1530 Series

• Timing Characteristics
° System Bus: Read/Write Characteristics I (80-Series MPU)

A0
tAW8 tAH8

CS1
(CS2=“1”)
tCYC8
tCCLR, tCCLW tCCHR, tCCHW

WR, RD
tDS8 tDH8

D0 ~ D7
(WRITE)
tACC8 tCH8
D0 ~ D7
(READ)

VDD = 5.0V ± 10%, Ta = –40 to 85°C

Parameter Signal Symbol Conditions Min Max Unit
Address hold time A0 tAH8 10 — ns
Address setup time tAW8 10 — ns
System cycle time tCYC8 200 — ns
Control L pulse width (WR) WR tCCLW 22 — ns
Control L pulse width (RD) RD tCCLR 77 — ns
Control H pulse width (WR) WR tCCHW 172 — ns
Control H pulse width (RD) RD tCCHR 117 — ns
Data setup time D0 ~ D7 tDS8 20 — ns
Data hold time tDH8 10 — ns
RD access time tACC8 CL = 100pF — 70 ns
Output disable time tCH8 10 50 ns

VDD = 2.7 to 4.5V, Ta = –40 to 85°C

Parameter Signal Symbol Conditions Min Max Unit
Address hold time A0 tAH8 25 — ns
Address setup time tAW8 25 — ns
System cycle time tCYC8 450 — ns
Control L pulse width (WR) WR tCCLW 44 — ns
Control L pulse width (RD) RD tCCLR 194 — ns
Control H pulse width (WR) WR tCCHW 394 — ns
Control H pulse width (RD) RD tCCHR 244 — ns
Data setup time D0 ~ D7 tDS8 40 — ns
Data hold time tDH8 20 — ns
RD access time tACC8 CL = 100pF — 140 ns
Output disable time tCH8 10 100 ns
*1. The input signal rise time and fall time (tr, tf) are specified at 15ns or less. When the cycle time is used at high speed,
the specification is tr + tf ≤ (tCYC8 –tCCLW – tCCHW) or tr + tf ≤ (tCYC8 – tCCLR – tCCHR).
*2. All timings are specified based on 20% and 80% of VDD.
*3. tCCLW and tCCLR are specified by the overlap period of CS1 = “0” (CS2 = “1”) and WR, RD = “0” level.

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 SED1530 Series

° System Bus: Read/Write Characteristics I (68-Series MPU)

A0
R/W
tAW6 tAH6

CS1
(CS2=“1”)
tCYC6
tEWHR, tEWHW tEWLR, tEWLW

E
tDS6 tDH6

D0 ~ D7
(WRITE)
tACC6 tOH6
D0 ~ D7
(READ)

VDD = 5.0V ± 10%, Ta = –40 to 85°C

Parameter Signal Symbol Conditions Min Max Unit
System cycle time tCYC6 200 — ns
Address setup time A0 tAW6 10 — ns
Address hold time R/W tAH6 10 — ns
Data setup time D0 ~ D7 tDS6 20 — ns
Data hold time tDH6 10 — ns
Output disable time tOH6 CL = 100pF 10 50 ns
Access time tACC6 — 70 ns
Enable H Read E tEWHR 77 — ns
pulse width Write tEWHW 22 — ns
Enable L Read E tEWLR 117 — ns
pulse width Write tEWLW 172 — ns

VDD = 2.7 to 4.5V, Ta = –40 to 85°C

Parameter Signal Symbol Conditions Min Max Unit
System cycle time tCYC6 450 — ns
Address setup time A0 tAW6 25 — ns
Address hold time R/W tAH6 25 — ns
Data setup time D0 ~ D7 tDS6 40 — ns
Data hold time tDH6 20 — ns
Output disable time tOH6 CL = 100pF 20 50 ns
Access time tACC6 — 70 ns
Enable H Read E tEWHR 194 — ns
pulse width Write tEWHW 44 — ns
Enable L Read E tEWLR 244 — ns
pulse width Write tEWLW 394 — ns

*1. The input signal rise time and fall time (tr, tf) are specified at 15ns or less. When the cycle time is used at high speed,
the specification is tr + tf ≤ (tCYC8 –tEWLW – tEWHW) or tr + tf ≤ (tCYC6 – tEWLR – tEWHR).
*2. All timings are specified based on 20% and 80% of VDD.
*3. tEWHR and tEWHW are specified by the overlap period of CS1 = “0” (CS2 = “1”) and E = “1” level.

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SED1530 Series

° Serial Interface

tCSS tCSH
CS1
(CS2=“1”)
tSAS tSAH

A0

tSCYC
tSLW

SCL tSHW
tf tr
tSDS tSDH

SI

VDD = 5.0V ± 10%, Ta = –40 to 85°C

Parameter Signal Symbol Conditions Min Max Unit
Serial clock period SCL tSCYC 500 — ns
SCL “H” pulse width tSHW 150 — ns
SCL “L” pulse width tSLW 150 — ns
Address setup time A0 tSAS 120 — ns
Address hold time tSAH 200 — ns
Data setup time SI tSDS 120 — ns
Data hold time tSDH 50 — ns
tCSS 30 — ns
CS-SCL time CS
tCSH 400 — ns

VDD = 2.7 to 4.5V, Ta = –40 to 85°C

Parameter Signal Symbol Conditions Min Max Unit
Serial clock period SCL tSCYC 1000 — ns
SCL “H” pulse width tSHW 300 — ns
SCL “L” pulse width tSLW 300 — ns
Address setup time A0 tSAS 250 — ns
Address hold time tSAH 400 — ns
Data setup time SI tSDS 250 — ns
Data hold time tSDH 100 — ns
tCSS 60 — ns
CS-SCL time CS
tCSH 400 — ns

*1. The input signal rise time and fall time (tr, tf) are specified at 15ns or less.
*2. All timings are specified based on 20% and 80% of VDD.

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 SED1530 Series

° Display Control Timing

CL
(OUT)
tDRE

FR
tDOH tDOL

DYO

VDD = 5.0V ± 10%, Ta = –40 to 85°C

Parameter Signal Symbol Conditions Min Typ Max Unit
FR delay time FR tDFR CL = 50pF — 80 150 ns
DYO “H” delay time DYO tDOH — 70 160 ns
DYO “L” delay time tDOL — 70 160 ns

VDD = 2.7 to 4.5V ± 10%, Ta = –40 to 85°C

Parameter Signal Symbol Conditions Min Typ Max Unit
FR delay time FR tDFR CL = 50pF — 120 240 ns
DYO “H” delay time DYO tDOH — 140 250 ns
DYO “L” delay time tDOL — 140 250 ns
*1. Effective only when operating in master mode.
*2. All timings are specified based on 20% or 80% of VDD.

° Reset Timing

tRW
RES

tR

Internal
Reset in Progress Reset Complete
State

VDD = 5.0V ± 10%, Ta = –40 to 85°C

Parameter Signal Symbol Conditions Min Typ Max Unit
Reset time tR 1.0 — — ms
Reset “L” pulse width RES tRW 1.0 — — ms

VDD = 2.7 to 4.5V, Ta = –40 to 85°C

Parameter Signal Symbol Conditions Min Typ Max Unit
Reset time tR 3.0 — — ms
Reset “L” pulse width RES tRW 3.0 — — ms

*1. All timings are specified based on 10% and 90% of VDD.

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SED1530 Series

• Table of Commands for the SED1530 Series

Code
Command Function
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0 Turns the LCD display on and off.
(1) Display ON/OFF 0 1 0 1 0 1 0 1 1 1 1 0: OFF 1: ON
Determines the RAM display line
(2) Display start line set 0 1 0 0 1 Display start address
displayed to COM0.
Sets the display RAM page to the
(3) Page address set 0 1 0 1 0 1 1 Page address
page address register.
Most significant Sets the 4 most significant bits of
(4) Column address set, first 4 bits 0 1 0 0 0 0 1 column address the display RAM column address
bits to the register.
Least significant Sets the 4 least significant bits of
(4) Column address set, last 4 bits 0 1 0 0 0 0 0 column address the display RAM column address
bits to the register.
(5) Status read 0 0 1 Status 0 0 0 0 Read status data.
(6) Write display data 1 1 0 Write data Writes to the display RAM.
(7) Reads display data 1 0 1 Read data Reads from the display RAM.
Sets the relationship between the
0 display RAM address and the SEG
(8) ADC select 0 1 0 1 0 1 0 0 0 0 output
1
0: Normal 1: Reverse
Sets the LCD display to normal/
0 reverse.
(9) Display: Normal/Reverse 0 1 0 1 0 1 0 0 1 1
1
0: Normal 1: Reverse
0 Display: All Pixels Lit
(10) Display: All Pixel Lit: ON/OFF 0 1 0 1 0 1 0 0 1 0
1 0: Normal display 1: All pixels lit
(11) LCD bias set 0 1 0 1 0 1 0 0 0 1 0 Sets the LCD drive voltage ratio.
Increments the column address
(12) Read/modify/write 0 1 0 1 1 1 0 0 0 0 0 counter by 1 when write, zero when
read.
(13) End 0 1 0 1 1 1 0 1 1 1 0 Gets out of read/modify/write mode.
(14) Reset 0 1 0 1 1 1 0 0 0 1 0 Internal reset.
Selects the direction of the COM
(15) Output mode register set 0 1 0 1 1 0 0 0 * * *
output scan. * = disabled
Operating Selects the power supply circuit
(16) Power control set 0 1 0 0 0 1 0 1
mode operating mode.
Electronic Sets the V5 output voltage to the
(17) Electronic volume register set 0 1 0 1 0 0
volume level electronic volume register.
0 Selects the standby mode.
(18) Standby set 0 1 0 1 0 1 0 1 1 0
1 0: OFF 1: ON
A composite command with dis-
(19) Power save play: OFF and Display: All Pixels
On.

Note: Do not use any other command, or a system malfunction may result.

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 SED1530 Series

■ MPU INTERFACE (REFERENCE EXAMPLE)

The SED1530 Series chips can be connected to 80-series and 68-series MPUs. Moreover, by utilizing the
serial interface, the connections can be made with fewer signal lines. When multiple SED1530 chips are used,
each can be connected to the MPU and the chips can be selected using the chip select.

• 80-Series MPU

VDD

VCC A0 A0 VDD
C86
A1 ~ A7 CS1
Decoder
IORQ CS2 VSS
MPU SED1530
D0 ~ D7 D0 ~ D7
VDD
RD RD
WR WR P/S

RES RES
GND VSS
RESET
VSS

• 68-Series MPU

VDD

VDD
VCC A0 A0 VDD
C86
A1 ~ A15 CS1
Decoder
VMA CS2
MPU SED1530
D0 ~ D7 D0 ~ D7
VDD
E E
R/W R/W P/S

RES RES
GND VSS
RESET
VSS

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SED1530 Series

• Serial Interface

VDD

VCC A0 A0 VDD
C86
A1 ~ A7 CS1
Decoder VDD
CS2 or GND
MPU SED1530
1 SI
2 SCL
P/S

RES RES
GND VSS VSS
RESET
VSS

385
 SED1530 Series

■ PIN LAYOUT

51 1

52 172

86 138

87 137

Chip Size: 6.65 X 4.57 mm

Pad Pitch: 118µm (Min.)
SED153*D*A (Aluminum Pad Model)
Pad Center Size: 90 X 90 µm
Chip Thickness: 300 µm

SED153*D*B (Gold Bump Model)

Bump Size: 76 X 76 µm
Bump Height: 17 to 28 µm (Typ)
Chip Thickness: 625 µm

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SED1530 Series

■ PAD COORDINATES
Unit: µm
X Y X Y X Y X Y
No. Pin Name No. Pin Name No. Pin Name No. Pin Name
Coord. Coord. Coord. Coord. Coord. Coord. Coord. Coord.
1 O127 2988 2142 46 O0 –2366 2142 91 O45 –2490 –2142 136 O90 2862 –2142
2 O128 2860 2142 47 O1 –2490 2142 92 O46 –2386 –2142 137 O91 2986 –2142
3 O129 2738 2142 48 O2 –2614 2142 93 O47 –2242 –2142 138 O92 3178 –2006
4 O130 2614 2142 49 O3 –2738 2142 94 O48 –2124 –2142 139 O93 3178 –1888
5 O131 2490 2142 50 O4 –2862 2142 95 O49 –2006 –2142 140 O94 3178 –1770
6 COM3 2386 2142 51 O5 –2986 2142 96 O50 –1888 –2142 141 O95 3178 –1652
7 FR5 2242 2142 52 O6 –3178 2006 97 O51 –1770 –2142 142 O96 3178 –1534
8 FR 2124 2142 53 O7 –3178 1888 98 O52 –1652 –2142 143 O97 3178 –1416
9 DYO 2006 2142 54 O8 –3178 1770 99 O53 –1534 –2142 144 O98 3178 –1298
10 CL 1000 2142 55 O9 –3178 1652 100 O54 –1416 –2142 145 O99 3178 –1180
11 DOF 1770 2142 56 O10 –3178 1534 101 O55 –1298 –2142 146 O100 3178 –1062
12 VSI 1652 2142 57 O11 –3178 1416 102 O56 –1180 –2142 147 O101 3178 –944
13 M/S 1534 2142 58 O12 –3178 1286 103 O57 –1062 –2142 148 O102 3178 –826
14 REG 1416 2142 59 O13 –3178 1150 104 O58 –944 –2142 149 O103 3178 –708
15 P/S 1298 2142 60 O14 –3178 1062 105 O59 –826 –2142 150 O104 3178 –590
16 CS1 1180 2142 61 O15 –3178 944 106 O60 –708 –2142 151 O105 3178 –472
17 CS2 1062 2142 62 O16 –3178 826 107 O61 –590 –2142 152 O106 3178 –354
18 C86 944 2142 63 O17 –3178 708 108 O62 –472 –2142 153 O107 3178 –236
19 A0 826 2142 64 O18 –3178 690 109 O63 –354 –2142 154 O108 3178 –118
20 WR (W/R) 708 2142 65 O19 –3178 472 110 O64 –236 –2142 155 O109 3178 0
21 RD (E) 590 2142 66 O20 –3178 364 111 O65 –118 –2142 156 O110 3178 118
22 VDD 354 2142 67 O21 –3178 238 112 O66 0 –2142 157 O111 3178 236
23 D0 236 2142 68 O22 –3178 118 113 O67 118 –2142 158 O112 3178 354
24 D1 236 2142 69 O23 –3178 0 114 O68 236 –2142 159 O113 3178 472
25 D2 118 2142 70 O24 –3178 –118 115 O69 354 –2142 160 O114 3178 590
26 D3 0 2142 71 O25 –3178 –236 116 O70 472 –2142 161 O115 3178 708
27 D4 –118 2142 72 O26 –3178 –354 117 O71 590 –2142 162 O116 3178 826
28 D5 –236 2142 73 O27 –3178 –472 118 O72 708 –2142 163 O117 3178 944
29 D6 (SCL) –354 2142 74 O28 –3178 –590 119 O73 826 –2142 164 O118 3178 1062
30 D7 (31) –472 2142 75 O29 –3178 –708 120 O74 944 –2142 165 O119 3178 1180
31 VSS –590 2142 76 O30 –3178 –826 121 O75 1062 –2142 166 O120 3178 1298
32 VOUT –708 2142 77 O31 –3178 –944 122 O76 1180 –2142 167 O121 3178 1416
33 CAP3– –826 2142 78 O32 –3178 –1062 123 O77 1298 –2142 168 O122 3178 1534
34 CAP1+ –944 2142 79 O33 –3178 –1180 124 O78 1416 –2142 169 O123 3178 1652
35 CAP1– –1062 2142 80 O34 –3178 –1298 125 O79 1534 –2142 170 O124 3178 1770
36 CAP2+ –1180 2142 81 O35 –3178 –1418 126 O80 1652 –2142 171 O125 3178 1888
37 CAP2– –1298 2142 82 O36 –3178 –1534 127 O81 1770 –2142 172 O126 3178 2006
38 V5 –1416 2142 83 O37 –3178 –1652 128 O82 1888 –2142
39 VR –1534 2142 84 O38 –3178 –1770 129 O83 2006 –2142
40 VDD –1652 2142 85 O39 –3178 –1888 130 O84 2124 –2142
41 V1 –1770 2142 86 O40 –3178 –2006 131 O85 2242 –2142
42 V2 –1888 2142 87 O41 –2986 –2142 132 O86 2366 –2142
43 V3 –2006 2142 88 O42 –2862 –2142 133 O87 2490 –2142
44 V4 –2124 2142 89 O43 –2738 –2142 134 O88 2614 –2142
45 V5 –2242 2142 90 O44 –2614 –2142 135 O89 2738 –2142

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