High Quality, 10-Bit, Digital CCIR-601 To PAL/NTSC Video Encoder

a
High Quality, 10-Bit, Digital CCIR-601

to PAL/NTSC Video Encoder
ADV7175A/ADV7176A*
FEATURES CCIR and Square Pixel Operation
ITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder Integrated Subcarrier Locking to External Video Source
High Quality 10-Bit Video DACs Color Signal Control/Burst Signal Control
Integral Nonlinearity <1 LSB at 10 Bits Interlaced/Noninterlaced Operation
NTSC-M, PAL-M/N, PAL-B/D/G/H/I Complete On-Chip Video Timing Generator
Single 27 MHz Clock Required (ⴛ2 Oversampling) Programmable Multimode Master/Slave Operation
80 dB Video SNR Macrovision Antitaping Rev 7.01 (ADV7175A Only)**
32-Bit Direct Digital Synthesizer for Color Subcarrier Closed Captioning Support
Multistandard Video Output Support: Teletext Insertion Port (PAL-WST)
Composite (CVBS) Onboard Color Bar Generation
Component S-Video (Y/C) Onboard Voltage Reference
Component YUV and RGB 2-Wire Serial MPU Interface (I 2C Compatible)
EuroSCART Output (RGB + CVBS/LUMA) Single Supply 5 V or 3 V Operation
Video Input Data Port Supports: Small 44-Lead MQFP Thermally Enhanced Package
CCIR-656 4:2:2 8-Bit Parallel Input Format
APPLICATIONS
4:2:2 16-Bit Parallel Input Format
MPEG-1 and MPEG-2 Video, DVD, Digital Satellite/
Full Video Output Drive or Low Signal Drive Capability
Cable Systems (Set Top Boxes/IRDs), Digital TVs,
34.7 mA max into 37.5 ⍀ (Doubly-Terminated 75R)
CD Video/Karaoke, Video Games, PC Video/Multimedia
5 mA min with External Buffers
Programmable Simultaneous Composite
and S-Video Y/C or RGB (SCART)/YUV Video Outputs
Programmable Luma Filters (Low-Pass/Notch/Extended) GENERAL DESCRIPTION
Programmable VBI (Vertical Blanking Interval) The ADV7175A/ADV7176A is an integrated digital video encoder
Programmable Subcarrier Frequency and Phase that converts Digital CCIR-601 4:2:2 8 or 16-bit component
Programmable LUMA Delay video data into a standard analog baseband television signal
Individual ON/OFF Control of Each DAC (Continued on page 11)
FUNCTIONAL BLOCK DIAGRAM
M
U
TELETEXT 10
TTX L 10-BIT DAC D (PIN 27)
INSERTION T DAC
TTXREQ BLOCK YUV TO I
RBG P 10 10-BIT
MATRIX L DAC C (PIN 26)
DAC
VAA E
X 10 10-BIT
E DAC B (PIN 31)
DAC
Y R
8 8 8 8 10
ADD INTER- LOW-PASS
COLOR SYNC POLATOR FILTER
DATA
P7–P0 4:2:2 TO 8 YCrCb U
8 8 8 10
4:4:4 TO ADD INTER- LOW-PASS
INTER- YUV BURST POLATOR FILTER 10
P15–P8 POLATOR MATRIX 10-BIT DAC A (PIN 32)
DAC
8 8 8 8 V 10
ADD INTER- LOW-PASS
BURST POLATOR FILTER ADV7175A/ADV7176A
10 10
HSYNC
REAL-TIME VREF
FIELD/VSYNC VIDEO TIMING I2C MPU PORT VOLTAGE
CONTROL SIN/COS
GENERATOR REFERENCE RSET
BLANK CIRCUIT DDS BLOCK CIRCUIT COMP
CLOCK RESET SCLOCK SDATA ALSB SCRESET/RTC GND
*Protected by U.S. patents numbers 5,343,196 and 5,442,355 and other intellectual property rights.
**This device is protected by U.S. Patent Numbers 4631603, 4577216, 4819098 and other intellectual property rights. The Macrovision anticopy process is
licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available.
NOTE: ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000
ADV7175A/ADV7176A–SPECIFICATIONS
5 V SPECIFICATIONS (V AA = 5 V ⴞ 5%1, VREF = 1.235 V, RSET = 150 ⍀. All specifications TMIN to TMAX2 unless otherwise noted)
Parameter Conditions1 Min Typ Max Unit
STATIC PERFORMANCE
Resolution (Each DAC) 10 Bits
Accuracy (Each DAC)
Integral Nonlinearity ±1 LSB
Differential Nonlinearity Guaranteed Monotonic ±1 LSB
DIGITAL INPUTS
Input High Voltage, VINH 2 V
Input Low Voltage, VINL 0.8 V
Input Current, IIN3 VIN = 0.4 V or 2.4 V ±1 µA
Input Current, IIN4 VIN = 0.4 V or 2.4 V ± 50 µA
Input Capacitance, CIN 10 pF
DIGITAL OUTPUTS
Output High Voltage, VOH ISOURCE = 400 µA 2.4 V
Output Low Voltage, VOL ISINK = 3.2 mA 0.4 V
Three-State Leakage Current 10 µA
Three-State Output Capacitance 10 pF
ANALOG OUTPUTS
Output Current5 33 34.7 37 mA
Output Current6 5 mA
DAC-to-DAC Matching 0.6 5 %
Output Compliance, VOC 0 1.4 V
Output Impedance, ROUT 15 kΩ
Output Capacitance, COUT IOUT = 0 mA 30 pF
VOLTAGE REFERENCE
Reference Range, VREF IVREFOUT = 20 µA 1.112 1.235 1.359 V
POWER REQUIREMENTS7
VAA 4.75 5.0 5.25 V
Normal Power Mode
IDAC (max)8 150 155 mA
IDAC (min)8 20 mA
ICCT9 100 150 mA
Low Power Mode
IDAC (max)8 80 mA
IDAC (min)8 15 mA
ICCT9 100 150 mA
Power Supply Rejection Ratio COMP = 0.1 µF 0.01 0.5 %/%
NOTES
1
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2
Temperature range T MIN to TMAX: 0°C to 70°C.
3
All digital input pins except pins RESET and RTC/SCRESET.
4
Excluding all digital input pins except pins RESET and RTC/SCRESET.
5
Full drive into 37.5 Ω load.
6
Minimum drive current (used with buffered/scaled output load).
7
Power measurements are taken with Clock Frequency = 27 MHz. Max T J = 110°C.
8
IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all four DACs. Turning off individual
DACs reduces I DAC correspondingly.
9
ICCT (Circuit Current) is the continuous current required to drive the device.
Specifications subject to change without notice.
–2– REV. C
ADV7175A/ADV7176A
3.3 V SPECIFICATIONS (V AA = 3.0 V–3.6 V , VREF = 1.235 V, RSET = 300 ⍀. All specifications TMIN to TMAX2 unless otherwise noted)
1

3
STATIC PERFORMANCE
Resolution (Each DAC) 10 Bits
Accuracy (Each DAC)
Integral Nonlinearity ±1 LSB
Differential Nonlinearity Guaranteed Monotonic ±1 LSB
DIGITAL INPUTS
Input High Voltage, VINH 2 V
Input Low Voltage, VINL 0.8 V
Input Current, IIN3, 4 VIN = 0.4 V or 2.4 V ±1 µA
Input Current, IIN3, 5 VIN = 0.4 V or 2.4 V ± 50 µA
Input Capacitance, CIN 10 pF
DIGITAL OUTPUTS
Output High Voltage, VOH ISOURCE = 400 µA 2.4 V
Output Low Voltage, VOL ISINK = 3.2 mA 0.4 V
Three-State Leakage Current3 10 µA
Three-State Output Capacitance3 10 pF
ANALOG OUTPUTS3
Output Current6, 7 16.5 17.35 18.5 mA
Output Current8 5 mA
DAC-to-DAC Matching 2.0 %
Output Compliance, VOC 0 1.4 V
Output Impedance, ROUT 15 kΩ
Output Capacitance, COUT IOUT = 0 mA 30 pF
3, 9
POWER REQUIREMENTS
VAA 3.0 3.3 3.6 V
Normal Power Mode
IDAC (max)10 150 155 mA
IDAC (min)10 20 mA
ICCT9 45 mA
Low Power Mode
IDAC (max)10 75 mA
IDAC (min)10 15 mA
ICCT11 45 mA
Power Supply Rejection Ratio COMP = 0.1 µF 0.01 0.5 %/%
NOTES
11
12
13
Guaranteed by characterization.
14
All digital input pins except pins RESET and RTC/SCRESET.
15
Excluding all digital input pins except pins RESET and RTC/SCRESET.
16
Full drive into 37.5 Ω load.
17
DACs can output 35 mA typically at 3.3 V (R SET = 150 Ω and RL = 75 Ω), optimum performance obtained at 18 mA DAC current (R SET = 300 Ω and RL = 150 Ω.
18
Minimum drive current (used with buffered/scaled output load).
19
Power measurements are taken with Clock Frequency = 27 MHz. Max T J = 110°C.
10
IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all four DACs. Turning off individual
DACs reduces I DAC correspondingly.
11
ICCT (Circuit Current) is the continuous current required to drive the device.
REV. C –3–
ADV7175A/ADV7176A–SPECIFICATIONS
1 (VAA = 4.75 V–5.25 V , VREF = 1.235 V, RSET = 150 ⍀. All specifications TMIN to TMAX
1 2
5 V DYNAMIC SPECIFICATIONS unless otherwise noted.)

Filter Characteristics
Luma Bandwidth3 (Low-Pass Filter) NTSC Mode
Stopband Cutoff >54 dB Attenuation 7.0 MHz
Passband Cutoff F3 dB >3 dB Attenuation 4.2 MHz
Chroma Bandwidth NTSC Mode
Luma Bandwidth3 (Low-Pass Filter) PAL Mode
Chroma Bandwidth PAL Mode
Differential Gain4 Normal Power Mode 0.4 %
Differential Phase4 Normal Power Mode 0.4 Degree
Differential Gain4 Lower Power Mode 2.0 %
Differential Phase4 Lower Power Mode 1.0 Degree
SNR4 (Pedestal) RMS 80 dB rms
SNR4 (Pedestal) Peak Periodic 70 dB p-p
SNR4 (Ramp) RMS 60 dB rms
SNR4 (Ramp) Peak Periodic 58 dB p-p
Hue Accuracy4 0.5 Degree
Color Saturation Accuracy4 1.0 %
Chroma Nonlinear Gain4 Referenced to 40 IRE 0.6 ±%
Chroma Nonlinear Phase4 NTSC 0.2 ± Degree
Chroma Nonlinear Phase4 PAL 0.4 ± Degree
Chroma/Luma Intermod4 Referenced to 714 mV (NTSC) 0.1 ±%
Chroma/Luma Intermod4 Referenced to 700 mV (PAL) 0.1 ±%
Chroma/Luma Gain Ineq4 0.6 ±%
Chroma/Luma Delay Ineq4 2.0 ns
Luminance Nonlinearity4 1.0 ±%
Chroma AM Noise4 66 dB
Chroma PM Noise4 63 dB
NOTES
1
2
3
These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4.
4
–4– REV. C
ADV7175A/ADV7176A
(VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET = 300 ⍀. All specifications TMIN to TMAX2
3.3 V DYNAMIC SPECIFICATIONS1 unless otherwise noted.)
Filter Characteristics
Luma Bandwidth3 (Low-Pass Filter) NTSC Mode
Chroma Bandwidth NTSC Mode
Luma Bandwidth3 (Low-Pass Filter) PAL Mode
Chroma Bandwidth PAL Mode
Differential Gain4 Normal Power Mode 0.7 %
Differential Phase4 Normal Power Mode 0.5 Degree
SNR4 (Pedestal) RMS 75 dB rms
SNR4 (Pedestal) Peak Periodic 68 dB p-p
SNR4 (Ramp) RMS 58 dB rms
SNR4 (Ramp) Peak Periodic 56 dB p-p
Hue Accuracy4 1.0 Degree
Color Saturation Accuracy4 1.2 %
Luminance Nonlinearity4 1.1 ±%
Chroma AM Noise4 NTSC 67 dB
Chroma PM Noise4 NTSC 63 dB
Chroma AM Noise4 PAL 64 dB
Chroma PM Noise4 PAL 63 dB
NOTES
1
2
3
These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4.
4
REV. C –5–
ADV7175A/ADV7176A
(V = 4.75 V–5.25 V , V AA
1
REF = 1.235 V, RSET = 150 ⍀. All specifications TMIN to TMAX2 unless
5 V TIMING SPECIFICATIONS otherwise noted.)
Parameter Conditions Min Typ Max Unit
MPU PORT3, 4
SCLOCK Frequency 0 100 kHz
SCLOCK High Pulsewidth, t1 4.0 µs
SCLOCK Low Pulsewidth, t2 4.7 µs
Hold Time (Start Condition), t3 After This Period the First Clock Is Generated 4.0 µs
Setup Time (Start Condition), t4 Relevant for Repeated Start Condition 4.7 µs
Data Setup Time, t5 250 ns
SDATA, SCLOCK Rise Time, t6 1 µs
SDATA, SCLOCK Fall Time, t7 300 ns
Setup Time (Stop Condition), t8 4.7 µs
3, 5
ANALOG OUTPUTS
Analog Output Delay 5 ns
DAC Analog Output Skew 0 ns
CLOCK CONTROL
AND PIXEL PORT3, 6
FCLOCK 27 MHz
Clock High Time, t9 8 ns
Clock Low Time, t10 8 ns
Data Setup Time, t11 3.5 ns
Data Hold Time, t12 4 ns
Control Setup Time, t11 4 ns
Control Hold Time, t12 3 ns
Digital Output Access Time, t13 24 ns
Digital Output Hold Time, t14 4 ns
Pipeline Delay, t15 37 Clock Cycles
TELETEXT PORT3, 7
RESET CONTROL3, 4
RESET Low Time 6 ns
NOTES
1
The max/min specifications are guaranteed over this range.
2
3
TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.
4
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
Pixel Port consists of the following:
Pixel Inputs: P15–P0
Pixel Controls: HSYNC, FIELD/VSYNC, BLANK
Clock Input: CLOCK
7
Teletext Port consists of the following:
Teletext Output: TTXREQ
Teletext Input: TTX
–6– REV. C
ADV7175A/ADV7176A
(VAA = 3.0–3.61, VREF = 1.235 V, RSET = 300 ⍀. All specifications TMIN to TMAX2 unless
3.3 V TIMING SPECIFICATIONS otherwise noted.)
Parameter Conditions Min Typ Max Unit

3, 4
MPU PORT
SCLOCK Frequency 0 100 kHz
SCLOCK High Pulsewidth, t1 4.0 µs
SCLOCK Low Pulsewidth, t2 4.7 µs
Hold Time (Start Condition), t3 After This Period the First Clock Is Generated 4.0 µs
Setup Time (Start Condition), t4 for Repeated Start Condition 4.7 µs
SDATA, SCLOCK Rise Time, t6 1 µs
SDATA, SCLOCK Fall Time, t7 300 ns
Setup Time (Stop Condition), t8 4.7 µs
3, 5
ANALOG OUTPUTS
Analog Output Delay 7 ns
DAC Analog Output Skew 0 ns
CLOCK CONTROL
AND PIXEL PORT3, 4, 6, 7
FCLOCK 27 MHz
Clock High Time, t9 8 ns
Clock Low Time, t10 8 ns
Data Setup Time, t11 3.5 ns
Control Setup Time, t11 4 ns
Control Hold Time, t12 3 ns
Digital Output Hold Time, t14 4 ns
Pipeline Delay, t15 37 Clock Cycles
TELETEXT PORT3, 6, 8
Digital Output Access Time t16 23 ns
RESET CONTROL3, 4
RESET Low Time 6 ns
NOTES
1
The max/min specifications are guaranteed over this range.
2
Temperature range T MIN to TMAX: 0oC to 70oC.
3
TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.
4
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
Characterized by design.
7
Pixel Port consists of the following:
Pixel Inputs: P15–P0
Pixel Controls: HSYNC, FIELD/VSYNC, BLANK
Clock Input: CLOCK
8
Teletext Port consists of the following:
Teletext Output: TTXREQ
Teletext Input: TTX
REV. C –7–
ADV7175A/ADV7176A
t5
t3 t3
SDATA
t6
t1
SCLOCK
t2
t7 t4 t8
Figure 1. MPU Port Timing Diagram
CLOCK
t9 t10 t12
HSYNC,
CONTROL FIELD/VSYNC,
I/PS BLANK
PIXEL INPUT
Cb Y Cr Y Cb Y
DATA
t11 t13
HSYNC,
CONTROL FIELD/VSYNC,
O/PS BLANK
t14
Figure 2. Pixel and Control Data Timing Diagram
TTXREQ
t 16
CLOCK
t 17
t 18
TTX
4 CLOCK 4 CLOCK 4 CLOCK 3 CLOCK

CYCLES CYCLES CYCLES CYCLES
Figure 3. Teletext Timing Diagram
–8– REV. C
ADV7175A/ADV7176A
ABSOLUTE MAXIMUM RATINGS 1 PACKAGE THERMAL PERFORMANCE
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V The 44-MQFP package used for this device takes advantage of
Voltage on Any Digital Input Pin . GND – 0.5 V to VAA + 0.5 V an ADI patented thermal coastline lead frame construction.
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C This maximizes heat transfer into the leads and reduces the
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . 150°C package thermal resistance.
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . 260°C The junction-to-ambient (θJA) thermal resistance in still air on a
Analog Outputs to GND2 . . . . . . . . . . . . . GND – 0.5 to VAA four-layer PCB is 35.5°C/W. The junction-to-case thermal
NOTES resistance (θJC) is 13.75°C/W.
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Analog output short circuit to any power supply or common can be of an indefinite
duration.
ORDERING GUIDE
Temperature Package Package

Model Range Description Option
ADV7175AKS 0°C to 70°C Plastic Quad Flatpack S-44
ADV7176AKS 0°C to 70°C Plastic Quad Flatpack S-44
PIN CONFIGURATION
TTXREQ/GND
SCRESET/
TTX/VAA
CLOCK
RSET
GND
RTC
P3
P1
P0
P2
P4
44 43 42 41 40 39 38 37 36 35 34
VAA 1 33 VREF
PIN 1
P5 2 IDENTIFIER 32 DAC A
P6 3 31 DAC B
P7 4 30 VAA
P8 5 29 GND
ADV7175A/ADV7176A
P9 6 MQFP 28 VAA
P10 7 TOP VIEW 27 DAC D

(Not to Scale)
P11 8 26 DAC C
P12 9 25 COMP
GND 10 24 SDATA
VAA 11 23 SCLOCK
12 13 14 15 16 17 18 19 20 21 22
P13
ALSB
FIELD/VSYNC
P15
GND
GND
P14
VAA
RESET
BLANK
HSYNC
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the ADV7175A/ADV7176A feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,
ESD SENSITIVE DEVICE
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. C –9–
ADV7175A/ADV7176A
PIN FUNCTION DESCRIPTIONS
Pin Input/
No. Mnemonic Output Function
1, 11, 20,
28, 30 VAA P Power Supply (3 V to 5 V).
10, 19, 21,
29, 43 GND G Ground Pin.
15 HSYNC I/O HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to
output (Master Mode) or accept (Slave Mode) Sync signals.
16 FIELD/VSYNC I/O Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This
pin may be configured to output (Master Mode) or accept (Slave Mode)
these control signals.
17 BLANK I/O Video Blanking Control Signal. The pixel inputs are ignored when this is
logic level “0.” This signal is optional.
18 ALSB I TTL Address Input. This signal sets up the LSB of the MPU address.
22 RESET I The input resets the on chip timing generator and sets the ADV7175A/
ADV7176A into default mode. This is NTSC operation, Timing Slave Mode
0, 8-bit operation, 2 × composite and S-Video out and all DACs powered on.
23 SCLOCK I MPU Port Serial Interface Clock Input.
24 SDATA I/O MPU Port Serial Data Input/Output.
25 COMP O Compensation Pin. Connect a 0.1 µF capacitor from COMP to VAA. For
Optimum Dynamic Performance in Low Power Mode, the value of the
COMP capacitor can be lowered to as low as 2.2 nF.
26 DAC C O RED/S-Video C/V Analog Output.
27 DAC D O GREEN/S-Video Y/Y Analog Output.
31 DAC B O BLUE/Composite/U Analog Output.
32 DAC A O PAL/NTSC Composite Video Output. Full-Scale Output is 180IRE (1286
mV) for NTSC and 1300 mV for PAL.
33 VREF I/O Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
34 RSET I A 150 Ω resistor connected from this pin to GND is used to control full-scale
amplitudes of the video signals.
35 SCRESET/RTC I This pin can be configured as an input by setting MR22 and MR21 of Mode
Register 2. It can be configured as a subcarrier reset pin, in which case a low-
to-high transition on this pin will reset the subcarrier to Field 0. Alternatively
it may be configured as a Real Time Control (RTC) input.
36 TTXREQ/GND O Teletext Data Request Signal/Defaults to GND when Teletext not selected
(enables backward compatibility to ADV7175/ADV7176).
37 TTX/VAA I Teletext Data/Defaults to VAA when Teletext not selected (enables backward
compatibility to ADV7175/ADV7176).
38–42 P0–P15 I 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or
2–9, 12–14 16-Bit YCrCb Pixel Port (P0–P15). P0 represents the LSB.
44 CLOCK I TTL Clock Input. Requires a stable 27 MHz reference Clock for standard
operation. Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be
used for square pixel operation.
–10– REV. C
ADV7175A/ADV7176A
(Continued from page 1) DATA PATH DESCRIPTION
compatible with worldwide standards. The 4:2:2 YUV video For PAL B, D, G, H, I, M, N and NTSC M modes, YCrCb
data is interpolated to two times the pixel rate. The color- 4:2:2 data is input via the CCIR-656 compatible pixel port at a
difference components (UV) are quadrature modulated using 27 MHz Data Rate. The pixel data is demultiplexed to from
a subcarrier frequency generated by an on-chip 32-bit digital three data paths. Y typically has a range of 16 to 235, Cr and
synthesizer (also running at two times the pixel rate). The two Cb typically have a range of 128 ± 112; however, it is pos-
times pixel rate sampling allows for better signal-to-noise-ratio. sible to input data from 1 to 254 on both Y, Cb and Cr. The
A 32-bit DDS with a 10-bit look-up table produces a superior ADV7175A/ADV7176A supports PAL (B, D, G, H, I, N, M)
subcarrier in terms of both frequency and phase. In addition to and NTSC (with and without Pedestal) standards. The appropri-
the composite output signal, there is the facility to output S- ate SYNC, BLANK and Burst levels are added to the YCrCb
Video (Y/C) video, YUV or RGB video. The Y/C, YUV or RGB data. Macrovision antitaping (ADV7175A only), closed caption-
format is simultaneously available at the analog outputs with the ing and teletext levels are also added to Y, and the resultant
composite video signal. data is interpolated to a rate of 27 MHz. The interpolated data
is filtered and scaled by three digital FIR filters.
Each analog output is capable of driving the full video-level
(35 mA) signal into an unbuffered, doubly terminated 75 Ω The U and V signals are modulated by the appropriate subcarrier
load. With external buffering, the user has the additional option sine/cosine phases and added together to make up the chromi-
to scale back the DAC output current to 5 mA min, thereby signifi- nance signal. The luma (Y) signal can be delayed 1–3 luma
cantly reducing the power dissipation of the device. cycles (each cycle is 74 ns) with respect to the chroma signal.
The luma and chroma signals are then added together to make
The ADV7175A/ADV7176A also supports both PAL and NTSC
up the composite video signal. All edges are slew rate limited.
square pixel operation.
The YCrCb data is also used to generate RGB data with
The output video frames are synchronized with the incoming
appropriate SYNC and BLANK levels. The RGB data is in
data timing reference codes. Optionally the encoder accepts
synchronization with the composite video output. Alternatively
(and can generate) HSYNC, VSYNC and FIELD timing signals.
analog YUV data can be generated instead of RGB.
These timing signals can be adjusted to change pulsewidth and
position while the part is in the master mode. The encoder The four 10-bit DACs can be used to output:
requires a single two times pixel rate (27 MHz) clock for standard 1. Composite Video + RGB Video.
operation. Alternatively, the encoder requires a 24.5454 MHz 2. Composite Video + YUV Video
clock for NTSC or 29.5 MHz clock for PAL square pixel 3. Two Composite Video Signals + LUMA and CHROMA
mode operation. All internal timing is generated on-chip. 3. (Y/C) Signals.
A separate teletext port enables the user to directly input teletext Alternatively, each DAC can be individually powered off if
data during the vertical blanking interval. not required.
The ADV7175A/ADV7176A modes are set up over a two-wire Video output levels are illustrated in Appendix 4 and Appendix 5.
serial bidirectional port (I2C Compatible) with two slave addresses.
Functionally the ADV7175A and ADV7176A are the same with INTERNAL FILTER RESPONSE
the exception that the ADV7175A can output the Macrovision The Y filter supports several different frequency responses,
anticopy algorithm. including two 4.5 MHz/5.0 MHz low pass responses, PAL/
NTSC subcarrier notch responses and a PAL/NTSC extended
The ADV7175A/ADV7176A is packaged in a 44-lead thermally
response. The U and V filters have a 2/2.4 MHz low-pass
enhanced MQFP package.
response for NTSC/PAL. These filter characteristics are illus-
trated in Figures 4 to 12.
PASSBAND PASSBAND STOPBAND STOPBAND

FILTER SELECTION CUTOFF (MHz) RIPPLE (dB) CUTOFF (MHz) ATTENUATION (dB) F3dB
MR04 MR03
NTSC 0 0 2.3 0.026 7.0 >54 4.2
PAL 0 0 3.4 0.098 7.3 >50 5.0
NTSC 0 1 1.0 0.085 3.57 >27.6 2.1
PAL 0 1 1.4 0.107 4.43 >29.3 2.7
NTSC/PAL 1 0 4.0 0.150 7.5 >40 5.65
NTSC 1 1 2.3 0.054 7.0 >54 4.2
PAL 1 1 3.4 0.106 7.3 >50.3 5.0
Figure 4. Luminance Internal Filter Specifications
PASSBAND PASSBAND STOPBAND STOPBAND ATTENUATION @

FILTER SELECTION CUTOFF (MHz) RIPPLE (dB) CUTOFF (MHz) ATTENUATION (dB) 1.3MHz (dB) F3dB
NTSC 1.0 0.085 3.2 >40 0.3 2.05

PAL 1.3 0.04 4.0 >40 0.02 2.45
Figure 5. Chrominance Internal Filter Specifications
REV. C –11–
ADV7175A/ADV7176A
0 0
–10 –10
TYPE A
–20 –20
AMPLITUDE – dB
AMPLITUDE – dB
–30 –30
–40 –40
–50 –50
TYPE B
–60 –60
0 2 4 6 8 10 12 0 2 4 6 8 10 12
FREQUENCY – MHz FREQUENCY – MHz
Figure 6. NTSC Low-Pass Filter Figure 9. PAL Notch Filter
0 0
–10 –10
–20 –20
AMPLITUDE – dB
AMPLITUDE – dB
–30 –30
–40 –40
–50 –50
–60 –60
0 2 4 6 8 10 12 0 2 4 6 8 10 12
Figure 7. NTSC Notch Filter Figure 10. NTSC/PAL Extended Mode Filter
0 0
–10 –10
TYPE B
–20 –20
AMPLITUDE – dB
AMPLITUDE – dB
–30 –30
–40 –40
TYPE A
–50 –50
–60 –60
0 2 4 6 8 10 12 0 2 4 6 8 10 12
Figure 8. PAL Low-Pass Filter Figure 11. NTSC UV Filter
–12– REV. C
ADV7175A/ADV7176A
0 SUBCARRIER RESET
Together with the SCRESET/RTC PIN and Bits MR22 and
–10 MR21 of Mode Register 2, the ADV7175A/ADV7176A can be
used in subcarrier reset mode. The subcarrier will reset to
–20
Field 0 at the start of the following field when a low to high
AMPLITUDE – dB
transition occurs on this input pin.

–30
REAL TIME CONTROL
Together with the SCRESET/RTC PIN and Bits MR22 and
–40 MR21 of Mode Register 2, the ADV7175A/ADV7176A can be
used to lock to an external video source. The real time control
–50 mode allows the ADV7175A/ADV7176A to automatically alter
the subcarrier frequency to compensate for line length variation.
–60 When the part is connected to a device that outputs a digital
0 2 4 6 8 10 12
FREQUENCY – MHz
datastream in the RTC format (such as an ADV7185 video
decoder [see Figure 13]), the part will automatically change to
Figure 12. PAL UV Filter the compensated subcarrier frequency on a line by line basis.
This digital datastream is 67 bits wide and the subcarrier is
COLOR BAR GENERATION
contained in Bits 0 to 21. Each bit is two clock cycles long.
The ADV7175A/ADV7176A can be configured to generate
00HEX should be written to all four subcarrier frequency regis-
100/7.5/75/7.5 for NTSC color bars or 100/0/75/0 for PAL
ters when using this mode.
color bars. These are enabled by setting MR17 of Mode Reg-
ister 1 to Logic “1.”
VIDEO TIMING DESCRIPTION
The ADV7175A/ADV7176A is intended to interface to off-
SQUARE PIXEL MODE
the-shelf MPEG1 and MPEG2 Decoders. Consequently, the
The ADV7175A/ADV7176A can be used to operate in square
ADV7175A/ADV7176A accepts 4:2:2 YCrCb Pixel Data via a
pixel mode. For NTSC operation an input clock of 24.5454 MHz
CCIR-656 pixel port and has several video timing modes of
is required. Alternatively an input clock of 29.5 MHz is required
operation that allow it to be configured as either system master
for PAL operation. The internal timing logic adjusts accordingly
video timing generator or a slave to the system video timing
for square pixel mode operation.
generator. The ADV7175A/ADV7176A generates all of the
required horizontal and vertical timing periods and levels for the
COLOR SIGNAL CONTROL
analog video outputs.
The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2. The ADV7175A/ADV7176A calculates the width and place-
ment of analog sync pulses, blanking levels and color burst
BURST SIGNAL CONTROL envelopes. Color bursts are disabled on appropriate lines, and
The burst information can be switched on and off the video serration and equalization pulses are inserted where required.
output using Bit MR25 of Mode Register 2. In addition the ADV7175A/ADV7176A supports a PAL or
NTSC square pixel operation in slave mode. The part requires
NTSC PEDESTAL CONTROL an input pixel clock of 24.5454 MHz for NTSC and an input
The pedestal on both odd and even fields can be controlled on a pixel clock of 29.5 MHz for PAL. The internal horizontal line
line-by-line basis using the NTSC Pedestal Control Registers. counters place the various video waveform sections in the cor-
This allows the pedestals to be controlled during the vertical rect location for the new clock frequencies.
blanking interval (Lines 10 to 25 and Lines 273 to 288).
The ADV7175A/ADV7176A has four distinct master and four
distinct slave timing configurations. Timing Control is estab-
PIXEL TIMING DESCRIPTION
lished with the bidirectional SYNC, BLANK and FIELD/
The ADV7175A/ADV7176A can operate in either 8-bit or
VSYNC pins. Timing Mode Register 1 can also be used to vary
16-bit YCrCb Mode.
the timing pulsewidths and where they occur in relation to
8-Bit YCrCb Mode each other.
This default mode accepts multiplexed YCrCb inputs through
the P7-P0 pixel inputs. The inputs follow the sequence Cb0, Y0
Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a
rising clock edge.
16-Bit YCrCb Mode
This mode accepts Y inputs through the P7–P0 pixel inputs and
multiplexed CrCb inputs through the P15–P8 pixel inputs. The
data is loaded on every second rising edge of CLOCK. The inputs
follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
REV. C –13–
ADV7175A/ADV7176A
CLOCK
LLC1 SCRESET/RTC
GLL
COMPOSITE
VIDEO GREEN/LUMA/Y
e.g., VCR P7–P0 RED/CHROMA/V
OR CABLE VIDEO P19–P12
DECODER BLUE/COMPOSITE/U
ADV7185 HSYNC
COMPOSITE
VSYNC/FIELD
ADV7175A/ADV7176A
SEQUENCE RESERVED
H/LTRANSITION BIT2 RESET
4 BITS 5 BITS
COUNT START RESERVED RESERVED BIT3
LOW
14 BITS
128
RESERVED
0 FSCPLL INCREMENT1 0
13 21
RTC
TIME SLOT: 01 14 19 67 68
NOT USED IN
ADV7175A/ADV7176A VALID INVALID 8/LLC
SAMPLE SAMPLE
NOTES:
1F PLL INCREMENT IS 22 BITS LONG, VALUED LOADED INTO ADV7175A/ADV7176A FSC DDS REGISTER IS
SC
FSC PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUB CARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD
BE WRITTEN TO THE SUB CARRIER FREQUENCY REGISTERS OF THE ADV7175A/ADV7176A.
2SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE.
3RESET BIT
RESET ADV7175A/ADV7176A’s DDS.
Figure 13. RTC Timing and Connections

Vertical Blanking Data Insertion
It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not bear line sync or pre/post-equalization
pulses (see Figures 15 to 26). This mode of operation is called “Partial Blanking” and is selected by setting MR31 to 1. It allows the
insertion of any VBI data (Opened VBI) into the encoded output waveform. This data is present in digitized incoming YCbCr data
stream (e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines by
setting MR31 to 0.
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7175A/ADV7176A is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel
data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 14. The HSYNC, FIELD/VSYNC and
BLANK (if not used) pins should be tied high during this mode.
–14– REV. C
ADV7175A/ADV7176A
ANALOG
VIDEO
EAV CODE SAV CODE

C F 0 0 X 8 1 8 1 0 F F A A A 8 1 8 1 F 0 0 X C Y C Y C C C
INPUT PIXELS Y Y Y r Y b
r F 0 0 Y 0 0 0 0 0 F F B B B 0 0 0 0 F 0 0 Y b r b
ANCILLARY DATA
(HANC)
4 CLOCK 4 CLOCK
NTSC/PAL M SYSTEM 268 CLOCK 1440 CLOCK
(525 LlNES/60Hz)
4 CLOCK 4 CLOCK
PAL SYSTEM
280 CLOCK 1440 CLCOK
(625 LINES/50Hz)
END OF ACTIVE START OF ACTIVE
VIDEO LINE VIDEO LINE
Figure 14. Timing Mode 0 (Slave Mode)

Mode 0 (CCIR-656): Master Option
The ADV7175A/ADV7176A generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video)
time codes in the CCIR-656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin, and the F bit
is output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 15 (NTSC) and Figure 16 (PAL). The H, V and F transitions
relative to the video waveform are illustrated in Figure 17.
DISPLAY DISPLAY
VERTICAL BLANK
522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22
F EVEN FIELD ODD FIELD
DISPLAY DISPLAY
VERTICAL BLANK
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285
F ODD FIELD EVEN FIELD
Figure 15. Timing Mode 0 (NTSC Master Mode)
REV. C –15–
ADV7175A/ADV7176A
DISPLAY DISPLAY
VERTICAL BLANK
622 623 624 625 1 2 3 4 5 6 7 21 22 23
F EVEN FIELD ODD FIELD
DISPLAY DISPLAY
VERTICAL BLANK
309 310 311 312 313 314 315 316 317 318 319 320 334 335 336
F ODD FIELD EVEN FIELD
Figure 16. Timing Mode 0 (PAL Master Mode)
ANALOG
VIDEO
Figure 17. Timing Mode 0 Data Transitions (Master Mode)
–16– REV. C
ADV7175A/ADV7176A
Mode 1: Slave Option HSYNC, BLANK, FIELD
In this mode the ADV7175A/ADV7176A accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled
the ADV7175A/ADV7176A automatically blanks all normally blank lines. Mode 1 is illustrated in Figure 18 (NTSC) and Fig-
ure 19 (PAL).
DISPLAY DISPLAY
VERTICAL BLANK
522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22
HSYNC
BLANK
FIELD EVEN FIELD ODD FIELD
DISPLAY DISPLAY
VERTICAL BLANK
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285
HSYNC
BLANK
FIELD ODD FIELD EVEN FIELD
Figure 18. Timing Mode 1 (NTSC)
DISPLAY DISPLAY
VERTICAL BLANK
622 623 624 625 1 2 3 4 5 6 7 21 22 23
HSYNC
BLANK
DISPLAY DISPLAY
VERTICAL BLANK
309 310 311 312 313 314 315 316 317 318 319 320 334 335 336
HSYNC
BLANK
Figure 19. Timing Mode 1 (PAL)
REV. C –17–
ADV7175A/ADV7176A
Mode 1: Master Option HSYNC, BLANK, FIELD
In this mode the ADV7175A/ADV7176A can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines. Pixel data is latched on the rising clock edge
following the timing signal transitions. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). Figure 20 illustrates the
HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data.
HSYNC
FIELD
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
BLANK
PIXEL
DATA Cb Y Cr Y
PAL = 132 * CLOCK/2

NTSC = 122 * CLOCK/2
Figure 20. Timing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2: Slave Option HSYNC, VSYNC, BLANK

In this mode the ADV7175A/ADV7176A accepts horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of
an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically blanks
all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL).
DISPLAY DISPLAY
VERTICAL BLANK
522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22
HSYNC
BLANK
VSYNC EVEN FIELD ODD FIELD
DISPLAY DISPLAY
VERTICAL BLANK
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285
HSYNC
BLANK
VSYNC EVEN FIELD

ODD FIELD
–18– REV. C
ADV7175A/ADV7176A
DISPLAY DISPLAY
VERTICAL BLANK
622 623 624 625 1 2 3 4 5 6 7 21 22 23
HSYNC
BLANK
VSYNC EVEN FIELD ODD FIELD
DISPLAY DISPLAY
VERTICAL BLANK
309 310 311 312 313 314 315 316 317 318 319 320 334 335 336
HSYNC
BLANK
VSYNC ODD FIELD EVEN FIELD

Mode 2: Master Option HSYNC, VSYNC, BLANK
In this mode, the ADV7175A/ADV7176A can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of
an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically blanks
all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). Figure 23 illus-
trates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 24 illustrates the
HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data.
HSYNC
VSYNC
PAL = 12 * CLOCK/2
BLANK NTSC = 16 * CLOCK/2
PIXEL Cb Y Cr Y
DATA
PAL = 132 * CLOCK/2
Figure 23. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
HSYNC
VSYNC
PAL = 864 * CLOCK/2
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
BLANK
PIXEL Cb Y Cr Y Cb
DATA
PAL = 132 * CLOCK/2

Figure 24. Timing Mode 2 Odd-to-Even Field Transition Master/Slave

REV. C –19–
ADV7175A/ADV7176A
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7175A/ADV7176A accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the
FIELD input when HSYNC is high indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK
input is disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in
Figure 25 (NTSC) and Figure 26 (PAL).
DISPLAY DISPLAY
VERTICAL BLANK
522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22
HSYNC
BLANK
DISPLAY DISPLAY
VERTICAL BLANK
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285
HSYNC
BLANK
DISPLAY DISPLAY
VERTICAL BLANK
622 623 624 625 1 2 3 4 5 6 7 21 22 23
HSYNC
BLANK
DISPLAY DISPLAY
VERTICAL BLANK
309 310 311 312 313 314 315 316 317 318 319 320 334 335 336
HSYNC
BLANK
–20– REV. C
ADV7175A/ADV7176A
POWER-ON RESET 1 1 0 1 0 1 A1 X
After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high-to-low transition on ADDRESS
CONTROL
the RESET pin. This initializes the pixel port so that the SET UP BY
pixel inputs, P7–P0 are selected. After reset, the ADV7175A/ ALSB
ADV7176A is automatically set up to operate in NTSC mode. READ/WRITE
Subcarrier frequency code 21F07C16HEX is loaded into the CONTROL
subcarrier frequency registers. All other registers, with the 0 WRITE

1 READ
exception of Mode Register 0, are set to 00H. All bits in Mode
Register 0 are set to Logic Level “0” except Bit MR02. Bit Figure 27. ADV7175A Slave Address
MR02 of Mode Register 0 is set to Logic “1.” This enables the
7.5 IRE pedestal.
0 1 0 1 0 1 A1 X
SCH Phase Mode
The SCH phase is configured in default mode to reset every ADDRESS
CONTROL
four (NTSC) or eight (PAL) fields to avoid an accumulation of SET UP BY
SCH phase error over time. In an ideal system, zero SCH phase ALSB
error would be maintained forever, but in reality, this is impos- READ/WRITE

CONTROL
sible to achieve due to clock frequency variations. This effect is
0 WRITE
reduced by the use of a 32-bit DDS, which generates this SCH. 1 READ
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor Figure 28. ADV7176A Slave Address
SCH phase jumps at the start of the four or eight field sequence. To control the various devices on the bus, the following proto-
Resetting the SCH phase should not be done if the video source col must be followed: First, the master initiates a data transfer by
does not have stable timing or the ADV7175A/ADV7176A is establishing a start condition, defined by a high-to-low transition
configured in RTC mode (MR21 = 1 and MR22 = 1). Under on SDATA while SCLOCK remains high. This indicates that
these conditions (unstable video) the subcarrier phase reset an address/data stream will follow. All peripherals respond to
should be enabled MR22 = 0 and MR21 = 1) but no reset the start condition and shift the next eight bits (7-bit address +
applied. In this configuration the SCH phase will never be reset, R/W bit). The bits transfer from MSB down to LSB. The
which means that the output video will now track the unstable peripheral that recognizes the transmitted address responds by
input video. The subcarrier phase reset, when applied, will reset pulling the data line low during the ninth clock pulse. This is
the SCH phase to Field 0 at the start of the next field (e.g., known as an acknowledge bit. All other devices withdraw from
subcarrier phase reset applied in Field 5 [PAL] on the start of the bus at this point and maintain an idle condition. The idle
the next field SCH phase will be reset to Field 0). condition is where the device monitors the SDATA and SCLOCK
lines waiting for the start condition and the correct transmitted
MPU PORT DESCRIPTION address. The R/W bit determines the direction of the data. A
The ADV7175A and ADV7176A support a two-wire serial (I2C Logic “0” on the LSB of the first byte means that the master
Compatible) microprocessor bus driving multiple peripherals. will write information to the peripheral. A Logic “1” on the LSB
Two inputs, serial data (SDATA) and serial clock (SCLOCK), of the first byte means that the master will read information
carry information between any device connected to the bus. Each from the peripheral.
slave device is recognized by a unique address. The ADV7175A The ADV7175A/ADV7176A acts as a standard slave device on
and ADV7176A each have four possible slave addresses for both the bus. The data on the SDATA pin is 8 bits long, supporting
read and write operations. These are unique addresses for each the 7-bit addresses, plus the R/W bit. The ADV7175A has 37
device and are illustrated in Figure 27 and Figure 28. The LSB subaddresses and the ADV7176A has 20 subaddresses to enable
sets either a read or write operation. Logic Level “1” corre- access to the internal registers. It therefore interprets the first
sponds to a read operation, while Logic Level “0” corresponds byte as the device address and the second byte as the starting
to a write operation. A1 is set by setting the ALSB pin of the subaddress. The subaddresses auto increment allow data to
ADV7175A/ADV7176A to Logic Level “0” or Logic Level “1.” be written to or read from the starting subaddress. A data
transfer is always terminated by a stop condition. The user can
REV. C –21–
ADV7175A/ADV7176A
also access any unique subaddress register on a one by one basis 1. In Read Mode, the highest subaddress register contents
without having to update all the registers. There is one excep- will continue to be output until the master device issues a
tion. The subcarrier frequency registers should be updated in no-acknowledge. This indicates the end of a read. A no-
sequence, starting with Subcarrier Frequency Register 0. The acknowledge condition is where the SDATA line is not pulled
auto increment function should then be used to increment and low on the ninth pulse.
access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier
2. In Write Mode, the data for the invalid byte will not be
frequency registers should not be accessed independently.
loaded into any subaddress register, a no-acknowledge will
Stop and start conditions can be detected at any stage during be issued by the ADV7175A/ADV7176A and the part will
the data transfer. If these conditions are asserted out of sequence return to the idle condition.
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high
SDATA
period, the user should issue only one start condition, one
stop condition or a single stop condition followed by a single
start condition. If an invalid subaddress is issued by the user, SCLOCK S 1-7 8 9 1-7 8 9 1-7 8 9 P
the ADV7175A/ADV7176A will not issue an acknowledge and START ADDR R/W ACK SUBADDRESS ACK DATA ACK STOP
will return to the idle condition. If, in auto-increment mode
Figure 29. Bus Data Transfer
the user exceeds the highest subaddress, the following action
will be taken: Figure 29 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 30 shows bus write and read sequences.
WRITE S SLAVE ADDR A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P
SEQUENCE
LSB = 1
LSB = 0
READ S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA A(M) DATA A(M) P
SEQUENCE
S = START BIT A(S) = ACKNOWLEDGE BY SLAVE A(S) = NO-ACKNOWLEDGE BY SLAVE
P = STOP BIT A(M) = ACKNOWLEDGE BY MASTER A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 30. Write and Read Sequences
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
SR7–SR6 (00)
ZERO SHOULD BE WRITTEN

TO THESE BITS
ADV7175A SUBADDRESS REGISTER ADV7176A SUBADDRESS REGISTER

SR5 SR4 SR3 SR2 SR1 SR0 SR5 SR4 SR3 SR2 SR1 SR0
0 0 0 0 0 0 MODE REGISTER 0 0 0 0 0 0 0 MODE REGISTER 0
0 0 0 0 1 0 SUB CARRIER FREQ REGISTER 0 0 0 0 0 1 0 SUB CARRIER FREQ REGISTER 0
0 0 0 1 1 0 SUB CARRIER PHASE REGISTER 0 0 0 1 1 0 SUB CARRIER PHASE REGISTER
0 0 0 1 1 1 TIMING REGISTER 0 0 0 0 1 1 1 TIMING REGISTER 0
0 0 1 0 0 0 CLOSED CAPTIONING EXTENDED DATA ⬇ BYTE 0 0 0 1 0 0 0 CLOSED CAPTIONING EXTENDED DATA ⬇ BYTE 0
0 0 1 0 0 1 CLOSED CAPTIONING EXTENDED DATA ⬇ BYTE 1 0 0 1 0 0 1 CLOSED CAPTIONING EXTENDED DATA ⬇ BYTE 1
0 0 1 0 1 0 CLOSED CAPTIONING DATA ⬇ BYTE 0 0 0 1 0 1 0 CLOSED CAPTIONING DATA ⬇ BYTE 0
0 0 1 0 1 1 CLOSED CAPTIONING DATA ⬇ BYTE 1 0 0 1 0 1 1 CLOSED CAPTIONING DATA ⬇ BYTE 1
0 0 1 1 0 0 TIMING REGISTER 1 0 0 1 1 0 0 TIMING REGISTER 1
0 0 1 1 1 0 NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)/TTX SETUP REG 0* 0 0 1 1 1 0 NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)/TTX SETUP REG 0*
0 1 0 0 1 1 MACROVISION REGISTER 1 0 0 1 0 0 TTXREQ CONTROL REGISTER
• • • • • • " "
• • • • • • " " *TTX REGISTERS ARE AVAILABLE IN PAL MODE ONLY
IN NTSC MODE THESE REGISTERS CONTROL PEDESTAL
1 0 0 0 1 1 MACROVISION REGISTER
1 0 0 1 0 0 TTXREQ CONTROL REGISTER
*TTX REGISTERS ARE AVAILABLE IN PAL MODE ONLY

IN NTSC MODE THESE REGISTERS CONTROL PEDESTAL
Figure 31. Subaddress Register
–22– REV. C
ADV7175A/ADV7176A
REGISTER ACCESSES MODE REGISTER 0 MR0 (MR07–MR00)
The MPU can write to or read from all of the ADV7175A/ (Address [SR4–SR0] = 00H)
ADV7176A registers except the subaddress register, which is a Figure 32 shows the various operations under the control of Mode
write-only register. The subaddress register determines which Register 0. This register can be read from as well as written to.
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the MR0 BIT DESCRIPTION
subaddress register. A read/write operation is performed from/to Output Video Standard Selection (MR01–MR00)
the target address, which then increments to the next address These bits are used to set up the encode mode. The ADV7175A/
until a stop command on the bus is performed. ADV7176A can be set up to output NTSC, PAL (B, D, G, H, I)
and PAL (M) standard video.
REGISTER PROGRAMMING Pedestal Control (MR02)
The following section describes each register, including subaddress This bit specifies whether a pedestal is to be generated on
register, mode registers, subcarrier frequency registers, subcarrier the NTSC composite video signal. This bit is invalid if the
phase register, timing registers, closed captioning extended data ADV7175A/ADV7176A is configured in PAL mode.
registers, closed captioning data registers and NTSC pedestal
control registers in terms of its configuration. Luminance Filter Control (MR04–MR03)
The luminance filters are divided into two sets (NTSC/PAL) of
Subaddress Register (SR7–SR0) four filters, low-pass A, low-pass B, notch and extended. When
The communications register is an 8-bit write-only register. PAL is selected, bits MR03 and MR04 select one of four PAL
After the part has been accessed over the bus, and a read/write luminance filters; likewise, when NTSC is selected, bits MR03
operation is selected, the subaddress is set up. The subaddress and MR04 select one of four NTSC luminance filters. The fil-
register determines to/from which register the operation takes ters are illustrated in Figures 4 to 12.
place.
RGB Sync (MR05)
Figure 31 shows the various operations under the control of This bit is used to set up the RGB outputs with the sync infor-
the subaddress register. Zero should always be written to mation encoded on all RGB outputs. (This funcionality is only
SR7–SR6. available on the ADV7176A.)
Register Select (SR5–SR0) Output Select (MR06)
These bits are set up to point to the required starting address. This bit specifies if the part is in composite video or RGB/YUV
mode. Please note that the main composite signal is still avail-
able in RGB/YUV mode.
MR07 MR06 MR05 MR04 MR03 MR02 MR01 MR00
OUTPUT SELECT LUMINANCE FILTER CONTROL OUTPUT VIDEO

STANDARD SELECTION
MR06 MR04 MR03
0 YC OUTPUT MR01 MR00
0 0 LOW PASS FILTER (A)
1 RGB/YUV OUTPUT 0 1 NOTCH FILTER 0 0 NTSC
1 0 EXTENDED MODE 0 1 PAL (B, D, G, H, I)
1 1 LOW PASS FILTER (B) 1 0 PAL (M)
1 1 RESERVED
MR07 RGB SYNC PEDESTAL

(0) CONTROL
MR05
MR02
ZERO SHOULD 0 DISABLE
BE WRITTEN TO 1 ENABLE 0 PEDESTAL OFF
THIS BIT 1 PEDESTAL ON
Figure 32. Mode Register 0 (MR0)
DAC A DAC D CLOSED CAPTIONING

CONTROL CONTROL FIELD SELECTION
MR16 MR14 MR12 MR11
0 NORMAL 0 NORMAL 0 0 NO DATA OUT
1 POWER-DOWN 1 POWER-DOWN 0 1 ODD FIELD ONLY
1 0 EVEN FIELD ONLY
1 1 DATA OUT
(BOTH FIELDS)
COLOR BAR DAC B DAC C INTERLACED MODE

CONTROL CONTROL CONTROL CONTROL
MR17 MR15 MR13 MR10
0 DISABLE 0 NORMAL 0 NORMAL 0 INTERLACED
1 ENABLE 1 POWER-DOWN 1 POWER-DOWN 1 NONINTERLACED
Figure 33. Mode Register 1 (MR1)
REV. C –23–
ADV7175A/ADV7176A
MODE REGISTER 1 MR1 (MR17–MR10) SUBCARRIER
FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
FREQUENCY FSC31
(Address (SR4–SR0) = 01H) REG 3
Figure 33 shows the various operations under the control of Mode SUBCARRIER
FREQUENCY FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
Register 1. This register can be read from as well as written to. REG 2
SUBCARRIER
FREQUENCY FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8
MR1 BIT DESCRIPTION REG 1
Interlaced Mode Control (MR10) SUBCARRIER
This bit is used to set up the output to interlaced or noninter- FREQUENCY FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0
REG 0
laced mode. This mode is only relevant when the part is in
composite video mode. Figure 34. Subcarrier Frequency Register
Closed Captioning Field Selection (MR12–MR11)
SUBCARRIER PHASE REGISTER (FP7–FP0)
These bits control the fields on which closed captioning data is
(Address [SR4–SR0] = 06H)
displayed; closed captioning information can be displayed on an
This 8-bit-wide register is used to set up the subcarrier phase.
odd field, even field or both fields.
Each bit represents 1.41°.
DAC Control (MR16–MR13)
These bits can be used to power down the DACs. This can TIMING REGISTER 0 (TR07–TR00)
be used to reduce the power consumption of the ADV7175A/ (Address [SR4–SR0] = 07H)
ADV7176A if any of the DACs are not required in the application. Figure 35 shows the various operations under the control of
Color Bar Control (MR17) Timing Register 0. This register can be read from as well as
This bit can be used to generate and output an internal color written to. This register can be used to adjust the width and
bar test pattern. The color bar configuration is 100/7.5/75/7.5 position of the master mode timing signals.
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7175A/ADV7176A is TR0 BIT DESCRIPTION
configured in a master timing mode as per the one selected by Master/Slave Control (TR00)
bits TR01 and TR02. This bit controls whether the ADV7175A/ADV7176A is in
master or slave mode.
SUBCARRIER FREQUENCY REGISTER 3-0
(FSC3–FSC0) Timing Mode Selection (TR02–TR01)
(Address [SR4–SR0] = 05H–02H) These bits control the timing mode of the ADV7175A/
These 8-bit-wide registers are used to set up the subcarrier ADV7176A. These modes are described in the Timing and
frequency. The value of these registers are calculated by using Control section of the data sheet.
the following equation: BLANK Input Control (TR03)
This bit controls whether the BLANK input is used when the
232 –1
Subcarrier Frequency Register = × FSCF part is in slave mode.
FCLK
Luma Delay (TR05–TR04)
i.e.: NTSC Mode, These bits control the addition of a luminance delay. Each bit
FCLK = 27 MHz, represents a delay of 74 ns.
FSCF = 3.5795454 MHz Pixel Port Control (TR06)
232 –1 This bit is used to set the pixel port to accept 8-bit or 16-bit
Subcarrier Frequency Value = × 3.5795454 ×106 data. If an 8-bit input is selected the data will be set up on Pins
27 ×106
P7–P0.
= 21F07C16 HEX
Timing Register Reset (TR07)
Figure 34 shows how the frequency is set up by the four registers. Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset or changing to a new timing mode.
TR07 TR06 TR05 TR04 TR03 TR02 TR01 TR00
TIMING BLANK INPUT MASTER/SLAVE

REGISTER RESET CONTROL CONTROL
TR03 TR00
TR07
0 ENABLE 0 SLAVE TIMING
1 DISABLE 1 MASTER TIMING
PIXEL PORT LUMA DELAY TIMING MODE

CONTROL SELECTION
TR05 TR04
TR06 TR02 TR01
0 0 0ns DELAY
0 8-BIT 0 1 74ns DELAY 0 0 MODE 0
1 16-BIT 1 0 148ns DELAY 0 1 MODE 1
1 1 222ns DELAY 1 0 MODE 2
1 1 MODE 3
Figure 35. Timing Register 0
–24– REV. C
ADV7175A/ADV7176A
CLOSED CAPTIONING EVEN FIELD TR1 BIT DESCRIPTION
DATA REGISTER 1–0 (CED15–CED0) HSYNC Width (TR11–TR10)
(Address [SR4–SR0] = 09–08H) These bits adjust the HSYNC pulsewidth.
These 8-bit-wide registers are used to set up the closed captioning HSYNC to FIELD/VSYNC Delay (TR13–TR12)
extended data bytes on even fields. Figure 36 shows how the These bits adjust the position of the HSYNC output relative to
high and low bytes are set up in the registers. the FIELD/VSYNC output.
HSYNC to FIELD Rising Edge Delay (TR15–TR14)
BYTE 1 CED15 CED14 CED13 CED12 CED11 CED10 CED9 CED8
When the ADV7175A/ADV7176A is in Timing Mode 1, these
bits adjust the position of the HSYNC output relative to the
BYTE 0 CED7 CED6 CED5 CED4 CED3 CED2 CED1 CED0
FIELD output rising edge.
Figure 36. Closed Captioning Extended Data Register VSYNC Width (TR15–TR14)
When the ADV7175A/ADV7176A is in Timing Mode 2, these
CLOSED CAPTIONING ODD FIELD bits adjust the VSYNC pulsewidth.
DATA REGISTER 1–0 (CCD15–CCD0)
HSYNC to Pixel Data Adjust (TR17–TR16)
(Subaddress [SR4–SR0] = 0B–0AH)
This enables the HSYNC to be adjusted with respect to the
These 8-bit-wide registers are used to set up the closed captioning
pixel data. This allows the Cr and Cb components to be
data bytes on odd fields. Figure 37 shows how the high and low
swapped. This adjustment is available in both master and slave
bytes are set up in the registers.
timing modes.
BYTE 1 CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8 MODE REGISTER 2 MR2 (MR27–MR20)
(Address [SR4–SR0] = 0DH)
BYTE 0 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0 Mode Register 2 is an 8-bit-wide register.
Figure 37. Closed Captioning Data Register Figure 39 shows the various operations under the control of Mode
Register 2. This register can be read from as well as written to.
TIMING REGISTER 1 (TR17–TR10)
(ADDRESS [SR4–SR0] = 0CH) MR2 BIT DESCRIPTION
Timing Register 1 is an 8-Bit-Wide Register Square Pixel Control (MR20)
This bit is used to set up square pixel mode. This is available in
Figure 38 shows the various operations under the control of
slave mode only. For NTSC, a 24.5454 MHz clock must be
Timing Register 1. This register can be read from as well as
supplied. For PAL, a 29.5 MHz clock must be supplied.
written to. This register can be used to adjust the width and
position of the master mode timing signals.
TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10
HSYNC TO PIXEL HSYNC TO FIELD HSYNC TO HSYNC WIDTH

DATA ADJUST RISING EDGE DELAY FIELD/VSYNC DELAY TR11 TR10 TA
(MODE 1 ONLY)
TR17 TR16 TR13 TR12 TB 0 0 1 x TPCLK
TR15 TR14 TC 0 1 4 x TPCLK
0 0 0 x TPCLK 0 0 0 x TPCLK
0 1 1 x TPCLK x 0 TB 0 1 4 x TPCLK 1 0 16 x TPCLK
1 0 2 x TPCLK x 1 TB + 32␮s 1 0 8 x TPCLK 1 1 128 x TPCLK
1 1 3 x TPCLK 1 1 16 x TPCLK
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0 0 1 x TPCLK
0 1 4 x TPCLK
1 0 16 x TPCLK
1 1 128 x TPCLK
TIMING MODE 1 (MASTER/PAL)

LINE 1 LINE 313 LINE 314
HSYNC TA
TB TC
FIELD/VSYNC
Figure 38. Timing Register 1
REV. C –25–
ADV7175A/ADV7176A
RGB/YUV CHROMINANCE GENLOCK SELECTION

CONTROL CONTROL
MR22 MR21
MR26 MR24
x 0 DISABLE GENLOCK
0 RGB OUTPUT 0 ENABLE COLOR
0 1 ENABLE SUBCARRIER
1 YUV OUTPUT 1 DISABLE COLOR
RESET PIN
1 1 ENABLE RTC PIN
LOWER POWER BURST ACTIVE VIDEO LINE WIDTH SQUARE PIXEL

MODE CONTROL CONTROL CONTROL
MR27 MR25 MR23 MR20
0 DISABLE 0 ENABLE BURST 0 720 PIXELS 0 DISABLE
1 ENABLE 1 DISABLE BURST 1 710/702 PIXELS 1 ENABLE
Figure 39. Mode Register 2
Genlock Selection (MR22–MR21) LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
These bits control the genlock feature of the ADV7175A/ FIELD 1/3 PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 PCO0
ADV7176A. Setting MR21 to a Logic “1” configures the LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
SCRESET/RTC pin as an input. Setting MR22 to Logic Level
FIELD 1/3 PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8
“0” configures the SCRESET/RTC pin as a subcarrier reset
input, therefore, the subcarrier will reset to Field 0, following a
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
low-to-high transition on the SCRESET/RTC pin. Setting
FIELD 2/4 PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0
MR22 to Logic Level “1” configures the SCRESET/RTC pin as
a real-time control input. LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
Active Video Line Width Control (MR23) FIELD 2/4 PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8
This bit switches between two active video line durations. A

zero selects CCIR.REC601 (720 pixels PAL/NTSC) and a one Figure 40. Pedestal Control Registers
selects ITU-R.BT.470 “analog” standard for active video dura-
tion (710 pixels NTSC 702 pixels PAL).
FIELD 1/3 TXO7 TXO6 TXO5 TXO4 TXO3 TXO2 TXO1 TXO0
Chrominance Control (MR24)
This bit enables the color information to be switched on and off LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
the video output. FIELD 1/3 TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9 TXO8
Burst Control (MR25)

This bit enables the burst information to be switched on and off
FIELD 2/4 TXE7 TXE6 TXE5 TXE4 TXE3 TXE2 TXE1 TXE0
the video output.
RGB/YUV Control (MR26)
FIELD 2/4 TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 TXE9 TXE8
This bit enables the output from the RGB DACs to be set to
YUV output video standard. Bit MR06 of Mode Register 0
must be set to Logic Level “1” before MR26 is set. Figure 41. Teletext Control Registers
Lower Power Mode (MR27) MODE REGISTER 3 MR3 (MR37–MR30)
This bit enables the lower power mode of the ADV7175A/ (Address [SR4–SR0] = 12H)
ADV7176A. This will reduce the DAC current by 50%. Mode Register 3 is an 8-bit-wide register.
Figure 42 shows the various operations under the control of
NTSC PEDESTAL/PAL TELETEXT CONTROL Mode Register 3.
REGISTERS 3–0 (PCE15–0, PCO15–0)/ (TXE15–0, TXO15–0)
(Subaddress [SR4–SR0] = 11–0EH) MR3 BIT DESCRIPTION
These 8-bit-wide registers are used to set up the NTSC pedes- Revision Code (MR30)
tal/PAL teletext on a line-by-line basis in the vertical blanking This bit is read only and indicates the revision of the device.
interval for both odd and even fields. Figures 40 and 41 show
the four control registers. A Logic “1” in any of the bits of these VBI Pass-Through (MR31)
registers has the effect of turning the pedestal OFF on the This bit determines whether or not data in the vertical blanking
equivalent line when used in NTSC. A Logic “1” in any of the interval (VBI) is output to the analog outputs or blanked. VBI
bits of these registers has the effect of turning teletext ON the Pass-Through is available in all timing modes except Slave 0.
equivalent line when used in PAL. Also when both VBI Pass-Through and BLANK input control
(TR03) are enabled, TR03 takes priority.
Reserved (MR33–MR32)
These bits are reserved.
Teletext Enable (MR34)
This bit must be set to “1” to enable teletext data insertion on
the TTX pin.
–26– REV. C
ADV7175A/ADV7176A
Input Default Color (MR36) DAC Output Switching (MR37)
This bit determines the default output color from the DACs for This bit is used to switch the DAC outputs from SCART to a
zero input data (or disconnected). A Logical “0” means that the EUROSCART configuration. A complete table of all DAC
color corresponding to 00000000 will be displayed. A Logical “1” output configurations is shown below.
forces the output color to black for 00000000 input video data.
Table I. DAC Output Configuration Matrix
MR06 MR26 MR37 DAC A DAC B DAC C DAC D Simultaneous Output

0 0 0 CVBS CVBS C Y 2 Composite and Y/C
0 0 1 Y CVBS C CVBS 2 Composite and Y/C
0 1 0 CVBS CVBS C Y 2 Composite and Y/C
0 1 1 Y CVBS C CVBS 2 Composite and Y/C
1 0 0 CVBS B R G RGB and Composite
1 0 1 G B R CVBS RGB and Composite
1 1 0 CVBS U V Y YUV and Composite
1 1 1 Y U V CVBS YUV and Composite
CVBS: Composite Video Baseband Signal NOTE
Y: Luminance Component Signal (For YUV or Y/C Mode) Each DAC can be individually powered ON or OFF with the following control bits
C: Chrominance Signal (For Y/C Mode) (“0” = ON, “1” = OFF):
U: Chrominance Component Signal (For YUV Mode) MR13 - DAC C
V: Chrominance Component Signal (For YUV Mode) MR14 - DAC D
R: RED Component Video (For RGB Mode) MR15 - DAC B
G: GREEN Component Video (For RGB Mode) MR16 - DAC A
B: BLUE Component Video (For RGB Mode)
RESERVED
MR35 = 0 MR30
ZERO SHOULD REV CODE

BE WRITTEN TO (READ ONLY)
THIS BIT
INPUT DEFAULT COLOR TELETEXT ENABLE VBI PASSTHROUGH

MR36 MR34 MR31
0 INPUT COLOR 0 DISABLE 0 DISABLE
1 BLACK 1 ENABLE 1 ENABLE
DAC OUTPUT
SWITCHING
MR37 DAC A DAC B DAC C DAC D
0 COMPOSITE BLUE/COMP/U RED/CHROMA/V GREEN/LUMA/Y
1 GREEN/LUMA/Y BLUE/COMP/U RED/CHROMA/V COMPOSITE
Figure 42. Mode Register 3

TTXREQ CONTROL REGISTER TC07 (TC07–TC00) TTXREQ Falling Edge Control (TC03–TC00)
(Address [SR4–SR0] = 24H) These bits control the position of the falling edge of TTXREQ.
Teletext Control Register is an 8-bit-wide register. It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles. This controls the active window for teletext
TTXREQ Rising Edge Control (TC07–TC04)
data. Increasing this value reduces the amount of teletext bits
These bits control the position of the rising edge of TTXREQ.
below the default of 360. If bits TC03–TC00 are unchanged
It can be programmed from zero CLOCK cycles to a max of 15
when bits TC07–TC04 are changed, the falling edge of TTXREQ
CLOCK cycles—see Figure 48.
will track that of the rising edge (i.e., the time between the fall-
ing and rising edge remains constant)—see Figure 48.
TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00
TTXREQ RISING EDGE CONTROL TTXREQ FALLING EDGE CONTROL

TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00
0 0 0 0 0 PCLK 0 0 0 0 0 PCLK
0 0 0 1 1 PCLK 0 0 0 1 1 PCLK
" " " " " PCLK " " " " " PCLK
1 1 1 0 14 PCLK 1 1 1 0 14 PCLK
1 1 1 1 15 PCLK 1 1 1 1 15 PCLK
Figure 43. Teletext Control Register

REV. C –27–
ADV7175A/ADV7176A
APPENDIX 1
BOARD DESIGN AND LAYOUT CONSIDERATIONS
The ADV7175A/ADV7176A is a highly integrated circuit contain- to reduce the lead inductance. Best performance is obtained
ing both precision analog and high speed digital circuitry. It has with 0.1 µF ceramic capacitor decoupling. Each group of VAA
been designed to minimize interference effects on the integrity pins on the ADV7175A/ADV7176A must have at least one 0.1 µF
of the analog circuitry by the high speed digital circuitry. It is decoupling capacitor to GND. These capacitors should be
imperative that these same design and layout techniques be placed as close to the device as possible.
applied to the system level design so that high speed, accurate It is important to note that while the ADV7175A/ADV7176A
performance is achieved. The “Recommended Analog Circuit contains circuitry to reject power supply noise, this rejection
Layout” shows the analog interface between the device and decreases with frequency. If a high frequency switching power
monitor. supply is used, the designer should pay close attention to reduc-
The layout should be optimized for lowest noise on the ADV7175A/ ing power supply noise and consider using a three terminal voltage
ADV7176A power and ground lines by shielding the digital regulator for supplying power to the analog power plane.
inputs and providing good decoupling. The lead length between Digital Signal Interconnect
groups of VAA and GND pins should by minimized to minimize The digital inputs to the ADV7175A/ADV7176A should be
inductive ringing. isolated as much as possible from the analog outputs and other
Ground Planes analog circuitry. Also, these input signals should not overlay the
The ground plane should encompass all ADV7175A/ADV7176A analog power plane.
ground pins, voltage reference circuitry, power supply bypass Due to the high clock rates involved, long clock lines to
circuitry for the ADV7175A/ADV7176A, the analog out- the ADV7175A/ADV7176A should be avoided to reduce
put traces, and all the digital signal traces leading up to the noise pickup.
ADV7175A/ADV7176A. The ground plane is the board’s
common ground plane. Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC) and not the
Power Planes
analog power plane.
The ADV7175A/ADV7176A and any associated analog circuitry
should have its own power plane, referred to as the analog Analog Signal Interconnect
power plane (VAA). This power plane should be connected to The ADV7175A/ADV7176A should be located as close to the
the regular PCB power plane (VCC) at a single point through a output connectors as possible to minimize noise pickup and
ferrite bead. This bead should be located within three inches of reflections due to impedance mismatch.
the ADV7175A/ADV7176A. The video output signals should overlay the ground plane, not
The metallization gap separating device power plane and the analog power plane, to maximize the high frequency power
board power plane should be as narrow as possible to mini- supply rejection.
mize the obstruction to the flow of heat from the device into Digital inputs, especially pixel data inputs and clocking signals,
the general board. should never overlay any of the analog signal circuitry and
The PCB power plane should provide power to all digital logic should be kept as far away as possible.
on the PC board, and the analog power plane should provide For best performance, the outputs should each have a 75 Ω
power to all ADV7175A/ADV7176A power pins and voltage load resistor connected to GND. These resistors should be
reference circuitry. placed as close as possible to the ADV7175A/ADV7176A as to
Plane-to-plane noise coupling can be reduced by ensuring that minimize reflections.
portions of the regular PCB power and ground planes do not The ADV7175A/ADV7176A should have no inputs left float-
overlay portions of the analog power plane unless they can be ing. Any inputs that are not required should be tied to ground.
arranged so that the plane-to-plane noise is common-mode.
Supply Decoupling
For optimum performance, bypass capacitors should be installed
using the shortest leads possible, consistent with reliable operation,
–28– REV. C
ADV7175A/ADV7176A
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
0.1␮F 0.01␮F
L1
5V (VAA) (FERRITE BEAD)
5V (VAA) 5V (VAA) 5V
1, 11, 20, 28, 30 10␮F 33␮F (VCC)
0.1␮F 0.1␮F GND
VAA
25 COMP
33 VREF DAC D 27
ADV7175A 75⍀
38–42,
2–9, 12–14 ADV7176A
5V (VAA) P15–P0 DAC C 26
S VIDEO
75⍀
4k⍀
RESET 35 SCRESET/RTC DAC B 31

100nF 75⍀
“UNUSED 15 HSYNC
INPUTS
SHOULD BE 16 FIELD/VSYNC
5V (VCC) GROUNDED” DAC A 32 5V (VCC) 5V (VCC)
17 BLANK
75⍀
100k⍀ 22 RESET 5k⍀ 5k⍀
TTX 100⍀
37 TTX SCLOCK 23
TTX REQ MPU BUS
36 TTX REQ 100⍀
SDATA 24
100k⍀ 44 CLOCK
RSET 34
5V (VAA) ALSB GND 150⍀
TELETEXT PULL-UP AND 10k⍀ 18
PULL-DOWN RESISTORS 10, 19, 21
29, 43
SHOULD ONLY BE USED
IF THESE PINS ARE NOT
CONNECTED
27MHz CLOCK
(SAME CLOCK AS USED BY
MPEG2 DECODER)
Figure 44. Recommended Analog Circuit Layout

The circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform
is guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if
the 13.5 MHz clock is required by the MPEG decoder. This will guarantee that the Cr and Cb pixel information is input to the
ADV7175A/ADV7176A in the correct sequence.
D Q
D Q 13.5MHz
CLOCK CK
CK
HSYNC
Figure 45. Circuit to Generate 13.5 MHz
REV. C –29–
ADV7175A/ADV7176A
APPENDIX 2
CLOSED CAPTIONING
The ADV7175A/ADV7176A supports closed captioning, conforming to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284
of even fields.
Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run-in
signal, the blanking level is held for two data bits and is followed by a Logic Level “1” start bit. 16 bits of data follow the start bit.
These consist of two 8-bit bytes, seven data bits and one odd parity bit. The data for these bytes is stored in closed captioning Data
Registers 0 and 1.
The ADV7175A/ADV7176A also supports the extended closed captioning operation, which is active during even fields, and is
encoded on scan Line 284. The data for this operation is stored in closed captioning extended Data Registers 0 and 1.
All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7175A/
ADV7176A. All pixels inputs are ignored during Lines 21 and 284.
FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Lines
21 and 284.
The ADV7175A/ADV7176A uses a single buffering method. This means that the closed captioning buffer is only one byte deep,
therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. The data
must be loaded at least one line before (Line 20 or Line 283) it is outputted on Line 21 and Line 284. A typical implementation of
this method is to use VSYNC to interrupt a microprocessor, which will in turn load the new data (two bytes) every field. If no new
data is required for transmission you must insert zeros in both the data registers; this is called NULLING. It is also important to load
“control codes,” all of which are double bytes on Line 21, or a TV will not recognize them. If you have a message like “Hello World”
which has an odd number of characters, it is important to pad it out to an even number to get “end of caption” 2-byte control code to
land in the same field.
10.5 ⴞ 0.25␮s 12.91␮s
7 CYCLES
OF 0.5035 MHz TWO 7-BIT + PARITY
(CLOCKRUN-IN) ASCII CHARACTERS
(DATA)
S P P
T A A
A D0–D6 R D0–D6 R
50 IRE
R I I
T T T
Y Y
BYTE 0 BYTE 1
40 IRE
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
10.003␮s
27.382␮s 33.764␮s
Figure 46. Closed Captioning Waveform (NTSC)
–30– REV. C
ADV7175A/ADV7176A
APPENDIX 3
TELETEXT INSERTION
Time TPD time needed by the ADV7175A/ADV7176A to interpolate input data on TTX and insert it onto the CVBS or Y outputs,
such that it appears TSYNTTXOUT = 10.2 µs after the leading edge of the horizontal signal. Time TTXDEL is the pipeline delay time by
the source that is gated by the TTXREQ signal in order to deliver TTX data.
With the programmability that is offered with TTXREQ signal on the Rising/Falling edges, the TTX data is always inserted at the
correct position of 10.2 µs after the leading edge of Horizontal Sync pulse, which enables a source interface with variable pipeline
delays.
The width of the TTXREQ signal must always be maintained so it allows the insertion of 360 (to comply with the Teletext Standard
“PAL–WST”) teletext bits at a text data rate of 6.9375 Mbits/s; this is achieved by setting TC03–TC00 to zero. The insertion
window is not open if the Teletext Enable bit (MR34) is set to zero.
Teletext Protocol
The relationship between the TTX bit clock (6.9375 MHz) and the system CLOCK (27 MHz) for 50 Hz is given as follows:
 27 MHz 
  = 6.75 MHz
 4 
 6.9375 × 106 
  = 1.027777
 6.75 × 106 
Thus 37 TTX bits correspond to 144 clocks (27 MHz) and each bit has a width of almost four clock cycles. The ADV7175A/ADV7176A
uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal
which can be outputted on the CVBS and Y outputs.
At the TTX input the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX bits
10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock
cycles are 47, 56, 65 and 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All
teletext lines are implemented in the same way. Individual control of teletext lines are controlled by Teletext Setup Registers.
45 BYTES (360 BITS) – PAL
TELETEXT VBI LINE ADDRESS & DATA
RUN-IN CLOCK
Figure 47. Teletext VBI Line
tSYNTTXOUT
CVBS/Y
tPD
HSYNC tPD
10.2␮s
TTXDATA
TTXDEL
TTXREQ
TTXST PROGRAMMABLE PULSE EDGES
tSYNTTXOUT = 10.2␮s
tPD = PIPELINE DELAY THROUGH ADV7175A/ADV7176A
TTXDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
Figure 48. Teletext Functionality Diagram

REV. C –31–
ADV7175A/ADV7176A
APPENDIX 4
NTSC WAVEFORMS (WITH PEDESTAL)
130.8 IRE PEAK COMPOSITE 1268.1mV
100 IRE REF WHITE 1048.4mV
714.2mV
7.5 IRE BLACK LEVEL 387.6mV
0 IRE BLANK LEVEL 334.2mV
–40 IRE SYNC LEVEL 48.3mV
Figure 49. NTSC Composite Video Levels
714.2mV

Figure 50. NTSC Luma Video Levels
963.8mV PEAK CHROMA
629.7mV (p-p)
286mV (p-p)
650mV BLANK/BLACK LEVEL
PEAK CHROMA
335.2mV
0mV
Figure 51. NTSC Chroma Video Levels
720.8mV

Figure 52. NTSC RGB Video Levels
–32– REV. C
ADV7175A/ADV7176A
NTSC WAVEFORMS (WITHOUT PEDESTAL)
130.8 IRE PEAK COMPOSITE 1289.8mV
714.2mV
0 IRE BLANK/BLACK LEVEL 338mV
Figure 53. NTSC Composite Video Levels
714.2mV
0 IRE BLANK/BLACK LEVEL 338mV
Figure 54. NTSC Luma Video Levels
978mV PEAK CHROMA
286mV (p-p) 694.9mV (p-p)

PEAK CHROMA
299.3mV
0mV
Figure 55. NTSC Chroma Video Levels
715.7mV
0 IRE BLANK/BLACK LEVEL 336.5mV
–40 IRE SYNC LEVEL 51mV
Figure 56. NTSC RGB Video Levels
REV. C –33–
ADV7175A/ADV7176A
PAL WAVEFORMS
1284.2mV PEAK COMPOSITE
1047.1mV REF WHITE
696.4mV
350.7mV BLANK/BLACK LEVEL
50.8mV SYNC LEVEL
Figure 57. PAL Composite Video Levels
1047mV REF WHITE
696.4mV
50.8mV SYNC LEVEL
Figure 58. PAL Luma Video Levels
989.7mV PEAK CHROMA
672mV (p-p)
307mV (p-p)
PEAK CHROMA
317.7mV
0mV
Figure 59. PAL Chroma Video Levels
1050.2mV REF WHITE
698.4mV
51mV SYNC LEVEL
Figure 60. PAL RGB Video Levels
–34– REV. C
ADV7175A/ADV7176A
UV WAVEFORMS
MAGENTA
MAGENTA
YELLOW
YELLOW
GREEN
BLACK
WHITE
GREEN
BLACK
CYAN
BLUE
WHITE
CYAN
BLUE
RED
RED
505mV
505mV
423mV
334mV
BETACAM LEVEL
171mV 82mV
BETACAM LEVEL 0mV 0mV
–82mV
0mV 0mV
ⴚ171mV
–423mV
ⴚ334mV
–505mV
ⴚ505mV
Figure 61. NTSC 100% Color Bars No Pedestal U Levels Figure 64. NTSC 100% Color Bars No Pedestal V Levels
MAGENTA
MAGENTA
YELLOW
YELLOW
GREEN
BLACK
WHITE
GREEN
BLACK
CYAN
BLUE
WHITE
CYAN
BLUE
RED
RED
467mV
467mV
391mV
309mV
BETACAM LEVEL
158mV 76mV
BETACAM LEVEL 0mV 0mV
–76mV
0mV 0mV
–158mV
–391mV
–309mV
–467mV
–467mV
Figure 65. NTSC 100% Color Bars with Pedestal V Levels
Figure 62. NTSC 100% Color Bars with Pedestal U Levels
MAGENTA
MAGENTA
YELLOW
YELLOW
GREEN
BLACK
WHITE
GREEN
BLACK
WHITE
CYAN
BLUE
CYAN
BLUE
RED
RED
350mV 350mV
293mV
232mV
SMPTE LEVEL
57mV
118mV
0mV 0mV
SMPTE LEVEL
–57mV
0mV 0mV
–118mV
–293mV
–232mV –350mV
–350mV
Figure 66. PAL 100% Color Bars V Levels
Figure 63. PAL 1005 Color Bars U Levels
REV. C –35–
ADV7175A/ADV7176A
APPENDIX 5
REGISTER VALUES
The ADV7175A/ADV7176A registers can be set depending on Address Data
the user standard required. 10Hex Pedestal Control Register 2 00Hex
The following examples give the various register formats for 11Hex Pedestal Control Register 3 00Hex
several video standards. 12Hex Mode Register 3 00Hex
24Hex Teletext Request Control Register 00Hex
In each case the output is set to composite o/p with all DACs
powered up and with the BLANK input control disabled. Addi- PAL M (FSC = 3.57561149 MHz)
tionally, the burst and color information are enabled on the Address Data
output and the internal color bar generator is switched off. In 00Hex Mode Register 0 06Hex
the examples shown, the timing mode is set to Mode 0 in slave 01Hex Mode Register 1 00Hex
format. TR02–TR00 of the Timing Register 0 control the 02Hex Subcarrier Frequency Register 0 A3Hex
timing modes. For a detailed explanation of each bit in the 03Hex Subcarrier Frequency Register 1 EFHex
command registers, please turn to the Register Programming 04Hex Subcarrier Frequency Register 2 E6Hex
section of the data sheet. TR07 should be toggled after setting 05Hex Subcarrier Frequency Register 3 21Hex
up a new timing mode. Timing Register 1 provides additional 06Hex Subcarrier Phase Register 00Hex
control over the position and duration of the timing signals. In 07Hex Timing Register 0 08Hex
the examples, this register is programmed in default mode. 08Hex Closed Captioning Ext Register 0 00Hex
09Hex Closed Captioning Ext Register 1 00Hex
NTSC (FSC = 3.5795454 MHz) 0AHex Closed Captioning Register 0 00Hex
Address Data 0BHex Closed Captioning Register 1 00Hex
00Hex Mode Register 0 04Hex 0CHex Timing Register 1 00Hex
01Hex Mode Register 1 00Hex 0DHex Mode Register 2 00Hex
02Hex Subcarrier Frequency Register 0 16Hex 0EHex Pedestal Control Register 0 00Hex
03Hex Subcarrier Frequency Register 1 7CHex 0FHex Pedestal Control Register 1 00Hex
04Hex Subcarrier Frequency Register 2 F0Hex 10Hex Pedestal Control Register 2 00Hex
05Hex Subcarrier Frequency Register 3 21Hex 11Hex Pedestal Control Register 3 00Hex
06Hex Subcarrier Phase Register 00Hex 12Hex Mode Register 3 00Hex
07Hex Timing Register 0 08Hex 24Hex Teletext Request Control Register 00Hex
0AHex Closed Captioning Register 0 00Hex
0BHex Closed Captioning Register 1 00Hex
0CHex Timing Register 1 00Hex
0DHex Mode Register 2 00Hex
0EHex Pedestal Control Register 0 00Hex
0FHex Pedestal Control Register 1 00Hex
10Hex Pedestal Control Register 2 00Hex
11Hex Pedestal Control Register 3 00Hex
12Hex Mode Register 3 00Hex
24Hex Teletext Request Control Register 00Hex
PAL B, D, G, H, I (FSC = 4.43361875 MHz)
Address
00Hex Mode Register 0 01 Hex
01Hex Mode Register 1 00 Hex
02Hex Subcarrier Frequency Register 0 CBHex
03Hex Subcarrier Frequency Register 1 8A Hex
04Hex Subcarrier Frequency Register 2 09 Hex
05Hex Subcarrier Frequency Register 3 2AHex
06Hex Subcarrier Phase Register 00 Hex
07Hex Timing Register 0 08 Hex
08Hex Closed Captioning Ext Register 0 00 Hex
09Hex Closed Captioning Ext Register 1 00 Hex
0AHex Closed Captioning Register 0 00 Hex
0BHex Closed Captioning Register 1 00 Hex
0CHex Timing Register 1 00 Hex
0DHex Mode Register 2 00 Hex
0EHex Pedestal Control Register 0 00 Hex
0FHex Pedestal Control Register 1 00 Hex
–36– REV. C
ADV7175A/ADV7176A
APPENDIX 6
OPTIONAL OUTPUT FILTER
If an output filter is required for the CVBS, Y, UV, Chroma and RGB outputs of the ADV7175A/ADV7176A, the following filter in
Figure 67 can be used. Plots of the filter characteristics are shown in Figures 68. An output filter is not required if the outputs of the
ADV7175A/ADV7176A are connected to an analog monitor or an analog TV; however, if the output signals are applied to a system
where sampling is used (e.g., digital TV), a filter is required to prevent aliasing.
L L L
1␮H 2.7␮H 0.68␮H 0
IN OUT
C C C
R 470pF 330pF 56pF R
75⍀ 75⍀ –16.7
–33.3
MAGNITUDE – dB
Figure 67. Output Filter
–50
–66.7
–83.3
–100
100k 1M 10M 100M
FREQUENCY – Hz
Figure 68. Output Filter Plot
REV. C –37–
ADV7175A/ADV7176A
APPENDIX 7
OPTIONAL DAC BUFFERING
For external buffering of the ADV7175A/ADV7176A DAC outputs, the configuration in Figure 69 is recommended. This configu-
ration shows the DAC outputs running at half (18 mA) their full current (36 mA) capability. This will allow the ADV7175A/ADV7176A
to dissipate less power, the analog current is reduced by 50% with a RSET of 300 Ω and a RLOAD of 75 Ω. This mode is recommended for
3.3 volt operation as optimum performance is obtained from the DAC outputs at 18 mA with a VAA of 3.3 volts. This buffer also
adds extra isolation on the video outputs, see buffer circuit in Figure 70. When calculating absolute output full current and voltage,
use the following equation:
V OUT = IOUT × RLOAD
IOUT =
(V REF ×K )
RSET
K = 4.2146 constant , VREF = 1.235 V
VAA
ADV7175A/ADV7176A
VREF OUTPUT
DAC A
BUFFER
75⍀
OUTPUT
DAC B
PIXEL DIGITAL BUFFER
75⍀
PORT CORE
OUTPUT
DAC C BUFFER
75⍀
RSET
300⍀ OUTPUT
DAC D
BUFFER
75⍀
Figure 69. Output DAC Buffering Configuration
VCC+
OUTPUT TO
AD8051
INPUT/ TV/MONITOR
OPTIONAL
FILTER O/P
VCC–
Figure 70. Recommended Output DAC Buffer
–38– REV. C
ADV7175A/ADV7176A
APPENDIX 8
OUTPUT WAVEFORMS
0.6
0.4
VOLTS
0.2
0.0
ⴚ0.2
L608
0.0 10.0 20.0 30.0 40.0 50.0 60.0

MICROSECONDS
NOISE REDUCTION: 0.00 dB
APL = 39.1% PRECISION MODE OFF SOUND-IN-SYNC OFF
625 LINE PAL NO FILTERING SYNCHRONOUS SYNC = SOURCE
SLOW CLAMP TO 0.00 V AT 6.72 ␮s FRAMES SELECTED: 1 2 3 4
Figure 71. 100/0/75/0 PAL Color Bars
0.5
VOLTS
0.0
L575
0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0

MICROSECONDS
APL NEEDS SYNC = SOURCE! PRECISION MODE OFF SOUND-IN-SYNC OFF
625 LINE PAL NO FILTERING SYNCHRONOUS SYNC = A
SLOW CLAMP TO 0.00 V AT 6.72 ␮s FRAMES SELECTED: 1
Figure 72. 100/0/75/0 PAL Color Bars Luminance
REV. C –39–
ADV7175A/ADV7176A
0.5
VOLTS
0.0
–0.5
L575
10.0 20.0 30.0 40.0 50.0 60.0

MICROSECONDS NO BRUCH SIGNAL
APL NEEDS SYNC = SOURCE! PRECISION MODE OFF SOUND-IN-SYNC OFF
625 LINE PAL NO FILTERING SYNCHRONOUS SYNC = A
SLOW CLAMP TO 0.00 V AT 6.72 ␮s FRAMES SELECTED: 1
Figure 73. 100/0/75/0 PAL Color Bars Chrominance
100.0
0.5
IRE:FLT
VOLTS
50.0
0.0
0.0
F1
–50.0
L76
0.0 10.0 20.0 30.0 40.0 50.0 60.0

MICROSECONDS
APL = 44.6% PRECISION MODE OFF
525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = A
SLOW CLAMP TO 0.00 V AT 6.72 ␮s FRAMES SELECTED: 1 2
Figure 74. 100/7.5/75/7.5 NTSC Color Bars
–40– REV. C
ADV7175A/ADV7176A
0.6
0.4
50.0
IRE:FLT
VOLTS
0.2
0.0 0.0
–0.2
F2
L238
10.0 20.0 30.0 40.0 50.0 60.0

MICROSECONDS
NOISE REDUCTION: 15.05dB
APL = 44.7% PRECISION MODE OFF
525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = SOURCE
Figure 75. 100/ 7.5/75/7.5 NTSC Color Bars Chrominance
0.4
50.0
0.2
IRE:FLT
VOLTS
0.0
–0.2
–50.0
–0.4
F1
L76
0.0 10.0 20.0 30.0 40.0 50.0 60.0

MICROSECONDS
NOISE REDUCTION: 15.05dB
APL NEEDS SYNC = SOURCE! PRECISION MODE OFF
525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = B
Figure 76. 100/ 7.5/75/7.5 NTSC Color Bars Chrominance
REV. C –41–
ADV7175A/ADV7176A
V
APL = 39.6% SYSTEM LINE L608
ANGLE (DEG) 0.0
GAIN x 1.000 0.000dB
cy
625 LINE PAL
BURST FROM SOURCE
DISPLAY +V & –V
R
g
M
g
75%
100%
YI b
yl B
G
Cy
m
g
SOUND IN SYNC OFF
Figure 77. PAL Vector Plot
R-Y
APL = 45.1% SYSTEM LINE L76F1
ANGLE (DEG) 0.0
GAIN x 1.000 0.000dB
I cy 525 LINE NTSC
BURST FROM SOURCE
R
M
g Q
YI b
100%
B-Y
75%
B
G
Cy
–Q
–I
SETUP 7.5%
Figure 78. NTSC Vector Plot
–42– REV. C
ADV7175A/ADV7176A
COLOR BAR (NTSC) WFM --> FCC COLOR BAR
FIELD = 2 LINE = 28
LUMINANCE LEVEL (IRE)
0.4 0.2 0.2 0.0 0.2 0.1 0.2 0.1
30.0
20.0
10.0
0.0
–10.0
CHROMINANCE LEVEL (IRE)

0.0 –0.2 –0.2 –0.3 –0.2 –0.3 0.0 0.0
1.0
0.0
–1.0
CHROMINANCE PHASE (DEG)

..... –0.1 –0.2 –0.2 –0.1 –0.3 –0.2 -----
0.0
–1.0
–2.0
GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK
AVERAGE: 32 --> 32 REFERENCE 75/7.5/75/7.5 COLOR BAR STANDARD
Figure 79. NTSC Color Bar Measurement
DGDP (NTSC) WFM --> MOD 5 STEP

BLOCK MODE START F2 L64, STEP = 32, END = 192
DIFFERENTIAL GAIN (%) MIN = –0.00 MAX = 0.11 p-p/MAX = 0.11
0.00 0.08 0.07 0.11 0.07 0.05
0.3
0.2
0.1
0.0
–0.1
DIFFERENTIAL PHASE (DEG) MIN = –0.02 MAX = 0.14 p-p = 0.16

0.00 0.03 –0.02 0.14 0.10 0.10
0.20
0.15
0.10
0.05
–0.00
–0.05
–0.10
1ST 2ND 3RD 4TH 5TH 6TH
Figure 80. NTSC Differential Gain and Phase Measurement
REV. C –43–
ADV7175A/ADV7176A
LUMINANCE NONLINEARITY (NTSC) WFM --> 5 STEP
FIELD = 2 LINE = 21
LUMINANCE NONLINEARITY (%) p-p = 0.2
99.9 100.0 99.9 99.9 99.8
100.4
100.3
100.2
100.1
100.0
99.9
99.8
99.7
99.6
99.5
99.4
99.3
99.2
99.1
99.0
98.9
98.8
98.7
98.6
1ST 2ND 3RD 4TH 5TH
Figure 81. NTSC Luminance Nonlinearity Measurement
CHROMINANCE AM PM (NTSC) WFM --> APPROPRIATE

FULL FIELD (BOTH FIELDS)
BANDWIDTH 100Hz TO 500kHz
AM NOISE –68.4dB RMS
–75.0 –70.0 –65.0 –60.0 –55.0 –50.0 –45.0 –40.0

dB RMS
PM NOISE –64.4dB RMS
–75.0 –70.0 –65.0 –60.0 –55.0 –50.0 –45.0 –40.0

dB RMS
(0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL)
Figure 82. NTSC AMPM Noise Measurement
–44– REV. C
ADV7175A/ADV7176A
NOISE SPECTRUM (NTSC) WFM --> PEDESTAL
FIELD = 2 LINE = 64
AMPLITUDE (0 dB = 714mV p-p) NOISE LEVEL = –80.1 dB RMS
BANDWIDTH 100kHz TO FULL
–5.0
–10.0
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
–55.0
–60.0
–65.0
–70.0
–75.0
–80.0
–85.0
–90.0
–95.0
–100.0
1.0 2.0 3.0 4.0 5.0 6.0

MHz
Figure 83. NTSC SNR Pedestal Measurement
NOISE SPECTRUM (NTSC) WFM --> RAMP SIGNAL

FIELD = 2 LINE = 64
AMPLITUDE (0 dB = 714mV p-p) NOISE LEVEL = –61.7 dB RMS
BANDWIDTH 10kHz TO FULL (TILT NULL)
–5.0
–10.0
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
–55.0
–60.0
–65.0
–70.0
–75.0
–80.0
–85.0
–90.0
–95.0
–100.0
1.0 2.0 3.0 4.0 5.0

MHz
Figure 84. NTSC SNR Ramp Measurement
REV. C –45–
ADV7175A/ADV7176A
PARADE SMPTE/EBU PAL
mV Y(A) mV Pb(B) mV Pr(C)
700 250 250
600 200 200
500 150 150
400 100 100
300 50 50
200
0 0
100 –50 –50
0 –100 –100
ⴚ100 –150 –150
ⴚ200 –200
–200
ⴚ300 –250
–250
Figure 85. PAL YUV Parade Plot
VM700A DEV 3 WC TEMP = 90ⴗC VDD = 5.25V

CHANNEL C SYSTEM DEFAULT 10-APR-97 09:23:07
LIGHTNING COLORBARS: 75% SMPTE/EBU (50Hz) AVERAGE 15 --> 32
L183 Pk-WHITE (100%) 700.0mV SETUP 0.0% COLOR p-p 525.0mV
YI G R CY M B
–274.82 –173.24 –88.36 88.31 174.35 260.51
0.93% 0.19% 0.19% 0.28% –0.65% –0.14%
B-Y
W
YI
CY
462.80
YI 864.78
–0.50%
–0.88%
G G
307.54 CY M
–0.21% 216.12
R –0.33%
M
R
156.63
–0.22% B B
B 61.00
R 1.92%
G M
CY
YI
W
R-Y
CY G B YI M R
–262.17 –218.70 –42.54 41.32 212.28 252.74
–0.13% –0.51% 0.69% –0.76% –3.43% –3.72%
COLOR P-P: B-Y 532.33mV 1.40% R-Y 514.90mV –1.92%

Pk-WHITE: 700.4mV (100%) SETUP –0.01% DELAY: B-Y –6ns R-Y –6ns
Figure 86. PAL YUV Lighting Plot
–46– REV. C
ADV7175A/ADV7176A
COMPONENT NOISE
LINE = 202
AMPLITUDE (0dB = 700mV p-p) NOISE dB RMS
BANDWIDTH 10kHz TO 5.0MHz
0.0
–5.0
–10.0
–15.0 -->Y –82.1
Pb –82.3
–20.0 Pr –83.3
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
–55.0
–60.0
–65.0
–70.0
–75.0
–80.0
–85.0
–90.0
–95.0
–100.0
1.0 2.0 3.0 4.0 5.0 6.0
MHz
Figure 87. PAL YUV SNR Plot
COMPONENT MULTIBURST
LINE = 202
AMPLITUDE (0dB = 100% OF 688.1mV 683.4mV 668.9mV
(dB)
0.04 –0.02 –0.05 –0.68 –2.58 –8.05
0.0
Y –5.0
–10.0
0.49 0.99 2.00 3.99 4.79 5.79
0.21 0.23 –0.78 –2.59 –7.15

0.0
Pb –5.0
–10.0
0.49 0.99 1.99 2.39 2.89
0.25 0.25 –0.77 –2.59 –7.13
0.0
Pr –5.0
–10.0
0.49 0.99 1.99 2.39 2.89
(MHz)
Figure 88. PAL YUV Multiburst Response
REV. C –47–
ADV7175A/ADV7176A
COMPONENT VECTOR SMPTE/EBU, 75%
M
g
YI
BK
CY
Figure 89. PAL YUV Vector Plot
RGB PARADE SMPTE/EBU
mV GREEN (A) mV BLUE (B) mV RED (C)
700 700
700
600 600
600
500 500
500
400 400
400
300 300
300
200 200
200
100 100
100
0 0
0
ⴚ100 ⴚ100 ⴚ100
ⴚ200 ⴚ200 ⴚ200
ⴚ300 ⴚ300 ⴚ300
20 --> 32
Figure 90. PAL RGB Waveforms
–48– REV. C
ADV7175A/ADV7176A
INDEX
Contents Page No. Contents Page No.
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1 MR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 24
ADV7175A/ADV7176A SPECIFICATIONS . . . . . . . . . . . 2 SUBCARRIER FREQUENCY REGISTER . . . . . . . . . . . 24
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 9 SUBCARRIER PHASE REGISTER . . . . . . . . . . . . . . . . . 24
PACKAGE THERMAL PERFORMANCE . . . . . . . . . . . . . 9 TIMING REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 24
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 9 CLOSED CAPTIONING EVEN FIELD . . . . . . . . . . . . . 25
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . 10 CLOSED CAPTIONING ODD FIELD . . . . . . . . . . . . . 25
DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . 11 TIMING REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 25
INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . 11 TR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 25
COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . 13 MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . 13 MR2 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 25
COLOR SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . 13 NTSC PEDESTAL/PAL TELETEXT CONTROL
BURST SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . 13 REGISTERS 3–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . 13 MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PIXEL TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . 13 MR3 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 26
SUBCARRIER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TTXREQ CONTROL REGISTER TC07 . . . . . . . . . . . . 27
REAL TIME CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . 13 APPENDIX 1. BOARD DESIGN AND LAYOUT
VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . 13 CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Timing Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 APPENDIX 2. CLOSED CAPTIONING . . . . . . . . . . . . 30
Timing Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 APPENDIX 3. TELETEXT INSERTION . . . . . . . . . . . 31
Timing Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 APPENDIX 4. WAVEFORMS . . . . . . . . . . . . . . . . . . . . 32
Timing Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 APPENDIX 5. REGISTER VALUES . . . . . . . . . . . . . . . 36
OUTPUT VIDEO TIMING . . . . . . . . . . . . . . . . . . . . . . . 21 APPENDIX 6. OPTIONAL OUTPUT FILTER . . . . . . . 37
POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 APPENDIX 7. OPTIONAL DAC BUFFERING . . . . . . 38
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 21 APPENDIX 8. OUTPUT WAVEFORMS . . . . . . . . . . . . 39
REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . 23 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 50
REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . 23
MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 23
REV. C –49–
ADV7175A/ADV7176A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic Quad Flatpack

(S-44)
C00225a–0–12/00 (rev. C)
0.548 (13.925)
0.546 (13.875)
0.096 (2.44)
MAX 0.398 (10.11)
0.390 (9.91)
0.037 (0.94)
8°
0.025 (0.64) 33 23
0.8°
34 22
SEATING
PLANE
TOP VIEW
(PINS DOWN)
44 12
0.040 (1.02) 1 11
0.040 (1.02)
0.032 (0.81)
0.032 (0.81)
0.033 (0.84) 0.016 (0.41)
0.083 (2.11) 0.029 (0.74) 0.012 (0.30)
0.077 (1.96)
PRINTED IN U.S.A.
–50– REV. C

High Quality, 10-Bit, Digital CCIR-601 To PAL/NTSC Video Encoder

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High Quality, 10-Bit, Digital CCIR-601

CLOCK RESET SCLOCK SDATA ALSB SCRESET/RTC GND

Parameter Conditions1 Min Typ Max Unit

5 V DYNAMIC SPECIFICATIONS unless otherwise noted.)

Parameter Conditions Min Typ Max Unit

Figure 1. MPU Port Timing Diagram

Figure 2. Pixel and Control Data Timing Diagram

4 CLOCK 4 CLOCK 4 CLOCK 3 CLOCK

Figure 3. Teletext Timing Diagram

Temperature Package Package

P10 7 TOP VIEW 27 DAC D

PASSBAND PASSBAND STOPBAND STOPBAND

Figure 4. Luminance Internal Filter Specifications

PASSBAND PASSBAND STOPBAND STOPBAND ATTENUATION @

NTSC 1.0 0.085 3.2 >40 0.3 2.05

Figure 5. Chrominance Internal Filter Specifications

Figure 6. NTSC Low-Pass Filter Figure 9. PAL Notch Filter

Figure 8. PAL Low-Pass Filter Figure 11. NTSC UV Filter

transition occurs on this input pin.

Figure 13. RTC Timing and Connections

EAV CODE SAV CODE

Figure 14. Timing Mode 0 (Slave Mode)

522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22

F EVEN FIELD ODD FIELD

F ODD FIELD EVEN FIELD

Figure 15. Timing Mode 0 (NTSC Master Mode)

622 623 624 625 1 2 3 4 5 6 7 21 22 23

F EVEN FIELD ODD FIELD

F ODD FIELD EVEN FIELD

Figure 16. Timing Mode 0 (PAL Master Mode)

Figure 17. Timing Mode 0 Data Transitions (Master Mode)

522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22

FIELD EVEN FIELD ODD FIELD

FIELD ODD FIELD EVEN FIELD

Figure 18. Timing Mode 1 (NTSC)

622 623 624 625 1 2 3 4 5 6 7 21 22 23

FIELD EVEN FIELD ODD FIELD

FIELD ODD FIELD EVEN FIELD

Figure 19. Timing Mode 1 (PAL)

PAL = 132 * CLOCK/2

Figure 20. Timing Mode 1 Odd/Even Field Transitions Master/Slave

Mode 2: Slave Option HSYNC, VSYNC, BLANK

522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22

VSYNC EVEN FIELD ODD FIELD

VSYNC EVEN FIELD

Figure 21. Timing Mode 2 (NTSC)

622 623 624 625 1 2 3 4 5 6 7 21 22 23

VSYNC EVEN FIELD ODD FIELD

VSYNC ODD FIELD EVEN FIELD

Figure 22. Timing Mode 2 (PAL)

Figure 23. Timing Mode 2 Even-to-Odd Field Transition Master/Slave

PAL = 132 * CLOCK/2

Figure 24. Timing Mode 2 Odd-to-Even Field Transition Master/Slave

522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22

FIELD EVEN FIELD ODD FIELD

FIELD ODD FIELD EVEN FIELD

Figure 25. Timing Mode 3 (NTSC)

622 623 624 625 1 2 3 4 5 6 7 21 22 23