LCD Television

Service Manual

Chassis： MSDFRX1603

Product: Roku BBY TV

Ver 1.0

Hisense Electric Co.，Ltd.

March, 2018
Version Page Section Description Date

Ver1.0 ALL ALL First issued 2018-03-26

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 Contents
Contents .......................................................................................................................................................................- 3 - 
Service Manual ...........................................................................................................................................................- 4 - 
1. Precautions and notices.....................................................................................................................................- 4 - 
1.1 Warning...................................................................................................................................................- 5 - 
1.2 Notes .......................................................................................................................................................- 7 - 
2. TV boards: ......................................................................................................................................................- 10 - 
2.1 Main board layout .................................................................................................................................- 10 - 
2.2.1 Main board :RSAG7.820. 7900 /ROH layout:...................................................................................- 10 - 
3. Factory/Service OSD Menu and Adjustment ..................................................................................................- 12 - 
3.1 How to enter the Factory OSD Menu ...................................................................................................- 12 - 
3.2 Factory OSD Menu ...............................................................................................................................- 14 - 
4. Software Upgrading ........................................................................................................................................- 16 - 
USB Upgrading ..........................................................................................................................................- 16 - 
5. Trouble shooting .............................................................................................................................................- 17 - 
5.1 Troubleshooting for Remote Control ....................................................................................................- 18 - 
5.2 Troubleshooting for Function Key ........................................................................................................- 19 - 
5.3 TV won’t Power On ..............................................................................................................................- 20 - 
5.4 Troubleshooting for Audio ....................................................................................................................- 21 - 
5.5 Troubleshooting for TV/VGA/HDMI input..........................................................................................- 22 - 
5.6 Troubleshooting for YPbPr input ..........................................................................................................- 23 - 
5.7 Troubleshooting for Video input ...........................................................................................................- 24 - 
6. Signals Block Diagram & power tree & schematic diagram : ........................................................................- 24 - 

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 Service Manual
1. Precautions and notices

BEFORE SERVICING THE LCD TV, READ THE SAFETY PRECAUTIONS IN

THIS MANUAL.

USE ONLY MANUFACTURER SPECIFIED REPLACEMENT PARTS WHEN

SERVICING.

USE OF NON-AUTHORIZED PARTS WILL VOID THE MANUFACTURE'S

WARRANTY

Proper service and repair is important to the safe, reliable operation of all Hisense

Equipment. The service procedures recommended by Hisense and described in this

Service Guide are effective methods of performing service operations. Some of these

service operations require the use of tools specially designed for the purpose. The special

tools should be used when and as recommended.

It is important to note that this manual contains various CAUTIONS and NOTICES

which should be carefully read in order to minimize the risk of personal injury to service

personnel. The possibility exists that improper service methods may damage the

equipment and pose risk of personal injury

. It is also important to understand that these CAUTIONS and NOTICES ARE NOT

EXHAUSTIVE. Service should only be performed by an experienced electronics

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techician trained in the proper Television safety and service methods and procedures

Hereafter throughout this manual, HISENSE will be referred to.

1.1 Warning

1.1.1

Critical components having special safety characteristics are identified with a by the

Ref. No. in the parts list. Use of non-manufacturer's recommended parts may create

shock, fire, or other hazards. Under no circumstances should the original design be

modified or altered without written permission from RCA. Hisense assumes no liability,

express or implied, arising out of any unauthorized modification of design. Servicetech

assumes all liability.

1.1.2.

All ICs and many other semiconductors are susceptible to electrostatic discharges (ESD).

Careless handling during repair can reduce life drastically. When repairing, be sure to

use anti-static table mats and properly use a grounding wrist stra. Keep components and

tools also at this same potential.

IMPORTANT:

Always disconnect the power cord from AC outlet before replacing parts or modules.

1.1.3

To prevent electrical shock, use only a properly grounded 3 prong outlet or extension

cord.

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1.1.4

When replacement parts are required, be sure to use replacement parts specified by the

manufacturer or have the same characteristics as the original part. Unauthorized

substitutions may result in fire, electric shock, or other hazards and will void the

manufacturer's warranty.

1.1.5

Safety regulations require that after a repair the set must be returned in its original

condition. In addition, prior to closing set, check that:

-Note:

>All wire harnesses and flex cables are properly routed and secured with factory tape

and/or mounted cable clamps.

> All cables and connectors are properly insulated and do not have any bare wires/lead

exposed

1.1.6

(1) Do not supply a voltage higher than that specified to this product. This may

damage the product and may cause a fire.

(2) Do not use this product:

> High humidity areas

> In an area where any water could enter or splash into the unit.

High humidity and water could damage the product and cause fire.

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 (3) If a foreign substance (such as water, metal, or liquid) gets inside the panel

module, immediately turn off the power. Continuing to use the product may cause fire

or electric shock.

(4) If the product emits smoke, and abnormal smell, or makes an abnormal sound,

immediately turn off the power. Continuing to use the product, it may cause fire or

electric shock.

(5) Do not pull out or insert the power cable from/to an outlet with wet hands. It may

cause electric shock.

(6) Do not damage or modify the power cable. It may cause fire or electric shock.

(7) If the power cable is damaged, or if the connector is loose, do not use the product:

otherwise, this can lead to fire or electric shock.

(8) If the power connector or the connector of the power cable becomes dirty or dusty,

wipe it with a dry cloth. Otherwise, this can lead to fire.

(9) Use only with the cart, stand, tripod, bracket, or table specified by the manufacturer,

or sold with the apparatus. When a cart is used, use caution when moving the

cart/apparatus combination to avoid injury from tip-over

1.2 Notes

Notes on Safe Handling of the LCD panel and during service

The work procedures shown with the Note indication are important for ensuring the

safety of the product and the servicing work. Be sure to follow these instructions.

• Before starting the work, secure a sufficient working space.

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• At all times other than when adjusting and checking the product, be sure to turn OFF

the POWER Button and disconnect the power cable from the power source of the TV

during servicing.

• To prevent electric shock and breakage of PC board, start the servicing work at least 30

seconds after the main power has been turned off. Especially when installing and

removing the power board, start servicing at least 2 minutes after the main power has

been turned off.

• While the main power is on, do not touch any parts or circuits other than the ones

specified. If any connection other than the one specified is made between the measuring

equipment and the high voltage power supply block, it can result in electric shock or

may trip the main circuit breaker When installing the LCD module in, and removing it

from the packing carton, be sure to have at least two persons perform the work.

• When the surface of the panel comes into contact with the cushioning materials, be

sure to confirm that there is no foreign matter on top of the cushioning materials before

the surface of the panel comes into contact with the cushioning materials. Failure to

observe this precaution may result in, the surface of the panel being scratched by foreign

matter.

• Be sure to handle the circuit board by holding the large parts as the heat sink or

transformer. Failure to observe this precaution may result in the occurrence of an

abnormality in the soldered areas.

• Do not stack the circuit boards. Failure to observe this precaution may result in

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problems resulting from scratches on the parts, the deformation of parts, and

short-circuits due to residual electric charge.

• Perform a safety check when servicing is completed. Verify that the peripherals of the

serviced points have not undergone any deterioration during servicing. Also verify that

the screws, parts and cables removed for servicing purposes have all been returned to

their proper locations in accordance with the original setup.

The lightning flash with arrowhead symbol, within an equilateral triangle is

intended to alert the user to the presence of uninsulated dangerous voltage within the

products enclosure that may be of sufficient magnitude to constitute a risk of electric

shock.

The exclamation point within an equilateral triangle is intended to alert the

service personnel to important safety information in the service literature. .

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 2. TV boards:

2.1 Main board layout

2.2.1 Main board :RSAG7.820. 7900 /ROH layout:

15
1
14
2

13
3

MSDFRX1603

11 10 7
12 9 8

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2.1.2 External terminals description:

No. Terminal item  Terminal description remark 

ANT & Cable IN
1 U8
Reset
2 SW1
AV in
3 XS8
HDMI1/ARC
4 XS5
HDMI2
5 XS6
HDMI3
6 XS7
Earphone hole
7 XS4
IR & Key socket
8 XP3
WIFI socket
9 XP2
Speaker socket
10 XP16
LVDS
11 XP8
Power input
12 XP802
USB2.0
13 XS2
Digital output
14 XS1 (optical)
Line output
15 XS9

2.2 Main board simply

Main board Boards function difference For Series

Complex board (main board & power

7900 board) HU32K2601HWR(2001)

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3. Factory/Service OSD Menu and Adjustment

3.1 How to enter the Factory OSD Menu

3.1.1. With user’s RC

1. Power TV On.

2. Press 5 times button、2 times button、2 times button and one time

button continuously, then the capital “M” display on the TV screen.

3. Press the “NETFLIX” button under button , then display the Factory menu.

Note; actually the remote control has NETFLIX silk-screen although the RC picture have none to
chapter 3.1.2 Buttons on TV Remote .

Factory menu figures as following

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3.1.2 Buttons on TV Remote:

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3.2 Factory OSD Menu

Factory OSD menu list: if you want to learn more about TV, you’d better read it but

would not adjust the value please. The Factory menu may be has difference for diverse

market and customer. Take HU32K2601HWR(2001) for example.

R Gain
G Gain
White Balance B Gain
R offset
G offset
B offset

Note:
Different source has different WB values. Before adjusting, please change to desired source.

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 TO FAC
Open Vchip Limit
Clean All
Factory Option Clean Protected
Factory SN
Image Switch
Set project ID
Restore Gamma Data

Version Info, take HU32K2601HWR(2001) for example ,it Includes TV model and TV current Version.

Model Num LC-32LB591U

Version Info Version xxx.xxxxxxxxx

Chip
Mstar-T14

MAC(wifi) and USB Update take HU55N3060UWGR for example ,

MAC(wifi) 64:6C:69:14:C0:a7

USB software updating……

USB Update

Note:
Above Factory menu only for reference, may have difference for diverse market and customer.

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4. Software Upgrading

USB Upgrading

1、 Download file and rename it.

Download ‘update.roku.his.shp.bby.7.5.0.****.app’ file which for roku Sharp BBY TV

then rename it as “update.roku”;

2、 Copy the “update.roku” file into a USB disk which no other “*.roku” file.
3、 Connect the USB disk to the TV USB port.
4、 Go to the USB Update menu item.
a. Perform to 3.3.1 TO enter Factory OSD Menu.
b. Scroll down to USB UPDATE.
5、 Select “USB Update” item and Update process will start automatically (the screen with progress
indicator bar)
6、 Upon completion ,TV should reboot.

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5. Trouble shooting

When there is something wrong with your TV, you can try turning off the TV and then restart it.
You can also operate according to the follow chart. If the problems still cann’t be solved, please
contact the profession technician.

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5.1 Troubleshooting for Remote Control

Remote control does not work

YES
Try new batteries Replace battery

NO

YES
Replace RC Replace remote control

Check IR receiver

YES
Change Led & IR board Replace Led & IR BD

NO

YES
Change Led & IR cable Replace Led & IR cable

NO

Replace main board

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5.2 Troubleshooting for Function Key

Buttons does not work

Check solder connections and see if

YES
Check switches any switches are stuck.

NO
YES
Check key board Replace Key BD

NO

Check Key BD cable

YES

Change Key BD OK

NO
Replace main board

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 5.3 TV won’t Power On

TV won’t power on

NO YES
Is LED Check Power Make Sure Power

light? Output source is live

YES NO YES

Check Power Cord Replace Power Cord

No light Blue light

Only one works

NO
Try Power on by RC and Check/replace IR BD

YES Check signal Button or Keypad PCA

Panel
Source Neither
YES Both
NO works
Work
NO Replace Main BD

Replace Main BD
YE
NO Power on
YES OK

Replace Panel
NO

Replace Power BD

OK

Note:

Led blue light when TV standby; led no light when TV work; the led blink at the beginning of TV power on .

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5.4 Troubleshooting for Audio

No sound

YES
Check connecter Reconnect

NO
YES
Check speaker wire Replace speaker wire

NO

YES
Check speaker set Replace speaker set

NO

Replace main board YES

OK

NO

Power Supply Board

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5.5 Troubleshooting for TV/VGA/HDMI input

No picture on the screen

NO
Check Signal Source
Make sure signal
source is available

YES
Check connect Reconnect

NO

YES
Check cable Replace cable

NO

Replace main board

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5.6 Troubleshooting for YPbPr input

No picture on the screen

Check Source work or not NO Check Source Device

YES

Check connect YES Reconnect

NO

YES
Check Wires (Green Blue, Red) Replace wires

NO

Replace main board

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5.7 Troubleshooting for Video input

No picture on the screen

Check Source work or not NO

Check Signal Source

YES

YES
Check connect Reconnect

NO

YES
Check Cable/ Wires Replace Cable/Wires

NO

Replace main board

6. Signals Block Diagram & power tree & schematic diagram :

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 5 4 3 2 1

External DDR3 NAND Flash

MIDLAND 256MB(2Gbit) SLC:512MB(4Gbit)
MAIN BOARD 512MB Optional
DDRx16
D
IR D

LED

Si2151
DDRB NAND
1866Mhz DDR3
Tuner I+Q GPIO / SAR KEY

CVBS IN CVBS LVDS

L+R AUDIO SPI
LCD Panel
DIM_PWM
RJ-45 Ethernet DDRx16
C BL_EN_GPIO C

Ethernet Optional 256MB DDR3 KGD

512MB Optional
HDMI1
+ARC HDMI_A 1866Mhz BL_ON_GPIO
SWITCH/
HDMI2 HDMI_C MStar BUCK

POWER 12V POWER

T14 POWER REGULATORS SUPPLY
HDMI3 HDMI_D (12V IN)
WIFI
2X2 Audio Power
802.11AC Supply (12V)

B USB0 Audio AMP B

I2S 10 Watt
SPK

SDIO AMP Line Out

Line Out GAIN2 JACK Lineout Optional
NOPOP

USB 2.0 HOST

00
Connector USB1 SPDIF SPDIF Out

79
SoC
USB0 GAIN1
HP JACK
HP Out NOPOP
Headphones Optional
A A

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 (1.1A max)
12V
3.3V_SB - 24mA w/o WiFi, 58mA w/WiFi
12V PANEL_VCC WIFI
FET PANEL
EN
3A/30V

Panel Power ON Enabled in Suspend Mode (155mA max)

IR/KEY Board (325mA max)

T14 MStar
T14 MStar
(1.653A max) STB CPU
(250mA max)
VCC12V MP1658GTF (308mA max)
V_1.5 DDR3
3.3V @ 3A 3.3V_SB TLV62566
1.5V @ 1A (575mA max) 12mA Stdby
Pull-up
EN=1 1.5V_PWR_GOOD
Main Supply Inputs

(90mA max)
P-FET VCC3.3V
3A, 26mOhm@ T14 MStar
2V5VGS STB CPU

Aux_Power_ONn NAND FLASH

Disabled in Standby
12V

(3.282A max) (932mA max)

MP1658GTF MP2131DG
VCC5V
VCC12V 5V @ 3A
1.1V @ 4A (3.6A max)
1V1_CORE
Aux_Power_ON EN=1 1.5V_PWR_GOOD
EN=1 T14 MStar
Disabled in Standby Vcore
1.1V

(2.1A max)
(1.5A - 2.1A)
VCC5V TPS2065D USB
AMP_PWR (12V) USB SWITCH 5V_USB TYPE A
.9A-1.5A
TAS5753 Speakers RESET PGOOD
Audio Amp 2 x 8 Ohms

00
2.0
(250mA)
(250mA)

79
Reset SoC_RESET
Descretes VCC5V TLV70233LDO 3.3V_TUNER Tuner
300mA SiliconLabs
Aux_Power_ON
250mA

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 5 4 3 2 1

3.3V_SB
3.3V_SB 3.3V_SB

3.3V_SB
R413 R3 R4
4.7k N2 10k 10k
V1 1% 1%
High Active Reset Out

2
3 2
R5 VCC RESET
11 RST_INHn 1 R6 0R/NC SoC_RST 7
D MMBT3906LT1 1 D
2.2k GND
Inhibit Reset from power regulators during Suspend

3
TLV803SDBZR
1 V2 SOC_RESET requirement
MMBT3904LT1
R7 6ms high after all power stable.

2
100R

SOC_RESET requirement
VDDC 2ms after 1.5V stable.
R388 Populate if
16 CORE_PWR_GOOD U1 is an
10k
Active Low
reset out.
DDR PWR or SoC Core PWR TLV803S
can cause RESET
C1
R387
16,17 1.5V_PWR_GOOD 100n/10V
10k Low Active Reset In/Out
SOC_RESETn 7
C C

C2
R9 100n/10V
3.3V_SB 100R

R10
4.7k
C3
1u/16V
R11
Reset Button
33R
RV1
KAN0663-0709B
AVLC18S02015/NC
2

C4
100n/10V
2

3
3
Raw Reset Button to SoC
SW can cause RESET
1

SW1
3.3V_SB
1

R12
B RST_BTNn 11 B
R13 33R
4.7k
Clear Reset Button Status Latch from SoC
R14
11 RST_LATCH_CLRn
33R
C5 R15
2

10n/10V 4.7k
VD1
1N4148W

00
1

V3
Latched Reset Button Status to SoC
2

MMBT3906LT1
1 R16
RST_BTNn_LATCH 11

79
33R
3

RST_BTNn_LATCH
1 V4 0 = RST_BTN
MMBT3904LT1 1 = AC PWR ON/Internal Reset
A A
2

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 5 4 3 2 1

T14 has internal ~100K pull-up on these GPIO but external resistors required NAND FLASH On FLASH Pins
512MB (4Gb) Standard VCC3.3V
See BOARD_ID spreadsheet VCC3.3V
Board ID[5:0] = 000001 (DVT) Use Assigned Value Here N3
C6 C7 C8
22u/6.3VV 100n/10V 100n/10V
Customer ID[3:0] 0000 = (Roku) VCC3.3V A1 L1
A2 A1 L1 L2
D
USE CUSTOMER SPECIFIC ID A2 L2 D
R25 R24 R23 R22 R21 R18 A9 L9
A10 A9 L9 L10
NC/4.7k NC/4.7k NC/4.7k NC/4.7k 4.7k NC/4.7k A10 L10
B1 M1
R27 B9 B1 M1 M2
BOARD_ID0 VCC3.3V B10 B9 M2 M9
4.7k B10 M9 M10
BOARD_ID1 D3 M10 VCC3.3V
CUST_ID0 D6 D3 G3
BOARD_ID2 D7 D6 G3 G4
CUST_ID1 D8 D7 G4 G5
BOARD_ID3 E3 D8 G5 G6
CUST_ID2 E4 E3 G6 G7
BOARD_ID4
Connections on D3, F7 and E5 E4 G7 G8
G4 for ONFI compatibility. E5 G8 Put this jumper on if needing to
CUST_ID3 E6 H3 write to NAND using JTAG >>>
BOARD_ID5 BOARD_ID CUSTOMER_ID E7 E6
E7
H3
H5
H5
VCC3.3V VCC3.3V
E8 H6
F3 E8 H6 H7
R39 R38 R37 R35 R34 R33 R32 R30 F4 F3 H7 J3
R36 R452
4.7k 4.7k F5 F4 J3 J5 R453
4.7k 4.7k 4.7k 4.7k NC/4.7k 4.7k 4.7k F5 J5
F6 NC/10k NC/10k
F7 F6 C3 NAND_WPn
VCC3.3V F8 F7 WP#
F8 C6 NAND_CEn
H8 CE#
C VCC2 R41 C
J6 D5 NAND_CLE
VCC3 CLE 1k
C4 NAND_ALE
N1B VCC3.3V NAND-AD0 H4 ALE
Idle-state = input w/ 100K PU NAND-AD1 J4 I/O0 C7 NAND_WEn
V15 W11 BOARD_ID0 NAND-AD2 K4 I/O1 WE# D4 NAND_REn
V16 PCM_D[0] TS0_D[0] Y10 BOARD_ID1 NAND-AD3 K5 I/O2 RE#
PCM_D[1] TS0_D[1] R42 I/O3
R16 W13 BOARD_ID2 NAND-AD4 K6 C5 C278
V17 PCM_D[2]
PCM_D[3]
TS0_D[2]
TS0_D[3]
Y12 BOARD_ID3 BOARD_ID 4.7k NAND-AD5 J7 I/O4
I/O5
VSS
VSS1
K3 <<< Near NAND pin-C7
PCB_D4 U17 W12 BOARD_ID4 NAND-AD6 K7 K8 NC/47p/50V
19 SDIO_D0 PCM_D[4] TS0_D[4] I/O6 VSS2
PCM_D5 AA15 Y13 BOARD_ID5 NAND-AD7 J8
19 SDIO_D1 PCM_D6 PCM_D[5] TS0_D[5] I/O7
U18 W10 CUST_ID0 C279
19 SDIO_D2 PCM_D[6] TS0_D[6]
PCM_D7 T12 V10 CUST_ID1 NAND_RBY C8 <<< Near NAND pin-D4
19 SDIO_D3 PCM_D[7] TS0_D[7] AA12 CUST_ID2 CUSTOMER_ID RB# NC/47p/50V
NAND-AD0 V12 TS0_CLK AA13 CUST_ID3
PCM_A[0] TS0_VLD MX30LF4G28AC
NAND-AD1 T17 Y11 R44
PCM_A[1] TS0_SYNC USB_OCn 8
NAND-AD2 AA16
NAND-AD3 T16 PCM_A[2] T9 GPIO NC/4.7k
NAND-AD4 R15 PCM_A[3]
PCM_A[4]
TS1_D[0]
TS1_D[1]
T8 0R R45
MSPI1_SDO 19
USB_EN 8
NOTE: 1) Add series termination to CMD & DATA for long traces
NAND-AD5 U13 V9 33R R46
NAND-AD6 R17 PCM_A[5]
PCM_A[6]
TS1_D[2]
TS1_D[3]
U7 33R R47
AMP_MUTEn 13
HP-MUTEn 13
2) trace to trace space = trace width x 2
NAND-AD7 T11 U9 MSPI1_INTn 19
T13 PCM_A[7] TS1_D[4] V7 SKT1
PCM_A[8] TS1_D[5] 0R R48 AUDIO_RSTn 13
Idle-state = tri-stated w/ 100K PU T14 U10 0R R49 LO-MUTEn 21
U16 PCM_A[9] TS1_D[6] V8
B
PCM_A[10] TS1_D[7] SOC-BL_ON 18 <<< Layout PCB to center 67-pin NAND device in SG-BGA-6367 socket footprint. B
Y14 U8 MSPI1_SCZ 19
(Backlight_EN)
V13 PCM_A[11] TS1_CLK R10
No Termination Required W15 PCM_A[12] TS1_VLD T10
MSPI1_SDI 19
R14 PCM_A[13] TS1_SYNC MSPI1_SCK 19 NAND Support:
On Unused Pins PCM_A[14]
63 Ball Pinout should be ----Toshiba----
Y15 overlayed with 67 Ball
PCM_IRQA_N U12 PCM_RESET W1 TC58NVG2S0HBAI6 - 67 pin package
19 SDIO_CD PCM_IRQA_N IP_T TIN_P 15 pinout for SG-BGA-6367
W14
T15 PCM_IOWR_N IM_T
W2
U4
TIN_M 15 3.3V_TUNER and
IFAGC 15 SG-BGA-6367
U11 PCM_OE_N IFAGC_T
Socket NAND for EVT / DVT only TC58NVG2S0HBAI4 - 63 pin package
W16 PCM_WAIT_N
Y16 PCM_IORD_N Y3
----Macronix----
PNL_WPn 12
U14 PCM_CD_N
PCM_REG_N
GPIO86/TGPIO0
GPIO87/TGPIO1
T4
HDMI3_DET 14
R51 R52 MX30LF4G28AC-XKI - 63 pin package
U15 W3 2.2k 2.2k ----Micron----

00
T18 PCM_WE_N GPIO88/TGPIO2/I2C_SCL Y1
PCM_CE_N GPIO89/TGPIO3/I2C_SDA MT29F4G08ABAEAH4 - 63 pin package
Dedicated Tuner I2C bus
R54 100R TUNER_I2C_SCL 15
NAND_CEn W18 V1 R56 100R TUNER_I2C_SDA 15

79
NAND_WPn AA19 EMMC_IO[0]/NAND_CEZ IP_S V2
NAND_CLE Y19 EMMC_IO[1]/NAND_WPZ IM_S U2 (TUNER)
EMMC_IO[2]/NAND_CLE QP_S Place near Tuner I2C Address = 0xC0 / 0xC1
AA18 U3 R51, R52, R54, R56
NAND_REn Y18 EMMC_IO[3]/NAND_DQS QM_S T2
W17 EMMC_IO[4]/NAND_REZ IFAGC_S V4
EMMC_IO[5]/NAND_CEZ1 GPIO52/DISEQC_OUT HDMI2_DET 14 SPI used on Sheet 19
A NAND_WEn V18 A
EMMC_IO[6]/NAND_WEZ

t:
Y20
NAND_ALE Y17 EMMC_IO[7]
W21 EMMC_IO[8]/NAND_ALE
NAND_RBY W20 EMMC_IO[9]/EMMC_CMD
EMMC_IO[10]/EMMC_CLK/NAND_RBZ NOTE: Mstar does the SPI_SDO and Roku, Inc. Confidential
Y21
EMMC_IO[11]/EMMC_RSTn

MSDFRX1603
SPI_SDI from the slave perspective so
SPI_SDO is an input to the chip and SPI_SDI
ui Title

Size
CI/TS/NAND/BOARD_ID
Document Number Rev
B
rc
C1
is an output from the chip Midland (FHD), Roku-PN 0002001435
Date: Thursday, November 30, 2017 Sheet 5 of 20
5 4 3 2 1
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 5 4 3 2 1

PCB MUST MATCH MSTAR DDR REFERENCE LAYOUT PRECISELY AVDD_DDR1

B-DDR3-CKE

AVDD_DDR1 R64
1k C285
R63 R66
B-MVREFCA NC/10n/50VV
RN1 56R 1k C10
D 1k 1 8 RN13 0R D
R65 10n/50VV
C11 B_DDR3_BA1 2 7B-DDR3-BA1 1 8
1k C12 B_DDR3_A12 3 6B-DDR3-A12 B_DDR3_DQL0 2 7B-DDR3-DQL0 B-DDR3-RESET
100n/10V 1n/50V 4 5 B_DDR3_DQL2 3 6B-DDR3-DQL2
4 5
RN2 56R
1 8 RN14 0R AVDD_DDR1
B_DDR3_A10 2 7B-DDR3-A10 1 8
B_DDR3_CKE 3 6B-DDR3-CKE B_DDR3_DQL6 2 7B-DDR3-DQL6
AVDD_DDR1 4 5 B_DDR3_DQL4 3 6B-DDR3-DQL4
R69 4 5
B-MVREFDQ RN3 56R
1 8 B_DDR3_DQU5 R71 0R B-DDR3-DQU5
1k B_DDR3_A6 2 7B-DDR3-A6

G7
R9
R1
N9
N1

D9

H9
H2

D2
C9
C1
K8
K2

B2

E9

A1
A8
F1
R70 C13 B_DDR3_A4 3 6B-DDR3-A4
RN15 0R N4
4 5 1 8
1k C14

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
100n/10V 1n/50V RN4 56R B_DDR3_DQU7 2 7B-DDR3-DQU7
1 8 B_DDR3_DQU1 3 6B-DDR3-DQU1
B_DDR3_A11 2 7B-DDR3-A11 4 5 B-DDR3-A0 N3
B_DDR3_A8 3 6B-DDR3-A8 B-DDR3-A1 P7 A0 D3 B-DDR3-DMU
4 5 RN16 0R B-DDR3-A2 P3 A1 DMU C7 B-DDR3-DQSU
N1A 1 8 B-DDR3-A3 N2 A2 DQSU B7 B-DDR3-DQSUB
B_DDR3_DQU3 2 7B-DDR3-DQU3 B-DDR3-A4 P8 A3 /DQSU
E11 B_DDR3_A0 RN5 56R B_DDR3_DMU 3 6B-DDR3-DMU B-DDR3-A5 P2 A4 D7 B-DDR3-DQU0
C B_DDR3_A[0] 4 5 A5 DQU0 C
F12 B_DDR3_A1 1 8 B-DDR3-A6 R8 C3 B-DDR3-DQU1
B_DDR3_A[1] D10 B_DDR3_A2 B_DDR3_RASZ 2 7B-DDR3-RASZ B-DDR3-A7 R2 A6 DQU1 C8 B-DDR3-DQU2
B_DDR3_A[2] B10 B_DDR3_A3 B_DDR3_ODT 3 6B-DDR3-ODT B-DDR3-A8 T8 A7 DQU2 C2 B-DDR3-DQU3
B_DDR3_A[3] RN17 0R A8 DQU3
E15 B_DDR3_A4 4 5 1 8 B-DDR3-A9 R3 A7 B-DDR3-DQU4
B_DDR3_A[4] B11 B_DDR3_A5 B-DDR3-A10 L7 A9 DQU4 A2 B-DDR3-DQU5
B_DDR3_DQSLB 2 7B-DDR3-DQSLB
B_DDR3_A[5] F14 B_DDR3_A6 RN6 56R B-DDR3-A11 R7 A10 DQU5 B8 B-DDR3-DQU6
B_DDR3_DQSL 3 6B-DDR3-DQSL
B_DDR3_A[6] C11 B_DDR3_A7 1 8 B-DDR3-A12 N7 A11 DQU6 A3 B-DDR3-DQU7
4 5
B_DDR3_A[7] D14 B_DDR3_A8 B_DDR3_A1 2 7B-DDR3-A1 B-DDR3-A13 T3 A12 256MB Standard DQU7
B_DDR3_A[8] A12 B_DDR3_A9 B_DDR3_A14 3 6B-DDR3-A14 B-DDR3-A14 T7 A13
RN18 0R
B_DDR3_A[9] F16 B_DDR3_A10 4 5 1 8 M7 A14 512MB Option E7 B-DDR3-DML
B_DDR3_A[10] D13 B_DDR3_A11 B_DDR3_DQSUB 2 7B-DDR3-DQSUB B-DDR3-BA0 M2 A15 DML F3 B-DDR3-DQSL
B_DDR3_A[11] D15 B_DDR3_A12 B_DDR3_DQSU 3 6B-DDR3-DQSU B-DDR3-BA1 N8 BA0 DQSL G3 B-DDR3-DQSLB
B_DDR3_A[12] RN7 56R BA1 /DQSL
C12 B_DDR3_A13 1 8 4 5 B-DDR3-BA2 M3
B_DDR3_A[13] E13 B_DDR3_A14 BA2 K4B2G1646F-BCMA E3 B-DDR3-DQL0
B_DDR3_A9 2 7B-DDR3-A9
B_DDR3_A[14] 0R B-DDR3-RASZ J3 DQL0 F7 B-DDR3-DQL1
B_DDR3_A13 3 6B-DDR3-A13 RN19
B9 B_DDR3_CASZ 1 8 B-DDR3-CASZ K3 /RAS DQL1 F2 B-DDR3-DQL2
4 5
B_DDR3_CASZ C8 B_DDR3_RASZ B_DDR3_DQU0 2 7B-DDR3-DQU0 B-DDR3-WEZ L3 /CAS DQL2 F8 B-DDR3-DQL3
B_DDR3_RASZ D11 B_DDR3_WEZ B_DDR3_DQU4 3 6B-DDR3-DQU4 B-DDR3-ODT K1 /WE DQL3 H3 B-DDR3-DQL4
B_DDR3_WEZ RN8 56R ODT DQL4
B8 B_DDR3_ODT 1 8 4 5 B-DDR3-RESET T2 H8 B-DDR3-DQL5
B_DDR3_ODT A9 B_DDR3_BA0 B-DDR3-CKE K9 /RESET DQL5 G2 B-DDR3-DQL6
B_DDR3_BA[0] B_DDR3_WEZ 2 7 B-DDR3-WEZ CKE DQL6
D16 B_DDR3_BA1 B_DDR3_CS0 3 6B-DDR3-CS0 RN20 0R H7 B-DDR3-DQL7
B_DDR3_BA[1] A10 B_DDR3_BA2 B-DDR3-MCLK J7 DQL7
4 5 1 8
B_DDR3_BA[2] F10 B_DDR3_RESET K7
B-DDR3-MCLKZ CK
B_DDR3_DQU2 2 7B-DDR3-DQU2
B_DDR3_RST E17 B_DDR3_CKE /CK H1 B-MVREFDQ
B RN9 56R B_DDR3_DQU6 3 6B-DDR3-DQU6 B
B_DDR3_CKE VREFDQ
MIU1

A20 B_DDR3_DQL0 1 8 4 5 R79 J1 M8 B-MVREFCA

B_DDR3_DQ[0] A16 B_DDR3_DQL1 B_DDR3_A5 2 7B-DDR3-A5 J9 NC1 VREFCA
B_DDR3_DQ[1] R78 NC2
C19 B_DDR3_DQL2 B_DDR3_A7 3 6 B-DDR3-A7 RN21 0R L1
B_DDR3_DQ[2] C15 B_DDR3_DQL3 4 5 1 8 56R L9 NC3 L2 B-DDR3-CS0
B_DDR3_DQ[3] C20 B_DDR3_DQL4 B_DDR3_DQL5 2 7B-DDR3-DQL5 56R NC4 /CS
B_DDR3_DQ[4] C14 B_DDR3_DQL5 RN10 56R B_DDR3_DQL7 3 6B-DDR3-DQL7
B_DDR3_DQ[5]

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B21 B_DDR3_DQL6 1 8 4 5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B_DDR3_DQ[6] B15 B_DDR3_DQL7 B_DDR3_A2 2 7B-DDR3-A2

ZQ
B_DDR3_DQ[7] C16
F18 B_DDR3_DQU0 B_DDR3_A0 3 6B-DDR3-A0 RN22 0R
B_DDR3_DQ[8] D19 B_DDR3_DQU1 4 5 1 8
C15 100n/10V

L8
T9
T1
P9
P1
M9
M1
J8
J2
G8
E1
A9
B3
G9
G1
F9
E8
E2
D8
D1
B9
B1
B_DDR3_DQ[9] D17 B_DDR3_DQU2 B_DDR3_DQL3 2 7B-DDR3-DQL3
B_DDR3_DQ[10] E21 B_DDR3_DQU3 B_DDR3_DQL1 3 6B-DDR3-DQL1
RN11 56R 100n/10V
B_DDR3_DQ[11] E19 B_DDR3_DQU4 1 8 4 5
B_DDR3_DQ[12] R82
D20 B_DDR3_DQU5 B_DDR3_CASZ 2 7B-DDR3-CASZ

00
B_DDR3_DQ[13] D18 B_DDR3_DQU6 B_DDR3_BA0 3 6B-DDR3-BA0 B_DDR3_DML R83 0R B-DDR3-DML
B_DDR3_DQ[14] F20 B_DDR3_DQU7 4 5 240R
B_DDR3_DQ[15] C16 B_DDR3_DML RN23 0R 1%
B_DDR3_DQM[0] D21 B_DDR3_DMU 1 8
RN12 56R (Top side, close to DRAM)

79
B_DDR3_DQM[1] C13 B_DDR3_MCLK 1 8 B_DDR3_MCLKZ 2 7B-DDR3-MCLKZ
B_DDR3_MCLK B13 B_DDR3_MCLKZ B_DDR3_BA2 2 7B-DDR3-BA2 B_DDR3_MCLK 3 6B-DDR3-MCLK
B_DDR3_MCLKZ A19 B_DDR3_DQSL B_DDR3_A3 3 6B-DDR3-A3 4 5
B_DDR3_DQS[0] C18 B_DDR3_DQSLB 4 5
B_DDR3_DQSB[0] B18 B_DDR3_DQSU
B_DDR3_DQS[1] R85 56R
A C17 B_DDR3_DQSUB B_DDR3_RESET B-DDR3-RESET A
B_DDR3_DQSB[1]

t:
D12 B_DDR3_CS0
B_DDR3_CSB[0]

MSDFRX1603 Roku, Inc. Confidential

ui Title

Size
External DDR3
Document Number Rev
B C1
rc
Midland (FHD), Roku-PN 0002001435
Date: Friday, December 01, 2017 Sheet 6 of 20
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 5 4 3 2 1

N1C

14 HDMI2-RX0N G1
RXA0N Note:
14 HDMI2-RX0P G2
RXA0P Due to layout space limitation,
H3 R6
14 HDMI2-RX1N
H2 RXA1N LINEIN_L1 R4
below functions can only choose 3 of them.
14 HDMI2-RX1P
J3 RXA1P LINEIN_R1 R3 LINE_IN_2L C17 2.2u/10V 1. LINEIN 3 (N6, N7)
14 HDMI2-RX2N
J2 RXA2N LINEIN_L2 P2 LINE_IN_2R
AV_AUL 20 2. LINEOUT 2 (N5, M7)
14 HDMI2-RX2P RXA2P LINEIN_R2 AV_AUR 20 3. LINEOUT 3 (M5, M6)
F1 N6 C18 2.2u/10V

ANALOG AUDIO
14 HDMI2-CLKN
14 HDMI2-CLKP G3 RXACKN LINEIN_L3 N7 4. SPI1 CK/DI (M8, N4)
D F5 RXACKP LINEIN_R3 5. SPI2 CK/DI (M4, N8) D
14 HDMI2-SCL DDCDA_CK
F6
14 HDMI2-SDA DDCDA_DA
14 HDMI2-HPDIN D5
HOTPLUGA R5 HP_Audio-L 13
Close to SoC pin
Y6 EARPHONE_OUTL T5
14 HDMI0-RX0N RXC0N EARPHONE_OUTR HP_Audio-R 13
AA6
14 HDMI0-RX0P RXC0P
14 HDMI0-RX1N AA7 N5 C276 C277
Y7 RXC1N LINEOUT_L2 M7
14 HDMI0-RX1P RXC1P LINEOUT_R2 1n/50V 1n/50V
14 HDMI0-RX2N W7 M5 LO_DAC2_L 0R R480 AU_DAC2_L 21
Y8 RXC2N LINEOUT_L3 M6 LO_DAC2_R
ARC on this port >> 14 HDMI0-RX2P RXC2P LINEOUT_R3 0R R481 AU_DAC2_R 21
Y5
14 HDMI0-CLKN RXCCKN

HDMI
14 HDMI0-CLKP W5
W4 RXCCKP R1 AUVAG
14 HDMI0-SCL DDCDC_CK AUVAG
Y4 R2 AUVRM << Close to SoC on Top Layer
14 HDMI0-SDA DDCDC_DA AUVRM
14 HDMI0-HPDIN AA4
HOTPLUGC C23 C24
D1 J21 R407 33R I2S_SCLK 10u/6.3V 100n/10V L1
14 HDMI3-RX0N RXD0N I2S_OUT_BCK AUBCK_OUT 13
D2 K19 R406 33R I2S_MCLK 0R R482
14 HDMI3-RX0P RXD0P I2S_OUT_MCK AUMCK_OUT 13
SPDIF OUT

I2S
E3 J20 R408 33R I2S_LRCLK
14 HDMI3-RX1N RXD1N I2S_OUT_WS AUWS_OUT 13
E2 J19 R409 33R I2S_SDIN BLM21PG221SN1
14 HDMI3-RX1P RXD1P I2S_OUT_SD AUSD_OUT 13
F3
14 HDMI3-RX2N
14 HDMI3-RX2P F2
C1
RXD2N
RXD2P
VCC3.3V OPTICAL
14 HDMI3-CLKN XS1
D3 RXDCKN P18
14 HDMI3-CLKP R86

SPDIF
C RXDCKP SPDIF_IN C
14 HDMI3-SCL E4 R18 SPDIF_OUT SPDIF_OUT-B 1
E5 DDCDD_CK SPDIF_OUT 2 SPDIF
14 HDMI3-SDA DDCDD_DA 100R VCC
14 HDMI3-HPDIN D4 3

NC1
NC2
HOTPLUGD R88 GND
1u/10V C27 R87 0R E6 10k C25 C26
14 HDMI-C_ARC ARC0 M8 SPI1_CK
SDIO_CMD 19 22p/50V 100n/16V GQ-101\Reflow

4
5
F4 SPI1_CK N4 SPI1_DI
14 HDMI-CEC CEC SPI1_DI SDIO_CLK 19
M4
MHL_CBUS C3 SPI2_CK N8
C2 MHL_CBUS SPI2_DI
14 ARC_DET MHL_VBUS_EN
Near SoC pin-F4 >>> C280

DIMMING
NC/33p/50V A3
IRIN IRIN 9

LOCAL
F7 SoC_RST 4
K7 RESET
J7 NC-K7 Z1
NC-J7 AA2 SOC_XTALI 1 4
H8 XIN AA3 SOC_XTALO X1 GND_4
TESTPIN XOUT 2 3
R90 GND_2 X2
C28 C29
MSDFRX1603 7V24000020
18p/50V 18p/50V
1M
B B
CRYSTAL Requirements R393

0R

CRYSTAL
VCC3.3V

R91

00
R92 R93 R95
33R
1k/NC 1k 1k JTAG populated for EVT / DVT only
XP1
33R

79
1 2 EJ_TMS R97 DDCR_CK 11
3 4 EJ_TCK R98 33R AUSD_OUT

5 6 EJ_TDO R99 33R DDCR_DA 11

A A
7 8 EJ_TDI R100 33R SPDIF_OUT

t:
9 10 R101 33R SOC_RESETn 4
Roku, Inc. Confidential
T14-JTAG
ui Title

Size
SoC Crystal, HDMI & Audio, SPDIF
Document Number Rev
B C1
rc
Midland (FHD), Roku-PN 0002001435
Date: Monday, December 11, 2017 Sheet 7 of 20
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 5 4 3 2 1

No Termination Required
On Unused Pins
N1E
3U3WF
A6
K2 RN B6 3.3V_SB
RIN0P RP
K1 C6
Route for 1.1A load minimum

PHY
D K3 GIN0M TN B5 L2 D
GIN0P TP
J1
G5 BIN0P LAN_LED[0]
C7
C5
LED0 9 BLM31PG121SN1
C30
WiFi
LED1 9 C31
G6 HSYNC0 LAN_LED[1] WD- WD+
VSYNC0 Y9 R102 R103
100n/10V 10u/6.3V XP2
DM_P0 AA9
DP_P0 4.7k 4.7k
M2 W9 USB2_DM1
Route as differential pairs @ 90ohms 1

USB
RIN1P DM_P1
RGB
M3 AA10 USB2_DP1 2
USB2_DM2 \/
GIN1M DP_P1 R104 0R
L2 H20 3
L3 GIN1P DM_P2 H19 USB2_DP2 4
BIN1P DP_P2 5
R105 0R
11 WAKE_ON_WIFIn 6
N2 11 WIFI_REG_ON 7
N1 RIN2P J6 8
33R

CVBS
GIN2M CVBS1 C35 47n/16V R107
N3 K6 CVBS0 CVBS0-RCA CBVS0-RCA 20 11 HOST_WAKE_WL 9
M1 GIN2P CVBS0 K5 VCOM0 CVBS-VCOM 10
BIN2P VCOM CBVS-VCOM 20
G7 C36 47n/16V R108 68R C32 C33 C34
VSYNC2 J5 CVBS-out

11
12
CVBS_OUT1
NC/100n/10V NC/100n/10V NC/100n/10V

MSDFRX1603 R109
C37 75R
NC/330p/50V 1%
C C
WIFI Connector

USB Ports +5V_USB

USB Current Limit Detection / Switch

Route as differential pairs @ 90ohms 1
XS2

USB2_DM1 R110 0R\/ 2 VCC

>1.5A LIMIT TOTAL for USB Ports
USB2_DP1 R111 0R 3 D- C38 C39 C40

GND
4 D+
GND 220u/16VV
GAP2

10u/10VV 100n/10V
GAP3

GAP4

C41 C42

5
6
NC/10p/50V NC/10p/50V
1

NC/SPARK GAP

NC/SPARK GAP

NC/SPARK GAP

VD2
I/O1

I/O2

B +5V_USB B
ESDA6V8UL
USB2.0 Host
VCC5V
N5
GND

(Type A Connector)
5 1
IN OUT
2 VCC3.3V
3

C45 GND
C44
10u/10VV 100n/16V 4 3
EN FLT

TPS2065DDBVR R112
10k
5 USB_EN R451
USB_OCn 5
R113 22R

00
C303
100n/16V/NC 4.7k

EN and OC pins required

79
A A

t:
Roku, Inc. Confidential
ui Title

Size
SoC USB & WiFi
Document Number Rev
B C1
rc
Midland (FHD), Roku-PN 0002001435
Date: Thursday, November 30, 2017 Sheet 8 of 20
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 5 4 3 2 1

D D

3.3V_SB

LED / IR HEADER
R129
4.7k
3.3V_SB VCC3.3V
R133
IRIN 7
IR R131 R132 33R
C60 RV6
3.3V_SB 3.3V_SB
LED 3U3
0R 0R 1n/50V
C AVLC18S02015/NC C
R134
XP3 R135
1 BIR_D 1k 10k
2 R137 0R
3 BLED1 LED_CATHODE
4 B3.3
5 B3.3VSB
6 R138 0R/NC I2C-SCL-P 7,11,12
7

3
8 I2C-SDA-P 7,11,12
KEY0 11 R139 0R/NC
9 V5
1 R140 NC/0R
LED_PWM_ONn 11
11
10

2N7002K

3
2
C62 C63 V6
KEY1 1 R141 4.7k
HX1.25-9P-W-K\TP 100n/16V 100n/16V
2N7002K

2
Populate as needed
for LED default = ON
B B
when AC power applied.

00
79
A A

t:
Roku, Inc. Confidential
ui Title

Size
RJ45-10/100 Ethernet, LED / IR Header
Document Number Rev
B C1
rc
Midland (FHD), Roku-PN 0002001435
Date: Thursday, November 30, 2017 Sheet 9 of 20
5 4 3 2 1
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 5 4 3 2 1

VDDC CORE VOLTAGE (1.1V)

3A 120mils (3.6A max) 3.3V_SB
Standby Power 3.3V VCC3.3VA_AG1

C64 C65 C66 C67 C68 C69 C70 1A 30mils (155mA max)
22u/6.3VV 22u/6.3VV 100n/10V 4.7u/6.3VV 4.7u/6.3VV 4.7u/6.3VV 4.7u/6.3VV Q2 G5 G6
C71 C72 C73 C74

NC1
NC2
RSAG7.308.0317/NC VCC3.3VA_AG2
SMR SMR
10u/6.3VV 100n/10V 100n/10V 100n/10V
D AVDDL_DVI D

1
2
Add heat sink Add conductive foam C75 C76

10u/6.3VV 100n/10V
C77
3.3V Standby Power Req'd AVDD_DMPLL
100n/10V
DVDD
ETH + AVDD_NODIE= PINs L7 + L4
AU33 = PIN T6 AVDD_AU
ADC = PIN L5 C78
USB/DVI = PINs U6 + V6 + L13 C80 100n/10V
C79 DMPLL = PIN L8
100n/10V 100n/10V
DADC = PIN L6
Some 0 Ohm resistors in power supply
Normal Power 3.3V may be ommited in space-constrained
VCC3.3V VCC3.3V_AG PCB layout. However, capacitor DDR3 POWER (Standby)
1A 30mils (90mA max) placement is crucial to design success. VCC1.5V AVDD-DDR

C C81 C82 C83 2A 40mils (325mA max) C

AVDD_MOD 10u/6.3VV 100n/10V 100n/10V
C84 C85 C87 C89
C86 C88 C90 C91
DDR Refernce Voltage 4.7u/10V 4.7u/10V 100n/10V
10u/6.3V 100n/10V 100n/10V
K11 = ref to GND 100n/10V 100n/10V
C92 M11 = ref to PWR
100n/10V 1.5V Standby Power Req'd
C93

2.2u/6.3VV
AVDD-DDR
Standby Power AVDD_DDR0 = PIN L12 + M12
AVDD_DDR1 = PIN K12 + J12
C94
AVDD_DMPLL
AVDD_AU 100n/10V

VCC3.3VA_AG2 AVDD-DDR DVDD AVDDL_DVI VDDC

AVDD_MOD
VCC3.3V_AG VCC3.3VA_AG1 C95
Caps* 1u/16V
*Must place at Pins N12, N13
AVDD-DDR
B B
M11

M12
H15

N13
N12
P15

K11

K12

K13

K18

K17
K16
K15
K14
L12

L13

L18
L17
L16
L15
L14
J16
J17

J12

J13

J15
J14
W8

H4

H5

H7
H6

U6

U5
V6

V5
T6

L8
L7
L6
L5
L4
J8

N1F C269
AVDD33_USB
AVDD33_USB

AVDD_NODIE

VDDIO_DRAM
VDDIO_DRAM

DVDD_DDR_B
DVDD_DDR_A

AVDDL_DVI

DVDD_NODIE
DVDD_NODIE
NC-P15
NC-J16
NC-J17
NC-H15
GND

VDDP3318

AVDD_PLL
AVDD_5V_HDMI_C

AVDD33_DMPLL
AVDD_MOD
AVDD_MOD

AVDD33_AU

AVDD33_DADC
AVDD33_ADC

AVDD11_DDR

AVDD04_DDR

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDDC
VDDC
VDDC
VDDC

VDDC
VDDC
AVDD33_ETH

AVDD_DDR1_D
AVDD_DDR1_C

AVDD_DDR0_D
AVDD_DDR0_C
MSDFRX1603 C275
100n/10V 10u/25V

G1 G2

00
SMR SMR
Q1

NC1
NC2
RSAG7.308.0300

79
G3 G4

1
2
SMR SMR
Add heat sink

A A
GND
GND
GND

GND
GND
GND
GND
GND
GND

GND
GND
GND

GND

GND

GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND

GND
GND
GND

GND
GND
GND
GND

GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND

GND

GND

GND

GND
Add conductive foam

t:
Roku, Inc. Confidential
A13
A15
A18

B12
B14
B16
B17
B19
B20

C9
C10
C21

D9

E20

F9
F11
F13
F15
F17
F19
F21

G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18

H9
H10
H11
H12
H13
H14
H18

J9
J10
J11

K4
K8
K9
K10

L9
L10
L11

M9
M10
M13
M14
M15
M16
M17
M18

N9
N10
N11
N14
N15
N16
N17
N18

P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14

R7
R8
R9
R11
R12
R13

V3

W6

Y2

AA20
ui Title

Size
SoC Power/GND
Document Number Rev
B C1
rc
Midland (FHD), Roku-PN 0002001435
Date: Thursday, November 30, 2017 Sheet 10 of 20
5 4 3 2 1
ci
d
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in
ma
 5 4 3 2 1

3.3V_SB
N1D

(Backlight_DIM)
18 SOC-BL_PDIM G21
PWM0 LVDS Block

PWM
G19
13 HP_DET PWM1
R159 G20
1k
PWM2 Route 100 Ohm Differential Pairs
1% 9 LED_PWM_ONn
(Config) PWM_PM E9
(LED_PWM) PWM_PM R19
D LVA0P LVA0_N 12 D
R160 10R SAR0 = 5 Key (Power, CH-, CH+, VOL-, VOL+) R411 1k SAR0 C4 R20
9 KEY0 SAR0 LVA0N LVA0_P 12

SAR
A4 R21 LVA1_N 12
VCC12V SAR2 B4 SAR1 LVA1P T19
12 Panel_ON-P1 SAR2 LVA1N LVA1_P 12
(Backlight_ON) F8 T21 LVA2_N 12
4 RST_BTNn SAR3/PM_SPI_CZ LVA2P
C96 SAR5 D6 T20 LVA2_P 12
PWR_DETECT LVA2N U19
LVACKP LVACK_N 12
R163 100n/16V R164 33R (Config) SPI_SDI A2 U20
8 WIFI_REG_ON PM_SPI_DI LVACKN LVACK_P 12
V19 LVA3_N 12
10k LVA3P V20
1% UART-RX E7 Standby GPIO LVA3N V21
LVA3_P 12
LVA4_N 12
7 DDCR_CK UART-TX E8 DDCA_CK LVA4P W19

LVDS
DDCA_DA LVA4N LVA4_P 12
Adjust for 1V nominal R155 = 10K, C97 = NC (PANEL I2C) DDCR_CK P17 K21
R165 9,12 I2C-SCL-P R176 33R LVB0_N 12
set point based on if SAR1 is not used (JTAG) R177 33R DDCR_DA P16 DDCR_CK LVB0P K20
1k 9,12 I2C-SDA-P DDCR_DA LVB0N LVB0_P 12
1% main supply voltage (IR/LED)
LVB1P
L19 LVB1_N 12

GPIO
3.3V_SB 7 DDCR_DA UART-RX2 H17 L20
UART_RX2 LVB1N LVB1_P 12
Setpoint_1V R168 0R SAR5 Used for A/V Mute and NAND WP during power fail R153 10k UART-TX2 H16 M19 LVB2_N 12
UART_TX2 LVB2P M20
1% LVB2N LVB2_P 12
(Config) GPIO_PM0 G4 M21
GPIO10 LVBCKP LVBCK_N 12
C98 PM_TX B3 N19 LVBCK_P 12
GPIO11/PM_UART_TX LVBCKN
2

R169 330p/50V B1 N21

17,19 AUX_PWR_ON GPIO14 LVB3P LVB3_N 12
1k VZ1 PM_RX B2 N20
1% GPIO15/PM_UART_RX LVB3N LVB3_P 12
BZT52C5V6 4 RST_INHn
(Config) GPIO_PM7 D8 P19 LVB4_N 12
D7 GPIO17 LVB4P P20
C 8 WAKE_ON_WIFIn R174 33R LVB4_P 12 C
GPIO20 LVB4N
PLACE CLOSE TO PIN
1

B7
VID1 A7 VID0
R175 33R
SoC ADC Pin Protection
8 HOST_WAKE_WL VID1 Standby GPIO Note: LVDS swapped
- Must be Populated - 4 RST_LATCH_CLRn W_I2CS_SDA
W_I2CS_SCL
T3
T1 GPIO217 - improve PCB routing.
4 RST_BTNn_LATCH GPIO218

3.3V_SB MSDFRX1603
(STANDBY) 3.3V_SB
XP4
PM_UART
1 R180 33R R490 R491
VCC3.3V

2 4.7k 4.7k
3 R179 33R PM_RX STANDBY GPIO
IC Configuration Selection 4 R178 33R PM_TX
R202 R203
Use P8 Connector for
Set to 3'b011 access to all debug
6
5

3.3V_SB 2.2k 2.2k (AUDIO AMP)

HX2.0-PH-4AB information including
PM51 I2C Address = 0x55 / 0x54
WIFI_REG_ON (SPI_SDI) Pull-Down = R182
SPI_SDI 3.3V_SB DDCR_CK R57 33R
R181 NC/4.7k R182 4.7k XP5 Debug port 3.3V_SB DDCR_DA R59 33R
AMP_I2C_SCL 13
AMP_I2C_SDA 13
B (MSTV Tool) R492 R493
B
RST_INHn (GPIO_PM7) Pull-Up = R183 1 R189 33R
GPIO_PM7 2 4.7k 4.7k
R183 4.7k R184 NC/4.7k 3 R188 33R UART-RX
4 R185 33R UART-TX
LED_PWM_ONn (PWM_PM) Pull-Up = R186
PWM_PM
6
5

R186 4.7k R187 NC/4.7k HX2.0-PH-4AB

CHIP_CONFIG[2:0] VCC3.3V
{SPI_DI, GPIO_PM7, PWM_PM}
VCC3.3V
XP6
3'b000 PM51 boot from SPI
3'b001 ARM boot from SPI
UART2
1 R192 33R R494 R495
3'b010 ARM boot from ROM, storage is eMMC 2 4.7k 4.7k
3'b011 ARM boot from ROM, storage is NAND 3

00
R191 33R UART-RX2
3'b100 Test Only 4 R190 33R UART-TX2
3'b101 ARM boot from non-PM SPI
3'b110 ARM boot from ROM, storage is eMMC
6
5

PM51 boot from SPI when PM power is ON 3.3V_SB

79
3'b111 ARM boot from ROM, storage is NAND HX2.0-PH-4AB
PM51 boot from SPI when PM power is ON
3.3V_SB R195 R196
XP7 3.3V_SB
A GPIO_PM0 NC/2.2k A
NC/2.2k

t:
R193 4.7k R194 NC/4.7k 1
2
CHIP_CONFIG[3] = GPIO_PM0
1'b0 Enable Authentication
3
4
W_I2CS_SCL
W_I2CS_SDA Roku, Inc. Confidential
1'b1 No Authentication
ui Title
GPIO / LVDS
6
5

HX2.0-PH-4AB Size Document Number Rev

Place group together B C1
rc
EVT/DVT for only Midland (FHD), Roku-PN 0002001435
Date: Thursday, November 30, 2017 Sheet 11 of 20
5 4 3 2 1
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 5 4 3 2 1

Note: Confirm that FET can handle panel current.

Note: If 5V is supplied to panel, 5V regulator must change to supply additional current
VCC5V L3
BLM18PG121SN1/NC
4.2A--(Vgs=-10v) LVDSVDD
Panel-V
L4
BLM18PG121SN1/NC 2 3
V8
D C286 R414 D
C99 AO3401L
VCC12V L5 C101 C103

1
BLM18PG121SN1 100n/25V 2.2u/10V 56k
L6 BLM18PG121SN1

C287
100n/25V 10u/25V

XP20
FHD
100n/16V/NC
R199 1
for 43" panel:T430HVN01.7,some components value as below: LVDSVDD
VCC1 56k CL2: 0.22uF/16V 2
CL1: 10uF/16V 3
CL3: 10nF/50V
LVDS POWER Control 4

3
RL3: 150K 5 L42 BLM15PX121SN1D/NC
R200 1 RL4: 150K
11 Panel_ON-P1 V9 6
RL2: 4.7K
10k MMBT3904LT1 7
Hi: On R201 8

2
9 R456 0R
VCC12V Lo: Off 10k
10 PIN10 LVA4_N 11
1% 11 PIN11 R463 0R/NC
12 LVA4_N_1 R457 0R/NCLVA4_N TX4AN 0R/NC TCON_SDA
C289 C288 PIN10 R464
VCC3.3V 13 LVA3_P
C290 VCC3.3V 14 LVA3_N 0R/NCTCON_SCL
100u/16V/NC 100n/16V/NC 1u/16V/NC Reserve for V-com adjustment function 15
R465
0R/NC LVA4_P
C PANEL LVDS TX Connectors R439 AI/WP
16
17
LVACK_P
LVACK_N
R466
PIN11 LVA4_P_1
LVA4_P 11
TX4AP C

R436 4.7k 18
19 LVA2_P SAM屏预留8bit
4.7k R435 0R/NC AI/WP 20 LVA2_N LVB4_P R467 1.5k/NC
VCC3.3V
21 LVA1_P
LVA4_P R468 1.5k/NC
22 LVA1_N

3
VCC_P R437
R440 23 LVA0_P VCC3.3V
LVDSVDD 4.7k 1
31
32

PNL_WPn
R84 5 0R/NC 24 LVA0_N LVB4_P 11 LVB4_N R469 1.5k/NC
30 V13 25 R458 0R
4.7k/NC TX4BP R470
C298 LVA4_N 1.5k/NC

2
29 26 R459 0R
HD 28 SEL 100n/16V/NC MMBT3904LT1
27
28
LVB4_P_1
LVB4_N_1
R460
R461
0R/NC LVB4_P
0R/NC LVB4_N
LVB4_N 11
27 PIN47 R471 0R/NC TCON_SCL
26 29 LVB3_P TX3BP TX4BN
25 R415 30 LVB3_N LVB3_P 11 LVB3_N 11
31 TX3BN
24 0R LVBCK_P 11
23 32 LVBCK_P TXCKBP LVBCK_N 11
SEL 22 TCON_SCL 33 LVBCK_N
SEL R419 0R/NC 34 TXCKBN PIN48 R472 0R/NC TCON_SDA
21 TX2BP
TX0AN 20 35 LVB2_P LVB2_P 11 LVB2_N 11 0R/NC TCON_SCL
36
R473
11 LVA0_N 19 I2C-SCL-P 3 2 TCON_SCL LVB2_N
7,9,11 I2C-SCL-P TX2BN R474 0R/NC TCON_SDA
11 LVA0_P 18 37 LVB1_P TX1BP
TX0AP 38 LVB1_N
17 V11 LVB1_P 11 PIN49 R475 0R/NC AI/WP
TX1AN 16 2N7002K 39 LVB0_P
11 LVA1_N R483 0R/NC TCON_SCL LVB1_N 11 TX1BN
B 15 40 LVB0_N R476 0R/NC TCON_SDA B
11 LVA1_P TX0BP

1
TX1AP 14 41
PIN4 R484 0R AI/WP PIN50 R477 0R/NC TCON_SCL
11 LVA2_N 13 42 LVB0_P 11
TX2AN 43 TX0BN
11 LVA2_P 12 R485 0R TCON_SCL
TX2AP 11 TCON_SDA 44 LVB0_N 11
R417 0R/NC 45 SEL
11 LVACK_N 10 R486
TXCKAN PIN2 0R/NC AI/WP 46
11 LVACK_P 9
TXCKAP 8 47 PIN47
I2C-SDA-P 3 2 TCON_SDA
11 LVA3_N 7 7,9,11 I2C-SDA-P 48 PIN48
TX3AN 49 PIN49
11 LVA3_P 6 V10
5 50 PIN50
TX3AP 2N7002K LVDSVDD
PIN4 4 51 R462 AI/WP
1

TCON_SDA 3 0R/NC
PIN2 2

53
52

00
1 R416 HX0.5-1x51AW-JD/NC
10k
XP8

79
C297 R418 LVDS PORT
2.2u/10VV/NC 10k

A S5 S1 S6 A

t:
M5 M6
M1 M2 M3 M4
Roku, Inc. Confidential
D4 D4 D4
MARK MARK MARK MARK MARK MARK ui Title

Size
PANEL Interface (LVDS)
Document Number Rev
B C1
rc
Midland (FHD), Roku-PN 0002001435
Date: Thursday, November 30, 2017 Sheet 12 of 20
5 4 3 2 1
ci
d
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ma
 5 4 3 2 1
VCCA
AMP_PWR AMP_PWR
VCC12V
L41

Header for AQ/TI GUI XP10 HX2.0-PH-8AB STPB2012-121PT

10 C107 C108 220u/25V 220u/25V
9 C111
N14 100n/50V 100n/50V C109 C110 R213

1
2
3
4
5
6
7
8
18R/NC
4 330p/50V/NC
I2S_MCLK VCC3.3V 21 PVDD 41
D 7 AUMCK_OUT MCLK PVDD D
I2S_SCLK 27 Rated 50V L11
7 AUBCK_OUT SCLK L+
I2S_LRCLK 26
7 AUWS_OUT LRCLK C112 33n/50V 22.0 uH
I2S_SDIN 28 3 C113
7 AUSD_OUT SDIN BSTRPA Sat = 1.9A C118
2 LOUT+
NC/10p/50V

NC/10p/50V

NC/10p/50V

NC/10p/50V
SPK_OUTA Tem = 1.5A 330n/50VV
C114 C115 C116 C117 48 LOUT- 330n/50VV
SPK_OUTB 47 C119 33n/50V
BSTRPB
L12
L-
46 C120 33n/50V 22.0 uH
BSTRPC 45 ROUT+ Sat = 1.9A
SPK_OUTC C121
30 43 ROUT- Tem = 1.5A
11 AMP_I2C_SCL SCL SPK_OUTD C122 33n/50V
42 C123 330n/50VV
29
I2C Address = 1010101 BSTRPD R216
11 AMP_I2C_SDA SDA
18R/NC
32

5
6
5 AUDIO_RSTn 330p/50V/NC
/RST
VCC3.3V R217 4.7k R+ 4
R219 C125
L33 C124 2.2u/10V R220 R- 3
34 7 R218 0R HP_Audio-L 7 L- 2
DVDD DR_INA
BLM18PG121SN1 18R/NC L+ 1 XP16
14 10k 1%
330p/50V/NC
C132
10u/6.3V
C133
100n/16V 19
DRVDD
TAS5753MD C126
R221
10k
AVDD 1u/16V/NC L13
C130 VCC3.3V 1% R+
C131
C 22.0 uH C
10u/6.3V 100n/16V L15 3.3VA_AMP 8 R222 0R HPAOL Sat = 1.9A
DR_OUTA
BLM18PG121SN1 Tem = 1.5A
10 R223 0R C135 C136
VCC3.3V DR_INB
C128 C129 R224 C134 330n/50VV 330n/50VV
2.2u/10V
HP_Audio-R 7
10u/6.3V 100n/16V L14
C137 10k 1% R-
R225 R226
1u/16V/NC 10k 22.0 uH
15k Sat = 1.9A
1%
20 9 R227 0R HPAOR Tem = 1.5A C139 C138
ADR / SPK_FAULT DR_OUTB R228 330n/50VV
39
5 HP-MUTEn /DR_SDI 18R/NC
C140 1u/16V 330p/50V/NC
5 AMP_MUTEn 25 12
/PDN DR_CN
R229 R230 18
ANA_REG1 13
C141 DR_CP
C142
4.7k 4.7k 38 R231 0R HPL_TIP
47n/16V PLL_FLTP 17 SSTIMER
4.7n/50V

ASES12U020R2/NC
PLL_FLTP 22
R232 OSC_RES

GAP8
PLL_FLTM 16
PLL_FLTM 24
470R DIG_REG

RV10
B 37 B
ANA_REG2 40 R233
Thermal Pad

GVDD_REG
OSC_GND

PLL_GND

C144 18k
C143 C333 C145 HP

TEST3

TEST2

TEST1
DGND

PGND
PGND

AGND
11 1u/16V 4.7u/16VV 100n/16V 1% 2.2n/50V
DRVSS HPR_TIP OUT
NC
R234 0R
C147 C148 XS4

ASES12U020R2/NC
GAP9
2
49

35

23

15

1
44

36

31

33

5
47n/16V C146 R
4.7n/50V
VCC3.3V

RV11
1u/16V 1 L
4
R235 3 SW
470R C149 GND
R447
100n/16V
4.7k

00
R448 100R HPJ_DET
11 HP_DET
C302 GAP12

79
Follow TI Layout Recommendations. 100n/16V

A
NOTES: 1 = Headphone installed A

t:
0 = No Headphones
* Do not place Core Regulator close to TAS5753 if possible
* Core Voltage GND return path and filter capacitor placement is crucial Roku, Inc. Confidential
* Poor GND implementation may result in noise on Audio and Headphones ui Title

Size
Audio Amp & Headphone Jack
Document Number Rev
B C1
rc
Midland (FHD), Roku-PN 0002001435
Date: Friday, December 01, 2017 Sheet 13 of 20
5 4 3 2 1
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 5 4 3 2 1

VD5
HDMI 1 HDMI-0-SDA
HDMI-0-SCL
R254
R255
100R
100R HDMI0-SDA 7 HDMI0_CLKN 1
IN1
10 HDMI0_CLKN
Hot-Plug Control
HDMI Connector w/ ARC HDMI0-SCL 7

ASES12U020R2/NC

ASES12U020R2/NC

ASES12U020R2/NC
HDMI0_CLKP 2 9 HDMI0_CLKP
DC1R019JB1 R257 IN2 HDMI0-5V
R256 47k 3 8
XS5 47k GND

RV14

RV13

RV12
1%
19 HDMI0_HPDIN 1% HDMI0_RX0N 4 7 HDMI0_RX0N
HPDET 18 HDMI0-5V HDMI0-5V IN3
+5V_17 RV16 C281
17 HDMI0-5V HDMI0_RX0P 5 6 HDMI0_RX0P R258 R259
CEC/GND_16 16 HDMI-0-SDA IN4 100n/10V
D SDA 1k 10k D
15 HDMI-0-SCL ASES12U020R2/NC
SCL 14 HDMI-C_ARC 1% 1%
NC HDMI-C_ARC 7 R260 TPD4E02B04DQAR
13 HDMI0_CEC R261 0RHDMIX_CEC HDMI-CEC 7
CEC 12 HDMI0_CLKN R262 0R HDMI0-CLKN HDMI0-CLKN 7 200R HDMI0_HPDIN
CLK-_11 11 VD6

ASES12U020R2/NC
CLKS V14

3
10 HDMI0_CLKP R264 0R HDMI0-CLKP HDMI0_RX1N 1 10 HDMI0_RX1N
CLK+_9 HDMI0-CLKP 7
9 HDMI0_RX0N R265 0R HDMI0-RX0N IN1 1 R263 10k
DATA0-_8 HDMI0-RX0N 7 HDMI0-HPDIN 7

RV15
8 HDMI0_RX1P 2 9 HDMI0_RX1P 1%
DATA0S HDMI0-5V IN2 MMBT3904LT1
7 HDMI0_RX0P R266 0R HDMI0-RX0P HDMI0-RX0P 7

2
DATA0+_6 6 HDMI0_RX1N R267 0R HDMI0-RX1N HDMI0-RX1N 7 R389 3 8
DATA1-_5 5 GND
DATA1S 4 HDMI0_RX1P R268 0R HDMI0-RX1P HDMI0-RX1P 7 10k HDMI0_RX2N 4 7 HDMI0_RX2N
DATA1+_3 3 HDMI0_RX2N R269 IN3
0R HDMI0-RX2N HDMI0-RX2N 7 ARC_DET 7
DATA2-_2
GND1
GND2
GND3
GND4

2 HDMI0_RX2P 5 6 HDMI0_RX2P
DATA2S R390 IN4
1 HDMI0_RX2P R270 0R HDMI0-RX2P HDMI0-RX2P 7
DATA2+_0
22.1k
20
21
22
23

TPD4E02B04DQAR

VD7
HDMI 2 HDMI-2-SDA R238 100R
HDMI2_CLKN 1
IN1
10 HDMI2_CLKN
C
HDMI DC1R019JB1
Connector HDMI-2-SCL R239 100R HDMI2-SDA
HDMI2-SCL
7
7
HDMI2_CLKP 2
IN2
9 HDMI2_CLKP HDMI2-5V C

ASES12U020R2/NC

ASES12U020R2/NC

ASES12U020R2/NC
3 8
XS6 GND
R240 R241
47k 47k HDMI2_RX0N 4 7 HDMI2_RX0N
RV17

RV18

RV19
19 HDMI2_HPDIN C282
HPDET IN3 R242
18 HDMI2-5V HDMI2-5V 1% 1%
+5V_17 17 HDMI2_RX0P 5 6 HDMI2_RX0P 1k 100n/10V R243
CEC/GND_16 16
RV21 IN4 1%
HDMI-2-SDA HDMI2-5V 10k
SDA 15 HDMI-2-SCL
SCL 14 HDMI2_HPDIN 1%
NC ASES12U020R2/NC TPD4E02B04DQAR
13 HDMI2_CEC R244 0R HDMIX_CEC
CEC V15

3
12 HDMI2_CLKN R245 0R HDMI2-CLKN
CLK-_11 HDMI2-CLKN 7 VD8
11 1 R246 10k

ASES12U020R2/NC
CLKS HDMI2-HPDIN 7
10 HDMI2_CLKP R247 0R HDMI2-CLKP HDMI2-CLKP 7 HDMI2_RX1N 1 10 HDMI2_RX1N 1%
CLK+_9 IN1 MMBT3904LT1
9 HDMI2_RX0N R248 0R HDMI2-RX0N HDMI2-RX0N 7

2
DATA0-_8
RV20
8 HDMI2_RX1P 2 9 HDMI2_RX1P
DATA0S 7 HDMI2_RX0P R249 IN2
0R HDMI2-RX0P HDMI2-RX0P 7
DATA0+_6 6 HDMI2_RX1N R250 HDMI2-5V
0R HDMI2-RX1N HDMI2-RX1N 7 3 8
DATA1-_5 5 GND
DATA1S 4 HDMI2_RX1P R251 R383
0R HDMI2-RX1P HDMI2-RX1P 7 HDMI2_RX2N 4 7 HDMI2_RX2N
DATA1+_3 3 HDMI2_RX2N R252 IN3
0R HDMI2-RX2N HDMI2-RX2N 7 5.6k
DATA2-_2
GND1
GND2
GND3
GND4

2 HDMI2_RX2P 5 6 HDMI2_RX2P
DATA2S HDMI2_DET 5 IN4
1 HDMI2_RX2P R253 0R HDMI2-RX2P HDMI2-RX2P 7
DATA2+_0 R384
B B
10k
20
21
22
23

TPD4E02B04DQAR

VD9

HDMI 3 HDMI-3-SDA R271 100R

HDMI3_CLKN 1
IN1
10 HDMI3_CLKN HDMI3-5V

HDMI DC1R019JB1
Connector HDMI-3-SCL R272 100R HDMI3-SDA
HDMI3-SCL
7
7
HDMI3_CLKP 2
IN2
9 HDMI3_CLKP
ASES12U020R2/NC

ASES12U020R2/NC

ASES12U020R2/NC

C283 R276
3 8 R275
XS7 GND
1k 100n/10V 10k
19 R273 R274 HDMI3_RX0N 4 7 HDMI3_RX0N
RV30

RV22

RV23

HDMI3_HPDIN IN3 1% 1%
HPDET 18 HDMI3-5V HDMI3-5V 47k 47k

00
+5V_17 17 1% 1% RV25 HDMI3_RX0P 5 6 HDMI3_RX0P HDMI3_HPDIN
CEC/GND_16 IN4
16 HDMI-3-SDA HDMI3-5V
SDA V16

3
15 HDMI-3-SCL
SCL 14 TPD4E02B04DQAR 1 R279 10k
ASES12U020R2/NC HDMI3-HPDIN 7

79
NC 13 HDMI3_CEC R277 0R HDMIX_CEC MMBT3904LT1 1%
CEC 12 HDMI3_CLKN VD10
R278 0R HDMI3-CLKN HDMI3-CLKN 7

2
CLK-_11 11
ASES12U020R2/NC

CLKS HDMI3_RX1N 1 10 HDMI3_RX1N

10 HDMI3_CLKP R280 0R HDMI3-CLKP IN1
CLK+_9 HDMI3-CLKP 7
9 HDMI3_RX0N R281 0R HDMI3-RX0N HDMI3_RX1P 2 9 HDMI3_RX1P
DATA0-_8 HDMI3-RX0N 7 IN2
RV24

A 8 A
DATA0S

t:
7 HDMI3_RX0P R282 0R HDMI3-RX0P HDMI3-5V 3 8
DATA0+_6 HDMI3-RX0P 7 GND
6 HDMI3_RX1N R283 0R HDMI3-RX1N HDMI3-RX1N 7
DATA1-_5 5 R455
HDMI3_RX2N 4 7 HDMI3_RX2N
DATA1S
DATA1+_3
4 HDMI3_RX1P R284 0R HDMI3-RX1P HDMI3-RX1P 7 5.6k
IN3 Roku, Inc. Confidential
DATA2-_2
3 HDMI3_RX2N R285 0R HDMI3-RX2N HDMI3-RX2N 7 HDMI3_DET 5 ui
HDMI3_RX2P 5
IN4
6 HDMI3_RX2P Title
GND1
GND2
GND3
GND4

2 HDMI Connectors
DATA2S R392
1 HDMI3_RX2P R286 0R HDMI3-RX2P HDMI3-RX2P 7
DATA2+_0 TPD4E02B04DQAR Size Document Number Rev
10k
B C1
rc
Midland (FHD), Roku-PN 0002001435
20
21
22
23

Date: Thursday, November 30, 2017 Sheet 14 of 20

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 5 4 3 2 1

Si2151 Tuner = NTSC, PAL/SECAM, ATSC/QAM, DVB-T2/T/C2/C,ISDB-T/C, DTMB

3.3V_TUNER
Tuner RF Shield
U8
RF_IN 1
C151 C152 RF_IN
100n/16V 1n/50V 2 7
GND GND

GND

GND

GND
D D
6
As close as possible to pin-7 TUNER_1_8V GND
Tuner RF Shield C153 C154 TUNER_1.8V

5
U9 100n/16V 1n/50V
FG053-F01T1NY-A\Reflow C155 C156 C157
1n/50V L16 1n/50V 1u/10V
0.27 uH Place 5mm from to pin-17 TUNER_SHIELD_LIBERTY
5 C158 C159
GND 4
GND 3 1n/50V 100n/16V
GND L17
RF_IN

17

15
GND

7
0.27 uH N8
R430

+3.3V

+3.3V

+3.3V

+1.8V
C160 39p/50V 19 DIF+ C163 C161
R429
1

RF_REF DIF+120p/50V/NC
75 ohm Line 0R TIN_P 5
20
RF_IN C162 47p/50V
\/ R287 0R RF_IP R-RESC1608N-HX 0R 100n/16V
C165 39p/50V 22 L8 C166 R-RESC1608N-HX
RF_IN
18 0.1 uH/NC 120p/50V/NC C167
R442
3

L7 NC 11 R288 200R IF_OUT+ DIF- IN-

LIF_P R441 TIN_M 5
VD3 0.18 uH DIF-
C BAV99LT1 R289 200R 0R 100n/16V C
GAP11

Z2 10 IF_OUT-
L9 L18 4 1 13 LIF_N 0R R-RESC1608N-HX
GND X1 XTAL_I/RCLK R-RESC1608N-HX C170
0.27 uH 0.27 uH Place Close
C164 3 2 14 C169 120p/50V/NC
C168 to MStar SoC
1

X2 GND XTAL_O
180p/50VV 33p/50V 33p/50V

L19 8Z24000016
Xtal Requirements I2C Address = 0xC0 / 0xC1
0.27 uH 24Mhz +/- 25ppm
CL=8pF
24
GPIO1
1 AGC1
GPIO2 4
AGC2
5 IFAGC_T R292 100R
AGC1

5 TUNER_I2C_SCL 3 C171
SCL
100n/16V
2
5 TUNER_I2C_SDA SDA XOUT Place

GND_EPAD
C172
B C173 23 12 Close to B
ADDR XOUT
47p/50V
47p/50V
tuner

GND

GND

GND

GND
Si2151
6

16

21

25
3.3V_TUNER

0.250A
C174
100n/16V R295

00
10k
3.3V_TUNER R297
VCC5V N9 5 IFAGC

79
TLV70233DBVR 0R
C176
1 5 Place Close
VIN VOUT 22n/25V
to MST chip
C175 C177
GND

A 1u/16V 3 4 1u/16V R297 value will change if AGC signal in PWM A

EN NC

t:
C178
2

100n/16V
Roku, Inc. Confidential
Tuner Power Regulator 3.3V @ 300mA
ui Title

Size
ATSC TUNER
Document Number Rev
B C1
rc
Midland (FHD), Roku-PN 0002001435
Date: Thursday, November 30, 2017 Sheet 15 of 20
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 5 4 3 2 1

DDR Voltage Regulator 1.5V @ 1.5A

3.3V_SB Imax Saturation = 4.0A
Imax Temperature = 2.6A

N10
1 1.5V_PWR_GOOD 4 REG_1V5 VCC1.5V
D PGOOD D
C179
L10 (1.5V @ 1A)
4
VIN SW
3 DDR Imax ~ 600mA
C180
100n/16V 2.2 uH
10u/6.3VV
R398 C182
C183 C184
2 5 15k
GND FB 22u/6.3VV/NC
1% 22u/6.3VV 22u/6.3VV

TLV62566DBVR\Roku
TLV62568P = 2.5V to 5.5V, 1A Max R401
TLV62566 = 2.5V to 5.5V, 1.5A Max Vout = 0.6( 1 + Rt/Rb ) 10k
TLV62569P = 2.5V to 5.5V, 2A Max Rtop = Rbot * (Vout-0.6v)/0.6V 1%
Rbot = 0.6*Rtop/(Vout - 0.6v)

VCC1.5V
AVDD_DDR1

L20 Close to DDR POWER PIN

BLM31PG121SN1
C186 C187 C299 C300 C188 C189 C190 C191 C192 C193 C194 C195 C196 C197 C198 C199 C200 C201 C202 C203 C204 C205 C206 C207 C208
22u/6.3VV 22u/6.3VV 22u/6.3VV 22u/6.3VV 10u/6.3VV 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V 100n/10V
C C

Follow TI Layout Recommendations.

AVDD_DDR1
C334 C335 C336 C337 C338 C339 C340 C341 C342 C343 C344
100n/10V
SOC_RESET requirement 100n/10V 100n/10V100n/10V
100n/10V100n/10V
100n/10V100n/10V 100n/10V 100n/10V 100n/10V

VDDC 2ms after 1.5V stable.

Core Voltage Regulator 1.1V @ 4A
(MStar recommends 4A)

1.5V_PWR_GOOD R487 47k PWR_EN_3 EN > 1.18V to turn on

R488 C346 N11
CORE_PWR_GOOD 4 VDDC
220n/10V 9
47k PG V_CORE
8 L21 VDDC Imax = 3.6A
EN 2
VCC5V SW 11
B 0.9 uH B
SW C210 C213 C322
Imax Saturation = 13A C211 C212
1 C216
PVIN Imax Temperature = 7.8A
10 6 22u/6.3VV 22u/6.3VV22u/6.3VV NC/10u/6.3V 22u/6.3VV 22u/6.3VV
VIN OUT
C214 C215
7
10u/10VV 10u/10VV FB C321
10n/10V/NC
VDDC
AGND

PGND
PGND

5
NC R308
Vout = 0.6( 1 + Rt/Rb )
Rtop = Rbot * (Vout-0.6v)/0.6V 91k 1%
(Must sense at load,

00
MP2131DG
4

3
12

Rbot = 0.6*Rtop/(Vout - 0.6v)

R311 Place R308 at SoC)
18k
1%

79
VID0 control NC. NOTES:
VDDC always 1.1V R315 * Do not place Core Regulator close to TAS5753 if possible
91k
A
1% * Core Voltage GND return path and filter capacitor placement is crucial A

t:
* Poor GND implementation may result in noise on Audio and Headphones
MStar recommends fixed 1.1V -- measure at SoC Roku, Inc. Confidential
Follow TI Layout Recommendations. ui Title

Size
Core_Power, DDR_Power
Document Number Rev
B C1
rc
Midland (FHD), Roku-PN 0002001435
Date: Monday, December 25, 2017 Sheet 16 of 20
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 5 4 3 2 1

D D

Standby Power 3.3V

R321
R324 N12 1A for WiFi 3.3V_SB
4 R320 10R
24.9k BOOT L22
VCC12V
100k 1% 5 C220
EN
1u/16V
2 4.7 uH
1 SW C224
R443 C222 C223 C228
VIN C221
40.2k 10p/50V 22u/6.3VV 22u/6.3VV 22u/6.3VV 22u/6.3VV
1%
R322
3 6
GND FB
C225 20k 1%
C226 C227 MP1658GTF
R323
100n/25V 10u/25V 10u/25V
Standby Requirement, 88% Efficient @ 60mA 12.4k
1% 4.5V to 28V input stage, 3A output FETs.
C Iout max requirement ~3A Vout = 0.807 ( 1 + Rt/Rb ) C
Rtop = Rbot * (Vout-0.807v)/0.0.807V
Rbot = Rtop *0.807/(Vout-0.807)

Power 5V
N13
VCC5V
4 R330 10R
BOOT L23
VCC12V
11,19 AUX_PWR_ON 5 C301
EN
1u/16V
2 4.7 uH
1 SW
VIN R445 C240 C239 C231 C232 C233
40.2k 10p/50V 22u/6.3VV 22u/6.3VV 22u/6.3VV 22u/6.3VV
R331 1%
3 6
B GND FB B
C236 C238 24.9k R444
C237
MP1658GTF 1% 5.1k
100n/25V 10u/25V 10u/25V
Iout max requirement ~3A
1% Rbot = 0.807*Rtop/(Vout - 0.807v)
(supports 1 USB Port)
R454 Set to 5.25V for USB Drop
2.2k
1%

Normal Power 3.3V

00
3.3V_SB V12
AO3401L VCC3.3V

2 3

79
C241 C242
R332
100n/10V 22n/50V

1
4.7k
R334
A A
R333

t:
24k 1k
R335 1% Roku, Inc. Confidential
3

11,19 AUX_PWR_ON AUX_PWR_ON 1

C345
V18
MMBT3904LT1 ui Title
DC-DC Regulators, 5V/3.3V_SB/3.3V
2

47k NC/100n/10V Size Document Number Rev

B C1
rc
Midland (FHD), Roku-PN 0002001435
Date: Thursday, November 30, 2017 Sheet 17 of 20
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 5 4 3 2 1

D D

Panel Backlight DIM Control

VCC3.3V VCC3.3V

R340 R446
NC/4.7k NC/1k
Panel Backlight Primary DIM Control

11 R344 R343 1k
SOC-BL_PDIM R342 0R BL_PDIM 19
100R

3
R345 1 V20 C247
NC/MMBT3904LT1 100n/16V
NC/4.7k

2
C R346 C
4.7k

Backlight Control
VCC3.3V VCC3.3V

DIM: 0=off, 1= all the way on

R347 R348 ON: Vin>2.0V, off: Vin<.8V
NC/4.7k NC/1k
Panel Backlight ON/OFF Control
R349 R350 1k
Hi: Off BKL_EN 19
Lo: On 100R

3
R352 1 C296
5 SOC-BL_ON R351 0R V19
B NC/MMBT3904LT1 100n/16V B
NC/4.7k

2
R353
4.7k

00
79
A A

t:
Roku, Inc. Confidential
ui Title

Size
Main P12V In / Backlight Control
Document Number Rev
B C1
rc
Midland (FHD), Roku-PN 0002001435
Date: Thursday, November 30, 2017 Sheet 18 of 20
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 5 4 3 2 1

300V
F801 VD807 VD808
VH-3AWS-2
1 2 NC/S3MB-13-F NC/S3MB-13-F
XP802
1 2 2 1
! TR53821400
LCL-3505-AZ\BBY
C802 L807
L806 C847 R803
RV801 LCL-3505-AJ 1 2 2 1
1 2 470p/1000VV 3.3M

1
2
4 1 2
NC\470p/400VV R802 R208 VD827 VD828 R208
1 4 3 PFC 电解电容位号只保留C810
R208 VD826
4
4 3
L TVR10621KFC3FGNY ! L801 ! 3.3M
2 1
VD825 R208
1 2
! C803 C846 C801
L802
2 NC/LCL-026-Q\TP
N 470n/275V 470p/1000VV R801 NC/LCL-020-Q\TP 2 1 1 2 C820 NC/2.2n/1000V
3

SCK10054LGY505
NC\470p/400VV 3.3M C821 NC/1n/DC1000VV
RT801 !
3

VD806 VD805 C822 NC/1n/DC1000VV

1
2
NC/S3MB-13-F
NC/SA-2S-486GP NC/S3MB-13-F C810
D 100u/250VV D
XS801
NC/150u/250VDCV
XP801
C811
NC/VH-3AWDS-2\reflow

1
1
VD804
XP801与XS802不同时使用 GS1M VD810
GS1M
HV

2
2
R806
1k

R830 R832
100R 100R
C806 NC/100p/DC1000VV
C975 C807 NC/100p/DC1000VV
C955 C967 100RR831 100R R834
C956 1
300V NC/1n/DC1000VV 3
C963 NC/1n/DC1000VV 2
2.2n/1000V 2.2n/1000V
NC/1n/DC1000VV VD937
NC/RFNL5BM6STL 90V
R835 C856 NC/1n/DC1000VV 1 2
100k C855 NC/1n/DC1000VV
C954 NC/1n/DC1000VV VD928 NC/US3M-13 C859 C957

2
C835 1 2 NC/68u/100VV 68u/100VV
VD813 C832 100p/2KV
C C
RS1M VD946 NUR460P/L03
NC/100p/DC1000VV
VD817 Q802

1
R809-43寸的最大270欧姆 NC/BLM18PG121SN1
，32寸的最大330欧姆 MBR10200CS2TR-E1 +12VSB
NC/BLM18PG121SN1 L903 T801 VCC12V
1

1
BLM31PG121SN1 L905
3 VCC
L906
HV Q801 1 2
N801 AOB7S65L V801 C869 C962
47R
1
Skip/latch HV
8 R809
270R NC/CS630A4H V802 3 1n/DC200VV
R837 C851 C857 100n/50V
C960 C969
100p/2KV 470u/25VV 470u/25VV
2 5 R808 2 1 1 BCK-04NG
FB Drv
2.2n/50V 180R C870 R838
VCC VD812
C843 R849
R818 1N4148W R819 ! NC/1n/DC1000VV 47R
2

39k 7 6 10k NC/100p/DC1000VV R817

NC VCC 27R 10R

4 3 R844 1
GND CS C842 820R R847
VD822
OZ531TGN 100p/50V 0.22R
GS1M
R851 R861
R866 1k
! 1k R860
2
2

27R C965 15k

VD939 C958
C845 10u/50VV STB
NC/BZT52C22 NC/10u/50VV N808
4.7u/25V
4 1 470n/50V
AUX_PWR_ON
2

C865
1

R858 R939
3 2 11,17
R985
1k NC/15k NC/4.7k

3
VD944 LTV-816S-TP-Cu FLG VSEN
V912 1
1

NC/BZT52C10
R856 R986

2
R833 3.9k NC/MMBT2222A NC/4.7k C964
NC/1n/50V C850

B 0R B
NC/1n/1000V

4 !
3 XP904 C848
2

00
1 XP901
NC/HX4.0-4P-W-K NC/1n/400VV
VLED1+
C840
90V
5
6 NC/100n/250V
C908
4

79
2

C909 NC/100n/250V
2.2u/160V 3 NC/1n/400VV
C976
NC/100p/DC1000VV !

3
4
FLG C961 C966 L908 2 C849
GND_POWER
MBR2150VRTR-G1 VD927 1 2 XP902
NC/2.2u/160VV L902 XP902海信标准
40寸VD927改为MURS160T3G 1
NC/HX4.0-2P-W-K
1

1n/1000V
L904 L901 NC/BLM18PG121SN1
1u/16V 2
R935 NC/BLM18PG121SN1 BLM31PG121SN1 1
680R C930 BLM31PG121SN1 NC/350.0 uH L909

t:
L907 VLED1-
+12VSBR930 N905 R979 82R LGB-1315-330U-K
10R
3

16 1 1 XP903
R931 VCC DRV1 V902 Q803
NC/PY-3AW-2
2

10k R962 1k VD923 C977 NC/100p/DC1000VV

V949 1 15 2 2 1 R978 1
STATUS DRV2
MMBT2907ALT1
R963 1N4148W
47R
ui
3

14 3 R943 CS630A4H
VREF RT GND
10k
100k R942
R920 NC/20R
13 4
rc
VREF ISEN1
R963设定工作频率， 1k R922\R923\R941\R942设定灯条电流，
一般40、43寸取150K， 1u/16V 100p/50V 参考电压0.5V
R941 R923
32寸取100K C938 12 5 C932 2.2R
ADJF ISEN2 10R

R922
ci

VSEN 11 6
A VSEN ADIM 2.2R VREF A

R934 BL_PDIM R940

FLG 10 7
CMPO PWM1 18 120k
1k
R933 R969 DIMMING
9 8 20k
18 BKL_EN BLON PWM2
1k PWM
BL_EN HOZ1GN
d

R967 R960 C959

20k 1u/16V
SW
270k
Roku, Inc. Confidential
ar

Title
R961 Power Drive
47k
Size Document Number Rev
C C1
Midland (FHD), Roku-PN 0002001435
bo

Date: Thursday, December 07, 2017 Sheet 18 of 20

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D D

C C

B B

00
79
A A

t:
Roku, Inc. Confidential
ui Title

Size
Micro SD Card Option
Document Number Rev
B C1
rc
Midland (FHD), Roku-PN 0002001435
Date: Thursday, November 30, 2017 Sheet 19 of 20
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D D

Audio Output C306 C307

A/V IN C308
10u/10V
R420
15k
R421 180p/50VV 1
N15
14
180p/50VV
R422
43k R423
C309
43k +INR +INL
7AU_DAC2_L AU_DAC2_R 7
C347 C311 2 13 C312 15k 10u/10V
C310 R424 -INR -INL C313 C348
1n/50V/NC 47p/50V 47p/50V R425
220p/50V 30.1k 3 12 220p/50V 1n/50V/NC
OUTR OUTL
LO1L_PA R426 R427 30.1k LO1R_PA
4 11
R370 5.1R GND UVP
5.1R
AV_AUR 7 MUTE_HP 5 10
Support 2Vrms Audio 10k RV26
C314
Mute GND
L32 C315 RV27
1% AVLC18S02015 VCC3.3V
into connector on R371 6 9 47n/16V AVLC18S02015
GAP13

C260 47n/16V C316 VSS VDD

AL_1 C259 12k BLM18PG121SN1
C 330p/50V 7 8 C
330p/50V 1u/10V C317 CN CP C318 C319
1u/10V
5 LO-MUTEn DRV632/BBY 100n/16V 2.2u/10V
C320
CVBS Audio In R374 R428
8 AV_AUL 7 4.7k 1u/10V
GND 9
红 SIGNAL9 10k
7 1%
SIGNAL7
GAP15

右 R376
C263 C264
12k
5 330p/50V 330p/50V
GND 6
白 SIGNAL6 4
SIGNAL4 CVBS-VCOM LO-MUTEn driven low by
CBVS-VCOM 8
中 PMU if POWER_DET (SAR5)
GND
2 below threashold. Line Out
黄 SIGNAL3
3 CVBS R377
1 C267 <<< near SoC
SIGNAL1 Video In
左 330p/50V 75R XS9
LO1R_PA 3 R
CVBS0-RCA CBVS0-RCA 8
XS8 4 WR
NC/ASES12U020R2

2 WL
LO1L_PA 1 L
B 5 GND B
GAP16
RV9

CKX-3.5-111

00
79
A A

t:
Roku, Inc. Confidential
ui Title

Size
AV-IN / LineOut
Document Number Rev
B C1
rc
Midland (FHD), Roku-PN 0002001435
Date: Monday, December 11, 2017 Sheet 20 of 20
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