Arcam: CD36 Main Board Panel Top Level
Arcam: CD36 Main Board Panel Top Level
Arcam: CD36 Main Board Panel Top Level
CON500
32
DAC_CLK 31
30
SCLK_MECH 29
CD Interface RC5 in & Digital out PSUsection
28
CD Interface.Sch RC5 in & Digital out.Sch PSUsection.Sch
SDATA_MECH 27
SPDIF SPDIF 26
LRCLK_MECH 25
SDATA_MECH
DAC_CLK
LRCLK_MECH
EMPH
SCLK_MECH
24
23
22
~XRST 21
20
19
18
EMPH 17
16
15
+5VDAC_SW
14
DAC_RELAY
~STANDBY
+18VU_SW
-18VU_SW
13
RMLED+
TRIGSW
RMLED-
12
TRIGIN
~XRST
~XRST
DISCO
DI/SW
SQSO
SCOR
SYSM
SQCK
SENS
LOAD
UNLD
CLOK
DATA
SCLK
11
XLAT
-30V
VfilA
VfilB
1/2X
RW
10
9
8
7
6
5
TRIGSW
4
TRIGIN
3
RMLED-
2
RMLED+
1
~XRST
~STANDBY
VfilA
MOLEX
VfilB DGND
52045
-30V
Flexfoil to 10DAC
THIS CONNECTOR REVERSED
+5VD
AT OTHER END OF FOIL
DISCO
DI/SW
SQSO
SCOR
SYSM
SQCK
SENS
LOAD
UNLD
CLOK
DATA
SCLK
XLAT
1/2X
RW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
ITEM500 1 BLANK PCB CD36 MAIN Blank PCB CD36 Main 290mm x 190mm overall L985PB FR4 / 1.6mm Green / White overlay
DRAWING TITLE
FD3 FD4 CD36 Main Board panel top level 05_E108 JR / MJT 14-07-05 0805 caps dropped to 50V where poss, PCB footprint changes 2.0
ARCAM
Filename: CD36main.PRJ 05_E090 JR 06-05-05 update to issue 1.0 1.0
FD1 FD2
Notes: 05_E072 JR 05-04-05 Changes, mainly to VFD supply B.0
PA7
R305
CON300 CON301 P317 DISP300
C300 10K
100 IC301_100
1
100N 1 1 F1
RX300 2
90 SQSO_D
92 SQCK_D
94 XLAT_D
50V 2 2 RMIN_D F1
+5V
3 3
4
C310 4 4 14G
5
100UF O/P 5 5 DGND_D 13G
6
99
98
97
96
95
93
91
89
88
87
86
85
84
83
82
81
6 6 12G
GND
6.3V 7
SM 11G
8
AVSS
VEE
VREF
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
FLD0
FLD1
FLD2
FLD3
FLD4
FLD5
FLD6
FLD7
AMP AMP 10G
9
CT CT 9G
DGND_IR 10
8G
STBY_D 1 80 11
FIX306 KSM-902TM1N PA5 FLD8 7G
C30810N 2 79 12
R321 PA4 FLD9 6G
TRIG_D 3 78 13
1 330R PA3 FLD10 5G
TGAUTO 4 77 14
PA2 FLD11 4G
LEDR 5 76 15
080550V PA1 FLD12 3G
Dia 3.5mm LEDG 6 75 16
PA0 FLD13 2G
RMLED+_D
RMLED-_D
FIX307 7 IC301 74 17
C30910N LED300 P97 FLD14 1G
8 73 18
5mm P96 M38B79 FLD15 NC
1 9 72 19
RED P95 CD73 CODE FLD16 P1
10 71 20
LED 5mm P94 QFP-100 FLD17 P2
11 70 21
Dia 3.5mm 50V 0805 600R@100MHz P93 FLD18 P3
CLOK_D 12 69 22
L300 P322 P92 FLD19 P4
DATA_D 13 68 23
+5VD_D P91 FLD20 P5
14 67 24
P90 FLD21 P6
IC300 15 66 25
P83 FLD22 P7
16 65 26
VCC
P82 FLD23 P8
LM809M3-4.38 DGND_D 17 64 27
+5VD_D CNVSS P30 P9
SOT-23 ~RST_D ~RST_D 18 63 28
RST RESET P31 P10
19 62 29
P81 P32 P11
GND
20 61 30
P80 P33 P12
R306 R307 21 60 31
VSS P34 P13
10K 10K 22 59 32
XIN P35 P14
23 58 33
XOUT P36 P15
P311 24 57 34
TRIG_D X300 VCC P37 P16
DGND_D 1 3 25 56 35
P77 P40 P17
P312 4.00MHz 26 55 36
TR303 P76 P41 P18
C312 10N SIL-3 SCLK_D 27 54 37
C311 P75 P42 P19
50V SENS_D 28 53 38
MMUN2211LT1 MMUN2211LT1 P74 P43 P20
0805 29 52 39
TR302 SOT-23 10uF P73 P44 P21
30 51
2
P72 P45
IC301_30
IC301_51
10V 41
1206 R325 R326 R327 R328 R329 F2
42
F2
P71
P70
P67
P66
P65
P64
P63
P62
P61
P60
P57
P56
P55
P54
P53
P52
P51
P50
P47
P46
DGND_D DGND_D
SOT-23 47K 47K 47K 47K 47K VFD 29-1405FN
Mount close to Xin/Xout
ZEC (GP)
VfilA_D
SCOR_D 31
RMIN_D 32
33
34
35
36
37
38
LOAD_D 39
UNLD_D 40
DISCO_D 41
DI/SW_D 42
43
CD/CDR_D 44
45
46
SYSM_D 47
48
49
50
DGND_D
TRIGIN_D
VfilB_D
IC301_50
P309 ITEM301
1/2X_D
LEDG -30V_D
RW_D
SUPPORT FMJ CD23T VFD
P310 1
LEDR Support FMJ CD23T VFD
CD SUPPORT
E930MC
R322 R323 600R@100MHz
0.91
1
2
3
4
560R 560R 30
P346 TGAUTO *
LED301
R312 R313 R324
BICOL -30V_D
RMLED+_D
CD/CDR_D
RMLED-_D
SCOR_D
TRIGIN_D
SYSM_D
SENS_D
UNLD_D
LOAD_D
SCLK_D
~RST_D
L301 +5VD_D
SQSO_D
SQCK_D
CLOK_D
STBY_D
1/2X_D
XLAT_D
RW_D
+5VD_D
TRIGSW_D
VfilA_D
DGND_D ITEM300 1 TAPE D/SIDED 12MM X 70MM Tape D/Sided 12MM X 70MM DS Polyester 4965 BDK / 4965T 12MM X 50M ROLL
1
2
3
4
5
6
7
8
9
DGND_D C317
CON302
50V CD36 Display and MPU 05_E108 JR / MJT 14-07-05 0805 caps dropped to 50V where poss, PCB footprint changes 2.0
SM
DGND_D
ARCAM
MOLEX Filename: Display & Micro.Sch 05_E090 JR 06-05-05 update to issue 1.0 1.0
52044
Notes: 05_E072 JR 05-04-05 Changes, mainly to VFD supply Caps added at filament B.0
_D suffix (i.e. -30V_D) means that the port is local to
A & R Cambridge Ltd. this DISPLAY board. Rs & Cs are 0805 unless otherwise stated. 05_E006 JR 17-01-05 First release A.0
Pembroke Avenue A 'tilde', as in ~RESET, means active LOW. ECO No. INITIALS DATE DESCRIPTION OF CHANGE ISSUE
Waterbeach
Cambridge CB5 9QR Contact Engineer: John Roscoe Contact Tel: 01223 203251 (or 203200) Printed: 14-Jul-2005 Sheet 2 of 5 A3 DRAWING NO. L985CT
R25 2K7 P13
These resistors have been P12
R60 13K
added to ensure that 5V logic P11
R55 2K7
levels from the CPU do not P10
R56 2K7
over-drive the 3.6V inputs. P9
R57 2K7
R58 2K7 P8
R59 2K7
DGND
P4 R15 1K0 SCOR
+3V6D +3V6D
DI/SW P7 R16 1K0 SCLK
DISCO P5 R17 1K0 SENS
C4 R11 C5 R18 1K0 CLOK
+5VD 100N 100N R19 1K0 XLAT
50V 100K 50V R20 1K0 DATA
R21 1K0 SYSM
R3 4K7 ~XRST
R1 R2 +7VD DGND DGND R22 1K0 SQCK
P6 R23 1K0 SQSO
4K7 4K7 R6 10K
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C17
7
C2
XLAT
GFS
XRST
SQSO
SCOR
VDD
SPOB
SPOA
DATA
XUGF
SYSM
XPCK
ATSK
SCLK
SENS
SQCK
C2PO
XLON
WFCK
CLOK
CON1 C3
VCC2
VCC1
100N 100UF R10 8K2
5 21 80 +3V6D
50V 25V COUT LMUT
4 22 79
YK MIRR RMUT P17
3 23 78
100N 50V DFCT AVDD2
2 TRAY+ 2 5 LOAD 24 77
OUT1 IN1 FOK AOUT2 C6 C23
1 TRAY- 25 IC3 76
P79 LOCK AIN2 100N
3 SPDR 26 CXD3017Q 75
C1 P1 MDP LOUT2 50V 100UF
SSTP 27 LQFP-80 74
SSTP AVSS2 25V
JST 6 UNLD SFDR 28 73
100N IN2 SFDR AVSS1 YK
PH DGND SRDR 29 72
50V C14 SRDR LOUT1
10 9 TFDR 30 71 DGND
OUT2 P2 P1 TFDR AIN1
TRDR 31 70
10N 50V P3 TRDR AOUT1
FFDR 32 69
0805 P2 FFDR AVDD1
FRDR 33 68
FRDR XVSS
4 34 67
Vz VSS XTAO
35 66 DAC_CLK
TEST XTAI
36 65
DZ1 R62 C31 TES1 XVDD
37 64 EMPH
XTST EMPH
GND
IC1 38 63 P52 BCK
BZX84C 15K 47UF VC BCK P50
LB1641 39 62 PCMD
4V7 35V FE PCMID P53 LRCK
1 SIP-10 40 61
SE LRCK
AVDD0
AVDD3
AVSS0
AVSS3
SOT-23 YK
DOUT
ASYO
RFDC
RFAC
CLTV
ADIO
IGEN
ASYI
BIAS
FILO
PCO
VDD
VSS
FILI
CE
TE
C11
DGND C12
DGND 100N
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
50V
P46
50V DGND
+3V6D 100N
L1 +3V6D R41
R39 P39 3K3
3.6V_SERVO DGND
33K P48 R43
SPDIF P54
10U R26 R4 R28 C7 R31 C9 C24 C18 C20 R29 R32 C22 R36 P45 SPDIF
Laser protection
P38 R7 P40 330R
remove link after VC
assembly 3K0 4K7 5K1 100N 68K 100N 1000UF 100UF 22UF 5K1 15K 100UF 10R
50V 50V 10V 25V 63V 25V R33 15K P32 10K R42
CON4 FE
YK YK YK YK P30 R13 P41 3K3
1
R12 100K P33
2 DGND DGND
C16 100K C29 P47
22
+7VD LOAD
LOAD
UNLD
UNLD
DISCO
C36 DISCO
DI/SW
DI/SW
IC4 RW
470UF RW
BA6392 CD/CDR not used on Solo
22
21
P77 SYSM
1 4 SRDR DGND SRDR
SL+ SRDR P74
2 5 SFDR SFDR
SL- SFDR
3 P78
RCIN1
CON5 FCS+ 12 9 FRDR FRDR
FCS+ FRDR
6 SSTP FCS- 13 10 FFDR FFDR
FCS- FFDR
5
4 SL- 11 P73
P18 RCIN2
3 SL+
2 SP+ TRK+ 16 20 TRDR TRDR
TRK+ TRDR P75
1 SP- TRK- 17 19 TFDR TFDR
TRK- TFDR
18 P71
RCIN3
JST
PH DGND P20 27 25
SP+ VBIN1 P76
26 23 VC
SP- VBIN2
24 SPDR P72 SPDR
SPDR
C28
15 P70 ~XRST
MUTE 100P
100V C
P69 7
VREFO VREFI
6 P81 Copyright 2005 A&R Cambridge Ltd
DGND
GNDHS
GNDHS
100N 27P 27P 1N5 05_E108 JR / MJT 14-07-05 0805 caps dropped to 50V where poss, PCB footprint changes 2.0
50V 100V 100V 50V
ARCAM
30
29
8
28
14
C39 0805 Filename: CD Interface.Sch 05_E090 JR 06-05-05 update to issue 1.0 1.0
330N DGND
100V Notes: 05_E072 JR 05-04-05 Brought up to date with Solo B.0
DGND
P16 MKS2
A & R Cambridge Ltd. 05_E006 JR 17-01-05 First release A.0
Pembroke Avenue
DGND ECO No. INITIALS DATE DESCRIPTION OF CHANGE ISSUE
Waterbeach
Cambridge CB5 9QR Contact Engineer: John Roscoe Contact Tel: 01223 203251 (or 203200) Printed: 14-Jul-2005 Sheet 3 of 5 A2 DRAWING NO. L985CT
Main Board Supplies
+5VD
VFD supplies
M100 NTF2955
P124 DZ100BZX84C SOT-223
+18Vunreg
+18VU_SW
R112 R123
Fit either SOT-23 or
C100 47K VfilA 10V
DO-35 zener, 2%
100N 470R
DGND DZ108
50V R111 R124 SOT-23 P128
BZX84B DZ105 P100
47K VfilB
30V 2% BZX79B
470R TR107 R102
SOT-23 30V C101
MMUN2111LT1
R105 R106 NF 10K
100N HT can be varied by changing R110
DO-35 DZ102 5V6 50V is 27.6V with 2k7 P127
100K 100K
SOT-23
BZX84C -30V
SOT-23
Standby - active LOW
TR113 10DAC supply from power board
R110 VFD power supply changed to cure flicker P129
P102 P103 ~PWRDN_N
ZTX753 CON100 This becomes analogue
2K7 P126
ELINE 5 ground when linked TR102
TR103 4 on 10DAC board MMUN2211LT1
SOT-23
BC846B 3
TR113_C
SOT-23 2
R107 P104 +5VD
1 DGND R100
10K 22K
IC102E DGND
TR106 R113 TR109 P130
P10910 AMP
BC846B 270R 11
~PWRDN_P CT
SOT-23 R103 DZ101
74HC14
MMUN2111LT1 10K
P108 SO-14
SOT-23
-18Vunreg
-18VU_SW
R108 M101
CON101 DBR100 10V
4 3BDF04M SOT-23 NTF3055V
10K
3 BZX84C SOT-223
2
VfilA
1
M104
NTF3055V
Transistors ON for enable
SOT-223 M103 NTF2955
AMP This is not a rectifier DZ107 P101 DZ104BZX84C SOT-223 D108 S1D
CT It is an AC switch
BZX84C +8VDACunreg DO-214AC
REG105 TO-220
15V LM1086CT-ADJ
R109
SOT-23 HS103A
10K 10V
DZ106 6072B
SOT-23 +5VDAC_SW
10V 7C/W
ADJ
D103 P112 R134
BZX84C DO-214AC
S1D
SOT-23 HS100A 120R
M102 NTF2955 REG104 C126
VfilB SW50-2
BZX84C SOT-223 LM1086CT-ADJ 1uF
8.8C/W
+12VUNREG +12VUNREG_SW R101 R136 25V R133
TO-220 +7VD C128
1206 360R C127
ADJ
DZ103 10K 10K 10uF
R125
10V 10V 10uF
220R P111
SOT-23 1206 10V
1206
HS101A D104 S1D
P110 DGND
DO-214AC +5VD C118 R141
0R0 ~PWRDN_N
REG101 R114 C115
LM317T 1uF 220UF TR100
1K0
R131 R132 25V 16V MMUN2211LT1
SOT-23
TO-220 10K 10K 1206 YK
C105 D102 C107 SW50-2 Supply, mainly to CPU
ADJ
ADJ
DGND
8.8C/W R130 SO-14 BAV99
AMP DGND
REG102 270R IC102A SOT-23
CT +5VD
P134 2 1 P119
XRST
SEC1B
C129 R142 R135
74HC14 1uF 1M0 100K
R140 SO-14 25V
C110 0R0 P121 R137 1K0
1206
R129 C123 C124 ~STANDBY
1uF 510R REMOVE THIS
DGND C130 R143
25V 10uF 10uF RESISTOR TO DISABLE
AC present detect and timer 1206 10V 10V
1uF 1M0
IC102D IC102C 25V STANDBY MODE
1206 1206
8 9 6 5 1206
DGND ~PWRDN_N
R127 P132 D105 P120
TR111 P118
100K 74HC14 74HC14
BC846B P115 SOT-23S1D SO-14 SO-14 +5VD IC102G
SOT-23 DO-214AC PWRD_N C125 14
D107BAV70 VCC
TR110 100N
SOT-23
MMUN2111LT1 IC102F
SOT-23 R128 P131 R104 50V
P133 12 13
100R 10K ~PWRDN_P
TR112 DAC_RELAY The method of system reset, power up/down via mains switch and standby mode has 7
GND
BC846B changed from that of the CD73.
Contacts N/C
74HC14 DGND
P113 When the CPU is reset by the LM809, IC300 on the display board, after a short SO-14 74HC14
P116 delay, approx. 200mS, the ~STANDBY line goes HIGH. SO-14
The ~STANDBY line, in turn, generates 2 more timed signals.
SOT-23 The drive voltage to the NPN & PNP digital
TR104 TR114 transistors is separated in order to prevent an
P114
MMUN2211LT1 1. ~XRST, the system reset line, which goes HIGH 1s after the standby line goes
XRST indeterminate bias voltage appearing on their
high, and is also gated into the 10DAC power-on mute cct.
bases due to their internal resistors across the
MMUN2211LT1 2. ~PWRDN, which switches off all the unregulated supplies except that which drives
supply.
the +5VD to the CPU.
P122 R115 P123 TR105
SOT-23
This delays the LV power being switched off by 1s after the output is muted.
MMUN2211LT1
1K0
C112 100UF C120 SOT-23 The XRST line from the CPU is no longer used
6.3V
SM
1uF C
25V
1206
Copyright 2005 A&R Cambridge Ltd
ITEM QTY PART No. DESCRIPTION NOTES
DGND
DRAWING TITLE
CD36 Main Board PSU Section 05_E108 JR / MJT 14-07-05 0805 caps dropped to 50V where poss, PCB footprint changes 2.0
ARCAM
Filename: PSUsection.Sch L981AY 05_E090 JR 06-05-05 update to issue 1.0 1.0
4
P201
IC200A P202
DGND D200
74HCT125D BAT54S
IC200C SOT-23
74HCT125D
2 3 P200 R200 100R 9
R204 1K0
8 P208
SPDIF SO-14 SO-14
10
DGND
4
74HCT125D 100N 50V L203
R206 R202 C203
13
Remote IR in SO-14
SCRN
SKT200 L200 600R@100MHz 3K3 100R 47P 1000R @ 100MHz
1
RMLED+
RMLED+ DGND 100V 4 8 P206 DLW31S SPDIF_GND
NC
L201
RMLED- PCB Mount SMT
RMLED- DGND
600R@100MHz 7A29398
KUNMING
HTJ +5VD C202 C207
C200 C201
100P 10N
100P 100P R208 100V 50V
100V 10R 0805
100V NF
EMC_GND
2
EMC_GND TX201
VCC
JFJ1001-010010 C206
C205
R201 100R
1
I/P 100N 100UF
GND
50V 10V
Trigger Input YXF
3
SKT202 NCL
DGND
L 2 TRIGIN
OPTICAL OUT
TRIGIN
R 3
1
DGND
10K pull-up on VFD board
NCR TRIGSW
TRIGSW
KUNMING
HTJ
IC200E
74HCT125D
SO-14
+5VD
14
VCC
C208
10uF
7 10V
GND 1206
DGND C Copyright 2005 A&R Cambridge Ltd
DRAWING TITLE
CD36 Main Board RC5 & digital out 05_E108 JR / MJT 14-07-05 0805 caps dropped to 50V where poss, PCB footprint changes 2.0
ARCAM
Filename: RC5 in & Digital out.Sch 05_E090 JR 06-05-05 update to issue 1.0 1.0