Winbond Datasheet

W29N02KVxxAE
W29N02KVxxAE
2G-BIT 3.3V
NAND FLASH MEMORY
Release Date: August 19th, 2021

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Table of Contents
1. GENERAL DESCRIPTION ............................................................................................................ 7

2. FEATURES .................................................................................................................................... 7
3. PACKAGE TYPES AND PIN CONFIGURATIONS ....................................................................... 8
3.1 Pin Assignment 48-pin TSOP1(x8) ....................................................................................... 8
3.2 Pin Assignment 48 ball VFBGA (x8) ..................................................................................... 9
3.3 Pin Assignment 63 ball VFBGA (x8) ................................................................................... 10
3.4 Pin Descriptions .................................................................................................................. 11
4. PIN DESCRITPIONS ................................................................................................................... 12
4.1 Chip Enable (#CE) .............................................................................................................. 12
4.2 Write Enable (#WE) ............................................................................................................ 12
4.3 Read Enable (#RE) ............................................................................................................. 12
4.4 Address Latch Enable (ALE) .............................................................................................. 12
4.5 Command Latch Enable (CLE) ........................................................................................... 12
4.6 Write Protect (#WP) ............................................................................................................ 12
4.7 Ready/Busy (RY/#BY) ........................................................................................................ 12
4.8 Input and Output (I/Ox) ....................................................................................................... 12
5. BLOCK DIAGRAM ....................................................................................................................... 13
6. MEMORY ARRAY ORGANIZATION ........................................................................................... 14
6.1 Array Organization (x8) ....................................................................................................... 14
7. MODE SELECTION TABLE ........................................................................................................ 15
8. COMMAND TABLE ...................................................................................................................... 16
9. DEVICE OPERATIONS ............................................................................................................... 17
9.1 READ Operation ................................................................................................................. 17
9.1.1 PAGE READ (00h-30h) ........................................................................................................ 17
9.1.2 TWO PLANE READ (00h-00h-30h) ...................................................................................... 17
9.1.3 RANDOM DATA OUTPUT (05h-E0h) ................................................................................... 19
9.1.4 READ ID (90h) ...................................................................................................................... 20
9.1.5 READ PARAMETER PAGE (ECh) ....................................................................................... 21
9.1.6 READ STATUS (70h) ........................................................................................................... 23
9.1.7 READ STATUS ENHANCED (78h) ...................................................................................... 25
9.1.8 READ UNIQUE ID (EDh) ...................................................................................................... 26
9.2 PROGRAM Operation ........................................................................................................ 27
9.2.1 PAGE PROGRAM (80h-10h) ................................................................................................ 27
9.2.2 SERIAL DATA INPUT (80h) ................................................................................................. 27
9.2.3 RANDOM DATA INPUT (85h) .............................................................................................. 28
9.2.4 TWO PLANE PAGE PROGRAM .......................................................................................... 29
9.3 COPY BACK Operation ...................................................................................................... 30
9.3.1 READ for COPY BACK (00h-35h) ........................................................................................ 30
9.3.2 PROGRAM for COPY BACK (85h-10h) ................................................................................ 31
9.3.3 TWO PLANE READ for COPY BACK ................................................................................... 32
9.3.4 TWO PLANE PROGRAM for COPY BACK .......................................................................... 32
9.4 BLOCK ERASE Operation.................................................................................................. 36
9.4.1 BLOCK ERASE (60h-D0h) ................................................................................................... 36
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9.4.2 TWO PLANE BLOCK ERASE.................................................................................................. 37

9.5 RESET Operation ............................................................................................................... 38
9.5.1 RESET (FFh) ........................................................................................................................ 38
9.6 FEATURE OPERATION ..................................................................................................... 39
9.6.1 GET FEATURES (EEh) ........................................................................................................ 42
9.6.2 SET FEATURES (EFh) ......................................................................................................... 43
9.7 ONE TIME PROGRAMMABLE (OTP) Area ....................................................................... 44
9.8 WRITE PROTECT .............................................................................................................. 45
9.9 BLOCK LOCK ..................................................................................................................... 47
10. ELECTRICAL CHARACTERISTICS ............................................................................................ 48
10.1 Absolute Maximum Ratings (3.3V) ..................................................................................... 48
10.2 Operating Ranges (3.3V) .................................................................................................... 48
10.3 Device Power-up Timing..................................................................................................... 49
10.4 DC Electrical Characteristics (3.3V) ................................................................................... 50
10.5 AC Measurement Conditions (3.3V) ................................................................................... 51
10.6 AC Timing Characteristics for Command, Address and Data Input (3.3V) ........................ 52
10.7 AC Timing Characteristics for Operation (3.3V) ................................................................. 53
10.8 Program and Erase Characteristics .................................................................................... 54
11. TIMING DIAGRAMS .................................................................................................................... 55
12. INVALID BLOCK MANAGEMENT ............................................................................................... 64
12.1 Invalid Blocks ...................................................................................................................... 64
12.2 Initial Invalid Blocks ............................................................................................................ 64
12.3 Error in Operation ............................................................................................................... 65
12.4 Addressing in Program Operation ...................................................................................... 65
13. PACKAGE DIMENSIONS ............................................................................................................ 66
13.1 TSOP 48-pin 12x20 ............................................................................................................ 66
13.2 Fine-Pitch Ball Grid Array 48-Ball ....................................................................................... 67
13.3 Fine-Pitch Ball Grid Array 63-Ball ....................................................................................... 68
14. ORDERING INFORMATION ....................................................................................................... 69
15. VALID PART NUMBERS ............................................................................................................. 70
16. REVISION HISTORY ................................................................................................................... 71

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List of Tables
Table 3-1 Pin Descriptions ..........................................................................................................................11
Table 6-1 Addressing ..................................................................................................................................14
Table 7-1 Mode Selection ...........................................................................................................................15
Table 8-1 Command Table ..........................................................................................................................16
Table 9-1 Device ID and Configuration Codes for Address 00h .................................................................21
Table 9-2 ONFI Identifying Codes for Address 20h ....................................................................................21
Table 9-3 Parameter Page Output Value ....................................................................................................23
Table 9-4 Status Register Bit Definition ......................................................................................................24
Table 9-5 Features ......................................................................................................................................39
Table 9-6 Feature Address 80h ...................................................................................................................40
Table 9-7 Feature Address 81h ...................................................................................................................41
Table 10-1 Absolute Maximum Ratings ......................................................................................................48
Table 10-2 Operating Ranges .....................................................................................................................48
Table 10-3 DC Electrical Characteristics ....................................................................................................50
Table 10-4 AC Measurement Conditions ....................................................................................................51
Table 10-5 AC Timing Characteristics for Command, Address and Data Input .........................................52
Table 10-6 AC Timing Characteristics for Operation ..................................................................................53
Table 10-7 Program and Erase Characteristics ..........................................................................................54
Table 12-1 Valid Block Number...................................................................................................................64
Table 12-2 Block Failure .............................................................................................................................65
Table 15-1 Part Numbers for Industrial Grade ............................................................................................70
Table 15-2 Part Numbers for Industrial Plus Grade ....................................................................................70
Table 16-1 History Table .............................................................................................................................71

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List of Figures
Figure 3-1 Pin Assignment 48-pin TSOP1 (Package code S) ...................................................................... 8
Figure 3-2 Pin Assignment 48-ball VFBGA (Package code D) ..................................................................... 9
Figure 3-3 Pin Assignment 63-ball VFBGA (Package code B) ...................................................................10
Figure 5-1 NAND Flash Memory Block Diagram ........................................................................................13
Figure 6-1 Array Organization .....................................................................................................................14
Figure 9-1 Page Read Operations ..............................................................................................................17
Figure 9-2 Random Data Output .................................................................................................................19
Figure 9-3 Two Plane Random Data Output ...............................................................................................19
Figure 9-4 Read ID ......................................................................................................................................20
Figure 9-5 Read Parameter Page ...............................................................................................................21
Figure 9-6 Read Status Operation ..............................................................................................................23
Figure 9-7 Read Status Enhanced (78h) Operation....................................................................................25
Figure 9-8 Read Unique ID .........................................................................................................................26
Figure 9-9 Page Program ............................................................................................................................27
Figure 9-10 Random Data Input ..................................................................................................................28
Figure 9-11 Two Plane Page Program ........................................................................................................30
Figure 9-12 Program for copy back Operation ............................................................................................33
Figure 9-13 Copy Back Operation with Random Data Input .......................................................................33
Figure 9-14 Two Plane Copy Back..............................................................................................................34
Figure 9-15 Two Plane Copy Back with Random Data Input ......................................................................34
Figure 9-16 Two Plane Program for Copy Back .........................................................................................35
Figure 9-17 Block Erase Operation .............................................................................................................36
Figure 9-18 Two Plane Block Erase Operation ...........................................................................................37
Figure 9-19 Reset Operation .......................................................................................................................38
Figure 9-20 Get Feature Operation .............................................................................................................42
Figure 9-21 Set Feature Operation .............................................................................................................43
Figure 9-22 Erase Enable ...........................................................................................................................45
Figure 9-23 Erase Disable ...........................................................................................................................45
Figure 9-24 Program Enable .......................................................................................................................45
Figure 9-25 Program Disable ......................................................................................................................46
Figure 9-26 Program for Copy Back Enable ...............................................................................................46
Figure 9-27 Program for Copy Back Disable ..............................................................................................46
Figure 10-1 Power ON/OFF Sequence .......................................................................................................49
Figure 11-1 Command Latch Cycle.............................................................................................................55
Figure 11-2 Address Latch Cycle ................................................................................................................55
Figure 11-3 Data Latch Cycle ......................................................................................................................56
Figure 11-4 Serial Access Cycle after Read ...............................................................................................56
Figure 11-5 Serial Access Cycle after Read (EDO) ....................................................................................57
Figure 11-6 Read Status Operation ............................................................................................................57
Figure 11-7 Page Read Operation ..............................................................................................................58
Figure 11-8 #CE Don't Care Read Operation .............................................................................................58
Figure 11-9 Random Data Output Operation ..............................................................................................59
Figure 11-10 Read ID ..................................................................................................................................60
Figure 11-11 Page Program ........................................................................................................................60

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Figure 11-12 #CE Don't Care Page Program Operation .............................................................................61

Figure 11-13 Page Program with Random Data Input ................................................................................61
Figure 11-14 Copy Back ..............................................................................................................................62
Figure 11-15 Block Erase ............................................................................................................................62
Figure 11-16 Reset ......................................................................................................................................63
Figure 12-1 Flow Chart of Create Initial Invalid Block Table .......................................................................64
Figure 12-2 Bad Block Replacement ..........................................................................................................65
Figure 13-1 TSOP 48-PIN 12X20mm .........................................................................................................66
Figure 13-2 Fine-Pitch Ball Grid Array 48-Ball ............................................................................................67
Figure 13-3 Fine-Pitch Ball Grid Array 63-Ball ............................................................................................68
Figure 14-1 Ordering Part Number Description ..........................................................................................69

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1. GENERAL DESCRIPTION
The W29N02KV (2G-bit) NAND Flash memory provides a storage solution for embedded systems with
limited space, pins and power. It is ideal for code shadowing to RAM, solid state applications and storing
media data such as, voice, video, text and photos. The device operates on a single 2.7V to 3.6V power
supply with active current consumption as low as 25mA at 3V and 10uA for CMOS standby current.
The memory array totals 285,212,672 bytes, and organized into 2,048 erasable blocks of 139,264 bytes.
Each block consists of 64 programmable pages of 2,176-bytes each. Each page consists of 2,048-bytes
for the main data storage and 128-bytes for the spare data area (The spare area is typically used for error
management functions).
The W29N02KV supports the standard NAND flash memory interface using the multiplexed 8-bit bus to
transfer data, addresses, and command instructions. The five control signals, CLE, ALE, #CE, #RE and
#WE handle the bus interface protocol. Also, the device has two other signal pins, the #WP (Write Protect)
and the RY/#BY (Ready/Busy) for monitoring the device status.
2. FEATURES
 Basic Features  Command set
– Density: 2Gbit (Single chip solution) – Standard NAND command set
– Vcc: 2.7V to 3.6V – Additional command support
– Bus width: x8  Copy Back
– Operating temperature  Two-plane operation
 Industrial: -40°C to 85°C – Contact Winbond for OTP feature
 Industrial Plus: -40°C to 105°C – Contact Winbond for Block Lock feature
 Single-Level Cell (SLC) technology.
 Organization  Lowest power consumption
– Density: 2G-bit/256M-byte – Read: 25mA(typ.)
– Page size – Program/Erase: 25mA(typ.)
 2,176 bytes – CMOS standby: 10uA(typ.)
– Block size
 Space Efficient Packaging
 64 pages
– 48-pin standard TSOP1
 Highest Performance – 48-ball VFBGA
– Read performance (Max.) – 63-ball VFBGA
 Random read: 25us – Contact Winbond for stacked
 Sequential read cycle: 25ns packages/KGD
– Write Erase performance
 Page program time: 250us (typ.)
 Block erase time: 2ms (typ.)
– Endurance: 60,000 Erase/Program
Cycles(1)
– Data retention: 10-years
Note:
1. Endurance specification is based on 8bit/544 byte ECC (Error Correcting Code).

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3. PACKAGE TYPES AND PIN CONFIGURATIONS

W29N02KV is offered in a 48-pin TSOP1 package (Code S) and 48-ball VFBGA package (Code
D) as shown in Figure 3-1 to 3-2, respectively. Package diagrams and dimensions are illustrated
in Section: Package Dimensions.
3.1 Pin Assignment 48-pin TSOP1(x8)
X8 Top View X8
N.C 1 48 Vss1
N.C 2 47 N.C
N.C 3 46 N.C
N.C 4 45 N.C
N.C 5 44 IO7
N.C 6 43 IO6
RY/#BY 7 42 IO5
#RE 8 41 IO4
#CE 9 40 N.C
N.C
N.C
10
11 48-pin TSOP1 39
38
Vcc1
DNU
Vcc Vcc
Vss
12
13 Standard package 37
36 Vss
N.C 14 35 N.C
N.C 15 12mm x 20mm 34 Vcc1
CLE 16 33 N.C
ALE 17 32 IO3
#WE 18 31 IO2
#WP 19 30 IO1
DNU 20 29 IO0
N.C 21 28 N.C
N.C 22 27 N.C
N.C 23 26 N.C
N.C 24 25 Vss1
Figure 3-1 Pin Assignment 48-pin TSOP1 (Package code S)
Note:
1. These pins might not be connected in the package. Winbond recommends connecting these pins to the
designed external sources for ONFI compatibility.

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3.2 Pin Assignment 48 ball VFBGA (x8)
Top View, ball down
1 2 3 4 5 6
A #WP ALE Vss #CE #WE RY/#BY
B N.C #RE CLE N.C N.C N.C
C N.C N.C N.C N.C N.C N.C
D N.C N.C N.C N.C N.C N.C
E DNU N.C DNU N.C N.C N.C
F N.C IO0 N.C N.C N.C Vcc
G N.C IO1 N.C Vcc IO5 IO7
H Vss IO2 IO3 IO4 IO6 Vss
Figure 3-2 Pin Assignment 48-ball VFBGA (Package code D)

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3.3 Pin Assignment 63 ball VFBGA (x8)
Top View, ball down
1 2 3 4 5 6 7 8 9 10
A N.C N.C N.C N.C
B N.C N.C N.C
C #WP ALE Vss #CE #WE RY/#BY
D N.C #RE CLE N.C N.C N.C
E N.C N.C N.C N.C N.C N.C
F N.C N.C N.C N.C N.C N.C
G DNU N.C DNU N.C N.C N.C
H N.C IO0 N.C N.C N.C Vcc
J N.C IO1 N.C Vcc IO5 IO7
K Vss IO2 IO3 IO4 IO6 Vss
L N.C N.C N.C N.C
M N.C N.C N.C N.C
Figure 3-3 Pin Assignment 63-ball VFBGA (Package code B)

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3.4 Pin Descriptions

PIN NAME I/O FUNCTION
#WP I Write Protect
ALE I Address Latch Enable
#CE I Chip Enable
#WE I Write Enable
RY/#BY O Ready/Busy
#RE I Read Enable
CLE I Command Latch Enable
I/O[0-7] I/O Data Input/Output (x8)
Vcc Supply Power supply
Vss Supply Ground
DNU - Do Not Use: DNUs must be left unconnected.
No Connect: NCs are not internally connected. They can be driven or left
N.C -
unconnected.
Table 3-1 Pin Descriptions

Note:
1. Connect all Vcc and Vss pins to power supply or ground. Do not leave Vcc or Vss disconnected.

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4. PIN DESCRITPIONS
4.1 Chip Enable (#CE)

#CE pin enables and disables device operation. When #CE is high the device is disabled and the
I/O pins are set to high impedance and enters into standby mode if not busy. When #CE is set
low the device will be enabled, power consumption will increase to active levels and the device is
ready for Read and Write operations.
4.2 Write Enable (#WE)

#WE pin enables the device to control write operations to input pins of the device. Such as,
command instructions, addresses and data that are latched on the rising edge of #WE.
4.3 Read Enable (#RE)

#RE pin controls serial data output from the pre-loaded Data Register. Valid data is present on
the I/O bus after the tREA period from the falling edge of #RE. Column addresses are incremented
for each #RE pulse.
4.4 Address Latch Enable (ALE)

ALE pin controls address input to the address register of the device. When ALE is active high,
addresses are latched via the I/O pins on the rising edge of #WE.
4.5 Command Latch Enable (CLE)

CLE pin controls command input to the command register of the device. When CLE is active high,
commands are latched into the command register via I/O pins on the rising edge of #WE.
4.6 Write Protect (#WP)

#WP pin can be used to prevent the inadvertent program/erase to the device. When #WP pin is
active low, all program/erase operations are disabled.
4.7 Ready/Busy (RY/#BY)

RY/#BY pin indicates the device status. When RY/#BY output is low, it indicates that the device
is processing either a program, erase or read operations. When it returns to high, those operations
have completed. RY/#BY pin is an open drain.
4.8 Input and Output (I/Ox)

I/Ox bi-directional pins are used for the following; command, address and data operations.

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5. BLOCK DIAGRAM
I/Ox I/O
Control
Column Decoder
Data Register
NAND Flash
Status Command Address
Register Register Register Array
#CE
ALE
CLE Logic
#RE Control
#WE High Voltage Row Decoder
#WP Generator
RY/#BY
Figure 5-1 NAND Flash Memory Block Diagram

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6. MEMORY ARRAY ORGANIZATION
6.1 Array Organization (x8)
2176 bytes 2176 bytes
DQ7
Data Register 2176bytes 2176bytes DQ0
1page = 2176bytes
1024 1block = 2176bytes×64 pages
blocks 136kbyte
Per plane
1plane = 136kbyte×1024blocks
1 block 1 block =1088Mb
2048 1device = 1088M ×2planes
blocks =2176Mb
Per device
Plane of even Plane of- odd

-
numbered blocks numbered blocks
Figure 6-1 Array Organization

I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1st cycle A7 A6 A5 A4 A3 A2 A1 A0
2nd cycle L L L L A11 A10 A9 A8
3rd cycle A19 A18 A17 A16 A15 A14 A13 A12
4th cycle A27 A26 A25 A24 A23 A22 A21 A20
5th cycle L L L L L L L A28
Table 6-1 Addressing
Notes:
1. “L” indicates a low condition, which must be held during the address cycle to insure correct processing.
2. A0 to A11 during the 1st and 2nd cycles are column addresses. A12 to A28 during the 3rd, 4th and 5th
cycles are row addresses.
3. A18 is plane address
4. The device ignores any additional address inputs that exceed the device’s requirement.

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7. MODE SELECTION TABLE
MODE CLE ALE #CE #WE #RE #WP

Read Command input H L L H X
mode
Address input L H L H X
Program Command input H L L H H
Erase Address input L H L H H
mode
Data input L L L H H
Sequential Read and Data output L L L H X
During read (busy) X X X X H X
During program (busy) X X X X X H
During erase (busy) X X X X X H
Write protect X X X X X L
Standby X X H X X 0V/Vcc
Table 7-1 Mode Selection
Notes:
1. “H” indicates a HIGH input level, “L” indicates a LOW input level, and “X” indicates a Don’t Care Level.
2. #WP should be biased to CMOS HIGH or LOW for standby.

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8. COMMAND TABLE
1ST 2ND 3rd 4th Acceptable
COMMAND during
CYCLE CYCLE CYCLE CYCLE busy
PAGE READ 00h 30h

READ for COPY BACK 00h 35h
READ ID 90h
READ STATUS 70h Yes
RESET FFh Yes
PAGE PROGRAM 80h 10h
PROGRAM for COPY BACK 85h 10h
BLOCK ERASE 60h D0h
RANDOM DATA INPUT*1 85h
RANDOM DATA OUTPUT*1 05h E0h
READ PARAMETER PAGE ECh
READ UNIQUE ID EDh
GET FEATURES EEh
SET FEATURES EFh
READ STATUS ENHANCED 78h Yes
TWO PLANE READ PAGE 00h 00h 30h
TWO PLANE READ FOR COPY BACK 00h 00h 35h
TWO PLANE RANDOM DATA READ 06h E0h
TWO PLANE PROGRAM(TRADITIONAL) 80h 11h 81h 10h
TWO PLANE PROGRAM(ONFI) 80h 11h 80h 10h
TWO PLANE PROGRAM FOR COPY 85h 11h 81h 10h
BACK(TRADITIONAL)
TWO PLANE PROGRAM FOR COPY 85h 11h 85h 10h
BACK(ONFI)
TWO PLANE BLOCK ERASE(TRADITIONAL) 60h 60h D0h
TWO PLANE BLOCK ERASE(ONFI) 60h D1h 60h D0h
Table 8-1 Command Table
Notes:
1. RANDOM DATA INPUT and RANDOM DATA OUTPUT command is only to be used within a page.
2. Any commands that are not in the above table are considered as undefined and are prohibited as inputs.
3. Do not cross plane address boundaries when using Copy Back Read and Program for copy back.

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9. DEVICE OPERATIONS
9.1 READ Operation
9.1.1 PAGE READ (00h-30h)

When the device powers on, 00h command is latched to command register. Therefore, system
only issues five address cycles and 30h command for initial read from the device. This operation
can also be entered by writing 00h command to the command register, and then write five address
cycles, followed by writing 30h command. After writing 30h command, the data is transferred from
NAND array to Data Register during tR. Data transfer progress can be done by monitoring the
status of the RY/#BY signal output. RY/#BY signal will be LOW during data transfer. Also, there
is an alternate method by using the READ STATUS (70h) command. If the READ STATUS
command is issued during read operation, the Read (00h) command must be re-issued to read
out the data from Data Register. When the data transfer is complete, RY/#BY signal goes HIGH,
and the data can be read from Data Register by toggling #RE. Read is sequential from initial
column address to the end of the page. (See Figure 9-1)
CLE
#CE
#WE
ALE
#RE
l/Ox 00h Address (5cycles) 30h Data Output ( Serial Access )
tR
RY/#BY
Don’t care
Figure 9-1 Page Read Operations
9.1.2 TWO PLANE READ (00h-00h-30h)

TWO PLANE READ (00h-00h-30h) transfers two pages data from the NAND array to the data
registers. Each page address have to be indicated different plane address.
To set the TWO PLANE READ mode, write the 00h command to the command register, and then
write five address cycles for plane 0. Secondly, write the 00h command to the command register,
and five address cycles for plane 1. Finally, the 30h command is issued. The first-plane and
second-plane addresses must be identical for all of issued address except plane address.
After the 30h command is written, page data is transferred from both planes to their respective
data registers in tR. RY/#BY goes LOW While these are transfered,. When the transfers are
complete, RY/#BY goes HIGH. To read out the data, at first, system writes TWO PLANE
RAMDOM DATA READ (06h-E0h) command to select a plane, next, repeatedly pulse #RE to
read out the data from selected plane. To change the plane address, issues TWO PLANE
RANDOM DATA READ (06h-E0h) command to select the another plane address, then repeatedly
pulse #RE to read out the data from the selected plane data register.

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Alternatively, data transfers can be monitored by the READ STATUS (70h). When the transfers
are complete, status register bit 6 is set to 1. To read data from the first of the two planes even
when READ STATUS ENHANCED (78h) command is used, the system must issue the TWO
PLANE RANDOM DATA READ (06h-E0h) command at first and pulse #RE repeatedly.
Write a TWO PLANE RANDOM DATA READ (06h-E0h) command to select the other plane ,after
the data cycle is complete. pulse #RE repeatedly to output the data beginning at the specified
column address,
During TWO PLANE READ operation,the READ STATUS ENHANCED (78h) command is
prohibited.
CLE
#WE
ALE
#RE
Plane address M Plane address M
Col Col Row Row Row Col Col Row Row Row
I/O× 00h Add1 Add2 Add1 Add2 Add3 00h Add1 Add2 Add1 Add2 Add3 30h
Column address J Plane 0 address Column address J Plane 1 address

tR
RY/#BY
CLE
#WE
ALE
#RE
I/O× 06h Address (5cycles) E0h DOUT0 DOUT1 DOUTn

Plane 0 or Plane 1 address Selected Plane data
RY/#BY

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9.1.3 RANDOM DATA OUTPUT (05h-E0h)

The RANDOM DATA OUTPUT allows the selection of random column addresses to read out data
from a single or multiple of addresses. The use of the RANDOM DATA OUTPUT command is
available after the PAGE READ (00h-30h) sequence by writing the 05h command following by
the two cycle column address and then the E0h command. Toggling #RE will output data
sequentially. The RANDOM DATA OUTPUT command can be issued multiple times, but limited
to the current loaded page.
tR
RY/#BY
#RE
I/Ox 00h Address(5cycles) 30h Data out 05h Address(2cycles) E0h Data out
Figure 9-2 Random Data Output
9.1.3.1. TWO PLANE RANDOM DATA OUTPUT (06h-E0h)

TWO PLANE RANDOM DATA READ (06h-E0h) command can indicate to specified plane and
column address on data register . This command is accepted by a device when it is ready.
Issuing 06h to the command register, two column address cycles, three row address cycles, E0h
are followed, this enables data output mode on the address device’s data register at the specified
column address. After the E0h command , the host have to wait at least tWHR before requesting
data output. The selected device is in data output mode until another valid command is issued.
The TWO PLANE RANDOM DATA READ (06h-E0h) command is used to select the data register
to be enabled for data output. When the data output is complete on the selected plane, the
command can be issued again to start data output on another plane.
If there is a need to update the column address without selecting a new data register, the
RANDOM DATA READ (05h-E0h) command can be used instead.
CLE
#CE
#WE
ALE
#RE
I/O× Data Out 06h Address (5cycles) E0h Data Out
Figure 9-3 Two Plane Random Data Output

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9.1.4 READ ID (90h)

READ ID command is comprised of two modes determined by the input address, device (00h) or
ONFI (20h) identification information. To enter the READ ID mode, write 90h to the Command
Register followed by a 00h address cycle, then toggle #RE for 5 single byte cycles, W29N02KV.
The pre-programmed code includes the Manufacturer ID, Device ID, and Product-Specific
Information (see Table 9.1). If the READ ID command is followed by 20h address, the output code
includes 4 single byte cycles of ONFI identifying information (See Table 9.2). The device remains
in the READ ID Mode until the next valid command is issued.
CLE
#CE
#WE
tAR
ALE
#RE
tWHR
tREA
I/Ox 90h 00h Byte0 Byte1 Byte2 Byte3 Byte4
(or 20h)
Address 1 Cycle
Figure 9-4 Read ID

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# of 1st 2nd 3rd 4th 5th

Byte/Cycles Byte/Cycle Byte/Cycle Byte/Cycle Byte/Cycle Byte/Cycle
W29N02KV EFh DAh 10h 95h 07h
Page Size: 2KB
Two Plane Spare Area Size:128B
Description MFR ID Device ID Operation BLK Size w/o Spare:128KB
Supported Organized:x8
Serial Access:25ns
Table 9-1 Device ID and Configuration Codes for Address 00h
1st 2nd 3rd 4th

# of Byte/Cycles Byte/Cycle Byte/Cycle Byte/Cycle Byte/Cycle
Code 4Fh 4Eh 46h 49h
Table 9-2 ONFI Identifying Codes for Address 20h
9.1.5 READ PARAMETER PAGE (ECh)

READ PARAMETER PAGE can read out the device’s parameter data structure, such as,
manufacturer information, device organization, timing parameters, key features, and other
pertinent device parameters. The data structure is stored with at least three copies in the device’s
parameter page. Figure 9-9 shows the READ PARAMETER PAGE timing. The RANDOM DATA
OUTPUT (05h-E0h) command is supported during data output.
CLE
#WE
ALE
#RE
I/Ox ECh 00h P00 P10 ・・・ P01 P11 ・・・

tR
RY/#BY
Figure 9-5 Read Parameter Page

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Byte Description Value

0-3 Parameter page signature 4Fh, 4Eh, 46h, 49h
4-5 Revision number 02h, 00h
6-7 Features supported 18h, 00h
8-9 Optional commands supported 3Ch, 00h
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
10-31 Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
57h, 49h, 4Eh, 42h, 4Fh, 4Eh, 44h, 20h, 20h, 20h, 20h,
32-43 Device manufacturer
20h
57h, 32h, 39h, 4Eh, 30h, 32h, 4Bh, 56h, 20h, 20h, 20h,
44-63 Device model W29N02KV
20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h
64 Manufacturer ID EFh
65-66 Date code 00h, 00h
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
67-79 Reserved
00h, 00h
80-83 # of data bytes per page 00h, 08h, 00h, 00h
84-85 # of spare bytes per page 80h, 00h
86-89 # of data bytes per partial page 00h, 02h, 00h, 00h
90-91 # of spare bytes per partial page 20h, 00h
92-95 # of pages per block 40h, 00h, 00h, 00h
96-99 # of blocks per unit 00h, 08h, 00h, 00h
100 # of logical units 01h
101 # of address cycles 23h
102 # of bits per cell 01h
103-104 Bad blocks maximum per unit 28h, 00h
105-106 Block endurance 01h, 05h
Guaranteed valid blocks at beginning
107 01h
of target
Block endurance for guaranteed valid
108-109 00h, 00h
blocks
110 # of programs per page 04h
111 Partial programming attributes 00h
112 # of ECC bits 08h
113 # of interleaved address bits 01h
114 Interleaved operation attributes 00h
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
115-127 Reserved
00h, 00h
128 I/O pin capacitance 0Ah
129-130 Timing mode support 1Fh, 00h
131-132 Program cache timing 00h, 00h

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Byte Description Value

133-134 Maximum page program time BCh, 02h
135-136 Maximum block erase time 10h, 27h
137-138 Maximum random read time 19h, 00h
139-140 tCCS minimum 3Ch, 00h
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
141-163 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h
164-165 Vendor specific revision # 01h,00h
166-253 Vendor specific 00h
254-255 Integrity CRC 04h, C9h
256-511 Value of bytes 0-255
512-767 Value of bytes 0-255
>767 Additional redundant parameter pages
Table 9-3 Parameter Page Output Value
9.1.6 READ STATUS (70h)

The W29N02KV has an 8-bit Status Register which can be read during device operation. Refer
to Table 9.3 for specific Status Register definitions. After writing 70h command to the Command
Register, read cycles will only read from the Status Register. The status can be read from I/O[7:0]
outputs, as long as #CE and #RE are LOW. Note; #RE does not need to be toggled for Status
Register read. The Command Register remains in status read mode until another command is
issued. To change to normal read mode, issue the PAGE READ (00h) command. After the PAGE
READ command is issued, data output starts from the initial column address.
#CE
tCLR
CLE
#WE tREA
#RE
I/Ox 70h Status Output
Figure 9-6 Read Status Operation

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SR bit Page Read Page Program Block Erase Definition
0=Successful
Program/Erase
I/O 0 Not Use Pass/Fail Pass/Fail
1=Error
in Program/Erase
I/O 1 Not Use Not Use Not Use Don’t cared

Ready = 1
I/O 6 Ready/Busy Ready/Busy Ready/Busy
Busy = 0
Unprotected = 1
I/O 7 Write Protect Write Protect Write Protect
Protected = 0
Table 9-4 Status Register Bit Definition

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9.1.7 READ STATUS ENHANCED (78h)

The READ STATUS ENHANCED (78h) command returns the status of the addressed plane on
a target even when it is busy (SR BIT 6 = 0).
Writing 78h to the command register, followed by three row address cycles containing the page,
plane and block addresses that is same as executed addresses, puts the device into read status
mode. The device stays in this mode until another valid command is issued
The device status is returned when the host requests data output. The SR BIT 6 and SR bit 5 bits
of the status register are shared for all planes on the device. The SR BIT 1 and SR BIT 0 (SR
bit0) bits are specific to the plane specified in the row address.
The READ STATUS ENHANCED (78h) command also enables the device for data output. To
begin data output following a READ operation after the device is ready (SR BIT 6 = 1), issue the
READ MODE (00h) command, then begin data output. If the host needs to change the data
register that will output data, use the TWO PLANE RANDOMDATA READ (06h-E0h) command
after the device is ready
Use of the READ STATUS ENHANCED (78h) command is prohibited when OTP mode is enabled.
It is also prohibited following some of the other reset, identification.
CLE
#CE
#WE
ALE
#RE
I/O× 78h Address (3cycles) Status Output
Figure 9-7 Read Status Enhanced (78h) Operation

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9.1.8 READ UNIQUE ID (EDh)

The W29N02KV NAND Flash device has a method to uniquely identify each NAND Flash device
by using the READ UNIQUE ID command. The format of the ID is limitless, but the ID for every
NAND Flash device manufactured, will be guaranteed to be unique.
Numerous NAND controllers typically use proprietary error correction code (ECC) schemes. In
these cases Winbond cannot protect unique ID data with factory programmed ECC. However, to
ensure data reliability, Winbond will program the NAND Flash devices with 16 bytes of unique ID
code, starting at byte 0 on the page, immediately followed by 16 bytes of the complement of that
unique ID. The combination of these two actions is then repeated 16 times. This means the final
copy of the unique ID will resides at location byte 511. At this point an XOR or exclusive operation
can be performed on the first copy of the unique ID and its complement. If the unique ID is good,
the results should yield all the bits as 1s. In the event that any of the bits are 0 after the XOR
operation, the procedure can be repeated on a subsequent copy of the unique ID data.
CLE
#WE
ALE
#RE
I/Ox EDh 00h Byte0 Byte1 Byte14 Byte15
tR Unique ID data
RY/#BY
Figure 9-8 Read Unique ID

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9.2 PROGRAM Operation

9.2.1 PAGE PROGRAM (80h-10h)
The W29N02KV Page Program command will program pages sequentially within a block, from
the lower order page address to higher order page address. Programming pages out of sequence
is prohibited. The W29N02KV supports partial-page programming operations up to 4 times before
an erase is required if partitioning a page. Note; programming a single bit more than once without
first erasing it is not supported.
9.2.2 SERIAL DATA INPUT (80h)

Page Program operation starts with the execution of the Serial Data Input command (80h) to the
Command Register, following next by inputting five address cycles and then the data is loaded.
Serial data is loaded to Data register with each #WE cycle. The Program command (10h) is written
to the Command Register after the serial data input is finished. At this time the internal write state
controller automatically executes the algorithms for program and verifies operations. Once the
programming starts, determining the completion of the program process can be done by
monitoring the RY/#BY output or the Status Register Bit 6, which will follow the RY/#BY signal.
RY/#BY will stay LOW during the internal array programming operation during the period of
(tPROG). During page program operation, only two commands are available, READ STATUS
(70h) and RESET (FFh). When the device status goes to the ready state, Status Register Bit 0
(I/O0) indicates whether the program operation passed (Bit0=0) or failed (Bit0=1), (see Figure 9-
13). The Command Register remains in read status mode until the next command is issued.
tPROG
RY/#BY
I/Ox 80h Address (5cycles) Din 10h 70h Status

I/O0=0pass
I/O0=1fail
Figure 9-9 Page Program

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9.2.3 RANDOM DATA INPUT (85h)

After the Page Program (80h) execution of the initial data has been loaded into the Data register,
if the need for additional writing of data is required, using the RANDOM DATA INPUT (85h)
command can perform this function to a new column address prior to the Program (10h) command.
The RANDOM DATA INPUT command can be issued multiple times in the same page (See
Figure 9-14).
CLE
#CE
#WE
ALE
#RE
tPROG
RY/#BY
Address
I/Ox 80h Address (5cycles) Din 85h (2cycles) Din 10h 70h Status
Don’t care
Figure 9-10 Random Data Input

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9.2.4 TWO PLANE PAGE PROGRAM

TWO PLANE PAGE PROGRAM command make it possible for host to input data to the
addressed plane's data register and queue the data register to be moved to the NAND Flash
array.
This command can be issued several times. Each time a new plane address is specified that
plane is also queued for data transfer. To input data for the final plane and to begin the program
operation for all previously queued planes, the PAGE PROGRAM command have to be issued.
All of the queued planes will move the data to the NAND Flash array. when it is ready (SR BIT 6
= 1),this command is accepted.
At the block and page address is specified, input a page to the data register and queue it to be
moved to the NAND Flash array ,the 80h is issued to the command register. Unless this command
has been preceded by a TWO PLANE PAGE PROGRAM command, issuing the 80h to the
command register clears all of the data registers' contents on the selected target. Write five
address cycles containing the column address and row address; data input cycles follow. Serial
data is input beginning at the column address specified. At any time, while the data input cycle,
the RANDOM DATA INPUT (85h) command can be issued. When data input is complete, write
11h to the command register. The device will go busy (SR BIT 6 = 0, SR BIT 5 = 0) for tDBSY.
To ascertain the progress of tDBSY, the host can monitor the target's RY/#BY signal or, the status
operations (70h, 78h) can be used alternatively. When the device status shows that it is ready
(SR BIT 6 = 1), additional TWO PLANE PAGE PROGRAM commands can be issued to queue
additional planes for data transfer, then, the PAGE PROGRAM command can be issued.
When the PAGE PROGRAM command is used as the final command of a two plane program
operation, data is transferred from the data registers to the NAND Flash array for all of the
addressed planes during tPROG. When the device is ready (SR BIT 6 = 1, SR BIT 5 = 1), the
host should check the status of the SR BIT 0 for each of the planes to verify that programming
completed successfully.
When system issues TWO PLANE PAGE PROGRAM and PAGE PROGRAM commands, READ
STATUS (70h) command can confirm whether the operation(s) passed or failed. If the status after
READ STATUS (70h) command indicates an error (SR BIT 0 = 1 and/or SR BIT 1 = 1), READ
STATUS ENHANCED (78h) command can be determined which plane is failed.
TWO PLANE PROGRAM commands require five-cycle addresses, one address indicates the
operational plane. These addresses are subject to the following requirements:
• The column address bits must be valid address for each plane
• The plane select bit, A18, must be set to “L” for 1st address input, and set to “H” for 2nd address
input.
• The page address (A17-A12) and block address (A28-A19) of first input are don’t care. It follows
secondary inputted page address and block address.
Two plane operations must be same type operation across the planes; for example, it is not
possible to perform a PROGRAM operation on one plane with an ERASE operation on another.

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tPROG
tDBSY (Program busy time)
RY/#BY
Busy Busy
※
l/Ox 80h Address Inputs Data Input 11h 81h Address Inputs Data Input 10h 70h SR0
Page program A0-A11=Valid Confirm Multiplane Page A0-A11=Valid Confirm Read Status
Setup code A12-A17=set to `Low` Code Program setup A12-A17=Valid Code Register
A18=set to `Low` code A18=set to `High`
A19-A28=set to `Low` A19-A28=Valid
1)The same row address, except for A18, is applied to the two blocks.
2)Any command between 11h and 81h is prohibited except 70h,78h,and FFh
※81h:Traditional Protocol 80h:ONFI Protocol
80h 11h 81h 10h

Data
Input
FirstPlane Second Plane
(1024 block) (1024 block)
Block 0 Block 1
Block 2 Block 3
:
:
Block 2044 Block 2045

Block 2046 Block 2047
Figure 9-11 Two Plane Page Program
9.3 COPY BACK Operation

Copy Back operations require two command sets. Issue a READ for COPY BACK (00h-35h)
command first, then the PROGRAM for COPY BACK (85h-10h) command. Copy back operations
are only supported within a same plane.
9.3.1 READ for COPY BACK (00h-35h)

The READ for COPY BACK command is used together with the PROGRAM for COPY BACK
(85h-10h) command. To start execution, READ for COPY BACK (00h) command is written to the
Command Register, followed by the five cycles of the source page address. To start the transfer
of the selected page data from the memory array to the Data register, write the 35h command to
the Command Register.
After execution of the READ for COPY BACK command sequence and RY/#BY returns to HIGH
marking the completion of the operation, the transferred data from the source page into the Data
register may be read out by toggling #RE. Data is output sequentially from the column address
that was originally specified with the READ for COPY BACK command. RANDOM DATA
OUTPUT (05h-E0h) commands can be issued multiple times without any limitation after READ
for COPY BACK command has been executed (see Figures 9-19 and 9-20).
At this point the device is in ready state to accept the PROGRAM for COPY BACK command.

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9.3.2 PROGRAM for COPY BACK (85h-10h)

After the READ for COPY BACK command operation has been completed and RY/#BY goes
HIGH, the PROGRAM for COPY BACK command can be written to the Command Register. The
command results in the transfer of data from the Data register to the Data Register, then internal
operations start programming of the new destination page. The sequence would be, write 85h to
the Command Register, followed by the five cycle destination page address to the NAND array.
Next write the 10h command to the Command Register; this will signal the internal controller to
automatically start to program the data to new destination page. During this programming time,
RY/#BY will LOW. The READ STATUS command can be used instead of the RY/#BY signal to
determine when the program is complete. When Status Register Bit 6 (I/O6) equals to “1”, Status
Register Bit 0 (I/O0) will indicate if the operation was successful or not.
The RANDOM DATA INPUT (85h) command can be used during the PROGRAM for COPY BACK
command for modifying the original data. Once the data is copied into the Data register using the
READ for COPY BACK (00h-35h) command, follow by writing the RANDOM DATA INPUT (85h)
command, along with the address of the data to be changed. The data to be changed is placed
on the external data pins. This operation copies the data into the Data register. Once the 10h
command is written to the Command Register, the original data and the modified data are
transferred to the Data Register, and programming of the new page commences. The RANDOM
DATA INPUT command can be issued numerous times without limitation, as necessary before
starting the programming sequence with 10h command.
Since COPY BACK operations do not use external memory and the data of source page might
include a bit errors, a competent ECC scheme should be developed to check the data before
programming data to a new destination page.

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9.3.3 TWO PLANE READ for COPY BACK

To improve read through rate, TWO PLANE READ for COPY BACK operation is copied data
concurrently from one or two plane to the specified data registers.
TWO PLANE PROGRAM for COPY BACK command can move the data in two pages from the
data registers to different pages. This operation improves system performance than PROGRAM
for COPY BACK operation.
9.3.4 TWO PLANE PROGRAM for COPY BACK

Function of TWO PLANE PROGRAM for COPY BACK command is equal to TWO-PLANE PAGE
PROGRAM command, except that when 85h is written to the command register, then data
register contents are not cleared. Refer to TWO-PLANE PAGE PROGRAM for more details
features.

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CLE
#CE
#WE
ALE
#RE
Data output Address Data Output Status

I/ Ox 00h Address (5cycles) 35h 05h (2cycles) E0h 85h Address(5cycles) 10h 70h Output
No limitation
Optional
tR tPROG
RY / # BY
Don’t care
Figure 9-12 Program for copy back Operation
CLE
#CE
#WE
ALE
#RE
tR tPROG
RY/#BY
Address Status
I/Ox 00h Address(5Cycles) 35h DataOutput 85h Address(5cycles) Data Input 85h (2cycles) Data Input 10h 70h Output
No limitation
Optional
Don’t care
Figure 9-13 Copy Back Operation with Random Data Input

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tR
RY/#BY
#RE
00h Address(5cycles) 00h Address(5cycles) 35h 06h Address(5cycles) E0h

I/O×
Plane 0 source Plane 1 source Plane 0 or Plane 1 source address
1
RY/#BY
#RE
I/O× Data Output 05h Address(2cycles) E0h Data Output

Data from selected Plane Selected Plan e Data from selected plane 2
colu mn address From new column address
1
Optional
tDBSY tPROG
RY/#BY
#RE
85h Address(5cycles) 11h 85h Address(5cycles) 10h 70h Status

I/O×
Plane 0 destination Plane 1 destination
Figure 9-14 Two Plane Copy Back
tR
RY/#BY
I/O× 00h Address(5cycles) 00h Address(5cycles) 35h 85h Address(5cycles) data 85h Address(2cycles) Data 11h
Plane 0 source Plane 1 source Unlimited number
of repetitions
1
Plane 0 destination optional
tDBSY tPROG
RY/#BY
I/O× 85h Address(5cycles) 10h 70h Status

Plane 1 destination
Figure 9-15 Two Plane Copy Back with Random Data Input

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Read Read Copy back Copy back

code code code code Read Status Register
Address Address Address ※ Address
l/O 00h (5 cycles) 35h 00h (5 cycles) 35h 85h (5 cycles) 11h
35h 85h (5 cycles) 10h 70h SR0
Col Add1,2 Col Add1,2 Col Add.1,2 Col Add.1,2

Row Add1,2,3 Row Add1, 2,3 Row Add.1,2,3 Row Add.1,2,3
Source address on Plane0 Source address on Plane1 Destination address on Plane0 Source address on Plane1
A0 - A11 = don’t care A0 - A11 = set to `Low’
A12-A17 = don’t care A12-A17 = Valid
A18 = set to `Low’ A18 = set to `High’
A19- A28 = don’t care A19-A28 = Valid
tR tR tDBSY tPROG
RY/#BY
Busy Busy Busy Busy
Single plane copy back read can be used to two plane operation.
First plane Second plane

SourcePage ※85h:ONFI Protocol
SourcePage 81h:Traditional Protocol
(1):Read for copy back on first plane

(2):Read for copy back on second plane
TargetPage TargetPage (3):Two-plane copy back program
(1) (3) (2) (3)
Main area Spare area Main area Spare area
Figure 9-16 Two Plane Program for Copy Back

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9.4 BLOCK ERASE Operation
9.4.1 BLOCK ERASE (60h-D0h)

Erase operations happen at the architectural block unit. This W29N02KV has 2048 erase blocks.
Each block is organized into 64 pages (x8:2176 bytes/page, x16:1088 words/page), 132K bytes
(x8:128K + 8K bytes, x16:64 K+ 4Kwords)/block. The BLOCK ERASE command operates on a
block by block basis.
Erase Setup command (60h) is written to the Command Register. Next, the three cycle block
address is written to the device. The page address bits are loaded during address block address
cycle, but are ignored. The Erase Confirm command (D0h) is written to the Command Register
at the rising edge of #WE, RY/#BY goes LOW and the internal controller automatically handles
the block erase sequence of operation. RY/#BY goes LOW during Block Erase internal operations
for a period of tBERS,
The READ STATUS (70h) command can be used for confirm block erase status. When Status
Register Bit6 (I/O6) becomes to “1”, block erase operation is finished. Status Register Bit0 (I/O0)
will indicate a pass/fail condition (see Figure 9-24).
CLE
#CE
#WE
ALE
#RE
I/Ox 60h Address Input (3cycles) D0h 70h Status Output

I/ O 0 = 0 pass
tBERS I/ O 0 = 1 fail
RY/#BY
Don’t care
Figure 9-17 Block Erase Operation

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9.4.2 TWO PLANE BLOCK ERASE

TWO PLANE BLOCK ERASE (60h-D1h) command indicates two blocks in the specified plane
that is to be erased. To start ERASE operation for indicated blocks in the specified plane, write
the BLOCK ERASE (60h-D0h) command.
To indicate a block to be erased, writing 60h to the command register, then, write three address
cycles containing the row address, the page address is ignored. By writing D1h command to
command register, the device will go busy (SR BIT 6 = 0, SR BIT 5 = 0) for tDBSY.
To confirm busy status during tDBSY, the host can monitor RY/#BY signal. Instead, system can
use READ STATUS (70h) or READ STATUS ENHANCED (78h) commands. When the status
shows ready (SR BIT 6 = 1, SR BIT 5 = 1), additional TWO PLANE BLOCK ERASE commands
can be issued for erasing two blocks in a specified plane.
When system issues TWO PLANE BLOCK ERASE (60h-D1h), and BLOCK ERASE (60h-D0h)
commands, READ STATUS (70h) command can confirm whether the operation(s) passed or
failed. If the status after READ STATUS (70h) command indicates an error (SR BIT 0 = 1), READ
STATUS ENHANCED (78h) command can be determined which plane is failed.
TWO PLANE BLOCK ERASE commands require three cycles of row addresses; one address
indicates the operational plane. These addresses are subject to the following requirements:
• The plane select bit, A18, must be different for each issued address.
• Block address (A28-A19) of first input is don’t care. It follows secondary inputted block address.
Two plane operations must be same type operation across the planes; for example, it is not
possible to perform a PROGRAM operation on one plane with an ERASE operation on another.
CLE
#CE
#WE
ALE
#RE
I/Ox 60h R1A R2A R3A D1h 60h R1B R2B R3B D0h
tDBSY tBERS
RY/#BY
Busy Busy
Don’t care
Figure 9-18 Two Plane Block Erase Operation

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9.5 RESET Operation
9.5.1 RESET (FFh)

READ, PROGRAM, and ERASE commands can be aborted by the RESET (FFh) command
during the time the W29N02KV is in the busy state. The Reset operation puts the device into
known status. The data that is processed in either the programming or erasing operations are no
longer valid. This means the data can be partially programmed or erased and therefore data is
invalid. The Command Register is cleared and is ready to accept next command. The Data
Register and Data register contents are marked invalid.
The Status Register indicates a value of E0h when #WP is HIGH; otherwise a value of 60h is
written when #WP is LOW. After RESET command is written to the command register, RY/#BY
goes LOW for a period of tRST (see Figure 9-20).
CLE
#CE
tWB
#WE
tRST
RY/#BY
I/Ox FFh
RESET
command
Figure 9-19 Reset Operation

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9.6 FEATURE OPERATION

The GET FEATURES (EEh) and SET FEATURES (EFh) commands are used to change the
NAND Flash device behavior from the default power on settings. These commands use a one-
byte feature address to determine which feature is to be read or modified. A range of 0 to 255
defines all features; each is described in the features table (see Table 9.5 thru 9.7). The GET
FEATURES (EEh) command reads 4-Byte parameter in the features table (See GET FEATURES
function). The SET FEATURES (EFh) command places the 4-Byte parameter in the features table
(See SET FEATURES function).
When a feature is set, meaning it remains active by default until the device is powered off. The
set feature remains the set even if a RESET (FFh) command is issued.
Feature address Description
00h N.A
02h-7Fh Reserved
80h Vendor specific parameter : Programmable I/O drive strength
81h Vendor specific parameter : Programmable RY/#BY pull-down strength
82h-FFh Reserved
Table 9-5 Features

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Feature Address 80h: Programmable I/O Drive Strength
Sub feature Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes
parameter
P1
I/O Full (default) Reserved (0) 0 0 00h 1

drive strength Three-quarters Reserved (0) 0 1 01h
One-half Reserved (0) 1 0 02h
One-quarter Reserved (0) 1 1 03h
P2
Reserved (0) 00h
P3
Reserved (0) 00h
P4
Reserved (0) 00h
Table 9-6 Feature Address 80h

Note:
1. The default drive strength setting is Full strength. The Programmable I/O Drive Strength mode is used
to change from the default I/O drive strength. Drive strength should be selected based on expected
loading of the memory bus. This table shows the four supported output drive-strength settings. The
device returns to the default drive strength mode when a power cycle has occurred. AC timing
parameters may need to be relaxed if I/O drive strength is not set to full.

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W29N02KVxxAE
Feature Address 81h: Programmable RY/#BY Pull-down Strength
Sub feature Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes
parameter
P1
RY/#BY Full (default) Reserved (0) 0 0 00h 1

pull-down Three-quarters Reserved (0) 0 1 01h
strength
One-half Reserved (0) 1 0 02h
One-quarter Reserved (0) 1 1 03h
P2
Reserved (0) 00h
P3
Reserved (0) 00h
P4
Reserved (0) 00h
Table 9-7 Feature Address 81h

Note:
1. The default programmable RY/#BY pull-down strength is set to Full strength. The pull-down strength is
used to change the RY/#BY pull-down strength. RY/#BY pull-down strength should be selected based
on expected loading of RY/#BY. The four supported pull-down strength settings are shown. The device
returns to the default pull-down strength when a power cycle has occurred.

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9.6.1 GET FEATURES (EEh)

The GET FEATURES command returns the device feature settings including those previously set
by the SET FEATURES command. To use the Get Feature mode write the command (EEh) to
the Command Register followed by the single cycle byte Feature Address. RY/#BY will goes LOW
for the period of tFEAT. If Read Status (70h) command is issued for monitoring the process
completion status, Read Command (00h) has to be executed to re-establish data output mode.
Once, RY/#BY goes HIGH, the device feature settings can be read by toggling #RE. The device
remains in Feature Mode until another valid command is issued to Command Register. See
Figure 9-21.
CLE
#CE
#WE
ALE
#RE
I/Ox EEh FA P1 P2 P3 P4
Feature address
1 cycle
tFEAT
RY/#BY
Figure 9-20 Get Feature Operation

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9.6.2 SET FEATURES (EFh)

The SET FEATURES command sets the behavior parameters by selecting a specified feature
address. To change device behavioral parameters, execute Set Feature command by writing EFh
to the Command Register, followed by the single cycle feature address. Each feature parameter
(P1-P4) is latched at the rising edge of each #WE. The RY/#BY signal will go LOW during the
period of tFEAT while the four feature parameters are stored. The Read Status (70h) command
can be issued for monitoring the progress status of this operation. The parameters are stored in
device until the device goes through a power on cycle. The device remains in feature mode until
another valid command is issued to Command Register.
CLE
#CE
#WE
ALE
#RE
tADL
I/Ox EFh FA P1 P2 P3 P4
tWB tFEAT
RY/#BY
Figure 9-21 Set Feature Operation

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9.7 ONE TIME PROGRAMMABLE (OTP) Area

The device has One-Time Programmable (OTP) memory area comprised of a number of pages
(2176 bytes/page) (1088words/page). This entire range of pages is functionally guaranteed. Only
the OTP commands can access the OTP area. When the device ships from Winbond, the OTP
area is in an erase state (all bits equal “1”). The OTP area cannot be erased, therefore protecting
the area only prevent further programming. Contact to Winbond for using this feature.

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9.8 WRITE PROTECT

#WP pin can enable or disable program and erase commands preventing or allowing program
and erase operations. Figure 9-29 to 9-34 shows the enabling or disabling timing with #WP setup
time (tWW) that is from rising or falling edge of #WP to latch the first commands. After first
command is latched, #WP pin must not toggle until the command operation is complete and the
device is in the ready state. (Status Register Bit5 (I/O5) equal 1)
# WE
tWW
I /Ox 60h D0h
#WP
RY/#BY
Figure 9-22 Erase Enable
#WE
tWW
I/Ox 60h D0h
#WP
RY/#BY
Figure 9-23 Erase Disable
#WE
tWW
I/Ox 80 h 10h
( or 15h )
#WP
RY/#BY
Figure 9-24 Program Enable

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#WE
tWW
I/Ox 80 h 10h
( or 15h)
#WP
RY/#BY
Figure 9-25 Program Disable
#WE
tWW
I/Ox 85h 10h
# WP
RY/#BY
Figure 9-26 Program for Copy Back Enable
#WE
tWW
I/Ox 85h 10 h
# WP
RY/#BY
Figure 9-27 Program for Copy Back Disable

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9.9 BLOCK LOCK

The device has block lock feature that can protect the entire device or user can indicate a ranges
of blocks from program and erase operations. Using this feature offers increased functionality and
flexibility data protection to prevent unexpected program and erase operations. Contact to
Winbond for using this feature.

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10. ELECTRICAL CHARACTERISTICS
10.1 Absolute Maximum Ratings (3.3V)

PARAMETERS SYMBOL CONDITIONS RANGE UNIT
Supply Voltage VCC –0.6 to +4.6 V
Voltage Applied to Any Pin VIN Relative to Ground –0.6 to +4.6 V
Storage Temperature TSTG –65 to +150 °C
Short circuit output current, I/Os 5 mA
Table 10-1 Absolute Maximum Ratings
Notes:
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -
2.0V for periods <30ns.
2. Maximum DC voltage on input/output pins is Vcc+0.3V which, during transitions, may overshoot to
Vcc+2.0V for periods <20ns.
3. This device has been designed and tested for the specified operation ranges. Proper operation outside
of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability.
Exposure beyond absolute maximum ratings may cause permanent damage.
10.2 Operating Ranges (3.3V)

SPEC
PARAMETER SYMBOL CONDITIONS UNIT
MIN MAX
Supply Voltage VCC 2.7 3.6 V
Industrial Grade -40 +85 °C

Ambient Temperature,
TA
Operating
Industrial Plus Grade -40 +105 °C
Table 10-2 Operating Ranges

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10.3 Device Power-up Timing

The device is designed to avoid unexpected program/erase operations during power transitions.
When the device is powered on, an internal voltage detector disables all functions whenever Vcc
is below about 2V at 3V device. Write Protect (#WP) pin provides hardware protection and is
recommended to be kept at VIL during power up and power down. A recovery time of minimum
1ms is required before internal circuit gets ready for any command sequences (See Figure 10-1).
Vcc
#WP
#WE
1ms
(Min)
RY/#BY
5 ms (Max)
Undefined
Figure 10-1 Power ON/OFF Sequence

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10.4 DC Electrical Characteristics (3.3V)

SPEC
PARAMETER SYMBOL CONDITIONS UNIT
MIN TYP MAX
tRC= tRC MIN

Sequential Read current Icc1 #CE=VIL - 25 35 mA
IOUT=0mA
Program current Icc2 - - 25 35 mA
Erase current Icc3 - - 25 35 mA
#CE=VIH
Standby current (TTL) ISB1 - - 1 mA
#WP=0V/Vcc
Standby current (CMOS)

- 10 50 µA
Industrial Grade #CE=Vcc – 0.2V
ISB2
Standby current (CMOS) #WP=0V/Vcc
- 10 100 µA
Industrial Plus Grade
Input leakage current ILI VIN= 0 V to Vcc - - ±10 µA
Output leakage current ILO VOUT=0V to Vcc - - ±10 µA
I/O7~0, #CE,#WE,#RE,
Input high voltage VIH 0.8 x Vcc - Vcc + 0.3 V
#WP,CLE,ALE
Input low voltage VIL - -0.3 - 0.2 x Vcc V
Output high voltage(1) VOH IOH=-400µA 2.4 - - V
Output low voltage(1) VOL IOL=2.1mA - - 0.4 V
Output low current IOL(RY/#BY) VOL=0.4V 8 10 mA
Table 10-3 DC Electrical Characteristics

Note:
1. VOH and VOL may need to be relaxed if I/O drive strength is not set to full.
2. IOL (RY/#BY) may need to be relaxed if RY/#BY pull-down strength is not set to full

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10.5 AC Measurement Conditions (3.3V)

SPEC
PARAMETER SYMBOL UNIT
MIN MAX
Input Capacitance(1), (2) CIN - 10 pF
Input/Output Capacitance(1), (2) CIO - 10 pF
Input Rise and Fall Times TR/TF - 5 ns
Input Pulse Voltages - 0 to VCC V
Input/Output timing Voltage - Vcc/2 V
Output load (1) CL 1TTL GATE and CL=30pF -
Table 10-4 AC Measurement Conditions
Notes:
1. Verified on device characterization , not 100% tested
2. Test conditions TA=25’C, f=1MHz, VIN=0V

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10.6 AC Timing Characteristics for Command, Address and Data Input

(3.3V)
SPEC
MIN MAX
ALE to Data Loading Time tADL 70 - ns
ALE Hold Time tALH 5 - ns
ALE setup Time tALS 10 - ns
#CE Hold Time tCH 5 - ns
CLE Hold Time tCLH 5 - ns
CLE setup Time tCLS 10 - ns
#CE setup Time tCS 15 - ns
Data Hold Time tDH 5 - ns
Data setup Time tDS 10 - ns
Write Cycle Time tWC 25 - ns
#WE High Hold Time tWH 10 - ns
#WE Pulse Width tWP 12 - ns
#WP setup Time tWW 100 - ns
Table 10-5 AC Timing Characteristics for Command, Address and Data Input
Note:
1. tADL is the time from the #WE rising edge of final address cycle to the #WE rising edge of first data
cycle.

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10.7 AC Timing Characteristics for Operation (3.3V)

SPEC
MIN MAX
ALE to #RE Delay tAR 10 - ns
#CE Access Time tCEA - 25 ns
#CE HIGH to Output High-Z(1) tCHZ - 30 ns
CLE to #RE Delay tCLR 10 - ns
#CE HIGH to Output Hold tCOH 15 - ns
Output High-Z to #RE LOW tIR 0 - ns
Data Transfer from Cell to Data Register tR - 25 µs
READ Cycle Time tRC 25 - ns
#RE Access Time tREA - 20 ns
#RE HIGH Hold Time tREH 10 - ns
#RE HIGH to Output Hold tRHOH 15 - ns
#RE HIGH to #WE LOW tRHW 100 - ns
#RE HIGH to Output High-Z(1) tRHZ - 100 ns
#RE LOW to output hold tRLOH 5 - ns
#RE Pulse Width tRP 12 - ns
Ready to #RE LOW tRR 20 - ns
Reset Time (READ/PROGRAM/ERASE)(2) tRST - 5/10/500 µs
#WE HIGH to Busy(3) tWB - 100 ns
#WE HIGH to #RE LOW tWHR 60 - ns
Table 10-6 AC Timing Characteristics for Operation
Notes: AC characteristics may need to be relaxed if I/O drive strength is not set to “full.”
1. Transition is measured ±200mV from steady-state voltage with load. This parameter is sampled and not
100 % tested.
2. Do not issue new command during tWB, even if RY/#BY is ready.

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10.8 Program and Erase Characteristics

SPEC
TYP MAX
Number of partial page programs NoP - 4 cycles
Page Program time tPROG 250 700 µs
Busy Time for SET FEATURES /GET FEATURES tFEAT - 1 µs
Busy Time for program/erase at locked block tLBSY - 3 µs
Busy Time for OTP program when OTP is protected tOBSY - 30 µs
Block Erase Time tBERS 2 10 ms
Busy Time for Two Plane page program and Two Plane Block µs
tDBSY 0.5 1
Erase
Table 10-7 Program and Erase Characteristics

Note:
1. tCBSY maximum time depends on timing between internal program complete and data-in.

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11. TIMING DIAGRAMS
CLE
tCLS tCLH
tCS tCH
#CE
tWP
#WE
tALS tALH
ALE
tDS tDH
I/Ox Command
Don’t care
Figure 11-1 Command Latch Cycle
CLE
tCLS
tCS
tWC
#CE
tWP tWH
#WE
tALS tALH
ALE
tDS tDH
I/Ox Address
Don’t care Undefined
Figure 11-2 Address Latch Cycle

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W29N02KVxxAE
CLE
tCLH
#CE
tCH
tALS
ALE
tWC
tWP tWP tWP
#WE
tWH
tDS tDH tDS tDH tDS tDH
I/Ox Din 0 Din 1 Din Final1
Don’t care
Figure 11-3 Data Latch Cycle

Note:
1. Din Final = 2,175(x8)
tCEA
#CE
tREA tREA
tREA tCHZ
tRP tREH tCOH
#RE
tRHZ
tRHZ
tRHOH
I/Ox Dout Dout Dout
tRR tRC
RY/#BY
Don’t care
Figure 11-4 Serial Access Cycle after Read

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W29N02KVxxAE
#CE tCHZ
tRC
tRP tREH tCOH
#RE tRHZ
tREA tREA tRHOH
tRLOH
tCEA
I/Ox Dout Dout Dout
tRR
RY/#BY
Don’t care
Figure 11-5 Serial Access Cycle after Read (EDO)
tCLR
CLE tCLS tCLH
tCS
#CE
tCH
tWP
#WE tCEA tCHZ
tWHR tRP tCOH
#RE
tRHZ
tDS tDH tIR tREA tRHOH
I/Ox 70h Status

output
Don’t care
Figure 11-6 Read Status Operation

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W29N02KVxxAE
CLE
tCLR
#CE
tWC
#WE
tWB tAR
ALE
tR tRC tRHZ
#RE
tRR tRP
I/Ox 00h Address(5Cycles) 30h Dout
n
Dout
n+1
Dout
m
Busy
RY/#BY
Don’t care
Figure 11-7 Page Read Operation
CLE
#CE
#RE
ALE
tR
RY/#BY
#WE
I/Ox 00h Address (5 cycles) 30h Data output
Don’t care
tCEA
#CE
tREA tCHZ
#RE tCOH
I/Ox Out
Figure 11-8 #CE Don't Care Read Operation

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W29N02KVxxAE
CLE
tCLR
#CE
tWC
#WE tWB
tAR
tWHR
ALE
tRC tREA
#RE
tRR
I/Ox 00h 30h 05h E0h
Colu mn address n
tR Colu mn address m
RY/#BY Busy
Don’t care
Figure 11-9 Random Data Output Operation

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W29N02KVxxAE
Note:
1. See Table 9.1 for actual value.
CLE
#CE
#WE
tAR
ALE
#RE
tWHR tREA
I/Ox 90h 00h Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
(or 20h)
Address, 1 cycle
Figure 11-10 Read ID
CLE
#CE
tWC tADL
#WE
tWB tPROG tWHR
ALE
#RE
I/Ox 80h Col Col Row Row Row 10h 70h Status
add 1 add 2 add 1 add 2 add 3
SERIAL DATA 1 up to m Byte PROGRAM READ STATUS
INPUT command serial input command command
RY/#BY
x8 device:m = 2176 bytes
Don’t care
Figure 11-11 Page Program

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W29N02KVxxAE
CLE
#CE
#WE
ALE
I/Ox 80h Address(5 cycles) Data input 10h
tCS tCH
#CE
Don’t care
tWP
#WE
Figure 11-12 #CE Don't Care Page Program Operation
CLE
#CE
ｔWC tADL tADL

#WE
tWB
ALE
#RE
Col Col Row Row Row Din Din Col Col Din Din 10h Status
I/Ox 80h add 1 add 2 add1 add2 add3 ｎ N+1 85h add1 add2 ｎ N+1 70h
Serial Data
Serial INPUT Rand om Data Inpu t Column address Serial INPUT Program tPROG
Input Command Command Command
Command
RY/#BY
Don’t care
Figure 11-13 Page Program with Random Data Input

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W29N02KVxxAE
CLE
#CE
tADL
ｔWC
#WE
tWB tWB
ALE
#RE
Col Col Row Row Row Col Col Row Row Row Din Din
I/Ox 00h add1 add2 add1 add2 add3 35h 85h add1 add2 add1 add2 add3 1 n 10h 70h Status
Serial data INPU T Program tPROG
Command tR Command
RY/#BY
Bu sy
Don’t care
Figure 11-14 Copy Back
CLE
#CE
tWC
#WE
tWB tBERS
ALE
#RE
I/Ox 60h Address(3cycles) D0h 70h Status
ERASE READ STATUS

command command
RY/#BY Busy
BLOCK ERASE SETUP
command
Don’t care
Figure 11-15 Block Erase

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W29N02KVxxAE
CLE
#CE
#WE
tWB
tRST
RY/#BY
I/Ox FFh
RESET
command
Figure 11-16 Reset

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12. INVALID BLOCK MANAGEMENT
12.1 Invalid Blocks

The W29N02KV may have initial invalid blocks when it ships from factory. Also, additional invalid
blocks may develop during the use of the device. Nvb represents the minimum number of valid
blocks in the total number of available blocks (See Table 12.1). An invalid block is defined as
blocks that contain one or more bad bits. Block 0, block address 00h is guaranteed to be a valid
block at the time of shipment.
Parameter Symbol Min Max Unit
Valid block number Nvb 2008 2048 blocks
Table 12-1 Valid Block Number
12.2 Initial Invalid Blocks

Initial invalid blocks are defined as blocks that contain one or more invalid bits when shipped from
factory.
Although the device contains initial invalid blocks, a valid block of the device is of the same quality
and reliability as all valid blocks in the device with reference to AC and DC specifications. The
W29N02KV has internal circuits to isolate each block from other blocks and therefore, the invalid
blocks will not affect the performance of the entire device.
Before the device is shipped from the factory, it will be erased and invalid blocks are permanently
marked. The mark information cannot be erased. All initial invalid blocks are marked with non-
FFh at the first byte of spare area on the 1st or 2nd page. It should be checked for invalid blocks
by reading the marked locations, and create a table of initial invalid blocks as following flow chart.
Figure 12-1 Flow Chart of Create Initial Invalid Block Table

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W29N02KVxxAE
12.3 Error in Operation

Additional invalid blocks may develop in the device during its life cycle. Following the procedures
herein is required to guarantee reliable data in the device.
After each program and erase operation, check the status read to determine if the operation failed.
In case of failure, a block replacement should be done with a bad-block management algorithm.
The system has to use a minimum 8-bit ECC per 544 bytes of data to ensure data recovery.
Operation Detection and recommended procedure
Erase Status read after erase  Block Replacement

Program Status read after program  Block Replacement
Read Verify ECC  ECC correction
Table 12-2 Block Failure
Figure 12-2 Bad Block Replacement

Notes:
1. An error happens in the nth page of block A during program or erase operation.
2. Copy the data in block A to the same location of block B which is valid block.
3. Copy the nth page data of block A in the buffer memory to the nth page of block B.
4. Creating or updating bad block table for preventing further program or erase to block A.
12.4 Addressing in Program Operation

The pages within the block have to be programmed sequentially from LSB (least significant bit)
page to the MSB (most significant bit) within the block. The LSB is defined as the start page to
program, does not need to be page 0 in the block. Random page programming is prohibited.

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13. PACKAGE DIMENSIONS
13.1 TSOP 48-pin 12x20
1 48
E
b
c
D
HD
A2
A
 L
L1 A1 Y
MILLIMETER INCH
Symbol
MIN. NOM. MAX. MIN. NOM. MAX.
A 1.20 0.047
A1 0.05 0.002
A2 0.95 1.00 1.05 0.037 0.039 0.041
D 18.3 18.4 18.5 0.720 0.724 0.728
HD 19.8 20.0 20.2 0.780 0.787 0.795
E 11.9 12.0 12.1 0.468 0.472 0.476
b 0.17 0.22 0.27 0.007 0.009 0.011
c 0.10 0.21 0.004 0.008
e 0.50 0.020
L 0.50 0.60 0.70 0.020 0.024 0.028
L1 0.80 0.031
Y 0.10 0.004
 0 5 0 5
Figure 13-1 TSOP 48-PIN 12X20mm

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13.2 Fine-Pitch Ball Grid Array 48-Ball
Figure 13-2 Fine-Pitch Ball Grid Array 48-Ball

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13.3 Fine-Pitch Ball Grid Array 63-Ball
Figure 13-3 Fine-Pitch Ball Grid Array 63-Ball

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14. ORDERING INFORMATION
W 29N 02 K V S I A E
Winbond Standard Product
W: Winbond
Product Family
ONFI compatible NAND Flash memory
Density
02: 2 Gbit
Product Version
K
Supply Voltage and Bus Width

V: 2.7~3.6V and x8 device
Packages
S: TSOP 48
D: VFBGA-48
B: VFBGA-63
Temperature Ranges
I: -40 to 85'C
J: -40 to 105'C
Option Information
A: OTP Command Supported
(Contact Winbond for Option information)
Reserved
E: 8-bit ECC
Figure 14-1 Ordering Part Number Description

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15. VALID PART NUMBERS

The following table provides the valid part numbers for the W29N02KV NAND Flash Memory.
Please contact Winbond for specific availability by density and package type. Winbond NAND
Flash memories use a 12-digit Product Number for ordering.
Part Numbers for Industrial Grade:
PACKAGE
DENSITY VCC BUS PRODUCT NUMBER TOP SIDE MARKING
TYPE
S
2G-bit 3V X8 W29N02KVSIAE W29N02KVSIAE
TSOP-48
D
2G-bit 3V X8 W29N02KVDIAE W29N02KVDIAE
VFBGA-48
B
2G-bit 3V X8 W29N02KVBIAE W29N02KVBIAE
VFBGA-63
Table 15-1 Part Numbers for Industrial Grade
Part Numbers for Industrial Plus Grade:
PACKAGE
DENSITY VCC BUS PRODUCT NUMBER TOP SIDE MARKING
TYPE
S
2G-bit 3V X8 W29N02KVSJAE W29N02KVSJAE
TSOP-48
D
2G-bit 3V X8 W29N02KVDJAE W29N02KVDJAE
VFBGA-48
B
2G-bit 3V X8 W29N02KVBJAE W29N02KVBJAE
VFBGA-63
Table 15-2 Part Numbers for Industrial Plus Grade

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16. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION

A 7/1/2020 New create
7 Updated Endurance and Retention specs
B 5/17/2021
64 Updated the descriptions for Initial Invalid Blocks mark
C 8/19/2021 7, 48, 50, 69, 70 Added Industrial Plus Grade
Table 16-1 History Table
Trademarks
Winbond is trademark of Winbond Electronics Corporation.
All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Furthermore, Winbond products are not intended for applications wherein failure of Winbond
products could result or lead to a situation where in personal injury, death or severe property or
environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their own
risk and agree to fully indemnify Winbond for any damages resulting from such improper use or
sales.

71 – Revision C

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W29N02KVxxAE

Release Date: August 19th, 2021

1. GENERAL DESCRIPTION ............................................................................................................ 7

9.4.2 TWO PLANE BLOCK ERASE.................................................................................................. 37

Release Date: August 19th, 2021

Release Date: August 19th, 2021

Release Date: August 19th, 2021

Figure 11-12 #CE Don't Care Page Program Operation .............................................................................61

Release Date: August 19th, 2021

Release Date: August 19th, 2021

3. PACKAGE TYPES AND PIN CONFIGURATIONS

3.1 Pin Assignment 48-pin TSOP1(x8)

Figure 3-1 Pin Assignment 48-pin TSOP1 (Package code S)

Release Date: August 19th, 2021

3.2 Pin Assignment 48 ball VFBGA (x8)

Top View, ball down

A #WP ALE Vss #CE #WE RY/#BY

B N.C #RE CLE N.C N.C N.C

C N.C N.C N.C N.C N.C N.C

D N.C N.C N.C N.C N.C N.C

E DNU N.C DNU N.C N.C N.C

F N.C IO0 N.C N.C N.C Vcc

G N.C IO1 N.C Vcc IO5 IO7

H Vss IO2 IO3 IO4 IO6 Vss

Figure 3-2 Pin Assignment 48-ball VFBGA (Package code D)

Release Date: August 19th, 2021

3.3 Pin Assignment 63 ball VFBGA (x8)

Top View, ball down

A N.C N.C N.C N.C

B N.C N.C N.C

C #WP ALE Vss #CE #WE RY/#BY

D N.C #RE CLE N.C N.C N.C

E N.C N.C N.C N.C N.C N.C

F N.C N.C N.C N.C N.C N.C

G DNU N.C DNU N.C N.C N.C

H N.C IO0 N.C N.C N.C Vcc

J N.C IO1 N.C Vcc IO5 IO7

K Vss IO2 IO3 IO4 IO6 Vss

L N.C N.C N.C N.C

M N.C N.C N.C N.C

Figure 3-3 Pin Assignment 63-ball VFBGA (Package code B)

Release Date: August 19th, 2021

3.4 Pin Descriptions

Table 3-1 Pin Descriptions

Release Date: August 19th, 2021

4.1 Chip Enable (#CE)

4.2 Write Enable (#WE)

4.3 Read Enable (#RE)

4.4 Address Latch Enable (ALE)

4.5 Command Latch Enable (CLE)

4.6 Write Protect (#WP)

4.7 Ready/Busy (RY/#BY)

4.8 Input and Output (I/Ox)

Release Date: August 19th, 2021

Figure 5-1 NAND Flash Memory Block Diagram

Release Date: August 19th, 2021

6. MEMORY ARRAY ORGANIZATION

6.1 Array Organization (x8)

2176 bytes 2176 bytes

Plane of even Plane of- odd