K.Ramakrishnan College of Engineering: Samayapurm, Trichy-621 112
K.Ramakrishnan College of Engineering: Samayapurm, Trichy-621 112
K.Ramakrishnan College of Engineering: Samayapurm, Trichy-621 112
S.NO TOPIC
UNIT1
Must Read Reference Pages
1 MOS transistor operation. Sec 1.2.4
2 Long Channel I-V Characteristics. Sec 1.7
3 Non-Ideal IV Effects. Sec 1.9
4 Layout design rules, Gate layout and Stick diagrams. Sec 1.4, 1.5 and 1.6
Sec 1.13 to 1.13.3 (Few parameters), 1.13.4, 1.13.6.3
5 Scaling.
and 1.13.6.5
Other important Topics
6 Delay models (Elmore model, RC, Linear model, Parasitic delay, Logical effort) Sec 1.11.1 to 1.12.1
UNIT 2
Must Read
1 Dynamic logic, Domino logic and dual rail domino logic Sec 2.4, 2.4.1, 2.4.2
Sec 2.7, 2.7.1.1, 2.7.1.2, 2.7.1.3, 2.7.1.3
2 Dynamic and Static power
Sec 2.7.2 until 2.7.2.4
3 Low power architecture Sec 2.7.3
UNIT 3
Must Read
1 Static and dynamic latches/registers. Sec 3.2, 3,2.1, 3,2.2, 3.2.3, 3.3 full
2 Pipelining. Sec 3.6 full
3 Timing classification and synchronous design Sec 3.10.1, 3.10.2, 3.10.2.4, 3.10.2.5
Other Important Topics
4 Pulse register, Schmitt trigger, Monostable and Astable sequential circuits Sec 3.4, 3.7, 3.8, 3.9
5 Sense amplifier based register Sec 3.5 full
UNIT 4
Must Read
1 Power-speed tradeoffs Sec
Sec 4.7, 4.7.1Sec
4.4 and and 4.7.2
4.4.1 - Booth
Must Read
1 Design for testing - DFT, Adhoc, Scan design, BIST, IDDQ testing Sec 5.7 to 5.7.4
Sec 5.4 - Actel or Xilinx or Altera MAX (Any one
2 FPGA Building block architectures
FPGA architecture)
3 DFM and Boundary scan Sec 5.7.5 and 5.8
Other Important Topics
Sec 5.5 (Any two of Actel or Xilinx or Altera
4 FPGA Interconnect Routing Procedures
Interconnect Architectures)