Design of an LC-VCO with One Octave Tuning Range

Andreas Kämpe and Håkan Olsson

Radio Electronics LECS, Department Microelectronics and Information Technology, KTH
Electrum 229, 164 40 Kista

Abstract  This paper presents the design of a capacitance tuning of two octaves, due to the square
wideband, fully integrated LC-VCO. The architecture dependency of the frequency to capacitance:
is fully differential and has a tuning range from 1.2
GHz to 2.6 GHz. The phase-noise varies within the
tuning range from -138 dBc/Hz to -128 dBc/Hz at 1
MHz frequency offset. The VCO is implemented in a
0.18μm CMOS process using a 1.8 V supply. The (1)
circuit, including the bias, consumes only 3.8 mW at
2.6GHz and 8.5mW at 1.2 GHz.

(2)
1 INTRODUCTION
(3)
As more and more wireless standards, such as
WLAN, DVB and UMTS. are introduced, an elegant
solution would be a multi-standard transceiver [1]. Where fmin and fmax denote the highest and lowest
Therefore there is a need for extremely wideband oscillation frequency, tuned by a varactor with a
circuit blocks for the RF front-end. The VCO is a capacitance that can be varied from C min to Cmax. The
key building block in frequency synthesizers. A tuning capacitor has to have a C max/Cmin ratio even
challenge is to design a VCO with a wide tuning larger than 4 to compensate for the capacitive
range maintaining a low phase-noise and power parasitics Cp of the negative resistance and the
consumption. The design is further complicated by inductor. Designing an on chip varactor with this
the lack of high quality monolithic inductors and the large Cmax/Cmin ratio in a low voltage CMOS
small capacitance variation of the varactors for low process is not easy, and would result in a large
control voltage, limitated by the CMOS technology. varactor sensitivity (VCO gain). This is not
Oscillators without LC-tanks such as ring oscillators recommended, since it would degrade the phase
can achieve a very wide tuning range but they suffer noise performance of the VCO. Low frequency noise
from very high phase noise or high power and interference reaching the varactor would phase-
consumption [2], [3], [4]. On the contrary a fully modulate the VCO and be up-converted to the
integrated LC-VCO can be made with a low phase- carrier frequency increasing the phase noise.
noise and with relatively low power consumption,
but they usually suffer from a narrow tuning range
[5], [6]. 3 THE CAPACITOR ARRAY
In this paper, a fully integrated LC-VCO with a
tuning range over one octave is presented. It also Achieving a large C max/Cmin ratio while having a
exhibits low phase-noise and low power small VCO gain can instead be solved by using an
consumption. The large tuning range is achieved by array of switched capacitors as shown in Fig. 1.
the use of an array of switched capacitors.

2 LC-VCO

For RF transceivers, the LC-type oscillator is

superior in phase noise due to the band pass filtering
of the LC resonator. Harmonics are attenuated and
any sideband noise is reduced. Fig. 1: Switched capacitor array.
The VCO’s output frequency is tuned by on-chip
varactors. These varactors should have low parasitic
capacitance and wide tuning range to cope with The switched capacitors are used as band selectors
process variations. For an LC-VCO to achieve a or as coarse tuning. For fine tuning, a varactor is
tuning range of one-octave, it would require a used. The switches consists of NMOS transistors due
to their higher transconductance, but there is a resistance. As the control voltage and thereby the
tradeoff with the transistor size, between loss and frequency is increased, the biasing current is
capacitive load. This translates into either a reduced decreased. This bias control guaranties startup, and
power consumption or an increased tuning range. ensures constant oscillation amplitude independent
For small losses, the drain source resistance (R DS(ON)) of the oscillation frequency.
should be reduced by maximizing the
transconductance. Thus a wide transistor with 4 VCO ARCHITECTURE
minimum gate length and a large overdrive (V gs-Vt)
should be used. For a small capacitive load, the C gs All the blocks in the VCO (inductor, varactor, cap-
and Cgd have to be minimized, requiring a narrow array, negative resistance) are fully differential to
transistor with minimum gate length. The capacitor reduce the sensitivity to power supply variations and
array is shown in Fig. 2 substrate interference. Fig. 3 shows the block
diagram of the VCO. The negative resistance
C C
W consists of a cross-coupled complementary structure
4R 4R
of n and p-channel-transistors.The oscillation
frequency f0 is controlled by the LC-tank. The array
B0
2C
of capacitors is switched in or out in discrete
2C 2W
frequency steps, while the varactor is used for fine
2R 2R tuning.
B1
4C 4C
4W

R R

B2

Fig. 2: Capacitor array. Varactor

The capacitors on both sides of drain and source are

used for band switching, but they also act as Cap-array
coupling capacitors isolating the biasing voltage
from the negative resistance. The drain and source
are biased via resistors. When the switch is on, the
biasing is set to 0V and the gate to 1.8 V. This
maximizes the overdrive resulting in a reduced
RDS(ON). When the switch is off the bias is set to 1.8
I0 I1 I2
V and the gate is at 0V. This reduces the voltage
dependent Cgs and Cgd capacitance by 20%. The
increased overdrive makes it possible to use smaller
transistors which reduce the capacitive load without Fig. 3: Block diagram.
increasing the losses.
The cross-coupled complementary structure with n-
The oscillation amplitude is determined by the MOS and p-MOS transistors was chosen due to its
negative resistance and the load impedance of the differential operation, large output swing and low
LC tank. At resonance the LC tank has an phase-noise for a given current. An (n&p-core)
impedance operated in the current-limited region [7] can
achieve the same oscillation amplitude but with less
current than an n-core structure. The varactor
. (4) consists of four accumulation-mode transistors in an
anti-parallel configuration, shown in fig. 4. This
enables differential tuning. The complete varactor
Thus the oscillation amplitude increases with the has a Cmax/Cmin ratio of 2.
oscillation frequency. If the tuning range is large,
e.g. one octave, the oscillation amplitude will vary
significantly between f max and f min. This requires an
adjustable negative resistance, and is achieved by
changing the biasing current, affecting the
transconductance of gmn and gmp in the negative
 Cntrl+ geometry and size was optimized using ASITIC,
then fine tuned and simulated with ADS.
Simulations (shown in Fig. 6.) resulted in an
inductance around 3.6 nH Between 1.0 and 3.0 GHz.
The Q varies from 10.5 to 14.5.
15 3.80E-9
Cntrl-
14
Q
3.75E-9
Fig. 4: MOS varactor 13

inductance (H)
Q
12 3.70E-9

11
5 THE INDUCTOR Inducta nce 3.65E-9
10

In an on chip LC-oscillator the inductor is the 9 3.60E-9

dominant source of loss, but is compensated by the 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

negative resistance. The Q of an inductor can be Fre quency (GHz)

increased by using a differential coil instead of two Fig. 6: Inductor performance.

single coils. The coupling factor increases the
inductance but with unaffected series resistance. The simulated S-parameter data was fitted to a
lumped model of a transmission line, shown in Fig
A fully differential inductor was designed. It has a 7.
diameter of 340 m and consists of three turns, see
Fig. 5.
MUTIND

Fig. 7: Inductor model.

The extraction of the simulated data to this model

resulted in less than 2% error from 1.2 GHz to 3GHz.

6 RESULTS
Fig. 5: Inductor layout.
The VCO was implemented in a 0.18μm CMOS
The inductor is designed by stacking the three top process and verified in simulations using Cadence
metal layers M6, M5 and M4 on top of each other. SpectreRF. This Resulted in a tuning range from 1.2
They are then all connected in parallel to minimize GHz to 2.6 GHz, shown in Fig. 8.
the series resistance, thereby reducing the phase
noise,

. (5)

The disadvantage of this triple layer inductor is the

reduced tuning-range. The metal layers M5, M4 and
lower are closer to the substrate which increases the
capacitive load.

The inductor was designed using Electromagnetic

(EM) simulators such as ASITIC [8] and ADS. The
 000 001 010 011 100 101 110 111
(GHz) differential (even the tuning is differential). The
2.7 VCO is implemented in a 0.18μm CMOS process
2.6
2.5
using a 1.8 V supply. Simulation at 2.6 GHz
2.4 oscillation frequency, showed a phase noise of -128
2.3
dBc/Hz at 1 MHz frequency offset. The VCO,
Frequency of oscillation

2.2
2.1 including the bias, consumes only 3.8 mW.
2.0
1.9
1.8 References
1.7
1.6
1.5
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