Texas Instruction Set

TMS320C6000 CPU and Instruction Set Reference Guide
Literature Number: SPRU189F October 2000
Printed on Recycled Paper
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL APPLICATIONS). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMERS RISK. In order to minimize risks associated with the customers applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TIs publication of information regarding any third partys products or services does not constitute TIs approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
Preface
Read This First

About This Manual
This reference guide describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C6000 digital signal processors (DSPs). Unless otherwise specified, all references to the C6000 refer to the TMS320C6000 platform of DSPs: C62x refers to the TMS320C62x fixedpoint DSPs in the C6000 platform, C64x refers to the TMS320C64x fixedpoint DSPs in the C6000 platform, and C67x refers to the TMS320C67x floating-point DSPs in the C6000 platform.
How to Use This Manual

Use this manual as a reference for the architecture of the TMS320C6000 CPU. First-time readers should read Chapter 1 for general information about TI DSPs, the features of the C6000, and the applications for which the C6000 is best suited. Read Chapters 2, 6, 7, and 8 to grasp the concepts of the architecture. Chapter 3, Chapter 4, and Chapter 5 contain detailed information about each instruction and are best used as reference material. However, you may want to read sections 3.1 through 3.9, sections 4.1 through 4.6, and sections 5.1 through 5.8 for general information about the instruction set and to understand the instruction descriptions. Then browse through Chapter 3, Chapter 4, and Chapter 5 to familiarize yourself with the instructions.
Contents
iii
How to Use This Manual How to Use This Manual
The following table gives chapter references for specific information:

If you are looking for information about: Addressing modes
Turn to these chapters: Chapter 3, TMS320C62x/C64x/C67x Fixed-Point Instruction Set Chapter 4, TMS320C67x Floating-Point Instruction Set Chapter 5, TMS320C64x Fixed-Point Instruction Set
Conditional operations
Chapter 3, TMS320C62x/C64x/C67x Fixed-Point Instruction Set Chapter 4, TMS320C67x Floating-Point Instruction Set Chapter 5, TMS320C64x Fixed-Point Instruction Set
Control registers CPU architecture and data paths Delay slots
Chapter 2, CPU Data Paths and Control Chapter 2, CPU Data Paths and Control Chapter 3, TMS320C62x/C64x/C67x Fixed-Point Instruction Set Chapter 4, TMS320C67x Floating-Point Instruction Set Chapter 5, TMS320C64x Fixed-Point Instruction Set Chapter 6, TMS320C62x/C64x Pipeline Chapter 7, TMS320C67x Pipeline
General-purpose register files Instruction set
Chapter 2, CPU Data Paths and Control Chapter 3, TMS320C62x/C64x/C67x Fixed-Point Instruction Set Chapter 4, TMS320C67x Floating-Point Instruction Set Chapter 5, TMS320C64x Fixed-Point Instruction Set
Interrupts and control registers
Chapter 8, Interrupts
iv
Notational Conventions
Parallel operations
Chapter 3, TMS320C62x/C64x/C67x Fixed-Point Instruction Set Chapter 4, TMS320C67x Floating-Point Instruction Set Chapter 5, TMS320C64x Fixed-Point Instruction Set
Pipeline phases and operation
Chapter 6, TMS320C62x/C64x Pipeline Chapter 7, TMS320C67x Pipeline
Reset
Chapter 8, Interrupts
If you are interested in topics that are not listed here, check Related Documentation From Texas Instruments, on page vi, for brief descriptions of other C6x-related books that are available.
Notational Conventions
This document uses the following conventions:
- Program listings and program examples are shown in a special font.
Here is a sample program listing:

LDW .D1 ADD .L1 NOP MPY .M1 *A0,A1 A1,A2,A3 3 A1,A4,A5
- To help you easily recognize instructions and parameters throughout the
book, instructions are in bold face and parameters are in italics (except in program listings).
- In instruction syntaxes, portions of a syntax that are in bold should be en-
tered as shown; portions of a syntax that are in italics describe the type of information that should be entered. Here is an example of an instruction: MPY src1,src2,dst MPY is the instruction mnemonic. When you use MPY, you must supply two source operands (src1 and src2) and a destination operand (dst) of appropriate types as defined in Chapter 3, TMS320C62x/C64x/C67x Fixed-Point Instruction Set. Although the instruction mnemonic (MPY in this example) is in capital letters, the C6x assembler is not case sensitive it can assemble mnemonics entered in either upper or lower case.
Read This First
v
Related Documentation From Texas Instruments
- Square brackets, [ and ], and parentheses, ( and ), are used to identify op-
tional items. If you use an optional item, you must specify the information within brackets or parentheses; however, you do not enter the brackets or parentheses themselves. Here is an example of an instruction that has optional items. [label] EXTU (.unit) src2, csta, cstb, dst The EXTU instruction is shown with a label and several parameters. The [label] and the parameter (.unit) are optional. The parameters src2, csta, cstb, and dst are not optional.
- Throughout this book MSB means most significant bit and LSB means
least significant bit.

The following books describe the TMS320C6x generation and related support tools. To obtain a copy of any of these TI documents, call the Texas Instruments Literature Response Center at (800) 4778924. When ordering, please identify the book by its title and literature number.
TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x digital signal processor, and discusses the application areas that are enhanced by the C64x VelociTI.2 extensions to the C62x/C67x architecture. TMS320C62x/C67x Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x digital signal processors, development tools, and third-party support. TMS320C6201 Digital Signal Processor Data Sheet (literature number SPRS051) describes the features of the TMS320C6201 and provides pinouts, electrical specifications, and timings for the device. TMs320C6202 Digital Signal Processor Data Sheet (literature number SPRS072) describes the features of the TMS320C6202 fixed-point DSP and provides pinouts, electrical specifications, and timings for the device. TMS320C6203 Digital Signal Processor Data Sheet (literature number SPRS086) describes the features of the TMS320C6203 fixed-point DSP and provides pinouts, electrical specifications, and timings for the device. TMS320C6211 Digital Signal Processor Data Sheet (literature number SPRS073) describes the features of the TMS320C6211 fixed-point DSP and provides pinouts, electrical specifications, and timings for the device.
vi
TMS320C6701 Digital Signal Processor Data Sheet (literature number SPRS067) describes the features of the TMS320C6701 floating-point DSP and provides pinouts, electrical specifications, and timings for the device. TMS320C6711 Digital Signal Processor Data Sheet (literature number SPRS088) describes the features of the TMS320C6711 floating-point DSP and provides pinouts, electrical specifications, and timings for the device. TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes common peripherals available on the TMS320C6000 digital signal processors. This book includes information on the internal data and program memories, the external memory interface (EMIF), the host port, serial ports, direct memory access (DMA), enhanced direct memory access (EDMA), expansion bus (XBUS), clocking and phase-locked loop (PLL), and the power-down modes. TMS320C6000 Programmers Guide (literature number SPRU198) describes ways to optimize C and assembly code for the TMS320C6000 DSPs and includes application program examples. TMS320C6000 Assembly Language Tools Users Guide (literature number SPRU186) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the C6000 generation of devices. TMS320C6000 Optimizing C Compiler Users Guide (literature number SPRU187) describes the C6000 C compiler and the assembly optimizer. This C compiler accepts ANSI standard C source code and produces assembly language source code for the C6000 generation of devices. The assembly optimizer helps you optimize your assembly code. TMS320 Third-Party Support Reference Guide (literature number SPRU052) alphabetically lists over 100 third parties that provide various products that serve the family of TMS320 digital signal processors. A myriad of products and applications are offeredsoftware and hardware development tools, speech recognition, image processing, noise cancellation, modems, etc. TMS320C6x Peripheral Support Library Programmers Reference (literature number SPRU273) describes the contents of the C6x peripheral support library of functions and macros. It lists functions and macros both by header file and alphabetically, provides a complete description of each, and gives code examples to show how they are used.
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Trademarks
TMS320C6x C Source Debugger Users Guide (literature number SPRU188) tells you how to invoke the C6x simulator and emulator versions of the C source debugger interface. This book discusses various aspects of the debugger, including command entry, code execution, data management, breakpoints, profiling, and analysis. TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions for installing and operating the C6x evaluation module. It also includes support software documentation, application programming interfaces, and technical reference material. TMS320C62x Multichannel Evaluation Module Users Guide (literature number SPRU285) provides instructions for installing and operating the C62x multichannel evaluation module. It also includes support software documentation, application programming interfaces, and technical reference material. TMS320C62x Multichannel Evaluation Module Technical Reference (SPRU308) provides provides technical reference information for the C62x multichannel evaluation module (McEVM). It includes support software documentation, application programming interface references, and hardware descriptions for the C62x McEVM. TMS320C6201/6701 Evaluation Module Technical Reference (SPRU305) provides provides technical information that describes the C6x evaluation module functionality. It includes a description of host software utilities and a complete application programming interface reference. TMS320C6000 DSP/BIOS Users Guide (literature number SPRU303) describes how to use DSP/BIOS tools and APIs to analyze embedded real-time DSP applications. TMS320C6000 Code Composer Studio Tutorial (literature number SPRU301) introduces the Code Composer Studio integrated development environment and software tools for the TMS320C6000.
Trademarks
XDS510, VelociTI, and 320 Hotline On-line are trademarks of Texas Instruments. All of the digital signal processors within the TMS320 family are trademarks of Texas Instruments. Windows and Windows NT are registered trademarks of Microsoft Corporation.
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Read This First
Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Summarizes the features of the TMS320 family of products and presents typical applications. Describes the TMS320C62xx DSP and lists its key features. 1.1 TMS320 Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 History of TMS320 DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 Typical Applications for the TMS320 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview of the TMS320C6x Generation of Digital Signal Processors . . . . . . . . . . . . . Features and Options of the TMS320C62x/C64x/C67x . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C62x/C64x/C67x Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 Internal Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 Memory and Peripheral Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-2 1-2 1-4 1-5 1-7 1-8 1-8 1-9
1.2 1.3 1.4
CPU Data Paths and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Summarizes the TMS320C62x/C64x/C67x architecture and describes the primary components of the CPU. 2.1 2.2 2.3 2.4 2.5 2.6 General-Purpose Register Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Register File Cross Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Memory, Load, and Store Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Data Address Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 TMS320C6000 Control Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.6.1 Pipeline/Timing of Control Register Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.6.2 Addressing Mode Register (AMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.6.3 Control Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.6.4 E1 Phase Program Counter (PCE1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 TMS320C67x Control Register File Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.7.1 Floating-Point Adder Configuration Register (FADCR) . . . . . . . . . . . . . . . . . . . 2-20 2.7.2 Floating-Point Auxiliary Configuration Register (FAUCR) . . . . . . . . . . . . . . . . . 2-22 2.7.3 Floating-Point Multiplier Configuration Register (FMCR) . . . . . . . . . . . . . . . . . 2-24 TMS320C64x Control Register File Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.8.1 Galois Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.8.2 Special Timing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 Summary of TMS320C64x Architecture Key Extensions . . . . . . . . . . . . . . . . . . . . . . . . 2-30
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2.7
2.8
2.9
Contents
TMS320C62x/C64x/C67x Fixed-Point Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the assembly language instructions that are common to both the TMS320C62x, TMS320C64x, and TMS320C67x, including examples of each instruction. Provides information about addressing modes, resource constraints, parallel operations, and conditional operations. 3.1 3.2 3.3 3.4 3.5 Instruction Operation and Execution Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Mapping Between Instructions and Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 TMS320C62x/C64x/C67x Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Delay Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Parallel Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.5.1 Example Parallel Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.5.2 Branching Into the Middle of an Execute Packet . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Conditional Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Resource Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.7.1 Constraints on Instructions Using the Same Functional Unit . . . . . . . . . . . . . . 3-17 3.7.2 Constraints on Cross Paths (1X and 2X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.7.3 Constraints on Loads and Stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.7.4 Constraints on Long (40-Bit) Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.7.5 Constraints on Register Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.7.6 Constraints on Register Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.8.1 Linear Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.8.2 Circular Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.8.3 Syntax for Load/Store Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 Individual Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.6 3.7
3.8
3.9 4
TMS320C67x Floating-Point Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Describes the TMS320C67x floating-point instruction set, including examples of each instruction. Provides information about addressing modes and resource constraints. 4.1 4.2 4.3 4.4 4.5 4.6 Instruction Operation and Execution Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Mapping Between Instructions and Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Overview of IEEE Standard Single- and Double-Precision Formats . . . . . . . . . . . . . . . . 4-6 Delay Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 TMS320C67x Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Individual Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Contents
TMS320C64x Fixed-Point Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Describes the TMS320C64x fixed-point instruction set, including examples of each instruction.. Provides information about addressing modes and resource constraints. 5.1 5.2 5.3 5.4 5.5 5.6 Instruction Operation and Execution Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Mapping Between Instructions and Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 TMS320C64x Opcode Map Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Delay Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Conditional Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Resource Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.6.1 Constraints on Cross Paths (1X and 2X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.6.2 Cross Path Stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.6.3 Constraints on Loads and Stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.6.4 Constraints on Long (40-Bit) Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.7.1 Linear Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.7.2 Circular Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Individual Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
5.7
5.8 6
TMS320C62x/C64x Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Describes phases, operation, and discontinuities for the TMS320C62x/C64x CPU pipeline. 6.1 Pipeline Operation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.1.1 Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.1.2 Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.1.3 Execute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.1.4 Summary of Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Pipeline Execution of Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.2.1 Single-Cycle Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6.2.2 Two-Cycle Instructions and C64x Non-multiply .M Unit Operations . . . . . . . . 6-15 6.2.3 Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 6.2.4 Extended Multiply Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.2.5 Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.2.6 Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 Performance Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 6.3.1 Pipeline Operation With Multiple Execute Packets in a Fetch Packet . . . . . . 6-21 6.3.2 Multicycle NOPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.3.3 Memory Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
6.2
6.3
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TMS320C67x Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Describes phases, operation, and discontinuities for the TMS320C67x CPU pipeline. 7.1 Pipeline Operation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.1.1 Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.1.2 Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.1.3 Execute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.1.4 Summary of Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Pipeline Execution of Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 Functional Unit Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 7.3.1 .S-Unit Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 7.3.2 .M-Unit Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 7.3.3 .L-Unit Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30 7.3.4 D-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34 7.3.5 Single-Cycle Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 7.3.6 16 X 16-Bit Multiply Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39 7.3.7 Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 7.3.8 Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42 7.3.9 Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44 7.3.10 2-Cycle DP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46 7.3.11 4-Cycle Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47 7.3.12 INTDP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47 7.3.13 DP Compare Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48 7.3.14 ADDDP/SUBDP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49 7.3.15 MPYI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-50 7.3.16 MPYID Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-50 7.3.17 MPYDP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51 Performance Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-52 7.4.1 Pipeline Operation With Multiple Execute Packets in a Fetch Packet . . . . . . 7-52 7.4.2 Multicycle NOPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-54 7.4.3 Memory Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-56
7.2 7.3
7.4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Describes the TMS320C6000 interrupts, including reset and nonmaskable interrupts (NMI), and explains interrupt control, detection, and processing. 8.1 Overview of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.1.1 Types of Interrupts and Signals Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.1.2 Interrupt Service Table (IST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.1.3 Summary of Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 Globally Enabling and Disabling Interrupts (Control Status RegisterCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Individual Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.3.1 Enabling and Disabling Interrupts (Interrupt Enable Register IER) . . . . . . . 8-13 8.3.2 Status of, Setting, and Clearing Interrupts (Interrupt Flag, Set, and Clear RegistersIFR, ISR, ICR) . . . . . . . . . . . . . . . . . 8-14 8.3.3 Returning From Interrupt Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8.2 8.3
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8.4
8.5
8.6
Interrupt Detection and Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.1 Setting the Nonreset Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Conditions for Processing a Nonreset Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3 Actions Taken During Nonreset Interrupt Processing . . . . . . . . . . . . . . . . . . . . 8.4.4 Setting the RESET Interrupt Flag for the TMS320C6000 . . . . . . . . . . . . . . . . . 8.4.5 Actions Taken During RESET Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . Performance Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.1 General Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.2 Pipeline Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.1 Single Assignment Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.2 Nested Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.3 Manual Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.4 Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-18 8-18 8-18 8-21 8-22 8-23 8-24 8-24 8-24 8-25 8-25 8-26 8-26 8-27
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Defines terms and abbreviations used throughout this book.
Contents
xiii
Figures
Figures
11 21 22 23 24 25 26 27 28 29 210 211 31 32 33 41 42 61 62 63 64 65 66 67 68 69 610 611 612 613 614 615 616 617 618
xiv
TMS320C62x/C64x/C67x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 TMS320C62x CPU Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 TMS320C67x CPU Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 TMS320C64x CPU Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Storage Scheme for 40-Bit Data in a Register Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Addressing Mode Register (AMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Control Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 E1 Phase Program Counter (PCE1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Floating-Point Adder Configuration Register (FADCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Floating-Point Auxiliary Configuration Register (FAUCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Floating-Point Multiplier Configuration Register (FMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 Galois Field Polynomial Generator Function Register (GFPGFR) . . . . . . . . . . . . . . . . . . . 2-29 TMS320C62x/C64x/C67x Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Basic Format of a Fetch Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Examples of the Detectability of Write Conflicts by the Assembler . . . . . . . . . . . . . . . . . . 3-20 Single-Precision Floating-Point Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Double-Precision Floating-Point Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Fixed-Point Pipeline Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Fetch Phases of the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Decode Phases of the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Execute Phases of the Pipeline and Functional Block Diagram of the TMS320C62x/C64x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Fixed-Point Pipeline Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Pipeline Operation: One Execute Packet per Fetch Packet . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Functional Block Diagram of TMS320C62x Based on Pipeline Phases . . . . . . . . . . . . . . 6-10 Functional Block Diagram of TMS320C64x Based on Pipeline Phases . . . . . . . . . . . . . . 6-11 Single-Cycle Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Single-Cycle Execution Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Single 16 x 16 Multiply Execution Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 Store Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 Store Execution Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 Extended Multiply Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Multiply Extensions Execution Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Load Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Load Execution Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Figures
619 620 621 622 623 624 625 626 627 71 72 73 74 75 76 77 78 79 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 81 82 83
Branch Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 Branch Execution Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 Pipeline Operation: Fetch Packets With Different Numbers of Execute Packets . . . . . . . 6-22 Multicycle NOP in an Execute Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 Branching and Multicycle NOPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 Pipeline Phases Used During Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 Program and Data Memory Stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 4-Bank Interleaved Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 4-Bank Interleaved Memory With Two Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 Floating-Point Pipeline Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Fetch Phases of the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Decode Phases of the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Execute Phases of the Pipeline and Functional Block Diagram of the TMS320C67x . . . 7-5 Floating-Point Pipeline Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Pipeline Operation: One Execute Packet per Fetch Packet . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Functional Block Diagram of TMS320C67x Based on Pipeline Phases . . . . . . . . . . . . . . 7-10 Single-Cycle Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 Single-Cycle Execution Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 Multiply Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39 Multiply Execution Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39 Store Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 Store Execution Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41 Load Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42 Load Execution Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-43 Branch Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44 Branch Execution Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-45 2-Cycle DP Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46 4-Cycle Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47 INTDP Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48 DP Compare Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48 ADDDP/SUBDP Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49 MPYI Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-50 MPYID Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51 MPYDP Instruction Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51 Pipeline Operation: Fetch Packets With Different Numbers of Execute Packets . . . . . . . 7-53 Multicycle NOP in an Execute Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-54 Branching and Multicycle NOPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-55 Pipeline Phases Used During Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-56 Program and Data Memory Stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-57 8-Bank Interleaved Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-58 8-Bank Interleaved Memory With Two Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-59 Interrupt Service Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 Interrupt Service Fetch Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 IST With Branch to Additional Interrupt Service Code Located Outside the IST . . . . . . . . 8-7
Contents
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Figures
84 85 86 87 88 89 810 811 812 813 814
Interrupt Service Table Pointer (ISTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 Control Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Interrupt Enable Register (IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 Interrupt Flag Register (IFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 Interrupt Set Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 Interrupt Clear Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 NMI Return Pointer (NRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 Interrupt Return Pointer (IRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 TMS320C62x/C64x Nonreset Interrupt Detection and Processing: Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 TMS320C67x Nonreset Interrupt Detection and Processing: Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 RESET Interrupt Detection and Processing: Pipeline Operation . . . . . . . . . . . . . . . . . . . . 8-22
xvi
Tables
Tables
11 21 22 23 24 25 26 27 28 29 210 211 212 213 214 215 31 32 33 34 35 36 37 38 39 310 311 312 313 314 315 316 317 318 319 Typical Applications for the TMS320 DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 40-Bit/64-Bit Register Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Functional Units and Operations Performed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Control Registers Common to C62x/C67x and C64x Cores . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Addressing Mode Register (AMR) Mode Select Field Encoding . . . . . . . . . . . . . . . . . . . . 2-15 Block Size Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Control Status Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Control Register File Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Floating-Point Adder Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . 2-21 Floating-Point Auxiliary Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . 2-23 Floating-Point Multiplier Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . 2-25 Modulo 2 Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 Modulo 5 Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 Modulo Arithmetic for Field GF(23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 GFPGFR Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 C64x 8-Bit and 16-Bit Instruction Set Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 Fixed-Point Instruction Operation and Execution Notations . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Instruction to Functional Unit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Functional Unit to Instruction Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 TMS320C62x/C64x/C67x Opcode Map Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Delay Slot and Functional Unit Latency Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Registers That Can Be Tested by Conditional Operations . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Indirect Address Generation for Load/Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 Relationships Between Operands, Operand Size, Signed/Unsigned, Functional Units, and Opfields for Example Instruction (ADD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 Program Counter Values for Example Branch Using a Displacement . . . . . . . . . . . . . . . . 3-41 Program Counter Values for Example Branch Using a Register . . . . . . . . . . . . . . . . . . . . 3-43 Program Counter Values for B IRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 Program Counter Values for B NRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 Data Types Supported by Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69 Address Generator Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69 Data Types Supported by Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74 Register Addresses for Accessing the Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89 Data Types Supported by Stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-127 Address Generator Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-127 Data Types Supported by Stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-131
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Tables
41 42 43 44 45 46 47 48 49 410 51 52 53 54 55 56 57 58 59 510 511 512 513 61 62 63 64 71 72 73 74 75 76 77 78 79 710 711 712 713 714 715 716 717
xviii
Floating-Point Instruction Operation and Execution Notations . . . . . . . . . . . . . . . . . . . . . . . 4-2 Instruction to Functional Unit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Functional Unit to Instruction Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 IEEE Floating-Point Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Special Single-Precision Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Hex and Decimal Representation for Selected Single-Precision Values . . . . . . . . . . . . . . . 4-9 Special Double-Precision Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Hex and Decimal Representation for Selected Double-Precision Values . . . . . . . . . . . . . 4-10 Delay Slot and Functional Unit Latency Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Address Generator Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58 New Instruction Operation and Execution Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Instruction to Functional Unit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Functional Unit to Instruction Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 TMS320C64x Opcode Map Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Delay Slot and Functional Unit Latency Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Registers That Can Be Tested by Conditional Operations . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Constraint Differences Between C62x/C67x and C64x Registers . . . . . . . . . . . . . . . . . . . 5-16 Address Generator Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108 LDNDW Address Generator Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-111 LDNW Address Generator Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115 STDW Address Generator Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-226 STNDW Address Generator Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-230 STNW Address Generator Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-234 Operations Occurring During Fixed-Point Pipeline Phases . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Execution Stage Length Description for Each Instruction Type . . . . . . . . . . . . . . . . . . . . . 6-14 Program Memory Accesses Versus Data Load Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 Loads in Pipeline From Example 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 Operations Occurring During Floating-Point Pipeline Phases . . . . . . . . . . . . . . . . . . . . . . . 7-7 Execution Stage Length Description for Each Instruction Type . . . . . . . . . . . . . . . . . . . . . 7-13 Single-Cycle .S-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 DP Compare .S-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 2-Cycle DP .S-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23 Branch .S-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 16 X 16 Multiply .M-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 4-Cycle .M-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 MPYI .M-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 MPYID .M-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 MPYDP .M-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29 Single-Cycle .L-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30 4-Cycle .L-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31 INTDP .L-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32 ADDDP/SUBDP .L-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 Load .D-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34 Store .D-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35
Tables
718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 81 82 83 84
Single-Cycle .D-Unit Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36 LDDW Instruction With Long Write Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 Single-Cycle Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 16 X 16-Bit Multiply Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39 Store Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 Load Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42 Branch Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44 2-Cycle DP Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46 4-Cycle Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47 INTDP Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48 DP Compare Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48 ADDDP/SUBDP Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49 MPYI Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-50 MPYID Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-50 MPYDP Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51 Program Memory Accesses Versus Data Load Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . 7-56 Loads in Pipeline From Example 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-59 Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 Interrupt Service Table Pointer (ISTP) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 Control Status Register (CSR) Interrupt Control Field Descriptions . . . . . . . . . . . . . . . . . 8-11
Contents
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Examples
Examples
31 32 33 34 35 51 52 53 61 62 71 72 81 82 83 84 85 86 87 88 89 810 811 812 813 814 Fully Serial p-Bit Pattern in a Fetch Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Fully Parallel p-Bit Pattern in a Fetch Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Partially Serial p-Bit Pattern in a Fetch Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 LDW in Circular Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 ADDAH in Circular Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 LDW in Circular Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 ADDAH in Circular Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 LDNW in Circular Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 Execute Packet in Figure 67 and Figure 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Load From Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 Execute Packet in Figure 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 Load From Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-58 Relocation of Interrupt Service Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 Code Sequence to Disable Maskable Interrupts Globally . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 Code Sequence to Enable Maskable Interrupts Globally . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 Code Sequence to Enable an Individual Interrupt (INT9) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 Code Sequence to Disable an Individual Interrupt (INT9) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 Code to Set an Individual Interrupt (INT6) and Read the Flag Register . . . . . . . . . . . . . . 8-15 Code to Clear an Individual Interrupt (INT6) and Read the Flag Register . . . . . . . . . . . . 8-15 Code to Return From NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 Code to Return from a Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 Code Without Single Assignment: Multiple Assignment of A1 . . . . . . . . . . . . . . . . . . . . . . 8-25 Code Using Single Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25 Manual Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26 Code Sequence to Invoke a Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27 Code Sequence for Trap Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
xx
Chapter 1 a
Introduction
The TMS320C6000 digital signal processor (DSP) platform is part of the TMS320 DSP family. The TMS320C62x DSP generation and the TMS320C64x DSP generation comprise fixed-point devices in the C6000 DSP platform, and the TMS320C67x DSP generation comprises floatingpoint devices in the C6000 DSP platform. The TMS320C62x and TMS320C64x DSPs are code-compatible. The TMS320C62x and TMS320C67x DSPs are code-compatible. All three use the VelociTI architecture, a high-performance, advanced VLIW (very long instruction word) architecture, making these DSPs excellent choices for multichannel and multifunction applications. The VelociTI architecture of the C6000 platform of devices make them the first off-the-shelf DSPs to use advanced VLIW to achieve high performance through increased instruction-level parallelism. A traditional VLIW architecture consists of multiple execution units running in parallel, performing multiple instructions during a single clock cycle. Parallelism is the key to extremely high performance, taking these DSPs well beyond the performance capabilities of traditional superscalar designs. VelociTI is a highly deterministic architecture, having few restrictions on how or when instructions are fetched, executed, or stored. It is this architectural flexibility that is key to the breakthrough efficiency levels of the TMSC6000 Optimizing C compiler. VelociTIs advanced features include:
-
Instruction packing: reduced code size All instructions can operate conditionally: flexibility of code Variable-width instructions: flexibility of data types Fully pipelined branches: zero-overhead branching.
Topic
1.1 1.2 1.3 1.4
Page
TMS320 Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Overview of the TMS320C6x Generation of Digital Signal Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Features and Options of the TMS320C62x/C64x/C67x . . . . . . . . . . . . 1-5 TMS320C62x/C64x/C67x Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1-1
TMS320 Family Overview
1.1 TMS320 Family Overview

The TMS320 DSP family consists of fixed-point, floating-point, and multiprocessor digital signal processors (DSPs). TMS320 DSPs have an architecture designed specifically for real-time signal processing.
1.1.1
History of TMS320 DSPs

In 1982, Texas Instruments (TI) introduced the TMS32010 the first fixedpoint DSP in the TMS320 family. Before the end of the year, Electronic Products magazine awarded the TMS32010 the title Product of the Year. Today, the TMS320 family consists of many generations:
- C1x, C2x, C2xx, C5x, and C54x fixed-point DSPs - C3x and C4x floating-point DSPs, and - C8x multiprocessor DSPs.
Now there is a new generation of DSPs, the TMS320C6x generation, with performance and features that are reflective of Texas Instruments commitment to lead the world in DSP solutions.
1.1.2
Typical Applications for the TMS320 Family

Table 11 lists some typical applications for the TMS320 family of DSPs. The TMS320 DSPs offer adaptable approaches to traditional signal-processing problems. They also support complex applications that often require multiple operations to be performed simultaneously.
1-2
TMS320 Family Overview
Table 11. Typical Applications for the TMS320 DSPs

Automotive Adaptive ride control Antiskid brakes Cellular telephones Digital radios Engine control Global positioning Navigation Vibration analysis Voice commands General-Purpose Adaptive filtering Convolution Correlation Digital filtering Fast Fourier transforms Hilbert transforms Waveform generation Windowing Instrumentation Digital filtering Function generation Pattern matching Phase-locked loops Seismic processing Spectrum analysis Transient analysis Consumer Digital radios/TVs Educational toys Music synthesizers Pagers Power tools Radar detectors Solid-state answering machines Control Disk drive control Engine control Laser printer control Motor control Robotics control Servo control
Graphics/Imaging 3-D transformations Animation/digital maps Homomorphic processing Image compression/transmission Image enhancement Pattern recognition Robot vision Workstations Medical Diagnostic equipment Fetal monitoring Hearing aids Patient monitoring Prosthetics Ultrasound equipment Telecommunications
Industrial Numeric control Power-line monitoring Robotics Security access
Military Image processing Missile guidance Navigation Radar processing Radio frequency modems Secure communications Sonar processing Voice/Speech Speaker verification Speech enhancement Speech recognition Speech synthesis Speech vocoding Text-to-speech Voice mail
1200- to 56 600-bps modems Adaptive equalizers ADPCM transcoders Base stations Cellular telephones Channel multiplexing Data encryption Digital PBXs Digital speech interpolation (DSI) DTMF encoding/decoding Echo cancellation
Faxing Future terminals Line repeaters Personal communications systems (PCS) Personal digital assistants (PDA) Speaker phones Spread spectrum communications Digital subscriber loop (xDSL) Video conferencing X.25 packet switching
Introduction
1-3
Overview of the TMS320C6x Generation of Digital Signal Processors
1.2 Overview of the TMS320C6x Generation of Digital Signal Processors

With a performance of up to 6000 million instructions per second (MIPS) and an efficient C compiler, the TMS320C6x DSPs give system architects unlimited possibilities to differentiate their products. High performance, ease of use, and affordable pricing make the TMS320C6x generation the ideal solution for multichannel, multifunction applications, such as:
- Pooled modems - Wireless local loop base stations - Remote access servers (RAS) - Digital subscriber loop (DSL) systems - Cable modems - Multichannel telephony systems
The TMS320C6x generation is also an ideal solution for exciting new applications; for example:
- Personalized home security with face and hand/fingerprint recognition - Advanced cruise control with global positioning systems (GPS) navigation -
and accident avoidance Remote medical diagnostics. Beam-forming base stations Virtual reality 3-D graphics Speech recognition Audio Radar Atmospheric modeling Finite element analysis Imaging (examples: fingerprint recognition, ultrasound, and MRI).
1-4
Features and Options of the TMS320C62x/C64x/C67x
1.3 Features and Options of the TMS320C62x/C64x/C67x

The C6000 devices execute up to eight 32-bit instructions per cycle. The C62x/C67x devices core CPU consists of 32 general-purpose registers of 32-bit word length and eight functional units. The C64x core CPU consists of 64 general-purpose 32-bit registers and eight functional units. These eight functional units contain:
- Two multipliers - Six ALUs
The C6000 generation has a complete set of optimized development tools, including an efficient C compiler, an assembly optimizer for simplified assemblylanguage programming and scheduling, and a Windows based debugger interface for visibility into source code execution characteristics. A hardware emulation board, compatible with the TI XDS510 emulator interface, is also available. This tool complies with IEEE Standard 1149.11990, IEEE Standard Test Access Port and Boundary-Scan Architecture. Features of the C6000 devices include:
- Advanced VLIW CPU with eight functional units, including two multipliers
and six arithmetic units

J J
Executes up to eight instructions per cycle for up to ten times the performance of typical DSPs Allows designers to develop highly effective RISC-like code for fast development time
- Instruction packing J J
Gives code size equivalence for eight instructions executed serially or in parallel Reduces code size, program fetches, and power consumption
- Conditional execution of all instructions J J J J
Reduces costly branching Increases parallelism for higher sustained performance Industrys most efficient C compiler on DSP benchmark suite Industrys first assembly optimizer for fast development and improved parallelization
- Efficient code execution on independent functional units
- 8/16/32-bit data support, providing efficient memory support for a variety
of applications
- 40-bit arithmetic options add extra precision for vocoders and other com-
putationally intensive applications

Introduction
1-5
Features and Options of the TMS320C62x/C64x/C67x
- Saturation and normalization provide support for key arithmetic opera-
tions
- Field manipulation and instruction extract, set, clear, and bit counting sup-
port common operation found in control and data manipulation applications. The C67x has these additional features:
- Hardware support for single-precision (32-bit) and double-precision
(64-bit) IEEE floating-point operations

- 32 32-bit integer multiply with 32- or 64-bit result.
The C64x additional features include:

- Each multiplier can perform two 16 x 16-bit or four 8 x 8 bit multiplies every
clock cycle.
- Quad 8-bit and dual 16-bit instruction set extensions with data flow support - Support for non-aligned 32-bit (word) and 64-bit (double word) memory
accesses
- Special communication-specific instructions have been added to address
common operations in error-correcting codes.

- Bit count and rotate hardware extends support for bit-level algorithms.
1-6
TMS320C62x/C64x/C67x Architecture
1.4 TMS320C62x/C64x/C67x Architecture

Figure 11 is the block diagram for the TMS320C62x/C64x/C67x DSPs. The C6000 devices come with program memory, which, on some devices, can be used as a program cache. The devices also have varying sizes of data memory. Peripherals such as a direct memory access (DMA) controller, power-down logic, and external memory interface (EMIF) usually come with the CPU, while peripherals such as serial ports and host ports are on only certain devices. Check the data sheet for your device to determine the specific peripheral configurations you have.
Figure 11. TMS320C62x/C64x/C67x Block Diagram

C62x/C64x/C67x device

Program cache/program memory 32-bit address 256-bit data
C62x/C64x/C67x CPU
Control registers Control logic Test
Power down
Program fetch
Instruction dispatch (See Note) Instruction decode
Data path A
Data path B
DMA, EMIF
Register file A
Register file B
.L1
.S1
.M1 .D1
.D2 .M2
.S2 .L2
Emulation Interrupts
Additional peripherals: Timers, serial ports, etc.
Data cache/data memory 32-bit address
8-, 16-, 32-bit data (64-bit data, C64x only)
Note: The instruction dispatch unit, on the C64x only, has advanced instruction packing.
Introduction
1-7
1.4.1
Central Processing Unit (CPU)

The C62x/C64x/C67x CPU, shaded in Figure 11, is common to all the C62x/C64x/C67x devices. The CPU contains:
-
Program fetch unit Instruction dispatch unit, advanced instruction packing (C64 only) Instruction decode unit Two data paths, each with four functional units 32 32-bit registers, 64 32-bit registers (C64 only) Control registers Control logic Test, emulation, and interrupt logic
The program fetch, instruction dispatch, and instruction decode units can deliver up to eight 32-bit instructions to the functional units every CPU clock cycle. The processing of instructions occurs in each of the two data paths (A and B), each of which contains four functional units (.L, .S, .M, and .D) and 16 32-bit general-purpose registers for the C62x/C67x and 32 32-bit generalpurpose registers for the C64x. The data paths are described in more detail in Chapter 2, CPU Data Paths and Control. A control register file provides the means to configure and control various processor operations. To understand how instructions are fetched, dispatched, decoded, and executed in the data path, see Chapter 6, TMS320C62x/C64x Pipeline, and Chapter 7, TMS320C67x Pipeline.
1.4.2
Internal Memory
The C62x/C64x/C67x have a 32-bit, byte-addressable address space. Internal (on-chip) memory is organized in separate data and program spaces. When off-chip memory is used, these spaces are unified on most devices to a single memory space via the external memory interface (EMIF). The C62x/C67x have two 32-bit internal ports to access internal data memory. The C64x has two 64-bit internal ports to access internal data memory. The C62x/C64x/C67x have a single internal port to access internal program memory, with an instruction-fetch width of 256 bits.
1-8
1.4.3
Memory and Peripheral Options

A variety of memory and peripheral options are available for the C6000 platform:
- Large on-chip RAM, up to 7M bits - Program cache - 2-level caches - 32-bit external memory interface supports SDRAM, SBSRAM, SRAM,
and other asynchronous memories for a broad range of external memory requirements and maximum system performance.
- DMA Controller transfers data between address ranges in the memory
map without intervention by the CPU. The DMA controller has four programmable channels and a fifth auxiliary channel.
- EDMA Controller performs the same functions as the DMA controller. The
EDMA has 16 programmable channels, as well as a RAM space to hold multiple configurations for future transfers.
- HPI is a parallel port through which a host processor can directly access
the CPUs memory space. The host device has ease of access because it is the master of the interface. The host and the CPU can exchange information via internal or external memory. In addition, the host has direct access to memory-mapped peripherals.
- Expansion bus is a replacement for the HPI, as well as an expansion of
the EMIF. The expansion provides two distinct areas of functionality (host port and I/O port) which can co-exist in a system. The host port of the expansion bus can operate in either asynchronous slave mode, similar to the HPI, or in synchronous master/slave mode. This allows the device to interface to a variety of host bus protocols. Synchronous FIFOs and asynchronous peripheral I/O devices may interface to the expansion bus.
- McBSP (multichannel buffered serial port) is based on the standard serial
port interface found on the TMS320C2000 and C5000 platform devices. In addition, the port can buffer serial samples in memory automatically with the aid of the DMA/EDNA controller. It also has multichannel capability compatible with the T1, E1, SCSA, and MVIP networking standards.
Introduction
1-9
- Timers in the C6000 devices are two 32-bit general-purpose timers used
for these functions:

J J J J J
Time events Count events Generate pulses Interrupt the CPU Send synchronization events to the DMA/EDMA controller.
- Power-down logic allows reduced clocking to reduce power consumption.
Most of the operating power of CMOS logic dissipates during circuit switching from one logic state to another. By preventing some or all of the chips logic from switching, you can realize significant power savings without losing any data or operational context. For more information on features and options of the peripherals for the TMS320C6000, refer to the TM320C6000 Peripherals Reference Guide (SPRU190).
1-10
Chapter 2
CPU Data Paths and Control

This chapter focuses on the CPU, providing information about the data paths and control registers. The two register files and the data cross paths are described. The components of the data path for TMS320C62x, TMS320C67x, and TMS320C64x are shown in Figure 21, Figure 22, and Figure 23, respectively. These components consist of the following:
-
Two general-purpose register files (A and B) Eight functional units (.L1, .L2, .S1, .S2, .M1, .M2, .D1, and .D2) Two load-from-memory data paths (LD1 and LD2) Two store-to-memory data paths (ST1 and ST2) Two data address paths (DA1 and DA2) Two register file data cross paths (1X and 2X).
Topic
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
Page
General-Purpose Register Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Register File Cross Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Memory, Load, and Store Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Data Address Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 TMS320C6000 Control Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 TMS320C67x Control Register File Extensions . . . . . . . . . . . . . . . . . 2-20 TMS320C64x Control Register File Extensions . . . . . . . . . . . . . . . . . 2-26 Summary of TMS320C64x Architecture Key Extensions . . . . . . . . . 2-30
August 1996
2-1

1X 2X Register file A (A0A15) Register file B (B0B15) Control register file

ST2 LD1 LD2 ST1 .M1 .S2 .D2 .D1
2-2
Figure 21. TMS320C62x CPU Data Paths
Data path A
Data path B
DA2
DA1
long src long dst dst .S1 src1
.L1
long src long dst dst .L2 src2

.M2
src1 dst long dst long src
dst long dst long src
dst src1 src2
src1
src1
dst src1
src2
src2 src1 dst
src2
src2
src2
src2
src1 dst
32 32
Figure 22. TMS320C67x CPU Data Paths

src1
.L1
src2
Data path A
LD1 32 LSB DA1
DA2
LD2 32 LSB
Data path B
LD2 32 MSB ST2
LD1 32 MSB ST1
32 32
long src long dst dst .S1 src1
src2
.M1
dst src1
src2
.D1
dst src1 src2
.D2
src2 src1 dst
src2
.M2
src1 dst
src2
.S2
src1 dst long dst long src
32 32
long src long dst dst .L2 src2 src1

Register file A (A0A15) 2X 1X Register file B (B0B15) Control register file
2-3
Figure 23. TMS320C64x CPU Data Path

src1
.L1
src2
ST1b ST1a
32 MSB 32 LSB
long src
Data path A
long dst dst .S1 src1 src2
long dst dst .M1 src1 src2

LD1b LD1a 32 MSB 32 LSB
DA1
.D1
dst src1
src2
DA2
src2
.D2
src1 dst
LD2a LD2b
32 LSB 32 MSB
src2 src2
.M2
src1 dst long dst src2
Data path B
src1 .S2 dst long dst long src

ST2a ST2b 32 MSB 32 LSB
.L2
src2 src1
Notes for .M unit: 1. long dst is 32 MSB 2. dst is 32 LSB
2-4
long src long dst dst

8 8 8 8 8
Register file A (A0A31)
See Note 1 See Note 2
2x 1x
See Note 2 See Note 1
Register file B (B0B31)
Control Register
General-Purpose Register Files
2.1 General-Purpose Register Files

There are two general-purpose register files (A and B) in the C6000 data paths. For the C62x/C67x DSPs, each of these files contains 16 32-bit registers (A0A15 for file A and B0B15 for file B). The general-purpose registers can be used for data, data address pointers, or condition registers. The C64x DSP register file doubles the number of general-purpose registers that are in the C62x/C67x cores, with 32 32-bit registers (A0A31 for file A and B0B31 for file B). The C62x/C67x general-purpose register files support data ranging in size from packed 16-bit data through 40-bit fixed-point and 64-bit floating point data. Values larger than 32 bits, such as 40-bit long and 64-bit float quantities, are stored in register pairs. In these the 32 LSBs of data are placed in an even-numbered register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). The C64x register file extends this by additionally supporting packed 8-bit types and 64-bit fixed-point data types. (The C64x does not directly support floating-point data types.) Packed data types store either four 8-bit values or two 16-bit values in a single 32-bit register, or four 16-bit values in a 64-bit register pair. There are 16 valid register pairs for 40-bit and 64-bit data in the C62x/C67x cores, and 32 valid register pairs for 40-bit and 64-bit data in the C64x core, as shown in Table 21. In assembly language syntax, a colon between the register names denotes the register pairs, and the odd-numbered register is specified first.
2-5
General-Purpose Register Files
Table 21. 40-Bit/64-Bit Register Pairs

Register Files A A1:A0 A3:A2 A5:A4 A7:A6 A9:A8 A11:A10 A13:A12 A15:A14 A17:A16 A19:A18 A21:A20 A23:A22 A25:A24 A27:A26 A29:A28 A31:A30 B B1:B0 B3:B2 B5:B4 B7:B6 B9:B8 B11:B10 B13:B12 B15:B14 B17:B16 B19:B18 B21:B20 B23:B22 B25:B24 B27:B26 B29:B28 B31:B30 C64x only Applicable Devices C62x/C64x/C67x
Figure 24 illustrates the register storage scheme for 40-bit long data. Operations requiring a long input ignore the 24 MSBs of the odd-numbered register. Operations producing a long result zero-fill the 24 MSBs of the odd-numbered register. The even-numbered register is encoded in the opcode.
Figure 24. Storage Scheme for 40-Bit Data in a Register Pair

31 Odd register Ignored Read from registers 31 8 7 0 31 Even register 0
39
32
40-bit data Write to registers
Odd register
39
32
31
Even register 40-bit data
Zero-filled
2-6
Functional Units
2.2 Functional Units

The eight functional units in the C6000 data paths can be divided into two groups of four; each functional unit in one data path is almost identical to the corresponding unit in the other data path. The functional units are described in Table 22. Besides being able to perform all the C62x instructions, the C64x also contains many 8-bit to 16-bit extensions to the instruction set. For example, the MPYU4 instruction performs four 8x8 unsigned multiplies with a single instruction on an .M unit. The ADD4 instruction performs four 8-bit additions with a single instruction on an .L unit. The additional C64x operations are shown in boldface in Table 22.
2-7
Functional Units
Table 22. Functional Units and Operations Performed

Functional Unit .L unit (.L1, .L2) Fixed-Point Operations 32/40-bit arithmetic and compare operations 32-bit logical operations Leftmost 1 or 0 counting for 32 bits Normalization count for 32 and 40 bits Byte shifts Data packing/unpacking 5-bit constant generation Dual 16-bit arithmetic operations Quad 8-bit arithmetic operations Dual 16-bit min/max operations Quad 8-bit min/max operations .S unit (.S1, .S2) 32-bit arithmetic operations 32/40-bit shifts and 32-bit bit-field operations 32-bit logical operations Branches Constant generation Register transfers to/from control register file (.S2 only) Byte shifts Data packing/unpacking Dual 16-bit compare operations Quad 8-bit compare operations Dual 16-bit shift operations Dual 16-bit saturated arithmetic operations Quad 8-bit saturated arithmetic operations Compare Reciprocal and reciprocal square-root operations Absolute value operations SP DP conversion operations Floating-Point Operations Arithmetic operations DP SP, INT DP, INT SP conversion operations
2-8
Functional Units
Table 22. Functional Units and Operations Performed (Continued)

Functional Unit .M unit (.M1, .M2) Fixed-Point Operations 16 x 16 multiply operations 16 x 32 multiply operations Quad 8 x 8 multiply operations Dual 16 x 16 multiply operations Dual 16 x 16 multiply with add/subtract operations Quad 8 x 8 multiply with add operation Bit expansion Bit interleaving/de-interleaving Variable shift operations Rotation Galois Field Multiply .D unit (.D1, .D2) 32-bit add, subtract, linear and circular address calculation Loads and stores with 5-bit constant offset Loads and stores with 15-bit constant offset (.D2 only) Load and store double words with 5-bit constant Load and store non-aligned words and double words 5-bit constant generation 32-bit logical operations
Note: Fixed-point operations are available on all three devices. Floating-point operations and 32 x 32-bit fixed-point multiply are available only on the C67x. Additonal C64x functions are shown in bold.
Floating-Point Operations 32 X 32-bit fixed-point multiply operations Floating-point multiply operations
Load doubleword with 5-bit constant offset
Most data lines in the CPU support 32-bit operands, and some support long (40-bit) and double word (64-bit) operands. Each functional unit has its own 32-bit write port into a general-purpose register file (Refer to Figure 23). All units ending in 1 (for example, .L1) write to register file A, and all units ending in 2 write to register file B. Each functional unit has two 32-bit read ports for source operands src1 and src2. Four units (.L1, .L2, .S1, and .S2) have an extra 8-bit-wide port for 40-bit long writes, as well as an 8-bit input for 40-bit long reads. Because each unit has its own 32-bit write port, when performing 32-bit operations all eight units can be used in parallel every cycle. Since each C64x multiplier can return up to a 64-bit result, an extra write port has been added from the multipliers to the register file as compared to the C62x.
2-9
Register File Cross Paths
2.3 Register File Cross Paths

Each functional unit reads directly from and writes directly to the register file within its own data path. That is, the .L1, .S1, .D1, and .M1 units write to register file A and the .L2, .S2, .D2, and .M2 units write to register file B. The register files are connected to the opposite-side register files functional units via the 1X and 2X cross paths. These cross paths allow functional units from one data path to access a 32-bit operand from the opposite side register file. The 1X cross path allows the functional units of data path A to read their source from register file B, and the 2X cross path allows the functional units of data path B to read their source from register file A. On the C62x/C67x six of the eight functional units have access to the register file on the opposite side, via a cross path. The .M1, .M2, .S1 and .S2 units src2 units are selectable between the cross path and the same side register file. In the case of the .L1 and .L2, both src1 and src2 inputs are also selectable between the cross path and the same-side register file. On the C64x all eight of the functional units have access to the register file on the opposite side, via a cross path. The src2 inputs of .M1, .M2, .S1, .S2, .D1, and .D2 units are selectable between the cross path and the same-side register file. In the case of the .L1 and .L2, both src1 and src2 inputs are also selectable between the cross path and the same-side register file. Only two cross paths, 1X and 2X, exist in the C6000 architecture. Thus the limit is one source read from each data paths opposite register file per cycle, or a total of two cross path source reads per cycle. In the C62x/C67x only one functional unit per data path, per execute packet, can get an operand from the opposite register file. In the C64x, multiple units on a side may read the same cross path source simultaneously. Thus the C64x cross path operand for one side may be used by up to two functional units on that side in an execute packet. On the C64x a delay clock cycle is introduced whenever an instruction attempts to read a register via a cross path that was updated in the previous cycle. This is known as a cross path stall. This stall is inserted automatically by the hardware, no NOP instruction is needed. It should be noted that no stall is introduced if the register being read is the destination for data placed by an LDx instruction. For more information see Chapter 5, section 5.6.2 Cross Path Stalls. Techniques for avoiding this stall are discussed in the TMS320C6000 Programmers Guide (SPRU198).
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Memory, Load, and Store Paths
2.4 Memory, Load, and Store Paths

The C62x has two 32-bit paths for loading data from memory to the register file: LD1 for register file A, and LD2 for register file B. The C67x also has a second 32-bit load path for both register files A and B. This allows the LDDW instruction to simultaneously load two 32-bit values into register file A and two 32-bit values into register file B. For side A, LD1a is the load path for the 32 LSBs and LD1b is the load path for the 32 MSBs. For side B, LD2a is the load path for the 32 LSBs and LD2b is the load path for the 32 MSBs. There are also two 32-bit paths, ST1 and ST2, for storing register values to memory from each register file. The C64x supports double word loads and stores. There are four 32-bit paths for loading data from memory to the register file. For side A, LD1a is the load path for the 32 LSBs and LD1b is the load path for the 32 MSBs. For side B, LD2a is the load path for the 32 LSBs and LD2b is the load path for the 32 MSBs. There are also four 32-bit paths, for storing register values to memory from each register file. ST1a is the write path for the 32 LSBs on side A and ST1b is the write path for the 32 MSBs on side A. For side B, ST2a is the write path for the 32 LSBs and ST2b is the write path for the 32 MSBs. On the C6000 architecture, some of the ports for long and double word operands are shared between functional units. This places a constraint on which long or double word operations can be scheduled on a data path in the same execute packet. See Chapter 5, section 5.6.4, Constraints on Long (40-Bit) Data.
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Data Address Paths
2.5 Data Address Paths

The data address paths DA1 and DA2 are each connected to the .D units in both data paths. This allows data addresses generated by any one path to access data to or from any register. The DA1 and DA2 resources and their associated data paths are specified as T1 and T2 respectively. T1 consists of the DA1 address path and the LD1 and ST1 data paths. For the C64x and C67x, LD1 is comprised of LD1a and LD1b to support 64-bit loads. For the C64x, ST1 is comprised of ST1a and ST1b to support 64-bit stores. Similarly, T2 consists of the DA2 address path and the LD2 and ST2 data paths. For the C64x and C67x, LD2 is comprised of LD2a and LD2b to support 64-bit loads. For the C64x, ST2 is comprised of ST2a and ST2b to support 64-bit stores. The T1 and T2 designations appear in functional unit fields for load and store instructions. For example, the following load instructions uses the .D1 unit to generate the address but is using the LD2 path resource from DA2 to place the data in the B register file. The use of the DA2 resource is indicated with the T2 designation.
LDW .D1T2 *A0[3],B1
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TMS320C6000 Control Register File
2.6 TMS320C6000 Control Register File

One unit (.S2) can read from and write to the control register file, as shown in this section. Table 23 lists the control registers contained in the control register file and describes each. If more information is available on a control register, the table lists where to look for that information. Each control register is accessed by the MVC instruction. See the MVC instruction description in Chapter 3, TMS320C62x/C64x/C67x Fixed-Point Instruction Set, for information on how to use this instruction. Additionally, some of the control register bits are specially accessed in other ways. For example, arrival of a maskable interrupt on an external interrupt pin, INTm, triggers the setting of flag bit IFRm. Subsequently, when that interrupt is processed, this triggers the clearing of IFRm and the clearing of the global interrupt enable bit, GIE. Finally, when that interrupt processing is complete, the B IRP instruction in the interrupt service routine restores the pre-interrupt value of the GIE. Similarly, saturating instructions like SADD set the SAT (saturation) bit in the CSR (Control Status Register).
Table 23. Control Registers Common to C62x/C67x and C64x Cores

Abbreviation AMR Register Name Addressing mode register Description Specifies whether to use linear or circular addressing for each of eight registers; also contains sizes for circular addressing Contains the global interrupt enable bit, cache control bits, and other miscellaneous control and status bits Displays status of interrupts Allows manually setting pending interrupts Allows manually clearing pending interrupts Allows enabling/disabling of individual interrupts Points to the beginning of the interrupt service table Contains the address to be used to return from a maskable interrupt Contains the address to be used to return from a nonmaskable interrupt Contains the address of the fetch packet that is in the E1 pipeline stage Page 2-14
CSR
Control status register
2-17
IFR ISR ICR IER ISTP IRP NRP PCE1
Interrupt flag register Interrupt set register Interrupt clear register Interrupt enable register Interrupt service table pointer Interrupt return pointer Nonmaskable interrupt return pointer Program counter, E1 phase
8-14 8-14 8-14 8-13 8-8 8-17 8-16 2-19
2-13
2.6.1
Pipeline/Timing of Control Register Accesses

As shown in this section, all MVC are single-cycle instructions that complete their access of the explicitly named registers in the E1 pipeline phase. This is true whether MVC is moving a general register to a control register, or vice versa. In all cases the source register content is read, moved through the .S2 unit, and written to the destination register in the E1 pipeline phase.
Pipeline Stage Read Written Unit in use E1
src2 dst
.S2
Even though MVC modifies the particular target control register in a single cycle, it can take extra clocks to complete modification of the non-explicitly named register. For example, the MVC cannot modify bits in the IFR directly. Instead, MVC can only write 1s into the ISR or the ICR to specify setting or clearing, respectively, of the IFR bits. MVC completes this ISR/ICR write in a single (E1) cycle (as described above) but the modification of the IFR bits themselves occur one clock later. For more information on the manipulation of ISR, ICR, and IFR see these control hardware sections in Chapter 8: section 8.3.2 Status of, Setting, and Clearing Interrupts, and section 8.3.3 Returning from Interrupt Servicing. Saturating instructions, such as SADD, set the saturation flag bit (SAT) in the Control Status Register (CSR) indirectly. As a result, several of these instructions update the SAT bit one full clock cycle after their primary results are written to the register file. For example, the SMPY instruction writes its result at the end of pipeline stage E2; its primary result is available after one delay slot. In contrast, the SAT bit in the CSR is updated one cycle later than the result is written; this update occurs after two delay slots. (For the specific behavior of an instruction, refer to the description of that individual instruction). The B IRP and B NRP instructions directly update the GIE and NMIE, respectively. Because these branches directly modify the CSR and IER (Interrupt Enable Register) respectively, there are no delay slots between when the branch is issued and when the control register updates take effect.
2.6.2
Addressing Mode Register (AMR)

For each of the eight registers (A4A7, B4B7) that can perform linear or circular addressing, the AMR specifies the addressing mode. A 2-bit field for each register selects the address modification mode: linear (the default) or circular mode. With
2-14
circular addressing, the field also specifies which BK (block size) field to use for a circular buffer. In addition, the buffer must be aligned on a byte boundary equal to the block size. The mode select fields and block size fields are shown in Figure 25, and the mode select field encoding is shown in Table 24.
Figure 25. Addressing Mode Register (AMR)

31 Reserved R, +0 26 25 BK1 R, W, +0 Mode select fields 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B7 mode B6 mode B5 mode B4 mode A7 mode A6 mode A5 mode A4 mode Block size fields 21 20 BK0 R, W, +0 16
R, W, +0 Legend: R W +0 Readable by the MVC instruction Writeable by the MVC instruction Value is zero after reset
Table 24. Addressing Mode Register (AMR) Mode Select Field Encoding
Mode 0 0 0 1 1 0 1 1 Description Linear modification (default at reset) Circular addressing using the BK0 field Circular addressing using the BK1 field Reserved
The reserved portion of AMR is always 0. The AMR is initialized to 0 at reset. The block size fields, BK0 and BK1, contain 5-bit values used in calculating block sizes for circular addressing.
Block size (in bytes) = 2 (N+1) where N is the 5-bit value in BK0 or BK1
2-15
Table 25 shows block size calculations for all 32 possibilities.
Table 25. Block Size Calculations

N 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Block Size 2 4 8 16 32 64 128 256 512 1 024 2 048 4 096 8 192 16 384 32 768 65 536 N 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Block Size 131 072 262 144 524 288 1 048 576 2 097 152 4 194 304 8 388 608 16 777 216 33 554 432 67 108 864 134 217 728 268 435 456 536 870 912 1 073 741 824 2 147 483 648 4 294 967 296
Note: When N is 11111, the behavior is identical to linear addressing.
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2.6.3
Control Status Register (CSR)

The CSR, shown in Figure 26, contains control and status bits. The functions of the fields in the CSR are shown in Table 26. For the EN, PWRD, PCC, and DCC fields, see the data sheet of your specific device to see if it supports the options that these fields control. Also see the C6000 Peripherals Reference Guide for more information on these options.
Figure 26. Control Status Register (CSR)

31 CPU ID 15 PWRD R, W, +0 Legend: R W +x +0 C 10 9 SAT R 8 EN 7 PCC 24 23 Revision ID 5 4 DCC R, W, +0 2 1 PGIE 0 GIE 16
R, C, +0 R, +x
Readable by the MVC instruction Writeable by the MVC instruction Value undefined after reset Value is zero after reset Clearable using the MVC instruction
2-17
Table 26. Control Status Register Field Descriptions

Bit Position Width Field Name CPU ID and Revision ID 31-24 8 CPU ID CPU ID identifies which of these CPUs: CPU ID = 00b: indicates C62x, CPU ID= 10b: indicates C67x, CPU ID = 1000b: indicates C64x Revision ID defines silicon revision of the CPU. Devices CPU Core Voltage 2.5V 1.8V 1.5V 1.8V 1.8V 1.5V Bits 31:16 of CSR 0x0001 0x0002 0x0003 0x0201 0x0202 0x0801 Function
23-16
Revision ID
C6201 C62x C6201B, C6202, C6211 C62x C6202B, C6203, C6204, C6205 C62x C6701 revision 0 (early CPU) C67x C6701, C6711, C6712 C67x C64xx C64x 15-10 9 6 1 PWRD SAT
Control power-down modes; the values are always read as zero. The saturate bit, set when any unit performs a saturate, can be cleared only by the MVC instruction and can be set only by a functional unit. The set by a functional unit has priority over a clear (by the MVC instruction) if they occur on the same cycle. The saturate bit is set one full cycle (one delay slot) after a saturate occurs. This bit will not be modified by a conditional instruction whose condition is false. Endian bit: 1 = little endian, 0 = big endian Program cache control mode Data cache control mode Previous GIE (global interrupt enable); saves GIE when an interrupt is taken. Global interrupt enable; enables (1) or disables (0) all interrupts except the reset interrupt and NMI (nonmaskable interrupt).
8 7-5 4-2 1 0
1 3 3 1 1
EN PCC DCC PGIE GIE
See the TMS320C6000 Peripherals Reference Guide for more information.
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2.6.4
E1 Phase Program Counter (PCE1)

The PCE1, shown in Figure 27, contains the 32-bit address of the fetch packet in the E1 pipeline phase.
Figure 27. E1 Phase Program Counter (PCE1)

31 PCE1 R, +x Legend: R +x Readable by the MVC instruction Value undefined after reset 0
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TMS320C67x Control Register File Extensions
2.7 TMS320C67x Control Register File Extensions

The C67x has three additional configuration registers to support floating point operations. The registers specify the desired floating-point rounding mode for the .L and .M units. They also contain fields to warn if src1 and src2 are NaN or denormalized numbers, and if the result overflows, underflows, is inexact, infinite, or invalid. There are also fields to warn if a divide by 0 was performed, or if a compare was attempted with a NaN source. Table 27 shows the additional registers used by the C67x. The OVER, UNDER, INEX, INVAL, DENn, NANn, INFO, UNORD and DIV0 bits within these registers will not be modified by a conditional instruction whose condition is false.
Table 27. Control Register File Extensions

Register Abbreviation FADCR FAUCR FMCR Name Floating-point adder configuration register Floating-point auxiliary configuration register Floating-point multiplier configuration register Description Specifies underflow mode, rounding mode, NaNs, and other exceptions for the .L unit. Specifies underflow mode, rounding mode, NaNs, and other exceptions for the .S unit. Specifies underflow mode, rounding mode, NaNs, and other exceptions for the .M unit. Page 2-20 2-22 2-24
2.7.1
Floating-Point Adder Configuration Register (FADCR)

The floating-point configuration register (FADCR) contains fields that specify underflow or overflow, the rounding mode, NaNs, denormalized numbers, and inexact results for instructions that use the .L functional units. FADCR has a set of fields specific to each of the .L units, .L1 and .L2. Figure 28 shows the layout of FADCR. The functions of the fields in the FADCR are shown in Table 28.
Figure 28. Floating-Point Adder Configuration Register (FADCR)

31 Fields used by .L2 15 Fields used by .L1 Reserved
R, +0
Reserved
R, +0
19 21 20 27 26 25 24 23 22 RMode UNDER INEX OVER INFO INVAL DEN2

R, W, +0
18 16 17 DEN1 NAN2 NAN1

R, W, +0
2 1 DEN1 NAN2
0 NAN1
Legend: R W +0
Readable by the MVC instruction Writeable by the MVC instruction Value is zero after reset
2-20
Table 28. Floating-Point Adder Configuration Register Field Descriptions

Bit Position 3127 2625 Width 5 2 Rmode .L2 Field Name Function Reserved Value 00: Round toward nearest representable floating-point number Value 01: Round toward 0 (truncate) Value 10: Round toward infinity (round up) Value 11: Round toward negative infinity (round down) Set to 1 when result underflows Set to 1 when result differs from what would have been computed had the exponent range and precision been unbounded; never set with INVAL Set to 1 when result overflows Set to 1 when result is signed infinity Set to 1 when a signed NaN (SNaN) is a source, NaN is a source in a floating-point to integer conversion, or when infinity is subtracted from infinity
24 23
1 1
UNDER .L2 INEX .L2
22 21 20
1 1 1
OVER .L2 INFO .L2 INVAL .L2
19 18 17 16 1511 109
1 1 1 1 5 2
DEN2 .L2 DEN1 .L2 NAN2 .L2 NAN1 .L2
src2 is a denormalized number src1 is a denormalized number src2 is NaN src1 is NaN
Reserved
Rmode .L1
Value 00: Round toward nearest even representable floating-point number Value 01: Round toward 0 (truncate) Value 10: Round toward infinity (round up) Value 11: Round toward negative infinity (round down) Set to 1 when result underflows Set to 1 when result differs from what would have been computed had the exponent range and precision been unbounded; never set with INVAL Set to 1 when result overflows Set to 1 when result is signed infinity Set to 1 when a signed NaN is a source, NaN is a source in a floatingpoint to integer conversion, or when infinity is subtracted from infinity
8 7
1 1
UNDER .L1 INEX .L1
6 5 4 3 2 1 0
1 1 1 1 1 1 1
OVER .L1 INFO .L1 INVAL .L1 DEN2 .L1 DEN1 .L1 NAN2 .L1 NAN1 .L1
2-21
2.7.2
Floating-Point Auxiliary Configuration Register (FAUCR)

The floating-point auxiliary register (FAUCR) contains fields that specify underflow or overflow, the rounding mode, NaNs, denormalized numbers, and inexact results for instructions that use the .S functional units. FAUCR has a set of fields specific to each of the .S units, .S1 and .S2. Figure 29 shows the layout of FAUCR. The functions of the fields in the FAUCR are shown in Table 29.
Figure 29. Floating-Point Auxiliary Configuration Register (FAUCR)

Fields used by .S2 19 21 20 31 27 26 24 23 22 25 Reserved DIV0 UNORD UND INEX OVER INFO INVAL DEN2
R, +0 R, W, +0
18 16 17 DEN1 NAN2 NAN1
3 5 4 2 0 15 11 10 8 7 6 1 9 Fields used by .S1 Reserved DIV0 UNORD UND INEX OVER INFO INVAL DEN2 DEN1 NAN2 NAN1
R, +0 R, W, +0
Legend: R W +0
2-22
Table 29. Floating-Point Auxiliary Configuration Register Field Descriptions

Bit Position Width 3127 26 25 24 23 22 21 20 19 18 17 16 1511 10 9 8 7 6 5 4 3 2 1 0 5 1 1 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1 1 1 DIV0 .S1 DIV0 .S2 Field Name Function Reserved Set to 1 when 0 is source to reciprocal operation
UNORD .S2 Set to 1 when NaN is a source to a compare operation UNDER .S2 Set to 1 when result underflows INEX .S2 OVER .S2 INFO .S2 INVAL .S2 DEN2 .S2 DEN1 .S2 NAN2 .S2 NAN1 .S2 Set to 1 when result differs from what would have been computed had the exponent range and precision been unbounded; never set with INVAL Set to 1 when result overflows Set to 1 when result is signed infinity Set to 1 when a signed NaN (SNaN) is a source, NaN is a source in a floating-point to integer conversion, or when infinity is subtracted from infinity
Reserved Set to 1 when 0 is source to reciprocal operation
UNORD .S1 Set to 1 when NaN is a source to a compare operation UNDER .S1 Set to 1 when result underflows INEX .S1 OVER .S1 INFO .S1 INVAL .S1 DEN2 .S1 DEN1 .S1 NAN2 .S1 NAN1 .S1 Set to 1 when result differs from what would have been computed had the exponent range and precision been unbounded; never set with INVAL Set to 1 when result overflows Set to 1 when result is signed infinity Set to 1 when SNaN is a source, NaN is a source in a floating-point to integer conversion, or when infinity is subtracted from infinity
src2 is a denormalized number src1 is a denormalized number src2 is a NaN src1 is a NaN
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2.7.3
Floating-Point Multiplier Configuration Register (FMCR)

The floating-point multiplier configuration register (FMCR) contains fields that specify underflow or overflow, the rounding mode, NaNs, denormalized numbers, and inexact results for instructions that use the .M functional units. FMCR has a set of fields specific to each of the .M units, .M1 and .M2. Figure 210 shows the layout of FMCR. The functions of the fields in the FMCR are shown in Table 210.
Figure 210. Floating-Point Multiplier Configuration Register (FMCR)

31 Fields used by .M2 15 Fields used by .M1 Reserved
R, +0

R, W, +0
18 16 17 DEN1 NAN2 NAN1 0 2 1 DEN1 NAN2 NAN1
3 5 4 11 10 9 8 7 6 RMode UNDER INEX OVER INFO INVAL DEN2 Reserved

R, +0 R, W, +0
Legend: R W +0
2-24
Table 210. Floating-Point Multiplier Configuration Register Field Descriptions

Bit Position 3127 2625 Width 5 2 Rmode .M2 Field Name Function Reserved Value 00: Round toward nearest representable floating-point number Value 01: Round toward 0 (truncate) Value 10: Round toward infinity (round up) Value 11: Round toward negative infinity (round down) Set to 1 when result underflows Set to 1 when result differs from what would have been computed had the exponent range and precision been unbounded; never set with INVAL Set to 1 when result overflows Set to 1 when result is signed infinity Set to 1 when SNaN is a source, NaN is a source in a floatingpoint to integer conversion, or when infinity is subtracted from infinity
24 23
1 1
UNDER .M2 INEX .M2
22 21 20
1 1 1
OVER .M2 INFO .M2 INVAL .M2
19 18 17 16 1511 109
1 1 1 1 5 2
DEN2 .M2 DEN1 .M2 NAN2 .M2 NAN1 .M2
Reserved Value 00: Round toward nearest representable floating-point number Value 01: Round toward 0 (truncate) Value 10: Round toward infinity (round up) Value 11: Round toward negative infinity (round down) Set to 1 when result underflows Set to 1 when result differs from what would have been computed had the exponent range and precision been unbounded; never set with INVAL Set to 1 when result overflows Set to 1 when result is signed infinity Set to 1 when SNaN is a source, NaN is a source in a floatingpoint to integer conversion, or when infinity is subtracted from infinity
Rmode .M1
8 7
1 1
UNDER .M1 INEX .M1
6 5 4
1 1 1
OVER .M1 INFO .M1 INVAL .M1
3 2 1 0
1 1 1 1
DEN2 .M1 DEN1 .M1 NAN2 .M1 NAN1 .M1
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2.8 TMS320C64x Control Register File Extensions

One new control register in the C64x is the Galois Field Polynomial Generator Function Register (GFPGFR).
2.8.1
Galois Field
Modern digital communication systems typically make use of error correction coding schemes to improve system performance under imperfect channel conditions. The scheme most commonly used is the Reed-Solomon code, due to its robustness against burst errors and its relative ease of implementation. The C64x contains Galois Field Multiply hardware that can be used for ReedSolomon encode and decode functions. To understand the relevance of the Galois Field Multiply hardware, it is necessary to first define some mathematical terms. Two kinds of number systems that are common in algorithm development are integers and real numbers. For integers the addition, subtraction and multiplication operations can be performed. Division can also be performed if a non-zero remainder can be allowed. For real numbers all four of these operations can be performed, even if there is a non-zero remainder for division operations. Real numbers can belong to a mathematical structure called a field. A field consists of a set of data elements along with addition, subtraction, multiplication, and division. A field of integers can also be created if modulo arithmetic is performed. An example is doing arithmetic using integers modulo 2. Perform the operations using normal integer arithmetic and then take the result modulo 2. Table 211 describes addition, subtraction and multiplication modulo 2.
Table 211. Modulo 2 Arithmetic

Addition + 0 1 0 0 1 1 1 0 Subtraction 0 1 0 0 1 1 1 0 Multiplication 0 1 0 0 0 1 0 1
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Note that addition and subtraction results are the same, and in fact are equivalent to the XOR (exclusive OR) operation in binary. Also, the multiplication result is equal to the AND operation in binary. These properties are unique to modulo 2 arithmetic, but modulo 2 arithmetic is used extensively in error correction coding. Another more general property is that division by any non-zero element is now defined. Division can always be performed if every element other than zero has a multiplicative inverse, i.e.: x @ x1 = 1. Another example, arithmetic modulo 5, illustrates this concept more clearly. The addition, subtraction and multiplication tables are given in Table 212.
Table 212. Modulo 5 Arithmetic

Addition + 0 1 2 3 4 0 0 1 2 3 4 1 1 2 3 4 0 2 2 3 4 0 1 3 3 4 0 1 2 4 4 0 1 2 3 0 1 2 3 4 0 0 1 2 3 4 Subtraction 1 4 0 1 2 3 2 3 4 0 1 2 3 2 3 4 0 1 4 1 2 3 4 0 0 1 2 3 4 0 0 0 0 0 0 Multiplication 1 0 1 2 3 4 2 0 2 4 1 3 3 0 3 1 4 2 4 0 4 3 2 1
In the rows of the multiplication table, it is clear that the element 1 appears in every non-zero row and column. Every non-zero element can be multiplied by at least one other element to get a result equal to 1. Therefore, division always works and arithmetic over integers modulo 5 forms a field. Fields generated in this manner are called finite fields or Galois fields and are written as GF(X), such as GF(2) or GF(5). They only work when the arithmetic performed is modulo a prime number. Galois fields can also be formed where the elements are vectors instead of integers if polynomials are used. Finite fields therefore can be found with a number of elements equal to any power of a prime number. Typically we are interested in implementing error correction coding systems using binary arithmetic. All of the fields that are dealt with in Reed Solomon coding systems are of the form GF(2m). This allows performing addition using XORs on the coefficients of the vectors, and multiplication using a combination of ANDs and XORs. A final example considers the field GF(23), which had 8 elements. This can be generated by arithmetic modulo the (irreducible) polynomial P(x) = x3 + x + 1. Elements of this field look like vectors of three bits.
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Table 213 shows the addition and multiplication tables for field GF(23).
Table 213. Modulo Arithmetic for Field GF(23)

Addition + 000 001 010 011 100 101 110 111 000 000 001 010 011 100 101 110 111 001 001 000 011 010 101 100 111 110 010 010 011 000 001 110 111 100 101 011 011 010 001 000 111 110 101 100 100 100 101 110 111 000 001 010 011 101 101 110 111 110 001 000 011 010 110 110 111 100 101 010 011 000 001 111 111 110 101 100 011 010 001 000
Multiplication 000 001 010 011 100 101 110 111 000 000 000 000 000 000 000 000 000 001 000 001 010 011 100 101 110 111 010 000 010 100 110 011 001 111 101 011 000 011 110 101 111 100 001 010 100 000 100 011 111 110 010 101 001 101 000 101 001 100 010 111 011 110 110 000 110 111 001 101 011 010 100 111 000 111 101 010 001 110 100 011
Note that the value 1 (001) appears in every non-zero row of the multiplication table, which indicates that this is a valid field. The channel error can now be modeled as a vector of bits, with a one in every bit position that an error has occurred, and a zero where no error has occurred. Once the error vector has been determined, it can be subtracted from the received message to determine the correct code word.
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The Galois Field Multiply hardware on the C64x is named GMPY4. This instruction performs four parallel operations on 8-bit packed data on the .M unit. The Galois Field Multiplier can be programmed to perform all Galois Multiplies for fields of the form GF(2m), where m can range between 1 and 8 using any generator polynomial. The field size and the polynomial generator are controlled by the Galois Field Polynomial Generator Function Register (GFPGFR). The GFPGFR, shown in Figure 211, contains the Galois field polynomial generator and the field size control bits. These bits control the operation of the GMPY4 instruction. This register can only be set via the MVC instruction. The default function after reset for the GMPY4 instruction is field size=7 and polynomial=0x1D.
Figure 211.Galois Field Polynomial Generator Function Register (GFPGFR)

31 Reserved R, +0 Legend: R W +x 27 26 SIZE R, W, +0x7 24 23 Reserved R, +0 87 POLY R, W, +0x1D 0
Readable by the MVC instruction Writeable by the MVC instruction Value undefined after reset
Table 214. GFPGFR Field Descriptions

Bit Position 3127 2624 238 70 Width 5 3 16 8 Field Name Reserved SIZE Reserved POLY Function Reserved. Read as zero. Ignored on write. Field size. Reserved. Read as zero. Ignored on write. Polynomial Generator.
2.8.2
Special Timing Considerations

If the next execute packet after an MVC instruction that changes the GFPGFR value contains a GMPY4 instruction, then the GMPY4 will be controlled by the newly loaded GFPGFR value.
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Summary of TMS320C64x Architecture Key Extensions
2.9 Summary of TMS320C64x Architecture Key Extensions

This summary lists the key extensions of the C64x architecture, as compared to the C62x architecture. The C64x is a code-compatible member of the C6000 DSP family. The C64x provides a superset of the C62x architecture and also complete code compatibility for existing C62x code running on a C64x device. The C64x provides extensions to the existing C62x architecture in these areas:
-
Register file enhancements Data path extensions Quad 8-bit and dual 16-bit extensions with data flow enhancements Additional functional unit hardware Increased orthogonality of the instruction set Additional instructions that reduce code size and increase register flexibility.
These areas are described in more detail below. Register File Enhancements:
- The C64x has twice as many registers. The C64x has 64 general-purpose
registers, whereas the C62x has 32 general-purpose registers.

- The C62x uses A1, A2, B0, B1 and B2 as conditional registers. In addition to
these, the C64x can also use A0 as a conditional register.

- The C62x register file supports packed 16-bit data types in addition to 32-bit
and 40-bit data types. The C64x register file extends this by supporting packed 8-bit types and 64-bit types. Data Path Extensions:
- The .D unit in the C64x can load and store double words (64 bits) with a
single instruction, whereas the .D unit in the C62x cannot with a single instruction.
- The .D unit in the C64x can now access operands via a data cross path
similar to the .L, .M, and .S functional units. In the C62x only address cross paths on the .D unit are supported.
2-30
- The C64x pipelines data cross path accesses over multiple cycles. This
allows the same register to be used as a data cross path operand by multiple functional units in the same execute packet. In the C62x, only one cross operand is allowed per side. This additional pipelining by the C64x can cause a delay clock cycle known as a cross path stall under certain conditions. See Chapter 5, section 5.6.2 Cross Path Stalls.
- In the C64x, up to two long sources and two long results can be accessed
on each data path every cycle. In the C62x only one long source and one long result per data path could occur every cycle. Additional Functional Unit Hardware:
- Each .M unit can now perform two 16x16 bit multiplies or four 8x8 bit multiplies
every clock cycle.

- The .D units in the C64x can now access words and double words on any
byte boundary by using non-aligned load and store instructions. The C62x only provides aligned load and store instructions.
- The .L units can perform byte shifts and the .M units can perform bi-direc-
tional variable shifts, in addition to the .S units ability to do shifts. The bi-directional shifts directly assist voice-compression codecs (vocoders).
- The .L units can perform quad 8-bit subtends with absolute value. This ab-
solute difference instruction greatly aids motion estimation algorithms.

- Special communications-specific instructions, such as SHFL, DEAL and
GMPY4 have been added to the .M unit to address common operations in error-correcting codes.
- Bit-count and rotate hardware on the .M unit extends support for bit-level al-
gorithms; such as binary morphology, image metric calculations and encryption algorithms. Increased Orthogonality of the Instruction Set:
- The .D unit can now perform 32-bit logical instructions, in addition to the
.S and .L units.
- The .D unit in the C64x now directly supports load and store instructions
for double word data values. The C62x does not directly support loads and stores of double words, and the C67x only directly supports loads of double words.
- The .L, and .D units can now be used to load 5-bit constants, in addition
to the .S units ability to load 16-bit constants.

2-31
Quad 8-bit and Dual 16-bit Extensions with Data Flow Enhancements:
- Extensive collection of PACK and byte shift instructions simplifies manipulation
of packed data types.

- Instructions have been added in the C64x that operate directly on packed
data to streamline data flow and increase instruction set efficiency. The C64x has a comprehensive collection of 8-bit and 16-bit instruction set extensions, which are shown in Table 215.
Table 215. C64x 8-Bit and 16-Bit Instruction Set Extensions.
Operation Multiply Multiply with Saturation Addition/Subtraction Addition with Saturation Absolute Value Subtract with Absolute Value Compare Shift Data Pack/Unpack Data Pack with Saturation Dot-product with Optional Negate Min/Max/Average Bit-expansion (Mask Generation)
Quad 8-bit X
Dual 16-bit X X
X X
X X X
X X X X X X X X X X X X X X
The C62x provides support for 16-bit data with the ADD2/SUB2 instructions. The C64x extends this support to include 8-bit data. Dot-product with negate is not available for 8-bit data.
2-32
Additional Instructions that Reduce Code Size and Increase Register Flexibility:
- BDEC and BPOS combine a branch instruction with the decrement/test posi-
tive of a destination register respectively. These instructions help reduce the number of instructions needed to decrement a loop counter and conditionally branch based upon the value of that counter. Any register can be used as the loop counter, which can free the standard conditional registers (A0A2 and B0B2) for other uses.
- The ADDKPC instruction helps reduce the number of instructions needed
to set up the return address for a function call.

- The BNOP instruction helps reduce the number of instructions required to
perform a branch when NOPs are needed to fill the delay slots of a branch.
- Execute packet boundary restrictions are removed, thereby eliminating all of
the NOPs added to pad fetch packets.
2-33
Chapter 3
TMS320C62x/C64x/C67x Fixed-Point Instruction Set
The TMS320C62x, TMS320C64x, and the TMS320C67x share an instruction set. All of the instructions valid for the C62x are also valid for the C64x and C67x. However, because the C67x is a floating-point device, there are some instructions that are unique to it and do not execute on the fixed-point device. Similarly, the C64x adds functionality to the C62x with some unique instructions. This chapter describes the assembly language instructions that are common to the C62x, C64x, and C67x digital signal processors. Also described are parallel operations, conditional operations, resource constraints, and addressing modes. Instructions unique to the C67x (floating-point addition, subtraction, multiplication, and others) are described in Chapter 4. Instructions unique to the C64x are described in Chapter 5.
Topic
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9
Page
Instruction Operation and Execution Notations . . . . . . . . . . . . . . . . . . 3-2 Mapping Between Instructions and Functional Units . . . . . . . . . . . . . 3-4 TMS320C62x/C64x/C67x Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Delay Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Parallel Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Conditional Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Resource Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 Individual Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3-1
Instruction Operation and Execution Notations
3.1 Instruction Operation and Execution Notations

Table 31 explains the symbols used in the fixed-point instruction descriptions.
Table 31. Fixed-Point Instruction Operation and Execution Notations

Symbol abs(x) and a +a by..z cond Meaning Absolute value of x Bitwise AND Perform 2s-complement subtraction using the addressing mode defined by the AMR Perform 2s-complement addition using the addressing mode defined by the AMR Selection of bits y through z of bit string b Check for either creg equal to 0 or creg not equal to 0 3-bit field specifying a conditional register n-bit constant field (for example, cst5) 32-bit integer value Leftmost 0 bit search of x Leftmost 1 bit search of x 40-bit integer value n least significant bits (for example, lsb16)
creg cstn
int lmb0(x) lmb1(x) long lsbn or LSBn
msbn or MSBn n most significant bits (for example, msb16) nop norm(x) not or op R scstn sint slong slsb16 smsb16 No operation Leftmost nonredundant sign bit of x Bitwise logical complement Bitwise OR Opfields Any general-purpose register n-bit signed constant field Signed 32-bit integer value Signed 40-bit integer value Signed 16 LSB of register Signed 16 MSB of register
3-2
Table 31. Fixed-Point Instruction Operation and Execution Notations (Continued)

Symbol s +s ucstn uint ulong ulsb16 umsb16 Meaning Perform 2s-complement subtraction and saturate the result to the result size if an overflow occurs Perform 2s-complement addition and saturate the result to the result size if an overflow occurs n-bit unsigned constant field (for example, ucst5) Unsigned 32-bit integer value Unsigned 40-bit integer value Unsigned 16 LSB of register Unsigned 16 MSB of register Clear a field in x, specified by b (beginning bit) and e (ending bit) Extract and sign-extend a field in x, specified by l (shift left value) and r (shift right value) Extract an unsigned field in x, specified by l (shift left value) and r (shift right value) Set field in x to all 1s, specified by b (beginning bit) and e (ending bit) Bitwise exclusive OR Signed 32-bit integer value that can optionally use cross path Signed 16 LSB of register that can optionally use cross path Signed 16 MSB of register that can optionally use cross path Unsigned 32-bit integer value that can optionally use cross path Unsigned 16 LSB of register that can optionally use cross path Unsigned 16 MSB of register that can optionally use cross path Assignment Addition Multiplication Subtraction Shift left Shift right with sign extension Shift right with a zero fill
x clear b,e x ext l,r x extu l,r x set b,e

xor xsint xslsb16 xsmsb16 xuint xulsb16 xumsb16 + << >>s >>z
3-3
Mapping Between Instructions and Functional Units
3.2 Mapping Between Instructions and Functional Units

Table 32 shows the mapping between instructions and functional units and Table 33 shows the mapping between functional units and instructions.
Table 32. Instruction to Functional Unit Mapping

.L Unit ABS ADD ADDU AND CMPEQ CMPGT CMPGTU CMPLT CMPLTU LMBD MV NEG NORM NOT OR SADD SAT SSUB SUB SUBU SUBC XOR ZERO
S2 only D2 only
.M Unit MPY MPYU MPYUS MPYSU MPYH MPYHU MPYHUS MPYHSU MPYHL MPYHLU MPYHULS MPYHSLU MPYLH MPYLHU MPYLUHS MPYLSHU SMPY SMPYHL SMPYLH SMPYH ADD ADDK ADD2 AND B disp B IRP B NRP B reg CLR EXT EXTU MV MVC MVK MVKH MVKLH NEG NOT OR
.S Unit SET SHL SHR SHRU SSHL SUB SUBU SUB2 XOR ZERO ADD ADDAB ADDAH ADDAW LDB LDBU LDH LDHU LDW
.D Unit STB (15-bit offset) STH (15-bit offset) STW (15-bit offset) SUB SUBAB SUBAH SUBAW ZERO
LDB (15-bit offset) LDBU (15-bit offset) LDH (15-bit offset) LDHU (15-bit offset) LDW (15-bit offset) MV STB STH STW
3-4
Table 33. Functional Unit to Instruction Mapping

C62x/C64x/C67x Functional Units Instruction ABS ADD ADDU ADDAB ADDAH ADDAW ADDK ADD2 AND B B IRP B NRP B reg CLR CMPEQ CMPGT CMPGTU CMPLT CMPLTU EXT EXTU IDLE LDB mem LDBU mem LDH mem LDHU mem
S2 only D2 only
.L Unit
.M Unit
.S Unit
.D Unit
n n n n n n n n n n n n n n n n n n n n n n n n n n n n
3-5
Table 33. Functional Unit to Instruction Mapping (Continued)

C62x/C64x/C67x Functional Units Instruction LDW mem LDB mem (15-bit offset) LDBU mem (15-bit offset) LDH mem (15-bit offset) LDHU mem (15-bit offset) LDW mem (15-bit offset) LMBD MPY MPYU MPYUS MPYSU MPYH MPYHU MPYHUS MPYHSU MPYHL MPYHLU MPYHULS MPYHSLU MPYLH MPYLHU MPYLUHS MPYLSHU MV MVC MVK
S2 only D2 only
.L Unit
.M Unit
.S Unit
.D Unit
n n n n n n n n n n n n n n n n n n n n n n n n n n n n
3-6

C62x/C64x/C67x Functional Units Instruction MVKH MVKLH NEG NOP NORM NOT OR SADD SAT SET SHL SHR SHRU SMPY SMPYH SMPYHL SMPYLH SSHL SSUB STB mem STH mem STW mem STB mem (15-bit offset) STH mem (15-bit offset) STW mem (15-bit offset) SUB
S2 only D2 only
.L Unit
.M Unit
.S Unit
.D Unit
n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
3-7

C62x/C64x/C67x Functional Units Instruction SUBU SUBAB SUBAH SUBAW SUBC SUB2 XOR ZERO
S2 only D2 only
.L Unit
.M Unit
.S Unit
.D Unit
n n n n
n n n n n n n
3-8
TMS320C62x/C64x/C67x Opcode Map
3.3 TMS320C62x/C64x/C67x Opcode Map

Table 34 and the instruction descriptions in this chapter explain the field syntaxes and values. The C62x, C64x, and C67x opcodes are mapped in Figure 31.
Table 34. TMS320C62x/C64x/C67x Opcode Map Symbol Definitions

Symbol Meaning base address register 3-bit field specifying a conditional register constant constant a constant b destination MVK or MVKH bit load/store opfield addressing mode register offset opfield, field within opcode that specifies a unique instruction parallel execution LDDW bit reserved select side A or B for destination source 2 source 1 n-bit unsigned constant field use cross path for src2 select .D1 or .D2 test for equality with zero or nonzero
baseR creg cst csta cstb dst h ld/st mode offsetR op p r rsv s src2 src1 ucstn
x y
3-9
Figure 31. TMS320C62x/C64x/C67x Opcode Map

Operations on the .L unit 31 29 28 27 23 22 18 17 13 12 11 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src 2
5
src 1/cst
5
op
7
Operations on the .M unit 31 29 28 27
23 22
18 17
13 12 11
6 0
5 0
4 0
3 0
2 0
creg
3
dst
5
src2
5
src 1/cst
5
op
5
Operations on the .D unit 31 29 28 27
23 22
18 17
13 12
6 1
5 0
4 0
3 0
2 0
creg
3
dst
5
src 2
5
src 1/cst
5
op
6
Load/store with 15-bit offset on the .D unit 31 29 28 27 23 22
7 y
3 1
2 1
creg
3
dst/src
5
ucst15
15
ld/st
3
Load/store baseR + offsetR/cst on the .D unit 31 29 28 27 23 22
18 17
13 12
7 y
3 0
2 1
creg
3
dst/src
5
baseR
5
offsetR/ucst5
5
mode
4
ld/st
3
Operations on the .S unit 31 29 28 27
23 22
18 17
13 12 11
5 1
4 0
3 0
2 0
creg
3
dst
5
src 2
5
src1/cst
5
op
6
ADDK on the .S unit 31 29 28 27
23 22
6 1
5 0
4 1
3 0
2 0
creg
3
dst
5
cst
16
3-10
Figure 31. TMS320C62x/C64x/C67x Opcode Map (Continued)

Field operations (immediate forms) on the .S unit 31 29 28 27 23 22 18 17 13 12 8 7 6 5 0 4 0 3 1 2 0 1 0
creg
3
dst
5
src 2
5
csta
5
cstb
5
op
2
MVK and MVKH on the .S unit 31 29 28 27 23 22
5 1
4 0
3 1
2 0
creg
3
dst
5
cst
16
Bcond disp on the .S unit 31 29 28 27
6 0
5 0
4 1
3 0
2 0
creg
3 IDLE 31
cst
21
18 17 16 15 14 13 12 11 10 9 Reserved 14 0 1 1 1 1 0 0 0 0
8 0
7 0
4 0
3 0
2 0
0 0
s p
1
NOP 31 Reserved 14
18 17 16 0
13
0 0 0 0 0 0 0 0 0 0 0 0 0 p 1
src
4
3-11
Delay Slots
3.4 Delay Slots

The execution of fixed-point instructions can be defined in terms of delay slots. The number of delay slots is equivalent to the number of cycles required after the source operands are read for the result to be available for reading. For a single-cycle type instruction (such as ADD), source operands read in cycle i produce a result that can be read in cycle i + 1. For a multiply instruction (MPY), source operands read in cycle i produce a result that can be read in cycle i + 2. Table 35 shows the number of delay slots associated with each type of instruction. Delay slots are equivalent to an execution or result latency. All of the instructions that are common to the C62x, C64x, and C67x have a functional unit latency of 1. This means that a new instruction can be started on the functional unit each cycle. Single-cycle throughput is another term for single-cycle functional unit latency.
Table 35. Delay Slot and Functional Unit Latency Summary

Instruction Type Delay Slots 0 0 0 1 4 5 Functional Unit Latency 1 1 1 1 1 1 Read Cycles Write Cycles Branch Taken NOP (no operation) Store i i i i i i Single cycle Multiply (16 16) Load i+1 i, i + 4 Branch i i+5
Cycle i is in the E1 pipeline phase. The branch to label, branch to IRP, and branch to NRP instructions instruction does not read any registers. The write on cycle i + 4 uses a separate write port from other .D unit instructions.
3-12
Parallel Operations
3.5 Parallel Operations

Instructions are always fetched eight at a time. This constitutes a fetch packet. The basic format of a fetch packet is shown in Figure 32. Fetch packets are aligned on 256-bit (8-word) boundaries.
Figure 32. Basic Format of a Fetch Packet

31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0
p
Instruction A LSBs of the byte address 000002
p
Instruction B 001002
p
Instruction C 010002
p
Instruction D 011002
p
Instruction E 100002
p
Instruction F 101002 Instruction G 110002
p
Instruction H 111002
The execution of the individual instructions is partially controlled by a bit in each instruction, the p-bit. The p -bit (bit 0) determines whether the instruction executes in parallel with another instruction. The p-bits are scanned from left to right (lower to higher address). If the p -bit of instruction i is 1, then instruction i + 1 is to be executed in parallel with (in the the same cycle as) instruction i. If the p-bit of instruction i is 0, then instruction i + 1 is executed in the cycle after instruction i. All instructions executing in parallel constitute an execute packet. An execute packet can contain up to eight instructions. Each instruction in an execute packet must use a different functional unit. An execute packet cannot cross an 8-word boundary. Therefore, the last p-bit in a fetch packet is always set to 0, and each fetch packet starts a new execute packet. There are three types of p -bit patterns for fetch packets. These three p -bit patterns result in the following execution sequences for the eight instructions:
- Fully serial - Fully parallel - Partially serial
Example 31 through Example 33 illustrate the conversion of a p-bit sequence into a cycle-by-cycle execution stream of instructions.
3-13
Parallel Operations
Example 31. Fully Serial p-Bit Pattern in a Fetch Packet

This p-bit pattern:
31 0 31 0 Instruction A Instruction B 0 31 0 Instruction C 0 31 0 Instruction D 0 31 0 Instruction E 0 31 0 Instruction F 0 31 0 Instruction G 0 31 0 Instruction H 0 0
results in this execution sequence:

Cycle/Execute Packet 1 2 3 4 5 6 7 8 Instructions A B C D E F G H
The eight instructions are executed sequentially.
Example 32. Fully Parallel p-Bit Pattern in a Fetch Packet

This p-bit pattern:

Cycle/Execute Packet 1 A B C D
Instructions E F G H
All eight instructions are executed in parallel.
3-14
Parallel Operations
Example 33. Partially Serial p-Bit Pattern in a Fetch Packet

This p-bit pattern:

Cycle/Execute Packet 1 2 3 4
Note:
Instructions A B C F D G E H
Instructions C, D, and E do not use any of the same functional units, cross paths, or other data path resources. This is also true for instructions F, G, and H.
3.5.1
Example Parallel Code

The || characters signify that an instruction is to execute in parallel with the previous instruction. The code for the fetch packet in Example 33 would be represented as this:
instruction A instruction B instruction C || instruction D || instruction E instruction F || instruction G || instruction H
3.5.2
Branching Into the Middle of an Execute Packet

If a branch into the middle of an execute packet occurs, all instructions at lower addresses are ignored. In Example 33, if a branch to the address containing instruction D occurs, then only D and E execute. Even though instruction C is in the same execute packet, it is ignored. Instructions A and B are also ignored because they are in earlier execute packets. If your result depends on executing A, B, or C, the branch to the middle of the execute packet will produce an erroneous result.
3-15
Conditional Operations
3.6 Conditional Operations

All instructions can be conditional. The condition is controlled by a 3-bit opcode field (creg) that specifies the condition register tested, and a 1-bit field (z) that specifies a test for zero or nonzero. The four MSBs of every opcode are creg and z. The specified condition register is tested at the beginning of the E1 pipeline stage for all instructions. For more information on the pipeline, see Chapter 6, TMS320C62x/C64x Pipeline, and Chapter 7, TMS320C67x Pipeline. If z = 1, the test is for equality with zero. If z = 0, the test is for nonzero. The case of creg = 0 and z = 0 is treated as always true to allow instructions to be executed unconditionally. The creg field is encoded in the instruction opcode as shown in Table 36.
Table 36. Registers That Can Be Tested by Conditional Operations

Specified Conditional C diti l Register Unconditional Reserved{ B0 B1 B2 A1 A2 Reserved
Note:
creg
Bit 31 0 0 0 0 0 1 1 1 30 0 0 0 1 1 0 0 1 29 0 0 1 0 1 0 1 x
z
28 0 1 z z z z z x
x can be any value. The C64x can also use A0 as a conditional register. Please see Chapter 5, section 5.5 Conditional Operations. This value is reserved for software breakpoints that are used for emulation purposes.
Conditional instructions are represented in code by using square brackets, [ ], surrounding the condition register name. The following execute packet contains two ADD instructions in parallel. The first ADD is conditional on B0 being nonzero. The second ADD is conditional on B0 being zero. The character ! indicates the inverse of the condition.
[B0] ADD || [!B0] ADD .L1 .L2 A1,A2,A3 B1,B2,B3
The above instructions are mutually exclusive. This means that only one will execute. If they are scheduled in parallel, mutually exclusive instructions are constrained as described in section 3.7. If mutually exclusive instructions share any resources as described in section 3.7, they cannot be scheduled in parallel (put in the same execute packet), even though only one will execute.
3-16
Resource Constraints
3.7 Resource Constraints

No two instructions within the same execute packet can use the same resources. Also, no two instructions can write to the same register during the same cycle. The following sections describe how an instruction can use each of the resources. Chapter 5, section 5.6 discusses the differences between the C62x/C67x and the C64x with respect to resource constaints.
3.7.1
Constraints on Instructions Using the Same Functional Unit

Two instructions using the same functional unit cannot be issued in the same execute packet. The following execute packet is invalid:
|| ADD .S1 SHR .S1 A0, A1, A2 ; \ .S1 is used for A3, 15, A4 ; / both instructions
The following execute packet is valid:

|| ADD .L1 SHR .S1 A0, A1, A2 ; \ Two different functional A3, 15, A4 ; / units are used
3.7.2
Constraints on Cross Paths (1X and 2X)

One unit (either a .S, .L, or .M unit) per data path, per execute packet, can read a source operand from its opposite register file via the cross paths (1X and 2X). For example, .S1 can read both of an instructions operands from the A register file, or it can read one operand from the B register file using the 1X cross path and the other from the A register file. This is denoted by an X following the unit name in the instruction syntax. Two instructions using the same cross path between register files cannot be issued in the same execute packet, because there is only one path from A to B and one path from B to A. The following execute packet is invalid:
|| ADD.L1X MPY.M1X A0,B1,A1 ; \ 1X cross path is used A4,B4,A5 ; / for both instructions

|| ADD.L1X MPY.M2X A0,B1,A1 ; \ Instructions use the 1X and B4,A4,B2 ; / 2X cross paths
The operand will come from a register file opposite of the destination if the x bit in the instruction field is set (shown in the opcode map located in Figure 31 on page 3-10).
3-17
3.7.3
Constraints on Loads and Stores

Load/store instructions can use an address pointer from one register file while loading to or storing from the other register file. Two load/store instructions using a destination/source from the same register file cannot be issued in the same execute packet. The address register must be on the same side as the .D unit used. The following execute packet is invalid:
LDW.D1 || LDW.D2 *A0,A1 ; \ .D2 unit must use the address *A2,B2 ; / register from the B register file

LDW.D1 || LDW.D2 *A0,A1 ; \ Address registers from correct *B0,B2 ; / register files
Two loads and/or stores loading to and/or storing from the same register file cannot be issued in the same execute packet. The following execute packet is invalid:
LDW.D1 || STW.D2 *A4,A5 ; \ Loading to and storing from the A6,*B4 ; / same register file
The following execute packets are valid:

LDW.D1 || STW.D2 LDW.D1 || LDW.D2 *A4,B5 ; \ Loading to, and storing from A6,*B4 ; / different register files *A0,B2 ; \ Loading to *B0,A1 ; / different register files
3.7.4
Constraints on Long (40-Bit) Data

Because the .S and .L units share a read register port for long source operands and a write register port for long results, only one long result may be issued per register file in an execute packet. All instructions with a long result on the .S and .L units have zero delay slots. See section 2.1 on page 2-5 for the order for long pairs. The following execute packet is invalid:
ADD.L1 || SHL.S1 A5:A4,A1,A3:A2 A8,A9,A7:A6 ; \ Two long writes ; / on A register file
3-18

ADD.L1 || SHL.S2 A5:A4,A1,A3:A2 B8,B9,B7:B6 ; \ One long write for ; / each register file
Because the .L and .S units share their long read port with the store port, operations that read a long value cannot be issued on the .L and/or .S units in the same execute packet as a store. The following execute packet is invalid:
ADD .L1 || STW .D1 A5:A4,A1,A3:A2 A8,*A9 ; \ Long read operation and a ; / store

ADD.L1 || STW.D1 A4, A1, A3:A2 A8,*A9 ; \ No long read with ; / with the store
3.7.5
Constraints on Register Reads

More than four reads of the same register cannot occur on the same cycle. Conditional registers are not included in this count. The following code sequences are invalid:
|| || || || MPY ADD SUB MPY ADD SUB .M1 .L1 .D1 .M1 .L1 .D2x A1,A1,A4 ; five reads of register A1 A1,A1,A5 A1,A2,A3 A1,A1,A4 ; five reads of register A1 A1,A1,A5 A1,B2,B3
This code sequence is valid:

|| [A1] || MPY ADD SUB .M1 A1,A1,A4 ; only four reads of A1 .L1 A0,A1,A5 .D1 A1,A2,A3
3.7.6
Constraints on Register Writes

Two instructions cannot write to the same register on the same cycle. Two instructions with the same destination can be scheduled in parallel as long as they do not write to the destination register on the same cycle. For example, a MPY issued on cycle i followed by an ADD on cycle i + 1 cannot write to the same register because both instructions write a result on cycle i + 1. Therefore, the following code sequence is invalid unless a branch occurs after the MPY, causing the ADD not to be issued.
MPY ADD .M1 A0,A1,A2 .L1 A4,A5,A2
3-19
However, this code sequence is valid:

|| MPY ADD .M1 A0,A1,A2 .L1 A4,A5,A2
Figure 33 shows different multiple-write conflicts. For example, ADD and SUB in execute packet L1 write to the same register. This conflict is easily detectable. MPY in packet L2 and ADD in packet L3 might both write to B2 simultaneously; however, if a branch instruction causes the execute packet after L2 to be something other than L3, a conflict would not occur. Thus, the potential conflict in L2 and L3 might not be detected by the assembler. The instructions in L4 do not constitute a write conflict because they are mutually exclusive. In contrast, because the instructions in L5 may or may not be mutually exclusive, the assembler cannot determine a conflict. If the pipeline does receive commands to perform multiple writes to the same register, the result is undefined.
Figure 33. Examples of the Detectability of Write Conflicts by the Assembler

L1: || L2: L3: ADD.L2 SUB.S2 MPY.M2 ADD.L2 B5,B6,B7 ; \ detectable, conflict B8,B9,B7 ; / B0,B1,B2 ; \ not detectable B3,B4,B2 ; / B5,B6,B7 ; \ detectable, no conflict B8,B9,B7 ; / B5,B6,B7 ; \ not detectable B8,B9,B7 ; /
L4:[!B0] ADD.L2 || [B0] SUB.S2 L5:[!B1] ADD.L2 || [B0] SUB.S2
3-20
Addressing Modes
3.8 Addressing Modes

The addressing modes on the C62x, C64x, and C67x are linear, circular using BK0, and circular using BK1. The mode is specified by the addressing mode register, or AMR (defined in Chapter 2). All registers can perform linear addressing. Only eight registers can perform circular addressing: A4A7 are used by the .D1 unit and B4B7 are used by the .D2 unit. No other units can perform circular addressing. LDB(U)/LDH(U)/LDW, STB/STH/STW, ADDAB/ADDAH/ADDAW/ADDAD, and SUBAB/SUBAH/SUBAW instructions all use the AMR to determine what type of address calculations are performed for these registers. Additional information on addressing modes for the C64x can be found in Chapter 5.
3.8.1
3.8.1.1
Linear Addressing Mode

LD/ST Instructions
For load and store instructions, linear mode simply shifts the offsetR/cst operand to the left by 2, 1, or 0 for word, halfword, or byte access, respectively, and then performs an add or a subtract to baseR (depending on the operation specified).
3.8.1.2
ADDA/SUBA Instructions
For integer addition and subtraction instructions, linear mode simply shifts the src1/cst operand to the left by 2, 1, or 0 for word, halfword, or byte data sizes, respectively, and then performs the add or subtract specified.
3.8.2
Circular Addressing Mode

The BK0 and BK1 fields in the AMR specify block sizes for circular addressing. See section 2.6.2, on page 2-14, for more information on the AMR.
3.8.2.1
LD/ST Instructions
After shifting offsetR/cst to the left by 2, 1, or 0 for LDW, LDH(U), or LDB(U), respectively, an add or subtract is performed with the carry/borrow inhibited between bits N and N + 1. Bits N + 1 to 31 of baseR remain unchanged. All other carries/borrows propagate as usual. If you specify an offsetR/cst greater than the circular buffer size, 2(N + 1), the effective offsetR/cst is modulo the circular buffer size (see Example 34). The circular buffer size in the AMR is not scaled; for example, a block size of 4 is 4 bytes, not 4 data size (byte, halfTMS320C62x/C64x/C67x Fixed-Point Instruction Set
3-21
Addressing Modes
word, word). So, to perform circular addressing on an array of 8 words, a size of 32 should be specified, or N = 4. Example 34 shows a LDW performed with register A4 in circular mode and BK0 = 4, so the buffer size is 32 bytes, 16 halfwords, or 8 words. The value put in the AMR for this example is 0004 0001h.
Example 34. LDW in Circular Mode

LDW .D1 *++A4[9],A1 1 cycle after LDW
A4 0000 0104h A1 XXXX XXXXh
Before LDW
A4 0000 0100h A1 XXXX XXXXh
5 cycles after LDW

A4 0000 0104h A1 1234 5678h
mem
104h
1234 5678h
mem 104h
1234 5678h
mem
104h
1234 5678h
Note:
9h words is 24h bytes. 24h bytes is 4 bytes beyond the 32-byte (20h) boundary 100h11Fh; thus, it is wrapped around to (124h 20h = 104h).
3.8.2.2
After shifting src1/cst to the left by 2, 1, or 0 for ADDAW, ADDAH, or ADDAB, respectively, an add or a subtract is performed with the carry/borrow inhibited between bits N and N + 1. Bits N + 1 to 31 (inclusive) of src2 remain unchanged. All other carries/borrows propagate as usual. If you specify src1 greater than the circular buffer size, 2(N + 1), the effective offsetR/cst is modulo the circular buffer size (see Example 35). The circular buffer size in the AMR is not scaled; for example, a block size of 4 is 4 bytes, not 4 data size (byte, halfword, word). So, to perform circular addressing on an array of 8 words, a size of 32 should be specified, or N = 4. Example 35 shows an ADDAH performed with register A4 in circular mode and BK0 = 4, so the buffer size is 32 bytes, 16 halfwords, or 8 words. The value put in the AMR for this example is 0004 0001h.
Example 35. ADDAH in Circular Mode

ADDAH .D1 A4,A1,A4 1 cycle after ADDAH
A4 0000 0106h A1 0000 0013h
Before ADDAH
A4 0000 0100h A1 0000 0013h
Note:
13h halfwords is 26h bytes. 26h bytes is 6 bytes beyond the 32-byte (20h) boundary 100h11Fh; thus, it is wrapped around to (126h 20h = 106h).
3-22
Addressing Modes
3.8.3
Syntax for Load/Store Address Generation

The C62x, C64x, and C67x CPUs have a load/store architecture, which means that the only way to access data in memory is with a load or store instruction. Table 37 shows the syntax of an indirect address to a memory location. Sometimes a large offset is required for a load/store. In this case you can use the B14 or B15 register as the base register, and use a 15-bit constant (ucst15) as the offset.
Table 37. Indirect Address Generation for Load/Store

No Modification of Address Register *R *+R[ucst5] *R[ucst5] *+B14/B15[ucst15] *+R[offsetR] *R[offsetR] Preincrement or Predecrement of Address Register *++R * R *+ +R[ucst5] * R[ucst5] not supported *++R[offsetR] * R[offsetR] Postincrement or Postdecrement of Address Register *R++ *R *R+ +[ucst5] *R [ucst5] not supported *R+ +[offsetR] *R [offsetR]
Addressing Type Register indirect Register relative Register relative with 15-bit constant offset Base + index
3-23
Individual Instruction Descriptions
3.9 Individual Instruction Descriptions

This section gives detailed information on the fixed-point instruction set for the C62x, C64x, and C67x. Each instruction presents the following information:
-
Assembler syntax Functional units Operands Opcode Description Execution Instruction type Delay slots Functional Unit Latency Examples
The ADD instruction is used as an example to familiarize you with the way each instruction is described. The example describes the kind of information you will find in each part of the individual instruction description and where to obtain more information.
3-24
Example
Example
Syntax
The way each instruction is described.

EXAMPLE (.unit) src, dst .unit = .L1, .L2, .S1, .S2, .D1, .D2
src and dst indicate source and destination, respectively. The (.unit) dictates which functional unit the instruction is mapped to (.L1, .L2, .S1, .S2, .M1, .M2, .D1, or .D2).
A table is provided for each instruction that gives the opcode map fields, units the instruction is mapped to, types of operands, and the opcode. The opcode map, repeated from the summary figure on page 3-10 shows the various fields that make up each instruction. These fields are described in Table 34 on page 3-9. There are instructions that can be executed on more than one functional unit. Table 38 shows how this situation is documented for the ADD instruction. This instruction has three opcode map fields: src1, src2, and dst. In the seventh row, the operands have the types cst5, long, and long for src1, src2, and dst, respectively. The ordering of these fields implies cst5 + long long, where + represents the operation being performed by the ADD. This operation can be done on .L1 or .L2 (both are specified in the unit column). The s in front of each operand signifies that src1 (scst5), src2 (slong), and dst (slong) are all signed values. In the third row, src1, src2, and dst are int, int, and long, respectively. The u in front of each operand signifies that all operands are unsigned. Any operand that begins with x can be read from a register file that is different from the destination register file. The operand comes from the register file opposite the destination if the x bit in the instruction is set (shown in the opcode map).
3-25
Example
Table 38. Relationships Between Operands, Operand Size, Signed/Unsigned, Functional Units, and Opfields for Example Instruction (ADD)
Opcode map field used...
For operand type... sint xsint sint sint xsint slong uint xuint ulong xsint slong slong xuint ulong ulong scst5 xsint sint scst5 slong slong sint xsint sint scst5 xsint sint sint sint sint sint ucst5 sint
Unit .L1, .L2
Opfield 0000011
Mnemonic ADD
src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src2 src1 dst src2 src1 dst
.L1, .L2
0100011
ADD
.L1, .L2
0101011
ADDU
.L1, .L2
0100001
ADD
.L1, .L2
0101001
ADDU
.L1, .L2
0000010
ADD
.L1, .L2
0100000
ADD
.S1, .S2
000111
ADD
.S1, .S2
000110
ADD
.D1, .D2
010000
ADD
.D1, .D2
010010
ADD
3-26
Example
Description Instruction execution and its effect on the rest of the processor or memory contents are described. Any constraints on the operands imposed by the processor or the assembler are discussed. The description parallels and supplements the information given by the execution block.
Execution for .L1, .L2 and .S1, .S2 Opcodes src1 + src2 dst if (cond) else nop Execution for .D1, .D2 Opcodes if (cond) else
src2 + src1 dst nop
The execution describes the processing that takes place when the instruction is executed. The symbols are defined in Table 31 on page 3-2. Pipeline This section contains a table that shows the sources read from, the destinations written to, and the functional unit used during each execution cycle of the instruction. This section gives the type of instruction. See section 6.2 on page 6-14 for information about the pipeline execution of this type of instruction. This section gives the number of delay slots the instruction takes to execute See section 3.4 on page 3-12 for an explanation of delay slots.
Instruction Type
Delay Slots
Functional Unit Latency This section gives the number of cycles that the functional unit is in use during the execution of the instruction. Example Examples of instruction execution. If applicable, register and memory values are given before and after instruction execution.
3-27
ABS
ABS
Syntax
Integer Absolute Value With Saturation

ABS (.unit) src2, dst .unit = .L1, .L2
Opcode map field used... For operand type... xsint sint slong slong Unit .L1, .L2 .L1, L2 Opfield 0011010 0111000
src2 dst src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
op
7
Description Execution
The absolute value of src2 is placed in dst. if (cond) else abs(src2) dst nop
The absolute value of src2 when src2 is an sint is determined as follows: 1) If src2 w 0, then src2 dst 2) If src2 t 0 and src2 231, then src2 dst 3) If src2 = 231, then 231 1 dst The absolute value of src2 when src2 is an slong is determined as follows: 1) If src2 w 0, then src2 dst 2) If src2 t 0 and src2 239, then src2 dst 3) If src2 = 239, then 239 1 dst Pipeline
src2 dst
.L
Instruction Type Delay Slots

3-28
Single-cycle 0
ABS
Example 1
ABS .L1
A1,A5 1 cycle after instruction A1 8000 4E3Dh A5 7FFF B1C3h 2147463619 2147463619
Before instruction A1 8000 4E3Dh A5 XXXX XXXXh 2147463619
Example 2
ABS .L1
A1,A5 1 cycle after instruction A1 3FF6 0010h A5 3FF6 0010h 1073086480 1073086480
Before instruction A1 3FF6 0010h A5 XXXX XXXXh 1073086480
3-29
ADD(U)
ADD(U)
Syntax
Signed or Unsigned Integer Addition Without Saturation

ADD (.unit) src1, src2, dst or ADDU (.L1 or .L2) src1, src2, dst or ADD (.D1 or .D2) src2, src1, dst .unit = .L1, .L2, .S1, .S2
Opcode map field used... For operand type... sint xsint sint sint xsint slong uint xuint ulong xsint slong slong xuint ulong ulong scst5 xsint sint scst5 slong slong sint xsint sint scst5 xsint sint sint sint sint sint ucst5 sint Unit .L1, .L2 Opfield 0000011
src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src2 src1 dst src2 src1 dst
.L1, .L2
0100011
.L1, .L2
0101011
.L1, .L2
0100001
.L1, .L2
0101001
.L1, .L2
0000010
.L1, .L2
0100000
.S1, .S2
000111
.S1, .S2
000110
.D1, .D2
010000
.D1, .D2
010010
3-30
ADD(U)
Opcode
31 29 28 27
.L unit
23 22 18 17 13 12 11 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
7
Opcode
31 29 28 27
.S unit
23 22 18 17 13 12 11 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
6
Description for .L1, .L2 and .S1, .S2 Opcodes src2 is added to src1. The result is placed in dst. Execution for .L1, .L2 and .S1, .S2 Opcodes if (cond) src1 + src2 dst else nop Opcode
31 29 28 27
.D unit
23 22 18 17 13 12 7 6 1 5 0 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
6
Description for .D1, .D2 Opcodes src1 is added to src2. The result is placed in dst. Execution for .D1, .D2 Opcodes if (cond) else Pipeline
Pipeline Stage Read Written Unit in use
src2 + src1 dst nop

E1
src1, src2 dst

.L, .S, or .D
Single-cycle 0
3-31
ADD(U)
Example 1
ADD .L2X
A1,B1,B2 1 cycle after instruction A1 0000 325Ah B1 FFFF FF12h B2 0000 316Ch 12652
Before instruction A1 0000 325Ah B1 FFFF FF12h B2 XXXX XXXXh 12890 238
Example 2
ADDU .L1
A1,A2,A5:A4 1 cycle after instruction A1 0000 325Ah A2 FFFF FF12h A5:A4 0000 0001h 0000 316Ch 4294979948
Before instruction A1 0000 325Ah A2 FFFF FF12h A5:A4 XXXX XXXX 12890 4294967058
Example 3
ADDU .L1
A1,A3:A2,A5:A4 1 cycle after instruction A1 0000 325Ah A3:A2 0000 00FFh FFFF FF12h
Before instruction A1 0000 325Ah 12890 A3:A2 0000 00FFh FFFF FF12h 1099511627538 A5:A4 0000 0000h 0000 0000h 0
Unsigned 32-bit integer Unsigned 40-bit (long) integer
A5:A4 0000 0000h 0000 316Ch 12652
Example 4
ADD .L1
A1,A3:A2,A5:A4 1 cycle after instruction A1 0000 325Ah A3:A2 0000 00FFh FFFF FF12h
Before instruction A1 0000 325Ah 12890 A3:A2 0000 00FFh FFFF FF12h 228 A5:A4 0000 0000h 0000 0000h 0
Signed 40-bit (long) integer
A5:A4 0000 0000h 0000 316Ch 12652
Example 5
ADD .L1
13,A1,A6 1 cycle after instruction A1 0000 325Ah A6 0000 324Dh 12877
Before instruction A1 0000 325Ah A6 XXXX XXXXh 12890
3-32
ADD(U)
Example 6
ADD .D1
A1,26,A6 1 cycle after instruction A1 0000 325Ah A6 0000 3274h 12916
Before instruction A1 0000 325Ah A6 XXXX XXXXh 12890
3-33
ADDAB/ADDAH/ADDAW
ADDAB/ADDAH/ADDAW
Syntax
Integer Addition Using Addressing Mode
ADDAB (.unit) src2, src1, dst or ADDAH (.unit) src2, src1, dst or ADDAW (.unit) src2, src1, dst .unit = .D1 or .D2
Opcode map field used... For operand type... sint sint sint sint ucst5 sint Unit .D1, .D2 Opfield byte: 110000 halfword: 110100 word: 111000 byte: 110010 halfword: 110110 word: 111010
src2 src1 dst src2 src1 dst
.D1, .D2
Opcode
31 29 28 27 23 22 18 17 13 12 7 6 1 5 0 4 0 3 0 2 0 1 0
creg
3
dst
5
src 2
5
src 1/cst
5
op
6
Description
src1 is added to src2 using the addressing mode specified for src2. The addition defaults to linear mode. However, if src2 is one of A4A7 or B4B7, the mode can be changed to circular mode by writing the appropriate value to the AMR (see section 2.6.2). src1 is left shifted by 1 or 2 for halfword and word data sizes respectively. Byte, halfword, and word mnemonics are ADDAB, ADDAH, and ADDAW, respectively. The result is placed in dst.
if (cond) else
Pipeline stage Read Written Unit in use
Execution Pipeline
src2 +a src1 dst nop

E1
src1, src2 dst

.D

3-34
Single-cycle 0
ADDAB/ADDAH/ADDAW
Example 1
ADDAB .D1
A4,A2,A4 1 cycle after instruction A2 0000 000Bh A4 0000 0103h AMR 0002 0001h
Before instruction A2 0000 000Bh A4 0000 0100h AMR 0002 0001h
BK0 = 2 size = 8 A4 in circular addressing mode using BK0
Example 2
ADDAH .D1
A4,A2,A4 1 cycle after instruction A2 0000 000Bh A4 0000 0106h AMR 0002 0001h
Before instruction A2 0000 000Bh A4 0000 0100h AMR 0002 0001h
Example 3
ADDAW .D1
A4,2,A4 1 cycle after instruction A4 0002 0000h AMR 0002 0001h
Before instruction A4 0002 0000h AMR 0002 0001h
3-35
ADDK
ADDK
Syntax
Integer Addition Using Signed 16-Bit Constant

ADDK (.unit) cst, dst .unit = .S1 or .S2
Opcode map field used... For operand type... Unit .S1, .S2
cst dst
scst16 uint
Opcode
31 29 28 27 23 22 7 6 1 0 1 0 0 0
creg
3
z
1
dst
5
cst
16
s
1
p
1
Description
A 16-bit signed constant is added to the dst register specified. The result is placed in dst. if (cond) else
Execution Pipeline
cst + dst dst nop

E1
cst dst
.S
Instruction Type Delay Slots Example
Single-cycle 0
ADDK .S1 15401,A1 1 cycle after instruction A1 0021 740Ah 2192394
Before instruction A1 0021 37E1h 2176993
3-36
ADD2
ADD2
Syntax
Two 16-Bit Integer Adds on Upper and Lower Register Halves

ADD2 (.unit) src1, src2, dst .unit = .S1 or .S2
Opcode map field used... For operand type... sint xsint sint Unit .S1, .S2
src1 src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 6 000001 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1
5
Description
The upper and lower halves of the src1 operand are added to the upper and lower halves of the src2 operand. Any carry from the lower half add does not affect the upper half add. if (cond) { ((lsb16(src1) + lsb16(src2)) and FFFFh) or ((msb16(src1) + msb16(src2)) << 16) dst } nop
E1
Execution
else Pipeline
src1, src2 dst

.S
Single-cycle 0
ADD2 .S1X A1,B1,A2 1 cycle after instruction A1 0021 37E1h A2 03BB 1C99h 922 58552 B1 039A E4B8h 955 7321
Before instruction A1 0021 37E1h A2 XXXX XXXXh B1 039A E4B8h 33 14305
3-37
AND
AND
Syntax
Bitwise AND
AND (.unit) src1, src2, dst .unit = .L1 or .L2, .S1 or .S2
Opcode map field used... For operand type... uint xuint uint scst5 xuint uint uint xuint uint scst5 xuint uint Unit .L1, .L2 Opfield 1111011
src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst
.L1, .L2
1111010
.S1, .S2
011111
.S1, .S2
011110
Opcode
.L unit form:
31 29 28 27 23 22 18 17 13 12 11 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
7
.S unit form:
31 29 28 27 23 22 18 17 13 12 11 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
6
Description
A bitwise AND is performed between src1 and src2. The result is placed in dst. The scst5 operands are sign extended to 32 bits. if (cond) else
Execution
src1 and src2 dst nop
3-38
AND
Delay Slots Pipeline 0
E1
src1, src2 dst

.L or .S
Instruction Type Example 1
Single-cycle
AND .L1X A1,B1,A2 1 cycle after instruction A1 F7A1 302Ah A2 02A0 2020h B1 02B6 E724h
Before instruction A1 F7A1 302Ah A2 XXXX XXXXh B1 02B6 E724h
Example 2
AND .L1
15,A1,A3 1 cycle after instruction A1 32E4 6936h A3 0000 0006h
Before instruction A1 32E4 6936h A3 XXXX XXXXh
3-39
B
Syntax
Branch Using a Displacement

B (.unit) label .unit = .S1 or .S2
Opcode map field used... For operand type... Unit .S1, .S2
cst
scst21
Opcode
31 29 28 27 7 6 0 0 1 0 0 0
creg
3
z
1
cst
21
s
1
p
1
Description
A 21-bit signed constant specified by cst is shifted left by 2 bits and is added to the address of the first instruction of the fetch packet that contains the branch instruction. The result is placed in the program fetch counter (PFC). The assembler/linker automatically computes the correct value for cst by the following formula:
cst = (label PCE1) >> 2

If two branches are in the same execute packet and both are taken, behavior is undefined. Two conditional branches can be in the same execute packet if one branch uses a displacement and the other uses a register, IRP, or NRP. As long as only one branch has a true condition, the code executes in a well-defined way. Execution if (cond) else Notes: 1) PCE1 (program counter) represents the address of the first instruction in the fetch packet in the E1 stage of the pipeline. PFC is the program fetch counter. 2) The execute packets in the delay slots of a branch cannot be interrupted. This is true regardless of whether the branch is taken. 3) See section 3.5.2 on page 3-15 for information on branching into the middle of an execute packet.
cst << 2 + PCE1 PFC nop
3-40
Pipeline
Target Instruction Pipeline Stage Read Written Branch Taken Unit in use .S n E1 PS PW PR DP DC E1
Branch 5 Table 39 gives the program counter values and actions for the following code example.
Example
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0004 0008 000C 0010 0014 0018 001C 0020 B ADD || ADD LOOP: MPY || SUB MPY MPY SHR ADD .S1 .L1 .L2 .M1X .D1 .M1 .M1 .S1 .D1 LOOP A1, A2, B1, B2, A3, B3, A5, A6, A3, A6, A6, A7, A4, 15, A4, A6, A3 B3 A4 A6 A5 A8 A4 A4
Table 39. Program Counter Values for Example Branch Using a Displacement
Cycle Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Program Counter Value 0000 0000h 0000 0004h 0000 000Ch 0000 0014h 0000 0018h 0000 001Ch 0000 000Ch 0000 0014h Branch target code executes Action Branch command executes (target code fetched)
3-41
B
Syntax
Branch Using a Register

B (.unit) src2 .unit = .S2
Opcode map field used... For operand type... xuint Unit .S2
src2
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 001101 6 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
Description
src2 is placed in the PFC.

If two branches are in the same execute packet and are both taken, behavior is undefined. Two conditional branches can be in the same execute packet if one branch uses a displacement and the other uses a register, IRP, or NRP. As long as onlly one branch has a true condition, the code executes in a well-defined way.
Execution
if (cond) else Notes:
src2 PFC nop
1) This instruction executes on .S2 only. PFC is program fetch counter. 2) The execute packets in the delay slots of a branch cannot be interrupted. This is true regardless of whether the branch is taken. Pipeline
Target Instruction Pipeline Stage Read Written Branch Taken Unit in use .S2 n E1 PS PW PR DP DC E1
src2
3-42
B
Instruction Type Delay Slots Branch 5 Table 310 gives the program counter values and actions for the following code example. In this example, the B10 register holds the value 1000 000Ch. Example
1000 1000 1000 1000 1000 1000 1000 1000 1000
B10 1000 000Ch
0000 0004 0008 000C 0010 0014 0018 001C 0020
B ADD || ADD MPY || SUB MPY MPY SHR ADD
.S2 .L1 .L2 .M1X .D1 .M1 .M1 .S1 .D1
B10 A1, B1, A3, A5, A3, A6, A4, A4,
A2, B2, B3, A6, A6, A7, 15, A6,
A3 B3 A4 A6 A5 A8 A4 A4
Table 310. Program Counter Values for Example Branch Using a Register
Cycle Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Program Counter Value 1000 0000h 1000 0004h 1000 000Ch 1000 0014h 1000 0018h 1000 001Ch 1000 000Ch 1000 0014h Branch target code executes Action Branch command executes (target code fetched)
3-43
B IRP
B IRP
Syntax
Branch Using an Interrupt Return Pointer

B (.unit) IRP
.unit = .S2
Opcode map field used... For operand type... xsint Unit .S2
src2
Opcode
31 29 28 27 23 22 18 17 00110 5 00000 5 13 12 11 x 000011 6 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
Description
IRP is placed in the PFC. This instruction also moves PGIE to GIE. PGIE is unchanged. If two branches are in the same execute packet and are both taken, behavior is undefined. Two conditional branches can be in the same execute packet if one branch uses a displacement and the other uses a register, IRP, or NRP. As long as only one branch has a ture condition, the code executes in a well-defined way.
Execution
IRP PFC nop
1) This instruction executes on .S2 only. PFC is the program fetch counter. 2) Refer to the chapter on interrupts for more information on IRP, PGIE, and GIE. 3) The execute packets in the delay slots of a branch cannot be interrupted. This is true regardless of whether the branch is taken.
3-44
B IRP
Pipeline
Pipeline Stage Read Written Branch Taken Unit in use .S2 E1 IRP PS PW
Target Instruction PR DP DC E1
Example
Given that an interrupt occurred at

PC = 0000 1000 IRP = 0000 1000
0000 0000 0000 0000 0000 0000 0000
0020 0024 0028 002C 0030 0034 0038
B ADD MPY NOP SHR ADD ADD
.S2 .S1 .M1 .S1 .L1 .L2
IRP A0, A2, A1 A1, A0, A1 A1, 15, A1 A1, A2, A1 B1, B2, B3
Table 311. Program Counter Values for B IRP

Cycle Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Program Counter Value (Hex) 0000 0020 0000 0024 0000 0028 0000 002C 0000 0030 0000 0034 0000 1000 Branch target code executes Action Branch command executes (target code fetched)
3-45
B NRP
B NRP
Syntax
Branch Using NMI Return Pointer

B (.unit) NRP
.unit = .S2
Opcode map field used... For operand type... xsint Unit .S2
src2
Opcode
31 29 28 27 23 22 18 17 00111 5 00000 5 13 12 11 x 000011 6 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
Description
NRP is placed in the PFC. This instruction also sets NMIE. PGIE is unchanged. If two branches are in the same execute packet and are both taken, behavior is undefined. Two conditional branches can be in the same execute packet if one branch uses a displacement and the other uses a register, IRP, or NRP. As long as only one branch has a true condition, the code executes in a well-defined way.
Execution
NRP PFC nop
1) This instruction executes on .S2 only. PFC is program fetch counter. 2) Refer to the chapter on interrupts for more information on NRP and NMIE. 3) The execute packets in the delay slots of a branch cannot be interrupted. This is true regardless of whether the branch is taken.
3-46
B NRP
Pipeline
Pipeline Stage Read Written Branch Taken Unit in use .S2 E1 NRP PS PW
Target Instruction PR DP DC E1
Example
Given that an interrupt occurred at

PC = 0000 1000 NRP = 0000 1000
0000 0000 0000 0000 0000 0000 0000
0020 0024 0028 002C 0030 0034 0038
B ADD MPY NOP SHR ADD ADD
.S2 .S1 .M1 .S1 .L1 .L2
NRP A0, A2, A1 A1, A0, A1 A1, 15, A1 A1, A2, A1 B1, B2, B3
Table 312. Program Counter Values for B NRP

Cycle Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Program Counter Value (Hex) 0000 0020 0000 0024 0000 0028 0000 002C 0000 0030 0000 0034 0000 1000 Branch target code executes Action Branch command executes (target code fetched)
3-47
CLR
CLR
Syntax
Clear a Bit Field

CLR (.unit) src2, csta, cstb, dst or CLR (.unit) src2, src1, dst .unit = .S1 or .S2
Opcode map field used... For operand type... uint ucst5 ucst5 uint xuint uint uint Unit .S1, .S2 Opfield 11
src2 csta cstb dst src2 src1 dst
.S1, .S2
111111
Opcode
Constant form:
31 29 28 27 23 22 18 17 13 12 8 7 6 5 0 0 1 0 0
creg
3
z
1
dst
5
src2
5
csta
5
cstb
5
1 0 2
s
1
p
1
Register form:
31 29 28 27 23 22 18 17 13 12 11 6 1 1 6 0 1 1 5 1 0 0 0 0
creg
3
z
1
dst
5
src2
5
src1
5
x
1
s
1
p
1
3-48
CLR
Description The field in src2, specified by csta and cstb, is cleared to zero. csta and cstb may be specified as constants or as the ten LSBs of the src1 registers, with cstb being bits 04 and csta bits 59. csta signifies the bit location of the LSB in the field and cstb signifies the bit location of the MSB in the field. In other words, csta and cstb represent the beginning and ending bits, respectively, of the field to be cleared. The LSB location of src2 is 0 and the MSB location of src2 is 31. In the example below, csta is 15 and cstb is 23. Only the ten LSBs are valid for the register version of the instruction. If any of the 22 MSBs are non-zero, the result is invalid.
cstb csta src2
x x x
31 30 29
x x x
28 27 26
x x 1 0 1 0 0 1 1 0 1 x
x x
x x
11 10
x x
9 8
x x
7 6
x x
5 4
x
3
x x x
2 1 0
25 24 23 22 21 20 19 18 17 16 15 14 13 12
dst
x x
x x
x x
0 0 0 0 0 0 0 0 0 x
x x
x x
9
x
8
x x
7 6
x x
5 4
x
3
x x
2 1
x
0
31 30 29
28 27 26
25 24 23 22 21 20 19 18 17 16 15 14 13 12
11 10
Execution
If the constant form is used: if (cond) else
src2 clear csta, cstb dst nop
If the register form is used: if (cond) else Pipeline

src2 clear src19..5, src14..0 dst nop

E1
src1, src2 dst

.S
Instruction Type Delay Slots Example 1
Single-cycle 0
CLR .S1 A1,4,19,A2 1 cycle after instruction A1 07A4 3F2Ah A2 07A0 000Ah
Before instruction A1 07A4 3F2Ah A2 XXXX XXXXh
3-49
CLR
Example 2
CLR .S2
B1,B3,B2 1 cycle after instruction B1 03B6 E7D5h B2 03B0 0001h B3 0000 0052h
Before instruction B1 03B6 E7D5h B2 XXXX XXXXh B3 0000 0052h
3-50
CMPEQ
CMPEQ
Syntax
Integer Compare for Equality

CMPEQ (.unit) src1, src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... sint xsint uint scst5 xsint uint xsint slong uint scst5 slong uint Unit .L1, .L2 Opfield 1010011
.L1, .L2
1010010
.L1, .L2
1010001
.L1, .L2
1010000
Opcode
31 29 28 27 23 22 18 17 13 12 11 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
7
Description
This instruction compares src1 to src2. If src1 equals src2, then 1 is written to dst. Otherwise, 0 is written to dst. if (cond) { if (src1 == src2) 1 dst else 0 dst } nop
Execution
else Pipeline
E1
src1, src2 dst

.L
3-51
CMPEQ
Instruction Type Delay Slots Example 1 Single-cycle 0
CMPEQ .L1X A1,B1,A2 Before instruction A1 0000 4B8h A2 XXXX XXXXh B1 0000 4B7h 1207 1208 1 cycle after instruction A1 0000 4B8h A2 0000 0000h B1 0000 4B7h false
Example 2
CMPEQ .L1
Ch,A1,A2 1 cycle after instruction A1 0000 000Ch A2 0000 0001h true
Before instruction A1 0000 000Ch A2 XXXX XXXXh 12
Example 3
CMPEQ .L2X A1,B3:B2,B1 Before instruction A1 F23A 3789h B1 XXXX XXXXh B3:B2 0000 0FFh F23A 3789h 1 cycle after instruction A1 F23A 3789h B1 0000 0001h true
B3:B2 0000 00FFh F23A 3789h
3-52
CMPGT(U)
CMPGT(U)
Syntax
Signed or Unsigned Integer Compare for Greater Than

CMPGT (.unit) src1, src2, dst or CMPGTU (.unit) src1, src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... sint xsint uint scst5 xsint uint xsint slong uint scst5 slong uint uint xuint uint ucst4 xuint uint xuint ulong uint ucst4 ulong uint
Unit .L1, .L2
Opfield 1000111
Mnemonic CMPGT
src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst
.L1, .L2
1000110
CMPGT
.L1, .L2
1000101
CMPGT
.L1, .L2
1000100
CMPGT
.L1, .L2
1001111
CMPGTU
.L1, .L2
1001110
CMPGTU
.L1, .L2
1001101
CMPGTU
.L1, .L2
1001100
CMPGTU
Opcode
31 29 28 27 23 22 18 17 13 12 11 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
7
3-53
CMPGT(U)
Description This instruction does a signed or unsigned comparison of src1 to src2. If src1 is greater than src2, then 1 is written to dst. Otherwise, 0 is written to dst. Only the four LSBs are valid in the 5-bit cst field when the ucst4 operand is used. If the MSB of the cst field is non-zero, the result is invalid. Note: The CMPGT instruction allows using a 5-bit constant as src1. If src2 is a 5-bit constant, as in
CMPGT .L1 A4, 5, A0
Then to implement this operation, the assembler converts this instruction to

CMPLT .L1 5, A4, A0
These two instructions are equivalent, with the second instruction using the conventional operand types for src1 and src2. Similarly, the CMPGT instruction allows a cross path operand to be used as src2. If src1 is a cross path operand as in
CMPGT .L1x B4, A5, A0
Then to implement this operation the assembler converts this instruction to

CMPLT .L1x A5, B4, A0
In both of these operations the listing file (.lst) will have the first implementation, and the second implementation will appear in the debugger. Execution if (cond) { if (src1 > src2) 1 dst else 0 dst
}
else Pipeline
nop
E1
src1, src2 dst

.L
Single-cycle 0
3-54
CMPGT(U)
Example 1
CMPGT .L1X A1,B1,A2 Before instruction A1 0000 01B6h A2 XXXX XXXXh B1 0000 08BDh 2237 438 1 cycle after instruction A1 0000 01B6h A2 0000 0000h B1 0000 08BDh false
Example 2
CMPGT .L1X A1,B1,A2 Before instruction A1 FFFF FE91h A2 XXXX XXXXh B1 FFFF FDC4h 572 367 1 cycle after instruction A1 FFFF FE91h A2 0000 0001h B1 FFFF FDC4h true
Example 3
CMPGT .L1
8,A1,A2 1 cycle after instruction A1 0000 0023h A2 0000 0000h false
Before instruction A1 0000 0023h A2 XXXX XXXXh 35
Example 4
CMPGT .L1X A1,B1,A2 Before instruction A1 0000 00EBh A2 XXXX XXXXh B1 0000 00EBh 235 235 1 cycle after instruction A1 0000 00EBh A2 0000 0000h B1 0000 00EBh false
Example 5
CMPGTU .L1 A1,A2,A3 Before instruction A1 0000 0128h A2 FFFF FFDEh A3 XXXX XXXXh 296 4294967262 1 cycle after instruction A1 0000 0128h A2 FFFF FFDEh A3 0000 0000h false
3-55
CMPGT(U)
Example 6
CMPGTU .L1 0Ah,A1,A2 Before instruction A1 0000 0005h A2 XXXX XXXXh 5 1 cycle after instruction A1 0000 0005h A2 0000 0001h true
Example 7
CMPGTU .L1 0Eh,A3:A2,A4 1 cycle after instruction 10 A3:A2 0000 0000h A4 0000 0001h 0000 000Ah true
Before instruction A3:A2 0000 0000h A4 XXXX XXXXh

0000 000Ah
3-56
CMPLT(U)
CMPLT(U)
Syntax
Signed or Unsigned Integer Compare for Less Than

CMPLT (.unit) src1, src2, dst or CMPLTU (.unit) src1, src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... sint xsint uint scst5 xsint uint xsint slong uint scst5 slong uint uint xuint uint ucst4 xuint uint xuint ulong uint ucst4 ulong uint Unit .L1, .L2 Opfield 1010111 Mnemonic CMPLT
.L1, .L2
1010110
CMPLT
.L1, .L2
1010101
CMPLT
.L1, .L2
1010100
CMPLT
.L1, .L2
1011111
CMPLTU
.L1, .L2
1011110
CMPLTU
.L1, .L2
1011101
CMPLTU
.L1, .L2
1011100
CMPLTU
Opcode
31 29 28 27 23 22 18 17 13 12 11 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
7
3-57
CMPLT(U)
Description This instruction does a signed or unsigned comparison of src1 to src2. If src1 is less than src2, then 1 is written to dst. Otherwise, 0 is written to dst. Note: The CMPLT instruction allows using a 5-bit constant as src1. If src2 is a 5-bit constant, as in
CMPLT .L1 A4, 5, A0

CMPGT .L1 5, A4, A0
These two instructions are equivalent, with the second instruction using the conventional operand types for src1 and src2. Similarly, the CMPLT instruction allows a cross path operand to be used as src2. If src1 is a cross path operand as in
CMPLT .L1x B4, A5, A0

CMPGT .L1x A5, B4, A0
In both of these operations the listing file (.lst) will have the first implementation, and the second implementation will appear in the debugger. Execution if (cond) { if (src1 < src2) 1 dst else 0 dst } nop
else Pipeline
E1
src1, src2 dst

.L
Single-cycle 0
3-58
CMPLT(U)
Example 1
CMPLT .L1
A1,A2,A3 1 cycle after instruction A1 0000 07E2h A2 0000 0F6Bh A3 0000 0001h true
Before instruction A1 0000 07E2h A2 0000 0F6Bh A3 XXXX XXXXh 2018 3947
Example 2
CMPLT .L1
A1,A2,A3 1 cycle after instruction A1 FFFF FED6h A2 0000 000Ch A3 0000 0001h true
Before instruction A1 FFFF FED6h A2 0000 000Ch A3 XXXX XXXXh 298 12
Example 3
CMPLT .L1
9,A1,A2 1 cycle after instruction A1 0000 0005h A2 0000 0000h false
Before instruction A1 0000 0005h A2 XXXX XXXXh 5
Example 4
CMPLTU .L1 A1,A2,A3 Before instruction A1 0000 289Ah A2 FFFF F35Eh A3 XXXX XXXXh
Unsigned 32-bit integer
1 cycle after instruction A1 0000 289Ah A2 FFFF F35Eh A3 0000 0001h true
10394 4294964062
3-59
CMPLT(U)
Example 5
CMPLTU .L1 14,A1,A2 Before instruction A1 0000 000Fh A2 XXXX XXXXh 15 1 cycle after instruction A1 0000 000Fh A2 0000 0001h true
Example 6
CMPLTU .L1 A1,A5:A4,A2 1 cycle after instruction 3900000 A1 003B 8260h A2 0000 0000h 3801090 A5:A4 0000 0000h false 003A 0002h
Before instruction A1 003B 8260h A2 XXXX XXXXh A5:A4 0000 0000h

003A 0002h
3-60
EXT
EXT
Syntax
Extract and Sign-Extend a Bit Field

EXT (.unit) src2, csta, cstb, dst or EXT (.unit) src2, src1, dst .unit = .S1 or .S2
Opcode map field used... For operand type... sint ucst5 ucst5 sint xsint uint sint Unit .S1, .S2
.S1, .S2
Opcode
Constant form:
31 29 28 27 23 22 18 17 13 12 8 7 6 0 1 2 5 0 0 1 0 0
creg
3
z
1
dst
5
src2
5
csta
5
cstb
5
s
1
p
1
Register form:
31 29 28 27 23 22 18 17 13 12 11 6 0 1 6 1 1 1 5 1 0 0 0 0
creg
3
z
1
dst
5
src2
5
src1
5
s
1
p
1
Description
The field in src2, specified by csta and cstb, is extracted and sign-extended to 32 bits. The extract is performed by a shift left followed by a signed shift right. csta and cstb are the shift left amount and shift right amount, respectively. This can be thought of in terms of the LSB and MSB of the field to be extracted. Then csta = 31 MSB of the field and cstb = csta + LSB of the field. The shift left and shift right amounts may also be specified as the ten LSBs of the src1 register with cstb being bits 04 and csta bits 59. In the example below, csta is 12 and cstb is 11 + 12 = 23. Only the ten LSBs are valid for the register version of the instruction. If any of the 22 MSBs are non-zero, the result is invalid.
3-61
EXT
csta
cstb csta
src2
1)
x x x x x x x x x x x x 1 0 1 0 0 1 1 0 1 x x x x x x x x x x x
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Shifts left by 12 to produce:
2)
1 0 1 0 0 1 1 0 1 x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Then shifts right by 23 to produce:
dst
3)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 0 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Execution
src2 ext csta, cstb dst nop

src2 ext src19..5, src14..0 dst nop

E1
src1, src2 dst

.S
Single-cycle 0
3-62
EXT
Example 1
EXT .S1
A1,10,19,A2 1 cycle after instruction A1 07A4 3F2Ah A2 FFFF F21Fh
Example 2
EXT .S1
A1,A2,A3 1 cycle after instruction A1 03B6 E7D5h A2 0000 0073h A3 0000 03B6h
Before instruction A1 03B6 E7D5h A2 0000 0073h A3 XXXX XXXXh
3-63
EXTU
EXTU
Syntax
Extract and Zero-Extend a Bit Field

EXTU (.unit) src2, csta, cstb, dst or EXTU (.unit) src2, src1, dst .unit = .S1 or .S2
Opcode map field used... For operand type... uint ucst5 ucst5 uint xuint uint uint Unit .S1, .S2
.S1, .S2
Opcode
Constant width and offset form:

31 29 28 27 23 22 18 17 13 12 8 7 00 2 6 5 0 0 1 0 0
creg
3
z
1
dst
5
src2
5
csta
5
cstb
5
s
1
p
1
Register width and offset form:

31 29 28 27 23 22 18 17 13 12 11 6 101011 6 5 1 0 0 0 0
creg
3
z
1
dst
5
src2
5
src1
5
s
1
p
1
Description
The field in src2, specified by csta and cstb, is extracted and zero extended to 32 bits. The extract is performed by a shift left followed by an unsigned shift right. csta and cstb are the amounts to shift left and shift right, respectively. This can be thought of in terms of the LSB and MSB of the field to be extracted. Then csta = 31 MSB of the field and cstb = csta + LSB of the field. The shift left and shift right amounts may also be specified as the ten LSBs of the src1 register with cstb being bits 04 and csta bits 59. In the example below, csta is 12 and cstb is 11 + 12 = 23. Only the ten LSBs are valid for the register version of the instruction. If any of the 22 MSBs are non-zero, the result is invalid.
3-64
EXTU
csta src2
1)
cstb cst a
x x x x x x x x x x x x 1 0 1 0 0 1 1 0 1 x x x x x x x x x x x
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Shifts left by 12 to produce:
2)
1 0 1 0 0 1 1 0 1 x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Then shifts right by 23 to produce:
dst
3)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Execution
If the constant form is used: if else (cond) src2 extu csta, cstb dst nop
If the register width and offset form is used: if else Pipeline (cond) src2 extu src19..5, src14..0 dst nop
E1
src1, src2 dst

.S
Single-cycle 0
3-65
EXTU
Example 1
EXTU .S1
A1,10,19,A2 1 cycle after instruction A1 07A4 3F2Ah A2 0000 121Fh
Example 2
EXTU .S1
A1,A2,A3 1 cycle after instruction A1 03B6 E7D5h A2 0000 0156h A3 0000 036Eh
Before instruction A1 03B6 E7D5h A2 0000 0156h A3 xxxx xxxxh
3-66
IDLE
IDLE
Syntax Opcode
31
Multicycle NOP With No Termination Until Interrupt

IDLE
18 17 16 15 14 13 12 11 10 9 Reserved 14 0 1 1 1 1 0 0 0 0
8 0
7 0
2 0
1 0
0 0
0 0
s p
1
Description
This instruction performs an infinite multicycle NOP that terminates upon servicing an interrupt, or a branch occurs due to an IDLE instruction being in the delay slots of a branch. NOP 0
3-67
LDB(U)/LDH(U)/LDW
LDB(U)/LDH(U)/LDW
Load From Memory With a 5-Bit Unsigned Constant Offset or Register Offset
Register Offset LDB (.unit) *+baseR[offsetR], dst or LDH (.unit) *+baseR[offsetR], dst or LDW (.unit) *+baseR[offsetR], dst or LDBU (.unit) *+baseR[offsetR], dst or LDHU (.unit) *+baseR[offsetR], dst Unsigned Constant Offset LDB (.unit) *+baseR[ucst5], dst or LDH (.unit) *+baseR[ucst5], dst or LDW (.unit) *+baseR[ucst5], dst or LDBU (.unit) *+baseR[ucst5], dst or LDHU (.unit) *+baseR[ucst5], dst
Syntax
.unit = .D1 or .D2 Opcode

31 29 28 27 23 22 18 17 13 12 9 8 r 7 y 6 4 3 0 2 1 1 0
creg
3
dst
5
baseR
5
offsetR/ucst5
5
mode
4
ld/st
3
Description
Each of these instructions loads from memory to a general-purpose register (dst). Table 313 summarizes the data types supported by loads. Table 314 describes the addressing generator options. The memory address is formed from a base address register (baseR) and an optional offset that is either a register (offsetR) or a 5-bit unsigned constant (ucst5). If an offset is not given, the assembler assigns an offset of zero.
offsetR and baseR must be in the same register file and on the same side as the .D unit used. The y bit in the opcode determines the .D unit and register file used: y = 0 selects the .D1 unit and baseR and offsetR from the A register file, and y = 1 selects the .D2 unit and baseR and offsetR from the B register file. offsetR/ucst5 is scaled by a left-shift of 0, 1, or 2 for LDB(U), LDH(U), and LDW, respectively. After scaling, offsetR/ucst5 is added to or subtracted from baseR. For the preincrement, predecrement, positive offset, and negative offset address generator options, the result of the calculation is the address to be accessed in memory. For postincrement or postdecrement addressing, the value of baseR before the addition or subtraction is the address to be accessed in memory.
The addressing arithmetic that performs the additions and subtractions defaults to linear mode. However, for A4A7 and for B4B7, the mode can be changed to circular mode by writing the appropriate value to the AMR (see section 2.6.2 on page 2-14).
3-68
LDB(U)/LDH(U)/LDW
For LDH(U) and LDB(U) the values are loaded into the 16 and 8 LSBs of dst, respectively. For LDH and LDB, the upper 16- and 24-bits, respectively, of dst values are sign-extended. For LDHU and LDBU loads, the upper 16- and 24-bits, respectively, of dst are zero-filled. For LDW, the entire 32 bits fills dst. dst can be in either register file, regardless of the .D unit or baseR or offsetR used. The s bit determines which file dst will be loaded into: s = 0 indicates dst will be in the A register file and s = 1 indicates dst will be loaded in the B register file. The r bit should be set to zero.
Table 313. Data Types Supported by Loads

ld/st Field
Left Shift of Offset 0 bits 0 bits 1 bit 1 bit 2 bits
Mnemonic LDB LDBU LDH LDHU LDW
Load Data Type
SIze 8 8 16 16 32
0 1 0 Load byte 0 0 1 Load byte unsigned 1 0 0 Load halfword 0 0 0 Load halfword unsigned 1 1 0 Load word
Table 314. Address Generator Options

Mode Field 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 Syntax *+R[offsetR] *R[offsetR] *+ +R[offsetR] * R[offsetR] *R+ +[offsetR] *R [offsetR] *+R[ucst5] *R[ucst5] *+ +R[ucst5] * R[ucst5] *R+ +[ucst5] *R [ucst5] Modification Performed Positive offset Negative offset Preincrement Predecrement Postincrement Postdecrement Positive offset Negative offset Preincrement Predecrement Postincrement Postdecrement
3-69
LDB(U)/LDH(U)/LDW
Increments and decrements default to 1 and offsets default to 0 when no bracketed register or constant is specified. Loads that do no modification to the baseR can use the syntax *R. Square brackets, [ ], indicate that the ucst5 offset is left-shifted by 2, 1, or 0 for word, halfword, and byte loads, respectively. Parentheses, ( ), can be used to set a nonscaled, constant offset. For example, LDW (.unit) *+baseR (12) dst represents an offset of 12 bytes, whereas LDW (.unit) *+baseR [12] dst represents an offset of 12 words, or 48 bytes. You must type either brackets or parentheses around the specified offset if you use the optional offset parameter. Word and halfword addresses must be aligned on word (two LSBs are 0) and halfword (LSB is 0) boundaries, respectively. Execution if (cond) else
mem dst nop
Pipeline
E1
E2
E3
E4
E5
baseR offsetR baseR

.D
dst
Load 4 for loaded value 0 for address modification from pre/post increment/decrement For more information on delay slots for a load, see Chapter 6, TMS320C62x/C64x Pipeline, and Chapter 7, TMS320C67x Pipeline.
LDW .D1 *A10,B1 1 cycle after LDW
B1 0000 0000h A10 0000 0100h
Example 1
Before LDW
B1 0000 0000h A10 0000 0100h
5 cycles after LDW

B1 21F3 1996h A10 0000 0100h
mem
100h
21F3 1996h
mem 100h
21F3 1996h
mem
100h
21F3 1996h
3-70
LDB(U)/LDH(U)/LDW
Example 2
Before LDB
A5 A7 AMR mem 0000 0204h
LDB .D1
*A5[4],A7 1 cycle after LDB

A5 0000 0204h A7 1951 1970h AMR 0000 0000h
5 cycles after LDB

A5 0000 0204h A7 FFFF FFE1h AMR 0000 0000h E1h mem 200h
1951 1970h
0000 0000h 200h E1h
mem 200h
E1h
Example 3
Before LDH
A1 A4 A8 AMR 0000 0002h 0000 0020h 1103 51FFh 0000 0000h
LDH .D1
*++A4[A1],A8 1 cycle after LDH

A1 0000 0002h A4 0000 0024h A8 1103 51FFh AMR 0000 0000h
5 cycles after LDH

A1 0000 0002h A4 0000 0024h A8 FFFF A21Fh AMR 0000 0000h
mem
24h
A21Fh
mem 24h
A21Fh
mem
24h
A21Fh
Example 4
Before LDW
A4 A6 AMR 0000 0100h 1234 4321h 0000 0000h
LDW .D1
*A4++[1],A6 1 cycle after LDW

A4 A6 AMR 0000 0104h 1234 4321h 0000 0000h
5 cycles after LDW

A4 A6 AMR 0000 0104h 0798 F25Ah 0000 0000h
mem
100h
0798 F25Ah
mem 100h
0798 F25Ah
mem 100h
0798 F25Ah
mem
104h
1970 19F3h
mem 104h
1970 19F3h
mem 104h
1970 19F3h
3-71
LDB(U)/LDH(U)/LDW
Example 5
Before LDW
A4 A6 AMR 0000 0100h 1234 5678h 0000 0000h
LDW .D1
*++A4[1],A6 1 cycle after LDW

A4 A6 0000 0104h 1234 5678h 0000 0000h
5 cycles after LDW

A4 A6 AMR 0000 0104h 0217 6991h 0000 0000h
mem
104h
0217 6991h
mem 104h
0217 6991h
mem 104h
0217 6991h
3-72
LDB(U)/LDH(U)/LDW
LDB(U)/LDH(U)/LDW
Syntax
Load From Memory With a 15-Bit Constant Offset
LDB (.unit) *+B14/B15[ucst15], dst or LDH (.unit) *+B14/B15[ucst15], dst or LDW (.unit) *+B14/B15[ucst15], dst or LDBU (.unit) *+B14/B15[ucst15], dst or LDHU (.unit) *+B14/B15[ucst15], dst .unit = .D2
Opcode
31 29 28 27 23 22 8 7 y 6 4 3 1 2 1 1 0
creg
3
dst
5
ucst15
15
ld/st
3
Description
Each of these instructions performs a load from memory to a general-purpose register (dst). Table 315 summarizes the data types supported by loads. The memory address is formed from a base address register (baseR) B14 (y = 0) or B15 (y = 1) and an offset, which is a 15-bit unsigned constant (ucst15). The assembler selects this format only when the constant is larger than five bits in magnitude. This instruction operates only on the .D2 unit. The offset, ucst15, is scaled by a left shift of 0, 1, or 2 for LDB(U), LDH(U), and LDW, respectively. After scaling, ucst15 is added to baseR. Subtraction is not supported. The result of the calculation is the address sent to memory. The addressing arithmetic is always performed in linear mode. For LDH(U) and LDB(U), the values are loaded into the 16 and 8 LSBs of dst, respectively. For LDH and LDB, the upper 16 and 24 bits of dst values are signextended, respectively. For LDHU and LDBU loads, the upper 16 and 24 bits of dst are zero-filled, respectively. For LDW, the entire 32 bits fills dst. dst can be in either register file. The s bit determines which file dst will be loaded into: s = 0 indicates dst is loaded in the A register file, and s = 1 indicates dst is loaded into the B register file. Square brackets, [ ], indicate that the ucst15 offset is left-shifted by 2, 1, or 0 for word, halfword, and byte loads, respectively. Parentheses, ( ), can be used to set a nonscaled, constant offset. For example, LDW (.unit) *+B14/B15(60) dst represents an offset of 60 bytes, whereas LDW (.unit) *+B14/B15[60] dst represents
3-73
LDB(U)/LDH(U)/LDW
an offset of 60 words, or 240 bytes. You must type either brackets or parentheses around the specified offset if you use the optional offset parameter. Word and halfword addresses must be aligned on word (two LSBs are 0) and halfword (LSB is 0) boundaries, respectively.
Table 315. Data Types Supported by Loads

ld/st Field
0 1 0 0 0 1 1 0 0 0 0 0 1 1 0 Left Shift of Offset 0 bits 0 bits 1 bit 1 bit 2 bits
Mnemonic LDB LDBU LDH LDHU LDW
Load Data Type Load byte Load byte unsigned Load halfword Load halfword unsigned Load word
SIze 8 8 16 16 32
Execution
if (cond) else Note:
mem dst nop
This instruction executes only on the B side (.D2). Pipeline

Pipeline Stage Read Written Unit in use .D2
E1
E2
E3
E4
E5
B14 / B15 dst
Load 4
3-74
LDB(U)/LDH(U)/LDW
Example
LDB .D2 Before LDB

B1 XXXX XXXXh B14 0000 0100h
*+B14[36],B1 1 cycle after LDB

B1 XXXX XXXXh B14 0000 0100h
mem
124127h 4E7A FF12h mem 124h 12h
mem
124127h 4E7A FF12h mem 124h 12h
5 cycles after LDB

B1 0000 0012h B14 0000 0100h
mem
124127h 4E7A FF12h mem 124h 12h
3-75
LMBD
LMBD
Syntax
Leftmost Bit Detection

LMBD (.unit) src1, src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... uint xuint uint cst5 xuint uint Unit .L1, .L2 Opfield 1101011
.L1, .L2
1101010
Opcode
31 29 28 27 23 22 18 17 13 12 11 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
7
Description
The LSB of the src1 operand determines whether to search for a leftmost 1 or 0 in src2. The number of bits to the left of the first 1 or 0 when searching for a 1 or 0, respectively, is placed in dst. The following diagram illustrates the operation of LMBD for several cases. When searching for 0 in src2, LMBD returns 0:
0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
When searching for 1 in src2, LMBD returns 4:

0 0 0 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
When searching for 0 in src2, LMBD returns 32:

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Execution
if (cond)
else
3-76
{ if (src10 == 0) lmb0(src2) dst if (src10 == 1) lmb1(src2) dst } nop
LMBD
Pipeline
E1
src1, src2 dst

.L
Single-cycle 0
LMBD .L1 A1,A2,A3 1 cycle after instruction A1 0000 0001h A2 009E 3A81h A3 0000 0008h
Before instruction A1 0000 0001h A2 009E 3A81h A3 XXXX XXXXh
3-77
MPY(U/US/SU)
MPY(U/US/SU)
Syntax
Signed or Unsigned Integer Multiply 16lsb x 16lsb

MPY (.unit) src1, src2, dst or MPYU (.unit) src1, src2, dst or MPYUS (.unit) src1, src2, dst or MPYSU (.unit) src1, src2, dst .unit = .M1 or .M2
Opcode map field used... For operand type... Unit .M1, .M2 Opfield Mnemonic 11001 MPY
src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst
slsb16 xslsb16 sint ulsb16 xulsb16 uint ulsb16 xslsb16 sint slsb16 xulsb16 sint scst5 xslsb16 sint scst5 xulsb16 sint
.M1, .M2
11111
MPYU
.M1, .M2
11101
MPYUS
.M1, .M2
11011
MPYSU
.M1, .M2
11000
MPY
.M1, .M2
11110
MPYSU
Opcode
31 29 28 27 23 22 18 17 13 12 11 7 6 0 5 0 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
5
Description
The src1 operand is multiplied by the src2 operand. The result is placed in dst. The source operands are signed by default. The S is needed in the mnemonic to specify a signed operand when both signed and unsigned operands are used. if (cond) else lsb16(src1) lsb16(src2) dst nop
Execution
3-78
MPY(U/US/SU)
Pipeline
E1
E2
src1, src2 dst

.M
Multiply (16 16) 1

MPY .M1 A1,A2,A3 2 cycles after instruction A1 0000 0123h A2 01E0 FA81h A3 FFF9 C0A3 409437
Before instruction A1 0000 0123h A2 01E0 FA81h A3 XXXX XXXXh 291 1407
Example 2
MPYU .M1
A1,A2,A3 2 cycles after instruction A1 0000 0123h A2 0F12 FA81h A3 011C C0A3 18661539
Before instruction A1 0000 0123h A2 0F12 FA81h A3 XXXX XXXXh 291 64129
Example 3
MPYUS .M1
A1,A2,A3 2 cycles after instruction A1 1234 FFA1h A2 1234 FFA1h A3 FFA1 2341h 6216895
Before instruction A1 1234 FFA1h A2 1234 FFA1h A3 XXXX XXXXh

Signed 16-LSB integer Unsigned 16-LSB integer Unsigned 32-bit integer
65441 95
3-79
MPY(U/US/SU)
Example 4
MPY .M1
13,A1,A2 2 cycles after instruction A1 3497 FFF3h A2 FFFF FF57h 163
Before instruction A1 3497 FFF3h A2 XXXX XXXXh 13
Example 5
MPYSU .M1
13,A1,A2 2 cycles after instruction A1 3497 FFF3h A2 000C FF57h 851779
Before instruction A1 3497 FFF3h A2 XXXX XXXXh

Signed 16-LSB integer Unsigned 16-LSB integer
65523
3-80
MPYH(U/US/SU)
MPYH(U/US/SU)
Syntax
Signed or Unsigned Integer Multiply 16msb x 16msb

MPYH (.unit) src1, src2, dst or MPYHU (.unit) src1, src2, dst or MPYHUS (.unit) src1, src2, dst or MPYHSU (.unit) src1, src2, dst .unit = .M1 or .M2
Opcode map field used... For operand type... Unit .M1, .M2 Opfield Mnemonic 00001 MPYH
smsb16 xsmsb16 sint umsb16 xumsb16 uint umsb16 xsmsb16 sint smsb16 xumsb16 sint
.M1, .M2
00111
MPYHU
.M1, .M2
00101
MPYHUS
.M1, .M2
00011
MPYHSU
Opcode
31 29 28 27 23 22 18 17 13 12 11 7 6 0 5 0 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
5
Description
The src1 operand is multiplied by the src2 operand. The result is placed in dst. The source operands are signed by default. The S is needed in the mnemonic to specify a signed operand when both signed and unsigned operands are used. if (cond) else msb16(src1) msb16(src2) dst nop
Execution
3-81
MPYH(U/US/SU)
Pipeline
E1
E2
src1, src2 dst

.M
Multiply (16 16) 1

MPYH .M1 A1,A2,A3 2 cycles after instruction A1 0023 0000h A2 FFA7 1234h A3 FFFF F3D5h 3115
Before instruction A1 0023 0000h A2 FFA7 1234h A3 XXXX XXXXh 35 89
Example 2
MPYHU .M1
A1,A2,A3 2 cycles after instruction A1 0023 0000h A2 FFA7 1234h A3 0022 F3D5h 2290645
Before instruction A1 0023 0000h A2 FFA7 1234h A3 XXXX XXXXh 35 65447
Example 3
MPYHSU .M1 A1,A2,A3 Before instruction A1 0023 0000h A2 FFA7 FFFFh A3 XXXX XXXXh
Signed 16-MSB integer Unsigned 16-MSB integer Unsigned 32-bit integer
2 cycles after instruction A1 0023 0000h A2 FFA7 FFFFh A3 0022 F3D5h 2290645
35 65447
3-82
MPYHL(U)/MPYHULS/MPYHSLU
Signed or Unsigned Integer Multiply 16msb x 16lsb
Syntax
MPYHL (.unit) src1, src2, dst or MPYHLU (.unit) src1, src2, dst or MPYHULS (.unit) src1, src2, dst or MPYHSLU (.unit) src1, src2, dst .unit = .M1 or .M2
Opcode map field used... For operand type... Unit .M1, .M2 Opfield 01001 Mnemonic MPYHL
smsb16 xslsb16 sint umsb16 xulsb16 uint umsb16 xslsb16 sint smsb16 xulsb16 sint
.M1, .M2
01111
MPYHLU
.M1, .M2
01101
MPYHULS
.M1, .M2
01011
MPYHSLU
Opcode
31 29 28 27 23 22 18 17 13 12 11 7 6 0 5 0 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
5
Description
The src1 operand is multiplied by the src2 operand. The result is placed in dst. The source operands are signed by default. The S is needed in the mnemonic to specify a signed operand when both signed and unsigned operands are used. if (cond) else msb16(src1) lsb16(src2) dst nop
3-83
Execution
Pipeline
E1
E2
src1, src2 dst

.M
Multiply (16 16) 1

MPYHL .M1 A1,A2,A3 2 cycles after instruction A1 008A 003Eh A2 21FF 00A7h A3 0000 5A06h 23046
Before instruction A1 008A 003Eh A2 21FF 00A7h A3 XXXX XXXXh

Signed 16-MSB integer Signed 16-LSB integer
138 167
3-84
Signed or Unsigned Integer Multiply 16lsb x 16msb
Syntax
MPYLH (.unit) src1, src2, dst or MPYLHU (.unit) src1, src2, dst or MPYLUHS (.unit) src1, src2, dst or MPYLSHU (.unit) src1, src2, dst .unit = .M1 or .M2
Opcode map field used... For operand type... slsb16 xsmsb16 sint ulsb16 xumsb16 uint ulsb16 xsmsb16 sint slsb16 xumsb16 sint Unit .M1, .M2 .M1, .M2 .M1, .M2 .M1, .M2 Opfield 10001 Mnemonic MPYLH
10111
MPYLHU
10101
MPYLUHS
10011
MPYLSHU
Opcode
31 29 28 27 23 22 18 17 13 12 11 7 6 0 5 0 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
5
Description
The src1 operand is multiplied by the src2 operand. The result is placed in dst. The source operands are signed by default. The S is needed in the mnemonic to specify a signed operand when both signed and unsigned operands are used. if (cond) else lsb16(src1) msb16(src2) dst nop
3-85
Execution
Pipeline
E1
E2
src1, src2 dst

.M
Multiply (16 16) 1

MPYLH .M1 A1,A2,A3 2 cycles after instruction A1 0900 000Eh A2 0029 00A7h A3 0000 023Eh 574
Before instruction A1 0900 000Eh A2 0029 00A7h A3 XXXX XXXXh

Signed 16-LSB integer Signed 16-MSB integer
14 41
3-86
MV
MV
Syntax
Move From Register to Register (Pseudo-Operation)

MV (.unit) src, dst .unit = .L1, .L2, .S1, .S2, .D1, .D2
Opcode map field used... For operand type... Unit .L1, .L2 .D1, .D2 .L1, .L2 .S1, .S2 Opfield 0000010 010010 0100001 000110
src dst src dst src dst src dst
xsint sint sint sint slong slong xsint sint
Opcode Description
See ADD and OR instructions. This is a pseudo operation that moves a value from one register to another. The assembler uses the operation ADD (.unit) 0, src, dst to perform this task. For the C64x, the operation performed is OR (.unit) FFFFh, src2, dst. In the case where dst is an slong, the C64x will use the ADD 0, src, dst operation like the C62x/C67x. if (cond) 0 + src dst else nop Single-cycle 0
Execution
3-87
MVC
MVC
Syntax
Move Between the Control File and the Register File

MVC (.unit) src2, dst .unit = .S2
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
op
6
Operands when moving from the control file to the register file:
Opcode map field used... For operand type... uint uint Unit .S2 Opfield 001111
src2 dst
Description
The src2 register is moved from the control register file to the register file. Valid values for src2 are any register listed in the control register file.
Operands when moving from the register file to the control file:
Opcode map field used... For operand type... xuint uint Unit .S2 Opfield 001110
src2 dst
Description
The src2 register is moved from the register file to the control register file. Valid values for src2 are any register listed in the control register file. Register addresses for accessing the control registers are in Table 316.
3-88
MVC
Table 316. Register Addresses for Accessing the Control Registers

Register Abbreviation AMR CSR IFR ISR ICR IER ISTP IRP NRP PCE1 FADCR{ FAUCR{ FMCR{
Note:
Name Addressing mode register Control status register Interrupt flag register Interrupt set register Interrupt clear register Interrupt enable register Interrupt service table pointer Interrupt return pointer Nonmaskable interrupt return pointer Program counter, E1 phase Floating-point adder configuration Floating-point auxiliary configuration Floating-point multiplier configuration
Register Address 00000 00001 00010 00010 00011 00100 00101 00110 00111 10000 10010 10011 10100
Read/ Write R, W R, W R W W R, W R, W R, W R, W R R, W R, W R, W
R = Readable by the MVC instruction W = Writeable by the MVC instruction TMSC320C67x only
Execution
if (cond) else Note:
src dst nop
The MVC instruction executes only on the B side (.S2). Pipeline

E1
src2 dst
.S2
3-89
MVC
Instruction Type Single-cycle Any write to the ISR or ICR (by the MVC instruction) effectively has one delay slot because the results cannot be read (by the MVC instruction) in the IFR until two cycles after the write to the ISR or ICR. Delay Slots Example 0
MVC .S2 B1,AMR 1 cycle after instruction B1 F009 0001h AMR 0009 0001h
Before instruction B1 F009 0001h AMR 0000 0000h
Note: The six MSBs of the AMR are reserved and therefore are not written to.
3-90
MVK
MVK
Syntax
Move a 16-Bit Signed Constant Into a Register and Sign Extend

MVK (.unit) cst, dst .unit = .S1 or .S2
Opcode map field used... For operand type... scst16 sint Unit .S1, .S2
cst dst
Opcode
31 29 28 27 23 22 7 6 0 1 0 1 0 0
creg
3
z
1
dst
5
cst
16
s
1
p
1
Description Execution Pipeline
The 16-bit constant is sign extended and placed in dst. if (cond) else
scst16 dst nop

E1
dst
.S
Single-cycle 0 Note: Use the MVK instruction to load 16-bit constants. The assembler will generate a warning for any constant over 16 bits. To load 32-bit constants, such as 0x 1234 5678, use the following pair of instructions:
MVKL MVKH 0x12345678 0x12345678
If you are loading the address of a label, use:

MVKL MVKH label label
3-91
MVK
Example 1
MVK .S1
293,A1 1 cycle after instruction A1 0000 0125h 293
Before instruction A1 XXXX XXXXh
Example 2
MVK .S2
125h,B1 1 cycle after instruction B1 0000 0125h 293
Before instruction B1 XXXX XXXXh
Example 3
MVK .S1
0FF12h,A1 1 cycle after instruction A1 FFFF FF12h 238
3-92
MVKH/MVKLH
MVKH/MVKLH
Syntax
Move 16-Bit Constant Into the Upper Bits of a Register

MVKH (.unit) cst, dst or MVKLH (.unit) cst, dst .unit = .S1 or .S2
Opcode map field used... For operand type... uscst16 sint Unit .S1, .S2
cst dst
Opcode
31 29 28 27 23 22 7 6 1 1 0 1 0 0
creg
3
z
1
dst
5
cst
16
s
1
p
1
Description
The 16-bit constant cst is loaded into the upper 16 bits of dst. The 16 LSBs of dst are unchanged. The assembler encodes the 16 MSBs of a 32-bit constant into the cst field of the opcode for the MVKH instruction. The assembler encodes the 16 LSBs of a constant into the cst field of the opcode for the MVKLH instruction. MVKLH if (cond)((cst15..0) << 16) or (dst15..0) dst else nop if (cond)((cst31..16) << 16) or (dst15..0) dst else nop
Execution
MVKH Pipeline
E1
dst
.S
Single-cycle 0
3-93
MVKH/MVKLH
Note: Use the MVK instruction to load 16-bit constants. The assembler will generate a warning for any constant over 16 bits. To load 32-bit constants, such as 0x1234 5678, use the following pair of instructions:
MVKL MVKH 0x12345678 0x12345678

Example 1
MVKH .S1
0A329123h,A1 1 cycle after instruction A1 0A32 7634h
Before instruction A1 0000 7634h
Example 2
MVKLH .S1
7A8h,A1 1 cycle after instruction A1 07A8 F25Ah
Before instruction A1 FFFF F25Ah
3-94
MVKL
MVKL
Syntax
Sign Extend 16-Bit Constant, Place In Register (Pseudo Operation)

MVKL (.unit) cst, dst .unit = .S1 or .S2
Opcode map field used... For operand type... scst16 sint Unit .S1, .S2
cst dst
Opcode
31 29 28 27 23 22 7 6 0 1 0 1 0 0
creg
3
z
1
dst
5
cst
16
s
1
p
1
Description
This is a pseudo-operation that sign extends the 16-bit constant and places it in dst. if (cond) else
Execution Pipeline
scst16 dst nop

E1
dst
.S
Single-cycle 0 Note: To load 32-bit constants, such as 0x1234 5678, use the following pair of instructions:
MVKL MVKH 0x12345678 0x12345678

3-95
MVKL
Example 1
MVKL .S1
293,A1 1 cycle after instruction A1 0000 0125h 293
Example 2
MVKL .S2
125h,B1 1 cycle after instruction B1 0000 0125h 293
Example 3
MVKL .S1
0FF12h,A1 1 cycle after instruction A1 FFFF FF12h 238
3-96
NEG
NEG
Syntax
Negate (Pseudo-Operation)
NEG (.unit) src, dst .unit = .L1, .L2, .S1, .S2
Opcode map field used... For operand type... Unit .S1, .S2 .L1, .L2 .L1, .L2 Opfield 010110 0000110 0100100
src dst src dst src dst
xsint sint xsint sint slong slong
Opcode Description
See SUB instruction. This is a pseudo operation used to negate src and place in dst. The assembler uses the operation SUB 0, src, dst to perform this task. if (cond) 0 s src dst else nop Single-cycle 0
Execution
3-97
NOP
NOP
Syntax
No Operation
NOP [count]
Opcode map field used... For operand type... ucst4 Unit none
src
Opcode
31 18 17 16 13 0 0 0 0 0 0 0 0 0 0 0 0 0 p 1
reserved
14
src
4
Description
src is encoded as count 1. For src + 1 cycles, no operation is performed. The maximum value for count is 9. NOP with no operand is treated like NOP 1 with src encoded as 0000.
A multicycle NOP will not finish if a branch is completed first. For example, if a branch is initiated on cycle n and a NOP 5 instruction is initiated on cycle n + 3, the branch is complete on cycle n + 6 and the NOP is executed only from cycle n + 3 to cycle n + 5. A single-cycle NOP in parallel with other instructions does not affect operation.
Execution Instruction Type Delay Slots Example 1
No operation for count cycles NOP 0

NOP MVK .S1
125h,A1 1 cycle after NOP (No operation executes) A1 1234 5678h
Before NOP A1 1234 5678h
1 cycle after MVK A1 0000 0125h
3-98
NOP
Example 2
MVK MVKLH NOP ADD
.S1 .S1 5 .L1
1,A1 0,A1 A1,A2,A1 1 cycle after ADD instruction (6 cycles after NOP 5) A1 0000 0004h A2 0000 0003h
Before NOP 5 A1 0000 0001h A2 0000 0003h
3-99
NORM
NORM
Syntax
Normalize Integer
NORM (.unit) src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... xsint uint slong uint Unit .L1, .L2 .L1, .L2 Opfield 1100011 1100000
src2 dst src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
op
7
Description
The number of redundant sign bits of src2 is placed in dst. Several examples are shown in the following diagram. In this case, NORM returns 0:
src2
0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
In this case, NORM returns 3:

src2
0 0 0 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

src2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

src2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Execution
if (cond) else
norm(src) dst nop
3-100
NORM
Instruction Type Pipeline Single-cycle
E1
src2 dst
.L
Delay Slots Example 1
0
NORM .L1 A1,A2 1 cycle after instruction A1 02A3 469Fh A2 0000 0005h 5
Before instruction A1 02A3 469Fh A2 XXXX XXXXh
Example 2
NORM .L1
A1,A2 1 cycle after instruction A1 FFFF F25Ah A2 0000 0013h 19
Before instruction A1 FFFF F25Ah A2 XXXX XXXXh
3-101
NOT
NOT
Syntax
Bitwise NOT (Pseudo-Operation)

NOT (.unit) src, dst (.unit) = .L1, .L2, .S1, or .S2
Opcode map field used... For operand type... Unit .L1, .L2 .S1, .S2 Opfield 1101110 001010
src dst src dst
xuint uint xuint uint
Opcode Description
See XOR instruction. This is a pseudo operation used to bitwise NOT the src operand and place the result in dst. The assembler uses the operation XOR (.unit) 1, src, dst to perform this task. if (cond) 1 xor src dst else nop Single-cycle 0
Execution
3-102
OR
OR
Syntax
Bitwise OR
OR (.unit) src1, src2, dst .unit = .L1, .L2, .S1, .S2
.L1, .L2
1111110
.S1, .S2
011011
.S1, .S2
011010
Opcode
.L unit form:
31 29 28 27 23 22 18 17 13 12 11 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
7
.S unit form:
31 29 28 27 23 22 18 17 13 12 11 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
6
Description
A bitwise OR instruction is performed beween src1 and src2. The result is placed in dst. The scst5 operands are sign extended to 32 bits.
3-103
OR
Execution Pipeline if (cond) else
src1 or src2 dst nop

E1
src1, src2 dst

.L or .S
Single-cycle 0
OR .L1X A1,B1,A2 1 cycle after instruction A1 08A3 A49Fh A2 08FF B7DFh B1 00FF 375Ah
Before instruction A1 08A3 A49Fh A2 XXXX XXXXh B1 00FF 375Ah
Example 2
OR .L2
12,B1,B2 1 cycle after instruction B1 0000 3A41h B2 FFFF FFF5h
Before instruction B1 0000 3A41h B2 XXXX XXXXh
3-104
SADD
SADD
Syntax
Integer Addition With Saturation to Result Size

SADD (.unit) src1, src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... sint xsint sint xsint slong slong scst5 xsint sint scst5 slong slong Unit .L1, .L2 Opfield 0010011
.L1, .L2
0110001
.L1, .L2
0010010
.L1, .L2
0110000
Opcode
31 29 28 27 23 22 18 17 13 12 11 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src 2
5
src 1/cst
5
op
7
Description
src1 is added to src2 and saturated if an overflow occurs according to the following rules:
1) If the dst is an int and src1 + src2 > 231 1, then the result is 231 1. 2) If the dst is an int and src1 + src2 < 231, then the result is 231. 3) If the dst is a long and src1 + src2 > 239 1, then the result is 239 1. 4) If the dst is a long and src1 + src2 < 239, then the result is 239. The result is placed in dst. If a saturate occurs, the SAT bit in the control status register (CSR) is set one cycle after dst is written.
Execution
if else
(cond) src1 +s src2 dst nop

3-105
SADD
Pipeline
E1
src1, src2 dst

.L

Before instruction
A1 A2 A3 CSR 5A2E 51A3h 012A 3FA2h XXXX XXXXh 0001 0100h
Single-cycle 0
SADD .L1 A1,A2,A3 1 cycle after instruction
A1 A2 A3 CSR 5A2E 51A3h 012A 3FA2h 5B58 9145h 0001 0100h 1532531013 A1 A2 A3 CSR
2 cycles after instruction

5A2E 51A3h 012A 3FA2h 5B58 9145h 0001 0100h Not saturated
1512984995 19546018
Example 2
Before instruction
A1 A2 A3 CSR 4367 71F2h 5A2E 51A3h XXXX XXXXh 0001 0100h
SADD .L1
A1,A2,A3 1 cycle after instruction

A1 A2 A3 4367 71F2h 5A2E 51A3h 7FFF FFFFh 0001 0100h 2147483647 A1 A2 A3 CSR

4367 71F2h 5A2E 51A3h 7FFF FFFFh 0001 0300h Saturated
1130852850 1512984995
CSR
3-106
SADD
Example 3
SADD .L1X
B2,A5:A4,A7:A6 1 cycle after instruction

1922644401 A5:A4 0000 0000h A7:A6 0000 0000h B2 112A 3FA2h CSR 0001 0100h CSR 7C83 39B1h 8DAD 7953h 2376956243
Before instruction
A5:A4 0000 0000h A7:A6 XXXX XXXXh B2 112A 3FA2h CSR 0001 0100h 7C83 39B1h XXXX XXXXh 287981474

A5:A4 0000 0000h A7:A6 0000 0000h B2 112A 3FA2h CSR 0001 0100h
Signed 40-bit (long) integer
7C83 39B1h 83C3 7953h
Not saturated
3-107
SAT
SAT
Syntax
Saturate a 40-Bit Integer to a 32-Bit Integer

SAT (.unit) src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... slong sint Unit .L1, .L2
src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 1000000 7 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
Description
A 40-bit src2 value is converted to a 32-bit value. If the value in src2 is greater than what can be represented in 32-bits, src2 is saturated. The result is placed in dst. If a saturate occurs, the SAT bit in the control status register (CSR) is set one cycle after dst is written. if (cond) { if (src2 > (231 1) ) (231 1) dst else if (src2 < 231) 231 dst else src231..0 dst } nop
Execution
else Pipeline
E1
src2 dst
.L
Single-cycle 0
3-108
SAT
Example 1
SAT .L2
B1:B0,B5 1 cycle after instruction

A1:A0 0000 001Fh 3413 539Ah A1:A0
Before instruction
A1:A0 0000 001Fh 3413 539Ah

0000 001Fh 3413 539Ah
A2 XXXX XXXXh CSR 0001 0100h
A2 7FFF FFFFh CSR 0001 0100h
A2 7FFF FFFFh CSR 0001 0300h Saturated
Example 2
SAT .L2

B1:B0 0000 0000h A190 7321h B1:B0
Before instruction
B1:B0 0000 0000h A190 7321h

0000 0000h A190 7321h
B5 XXXX XXXXh CSR 0001 0100h
B5 7FFF FFFFh CSR 0001 0100h
B5 7FFF FFFFh CSR 0001 0300h Saturated
Example 3
SAT .L2

B1:B0 0000 00FFh A190 7321h B1:B0
Before instruction
B1:B0 0000 00FFh A190 7321h

0000 00FFh A190 7321h
B5 XXXX XXXXh CSR 0001 0100h
B5 A190 7321h CSR 0001 0100h
B5 A190 7321h CSR 0001 0100h Not saturated
3-109
SET
SET
Syntax
Set a Bit Field

SET (.unit) src2, csta, cstb, dst or SET (.unit) src2, src1, dst .unit = .S1 or .S2
Opcode map field used... For operand type... uint ucst5 ucst5 uint xuint uint uint Unit .S1, .S2
.S1, .S2
Opcode
Constant form:
31 29 28 27 23 22 18 17 13 12 8 7 6 5 0 0 1 0 0
creg
3
z
1
dst
5
src2
5
csta
5
cstb
5
10 2
s
1
p
1
Register form:
31 29 28 27 23 22 18 17 13 12 11 6 111011 6 5 1 0 0 0 0
creg
3
z
1
dst
5
src2
5
src1
5
s
1
p
1
3-110
SET
Description The field in src2, specified by csta and cstb, is set to all 1s. The csta and cstb operands may be specified as constants or in the ten LSBs of the src1 register, with cstb being bits 04 and csta bits 59. csta signifies the bit location of the LSB of the field and cstb signifies the bit location of the MSB of the field. In other words, csta and cstb represent the beginning and ending bits, respectively, of the field to be set to all 1s. The LSB location of src2 is 0 and the MSB location of src2 is 31. In the example below, csta is 15 and cstb is 23. Only the ten LSBs are valid for the register version of the instruction. If any of the 22 MSBs are non-zero, the result is invalid.
cstb csta src2
x x x x x x x x 1 0 1 0 0 1 1 0 1 x x x x x x x x x x x x x x x
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
dst
x x x x x x x x 1 1 1 1 1 1 1 1 1 x x x x x x x x x x x x x x x
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Execution
src2 set csta, cstb dst nop

src2 set src19..5, src14..0 dst nop

E1
src1, src2 dst

.S
Single-cycle 0
3-111
SET
Example 1
SET .S1
A0,7,21,A1 1 cycle after instruction A0 4B13 4A1Eh A1 4B3F FF9Eh
Before instruction A0 4B13 4A1Eh A1 XXXX XXXXh
Example 2
SET .S2
B0,B1,B2 1 cycle after instruction B0 9ED3 1A31h B1 0000 C197h B2 9EFF FA31h
Before instruction B0 9ED3 1A31h B1 0000 C197h B2 XXXX XXXXh
3-112
SHL
SHL
Syntax
Arithmetic Shift Left

SHL (.unit) src2, src1, dst .unit = .S1 or .S2
Opcode map field used... For operand type... xsint uint sint slong uint slong xuint uint ulong xsint ucst5 sint slong ucst5 slong xuint ucst5 ulong Unit .S1, .S2 Opfield 110011
src2 src1 dst src2 src1 dst src2 src1 dst src2 src1 dst src2 src1 dst src2 src1 dst
.S1, .S2
110001
.S1, .S2
010011
.S1, .S2
110010
.S1, .S2
110000
.S1, .S2
010010
Opcode
31 29 28 27 23 22 18 17 13 12 11 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
6
Description
The src2 operand is shifted to the left by the src1 operand. The result is placed in dst. When a register is used, the six LSBs specify the shift amount and valid values are 040. When an immediate is used, valid shift amounts are 031. If 39 < src1 < 64, src2 is shifted to the left by 40. Only the six LSBs of src1 are used by the shifter, so any bits set above bit 5 do not affect execution.
3-113
SHL
src2 << src1 dst nop

E1
src1, src2 dst

.S
Single-cycle 0
SHL .S1 A0,4,A1 1 cycle after instruction A0 29E3 D31Ch A1 9E3D 31C0h
Before instruction A0 29E3 D31Ch A1 XXXX XXXXh
Example 2
SHL .S2
B0,B1,B2 1 cycle after instruction B0 4197 51A5h B1 0000 0009h B2 2EA3 4A00h
Before instruction B0 4197 51A5h B1 0000 0009h B2 XXXX XXXXh
Example 3
SHL .S2
B1:B0,B2,B3:B2 1 cycle after instruction B1:B0 0000 0009h B2 0000 0000h XXXX XXXXh B3:B2 0000 0094h 0000 0000h 4197 51A5h
Before instruction B1:B0 0000 0009h B2 0000 0022h B3:B2 XXXX XXXXh 4197 51A5h
3-114
SHR
SHR
Syntax
Arithmetic Shift Right

SHR (.unit) src2, src1, dst .unit = .S1 or .S2
Opcode map field used... For operand type... xsint uint sint slong uint slong xsint ucst5 sint slong ucst5 slong Unit .S1, .S2 Opfield 110111
.S1, .S2
110101
.S1, .S2
110110
.S1, .S2
110100
Opcode
31 29 28 27 23 22 18 17 13 12 11 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
6
Description
The src2 operand is shifted to the right by the src1 operand. The sign-extended result is placed in dst. When a register is used, the six LSBs specify the shift amount and valid values are 040. When an immediate is used, valid shift amounts are 031. If 39 < src1 < 64, src2 is shifted to the right by 40. Only the six LSBs of src1 are used by the shifter, so any bits set above bit 5 do not affect execution.
Execution Pipeline
if (cond) else
src2 >>s src1 dst nop

E1
src1, src2 dst

.S
Instruction Type
Single-cycle
3-115
SHR
Delay Slots Example 1 0
SHR .S1 A0,8,A1 1 cycle after instruction A0 F123 63D1h A1 FFF1 2363h
Before instruction A0 F123 63D1h A1 XXXX XXXXh
Example 2
SHR .S2
B0,B1,B2 1 cycle after instruction B0 1492 5A41h B1 0000 0012h B2 0000 0524h
Before instruction B0 1492 5A41h B1 0000 0012h B2 XXXX XXXXh
Example 3
SHR .S2
B1:B0,B2,B3:B2 1 cycle after instruction B1:B0 0000 0012h B2 0000 090Ah XXXX XXXXh B3:B2 0000 0000h 0000 090Ah 1492 5A41h
Before instruction B1:B0 0000 0012h B2 0000 0019h B3:B2 XXXX XXXXh 1492 5A41h
3-116
SHRU
SHRU
Syntax
Logical Shift Right

SHRU (.unit) src2, src1, dst .unit = .S1 or .S2
Opcode map field used... For operand type... xuint uint uint ulong uint ulong xuint ucst5 uint ulong ucst5 ulong Unit .S1, .S2 Opfield 100111
.S1, .S2
100101
.S1, .S2
100110
.S1, .S2
100100
Opcode
31 29 28 27 23 22 18 17 13 12 11 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
6
Description
The src2 operand is shifted to the right by the src1 operand. The zero-extended result is placed in dst. When a register is used, the six LSBs specify the shift amount and valid values are 040. When an immediate is used, valid shift amounts are 031. If 39 < src1 < 64, src2 is shifted to the right by 40. Only the six LSBs of src1 are used by the shifter, so any bits set above bit 5 do not affect execution.
Execution
if (cond) else
src2 >>z src1 dst nop
3-117
SHRU
Pipeline
E1
src1, src2 dst

.S
Single-cycle 0
SHRU .S1 A0,8,A1 1 cycle after instruction A0 F123 63D1h A1 00F1 2363h
Before instruction A0 F123 63D1h A1 XXXX XXXXh
3-118
SMPY (HL/LH/H)
SMPY (HL/LH/H)
Syntax
Integer Multiply With Left Shift and Saturation

SMPY (.unit) src1, src2, dst or SMPYHL (.unit) src1, src2, dst or SMPYLH (.unit) src1, src2, dst or SMPYH (.unit) src1, src2, dst .unit = .M1 or .M2
Opcode map field used... For operand type... Unit .M1, .M2 Opfield 11010 Mnemonic SMPY
slsb16 xslsb15 sint smsb16 xslsb16 sint slsb16 xsmsb16 sint smsb16 xsmsb16 sint
.M1, .M2
01010
SMPYHL
.M1, .M2
10010
SMPYLH
.M1, .M2
00010
SMPYH
Opcode
31 29 28 27 23 22 18 17 13 12 11 7 6 0 5 0 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
5
Description
The src1 operand is multiplied by the src2 operand. The result is left shifted by 1 and placed in dst. If the left-shifted result is 0x8000 0000, then the result is saturated to 0x7FFF FFFF. If a saturate occurs, the SAT bit in the CSR is set one cycle after dst is written.
3-119
SMPY (HL/LH/H)
Execution if (cond) { if (((src1 src2) << 1) != 0x8000 0000 ) ((src1 src2) << 1) dst else 0x7FFF FFFF dst } nop
else Pipeline
E1
E2
src1, src2 dst

.M
Single-cycle (16 1
SMPY .M1
16)
A1,A2,A3 2 cycle after instruction A1 0000 0123h A2 01E0 FA81h A3 FFF3 8146h CSR 0001 0100h 818874 Not saturated
Before instruction A1 0000 0123h A2 01E0 FA81h A3 XXXX XXXXh CSR 0001 0100h 291 1407
Example 2
SMPYHL .M1 A1,A2,A3 Before instruction A1 008A 0000h A2 0000 00A7h A3 XXXX XXXXh CSR 0001 0100h
2 cycles after instruction A1 008A 0000h A2 0000 00A7h A3 0000 B40Ch CSR 0001 0100h 46092 Not saturated
138 167
3-120
SMPY (HL/LH/H)
Example 3
SMPYLH .M1 A1,A2,A3 Before instruction A1 0000 8000h A2 8000 0000h A3 XXXX XXXXh CSR 0001 0100h
2 cycles after instruction A1 0000 8000h A2 8000 0000h A3 7FFF FFFFh CSR 0001 0300h 2147483647 Saturated
32768 32768
3-121
SSHL
SSHL
Syntax
Shift Left With Saturation

SSHL (.unit) src2, src1, dst .unit = .S1 or .S2
Opcode map field used... For operand type... xsint uint sint xsint ucst5 sint Unit .S1, .S2 Opfield 100011
.S1, .S2
100010
Opcode
31 29 28 27 23 22 18 17 13 12 11 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
6
Description
The src2 operand is shifted to the left by the src1 operand. The result is placed in dst. When a register is used to specify the shift, the five least significant bits specify the shift amount. Valid values are 0 through 31, and the result of the shift is invalid if the shift amount is greater than 31. The result of the shift is saturated to 32 bits. If a saturate occurs, the SAT bit in the CSR is set one cycle after dst is written. Note: For the C64x, when a register is used to specify the shift, the six least-significant bits specify the shift amount. Valid values are 0 through 63. If the shift count value is greater than 32, then the result is saturate to 32 bits when src2 is non-zero.
3-122
SSHL
Execution
if (cond)
else Pipeline
{ if ( bit(31) through bit(31src1) of src2 are all 1s or all 0s) dst = src2 << src1; else if (src2 > 0) saturate dst to 0x7FFF FFFF; else if (src2 < 0) saturate dst to 0x8000 0000; } nop
E1
src1, src2 dst

.S

Before instruction A0 02E3 031Ch A1 XXXX XXXXh CSR 0001 0100h
Single-cycle 0
SSHL .S1 A0,2,A1 1 cycle after instruction A0 02E3 031Ch A1 0B8C 0C70h CSR 0001 0100h 2 cycles after instruction A0 02E3 031Ch A1 0B8C 0C70h CSR 0001 0100h Not saturated
Example 2
SSHL .S1
A0,A1,A2 1 cycle after instruction 2 cycles after instruction A0 4719 1925h A1 0000 0006h A2 7FFF FFFFh CSR 0001 0300h
Saturated
Before instruction A0 4719 1925h A1 0000 0006h A2 XXXX XXXXh CSR 0001 0100h
A0 4719 1925h A1 0000 0006h A2 7FFF FFFFh CSR 0001 0100h
3-123
SSUB
SSUB
Syntax
Integer Subtraction With Saturation to Result Size

SSUB (.unit) src1, src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... sint xsint sint xsint sint sint scst5 xsint sint scst5 slong slong Unit .L1, .L2 Opfield 0001111
.L1, .L2
0011111
.L1, .L2
0001110
.L1, .L2
0101100
Opcode
31 29 28 27 23 22 18 17 13 12 11 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
7
Description
src2 is subtracted from src1 and is saturated to the result size according to the following rules:
1) If the result is an int and src1 src2 > 231 1, then the result is 231 1. 2) If the result is an int and src1 src2 < 231, then the result is 231. 3) If the result is a long and src1 src2 > 239 1, then the result is 239 1. 4) If the result is a long and src1 src2 < 239, then the result is 239. The result is placed in dst. If a saturate occurs, the SAT bit in the CSR is set one cycle after dst is written.
Execution
if (cond) else
src1 s src2 dst nop
3-124
SSUB
Pipeline
E1
src1, src2 dst

.L

Before instruction
B1 B2 B3 CSR 5A2E 51A3h 802A 3FA2h XXXX XXXXh 0001 0100h
Single-cycle 0
SSUB .L2 B1,B2,B3 1 cycle after instruction
B1 B2 B3 CSR 5A2E 51A3h 802A 3FA2h 7FFF FFFFh 0001 0100h 2147483647 B1 B2 B3 CSR

5A2E 51A3h 802A 3FA2h 7FFF FFFFh 0001 0300h Saturated
1512984995 2144714846
Example 2
Before instruction
A0 A1 A2 CSR 4367 71F2h 5A2E 51A3h XXXX XXXXh 0001 0100h
SSUB .L1
A0,A1,A2 1 cycle after instruction

A0 A1 A2 4367 71F2h 5A2E 51A3h E939 204Fh 0001 0100h 382132145 A0 A1 A2 CSR

4367 71F2h 5A2E 51A3h E939 204Fh 0001 0100h Not saturated
1130852850 1512984995
CSR
3-125
STB/STH/STW
STB/STH/STW
Syntax
Store to Memory With a Register Offset or 5-Bit Unsigned Constant Offset

STB (.unit) src,*+baseR[offsetR] or STH (.unit) src, *+baseR[offsetR] or STW (.unit) src, *+baseR[offsetR] .unit = .D1 or .D2
Opcode
31 29 28 27 23 22 18 17 13 12 9 8 7 y 6 4 3 0 2 1 1 0
creg
3
src
5
baseR
5
offsetR/ucst5
5
mode
4
ld/st
3
Description
Each of these instructions performs a store to memory from a general-purpose register (src). Table 317 summarizes the data types supported by stores. Table 318 describes the addressing generator options. The memory address is formed from a base address register (baseR) and an optional offset that is either a register (offsetR) or a 5-bit unsigned constant (ucst5).
offsetR and baseR must be in the same register file and on the same side as the .D unit used. The y bit in the opcode determines the .D unit and register file used: y = 0 selects the .D1 unit and baseR and offsetR from the A register file, and y = 1 selects the .D2 unit and baseR and offsetR from the B register file. offsetR/ucst5 is scaled by a left-shift of 0, 1, or 2 for STB, STH, and STW, respectively. After scaling, offsetR/ucst5 is added to or subtracted from baseR. For the preincrement, predecrement, positive offset, and negative offset address generator options, the result of the calculation is the address to be accessed in memory. For postincrement or postdecrement addressing, the value of baseR before the addition or subtraction is sent to memory.
The addressing arithmetic that performs the additions and subtractions defaults to linear mode. However, for A4A7 and for B4B7, the mode can be changed to circular mode by writing the appropriate value to the AMR (see section 2.6.2 on page 2-14). For STB and STH the 8 and 16 LSBs of the src register are stored. For STW the entire 32-bit value is stored. src can be in either register file, regardless of the .D unit or baseR or offsetR used. The s bit determines which file the source is read from: s = 0 indicates src will be in the A register file, and s = 1 indicates src will be in the B register file. The r bit should be set to zero.
3-126
STB/STH/STW
Table 317. Data Types Supported by Stores

Mnemonic STB STH STW
ld/st Field
Store Data Type
SIze 8 16 32
Left Shift of Offset 0 bits 1 bit 2 bits
0 1 1 Store byte 1 0 1 Store halfword 1 1 1 Store word

Increments and decrements default to 1 and offsets default to zero when no bracketed register or constant is specified. Stores that do no modification to the baseR can use the syntax *R. Square brackets, [ ], indicate that the ucst5 offset is left-shifted by 2, 1, or 0 for word, halfword, and byte loads, respectively. Parentheses, ( ), can be used to set a nonscaled, constant offset. For example, STW (.unit) *+baseR(12) dst represents an offset of 12 bytes whereas STW (.unit) *+baseR[12] dst represents an offset of 12 words, or 48 bytes. You must type either brackets or parentheses around the specified offset if you use the optional offset parameter. Word and halfword addresses must be aligned on word (two LSBs are 0) and halfword (LSB is 0) boundaries, respectively. Execution if (cond) else
src mem nop

3-127
STB/STH/STW
Instruction Type Pipeline Store
Pipeline Stage Read
E1
E2
E3
baseR, offsetR src baseR

.D2
Written Unit in use
Delay Slots
0 For more information on delay slots for a store, see Chapter 6, TMS320C62x/C64x Pipeline, and Chapter 7, TMS320C67x Pipeline.
STB .D1 Before instruction A1,*A10 1 cycle after instruction A1 A10 mem 100h 9A32 7634h 0000 0100h 11h A1 A10 mem 100h 3 cycles after instruction 9A32 7634h 0000 0100h 34h
Example 1
A1 A10 mem 100h
9A32 7634h 0000 0100h 11h
Example 2
STH .D1 Before instruction
A1,*+A10(4) 1 cycle after instruction A1 A10 9A32 7634h 0000 0100h 1134h A1 A10 mem 104h 3 cycles after instruction 9A32 7634h 0000 0100h 7634h
A1 A10 mem 104h
9A32 7634h 0000 0100h 1134h
mem 104h
3-128
STB/STH/STW
Example 3
STW .D1 Before instruction
A1,*++A10[1] 1 cycle after instruction A1 A10 9A32 7634h 0000 0104h 1111 1134h 0000 1111h A1 A10 mem 100h mem 104h 3 cycles after instruction 9A32 7634h 0000 0104h 1111 1134h 9A32 7634h
A1 A10 mem 100h mem 104h
9A32 7634h 0000 0100h 1111 1134h 0000 1111h
mem 100h mem 104h
Example 4
STH .D1 Before instruction
A1,*A10[A11] 1 cycle after instruction A1 A10 A11 mem F8h 9A32 2634h 0000 00F8h 0000 0004h 0000h 0000h A1 A10 A11 mem F8h mem 100h 3 cycles after instruction 9A32 2634h 0000 00F8h 0000 0004h 0000h 2634h
A1 A10 A11 mem F8h mem 100h
9A32 2634h 0000 0100h 0000 0004h 0000h 0000
mem 100h
3-129
STB/STH/STW
STB/STH/STW
Syntax
Store to Memory With a 15-Bit Offset

STB (.unit) src, *+B14/B15[ucst15] or STH (.unit) src, *+B14/B15[ucst15] or STW (.unit) src, *+B14/B15[ucst15] .unit = .D2
Opcode
31 29 28 27 23 22 8 7 y 6 4 3 1 2 1 1 0
creg
3
src
5
ucst15
15
ld/st
3
Description
These instructions perform stores to memory from a general-purpose register (src). Table 319 summarizes the data types supported by stores. The memory address is formed from a base address register B14 (y = 0) or B15 (y = 1) and an optional offset that is a 15-bit unsigned constant (ucst15). The assembler selects this format only when the constant is larger than five bits in magnitude. This instruction executes only on the .D2 unit. The offset, ucst15, is scaled by a left-shift of 0, 1, or 2 for STB, STH, and STW, respectively. After scaling, ucst15 is added to baseR. The result of the calculation is the address that is sent to memory. The addressing arithmetic is always performed in linear mode. For STB and STH the 8 and 16 LSBs of the src register are stored. For STW the entire 32-bit value is stored. src can be in either register file. The s bit determines which file the source is read from: s = 0 indicates src is in the A register file, and s = 1 indicates src is in the B register file. Square brackets, [ ], indicate that the ucst15 offset is left-shifted by 2, 1, or 0 for word, halfword, and byte loads, respectively. Parentheses, ( ), can be used to set a nonscaled, constant offset. For example, STW (.unit) *+B14/B15(60) dst represents an offset of 12 bytes, whereas STW (.unit) *+B14/B15[60] dst represents an offset of 60 words, or 240 bytes. You must type either brackets or parentheses around the specified offset if you use the optional offset parameter. Word and halfword addresses must be aligned on word (two LSBs are 0) and halfword (LSB is 0) boundaries, respectively.
3-130
STB/STH/STW
Table 319. Data Types Supported by Stores

Mnemonic STB STH STW
ld/st Field
Store Data Type
SIze 8 16 32
Left Shift of Offset 0 bits 1 bit 2 bits
0 1 1 Store byte 1 0 1 Store halfword 1 1 1 Store word
Execution Pipeline
if (cond) else
src mem nop

E1 B14/B15, src E2 E3
.D2
Store 0 Note: This instruction executes only on the .D2 unit.
Example
STB .D2 Before instruction B1 1234 5678h 0000 1000h 42h
B1,*+B14[40] 1 cycle after instruction B1 B14 1234 5678h 0000 1000h 42h B1 B14 mem 1028h 3 cycles after instruction 1234 5678h 0000 1000h 78h
B14 mem 1028h
mem 1028h
3-131
SUB(U)
SUB(U)
Syntax
Signed or Unsigned Integer Subtraction Without Saturation

SUB (.unit) src1, src2, dst or SUBU (.unit) src1, src2, dst or SUB (.D1 or .D2) src2, src1, dst .unit = .L1, .L2, .S1, .S2
Opcode map field used... For operand type... Unit .L1, .L2 Opfield 0000111 Mnemonic SUB
src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst
sint xsint sint xsint sint sint sint xsint slong xsint sint slong uint xuint ulong xuint uint ulong scst5 xsint sint scst5 slong slong sint xsint sint scst5 xsint sint
.L1, .L2
0010111
SUB
.L1, .L2
0100111
SUB
.L1, .L2
0110111
SUB
.L1, .L2
0101111
SUBU
.L1, .L2
0111111
SUBU
.L1, .L2
0000110
SUB
.L1, .L2
010010 0
SUB
.S1, .S2
010111
SUB
.S1, .S2
010110
SUB
3-132
SUB(U)
Opcode map field used... For operand type...
Unit .D1, .D2
Opfield 010001
Mnemonic SUB
sint sint sint sint ucst5 sint
.D1, .D2
010011
SUB
Opcode
.L unit form:
31 29 28 27 23 22 18 17 13 12 11 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
7
.S unit form:
31 29 28 27 23 22 18 17 13 12 11 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
6
Description for .L1, .L2 and .S1, .S2 Opcodes src2 is subtracted from src1. The result is placed in dst. Execution for .L1, .L2 and .S1, .S2 Opcodes if (cond) src1 src2 dst else nop Opcode
.D unit form:
31 29 28 27 23 22 18 17 13 12 7 6 1 5 0 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
6
Description for .D1, .D2 Opcodes src1 is subtracted from src2. The result is placed in dst. Execution for .D1, .D2 Opcodes if (cond) else
src2 src1 dst nop

3-133
SUB(U)
Note: Subtraction with a signed constant on the .L and .S units allows either the first or the second operand to be the signed 5-bit constant. SUB src1, scst5, dst is encoded as ADD scst5, src2, dst where the src1 register is now src2 and scst5 is now scst5. However, the .D unit provides only the second operand as a constant since it is an unsigned 5-bit constant. ucst5 allows a greater offset for addressing with the .D unit. Pipeline
E1
src1, src2 dst

.L, .S, or .D
Single-cycle 0
SUB .L1 A1,A2,A3 1 cycle after instruction A1 0000 325Ah A2 FFFF FF12h A3 0000 3348h 13128
Before instruction A1 0000 325Ah A2 FFFF FF12h A3 XXXX XXXXh 12810 238
Example 2
SUBU .L1 Before instruction

A1 A2
A1,A2,A5:A4 1 cycle after instruction

A1 A2 A5:A4
0000 325Ah FFFF FF12h

XXXX XXXXh
12810 4294967058
XXXX XXXXh
0000 325Ah FFFF FF12h 0000 00FFh 0000 3348h 4294954168
A5:A4
Unsigned 32-bit integer Signed 40-bit (long) integer
3-134
SUBAB/SUBAH/SUBAW
SUBAB/SUBAH/SUBAW
Syntax
Integer Subtraction Using Addressing Mode
SUBAB (.unit) src2, src1, dst or SUBAH (.unit) src2, src1, dst or SUBAW (.unit) src2, src1, dst .unit = .D1 or .D2
Opcode map field used... For operand type... sint sint sint sint ucst5 sint Unit .D1, .D2 Opfield Byte: 110001 Halfword: 110101 Word: 111001 Byte: 110011 Halfword: 110111 Word: 111011
.D1, .D2
Opcode
31 29 28 27 23 22 18 17 13 12 7 6 1 5 0 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
6
Description
src1 is subtracted from src2. The subtraction defaults to linear mode. However, if src2 is one of A4A7 or B4B7, the mode can be changed to circular mode by writing the appropriate value to the AMR (see section 2.6.2 on page 2-14). src1 is left shifted by 1 or 2 for halfword and word data sizes, respectively. SUBAB, SUBAH, and SUBAW are byte, halfword, and word mnemonics, respectively. The result is placed in dst.
if (cond) else
Execution Pipeline
src2 a src1 dst nop

E1
src1, src2 dst

.D
Single-cycle 0
3-135
SUBAB/SUBAH/SUBAW
Example 1
SUBAB .D1
A5,A0,A5 1 cycle after instruction A0 0000 0004h A5 0000 400Ch AMR 0003 0004h
Before instruction A0 0000 0004h A5 0000 4000h AMR 0003 0004h
Example 2
SUBAW .D1
A5,2,A3 1 cycle after instruction A3 0000 0108h A5 0000 0100h AMR 0003 0004h
Before instruction A3 XXXX XXXXh A5 0000 0100h AMR 0003 0004h
3-136
SUBC
SUBC
Syntax
Conditional Integer Subtract and Shift Used for Division

SUBC (.unit) src1, src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... uint xuint uint Unit .L1, .L2
src1 src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 5 1001011 7 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
src1
5
Description
Subtract src2 from src1. If result is greather than or equal to 0, left shift result by 1, add 1 to it, and place it in dst. If result is less than 0, left shift scr1 by 1, and place it in dst. This step is commonly used in division. if (cond) { if (src1 src2 w 0) ( (src1src2) << 1) + 1 dst else src1 << 1 dst } nop
Execution
else Pipeline
E1
src1, src2 dst

.L
Single-cycle 0
3-137
SUBC
Example 1
SUBC .L1
A0,A1,A0 1 cycle after instruction A0 0000 024B4h A1 0000 1F12h 9396
Before instruction A0 0000 125Ah A1 0000 1F12h 4698 7954
Example 2
SUBC .L1
A0,A1,A0 1 cycle after instruction A0 0000 47E5h A1 0001 F63Fh 18405
Before instruction A0 0002 1A31h A1 0001 F63Fh 137777 128575
3-138
SUB2
SUB2
Syntax
Two 16-Bit Integer Subtractions on Upper and Lower Register Halves

SUB2 (.unit) src1, src2, dst .unit = .S1 or .S2
Opcode map field used... For operand type... sint xsint sint Unit .S1, .S2
src1 src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 6 010001 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1
5
Description
The upper and lower halves of src2 are subtracted from the upper and lower halves of src1. Any borrow from the lower-half subtraction does not affect the upper-half subtraction. if (cond) { ((lsb16(src1) lsb16(src2)) and FFFFh) or ((msb16(src1) msb16(src2)) << 16) dst } nop
E1
Execution
else Pipeline
src1, src2 dst

.S
Single-cycle 0
SUB2 .S2X B1,A0,B2 1 cycle after instruction 12913 6984 A0 0021 3271h B1 003A 1B48h B2 0019 E8D7h 25 5929
Before instruction A0 0021 3271h B1 003A 1B48h B2 XXXX XXXXh

Signed 16-MSB integer Signed 16-LSB integer 33 58
3-139
XOR
XOR
Syntax
Exclusive OR
XOR (.unit) src2, src1, dst .unit = .L1 or .L2, .S1 or .S2
.L1, .L2
1101110
.S1, .S2
001011
.S1, .S2
001010
Opcode
.L unit form:
31 29 28 27 23 22 18 17 13 12 11 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
7
.S unit form:
31 29 28 27 23 22 18 17 13 12 11 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
6
Description
A bitwise exclusive-OR is performed between src1 and src2. The result is placed in dst. The scst5 operands are sign extended to 32 bits.
3-140
XOR
src1 xor src2 dst nop

E1
src1, src2 dst

.L or .S
Single-cycle 0
XOR .L1 A1,A2,A3 1 cycle after instruction A1 0721 325Ah A2 0019 0F12h A3 0738 3D48h
Before instruction A1 0721 325Ah A2 0019 0F12h A3 XXXX XXXXh
Example 2
XOR .L2
B1,0dh,B2 1 cycle after instruction B1 0000 1023h B2 0000 102Eh
Before instruction B1 0000 1023h B2 XXXX XXXXh
3-141
ZERO
ZERO
Syntax
Zero a Register (Pseudo-Operation)

ZERO (.unit) dst .unit = .L1, .L2, .D1, .D2, .S1, or .S2
Opcode map field used... For operand type... Unit .L1, .L2 .D1, .D2 .S1, .S2 .L1, .L2 Opfield 0010111 010001 010111 0110111
dst dst dst dst
sint sint sint slong
Description
This is a pseudo operation used to fill the dst register with 0s by subtracting the dst from itself and placing the result in the dst. The assembler uses the operation SUB (.unit) src1, src2, dst to perform this task where src1 and src2 both equal dst. For the C64x, the operation performed is MVK 0, dst. In the case where dst is an slong, the C64x will use the SUB operation like the C62x/C67x. if (cond) else
Execution
dst dst dst nop
Single-cycle 0
3-142
Chapter 4
TMS320C67x Floating-Point Instruction Set

The TMS320C67x floating-point DSP uses all of the instructions available to the TMS320C62x, but it also uses other instructions that are specific to the C67x. These specific instructions are for 32-bit integer multiply, doubleword load, and floating-point operations, including addition, subtraction, and multiplication. This chapter describes these C67x-specific instructions. Instructions that are common to both the C62x and C67x are described in Chapter 3.
Topic
4.1 4.2 4.3 4.4 4.5 4.6
Page
Instruction Operation and Execution Notations . . . . . . . . . . . . . . . . . . 4-2 Mapping Between Instructions and Functional Units . . . . . . . . . . . . . 4-4 Overview of IEEE Standard Single- and Double-Precision Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Delay Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 TMS320C67x Instruction Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Individual Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4-1

Table 41 explains the symbols used in the floating-point instruction descriptions.
Table 41. Floating-Point Instruction Operation and Execution Notations

Symbol abs(x) cond creg cstn dp dp(x) dst_h dst_l int int(x) lsbn or LSBn Meaning Absolute value of x Check for either creg equal to 0 or creg not equal to 0 3-bit field specifying a conditional register n-bit constant field (for example, cst5) Double-precision floating-point register value Convert x to dp msb32 of dst lsb32 of dst 32-bit integer value Convert x to integer n least significant bits (for example, lsb32)
msbn or MSBn n most significant bits (for example, msb32) nop R rcp(x) sdint sint sp sp(x) sqrcp(x) src1_h src1_l src2_h src2_l No operation Any general-purpose register Reciprocal approximation of x Signed 64-bit integer value (two registers) Signed 32-bit integer value Single-precision floating-point register value that can optionally use cross path Convert x to sp Square root of reciprocal approximation of x msb32 of src1 lsb32 of src1 msb32 of src2 lsb32 of src2
4-2
Table 41. Floating-Point Instruction Operation and Execution Notations (Continued)

Symbol ucstn uint dp xsint sp xsp xuint + << Meaning n-bit unsigned constant field (for example, ucstn5) Unsigned 32-bit integer value Double-precision floating-point register value Signed 32-bit integer value that can optionally use cross path Single-precision floating-point register value Single-precision floating-point register value that can optionally use cross path Unsigned 32-bit integer value that can optionally use cross path Assignment Addition Multiplication Subtraction Shift left
4-3

Table 42 shows the mapping between instructions and functional units and and Table 43 shows the mapping between functional units and instructions.

.L Unit ADDDP ADDSP DPINT DPSP DPTRUNC INTDP INTDPU INTSP INTSPU SPINT SPTRUNC SUBDP SUBSP .M Unit MPYDP MPYI MPYID MPYSP .S Unit ABSDP ABSSP CMPEQDP CMPEQSP CMPGTDP CMPGTSP CMPLTDP CMPLTSP RCPDP RCPSP RSQRDP RSQRSP SPDP .D Unit ADDAD LDDW

C67x Functional Units Instruction ABSDP ABSSP ADDAD ADDDP ADDSP CMPEQDP CMPEQSP CMPGTDP CMPGTSP .L Unit .M Unit .S Unit .D Unit Type 2-cycle DP Single cycle
n n n n n n n n n
Single cycle ADDDP/ SUBDP Four cycle DP compare Single cycle DPcompare Single cycle
4-4

C67x Functional Units Instruction CMPLTDP CMPLTSP DPINT DPSP DPTRUNC INTDP INTDPU INTSP INTSPU LDDW MPYDP MPYI MPYID MPYSP RCPDP RCPSP RSQRDP RSQRSP SPDP SPINT SPTRUNC SUBDP SUBSP .L Unit .M Unit .S Unit .D Unit Type DP compare Single cycle 4-cycle 4-cycle 4-cycle INTDP INTDP 4-cycle 4-cycle
n n n n n n n n n n n n n n n n n n n n n n n
Load MPYDP MPYI MPYID 4-cycle 2-cycle DP Single cycle 2-cycle DP Single cycle 2-cycle DP 4-cycle 4-cycle ADDDP/ SUBDP 4-cycle
4-5
Overview of IEEE Standard Single- and Double-Precision Formats
4.3 Overview of IEEE Standard Single- and Double-Precision Formats

Floating-point operands are classified as single-precision (SP) and doubleprecision (DP). Single-precision floating-point values are 32-bit values stored in a single register. Double-precision floating-point values are 64-bit values stored in a register pair. The register pair consists of consecutive even and odd registers from the same register file. The least significant 32 bits are loaded into the even register. The most significant 32 bits containing the sign bit and exponent are loaded into the next register (which is always the odd register). The register pair syntax places the odd register first, followed by a colon, then the even register (that is, A1:A0, B1:B0, A3:A2, B3:B2, etc.). Instructions that use DP sources fall in two categories: instructions that read the upper and lower 32-bit words on separate cycles, and instructions that read both 32-bit words on the same cycle. All instructions that produce a double-precision result write the low 32-bit word one cycle before writing the high 32-bit word. If an instruction that writes a DP result is followed by an instruction that uses the result as its DP source and it reads the upper and lower words on separate cycles, then the second instruction can be scheduled on the same cycle that the high 32-bit word of the result is written. The lower result is written on the previous cycle. This is because the second instruction reads the low word of the DP source one cycle before the high word of the DP source. IEEE floating-point numbers consist of normal numbers, denormalized numbers, NaNs (not a number), and infinity numbers. Denormalized numbers are nonzero numbers that are smaller than the smallest nonzero normal number. Infinity is a value that represents an infinite floating-point number. NaN values represent results for invalid operations, such as (+infinity + (infinity)). Normal single-precision values are always accurate to at least six decimal places, sometimes up to nine decimal places. Normal double-precision values are always accurate to at least 15 decimal places, sometimes up to 17 decimal places. Table 44 shows notations used in discussing floating-point numbers.
4-6

Table 44. IEEE Floating-Point Notations
signed NaN_out signed Inf SDFPN LDFPN SFPN LFPN Inf NaN_out QNaN SNaN NaN x f e s Symbol

NaN_out with s = 0 or 1 +infinity or infinity Smallest denormalized floating-point number Largest denormalized floating-point number Smallest floating-point number Largest floating-point number Infinity QNaN with all bits in the f field= 1 Quiet NaN Signal NaN Not-a-Number (SNaN or QNaN) Can have value of 0 or 1 (dont care) Fraction (mantissa) field Exponent field Sign bit Meaning
4-7
Figure 41 shows the fields of a single-precision floating-point number represented within a 32-bit register.
Figure 41. Single-Precision Floating-Point Fields

31 30 s Legend: s e f e sign bit (0 positive, 1 negative) 8-bit exponent ( 0 < e < 255) 23-bit fraction 0 < f < 1*21 + 1*22 + ... + 1*223 or 0 < f < ((223)1)/(223) 23 22 f 0
The floating-point fields represent floating-point numbers within two ranges: normalized (e is between 0 and 255) and denormalized (e is 0). The following formulas define how to translate the s, e, and f fields into a single-precision floating-point number. Normal 1s * 2(e127) * 1.f 0 < e < 255
Denormalized (Subnormal) 1s * 2126 * 0.f e = 0; f nonzero
Table 45 shows the s,e, and f values for special single-precision floatingpoint numbers.
Table 45. Special Single-Precision Values
4-8

Symbol +0 0 Sign (s) 0 1 0 1 x x x Exponent (e) 0 0 Fraction (f) 0 0 0 0 +Inf Inf 255 255 255 255 255 NaN nonzero 1xx..x QNaN SNaN 0xx..x and nonzero
Table 46 shows hex and decimal values for some single-precision floatingpoint numbers.
Figure 42. Double-Precision Floating-Point Fields

31 30 s e 20 19 f 0 31 f 0

Symbol Hex Value Decimal Value QNaN 0.0 NaN_out 0 0x7FFF FFFF 0x0000 0000 0x8000 0000 0 1 2 0.0 1.0 2.0 0x3F80 0000 0x4000 0000 LFPN 0x7F7F FFFF 0x0080 0000 3.40282347e+38 1.17549435e38 1.17549421e38 1.40129846e45 SFPN LDFPN 0x007F FFFF 0x0000 0001 SDFPN
Table 46. Hex and Decimal Representation for Selected Single-Precision Values
Figure 42 shows the fields of a double-precision floating-point number represented within a pair of 32-bit registers.
Odd register Legend: s e f sign bit (0 positive, 1 negative) 11-bit exponent ( 0 < e < 2047) 52-bit fraction 0 < f < 1*21 + 1*22 + ... + 1*252 or 0 < f < ((252)1)/(252)
Even register
The floating-point fields represent floating-point numbers within two ranges: normalized (e is between 0 and 2047) and denormalized (e is 0). The following formulas define how to translate the s, e, and f fields into a double-precision floating-point number. Normal 1s * 2(e1023) * 1.f 0 < e < 2047
Denormalized (Subnormal) 1s * 21022 * 0.f e = 0; f nonzero

4-9

Table 48. Hex and Decimal Representation for Selected Double-Precision Values
Table 48 shows hex and decimal values for some double-precision floatingpoint numbers.
SDFPN LDFPN SFPN LFPN 2 1 0 0 NaN_out Symbol SNaN 0x0000 0000 0000 0001 0x000F FFFF FFFF FFFF 0x0010 0000 0000 0000 0x7FEF FFFF FFFF FFFF 0x4000 0000 0000 0000 0x3FF0 0000 0000 0000 0x8000 0000 0000 0000 0x0000 0000 0000 0000 0x7FFF FFFF FFFF FFFF Hex Value x 2047 4.9406564584124654e324 2.2250738585072009e308 2.2250738585072014e308 1.7976931348623157e+308 2.0 1.0 0.0 0.0 QNaN Decimal Value 0xx..x and nonzero
Table 47. Special Double-Precision Values

Table 47 shows the s,e, and f values for special double-precision floatingpoint numbers.
QNaN NaN Inf +Inf 0 +0 Symbol Sign (s) 1 0 1 0 x x 2047 2047 2047 2047 0 0 Exponent (e) 1xx..x nonzero 0 0 0 0 Fraction (f)
4-10
Delay Slots
4.4 Delay Slots

The execution of floating-point instructions can be defined in terms of delay slots and functional unit latency. The number of delay slots is equivalent to the number of additional cycles required after the source operands are read for the result to be available for reading. For a single-cycle type instruction, operands are read on cycle i and produce a result that can be read on cycle i + 1. For a 4-cycle instruction, operands are read on cycle i and produce a result that can be read on cycle i + 4. Table 49 shows the number of delay slots associated with each type of instruction. The double-precision floating-point addition, subtraction, multiplication, compare, and the 32-bit integer multiply instructions also have a functional unit latency that is greater than 1. The functional unit latency is equivalent to the number of cycles that the instruction uses the functional unit read ports. For example, the ADDDP instruction has a functional unit latency of 2. Operands are read on cycle i and cycle i + 1. Therefore, a new instruction cannot begin until cycle i + 2, rather than i + 1. ADDDP produces a result that can be read on cycle i + 7, because it has six delay slots. Delay slots are equivalent to an execution or result latency. All of the instructions that are common to the C62x and C67x have a functional unit latency of 1. This means that a new instruction can be started on the functional unit each cycle. Single-cycle throughput is another term for single-cycle functional unit latency.

Instruction Type Single cycle 2-cycle DP 4-cycle INTDP Load Delay Slots 0 1 3 4 4 1 6 8 9 9 Functional Unit Latency 1 1 1 1 1 2 2 4 4 4 Read Cycles i i i i i Write Cycles i i, i + 1 i+3 i + 3, i + 4 i, i + 4 1+1 DP compare i, i + 1 i, i + 1 ADDDP/SUBDP MPYI i + 5, i + 6 i+8 i, i + 1, 1 + 2, i + 3 i, i + 1, 1 + 2, i + 3 i, i + 1, 1 + 2, i + 3 MPYID i + 8, i + 9 i + 8, i + 9 MPYDP
Cycle i is in the E1 pipeline phase. A write on cycle i + 4 uses a separate write port from other instructions on the .D unit.
4-11
TMS320C67x Instruction Constraints
4.5 TMS320C67x Instruction Constraints

If an instruction has a multicycle functional unit latency, it locks the functional unit for the necessary number of cycles. Any new instruction dispatched to that functional unit during this locking period causes undefined results. If an instruction with a multicycle functional unit latency has a condition that is evaluated as false during E1, it still locks the functional unit for subsequent cycles. An instruction of the following types scheduled on cycle i has the following constraints: DP compare ADDDP/SUBDP MPYI MPYID MPYDP No other instruction can use the functional unit on cycles i and i + 1. No other instruction can use the functional unit on cycles i and i + 1. No other instruction can use the functional unit on cycles i, i + 1, i + 2, and i + 3. No other instruction can use the functional unit on cycles i, i + 1, i + 2, and i + 3. No other instruction can use the functional unit on cycles i, i + 1, i + 2, and i + 3.
If a cross path is used to read a source in an instruction with a multicycle functional unit latency, you must ensure that no other instructions executing on the same side uses the cross path. An instruction of the following types scheduled on cycle i using a cross path to read a source, has the following constraints: DP compare ADDDP/SUBDP MPYI MPYID MPYDP No other instruction on the same side can used the cross path on cycles i and i + 1. No other instruction on the same side can use the cross path on cycles i and i + 1. No other instruction on the same side can use the cross path on cycles i, i + 1, i + 2, and i + 3. No other instruction on the same side can use the cross path on cycles i, i + 1, i + 2, and i + 3. No other instruction on the same side can use the cross path on cycles i, i + 1, i + 2, and i + 3.
Other hazards exist because instructions have varying numbers of delay slots, and need the functional unit read and write ports of varying numbers of cycles. A read or write hazard exists when two instructions on the same functional unit attempt to read or write, respectively, to the register file on the same cycle.
4-12
An instruction of the following types scheduled on cycle i has the following constraints: 2-cycle DP A single-cycle instruction cannot be scheduled on that functional unit on cycle i + 1 due to a write hazard on cycle i + 1. Another 2-cycle DP instruction cannot be scheduled on that functional unit on cycle i + 1 due to a write hazard on cycle i + 1. A single-cycle instruction cannot be scheduled on that functional unit on cycle i + 3 due to a write hazard on cycle i + 3. A multiply (16 16-bit) instruction cannot be scheduled on that functional unit on cycle i + 2 due to a write hazard on cycle i + 3. A single-cycle instruction cannot be scheduled on that functional unit on cycle i + 3 or i + 4 due to a write hazard on cycle i + 3 or i + 4, respectively. An INTDP instruction cannot be scheduled on that functional unit on cycle i + 1 due to a write hazard on cycle i + 1. A 4-cycle instruction cannot be scheduled on that functional unit on cycle i + 1 due to a write hazard on cycle i + 1. A 4-cycle instruction cannot be scheduled on that functional unit on cycle i + 4, i + 5, or i + 6. A MPYDP instruction cannot be scheduled on that functional unit on cycle i + 4, i + 5, or i + 6. A multiply (16 16-bit) instruction cannot be scheduled on that functional unit on cycle i + 6 due to a write hazard on cycle i + 7. MPYID A 4-cycle instruction cannot be scheduled on that functional unit on cycle i + 4, i + 5, or i + 6. A MPYDP instruction cannot be scheduled on that functional unit on cycles i + 4, i + 5, or i + 6. A multiply (16 16-bit) instruction cannot be scheduled on that functional unit on cycle i + 7 or i + 8 due to a write hazard on cycle i + 8 or i + 9, respectively.
4-cycle
INTDP
MPYI
4-13
MPYDP
A 4-cycle instruction cannot be scheduled on that functional unit on cycle i + 4, i + 5, or i + 6. A MPYI instruction cannot be scheduled on that functional unit on cycle i + 4, i + 5, or i + 6. A MPYID instruction cannot be scheduled on that functional unit on cycle i + 4, i + 5, or i + 6. A multiply (1616-bit) instruction cannot be scheduled on that functional unit on cycle i + 7 or i + 8 due to a write hazard on cycle i + 8 or i + 9, respectively.
ADDDP/SUBDP
A single-cycle instruction cannot be scheduled on that functional unit on cycle i + 5 or i + 6 due to a write hazard on cycle i + 5 or i + 6, respectively. A 4-cycle instruction cannot be scheduled on that functional unit on cycle i + 2 or i + 3 due to a write hazard on cycle i + 5 or i + 6, respectively. An INTDP instruction cannot be scheduled on that functional unit on cycle i + 2 or i + 3 due to a write hazard on cycle i + 5 or i + 6, respectively.
All of the above cases deal with double-precision floating-point instructions or the MPYI or MPYID instructions except for the 4-cycle case. A 4-cycle instruction consists of both single- and double-precision floating-point instructions. Therefore, the 4-cycle case is important for the following single-precision floating-point instructions:
-
ADDSP SUBSP SPINT SPTRUNC INTSP MPYSP
The .S and .L units share their long write port with the load port for the 32 most significant bits of an LDDW load. Therefore, the LDDW instruction and the .S or .L unit writing a long result cannot write to the same register file on the same cycle. The LDDW writes to the register file on pipeline phase E5. Instructions that use a long result and use the .L and .S unit write to the register file on pipeline phase E1. Therefore, the instruction with the long result must be scheduled later than four cycles following the LDDW instruction if both instructions use the same side.
4-14

This section gives detailed information on the floating-point instruction set for the C67x. Each instruction presents the following information:
-
Assembler syntax Functional units Operands Opcode Description Execution Pipeline Instruction type Delay slots Examples
4-15
ABSDP
ABSDP
Syntax
Double-Precision Floating-Point Absolute Value

ABSDP (.unit) src2, dst .unit = .S1 or .S2
Opcode map field used... For operand type... dp dp Unit .S1, .S2
src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 6 101100 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
rsv
5
Description
The absolute value of src2 is placed in dst. The 64-bit double-precision operand is read in one cycle by using the src2 port for the 32 MSBs and the src1 port for the 32 LSBs. if (cond) else abs(src2) dst nop
Execution
The absolute value of src2 is determined as follows: 1) If src2 w 0, then src2 dst 2) If src2 t 0, then src2 dst Notes: 1) If scr2 is SNaN, NaN_out is placed in dst and the INVAL and NAN2 bits are set. 2) If src2 is QNaN, NaN_out is placed in dst and the NAN2 bit is set. 3) If src2 is denormalized, +0 is placed in dst and the INEX and DEN2 bits are set. 4) If src2 is +infinity or infinity, +infinity is placed in dst and the INFO bit is set. Pipeline
E1
E2
src2_l src2_h dst_l

.S
dst_h
4-16
ABSDP
If dst is used as the source for the ADDDP, CMPEQDP, CMPLTDP, CMPGTDP, MPYDP, or SUBDP instruction, the number of delay slots can be reduced by one, because these instructions read the lower word of the DP source one cycle before the upper word of the DP source. Instruction Type Delay Slots Functional Unit Latency Example 2-cycle DP 1 1
ABSDP .S1 Before instruction
A1:A0,A3:A2 2 cycles after instruction 2.5 A1:A0 c004 0000h A3:A2 4004 0000h 0000 0000h 0000 0000h 2.5 2.5
A1:A0 c004 0000h A3:A2 XXXX XXXXh
0000 0000h XXXX XXXXh
4-17
ABSSP
ABSSP
Syntax
Single-Precision Floating-Point Absolute Value

ABSSP (.unit) src2, dst .unit = . S1 or .S2
Opcode map field used... For operand type... xsp sp Unit .S1, .S2
src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 111100 6 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
The absolute value in src2 is placed in dst. if (cond) else abs(src2) dst nop
The absolute value of src2 is determined as follows: 1) If src2 w 0, then src2 dst 2) If src2 t 0, then src2 dst Notes: 1) If scr2 is SNaN, NaN_out is placed in dst and the INVAL and NAN2 bits are set. 2) If src2 is QNaN, NaN_out is placed in dst and the NAN2 bit is set. 3) If src2 is denormalized, +0 is placed in dst and the INEX and DEN2 bits are set. 4) If src2 is +infinity or infinity, +infinity is placed in dst and the INFO bit is set. Pipeline
E1
src2 dst
.S
Instruction Type
4-18
Single-cycle
ABSSP
Delay Slots Functional Unit Latency Example 0 1
ABSSP .S1X B1,A5 Before instruction B1 c020 0000h A5 XXXX XXXXh 2.5 1 cycle after instruction B1 c020 0000h A5 4020 0000h 2.5 2.5
4-19
ADDAD
ADDAD
Syntax
Integer Addition Using Doubleword Addressing Mode

ADDAD (.unit) src2, src1, dst .unit = . D1 or .D2
Opcode map field used... For operand type... sint sint sint sint ucst5 sint Unit .D1, .D2 Opfield 111100
.D1, .D2
111101
Opcode
31 29 28 27 23 22 18 17 13 12 7 6 1 5 0 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
6
Description
src1 is added to src2 using the doubleword addressing mode specified for src2. The addition defaults to linear mode. However, if src2 is one of A4A7 or B4B7, the mode can be changed to circular mode by writing the appropriate value to the AMR (see section 2.6.2 on page 2-14). src1 is left shifted by 3 due to doubleword data sizes. The result is placed in dst. (See the ADDAB/ ADDAH/ADDAW instruction, page 3-34, for byte, halfword, and word versions.)
Note: There is no SUBAD instruction.
Execution Pipeline
if (cond) else
src2 +(src1 tt 3) dst nop

E1
src1 src2 dst

.D
Instruction Type
4-20
Single-cycle
ADDAD
Delay Slots Functional Unit Latency Example 0 1
ADDAD .D1
A1,A2,A3 1 cycle after instruction A1 0000 1234h A2 0000 0002h A3 0000 1244h 4660 2 4676
Before instruction A1 0000 1234h A2 0000 0002h A3 XXXX XXXXh 4660 2
4-21
ADDDP
ADDDP
Syntax
Double-Precision Floating-Point Addition

ADDDP (.unit) src1, src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... dp xdp dp Unit .L1, .L2
src1 src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 5 0011000 7 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
src1
5
src2 is added to src1. The result is placed in dst.

if (cond) else
src1 + src2 dst nop
4-22
ADDDP
Notes: 1) If rounding is performed, the INEX bit is set. 2) If one source is SNaN or QNaN, the result is NaN_out. If either source is SNaN, the INVAL bit is set, also. 3) If one source is +infinity and the other is infinity, the result is NaN_out and the INVAL bit is set. 4) If one source is signed infinity and the other source is anything except NaN or signed infinity of the opposite sign, the result is signed infinity and the INFO bit is set. 5) If overflow occurs, the INEX and OVER bits are set and the results are rounded as follows (LFPN is the largest floating-point number):
Overflow Output Rounding Mode Result Sign + Nearest Even +infinity infinity Zero +LFPN LFPN +Infinity +infinity LFPN Infinity +LFPN infinity
6) If underflow occurs, the INEX and UNDER bits are set and the results are rounded as follows (SPFN is the smallest floating-point number):
Underflow Output Rounding Mode Result Sign + Nearest Even +0 0 Zero +0 0 +Infinity +SFPN 0 Infinity +0 SFPN
7) If the sources are equal numbers of opposite sign, the result is +0 unless the rounding mode is infinity, in which case the result is 0. 8) If the sources are both 0 with the same sign or both are denormalized with the same sign, the sign of the result is negative for negative sources and positive for positive sources. 9) A signed denormalized source is treated as a signed 0 and the DENn bit is set. If the other source is not NaN or signed infinity, the INEX bit is set.
4-23
ADDDP
Pipeline
E1
E2
E3
E4
E5
E6
E7
src1_l src2_l
src1_h src2_h dst_l dst_h
.L
.L
If dst is used as the source for the ADDDP, CMPEQDP, CMPLTDP, CMPGTDP, MPYDP, or SUBDP instruction, the number of delay slots can be reduced by one, because these instructions read the lower word of the DP source one cycle before the upper word of the DP source. Instruction Type Delay Slots Functional Unit Latency Example ADDDP/SUBDP 6 2
ADDDP .L1X B1:B0,A3:A2,A5:A4 Before instruction 7 cycles after instruction 8.6 2.5 B1:B0 4021 3333h A3:A2 C004 0000h A5:A4 4018 6666h 4021 3333h 0000 0000h 6666 6666h 8.6 2.5 6.1
B1:B0 4021 3333h A3:A2 C004 0000h A5:A4 XXXX XXXXh
3333 3333h 0000 0000h XXXX XXXXh
4-24
ADDSP
ADDSP
Syntax
Single-Precision Floating-Point Addition

ADDSP (.unit) src1, src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... sp xsp sp Unit .L1, .L2
src1 src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 5 0010000 7 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
src1
5
src2 is added to src1. The result is placed in dst.

if (cond) else
src1 + src2 dst nop
4-25
ADDSP
Notes: 1) If rounding is performed, the INEX bit is set. 2) If one source is SNaN or QNaN, the result is NaN_out. If either source is SNaN, the INVAL bit is set also. 3) If one source is +infinity and the other is infinity, the result is NaN_out and the INVAL bit is set. 4) If one source is signed infinity and the other source is anything except NaN or signed infinity of the opposite sign, the result is signed infinity and the INFO bit is set. 5) If overflow occurs, the INEX and OVER bits are set and the results are rounded as follows (LFPN is the largest floating-point number):
6) If underflow occurs, the INEX and UNDER bits are set and the results are rounded as follows (SPFN is the smallest floating-point number):
7) If the sources are equal numbers of opposite sign, the result is +0 unless the rounding mode is infinity, in which case the result is 0. 8) If the sources are both 0 with the same sign or both are denormalized with the same sign, the sign of the result is negative for negative sources and positive for positive sources. 9) A signed denormalized source is treated as a signed 0 and the DENn bit is set. If the other source is not NaN or signed infinity, the INEX bit is also set.
4-26
ADDSP
Pipeline
E1
E2
E3
E4
src1 src2 dst

.L
Instruction Type Delay Slots Functional Unit Latency Example
4-cycle 3 1
ADDSP .L1
A1,A2,A3 4 cycles after instruction A1 C020 0000h A2 4109 999Ah A3 40C3 3334h 2.5 8.6 6.1
Before instruction A1 C020 0000h A2 4109 999Ah A3 XXXX XXXXh 2.5 8.6
4-27
CMPEQDP
CMPEQDP
Syntax
Double-Precision Floating-Point Compare for Equality

CMPEQDP (.unit) src1, src2, dst .unit = .S1 or .S2
Opcode map field used... For operand type... dp xdp sint Unit .S1, .S2
src1 src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 6 101000 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1
5
Description
This instruction compares src1 to src2. If src1 equals src2, 1 is written to dst. Otherwise, 0 is written to dst. if (cond) { if (src1 == src2) 1 dst else 0 dst } nop
Execution
else
Special cases of inputs:
4-28
CMPEQDP
Input
FAUCR Fields
src1
NaN dont care NaN +/denormalized +/0 +/0
src2
dont care NaN NaN +/0 +/denormalized +/0
Output 0 0 0 1 1 1 1 1 0 1 0
UNORD 1 1 1 0 0 0 0 0 0 0 0
INVAL 0 0 0 0 0 0 0 0 0 0 0
+/denormalized +/denormalized +infinity +infinity infinity infinity +infinity other infinity other
Notes: 1) In the case of NaN compared with itself, the result is false. 2) No configuration bits besides those in the preceding table are set, except the NaNn and DENn bits when appropriate. Pipeline
Pipeline Stage Read Written Unit in use .S
E1
E2
src1_l src2_l
src1_h src2_h dst

.S
4-29
CMPEQDP
Instruction Type Delay Slots Functional Unit Latency Example DP compare 1 2
CMPEQDP .S1 A1:A0,A3:A2,A4 Before instruction 2 cycles after instruction 8.6 2.5 A1:A0 4021 3333h A3:A2 c004 0000h A4 0000 0000h 3333 3333h 0000 0000h false 8.6 2.5
A1:A0 4021 3333h A3:A2 c004 0000h A4 XXXX XXXXh
3333 3333h 0000 0000h
4-30
CMPEQSP
CMPEQSP
Syntax
Single-Precision Floating-Point Compare for Equality

CMPEQSP (.unit) src1, src2, dst .unit = .S1 or .S2
Opcode map field used... For operand type... sp xsp sint Unit .S1, .S2
src1 src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 6 111000 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1
5
Description
This instruction compares src1 to src2. If src1 equals src2, 1 is written to dst. Otherwise, 0 is written to dst. if (cond) { if (src1 == src2) 1 dst else 0 dst } nop
Execution
else
4-31
CMPEQSP
Input Configuration Register
src1
src2
Output 0 0 0 1 1 1 1 1 0 1 0
UNORD 1 1 1 0 0 0 0 0 0 0 0
INVAL 0 0 0 0 0 0 0 0 0 0 0
Notes: 1) In the case of NaN compared with itself, the result is false. 2) No configuration bits besides those shown in the preceding table are set, except for the NaNn and DENn bits when appropriate. Pipeline
E1
src1 src2 dst

.S
4-32
CMPEQSP
Instruction Type Delay Slots Functional Unit Latency Example Single-cycle 0 1
CMPEQSP .S1 A1,A2,A3 Before instruction A1 C020 0000h A2 4109 999Ah A3 XXXX XXXXh 2.5 8.6 1 cycle after instruction A1 C020 0000h A2 4109 999Ah A3 0000 0000h 2.5 8.6 false
4-33
CMPGTDP
CMPGTDP
Syntax
Double-Precision Floating-Point Compare for Greater Than

CMPGTDP (.unit) src1, src2, dst .unit = .S1 or .S2
src1 src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 6 101001 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1
5
Description
This instruction compares src1 to src2. If src1 is greater than src2, 1 is written to dst. Otherwise, 0 is written to dst. if (cond) { if (src1 > src2) 1 dst else 0 dst } nop
Execution
else
4-34
CMPGTDP
src1
src2
Output 0 0 0 0 0 0 0 0 1 0 0
UNORD 1 1 1 0 0 0 0 0 0 0 0
INVAL 1 1 1 0 0 0 0 0 0 0 0
Note: No configuration bits besides those shown in the preceding table are set, except the NaNn and DENn bits when appropriate. Pipeline
E1
E2
src1_l src2_l
src1_h src2_h dst

.S
4-35
CMPGTDP
CMPGTDP .S1 A1:A0,A3:A2,A4 Before instruction 2 cycles after instruction 8.6 2.5 A1:A0 4021 3333h A3:A2 c004 0000h A4 0000 0001h 3333 3333h 0000 0000h true 8.6 2.5
A1:A0 4021 3333h A3:A2 c004 0000h A4 XXXX XXXXh
3333 3333h 0000 0000h
4-36
CMPGTSP
CMPGTSP
Syntax
Single-Precision Floating-Point Compare for Greater Than

CMPGTSP (.unit) src1, src2, dst .unit = .S1 or .S2
src1 src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 6 111001 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1
5
Description
This instruction compares src1 to src2. If src1 is greater than src2, 1 is written to dst. Otherwise, 0 is written to dst. if (cond) { if (src1 > src2) 1 dst else 0 dst } nop
Execution
else
4-37
CMPGTSP
src1
src2
Output 0 0 0 0 0 0 0 0 1 0 0
UNORD 1 1 1 0 0 0 0 0 0 0 0
INVAL 1 1 1 0 0 0 0 0 0 0 0
Note: No configuration bits besides those shown in the preceding table are set, except for the NaNn and DENn bits when appropriate. Pipeline
E1
src1 src2 dst

.S
4-38
CMPGTSP
CMPGTSP .S1X A1,B2,A3 Before instruction A1 C020 0000h B2 4109 999Ah A3 XXXX XXXXh 2.5 8.6 1 cycle after instruction A1 C020 0000h B2 4109 999Ah A3 0000 0000h 2.5 8.6 false
4-39
CMPLTDP
CMPLTDP
Syntax
Double-Precision Floating-Point Compare for Less Than

CMPLTDP (.unit) src1, src2, dst .unit = .S1 or .S2
src1 src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 6 101010 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1
5
Description
This instruction compares src1 to src2. If src1 is less than src2, 1 is written to dst. Otherwise, 0 is written to dst. if (cond) { if (src1 t src2) 1 dst else 0 dst } nop
Execution
else
4-40
CMPLTDP
src1
src2
Output 0 0 0 0 0 0 0 0 0 0 1
UNORD 1 1 1 0 0 0 0 0 0 0 0
INVAL 1 1 1 0 0 0 0 0 0 0 0
E1
E2
src1_l src2_l
src1_h src2_h dst

.S
4-41
CMPLTDP
CMPLTDP Before instruction
.S1X
A1:A0,B3:B2,A4 2 cycles after instruction
A1:A0 4021 3333h B3:B2 c004 0000h A4 XXXX XXXXh
3333 3333h 0000 0000h
8.6 2.5
A1:A0 4021 3333h B3:B2 c004 0000h A4 0000 0000h
4021 3333h 0000 0000h false
8.6 2.5
4-42
CMPLTSP
CMPLTSP
Syntax
Single-Precision Floating-Point Compare for Less Than

CMPLTSP (.unit) src1, src2, dst .unit = .S1 or .S2
src1 src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 6 111010 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1
5
Description
This instruction compares src1 to src2. If src1 is less than src2, 1 is written to dst. Otherwise, 0 is written to dst. if (cond) { if (src1 t src2) 1 dst else 0 dst } nop
Execution
else
4-43
CMPLTSP
src1
src2
Output 0 0 0 0 0 0 0 0 0 0 1
UNORD 1 1 1 0 0 0 0 0 0 0 0
INVAL 1 1 1 0 0 0 0 0 0 0 0
E1
src1 src2 dst

.S
4-44
CMPLTSP
CMPGTSP .S1 A1,A2,A3 Before instruction A1 C020 0000h A2 4109 999Ah A3 XXXX XXXXh 2.5 8.6 1 cycle after instruction A1 C020 0000h A2 4109 999Ah A3 0000 0001h 2.5 8.6 true
4-45
DPINT
DPINT
Syntax
Convert Double-Precision Floating-Point Value to Integer

DPINT (.unit) src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... dp sint Unit .L1, .L2
src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 0001000 7 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
Description
The 64-bit double-precision value in src2 is converted to an integer and placed in dst. The operand is read in one cycle by using the src2 port for the 32 MSBs and the src1 port for the 32 LSBs. if (cond) else Notes: 1) If src2 is NaN, the maximum signed integer (7FFF FFFFh or 8000 0000h) is placed in dst and the INVAL bit is set. 2) If src2 is signed infinity or if overflow occurs, the maximum signed integer (7FFF FFFFh or 8000 0000h) is placed in dst and the INEX and OVER bits are set. Overflow occurs if src2 is greater than 231 1 or less than 231. 3) If src2 is denormalized, 0000 0000h is placed in dst and the INEX and DEN2 bits are set. 4) If rounding is performed, the INEX bit is set. int(src2) dst nop
Execution
Pipeline
E1
E2
E3
E4
src2_l src2_h dst

.L
4-46
DPINT
Instruction Type Delay Slots Functional Unit Latency Example 4-cycle 3 1
DPINT Before instruction
.L1
A1:A0,A4 4 cycles after instruction 8.6 A1:A0 4021 3333h A4 0000 0009h 3333 3333h 8.6 9
A1:A0 4021 3333h A4 XXXX XXXXh
3333 3333h
4-47
DPSP
DPSP
Convert Double-Precision Floating-Point Value to Single-Precision Floating-Point Value

DPSP (.unit) src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... dp sp Unit .L1, .L2
Syntax
src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 0001001 7 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
Description
The double-precision 64-bit value in src2 is converted to a single-precision value and placed in dst. The operand is read in one cycle by using the src2 port for the 32 MSBs and the src1 port for the 32 LSBs. if (cond) else sp(src2) dst nop
Execution
4-48
DPSP
Notes: 1) If rounding is performed, the INEX bit is set. 2) If src2 is SNaN, NaN_out is placed in dst and the INVAL and NAN2 bits are set. 3) If src2 is QNaN, NaN_out is placed in dst and the NAN2 bit is set. 4) If src2 is a signed denormalized number, signed 0 is placed in dst and the INEX and DEN2 bits are set. 5) If src2 is signed infinity, the result is signed infinity and the INFO bit is set. 6) If overflow occurs, the INEX and OVER bits are set and the results are set as follows (LFPN is the largest floating-point number):
7) If underflow occurs, the INEX and UNDER bits are set and the results are set as follows (SPFN is the smallest floating-point number):
4-49
DPSP
Pipeline
E1
E2
E3
E4
src2_l src2_h dst

.L
4-cycle 3 1
DPSP Before instruction
.L1
A1:A0,A4 4 cycles after instruction 8.6 A1:A0 4021 3333h A4 4109 999Ah 4021 3333h 8.6 8.6
3333 3333h
4-50
DPTRUNC
DPTRUNC
Convert Double-Precision Floating-Point Value to Integer With Truncation

DPTRUNC (.unit) src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... dp sint Unit .L1, .L2
Syntax
src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 0000001 7 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
Description
The 64-bit double-precision value in src2 is converted to an integer and placed in dst. This instruction operates like DPINT except that the rounding modes in the FADCR are ignored; round toward zero (truncate) is always used. The 64-bit operand is read in one cycle by using the src2 port for the 32 MSBs and the src1 port for the 32 LSBs. if (cond) else int(src2) dst nop
Execution
4-51
DPTRUNC
Notes: 1) If src2 is NaN, the maximum signed integer (7FFF FFFFh or 8000 0000h) is placed in dst and the INVAL bit is set. 2) If src2 is signed infinity or if overflow occurs, the maximum signed integer (7FFF FFFFh or 8000 0000h) is placed in dst and the INEX and OVER bits are set. Overflow occurs if src2 is greater than 231 1 or less than 231. 3) If src2 is denormalized, 0000 0000h is placed in dst and the INEX and DEN2 bits are set. 4) If rounding is performed, the INEX bit is set. Pipeline
Pipeline Stage Read Written Unit in use .L
E1
E2
E3
E4
src2_l src2_h dst
4-cycle 3 1
DPTRUNC Before instruction
.L1
A1:A0,A4 4 cycles after instruction 8.6 A1:A0 4021 3333h A4 0000 0008h 3333 3333h 8.6 8
3333 3333h
4-52
INTDP(U)
INTDP(U)
Syntax
Convert Integer to Double-Precision Floating-Point Value

INTDP (.unit) src2, dst or INTDPU (.unit) src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... xsint dp xuint dp Unit .L1, .L2 .L1, .L2 Opfield 0111001 0111011
src2 dst src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
op
7
The integer value in src2 is converted to a double-precision value and placed in dst. if (cond) else dp(src2) dst nop
You cannot set configuration bits with this instruction. Pipeline

Pipeline Stage Read Written Unit in use .L E1 E2 E3 E4 E5
src2 dst_l dst_h
If dst is used as the source for the ADDDP, CMPEQDP, CMPLTDP, CMPGTDP, MPYDP, or SUBDP instruction, the number of delay slots can be reduced by one, because these instructions read the lower word of the DP source one cycle before the upper word of the DP source. Instruction Type Delay Slots Functional Unit Latency INTDP 4 1
4-53
INTDP(U)
Example 1
INTDP
.L1x B4,A1:A0 5 cycles after instruction B4 1965 1127h A1:A0 41B9 6511h 426053927 2700 0000h 4.2605393 E08
Before instruction B4 1965 1127h A1:A0 XXXX XXXXh 426053927 XXXX XXXXh
Example 2
INTDPU
.L1 A4,A1:A0 5 cycles after instruction A4 FFFF FFDEh A1:A0 41EF FFFFh 4294967262 FBC0 0000h 4.2949673 E09
Before instruction A4 FFFF FFDEh A1:A0 XXXX XXXXh 4294967262 XXXX XXXXh
4-54
INTSP(U)
INTSP(U)
Syntax
Convert Integer to Single-Precision Floating-Point Value

INTSP (.unit) src2, dst or INTSPU (.unit) src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... xsint sp xuint sp Unit .L1, .L2 .L1, .L2 Opfield 1001010 1001001
src2 dst src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
op
7
Description
The integer value in src2 is converted to single-precision value and placed in dst. if (cond) else sp(src2) dst nop
Execution
The only configuration bit that can be set is the INEX bit and only if the mantissa is rounded. Pipeline
Pipeline Stage Read Written Unit in use .L
E1
E2
E3
E4
src2 dst
Instruction Type Delay Slots Functional Unit Latency
4-cycle 3 1
4-55
INTSP(U)
Example 1
INTSP .L1 A1,A2 Before instruction A1 1965 1127h A2 XXXX XXXXh 426053927 4 cycles after instruction A1 1965 1127h A2 4DCB 2889h 426053927 4.2605393 E08
Example 2
INTSPU .L1X B1,A2 Before instruction B1 FFFF FFDEh A2 XXXX XXXXh 4294967262 4 cycles after instruction B1 C020 0000h A2 4F80 0000h 4294967262 4.2949673 E09
4-56
LDDW
LDDW
Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset
LDDW (.unit) *+baseR[offsetR/ucst5], dst .unit = .D1 or .D2
Syntax
Opcode
31 29 28 27 23 22 18 17 13 12 9 8 7 y 6 4 3 0 2 1 1 0
creg
3
dst
5
baseR
5
offsetR/ucst5
5
mode
4
ld/st
3
Description
This instruction loads a doubleword to a pair of general-purpose registers (dst). Table 410 describes the addressing generator options. The memory address is formed from a base address register (baseR) and an optional offset that is either a register (offsetR) or a 5-bit unsigned constant (ucst5).
offsetR and baseR must be in the same register file and on the same side as the .D unit used. The y bit in the opcode determines the .D unit and the register file used: y = 0 selects the .D1 unit and the baseR and offsetR from the A register file, and y = 1 selects the .D2 unit and baseR and offsetR from the B register file. The s bit determines the register file into which the dst is loaded: s = 0 indicates that dst is in the A register file, and s = 1 indicates that dst is in the B register file. The r bit has a value of 1 for the LDDW instruction and a value of 0 for all other load and store instructions. The dst field must always be an even value because LDDW loads register pairs. Therefore, bit 23 is always zero. Furthermore, the value of the ld/st field is110.
The bracketed offsetR/ucst5 is scaled by a left-shift of 3 to correctly represent doublewords. After scaling, offsetR/ucst5 is added to or subtracted from baseR. For the preincrement, predecrement, positive offset, and negative offset address generator options, the result of the calculation is the address to be accessed in memory. For postincrement or postdecrement addressing, the shifted value of baseR before the addition or subtraction is the address to be accessed in memory. Increments and decrements default to 1 and offsets default to 0 when no bracketed register, bracketed constant, or constant enclosed in parentheses is specified. Square brackets, [ ], indicate that ucst5 is left shifted by 3. Parentheses, ( ), indicate that ucst5 is not left shifted. In other words, parentheses indicate a byte offset rather than a doubleword offset. You must type either brackets or parathesis around the specified offset if you use the optional offset parameter.
4-57
LDDW
The addressing arithmetic that performs the additions and subtractions defaults to linear mode. However, for A4A7 and for B4B7, the mode can be changed to circular mode by writing the appropriate value to the AMR (see section 2.6.2 on page 2-14). The destination register pair must consist of a consecutive even and odd register pair from the same register file. The instruction can be used to load a double-precision floating-point value (64 bits), a pair of single-precision floating-point words (32 bits), or a pair of 32-bit integers. The least significant 32 bits are loaded into the even register and the most significant 32 bits (containing the sign bit and exponent) are loaded into the next register (which is always the odd register). The register pair syntax places the odd register first, followed by a colon, then the even register (that is, A1:A0, B1:B0, A3:A2, B3:B2, etc.). All 64 bits of the double-precision floating point value are stored in big- or littleendian byte order, depending on the mode selected. When LDDW is used to load two 32-bit single-precision floating-point values or two 32-bit integer values, the order is dependent on the endian mode used. In little-endian mode, the first 32-bit word in memory is loaded into the even register. In big-endian mode, the first 32-bit word in memory is loaded into the odd register. Regardless of the endian mode, the double word address must be on a doubleword boundary (the three LSBs are zero). Table 410 summarizes the address generation options supported.

4-58
LDDW
mem dst nop

E1 baseR offsetR baseR .D E2 E3 E4 E5
dst
Instruction Type Delay Slots Functional Unit Latency Example 1
Load 4 1
LDDW .D2 Before instruction
*+B10[1],A1:A0 5 cycles after instruction A1:A0 4021 3333h 16 B10 0000 0010h mem 0x18 3333 3333h 4021 3333h 3333 3333h 8.6 16 8.6
A1:A0 XXXX XXXXh B10 0000 0010h mem 0x18 3333 3333h
XXXX XXXXh
4021 3333h
8.6
Little-endian mode
Example 2
LDDW .D1 Before instruction
*++A10[1],A1:A0 1 cycle after instruction A1:A0 XXXX XXXXh 16 A10 0000 0018h mem 0x18 4021 3333h 3333 3333h XXXX XXXXh 24 8.6
A1:A0 XXXX XXXXh A10 0000 0010h mem 0x18 4021 3333h
XXXX XXXXh
3333 3333h
8.6
5 cycles after instruction A1:A0 4021 3333h A10 0000 0018h mem 0x18 4021 3333h 3333 3333h 3333 3333h 8.6 24 8.6
Big-endian mode
4-59
MPYDP
MPYDP
Syntax
Double-Precision Floating-Point Multiply

MPYDP (.unit) src1, src2, dst .unit = .M1 or .M2
Opcode map field used... For operand type... dp dp dp Unit .M1, .M2
src1 src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 7 01110 5 6 0 5 0 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1
5
The src1 operand is multiplied by the src2 operand. The result is placed in dst. if (cond) else Notes: 1) If one source is SNaN or QNaN, the result is a signed NaN_out. If either source is SNaN, the INVAL bit is set also. The sign of NaN_out is the exclusive-or of the input signs. 2) Signed infinity multiplied by signed infinity or a normalized number (other than signed 0) returns signed infinity. Signed infinity multiplied by signed 0 returns a signed NaN_out and sets the INVAL bit. 3) If one or both sources are signed 0, the result is signed 0 unless the other source is NaN or signed infinity, in which case the result is signed NaN_out. 4) If signed 0 is multiplied by signed infinity, the result is signed NaN_out and the INVAL bit is set. 5) A denormalized source is treated as signed 0 and the DENn bit is set. The INEX bit is set except when the other source is signed infinity, signed NaN, or signed 0. Therefore, a signed infinity multiplied by a denormalized number gives a signed NaN_out and sets the INVAL bit. 6) If rounding is performed, the INEX bit is set.
src1 src2 dst nop
4-60
MPYDP
Pipeline
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
src1_l src1_l src1_h src1_h src2_l src2_h src2_l src2_h dst_l

.M .M .M .M
dst_h
If dst is used as the source for the ADDDP, CMPEQDP, CMPLTDP, CMPGTDP, MPYDP, or SUBDP instruction, the number of delay slots can be reduced by one, because these instructions read the lower word of the DP source one cycle before the upper word of the DP source. Instruction Type Delay Slots Functional Unit Latency Example MPYDP 9 4
MPYDP .M1 Before instruction
A1:A0,A3:A2,A5:A4 10 cycles after instruction 8.6 2.5 A1:A0 4021 3333h A3:A2 C004 0000h A5:A4 C035 8000h 4021 3333h 0000 0000h 0000 0000h 8.6 2.5 21.5
A1:A0 4021 3333h A3:A2 C004 0000h A5:A4 XXXX XXXXh
3333 3333h 0000 0000 XXXX XXXXh
4-61
MPYI
MPYI
Syntax
32-Bit Integer Multiply Result Is Lower 32 Bits

MPYI (.unit) src1, src2, dst .unit = .M1 or .M2
Opcode map field used... For operand type... sint xsint sint cst5 xsint sint Unit .M1, .M2 Opfield 00100
.M1, .M2
00110
Opcode
31 29 28 27 23 22 18 17 13 12 11 7 6 0 5 0 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
5
Description
The src1 operand is multiplied by the src2 operand. The lower 32 bits of the result are placed in dst. if (cond) else
Pipeline Stage Read Written Unit in use .M .M .M .M
Execution Pipeline
lsb32(src1 src2) dst nop
E1
E2
E3
E4
E5
E6
E7
E8
E9
src1 src2
src1 src2
src1 src2
src1 src2 dst
MPYI 8 4
4-62
MPYI
Example
MPYI
.M1X Before instruction
A1,B2,A3 9 cycles after instruction A1 0034 5678h B2 0011 2765h A3 CBCA 6558h 3430008 1124197 875928232
A1 0034 5678h B2 0011 2765h A3 XXXX XXXXh
3430008 1124197
4-63
MPYID
MPYID
Syntax
32-Bit Integer Multiply Result Is 64 Bits

MPYID (.unit) src1, src2, dst .unit = .M1 or .M2
Opcode map field used... For operand type... sint xsint sdint cst5 xsint sdint Unit .M1, .M2 Opfield 01000
.M1, .M2
01100
Opcode
31 29 28 27 23 22 18 17 13 12 11 7 6 0 5 0 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1/cst
5
op
5
Description
The src1 operand is multiplied by the src2 operand. The 64-bit result is placed in the dst register pair. if (cond) else lsb32(src1 src2) dst_l msb32(src1 src2) dst_h nop
Execution
Pipeline
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
src1 src2
src1 src2
src1 src2
src1 src2 dst_l dst_h
.M
.M
.M
.M
MPYID 9 (8 if dst_l is src of next instruction) 4
4-64
MPYID
Example
MPYID .M1 Before instruction
A1,A2,A5:A4 10 cycles after instruction A1 0034 5678h A2 0011 2765h A5:A4 0000 0381h 3430008 1124197 CBCA 6558h 3856004703576
A1 0034 5678h A2 0011 2765h A5:A4 XXXX XXXXh
3430008 1124197 XXXX XXXXh
4-65
MPYSP
MPYSP
Syntax
Single-Precision Floating-Point Multiply

MPYSP (.unit) src1, src2, dst .unit = .M1 or .M2
Opcode map field used... For operand type... sp xsp sp Unit .M1, .M2
src1 src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 7 11100 5 6 0 5 0 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1
5
The src1 operand is multiplied by the src2 operand. The result is placed in dst. if (cond) else Notes: 1) If one source is SNaN or QNaN, the result is a signed NaN_out. If either source is SNaN, the INVAL bit is set also. The sign of NaN_out is the exclusive-or of the input signs. 2) Signed infinity multiplied by signed infinity or a normalized number (other than signed 0) returns signed infinity. Signed infinity multiplied by signed 0 returns a signed NaN_out and sets the INVAL bit. 3) If one or both sources are signed 0, the result is signed 0 unless the other source is NaN or signed infinity, in which case the result is signed NaN_out. 4) If signed 0 is multiplied by signed infinity, the result is signed NaN_out and the INVAL bit is set. 5) A denormalized source is treated as signed 0 and the DENn bit is set. The INEX bit is set except when the other source is signed infinity, signed NaN, or signed 0. Therefore, a signed infinity multiplied by a denormalized number gives a signed NaN_out and sets the INVAL bit. 6) If rounding is performed, the INEX bit is set.
src1 src2 dst nop
4-66
MPYSP
Pipeline
E1
E2
E3
E4
src1 src2 dst

.M
If dst is used as the source for the ADDDP, CMPEQDP, CMPLTDP, CMPGTDP, MPYDP, or SUBDP instruction, the number of delay slots can be reduced by one, because these instructions read the lower word of the DP source one cycle before the upper word of the DP source. Instruction Type Delay Slots Functional Unit Latency Example 4-cycle 3 1
MPYSP .M1X A1,B2,A3 Before instruction A1 C020 0000h B2 4109 999Ah A3 XXXX XXXXh 2.5 8.6 4 cycles after instruction A1 C020 0000h B2 4109 999Ah A3 C1AC 0000h 2.5 8.6 21.5
4-67
RCPDP
RCPDP
Syntax
Double-Precision Floating-Point Reciprocal Approximation

RCPDP (.unit) src2, dst .unit = .S1 or .S2
src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 6 101101 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
rsv
5
Description
The 64-bit double-precision floating-point reciprocal approximation value of src2 is placed in dst. The operand is read in one cycle by using the src1 port for the 32 LSBs and the src2 port for the 32 MSBs. The RCPDP instruction provides the correct exponent, and the mantissa is accurate to the eighth binary position (therefore, mantissa error is less than 28). This estimate can be used as a seed value for an algorithm to compute the reciprocal to greater accuracy. The Newton-Rhapson algorithm can further extend the mantissas precision: x[n+1] = x[n](2 v*x[n]) where v = the number whose reciprocal is to be found. x[0], the seed value for the algorithm, is given by RCPDP. For each iteration, the accuracy doubles. Thus, with one iteration, accuracy is 16 bits in the mantissa; with the second iteration, the accuracy is 32 bits; with the third iteration, the accuracy is the full 52 bits.
Execution
if (cond) else
rcp(src2) dst nop
4-68
RCPDP
Notes: 1) If src2 is SNaN, NaN_out is placed in dst and the INVAL and NAN2 bits are set. 2) If src2 is QNaN, NaN_out is placed in dst and the NAN2 bit is set. 3) If src2 is a signed denormalized number, signed infinity is placed in dst and the DIV0, INFO, OVER, INEX, and DEN2 bits are set. 4) If src2 is signed 0, signed infinity is placed in dst and the DIV0 and INFO bits are set. 5) If src2 is signed infinity, signed 0 is placed in dst. 6) If the result underflows, signed 0 is placed in dst and the INEX and UNDER bits are set. Underflow occurs when 21022 t src2 t infinity. Pipeline
E1
E2
src2_l src2_h dst_l

.S
dst_h
RCPDP Before instruction
.S1
A1:A0,A3:A2 2 cycles after instruction A1:A0 4010 0000h A3:A2 3FD0 0000h 0000 0000h 0000 0000h 4.00 0.25
A1:A0 4010 0000h A3:A2 XXXX XXXXh
4-69
RCPSP
RCPSP
Syntax
Single-Precision Floating-Point Reciprocal Approximation

RCPSP (.unit) src2, dst .unit = .S1 or .S2
src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 111101 6 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
Description
The single-precision floating-point reciprocal approximation value of src2 is placed in dst. The RCPSP instruction provides the correct exponent, and the mantissa is accurate to the eighth binary position (therefore, mantissa error is less than 28). This estimate can be used as a seed value for an algorithm to compute the reciprocal to greater accuracy. The Newton-Rhapson algorithm can further extend the mantissas precision: x[n+1] = x[n](2 v*x[n]) where v = the number whose reciprocal is to be found. x[0], the seed value for the algorithm, is given by RCPSP. For each iteration, the accuracy doubles. Thus, with one iteration, accuracy is 16 bits in the mantissa; with the second iteration, the accuracy is the full 23 bits.
Execution
if (cond) else
rcp(src2) dst nop
4-70
RCPSP
Notes: 1) If src2 is SNaN, NaN_out is placed in dst and the INVAL and NAN2 bits are set. 2) If src2 is QNaN, NaN_out is placed in dst and the NAN2 bit is set. 3) If src2 is a signed denormalized number, signed infinity is placed in dst and the DIV0, INFO, OVER, INEX, and DEN2 bits are set. 4) If src2 is signed 0, signed infinity is placed in dst and the DIV0 and INFO bits are set. 5) If src2 is signed infinity, signed 0 is placed in dst. 6) If the result underflows, signed 0 is placed in dst and the INEX and UNDER bits are set. Underflow occurs when 2126 t src2 t infinity. Pipeline
E1
src2 dst
.S
Single-cycle 0 1
RCPSP .S1
A1,A2 1 cycle after instruction A1 4080 0000h A2 3E80 0000h 4.0 0.25
Before instruction A1 4080 0000h A2 XXXX XXXXh 4.0
4-71
RSQRDP
RSQRDP
Syntax
Double-Precision Floating-Point Square-Root Reciprocal Approximation

RSQRDP (.unit) src2, dst .unit = .S1 or .S2
src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 6 101110 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
rsv
5
Description
The 64-bit double-precision floating-point square-root reciprocal approximation value of src2 is placed in dst. The operand is read in one cycle by using the src1 port for the 32 LSBs and the src2 port for the 32 MSBs. The RSQRDP instruction provides the correct exponent, and the mantissa is accurate to the eighth binary position (therefore, mantissa error is less than 28). This estimate can be used as a seed value for an algorithm to compute the reciprocal square root to greater accuracy. The Newton-Rhapson algorithm can further extend the mantissas precision: x[n+1] = x[n](1.5 (v/2)*x[n]*x[n]) where v = the number whose reciprocal square root is to be found. x[0], the seed value for the algorithm is given by RSQRDP. For each iteration the accuracy doubles. Thus, with one iteration, the accuracy is 16 bits in the mantissa; with the second iteration, the accuracy is 32 bits; with the third iteration, the accuracy is the full 52 bits.
Execution
if (cond) else
sqrcp(src2) dst nop
4-72
RSQRDP
Notes: 1) If src2 is SNaN, NaN_out is placed in dst and the INVAL and NAN2 bits are set. 2) If src2 is QNaN, NaN_out is placed in dst and the NAN2 bit is set. 3) If src2 is a negative, nonzero, nondenormalized number, NaN_out is placed in dst and the INVAL bit is set. 4) If src2 is a signed denormalized number, signed infinity is placed in dst and the DIV0, INEX, and DEN2 bits are set. 5) If src2 is signed 0, signed infinity is placed in dst and the DIV0 and INFO bits are set. The Newton-Rhapson approximation cannot be used to calculate the square root of 0 because infinity multiplied by 0 is invalid. 6) If src2 is positive infinity, positive 0 is placed in dst. Pipeline
E1
E2
src2_l src2_h dst_l

.S
dst_h
If dst is used as the source for the ADDDP, CMPEQDP, CMPLTDP, CMPGTDP, MPYDP, or SUBDP instruction, the number of delay slots can be reduced by one, because these instructions read the lower word of the DP source one cycle before the upper word of the DP source. Instruction Type Delay Slots Functional Unit Latency 2-cycle DP 1 1
4-73
RSQRDP
Example
RCPDP Before instruction
.S1
A1:A0,A3:A2 2 cycles after instruction 4.0 A1:A0 4010 0000h A3:A2 3FE0 0000h 0000 0000h 0000 0000h 4.0 0.5
A1:A0 4010 0000h A3:A2 XXXX XXXXh
4-74
RSQRSP
RSQRSP
Syntax
Single-Precision Floating-Point Square-Root Reciprocal Approximation

RSQRSP (.unit) src2, dst .unit = .S1 or .S2
src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 111110 6 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
Description
The single-precision floating-point square-root reciprocal approximation value of src2 is placed in dst. The RSQRSP instruction provides the correct exponent, and the mantissa is accurate to the eighth binary position (therefore, mantissa error is less than 28). This estimate can be used as a seed value for an algorithm to compute the reciprocal square root to greater accuracy. The Newton-Rhapson algorithm can further extend the mantissas precision: x[n+1] = x[n](1.5 (v/2)*x[n]*x[n]) where v = the number whose reciprocal square root is to be found. x[0], the seed value for the algorithm, is given by RSQRSP. For each iteration, the accuracy doubles. Thus, with one iteration, accuracy is 16 bits in the mantissa; with the second iteration, the accuracy is the full 23 bits.
Execution
if (cond) else
sqrcp(src2) dst nop
4-75
RSQRSP
Notes: 1) If src2 is SNaN, NaN_out is placed in dst and the INVAL and NAN2 bits are set. 2) If src2 is QNaN, NaN_out is placed in dst and the NAN2 bit is set. 3) If src2 is a negative, nonzero, nondenormalized number, NaN_out is placed in dst and the INVAL bit is set. 4) If src2 is a signed denormalized number, signed infinity is placed in dst and the DIV0, INEX, and DEN2 bits are set. 5) If src2 is signed 0, signed infinity is placed in dst and the DIV0 and INFO bits are set. The Newton-Rhapson approximation cannot be used to calculate the square root of 0 because infinity multiplied by 0 is invalid. 6) If src2 is positive infinity, positive 0 is placed in dst. Pipeline
E1
src2 dst
.S
Single-cycle 0 1
RSQRSP .S1 A1,A2 Before instruction A1 4080 0000h A2 XXXX XXXXh 4.0 1 cycle after instruction A1 4080 0000h A2 3F00 0000h 4.0 0.5
4-76
RSQRSP
Example 2
RSQRSP .S2X A1,B2 Before instruction A1 4109 999Ah B2 XXXX XXXXh 8.6 1 cycle after instruction A1 4109 999Ah B2 3EAE 8000h 8.6 0.34082031
4-77
SPDP
SPDP
Convert Single-Precision Floating-Point Value to a Double-Precision Floating-Point Value

SPDP (.unit) src2, dst .unit = .S1 or .S2
Opcode map field used... For operand type... xsp dp Unit .S1, .S2
Syntax
src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 000010 6 6 5 1 4 0 3 0 2 0 1 0
creg
3
dst
5
src2
5
Description
The single-precision value in src2 is converted to a double-precision value and placed in dst. if (cond) else Notes: 1) If src2 is SNaN, NaN_out is placed in dst and the INVAL and NAN2 bits are set. 2) If src2 is QNaN, NaN_out is placed in dst and the NAN2 bit is set. 3) If src2 is a signed denormalized number, signed 0 is placed in dst and the INEX and DEN2 bits are set. 4) If src2 is signed infinity, INFO bit is set. 5) No overflow or underflow can occur. dp(src2) dst nop
Execution
Pipeline
E1
E2
src2 dst_l
.S
dst_h
4-78
SPDP
SPDP Before instruction
.S1X
B2,A1:A0 2 cycles after instruction
B2 4109 999Ah A1:A0 XXXX XXXXh XXXX XXXXh
8.6
B2 4109 999Ah A1:A0 4021 3333h 4000 0000h
8.6 8.6
4-79
SPINT
SPINT
Syntax
Convert Single-Precision Floating-Point Value to Integer

SPINT (.unit) src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... xsp sint Unit .L1, .L2
src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 0001010 7 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
The single-precision value in src2 is converted to an integer and placed in dst. if (cond) else Notes: 1) If src2 is NaN, the maximum signed integer (7FFF FFFFh or 8000 0000h) is placed in dst and the INVAL bit is set. 2) If src2 is signed infinity or if overflow occurs, the maximum signed integer (7FFF FFFFh or 8000 0000h) is placed in dst and the INEX and OVER bits are set. Overflow occurs if src2 is greater than 231 1 or less than 231. 3) If src2 is denormalized, 0000 0000h is placed in dst and INEX and DEN2 bits are set. 4) If rounding is performed, the INEX bit is set. int(src2) dst nop
Pipeline
E1
E2
E3
E4
src2 dst
.L

4-80
4-cycle 3
SPINT
1
Functional Unit Latency Example
SPINT .L1 A1,A2 Before instruction A1 4109 9999Ah 8.6 A2 XXXX XXXXh 4 cycles after instruction A1 4109 999Ah A2 0000 0009h 8.6 9
4-81
SPTRUNC
SPTRUNC
Syntax
Convert Single-Precision Floating-Point Value to Integer With Truncation

SPTRUNC (.unit) src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... xsp sint Unit .L1, .L2
src2 dst
Opcode
31 29 28 27 23 22 18 17 13 12 11 00000 5 x 0001011 7 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
Description
The single-precision value in src2 is converted to an integer and placed in dst. This instruction operates like SPINT except that the rounding modes in the FADCR are ignored, and round toward zero (truncate) is always used. if (cond) else Notes: 1) If src2 is NaN, the maximum signed integer (7FFF FFFFh or 8000 0000h) is placed in dst and the INVAL bit is set. 2) If src2 is signed infinity or if overflow occurs, the maximum signed integer (7FFF FFFFh or 8000 0000h) is placed in dst and the INEX and OVER bits are set. Overflow occurs if src2 is greater than 231 1 or less than 231. 3) If src2 is denormalized, 0000 0000h is placed in dst and INEX and DEN2 bits are set. 4) If rounding is performed, the INEX bit is set. int(src2) dst nop
Execution
Pipeline
E1
E2
E3
E4
src2 dst
.L
4-82
SPTRUNC
Instruction Type Delay Slots Functional Unit Latency Example 4-cycle 3 1
SPTRUNC .L1X B1,A2 Before instruction B1 4109 9999Ah 8.6 A2 XXXX XXXXh 4 cycles after instruction B1 4109 999Ah A2 0000 0008h 8.6 8
4-83
SUBDP
SUBDP
Syntax
Double-Precision Floating-Point Subtract

SUBDP (.unit) src1, src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... dp xdp dp xdp dp dp Unit .L1, .L2 Opfield 0011001
.L1, .L2
0011101
Opcode
31 29 28 27 23 22 18 17 13 12 11 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
src1
5
op
7
Execution
if (cond) else
src1 src2 dst nop
4-84
SUBDP
Notes: 1) If rounding is performed, the INEX bit is set. 2) If one source is SNaN or QNaN, the result is NaN_out. If either source is SNaN, the INVAL bit is set also. 3) If both sources are +infinity or infinity, the result is NaN_out and the INVAL bit is set. 4) If one source is signed infinity and the other source is anything except NaN or signed infinity of the same sign, the result is signed infinity and the INFO bit is set. 5) If overflow occurs, the INEX and OVER bits are set and the results are set as follows (LFPN is the largest floating-point number):
7) If the sources are equal numbers of the same sign, the result is +0 unless the rounding mode is infinity, in which case the result is 0. 8) If the sources are both 0 with opposite signs or both denormalized with opposite signs, the sign of the result is the same as the sign of src1. 9) A signed denormalized source is treated as a signed 0 and the DENn bit is set. If the other source is not NaN or signed infinity, the INEX bit is also set.
4-85
SUBDP
Pipeline
E1
E2
E3
E4
E5
E6
E7
src1_l src2_l
.L
.L
If dst is used as the source for the ADDDP, CMPEQDP, CMPLTDP, CMPGTDP, MPYDP, or SUBDP instruction, the number of delay slots can be reduced by one, because these instructions read the lower word of the DP source one cycle before the upper word of the DP source. Instruction Type Delay Slots Functional Unit Latency Example ADDDP/SUBDP 6 2
SUBDP .L1X B1:B0,A3:A2,A5:A4 Before instruction 7 cycles after instruction 8.6 2.5 B1:B0 4021 3333h A3:A2 C004 0000h A5:A4 4026 3333h 3333 3333h 0000 0000h 3333 3333h 8.6 2.5 11.1
B1:B0 4021 3333h A3:A2 C004 0000h A5:A4 XXXX XXXXh
3333 3333h 0000 0000h XXXX XXXXh
4-86
SUBSP
SUBSP
Syntax
Single-Precision Floating-Point Subtract

SUBSP (.unit) src1, src2, dst .unit = .L1 or .L2
Opcode map field used... For operand type... sp xsp sp xsp sp sp Unit .L1, .L2 Opfield 0010001
.L1, .L2
0010101
Opcode
31 29 28 27 23 22 18 17 13 12 11 5 4 1 3 1 2 0 1 0
creg
3
dst
5
src2
5
src1
5
op
7
Execution
if (cond) else
src1 src2 dst nop
4-87
SUBSP
Notes: 1) If rounding is performed, the INEX bit is set. 2) If one source is SNaN or QNaN, the result is NaN_out. If either source is SNaN, the INVAL bit is set also. 3) If both sources are +infinity or infinity, the result is NaN_out and the INVAL bit is set. 4) If one source is signed infinity and the other source is anything except NaN or signed infinity of the same sign, the result is signed infinity and the INFO bit is set. 5) If overflow occurs, the INEX and OVER bits are set and the results are set as follows (LFPN is the largest floating-point number):
7) If the sources are equal numbers of the same sign, the result is +0 unless the rounding mode is infinity, in which case the result is 0. 8) If the sources are both 0 with opposite signs or both denormalized with opposite signs, the sign of the result is the same as the sign of src1. 9) A signed denormalized source is treated as a signed 0 and the DENn bit is set. If the other source is not NaN or signed infinity, the INEX bit is also set.
4-88
SUBSP
Pipeline
E1
E2
E3
E4
src1 src2 dst

.L
4-cycle 3 1
SUBSP .L1X A2,B1,A3 Before instruction A2 4109 999Ah B1 C020 0000h A3 XXXX XXXXh 4 cycles after instruction A2 4109 999Ah B1 C020 0000h A3 4131 999Ah 8.6 2.5 11.1
4-89
Chapter 5
TMS320C64x Fixed-Point Instruction Set

The TMS320C64x fixed-point DSP uses all of the instructions available to the TMS320C62x, but it also uses other instructions that are specific to the C64x. These specific instructions include 8-bit and 16-bit extensions, nonaligned word loads and stores, data packing/unpacking operations. This chapter describes these C64x-specific instructions. Instructions that are common to both the C62x and C64x are described in Chapter 3.
Topic
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8
Page
Instruction Operation and Execution Notations . . . . . . . . . . . . . . . . . . 5-2 Mapping Between Instructions and Functional Units . . . . . . . . . . . . . 5-5 TMS320C64x Opcode Map Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Delay Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Conditional Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Resource Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Individual Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
5-1

Table 51 explains the symbols used in the new instruction descriptions.
Table 51. New Instruction Operation and Execution Notations

Symbol abs(x) and bi bit_count bit_reverse byte0 byte1 byte2 byte3 bv2 bv4 cond creg cstn Meaning Absolute value of x Bitwise AND Select bit i of source/destination b Count the number of bits that are 1 in a specified byte Reverse the order of bits in a 32-bit register 8-bit value in the least significant byte position in 32-bit register (bits 0-7) 8 -bit value in the next to least significant byte position in 32-bit register (bits 8-15) 8-bit value in the next to most signficant byte position in 32-bit register (bits 16-23) 8-bit value in the most signficant byte position in 32-bit register (bits 24-31) Bit Vector of two flags for s2 or u2 data type Bit Vector of four flags for s4 or u4 data type Check for either creg equal to 0 or creg not equal to 0 3-bit field specifying a conditional register n-bit constant field (for example, cst5)
dst_h or dst_o msb32 of dst (placed in odd-numbered register of 64-bit register pair) dst_l or dst_e
dws4 dwu4 gmpy i2 i4 int lsbn or LSBn lsb32 of dst (placed in even-numbered register of a 64-bit register pair) Four packed signed 16-bit integers in a 64-bit register pair Four packed unsigned 16-bit integers in a 64-bit register pair Galois Field Multiply Two packed 16-bit integers in a single 32-bit register Four packed 8-bit integers in a single 32-bit register 32-bit integer value n least significant bits (for example, lsb16)
5-2
Table 51. New Instruction Operation and Execution Notations (Continued)

Symbol msbn or MSBn nop or R ROTL sat sbyte0 sbyte1 sbyte2 sbyte3 scstn se sint slsb16 smsb16 s2 s4 sllong ubyte0 ubyte1 ubyte2 ubyte3 ucstn uint Meaning n most significant bits (for example, msb16) No operation Bitwise OR Any general-purpose register Rotate left Saturate Signed 8-bit value in the least significant byte position in 32-bit register (bits 07) Signed 8-bit value in the next to least significant byte position in 32-bit register (bits 815) Signed 8-bit value in the next to most significant byte position in 32-bit register (bits 1623) Signed 8-bit value in the most significant byte position in 32-bit register (bits 2431) Signed n-bit constant field (for example, scst7) Sign-extend Signed 32-bit integer value Signed 16-bit integer value in lower half of 32-bit register Signed 16-bit integer value in upper half of 32-bit register Two packed signed 16-bit integers in a single 32-bit register Four packed signed 8-bit integers in a single 32-bit register Signed 64-bit integer value Unsigned 8-bit value in the least significant byte position in 32-bit register (bits 07) Unsigned 8-bit value in the next to least significant byte position in 32-bit register (bits 815) Unsigned 8-bit value in the next to most significant byte position in 32-bit register (bits 1623) Unsigned 8-bit value in the most significant byte position in 32-bit register (bits 2431) n-bit unsigned constant field (for example, ucstn5) Unsigned 32-bit integer value
5-3
Table 51. New Instruction Operation and Execution Notations (Continued)

Symbol ullong ulsb16 umsb16 u2 u4 xsint xs2 xs4 xuint xu2 xu4 Meaning Unsigned 64-bit integer value Unsigned 16-bit integer value in lower half of 32-bit register Unsigned 16-bit integer value in upper half of 32-bit register Two packed unsigned 16-bit integers in a single 32-bit register Four packed unsigned 8-bit integers in a single 32-bit register Signed 32-bit integer value that can optionally use cross path Two packed signed 16-bit integers in a single 32-bit register that can optionally use cross path Four packed signed 8-bit integers in a single 32-bit register that can optionally use cross path Unsigned 32-bit integer value that can optionally use cross path Two packed unsigned 16-bit integers in a single 32-bit register that can optionally use cross path Four packed unsigned 8-bit integers in a single 32-bit register that can optionally use cross path Assignment Addition Increment by one Multiplication Subtraction Greater than Less than Shift left Shift right Greater than or equal to Less than or equal to Equal to Logical Inverse Logical And
+ ++ x > < << >> >= <= == ~ &
5-4

Table 52 shows the mapping between instructions and functional units. Table 53 shows the mapping between functional units and instructions.

.L unit ABS2 ADD2 ADD4 AND ANDN MAX2 MAXU4 MIN2 MINU4 MVK OR PACK2 PACKH2 PACKH4 PACKHL2 PACKL4 PACKLH2 SHLMB SHRMB SUB2 SUB4 SUBABS4 SWAP2 SWAP4 UNPKHU4 UNPKLU4 XOR .M unit AVG2 AVGU4 BITC4 BITR DEAL DOTP2 DOTPN2 DOTPNRSU2 DOTPNRUS2 DOTPRSU2 DOTPRUS2 DOTPSU4 DOTPUS4 DOTPU4 GMPY4 MPY2 MPYHI MPYIH MPYHIR MPYIHR MPYLI MPYIL MPYLIR MPYILR MPYSU4 MPYUS4 MPYU4 MVD ROTL SHFL SMPY2 SSHVL SSHVR XPND2 XPND4 .S unit ADD2 ADDKPC AND ANDN BDEC BNOP BPOS CMPEQ2 CMPEQ4 CMPGT2 CMPGTU4 CMPLT2 CMPLTU4 MVK OR PACK2 PACKH2 PACKHL2 PACKLH2 SADD2 SADDU4 SADDSU2 SADDUS2 SHLMB SHR2 SHRMB SHRU2 SPACK2 SPACKU4 SUB2 SWAP2 UNPKHU4 UNPKLU4 XOR .D unit ADD2 ADDAD AND ANDN LDDW LDNDW LDNW MVK OR STDW STNDW STNW SUB2 XOR
5-5

Instruction ABS2 ADD2Y ADD4 ADDAD ADDKPC ANDY ANDN AVG2 AVGU4 BDEC BITC4 BITR BNOP BNOP reg BPOS CMPEQ2 CMPEQ4 CMPGT2 CMPGTU4 CMPLT2 CMPLTU4 DEAL DOTP2 DOTPN2 DOTPNRSU2 DOTPNRUS2 DOTPRSU2 DOTPRUS2 DOTPSU4 .L unit .M unit .S unit .D unit
5-6

Instruction DOTPUS4 DOTPU4 GMPY4 LDDW LDNDW LDNW MAX2 MAXU4 MIN2 MINU4 MPY2 MPYHI MPYIH MPYHIR MPYIHR MPYLI MPYIL MPYLIR MPYILR MPYSU4 MPYUS4 MPYU4 MVD MVKY ORY PACK2 PACKH2 PACKH4 PACKHL2 .L unit .M unit .S unit .D unit
5-7

Instruction PACKL4 PACKLH2 ROTL SADD2 SADDSU2 SADDU4 SADDUS2 SHFL SHLMB SHR2 SHRMB SHRU2 SMPY2 SPACK2 SPACKU4 SSHVL SSHVR STDW STNDW STNW SUB2Y SUB4 SUBABS4 SWAP2 SWAP4 UNPKHU4 UNPKLU4 XORY 5-8 .L unit .M unit .S unit .D unit

Instruction XPND2 XPND4 .L unit .M unit .S unit .D unit
Note: Y indicates instructions that exist on C62x/C67x but are now also available on one or more additional functional units.
5-9
TMS320C64x Opcode Map Symbols
5.3 TMS320C64x Opcode Map Symbols

Table 54 and the instruction descriptions in this chapter explain the field syntaxes and values.
Table 54. TMS320C64x Opcode Map Symbol Definitions

Symbol Meaning base address register 3-bit field specifying a conditional register constant constant a constant b destination MVK or MVKH bit load/store opfield addressing mode register offset opfield, field within opcode that specifies a unique instruction parallel execution LDDW bit reserved select side A or B for destination scaling mode bit source 2 source 1 n-bit unsigned constant field use cross path for src2 select .D1 or .D2 test for equality with zero or nonzero
baseR creg cst csta cstb dst h ld/st mode offsetR op p r rsv s sc src2 src1 ucstn
x y
5-10
Delay Slots
5.4 Delay Slots

The execution of the additional instructions can be defined in terms of delay slots. The number of delay slots is equivalent to the number of cycles required after the source operands are read for the result to be available for reading. For a single-cycle type instruction (such as CMPGT2), source operands read in cycle i produce a result that can be read in cycle i + 1. For a two-cycle instruction (such as AVGU4), source operands read in cycle i produce a result that can be read in cycle i + 2. For a four-cycle instruction (such as DOTP2), source operands read in cycle i produce a result that can be read in cycle i + 4. Table 55 shows the number of delay slots associated with each type of instruction. Delay slots are equivalent to an execution or result latency. All of the additional instructions have a functional unit latency of 1. This means that a new instruction can be started on the functional unit every cycle. Single-cycle throughput is another term for single-cycle functional unit latency.

Instruction Type NOP (no operation) Store Single cycle Two cycle Multiply (16x16) Four cycle Load Branch Delay Slots 0 0 0 1 1 3 4 5 Functional Unit Latency 1 1 1 1 1 1 1 1 i i i i i i i i i i+1 i+1 i+3 i, i + 4 i+5 Read Cycles Write Cycles Branch Taken
Cycle i is in the E1 pipeline phase. For loads, any address modification happens in cycle i. The loaded data is written into the register file in cycle i + 4. The branch to label, branch to IRP, and branch to NRP instructions do not read any general-purpose registers.
5-11
Conditional Operations
5.5 Conditional Operations

The C64x handles conditional operations in the same manner as the TMS320C62x/TMS320C67x. In addition, the C64x can use A0 as a conditional register as well as A1,A2, B0, B1 and B2. The creg field is encoded in the instruction opcode as shown in Table 56.
Table 56. Registers That Can Be Tested by Conditional Operations

Specified Conditional C diti l Register Unconditional Reserved{ B0 B1 B2 A1 A2 A0 Reserved
creg
Bit 31 0 0 0 0 0 1 1 1 1 30 0 0 0 1 1 0 0 1 1 29 0 0 1 0 1 0 1 0 x
z
28 0 1 z z z z z z x
This value is reserved for software breakpoints that are used for emulation purposes.
5-12
5.6 Resource Constraints

This section will cover the differences between the C62x and the C64x with respect to resource constraints. If no differences are cited, then the same constraints covered in Chapter 3, section 3.7 apply.
5.6.1
Constraints on Cross Paths (1X and 2X)

Units in one data path may read a single operand from the opposite data path by using a cross path (1X and 2X). The C62x/C67x architectures provided cross path access to the .L, .S and .M units. One functional unit per data path per execute packet may read an operand via a cross path on these architectures. The C64x adds data cross path access to the .D unit for arithmetic and logical operations. Also, multiple units in a given path may read an operand via the same cross path on the C64x, provided that each unit is reading the same operand. For example, the .S1 unit can read both its operands from the A register file; or it can read an operand from the B register file using the 1X cross path and the other from the A register file. The use of a cross path is denoted by an X following the functional unit name in the instruction syntax (as in S1X). The following execute packet is invalid because the 1X cross path is being used for two different B register operands:
MV .S1X B0, A0 ; \ Invalid. Instructions are using the 1X cross path ||MV .L1X B1, A1 ; / with different B registers
The following execute packet is valid because all uses of the 1X cross path are for the same B register operand, and all uses of the 2X cross path are for the same A register operand:
ADD .L1X A0,B1,A1 ; \ Instructions use the 1X with B1 || SUB .S1X A2,B1,A2 ; / 1X cross paths using B1 || AND .D1 A4,A1,A3 ; || MPY .M1 A6,A1,A4 ; || ADD .L2 B0,B4,B2 ; || SUB .S2X B4,A4,B3 ; / 2X cross paths using A4 || AND .D2X B5,A4,B4 ; / 2X cross paths using A4 || MPY .M2 B6,B4,B5 ;
As in the C62x core, when an operand comes from a register file opposite of the destination register, the x bit in the instruction field is set.
5-13
5.6.2
Cross Path Stalls

The C64x introduces a delay clock cycle whenever an instruction attempts to read a register via a cross path that was updated in the previous cycle. This is known as a cross path stall. This stall is inserted automatically by the hardware, no NOP instruction is needed. It should be noted that no stall is introduced if the register being read has data placed by a load instruction, or if an instruction reads a result one cycle after the result is generated. Here are some examples:
ADD .S1 A0, A0, A1; / Stall is introduced; A1 is ; ADD .S2X updated
1 cycle before it is used as a cross path
A1, B0, B1; \ source
ADD
.S1
A0, A0, A1 ; / No stall is introduced; A0 not updated ; 1 cycle before it is used as a cross
ADD
.S2X
A0, B0, B1 ; \ path source
LDW
.D1
*++A0[1], A1; / No stall is introduced; A1 is the load ; destination NOP 4 represents 4 instructions to
NOP ADD
4 .S2X
A1, B0, B1 ; \ be executed between the load and add.
LDW ADD
.D1 .S2X
*++A0[1], A1 ; / Stall is introduced; A0 is updated A0, B0, B1 ; 1 cycle before it is used as a cross ; \ path source .
This cross path stall does not occur on the C62x/C67x. However, all code written for the C62x/C67x that contains cross paths used in the manner above and that runs on the C64x will exhibit this behavior. The code will still run correctly but it will take more clock cycles. It is possible to avoid the cross path stall by scheduling an instruction that reads an operand via the cross path at least one cycle after the operand is updated. With appropriate scheduling, the C64x can provide one cross path operand per data path per cycle with no stalls. In many cases, the TMS320C6000 Optimizing C Compiler and Assembly Optimizer automatically perform this scheduling.
5.6.3
Constraints on Loads and Stores

The data address paths named DA1 and DA2 are each connected to the .D units in both data paths. Load/store instructions can use an address register
5-14
from one register file while loading to or storing from the other register file. Two load/store instructions using a destination/source from the same register file cannot be issued in the same execute packet. The address register must be on the same side as the .D unit used. The DA1 and DA2 resources and their associated data paths are specified as T1 and T2, respectively. T1 consists of the DA1 address path and the LD1a, LD1b, ST1a, and ST1b data paths. Similarly, T2 consists of the DA2 address path and the LD2a, LD2b, ST2a, and ST2b data paths. The T1 and T2 designations appear in functional unit fields for load and store instructions. The C64x can access words and double words at any byte boundary using non-aligned loads and stores. As a result, word and double word data does not need alignment to 32-bit or 64-bit boundaries. No other memory access may be used in parallel with a non-aligned memory access. The other .D unit can be used in parallel, as long as it is not performing a memory access. The following execute packet is invalid:
LDNW .D2T2 *B2[B12],B13 ; \ Two memory operations, || LDB .D1T1 *A2,A14 ; / one non-aligned

LDNW .D2T2 *B2[B12], A13; \ One non-aligned memory ; operation, ADD .D1x A12, B13, A14 ; one non-memory .D unit ; / operation
||
5.6.4
Constraints on Long (40-Bit) Data

Some of the ports for long and double word operands are shared between functional units. This creates constraints on when long or double word operations can be scheduled in a data path. The restrictions are different between the C64x, the C62x, and the C67x. These differences are summarized in Table 57.
5-15
Table 57. Constraint Differences Between C62x/C67x and C64x Registers

Situation Both .S and .L units on the same side use a long source. Both .S and .L units on the same side write a long result. A store reads the data to store from the same side that the .S unit reads a long source. A store (other than STDW) reads the data to store from the same side that the .L unit reads a long source. An STDW reads the data to store from the same side that the .L unit reads a long source. An LDDW writes back data (loaded from memory) to the same side that the .S unit writes a long result. An LDDW writes back data (loaded from memory) to the same side that the .L unit writes a long result.
Legend: Conflict = Conflict exists OK = No conflict exists N/A = Not Applicable; instruction not available to core
C62x Conflict Conflict Conflict Conflict N/A N/A N/A
C67x Conflict Conflict Conflict Conflict N/A Conflict Conflict
C64x OK OK Conflict OK Conflict Conflict OK
On the C62x and C67x, only one long result may be issued per register file in an execute packet. On the C64x, the .L, .S and .D units can operate independently, as long as the .D unit does loads of data smaller than double words. Up to two instructions with long results may be issued per side in an execute packet. Double word load instructions conflict with long results from the .S units. All stores conflict with a long source on the .S unit. Only double word stores conflict with a long source on the .L unit. The following execute packet is invalid on the C62x/C67x and the C64x cores, because the .D unit store on the T1 path conflicts with the long source on the .S1 unit:
ADD .S1 A1,A5:A4, A3:A2; \ Long source on .S unit and a / store on the T1 path of the .D unit
|| STW .D1T1 A8,*A9;
The following code sequence is invalid on the C64x and C67x cores. This example is not applicable to the C62x core because it uses the LDDW instruction that is not supported on the C62x core.
LDDW .D1T1 *A16,A11:A10 ; \ Double word load written to ; NOP 3 SHL 5-16 .S1 A8,A9,A7:A6 ; A11:A10 on .D1 conflicts after 3 cycles
; / with write to A7:A6 on .S1
The following code sequences are invalid on the C64x core. These examples are not applicable to the C62x and C67x cores, because the STDW instruction is not supported on the C62x or C67x cores.
ADD .L1 A1,A5:A4,A3:A2 || STDW .D1T1 A13:A12,*A16 ; \ Long source on .L1 conflicts ; with double word store on the ; / T1 path of .D1
SHL .S1 A5:A4,A1,A3:A2 ; \ Long source on .S1 conflicts || STDW .D1T1 A9:A8,*A19 ; with double word store on the ; / T1 path of .D1
The following code sequences are invalid on the C62x and C67x cores but valid on the C64x core:
ADD .L1 || SHL .S1 A1,A5:A4,A3:A2 A8,A9,A7:A6 ; \ Two long writes ; / on A register file
LDW NOP ADD || SHL
.D1T1 *A13,A11 3 .L1 A4,A1,A3:A2 .S1 A8,A2,A7:A6
; ; ; ;
\ / \ /
Word read on T1 path of .D1 doesnt conflict after 3 cycles with long write on .L1 unit and long write on .S1 unit
ADD .L1 A1,A5:A4,A3:A2 ; \ Long source operand on .L1 || STW .D1T1 A8,*A9 ; doesnt conflict with store ; / word on the T1 path of .D1
The following execute packets are valid on all cores:

ADD .L1 || SHL .S2 A1,A5:A4,A3:A2 ; \ One long write for B8,B9,B7:B6 ; / each register file A4, A1, A3:A2 A8,*A9 ; \ No long read with ; / the store on T1 path of .D1
ADD .L1 || STW .D1T1
The following execute packet is invalid on all cores:

SHR .S1 A5:A4, A1, A3:A2 ; \ No long read on .S1 with || STW .D1T1 A8,*A9 ; / the store on T1 path of .D1
5-17
Addressing Modes
5.7 Addressing Modes

The addressing modes on the C6000 DSPs are linear, circular using BK0, and circular using BK1. The mode is specified by the addressing mode register, or AMR (defined in Chapter 2). All registers can perform linear addressing. Only eight registers can perform circular addressing: A4-A7 are used by the .D1 unit, and B4-B7 are used by the .D2 unit. No other units can perform circular addressing. LDB(U)/LDH(U)/LDW, STB/ STH/STW, LDNDW, LDNW, STNDW, STNW, LDDW, STDW, ADDAB/ADDAH/ ADDAW/ADDAD, and SUBAB/SUBAH/SUBAW instructions all use the AMR to determine what type of address calculations are performed for these registers. There is no SUBAD instruction.
5.7.1
5.7.1.1
Linear Addressing Mode

LD/ST Instructions
For load and store instructions, linear mode simply shifts the offsetR/cst operand to the left by 3, 2, 1, or 0 for double word, word, halfword, or byte access, respectively; and then performs an add or a subtract to baseR (depending on the operation specified). The LDNDW and STNDW instructions also support non-scaled offsets. In non-scaled mode, the offsetR/cst is not shifted before adding or subtracting from the baseR. For the pre-increment, pre-decrement, positive offset, and negative offset address generation options, the result of the calculation is the address to be accessed in memory. For post-increment or post-decrement addressing, the value of baseR before the addition or subtraction is the address to be accessed from memory.
5.7.1.2
For integer addition and subtraction instructions, linear mode simply shifts the src1/cst operand to the left by 3, 2, 1, or 0 for double word, word, halfword, or byte data sizes, respectively, and then performs the add or subtract specified.
5.7.2
Circular Addressing Mode

The BK0 and BK1 fields in the AMR specify block sizes for circular addressing. See the description of the AMR (defined in Chapter 2) for more information.
5-18
Addressing Modes
5.7.2.1
LD/ST Instructions
As with linear address arithmetic, offsetR/cst is shifted left by 3, 2, 1, or 0 according to the data size, and is then added to or subtracted from baseR to produce the final address. Circular addressing modifies this slightly by only allowing bits N through 0 of the result to be updated, leaving bits 31 through N+1 unchanged after address arithmetic. The resulting address is bounded to 2(N+1) range, regardless of the size of the offsetR/cst. The circular buffer size specified in the AMR is not scaled. For example, a block-size of 8 is 8 bytes, not 8 times the data size (byte, half word, word). So, to perform circular addressing on an array of 8 words, a size of 32 should be specified, or N = 4. Example 51 shows an LDW performed with register A4 in circular mode and BK0 = 4, so the buffer size is 32 bytes, 16 half words, or 8 words. The value put in the AMR for this example is 00040001h.
Example 51. LDW in Circular Mode

LDW .D1 *++A4[9],A1 Before LDW
A4 A1 mem
Note:
1 cycle after LDW

A4 A1 mem 104h 0000 0104h XXXX XXXXh 1234 5678h mem
5 cycles after LDW

A4 0000 0104h A1 1234 5678h 104h 1234 5678h
0000 0100h XXXX XXXXh 1234 5678h
104h
9h words is 24h bytes. 24h bytes is 4 bytes beyond the 32-byte (20h) boundary 100h11Fh; thus, it is wrapped around to (124h 20h = 104h).
5.7.2.2
As with linear address arithmetic, offsetR/cst is shifted left by 3, 2, 1, or 0 according to the data size, and is then added to or subtracted from baseR to produce the final address. Circular addressing modifies this slightly by only allowing bits N through 0 of the result to be updated, leaving bits 31 through N+1 unchanged after address arithmetic. The resulting address is bounded to 2(N+1) range, regardless of the size of the offsetR/cst. The circular buffer size in the AMR is not scaled. For example, a block size of 8 is 8 bytes, not 8 times the data size (byte, half word, word). So, to perform circular addressing on an array of 8 words, a size of 32 should be specified, or N = 4. Example 52 shows an ADDAH performed with register A4 in circular mode and BK0=4, so the buffer size is 32 bytes, 16 half words, or 8 words. The value put in the AMR for this example is 00040001h.
5-19
Addressing Modes
Example 52. ADDAH in Circular Mode

ADDAH .D1 A4,A1,A4 1 cycle after ADDAH
A4 0000 0106h A1 0000 0013h
Before ADDAH
A4 0000 0100h A1 0000 0013h
Note:
13h halfwords is 26h bytes. 26h bytes is 6 bytes beyond the 32-byte (20h) boundary 100h11Fh; thus, it is wrapped around to (126h 20h = 106h).
5.7.2.3
Circular Addressing Considerations with Non-Aligned Memory

Circular addressing may be used with non-aligned accesses. When circular addressing is enabled, address updates and memory accesses occur in the same manner as for the equivalent sequence of byte accesses. The only restriction is that the circular buffer size be at least as large as the data size being accessed. Non-aligned access to circular buffers that are smaller than the data being read will cause undefined results. Non-aligned accesses to a circular buffer apply the circular addressing calculation to logically adjacent memory addresses. The result is that non-aligned accesses near the boundary of a circular buffer will correctly read data from both ends of the circular buffer, thus seamlessly causing the circular buffer to wrap around at the edges. Consider, for example, a circular buffer size of 16 bytes. A circular buffer of this size at location 0x20, would look like this in physical memory:
1 7 x
1 8 x
1 9 x
1 A x
1 B x
1 C x
1 D x
1 E x
1 F x
2 0 a
2 1 b
2 2 c
2 3 d
2 4 e
2 5 f
2 6 g
2 7 h
2 8 i
2 9 j
2 A k
2 B l
2 C m
2 D n
2 E o
2 F p
3 0 x
3 1 x
3 2 x
3 3 x
3 4 x
3 5 x
3 6 x
3 7 x
3 8 x
The effect of circular buffering is to make it so that memory accesses and address updates in the 0x200x2F range stay completely inside this range. Effectively, the memory map behaves in this manner:
2 7 h
2 8 i
2 9 j
2 A k
2 B l
2 C m
2 D n
2 E o
2 F p
2 0 a
2 1 b
2 2 c
2 3 d
2 4 e
2 5 f
2 6 g
2 7 h
2 8 i
2 9 j
2 A k
2 B l
2 C m
2 D n
2 E o
2 F p
2 0 a
2 1 b
2 2 c
2 3 d
2 4 e
2 5 f
2 6 g
2 7 h
2 8 i
5-20
Addressing Modes
Example 53 shows an LDNW performed with register A4 in circular mode and BK0 = 3, so the buffer size is 16 bytes, 8 half words, or 4 words. The value put in the AMR for this example is 00030001h. The buffer starts at address 0x0020 and ends at 0x002F. The register A4 is initialized to the address 0x002A.
Example 53. LDNW in Circular Mode

LDNW .D1 *++A4[2],A1 Before LDNW
A4 A1 mem
Note:
1 cycle after LDNW

A4 A1 mem 0022h 0000 0022h XXXX XXXXh 5678 9ABCh mem
5 cycles after LDNW

A4 0000 0022h A1 5678 9ABCh 0022h 5678 9ABCh
0000 002Ah XXXX XXXXh 5678 9ABCh
0022h
2h words is 8h bytes. 8h bytes is 3 bytes beyond the 16-byte (10h) boundary starting at address 002Ah; thus, it is wrapped around to 0022h (002Ah + 8h = 0022h).
5-21

This section gives detailed information on the fixed-point instruction set for the C64x. Each instruction presents the following information:
-
Assembler syntax Functional units Operands Opcode Description Execution Instruction type Delay slots See Also lists instructions of similar type Examples
5-22
ABS2
ABS2
Syntax
Absolute Value With Saturation, Signed Packed 16-Bit

ABS2 (.unit) src2, dst .unit = .L1, .L2
For operand type... Unit xs2 s2
Opfield
src2 dst
Opcode
31 29 28 27 23 22 18 17
.L1, .L2 00100
13
12 x 1
11 0
10 0
9 1
8 1
7 0 10
6 1
5 0
4 1
3 1
2 0
creg
3
z
1
dst
5
src/cst
5
op
5
s
1
p
1
Description
In the ABS2 instruction, the absolute values of the upper and lower halves of the src2 operand are placed in the upper and lower halves of the dst.
if (cond) {
Execution
(abs(lsb16(src2)) lsb16(dst) (abs(msb16(src2)) msb16(dst)

}
else nop Specifically, this instruction performs the following steps for each half-word of src2, then writes its result to the appropriate half-word of dst: 1) If the value is between 0 and 215, then value dst 2) If the value is less than 0 and not equal to 215, then value dst 3) If the value is equal to 215, then 215 1 dst Note: This operation is performed on each 16-bit value separately. This instruction does not affect the SAT bit in the CSR.
5-23
ABS2
Pipeline ___________________ Pipeline Stage E1
___________________ Read Written Unit in use
src2 dst
.L
___________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 ABS ABS2 .L1 A0,A15
1 cycle after instruction 152 20029 A0 FF68 4E3Dh 152 20029
Before instruction A0 FF68 4E3Dh
A2
XXXX XXXXh
A2
0098 4E3Dh
152 20029
Example 2
ABS2
.L1
A0,A15
1 cycle after instruction 16374 3835 A0 3FF6 F105h 16374 3835
Before instruction A0 3FF6 F105h
A2
XXXX XXXXh
A2
3FF6 0EFBh
16374 3835
5-24
ADD2
ADD2
Syntax
Two 16-Bit Integer Adds on Upper and Lower Register Halves

ADD2 (.unit) src1, src2, dst .unit = .S1, .S2, .L1, .L2, .D1 or .D2
For operand type... Unit i2 xi2 i2 i2 xi2 i2 i2 xi2 i2 .S1, .S2
Opfield 000001
src1 src2 dst src1 src2 dst src1 src2 dst

Opcode
.L1, .L2
0000101
.D1, .D2
0100
.S unit
31 29 27 23 22 18 17 13 12 x 1 11 6 5 1 4 0 4 3 0 2 0 1 0
creg
3
z
1
dst
5
src2
5 5
src1
op
6
s
1
p
1
.L Unit
31 29 28 27 23 22 18 17 13 12 x 1 11 5 4 1 3 1 3 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
.D unit
31 creg 3 29 28 27 dst 5 5 23 22 src2 18 17 src1 5 13 12 x 1 11 1 2 10 0 9 6 5 1 4 1 4 3 0 2 0 1 0
z
1
op
4
s
1
p
1
Description
In the ADD2 instruction, the upper and lower halves of the src1 operand are added to the upper and lower halves of the src2 operand. The values in src1 and src2 are treated as signed, packed 16-bit data and the results are written in signed, packed 16-bit format into dst.
5-25
ADD2
For each pair of signed packed 16-bit values found in the src1 and src2, the sum between the 16-bit value from src1 and the 16-bit value from src2 is calculated to produce a16-bit result. The result is placed in the corresponding positions in the dst. The carry from the lower half add does not affect the upper half add. This is the same ADD2 instruction that is found on the C62x, but with the added flexibility of being able to perform this operation on the .L and .D units as well as the .S unit.
31 a_hi 16 15 a_lo 0
src1
ADD2
b_hi
b_lo
src2
31 a_hi + b_hi
16
15 a_lo + b_lo
0
dst
Execution
if (cond)
{ msb16(src1) + msb16(src2) msb16(dst); lsb16(src1) + lsb16(src2) lsb16(dst); }
else nop
5-26
ADD2
Pipeline ___________________________ Pipeline Stage E1
___________________________ Read Written Unit in use
src1, src2 dst

.S, .L, .D
___________________________ Instruction Type Delay Slots See Also Example Single-cycle 0 ADD, ADD4, SUB2 ADD2 .L1 A0,A1,A2
1 cycle after instruction 33 14305 signed A1 039A E4B8h 922 6984 signed A2 XXXX XXXXh A2 03BB 1C99h A1 039A E4B8h A0 0021 37E1h 33 14305 signed 922 6984 signed 955 7321 signed
Before instruction A0 0021 37E1h
5-27
ADD4
ADD4
Syntax
Add Four 8-Bit Pairs For Four 8-Bit Results

ADD4 (.unit) src1, src2, dst unit = .L1, .L2
For operand type... Unit i4 xi4 i4
Opfield
src1 src2 dst

Opcode
31 creg 3 29 28 27 dst 5 23 22 18 17
.L1, .L2 1100101
13
12 x 1
11
4 1 1 3
2 0
z
1
src2
5
src1
5
op
7
s
1
p
1
Description
The ADD4 instruction performs 2s-complement addition between packed 8-bit quantities. The values in src1 and src2 are treated as packed 8-bit data and the results are written in packed 8-bit format. For each pair of packed 8-bit values found in src1 and src2, the sum between the 8-bit value from src1 and the 8-bit value from src2 is calculated to produce an 8-bit result. The result is placed in the corresponding positions in dst. No saturation is performed. The carry from one 8-bit add does not affect the add of any other 8-bit add.
31 3 a_3
24
23 2 a_2
16
15 1 a_1
7 0 a_0
1 src1
ADD4 b_3 b 3 b_2 b 2 b_1 b 1 b_0 b 0
src2 2
31 a_3 + b_3
24 23 a_2 + b_2
16
15 a_1 + b_1
7 a_0 + b_0
dst
5-28
ADD4
Execution if (cond) { byte0(src1) + byte0(src2) byte0(dst) byte1(src1) + byte1(src2) byte1(dst) byte2(src1) + byte2(src2) byte2(dst) byte3(src1) + byte3(src2) byte3(dst) } else nop Pipeline __________________________ Pipeline Stage E1
__________________________ Read Written Unit in use
src1, src2 dst

.L
__________________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 ADD, ADD2, SUB4 ADD4 .L1 A0,A1,A2
1 cycle after instruction A0 FF 68 4E 3Dh
Before instruction A0 FF 68 4E 3Dh
A1
3F F6 F1 05h
A1
3F F6 F1 05h
A2
XXXX XXXXh
A2
3E 5E 3F 42h
5-29
ADD4
Example 2
ADD4
.L1
A0,A1,A2
1 cycle after instruction A0 4A E2 D3 1Fh
Before instruction A0 4A E2 D3 1Fh
A1
32 1A C1 28h
A1
32 1A C1 28h
A2
XXXX XXXXh
A2
7C FC 94 47h
5-30
ADDAD
ADDAD
Syntax
Integer Addition Using Doubleword Addressing Mode

ADDAD (.unit) src2, src1, dst .unit = . D1 or .D2
Opcode map field used... For operand type... sint sint sint sint ucst5 sint Unit .D1, .D2 Opfield 111100
.D1, .D2
111101
Opcode
.D unit
31 29 28 27 23 22 18 17 13 12 7 6 1 5 1 4 1 5 3 0 2 0 1 0
creg
3
z
1
dst
5 5
src2
src1/cst
5
op
6
s
1
p
1
Description
src1 is added to src2 using the doubleword addressing mode specified for src2. The addition defaults to linear mode. However, if src2 is one of A4A7 or B4B7, the mode can be changed to circular mode by writing the appropriate value to the AMR (see section 2.6.2 on page 2-14). src1 is left shifted by 3 due to doubleword data sizes. The result is placed in dst. (See the ADDAB/ ADDAH/ADDAW instruction, page 3-34, for byte, halfword, and word versions.)
Note: There is no SUBAD instruction.
Execution
if (cond) else
src2 +(src1 tt 3) dst nop
5-31
ADDAD
Pipeline ___________________________ Pipeline ___________________________ Read Written Unit in use
src1, src2 dst

.D
___________________________ Instruction Type Delay Slots See Also Example Single-cycle 0 ADDAB, ADDAH, ADDAW ADDAD .D1 A1,A2,A3
1 cycle after instruction A1 0000 1234h A2 0000 0002h A3 0000 1244h 4660 2 4676
Before instruction A1 0000 1234h A2 0000 0002h A3 XXXX XXXXh 4660 2
5-32
ADDKPC
ADDKPC
Syntax
Add a Signed 7-bit Constant to Program Counter

ADDKPC (.unit) src1, dst, src2 .unit = S2
For operand type... scst7 ucst3 uint
Unit .S2
src1 src2 dst

Opcode
31 29 28 27 23 22 16 15
13
12 0 1
11 0
10 0
9 0
8 1
7 0 10
6 1
5 1
4 0
3 0
2 0
creg
3
z
1
dst
5
scst7
7
ucst3
3
s
1
p
1
Description
In the ADDKPC instruction, a 7-bit signed constant is shifted 2 bits to the left, then added to the address of the first instruction of the fetch packet that contains the ADDKPC instruction (PCE1). The result is placed in the destination register. The 3-bit unsigned constant specifies the number of NOP cycles to insert after the current instruction. This instruction helps reduce the number of instructions needed to set up the return address for a function call. The following code: B MVKL MVKH NOP LABEL could be replaced by: B .S2 ADDKPC .S2 LABEL Only one ADDKPC instruction can be executed per cycle. An ADDKPC instruction cannot be paired with any relative branch instruction in the same execute packet. If an ADDKPC and a relative branch are in the same execute packet, and if the ADDKPC instruction is executed when the branch is taken, behavior is undefined.
5-33
.S2 .S2 .S2 3
func LABEL, B3 LABEL, B3
func LABEL, B3, 4
ADDKPC
Execution if (cond) (scst7 << 2) + PCE1 dst else nop Pipeline ______________________ Pipeline Stage E1
______________________ Read Written Unit in use
src1, src2 dst

.S
______________________ Instruction Type Delay Slots See Also Example Single-cycle 0 B, BNOP ADDKPC .S2 30h,B3,5
1 cycle after instruction
Before instruction PCE1 0100 0000h
B3
XXXX XXXXh
B3
0100 00C0h
5-34
AND
AND
Syntax
Bitwise AND
AND (.unit) src1, src2, dst .unit = .L1, .L2, .S1, .S2, .D1, .D2
For operand type... Unit uint xint uint scst5 xuint uint uint xunit uint scst5 xuint uint uint xuint uint scst5 xuint uint .L1, .L2
Opfield 1111001
src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src src2 dst src1 src2 dst
Opcode
.L1, .L2
1111010
.S1, .S2
011111
.S1, .S2
011110
.D1, .D2
0110
.D1, .D2
0111
.L unit form:
31 29 28 27 23 22 18 17 13 12 x 1 11 5 4 1 3 1 3 2 0 1 0
creg
3
dst
5
src2
5
src1lcst
5
op
7
s
1
p
1
.S unit form:
31 29 28 27 23 22 18 17 13 12 x 1 11 6 5 1 4 1 4 3 0 2 0 1 0
creg
3
dst
5
src2
5
src1lcst
5
op
6
s
1
p
1
5-35
AND
.D unit form:
31 29 28 z 1 27 23 22 18 17 13 12 x 1 11 1 2 10 0 9 6 5 1 4 1 4 3 0 2 0 1 s 1 0 p 1
creg
3
dst
5
src2
5
src1/cst5
5
op
4
Description
In this instruction a bitwise AND is performed between src1 and src2. The result is placed in dst. The scst5 operands are sign extended to 32 bits. This is the same AND instruction that is found on the C62x, but with the added flexibility of being able to perform this operation on the .D unit as well as the .L and .S units. if (cond) src1 and src2 dst else nop
Execution
Pipeline
_________________________ Pipeline Stage E1
_________________________ Read Written Unit in use
src1, src2 dst

.L, .S, or .D
_________________________ Instruction Type Delay Slots See Also Example 1 Single Cycle 0 ANDN, OR, XOR AND .L1X A1, B1, A2
1 cycle after instruction A1 A2 B1 F7A1 302Ah 02A0 2020h 02B6 E724h
Before instruction A1 A2 B1 F7A1 302Ah XXXX XXXXh 02B6 E724h
5-36
AND
Example 2
AND .L1
15,A1,A3
1 cycle after instruction A1 A3 32E4 6936h 0000 0006h
Before instruction A1 A3 32E4 6936h XXXX XXXXh
5-37
ANDN
ANDN
Syntax
Bit-Wise Logical AND Invert

ANDN (.unit) src1, src2, dst unit = .L1, .L2, .D1, .D2, S1, .S2
For operand type... Unit uint xuint uint uint xunit uint uint xuint uint
Opfield

Opcode
.L1, .L2 1111100
.D1, .D2 .S1, .S2
0000
0110
.D unit form:
31 29 28 27 23 22 18 17 13 12 x 1 11 1 2 10 0 9 6 5 1 4 1 4 3 0 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
4
s
1
p
1
.L unit form:
31 29 28 27 23 22 18 17 13 12 x 1 11 5 4 1 3 1 3 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
.S unit form:
31 29 28 27 23 22 18 17 13 12 x 1 11 1 2 10 1 9 6 5 1 4 1 4 3 0 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
4
s
1
p
1
Description
In the ANDN instruction, a bitwise logical AND is performed between src1 and the bitwise logical inverse of src2. The result is placed in dst. if (cond) src1 and ~ src2 dst else nop
Execution
5-38
ANDN
Pipeline _________________________ Pipeline Stage E1
_________________________ Read Written Unit in use
src1, src2 dst

.L, .S, or .D
_________________________ Instruction Type Delay Slots See Also Example Single-cycle 0 AND, OR, XOR ANDN .L1 A0,A1,A2
1 cycle after instruction A0 1957 21ABh
Before instruction A0 1957 21ABh
A1
081C 17E6h
F7E3E819
A1
081C 17E6h
A2
XXXX XXXXh
A2
1143 2009h
5-39
AVG2
AVG2
Syntax
Average, Signed Packed 16-Bit

AVG2 (.unit) src1,src2, dst .unit = .M1, .M2
For operand type... Unit s2 xs2 s2 .M1, .M2
Opfield 10011
src1 src2 dst

Opcode
31 29 28 z 1 27 23 22 18 17
13
12 x 1
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
dst
5
src2
5
src1
5
op
5
s
1
p
1
Description
The AVG2 instruction performs an averaging operation on packed 16-bit data. For each pair of signed 16-bit values found in src1 and src2, AVG2 calculates the average of the two values and returns a signed 16-bit quantity in the corresponding position in the dst. if (cond) { ((lsb16(src1) + lsb16(src2) + 1) >> 1) lsb16(dst); ((msb16(src1) + msb16(src2) + 1) >> 1) msb16(dst); } The averaging operation is performed by adding 1 to the sum of the two 16-bit numbers being averaged. The result is then right-shifted by 1 to produce a 16-bit result. Note: No overflow conditions exist.
Execution
Pipeline
________________________________ Pipeline Stage E1 E2
_________________________________ Read Written Unit in use .M
src1, src2 dst
________________________________
5-40
AVG2
Instruction Type Delay Slots See Also Example Two-cycle 1 AVGU4 AVG2 .M1 A0,A1,A2
2 cycles after instruction 24984 17239 A0 6198 4357h 24984 17239
A1
7582 AE15
30082 20971
A1
7582 AE15h
30082 20971
A2
XXXX XXXXh
A2
6B8D F8B6
27533 1866
5-41
AVGU4
AVGU4
Syntax
Average, Unsigned Packed 8-Bit

AVGU4 (.unit) src1,src2, dst .unit = .M1, .M2
For operand type... Unit u4 xu4 u4 .M1, .M2
Opfield 10010
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
5
s
1
p
1
Description
The AVGU4 instruction performs an averaging operation on packed 8-bit data. The values in src1 and src2 are treated as unsigned, packed 8-bit data and the results are written in unsigned, packed 8-bit format. For each unsigned, packed 8-bit value found in src1 and src2, AVGU4 calculates the average of the two values and returns an unsigned, 8-bit quantity in the corresponding positions in the dst.
31 ua_3
24
23 ua_2
16
15 ua_1
7 ua_0
src1
AVGU4 ub_3 ub_2 ub_1 ub_0
src2
31
24
23
16
15
0 (ua_0 + ub_0 +1)>>1
(ua_3 + ub_3 +1)>>1
(ua_2 + ub_2 +1)>>1
(ua_1 + ub_1 +1)>>1
dst
5-42
AVGU4
Execution
if (cond)
{ ((ubyte0(src1) + ubyte0(src2) + 1) >> 1) ubyte0(dst); (((ubyte1(src1) + ubyte1(src2) + 1) >> 1) ubyte1(dst); (((ubyte2(src1) + ubyte2(src2) + 1) >> 1) ubyte2(dst); (((ubyte3(src1) + ubyte3(src2) + 1) >> 1) ubyte3(dst) }
else nop The averaging operation is performed by adding 1 to the sum of the two 8-bit numbers being averaged. The result is then right-shifted by 1 to produce an 8-bit result. Note: No overflow conditions exist. Pipeline ______________________________ Pipeline Stage E1 E2
_______________________________ Read Written Unit in use .M
src1, src2 dst
_______________________________ Instruction Type Delay Slots See Also Example Two-cycle 1 AVG2 AVGU4 .M1 A0,A1,A2
2 cycles after instruction 26 46 95 78 unsigned A1 9E F2 6E 3Fh 158 242 110 63 unsigned A2 XXXX XXXXh A2 5C 90 67 47h A1 9E F2 6E 3Fh A0 1A 2E 5F 4Eh 26 46 95 78 unsigned 158 242 110 63 unsigned 92 144 103 71 unsigned
Before instruction A0 1A 2E 5F 4Eh
5-43
BDEC
BDEC
Syntax
Branch and Decrement

BDEC (.unit) scst10, dst .unit = .S1, .S2 Opcode map field used... For operand type... Unit scst10 int .S1, .S2
src dst
Opcode
31 29 28 z 1 27 23 22 13
12 1 1
11 0
10 0
9 0
8 0
7 0 10
6 0
5 1
4 0
3 0
2 0
creg
3
dst
5
scst10
10
s
1
p
1
Description
If the predication and decrement register (dst) is positive (greater than or equal to 0), the BDEC instruction performs a relative branch and decrements dst by one. The instruction performs the relative branch using a 10-bit signed constant specified by the scst10. The constant is shifted 2 bits to the left, then added to the address of the first instruction of the fetch packet that contains the BDEC instruction (PCE1). The result is placed in the program fetch counter (PFC). This instruction helps reduce the number of instructions needed to decrement a register and conditionally branch based upon the value of the register. Note also that any register can be used which can free the predicate registers (A0A2 and B0B2) for other uses. The following code: [!A1] ||[!A1] could be replaced by: BDEC NOP Note: Only one BDEC instruction can be executed per cycle. The BDEC instruction can be predicated by using any conventional condition register. The conditions are effectively ANDed together. If two branches are in the same execute packet, and if both are taken, behavior is undefined. .S1 5 func, A10 CMPLT SUB B NOP 5 .L1 .L1 .S1 A10,0,A1 A10,1,A10 func
5-44
BDEC
Execution if(cond) { if (dst >=0), PFC = ((PCE1 + se(scst10)) <<2); if (dst >=0), dst = dst 1; else nop } else nop Pipeline ____________________________________________________________ Target Instruction ____________________________________________________________ Pipeline Stage E1 PS PW PR DP DC E1
____________________________________________________________ Read Written Branch Taken Unit in use .S
dst dst, PC
X
____________________________________________________________ Instruction Type Delay Slots Example 1 Branch 5 BDEC .S1 100h,A10
After branch has been taken
PC
XXXX XXXXh
PC
0100 0400h
A10
0000 000Ah
A10
0000 0009h
5-45
BDEC
Example 2
BDEC
.S1
300h,A10 ; 300h is sign extended

PC
XXXX XXXXh
PC
00FF FC00h
A10
0000 0010h
A10
0000 000Fh
5-46
BITC4
BITC4
Syntax
Bit Count, Packed 8-Bit

BITC4 (.unit) src2, dst .unit = .M1, .M2
For operand type... Unit xu4 u4 .M1, .M2
Opfield 11110
src2 dst
Opcode
31 29 28 z 1 27 23 22 18 17
13
12 x 1
11 0
10 0
9 0
8 0
7 1 10
6 1
5 1
4 1
3 0
2 0
1 s 1
0 p 1
creg
3
dst
5
src
5
op
5
Description
The BITC4 instruction performs a bit-count operation on 8-bit quantities. The value in src2 is treated as packed 8-bit data, and the result is written in packed 8-bit format. For each of the 8-bit quantities in src2, the count of the number of 1 bits in that value is written to the corresponding position in dst.
24 23 16 15 ub_2 ub_1 8 7 ub_0 0
src2
31 ub_3
bit_count(ub_3)
bit_count(ub_2)
bit_count(ub_1)
bit_count(ub_0)
dst
Execution
if (cond)
{ ((bit_count src2(ubyte0)) ubyte0(dst); ((bit_count src2(ubyte1)) ubyte1(dst); ((bit_count src2(ubyte2)) ubyte2(dst); ((bit_count src2(ubyte3)) ubyte3(dst); }
else nop
5-47
BITC4
Pipeline ________________________________ Pipeline Stage E1 E2
_________________________________ Read Written
src2 dst
Unit in use .M __________________________________ Instruction Type Delay Slots Example Two-cycle 1 BITC4 .M1 A1,A2
2 cycles after instruction A1 9E 52 6E 30h
Before instruction A1 9E 52 6E 30h
A2
XXXX XXXX h
A2
05 03 05 02h
5-48
BITR
BITR
Syntax
Bit Reverse
BITR (.unit) src2, dst .unit = .M1, .M2
For operand type... Unit xu4 u4 .M1, .M2
Opfield 11111
src2 dst
Opcode
31 creg 3 29 28 z 1 27 23 22 18 17
13
12 x 1
11 0
10 0
9 0
8 0
7 1 10
6 1
5 1
4 1
3 0
2 0
dst
5
src
5
op
5
s
1
p
1
Description
The BITR instruction implements a bit-reversal. A bit-reversal function reverses the order of bits in a 32-bit word. This means that bit 0 of the source becomes bit 31 of the result, bit 1 of the source becomes bit 30 of the result, bit 2 becomes bit 29, and so on.
31 abcdefghijklmnopqrstuvwxyzABCDEF 0
src2
31 FEDCBAzyxwvutsrqponmlkjihgfedcba
0
dst
Execution
if (cond)
{ bit_reverse (src2) dst }
else nop
5-49
BITR
Pipeline _______________________________ Pipeline Stage E1 E2
________________________________ Read Written
src2 dst
Unit in use .M _________________________________ Instruction Type Delay Slots Example Two-cycle 1 BITR .M2 B4,B5
2 cycles after instruction B4 A6E2 C179h
Before instruction B4 A6E2 C179h
B5
XXXX XXXXh
B5
9E83 4765h
5-50
BNOP
BNOP
Syntax
Branch Using a Displacement With NOP

BNOP (.unit) src2, src1 .unit = .S1, .S2 Opcode map field used... For operand type... Unit scst12 ucst3 .S1, .S2
src2 src1
Opcode
31 29 28 27 16 15 13 12 0 1
11 0
10 0
9 0
8 1
7 0 10
6 0
5 1
4 0
3 0
2 0
creg
3
z
1
scst12
12
ucst3
3
s
1
p
1
Description
The constant displacement form of the BNOP instruction performs a relative branch with NOP instructions. The instruction performs the relative branch using the 12-bit signed constant specified by src2. The constant is shifted 2 bits to the left, then added to the address of the first instruction of the fetch packet that contains the BNOP instruction (PCE1). The result is placed in the program fetch counter (PFC). The 3-bit unsigned constant specified in src1 gives the number of delay slot NOP instructions to be inserted, from 0 to 5. With src1 = 0, no NOP cycles are inserted. This instruction helps reduce the number of instructions to perform a branch when NOP instructions are required to fill the delay slots of a branch. The following code:
B NOP .S1 N LABEL
LABEL: ADD could be replaced by:

BNOP .S1 LABEL, N
LABEL: ADD Note: BNOP instructions may be predicated. The predication condition controls whether or not the branch is taken, but does not affect the insertion of NOPs. BNOP always inserts the number of NOPs specified by N, regardless of the predication condition.
5-51
BNOP
Only one branch instruction can be executed per cycle. If two branches are in the same execute packet, and if both are taken, the behavior is undefined. It should also be noted that when a predicated BNOP instruction is used with a NOP count greater than 5, the C64x will insert the full delay slots requested when the predicated condition is false. For example, the following set of instructions will insert 7 cycles of NOPs:
ZERO [A0] .L1 A0 LABEL,7; branch is not taken and ; 7 cycles of NOPs are inserted
BNOP .S1
Conversely, when a predicated BNOP instruction is used with a NOP count greater than 5 and the predication condition is true, the branch will be taken and the multi-cycle NOP is terminated when the branch is taken. For example in the following set of instructions, only 5 cycles of NOP are inserted:
MVK [A0] BNOP .D1 .S1 1,A0 LABEL,7; branch is taken and 5 cycles of ; NOPs are inserted
Execution
if (cond)
{ PFC = (PCE1 + (se(scst12) << 2)); nop (src1); }
else
nop(src1 +1)
5-52
BNOP
Pipeline ____________________________________________________________
Target Instruction
____________________________________________________________ Pipeline Stage E1 PS PW PR DP DC E1
____________________________________________________________ Read Written Branch Taken
src2 PC
X
Unit in use .S ____________________________________________________________ Instruction Type Delay Slots See Also Example Branch 5 ADDKPC, B, NOP BNOP .S1 30h,2
PC
XXXX XXXXh
PC
0100 1100h
5-53
BNOP
BNOP
Syntax
Branch Using a Register With NOP

BNOP (.unit) src2, src1 .unit = .S2
For operand type... Unit xuint ucst3 .S2
src2 src1
Opcode
31 29 28 z 1 27 0 0 0 5 0 23 1 22 18 17 0 2 16 0 15 13 12 x 1
11 0
10 0
9 1
8 1
7 0
6 1 10
5 1
4 0
3 0
2 0
1 1 1
creg
3
src2
5
ucst3
3
p
1
Description
The register form of the BNOP instruction performs an absolute branch with NOP instructions. The register specified in src2 is placed in the program fetch counter (PFC). The 3-bit unsigned constant specified in src1 gives the number of delay slots NOP instructions to be inserted, from 0 to 5. With src1 = 0, no NOP cycles are inserted. This instruction helps reduce the number of instructions to perform a branch when NOP instructions are required to fill the delay slots of a branch. The following code: B NOP .S2 N B3
could be replaced by: BNOP Note: BNOP instructions may be predicated. The predication condition controls whether or not the branch is taken, but does not affect the insertion of NOPs. BNOP always inserts the number of NOPs specified by N, regardless of the predication condition. Only one branch instruction can be executed per cycle. If two branches are in the same execute packet, and if both are taken, the behavior is undefined. It
5-54
.S2
B3,
BNOP
should also be noted that when a predicated BNOP instruction is used with a NOP count greater than 5, the C64x will insert the full delay slots requested when the predicated condition is false. For example, the following set of instructions will insert 7 cycles of NOPs:
ZERO [A0] BNOP .L1 .S1 A0 B3,7; ; branch is not taken and 7 cycles of NOPs are inserted
Conversely, when a predicated BNOP instruction is used with a NOP count greater than 5 and the predication condition is true, the branch will be taken and multi-cycle NOP is terminated when the branch is taken. For example, in the following set of instructions only 5 cycles of NOP are inserted:
MVK [A0] BNOP .D1 .S1 1,A0 B3,7; branch is taken and 5 cycles of ; NOPs are inserted
Execution
if (cond)
src2 PFC
nop (src1); } else Pipeline nop (src1 +1)
____________________________________________________________ Target Instruction ____________________________________________________________ Pipeline Stage E1 PS PW PR DP DC E1
src2 PC
X
Unit in use .S2 ____________________________________________________________

5-55
BNOP
Instruction Type Delay Slots See Also Example Branch 5 ADDKPC, B, NOP BNOP .S2 A5,2
PC
XXXX XXXXh
PC
0100 F000h
A5
0100 F000h
A5
0100 F000h
5-56
BPOS
BPOS
Syntax
Branch Positive
BPOS (.unit) scst10, dst .unit = .S1, .S2 Opcode map field used... For operand type... Unit scst10 int .S1, .S2
src dst
Opcode
31 29 28 z 1 27 23 22
13
12 0 1
11 0
10 0
9 0
8 0
7 0 10
6 0
5 1
4 0
3 0
2 0
1 s 1
0 p 1
creg
3
dst
5
scst10
10
Description
If the predication register (dst) is positive (greater than or equal to 0), the BPOS instruction performs a relative branch. If dst is negative, the BPOS instruction takes no other action. The instruction performs the relative branch using a 10-bit signed constant specified by the scst10. The constant is shifted 2 bits to the left, then added to the address of the first instruction of the fetch packet that contains the BDEC instruction (PCE1). The result is placed in the program fetch counter (PFC). Any register can be used which can free the predicate registers (A0A2 and B0B2) for other uses. Note: Only one BPOS instruction can be executed per cycle. The BPOS instruction can be predicated by using any conventional condition register. The conditions are effectively ANDed together. If two branches are in the same execute packet, and if both are taken, behavior is undefined.
Execution
if (cond)
{ if (dst >=0), PFC = (PCE1 + (se(scst10) << 2)); else nop }
else
nop
5-57
BPOS
Pipeline ____________________________________________________________ Target Instruction ______________________________________________ Pipeline Stage E1 PS PW PR DP DC E1
dst PC
X
Unit in use .S ____________________________________________________________ Instruction Type Delay Slots Example Branch 5 BPOS .S1 200h,A10
PC
XXXX XXXXh
PC
0100 0800h
A10
0000 000Ah
A10
0000 000Ah
5-58
CMPEQ2
CMPEQ2
Syntax
Compare if Equal, Packed 16-Bit

CMPEQ2 (.unit) src1,src2, dst .unit = .S1, .S2
For operand type... Unit s2 xs2 bv2 .S1, .S2
Opfield 011101
src1 src2 dst

Opcode
31 29 28 z 1 27 23 22 18 17
13
12 x 1
11
5 1
4 0 4
3 0
2 0
1 s 1
0 p 1
creg
3
dst
5
src2
5
src1
5
op
6
Description
The CMPEQ2 instruction performs equality comparisons on packed 16-bit data. Each 16-bit value in src1 is compared against the corresponding 16-bit value in src2, returning either a 1 if equal or 0 if not equal. The equality results are packed into the two least-significant bits of dst. The result for the lower pair of values is placed in bit 0, and the results for the upper pair of values are placed in bit 1. The remaining bits of dst are set to 0.
5-59
CMPEQ2
31 a_hi
16 15 a_lo
src1
b_hi
b_lo
src2
a_lo = = b_lo a_hi = = b_hi
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = = 31 2 1 0
dst
Execution
if (cond
{ if (lsb16(src1) == lsb16(src2), 1 dst0 else 0 dst0 ; if (msb16(src1) == msb16(src2)), 1 dst1 else 0 dst1 }
else nop Pipeline ______________________ Pipeline Stage E1
_______________________ Read Written Unit in use
src1, src2 dst

.S
_______________________
5-60
CMPEQ2
Instruction Type Delay Slots See Also Example 1 Single-cycle 0 CMPEQ, CMPEQ4, CMPGT2, XPND2 CMPEQ2 .S1 A3,A4,A5
1 cycle after instruction A3 1105 6E30h
A4
1105 6980h
A4
1105 6980h
A5
XXXX XXXXh
A5
0000 0002h
Example 2
CMPEQ2
.S2
B2,B8,B15
1 cycle after instruction B2 F23A 3789h
Before instruction B2 F23A 3789h
B8
04B8 3789h
B8
04B8 3789h
B15
XXXX XXXXh
B15
0000 0001h
Example 3
CMPEQ2
.S2
B2,B8,B15
1 cycle after instruction B2 01B6 2451h
Before instruction B2 01B6 2451h
B8
01B6 2451h
B8
01B6 2451h
B15
XXXX XXXXh
B15
0000 0003h
5-61
CMPEQ4
CMPEQ4
Syntax
Compare if Equal, Packed 8-Bit

CMPEQ4 (.unit) src1,src2, dst .unit = .S1, .S2 Opcode map field used... For operand type... Unit s4 xs4 bv4 .S1, .S2 Opfield 011100
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11
5 1
4 0 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
6
s
1
p
1
Description
The CMPEQ4 instruction performs equality comparisons on packed 8-bit data. Each 8-bit value in src1 is compared against the corresponding 8-bit value in src2, returning a 1 if equal or 0 if not equal. The equality comparison results are packed into the four least-significant bits of dst. The 8-bit values in each input are numbered from 0 to 3, starting with the leastsignificant byte, then working towards the most- significant byte. The comparison results for byte 0 are written to bit 0 of the result. Likewise the results for byte 1 to 3 are written to bits 1 to 3 of the result, respectively, as shown in the diagram below. The remaining bits of dst are set to 0.
5-62
CMPEQ4
31 sa_3
24 23 sa_2
16 15 sa_1
8 7 sa_0
src1
sb_3
sb_2
sb_1
sb_0
src2
sa_0 = = sb_0 sa_1 = = sb_1 sa_2 = = sb_2 sa_3 = = sb_3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = = = = 31 4 3 2 1 0
dst
Execution
if (cond
{ if (sbyte0(src1) == sbyte0(src2)), 1 dst0 else 0 dst0 ; if (sbyte1(src1) == sbyte1(src2)), 1 dst1 else 0 dst1 if (sbyte2(src1) == sbyte2(src2)), 1 dst2 else 0 dst2 if (sbyte3(src1) == sbyte3(src2)), 1 dst3 else 0 dst3 }
else nop
5-63
CMPEQ4
Pipeline _______________________ Pipeline Stage E1
_______________________ Read Written
src1, src2 dst
Unit in use .S _______________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 CMPEQ, CMPEQ2, CMPGTU4, XPND4 CMPEQ4 .S1 A3,A4, A5
1 cycle after instruction A3 02 3A 4E 1Ch
Before instruction A3 02 3A 4E 1Ch
A4
02 B8 4E 76h
A4
02 B8 4E 76h
A5
XXXX XXXXh
A5
0000 000Ah
Example 2
CMPEQ4
.S2
B2,B6,B13
1 cycle after instruction B2 F2 3A 37 89h
Before instruction B2 F2 3A 37 89h
B8
04 B8 37 89h
B8
04 B8 37 89h
B13
XXXX XXXXh
B13
0000 0003h
5-64
CMPEQ4
Example 3
CMPEQ4
.S2
B2,B8,B13
1 cycle after instruction B2 01 B6 24 51h
Before instruction B2 01 B6 24 51h
B8
05 B6 24 51h
B8
05 B6 24 51h
B13
XXXX XXXXh
B13
0000 0007h
5-65
CMPGT2
CMPGT2
Syntax
Compare for Greater Than, Packed 16-Bit

CMPGT2 (.unit) src1,src2, dst .unit = .S1, .S2
Opfield 010100
src1 src2 dst

Opcode
31 29 28 z 1 27 23 22 18 17
13
12 x 1
11
5 1
4 0 4
3 0
2 0
1 s 1
0 p 1
creg
3
dst
5
src2
5
src1
5
op
6
Description
The CMPGT2 instruction performs comparisons for greater than values on signed, packed 16-bit data. Each signed 16-bit value in src1 is compared against the corresponding signed 16-bit value in src2, returning a 1 if src1 is greater than src2 or returning a 0 if it is not greater. The comparison results are packed into the two least-significant bits of dst. The result for the lower pair of values is placed in bit 0, and the results for the upper pair of values are placed in bit 1. The remaining bits of dst are set to 0.
5-66
CMPGT2
31 a_hi
16 15 a_lo
src1
b_hi
b_lo
src2
a_lo > b_lo a_hi > b_hi
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 > > 31 2 1 0
dst
Execution
if (cond)
{ if (lsb16(src1) > lsb16(src2), 1 dst0 else 0 dst0 ; if (msb16(src1) > msb16(src2)), 1 dst1 else 0 dst1 }
else nop Pipeline ______________________ Pipeline Stage E1
src1, src2 dst

.S
______________________ Instruction Type Delay Slots See Also Single-cycle 0 CMPEQ2, CMPGT, CMPGTU4, XPND2
5-67
CMPGT2
Example 1
CMPGT2
.S1
A3,A4,A5
1 cycle after instruction 4357 28208 A3 1105 6E30h 4357 28208
A4
1105 6980h
4357 27008
A4
1105 6980h
4357 22008
A5
XXXX XXXXh
A5
0000 0001h
Example 2
CMPGT2
.S2
B2,B8,B15
1 cycle after instruction 3526 14217 B2 F23A 3789h 3526 14217
Before instruction B2 F23A 3789h
B8
04B8 4975h
1208 18805
B8
04B8 4975h
1208 18805
B15
XXXX XXXX h
B15
0000 0000h
Example 3
CMPGT2
.S2
B2, B8, B15

1 cycle after instruction 422 9297 B2 01A6 2451h 422 9297
Before instruction B2 01A6 2451h
B8
0124 A051h
292 24495
B8
0124 A051h
292 24495
B15
XXXX XXXXh
B15
0000 0003h
5-68
CMPGTU4
CMPGTU4
Syntax
Compare for Greater Than, Unsigned Packed 8-Bit

CMPGTU4 (.unit) src1,src2, dst .unit = .S1, .S2 Opcode map field used... For operand type... Unit u4 xu4 bv4 .S1, .S2 Opfield 010101
src1 src2 dst

Opcode
31 29 28 z 1 27 23 22 18 17
13
12 x 1
11
5 1
4 0 4
3 0
2 0
creg
3
dst
5
src2
5
src1
5
op
6
s
1
p
1
Description
The CMPGTU4 instruction performs comparisons for greater than values on packed 8-bit data. Each unsigned 8-bit value in src1 is compared against the corresponding 8-bit unsigned value in src2, returning a 1 if the byte in src1 is greater than the corresponding byte in src2 or 0 if is not greater. The comparison results are packed into the four least-significant bits of dst. The 8-bit values in each input are numbered from 0 to 3, starting with the leastsignificant byte, then working towards the most-significant byte. The comparison results for byte 0 are written to bit 0 of the result. Likewise, the results for byte 1 to 3 are written to bits 1 to 3 of the result, respectively, as shown in the diagram below. The remaining bits of dst are set to 0.
5-69
CMPGTU4
31 ua_3
24 23 ua_2
16 15 ua_1
8 7 ua_0
src1
ub_3
ub_2
ub_1
ub_0
src2
ua_0 > ub_0 ua_1 > ub_1 ua_2 > ub_2 ua_3 > ub_3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 > > > > 31 4 3 2 1 0
dst
Execution
if (cond)
{ if (ubyte0(src1) > ubyte0(src2)), 1 dst0 else 0 dst0 ; if (ubyte1(src1) > ubyte1(src2)), 1 dst1 else 0 dst1 ; if (ubyte2(src1) > ubyte2(src2)), 1 dst2 else 0 dst2 ; if (ubyte3(src1) > ubyte3(src2)), 1 dst3 else 0 dst3 ; }
else nop
5-70
CMPGTU4
________________________ Read Written
src1, src2 dst
Unit in use .S ________________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 CMPEQ4, CMPGT, CMPGT2, XPND4 CMPGTU4 .S1 A3,A4,A5
1 cycle after instruction 37 58 28 228 A3 25 3A 1C E4h 37 58 28 228
Before instruction A3 25 3A 1C E4h
A4
02 B8 4E 76h
2 184 78 118
A4
02 B8 4E 76h
2 184 78 118
A5
XXXX XXXXh
A5
0000 0009h
Example 2
CMPGTU4
.S2
B2,B8,B13
Before instruction B2 89 F2 3A 37h 137 242 58 55 B2
89 F2 3A 37h
137 242 58 55
B8
04 8F 17 89h
4 143 23 137
B8
04 8F 17 89h
4 143 23 137
B13
XXXX XXXXh
B13
0000 000Eh
5-71
CMPGTU4
Example 3
CMPGTU4
Before instruction B2 12 33 9D 51h
.S2
B2,B8,B13
18 51 157 81
B2
12 33 9D 51h
18 51 157 81
B8
75 67 24 C5h
117 103 36 197
B8
75 67 24 C5h
117 103 36 197
B13
XXXX XXXXh
B13
0000 0002h
5-72
CMPLT2
CMPLT2
Syntax
Compare for Less Than, Packed 16-Bit (Pseudo-Operation)

CMPLT2 (.unit) src2, src1, dst .unit = .S1, .S2
Opfield 010100
src1 src2 dst

Opcode Description See CMPGT2 instruction.
The CMPLT2 instruction is a pseudo-operation used to perform less-than comparisons on signed, packed 16-bit data. Each signed 16-bit value in src2 is compared against the corresponding signed 16-bit value in src1, returning a 1 if src2 is less than src1 or returning a 0 if it is not less than. The comparison results are packed into the two least-significant bits of dst. The result for the lower pair of values is placed in bit 0, and the results for the upper pair of values are placed in bit 1. The remaining bits of dst are set to 0. The assembler uses the operation CMPGT2 (.unit) src1, src2, dst to perform this task. if (cond) { if (lsb16(src2) < lsb16(src1), 1 dst0 else 0 dst0 ; if (msb16(src2) < msb16(src1)), 1 dst1 else 0 dst1 } else nop
Execution
Pipeline
_______________________ Pipeline Stage E1
src1, src2 dst

.S
_______________________
5-73
CMPLT2
Instruction Type Delay Slots See Also Example 1 Single-cycle 0 CMPEQ2, CMPGT2, CMPLTU4, XPND2
CMPLT2 .S1 A4,A3,A5; assembler treats as CMPGT2 A3,A4,A5
Before instruction A3 1105 6E30h 4357 28208 A3 1 cycle after instruction 1105 6E30h 4357 28208
A4
1105 6980h
4357 27008
A4
1105 6980h
4357 27008
A5
XXXX XXXXh
A5
0000 0001h
Example 2
CMPLT2 .S2 B8,B2,B15; assembler treats as CMPGT2 B2,B8,B15

Before instruction B2 F23A 3789h 3526 14217 B2 1 cycle after instruction F23A 3789h 3526 14217
B8
04B8 4975h
1208 18805
B8
04B8 4975h
1208 18805
B15
XXXX XXXXh
B15
0000 0000h
Both are false
Example 3
CMPLT2 .S2 B8,B2,B12; assembler treats as CMPGT2 B2,B8,B15

Before instruction B2 01A6 2451h 422 9297 B2 1 cycle after instruction 01A6 2451h 422 9297
B8
0124 A051h
292 24495
B8
0124 A051h
292 24495
B12
XXXX XXXXh
B12
0000 0003h
Both are true
5-74
CMPLTU4
CMPLTU4
Syntax
Compare for Less Than, Unsigned Packed 8-Bit (Pseudo-Operation)

CMPLTU4 (.unit) src2, src1, dst .unit = .S1, .S2 Opcode map field used... For operand type... Unit u4 xu4 bv4 .S1, .S2 Opfield 010101
src1 src2 dst

Opcode Description See CMPGTU4 instruction.
CMPLTU4 is a pseudo-operation that performs less-than comparisons on packed 8-bit data. Each unsigned 8-bit value in src2 is compared against the corresponding 8-bit unsigned value in src1, returning a 1 if the byte in src2 is less than the corresponding byte in src1 or 0 it if is not less than. The comparison results are packed into the four least-significant bits of dst. The 8-bit values in each input are numbered from 0 to 3, starting with the leastsignificant byte, and moving towards the most-significant byte. The comparison results for byte 0 are written to bit 0 of the result. Similarly, the results for byte 1 to 3 are written to bits 1 to 3 of the result, respectively, as shown in the CMPGTU4 instruction diagram. The remaining bits of dst are set to 0. The assembler uses the operation CMPGTU4 (.unit) src1, src2, dst to perform this task.
Execution
if (cond)
{ if (ubyte0(src2) < ubyte0(src1)), 1 dst0 else 0 dst0 ; if (ubyte1(src2) < ubyte1(src1)), 1 dst1 else 0 dst1 ; if (ubyte2(src2) < ubyte2(src2)), 1 dst2 else 0 dst2 ; if (ubyte3(src2) < ubyte3(src1)), 1 dst3 else 0 dst3 ; }
else nop
5-75
CMPLTU4
_______________________ Read Written
src1, src2 dst
Unit in use .S _______________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 CMPEQ4, CMPGT, CMPLT2, XPND4
CMPLTU4 .S1 A4,A3,A5; assembler treats as CMPGTU4 A3,A4,A5
Before instruction A3 25 3A 1C E4h 37 58 28 228 A3 1 cycle after instruction 02 3A 1C E4h 37 58 28 228
A4
02 B8 4E 76h
2 184 78 118
A4
02 B8 4E 76h
2 184 78 118
A5
XXXX XXXXh
A5
0000 0009h
Example 2
CMPLTU4 .S2 B8,B2,B13; assembler treats as CMPGTU4 B2,B8,B13

Before instruction B2 89 F2 3A 37h 137 242 58 55 B2 1 cycle after instruction 89 F2 3A 37h 137 242 58 55
B8
04 8F 17 89h
4 143 23 137
B8
04 8F 17 89h
4 143 23 137
B13
XX XX XX XXh
B13
0000 000Eh
5-76
CMPLTU4
Example 3
CMPLTU4 .S2 B8,B2,B13; assembler treats as CMPGTU4 B2,B8,B13

Before instruction B2 12 33 9D 51h 18 51 157 81 B2 1 cycle after instruction 12 33 9D 51h 18 51 157 81
B8
75 67 24 C5h
117 103 36 197
B8
75 67 24 C5h
117 103 36 197
B13
XX XX XX XXh
B13
0000 0002h
5-77
DEAL
DEAL
Syntax
De-Interleave and Pack

DEAL (.unit) src2, dst .unit = .M1, .M2
For operand type... Unit xuint uint .M1, .M2
Opfield 11101
src2 dst
Opcode
31 29 28 z 1 27 23 22 18 17
13
12 x 1
11 0
9 0
9 0
8 0 10
7 1
6 1
5 1
4 1
3 0
2 0
creg
3
dst
5
src2
5
op
5
s
1
p
1
Description
The DEAL instruction performs a de-interleave and pack operation on the bits in src2. The odd and even bits of src2 are extracted into two separate, 16-bit quantities. These 16-bit quantities are then packed such that the even bits are placed in the lower half-word, and the odd bits are placed in the upper half word. As a result, bits 0, 2, 4, ... , 28, 30 of src2 are placed in bits 0, 1, 2, ... , 14, 15 of dst. Likewise, bits 1, 3, 5, ... , 29, 31 of src2 are placed in bits 16, 17, 18, ... , 30, 31 of dst.
31 aAbBcCdDeEfFgGhHiIjJkKlLmMnNoOpP 0
src2
31 abcdefghijklmnopABCDEFGHIJKLMNOP
0
dst
Note: The DEAL instruction is the exact inverse of the SHFL instruction.
5-78
DEAL
Execution if (cond) {
src231,29,27...1 dst31,30,29...16 ; src230,28,26...0 dst15,14,13...0 ;

} else nop Pipeline _______________________ Pipeline Stage E1 E2
_______________________ Read Written Unit in use .M
src2 dst
_______________________ Instruction Type Delay Slots See Also Example Two-cycle 1 SHFL DEAL .M1 A1,A2
2 cycles after instruction A1 9E52 6E30h
Before instruction A1 9E52 6E30h
A2
XXXX XXXXh
A2
B174 6CA4h
5-79
DOTP2
DOTP2
Syntax
Dot Product, Signed Packed 16-Bit

DOTP2 (.unit) src1,src2, dst .unit = .M1, .M2
For operand type... Unit s2 xs2 int s2 xs2 sllong .M1, .M2
Opfield 01100

Opcode
31 29 28 27 23 22 18 17
.M1, .M2
01011
13
12 x 1
11 0 1
10
5 1
4 1
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
5
s
1
p
1
Description
The DOTP2 instruction returns the dot-product between two pairs of signed, packed 16-bit values. The values in src1 and src2 are treated as signed, packed 16-bit quantities. The signed result is written either to a single 32-bit register, or sign-extended into a 64-bit register pair. The product of the lower half-words of src1 and src2 is added to the product of the upper half-words of src1 and src2. The result is then written to the dst. In the 64-bit result version the upper word of the register pair always contains either all 0s or all 1s, depending on whether the result is positive or negative, respectively.
5-80
DOTP2
31 a_hi
16
15 a_lo
0
src1
DOTP2
b_hi
b_lo
src2
=
63 0 or F 32 31 a_hi*b_hi + a_lo*b_lo 0
dst_o:dst_e
The 32-bit result version returns the same results that the 64-bit result version does in the lower 32 bits. The upper 32-bits are discarded.
31 a_hi 16 15 a_lo 0
src1
DOTP2
b_hi
b_lo
src2
=
31 a_lo*b_lo + a_hi*b_hi 0
dst
Note: In the overflow case, where all four half-words in src1 and src2 are 0x8000, the value 0x80000000 is written into the 32-bit dst and 0x0000000080000000 is written into the 64-bit dst.
5-81
DOTP2
Execution if (cond) { (lsb16(src1) x lsb16(src2)) + (msb16(src1) x msb16(src2)) dst } else nop Pipeline ______________________________________________ Pipeline Stage E1 E2 E3 E4
______________________________________________ Read Written Unit in use .M
src1, src2 dst
______________________________________________ Instruction Type Delay Slots See Also Example 1 Four-cycle 3 DOTPN2 DOTP2 .M1 A5,A6,A8
4 cycles after instruction 27186 4499 A5 6A32 1193h 27186 4499
Before instruction A5 6A32 1193h
A6
B174 6CA4h
20108 27812
A6
B174 6CA4h
20108 27812
A8
XXXX XXXXh
A8
E6DF F6D4h
421529900
5-82
DOTP2
Example 2
DOTP2
.M1
A5,A6,A9:A8
4 cycles after instruction A5 6A32 1193h 27186 4499
Before instruction A5 6A32 1193h 27186 4499
A6
B174 6CA4h
20108 27812
A6
B174 6CA4h
20108 27812
A9:A8
XXXX XXXXh
XXXX XXXXh
A9:A8
FFFF FFFFh
E6DF F6D4h 421529900
Example 3
DOTP2
.M2
B2,B5,B8
4 cycles after instruction B2 1234 3497h 4660 13463
Before instruction B2 1234 3497h 4660 13463
B5
21FF 50A7h
8703 20647
B5
21FF 50A7h
8703 20647
B8
XXXX XXXXh
B8
12FC 544Dh
318526541
Example 4
DOTP2
.M2
B2,B5,B9:B8
Before instruction B2 1234 3497h 4660 13463 B2
4 cycles after instruction 1234 3497h 4660 13463
B5
21FF 50A7h
8703 20647
B5
21FF 50A7h
8703 20647
B9:B8
XXXX XXXXh
XXXX XXXXh
B9:B8
0000 0000h
12FC 544Dh 318526541
5-83
DOTPN2
DOTPN2
Syntax
Dot Product With Negate, Signed Packed 16-Bit

DOTPN2 (.unit) src1,src2, dst .unit = .M1, .M2
For operand type... Unit s2 xs2 int .M1, .M2
Opfield 01001
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 0 1
10
5 1 1 4 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
5
s
1
p
1
Description
The DOTPN2 instruction returns the dot-product between two pairs of signed, packed 16-bit values where the second product is negated. The values in src1 and src2 are treated as signed, packed 16-bit quantities. The signed result is written to a single 32-bit register. The product of the lower half-words of src1 and src2 is subtracted from the product of the upper half-words of src1 and src2. The result is then written to dst.
31 a_hi
16 15 a_lo
0
src1
DOTPN2
b_hi
b_lo
src2
=
31 a_hi*b_hi a_lo*b_lo 0
dst
5-84
DOTPN2
Execution if (cond) { (msb16(src1) x msb16(src2)) (lsb16(src1) x lsb16(src2)) dst } else nop Note that unlike DOTP2, no overflow case exists for this instruction. Pipeline _______________________________________________________ Pipeline Stage E1 E2 E3 E4
________________________________________________________ Read Written Unit in use .M
src1, src2 dst
________________________________________________________ Instruction Type Delay Slots See Also Example 1 Four-cycle 3 DOTP2 DOTPN2 .M1 A5,A6,A8
4 cycles after instruction A5
Before instruction A5
3629 274Ah
13865 10058
3629 274Ah
13865 10058
A6
325C 8036h
12892 32714
A6 .
325C 8036h
12892 32714
A8
XXXX XXXXh
A8
1E44 2F20h
507784992
5-85
DOTPN2
Example 2
DOTPN2
.M2
B2,B5,B8
4 cycles after instruction B2
Before instruction B2
3FF6 5010h
16374 20496
3FF6 5010h
16374 20496
B5
B1C3 0244h
20029 580
B5
B1C3 0244h
20029 580
B8
XXXX XXXXh
B8
EBBE 6A22h
339842526
5-86
DOTPNRSU2
DOTPNRSU2
Syntax
Dot Product With Negate, Shift and Round, Signed by Unsigned Packed 16-Bit
DOTPNRSU2 (.unit) src1,src2, dst .unit = .M1, .M2
For operand type... Unit s2 xu2 int .M1, .M2
Opfield 00111
src1 src2 dst

Opcode
31 29 28 z 1 27 23 22 18 17
13
12 x 1
11 0 1
10
5 1 1 4 0
2 0
1 s 1
0 p 1
creg
3
dst
5
src2
5
src1
5
op
5
Description
The DOTPNRSU2 instruction returns the dot-product between two pairs of packed 16-bit values, where the second product is negated. This instructiion takes the result of the dot-product and performs an additional round and shift step. The values in src1 are treated as signed, packed 16-bit quantities; whereas the values in src2 are treated as unsigned, packed 16-bit quantities. The results are written to dst. The product of the lower half-words of src1 and src2 is subtracted from the product of the upper half-words of src1 and src2. The value 2 15 is then added to this sum, producing an intermediate 32-bit result. The intermediate result is signed shifted right by 16, producing a rounded, shifted result that is sign extended and placed in dst.
5-87
DOTPNRSU2
31 sa_hi
16 15 sa_lo
0
src1
DOTPNRSU2 31 ub_hi 16 15 ub_lo 0

src2
=
31 (((sa_hi*ub_hi) (sa_lo*ub_lo)) + 0x8000)>>16 0
dst
Note: The intermediate results of DOTPNRSU2 are only maintained to 32-bit precision, thus overflow may occur during the rounding step. Execution if (cond) { int = (smsb16(src1) x umsb16(src2)) (slsb16(src1) x ulsb16(src2)) + 0x8000; int >> 16 dst
}
else nop Pipeline ________________________________________________ Pipeline Stage E1 E2 E3 E4
________________________________________________ Read Written Unit in use .M
src1, src2 dst
________________________________________________
5-88
DOTPNRSU2
Instruction Type Delay Slots See Also Example 1 Four-cycle 3 DOTP2, DOTPN2, DOTPRSU2 DOTPNRSU2 .M1 A5, A6, A8
Before instruction
A5
3629 274Ah
13865 10058 signed
A5
3629 274Ah
13865 10058 signed
A6
325C 8036h
12892 32822 unsigned
A6
325C 8036h
A8
XXXX XXXXh
A8
FFFF F6FAh
2310 signed
Example 2
DOTPNRSU2
.M2
B2, B5, B8
3FF6 5010h
16374 20496 signed
3FF6 5010h
16374 20496 signed
B5
B1C3 0244h
45507 580 unsigned
B5
B1C3 0244h
45507 580 unsigned
B8
XXXX XXXXh
B8
0000 2BB4h
11188
signed
5-89
DOTPNRUS2
DOTPNRUS2
Dot Product With Negate, Shift and Round, Unsigned by Signed Packed 16-Bit (Pseudo-Operation)
Syntax
DOTPNRUS2 (.unit) src2, src1, dst .unit = .M1, .M2
Opfield 00111
src1 src2 dst

Opcode Description See DOTPNRSU2 instruction.
The DOTPNRUS2 pseudo-operation performs the dot-product between two pairs of packed 16-bit values, where the second product is negated. This instruction takes the result of the dot-product and performs an additional round and shift step. The values in src1 are treated as signed, packed 16-bit quantities, whereas the values in src2 are treated as unsigned, packed 16-bit quantities. The results are written to dst. The assembler uses the DOTPNRSU2 src1, src2, dst instruction to perform this task. The product of the lower half-words of src1 and src2 is subtracted from the product of the upper half-words of src1 and src2. The value 2 15 is then added to this sum, producing an intermediate 32-bit result. The intermediate result is signed shifted right by 16, producing a rounded, shifted result that is sign extended and placed in dst.
Execution
if (cond)
{ int = (umsb16(src2) x smsb16(src1)) (ulsb16(src2) x lsb16(src1)) + 0x8000; int >> 16 dst

}
else nop
5-90
DOTPNRUS2
Pipeline _________________________________________ Pipeline Stage E1 E2 E3 E4
__________________________________________ Read Written Unit in use .M
src1, src2 dst
__________________________________________ Instruction Type Delay Slots See Also Four-cycle 3 DOTP2, DOTPN2, DOTPNRSU2, DOTPRUS2
5-91
DOTPRSU2
DOTPRSU2
Syntax
Dot Product With Shift and Round, Signed by Unsigned Packed 16-Bit
DOTPRSU2 (.unit) src1,src2, dst .unit = .M1, .M2
Opfield 01101
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
5
s
1
p
1
Description
The DOTPRSU2 instruction returns the dot-product between two pairs of packed 16-bit values. This instruction takes the result of the dot-product and performs an additional round and shift step. The values in src1 are treated as signed packed 16-bit quantities, whereas the values in src2 are treated as unsigned packed 16-bit quantities. The results are written to dst. The product of the lower half-words of src1 and src2 is added to the product of the upper half-words of src1 and src2. The value 215 is then added to this sum, producing an intermediate 32-bit result. The intermediate result is signed shifted right by 16, producing a rounded, shifted result that is sign extended and placed in dst.
5-92
DOTPRSU2
31 sa_hi
16 15 sa_lo
0
src1
DOTPRSU2 31 ub_hi 16 15 ub_lo 0

src2
=
31 (((sa_hi*ub_hi) + (sa_lo*ub_lo)) + 0x8000)>>16 0
dst
Note: The intermediate results of DOTPRSU2 are only maintained to 32-bit precition, and so overflow may occur during the rounding step. Execution if (cond) { int = (smsb16(src1) x umsb16(src2)) + (slsb16(src1) x ulsb16(src2)) + 0x8000; int >> 16 dst } else nop Pipeline ________________________________________________ Pipeline Stage E1 E2 E3 E4
src1, src2 dst
________________________________________________ Instruction Type Delay Slots Four-cycle 3

5-93
DOTPRSU2
See Also Example 1 DOTP2, DOTPN2, DOTPNRSU2 DOTPRSU2 .M1 A5, A6, A8
Before instruction
A5
3629 274Ah
13865 10058 signed
A5
3629 274Ah
13865 10058 signed
A6
325C 8036h
A6
325C 8036h
A8
XXXX XXXXh
A8
0000 1E55
7765 signed
Example 2
DOTPRSU2
.M2
B2, B5, B8
Before instruction
B2 B1C3 0244h
20029 580 signed
B2 B1C3 0244h
20029 580 signed
B5 3FF6 5010h
B5 3FF6 5010h
B8 XXXX XXXXh
B8 FFFF ED29
4823 signed
5-94
DOTPRUS2
DOTPRUS2
Dot Product With Shift and Round, Unsigned by Signed Packed 16-Bit (Pseudo-Operation)
DOTPRUS2 (.unit) src2, src1, dst .unit = .M1, .M2
Syntax
Opfield 01101
src1 src2 dst

Opcode Description See DOTPRSU2 instruction.
The DOTPRUS2 pseudo-operation returns the dot-product between two pairs of packed 16-bit values. This instruction takes the result of the dot-product, and performs an additional round and shift step. The values in src1 are treated as signed packed 16-bit quantities, whereas the values in src2 are treated as unsigned packed 16-bit quantities. The results are written to dst. The assembler uses the DOTPRSU2 src1, src2, dst instruction to perform this task. The product of the lower half-words of src1 and src2 is added to the product of the upper half-words of src1 and src2. The value 215 is then added to this sum, producing an intermediate 32-bit result. The intermediate result is signed shifted right by 16, producing a rounded, shifted result that is sign extended and placed in dst.
Execution
if (cond)
{ int = (umsb16(src2) x smsb16(src1)) + (ulsb16(src2) x slsb16(src1)) + 0 x 8000; int >> 16 dst }
else nop
5-95
DOTPRUS2
Pipeline ________________________________________________ Pipeline Stage E1 E2 E3 E4
src1, src2 dst
________________________________________________ Instruction Type Delay Slots See Also Four-cycle 3 DOTP2, DOTPN2, DOTPNRUS2, DOTPRSU2
5-96
DOTPSU4
DOTPSU4
Syntax
Dot Product, Signed by Unsigned Packed 8-Bit

DOTPSU4 (.unit) src1,src2, dst .unit = .M1, .M2
Opcode map field used... src1 src2 dst Opcode

31 29 28 27 23 22 18 17
For operand type... Unit s4 .M1, .M2 xu4 int
Opfield 00010
13
12 x 1
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
5
s
1
p
1
Description
The DOTPSU4 instruction returns the dot-product between four sets of packed 8-bit values. The values in src1 are treated as signed packed 8-bit quantities, whereas the values in src2 are treated as unsigned 8-bit packed data. The signed result is written into dst. For each pair of 8-bit quantities in src1 and src2, the signed 8-bit value from src1 is multiplied with the unsigned 8-bit value from src2. The four products are summed together, and the resulting dot product is written as a signed 32-bit result to dst.
31 sa_3 24 23 sa_2 DOTPSU4 ub_3 ub_2 ub_1 ub_0
src2
16
15 sa_1
7 sa_0
0
src1
=
31 (sa_3*ub_3) + (sa_2*ub_2) + (sa_1*ub_1) + (sa_0*ub_0) 0
dst
5-97
DOTPSU4
Execution if (cond) { (sbyte0(src1) x ubyte0(src2)) + (sbyte1(src1) x ubyte1(src2)) + (sbyte2(src1) x ubyte2(src2)) + (sbyte3(src1) x ubyte3(src2)) dst } else nop Pipeline __________________________________________ Pipeline Stage E1 E2 E3 E4
src1, src2 dst
__________________________________________ Instruction Type Delay Slots See Also Example 1 Four-cycle 3 DOTPU4 DOTPSU4 .M1 A5, A6, A8
4 cycles after instruction 106 50 17 109 signed A6 B1 74 6C A4h 177 116 108 164 unsigned A8 XXXX XXXXh A8 0000 214Ah A6 B1 74 6C A4h A5 6A 32 11 93h 106 50 17 109 signed 177 116 108 164 unsigned 8522 signed
Before instruction A5 6A 32 11 93h
5-98
DOTPSU4
Example 2
DOTPSU4
.M2
B2, B5, B8
Before instruction B2 3F F6 50 10h 63 -10 80 16 B2
3F F6 50 10h
63 -10 80 16
signed
B5 C3 56 02 44h 195 86 2 68 B5 C3 56 02 44h
signed
195 86 2 68
unsigned
B8
unsigned
B8 0000 3181h 12673 signed
XXXX XXXXh
5-99
DOTPUS4
DOTPUS4
Syntax
Dot-Product, Unsigned by Signed Packed 8-Bit (Pseudo-Operation)

DOTPUS4 (.unit) src2, src1, dst .unit = .M1, .M2
Opfield 00010
src1 src2 dst
Opcode Description
See DOTPSU4 instruction. The DOTPUS4 pseudo-operation returns the dot-product between four sets of packed 8-bit values. The values in src1 are treated as signed packed 8-bit quantities, whereas the values in src2 are treated as unsigned 8-bit packed data. The signed result is written into dst. The assembler uses the DOTPSU4 src1, src2, dst instruction to perform this task. For each pair of 8-bit quantities in src1 and src2, the signed 8-bit value from src1 is multiplied with the unsigned 8-bit value from src2. The four products are summed together, and the resulting dot-product is written as a signed 32-bit result to dst.
Execution
if (cond)
{ (ubyte0(src2) x sbyte0(src1)) + (ubyte1(src2) x sbyte1(src1)) + (ubyte2(src2) x sbyte2(src1)) + (ubyte3(src2) x sbyte3(src1)) dst }
else nop
5-100
DOTPUS4
Pipeline __________________________________________ Pipeline Stage E1 E2 E3 E4
src1, src2 dst
__________________________________________ Instruction Type Delay Slots See Also Four-cycle 3 DOTPU4, DOTPSU4
5-101
DOTPU4
DOTPU4
Syntax
Dot Product, Unsigned Packed 8-Bit

DOTPU4 (.unit) src1, src2, dst .unit = .M1, .M2
For operand type... Unit u4 xu4 uint .M1, .M2
Opfield 00110
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
5
s
1
p
1
Description
The DOTPU4 instruction returns the dot-product between four sets of packed 8-bit values. The values in both src1 and src2 are treated as unsigned, 8-bit packed data. The unsigned result is written into dst. For each pair of 8-bit quantities in src1 and src2, the unsigned 8-bit value from src1 is multiplied with the unsigned 8-bit value from src2. The four products are summed together, and the resulting dot-product is written as a 32-bit result to dst.
31 ua_3 24 23 ua_2 DOTPU4 ub_3 ub_2 ub_1 ub_0 16 15 ua_1 8 7 ua_0 0
src1
src2
=
31 (ua_3*ub_3) + (ua_2*ub_2) + (ua_1*ub_1) + (ua_0*ub_0) 0
dst
5-102
DOTPU4
Execution if (cond) { (ubyte0(src1) x ubyte0(src2)) + (ubyte1(src1) x ubyte1(src2)) + (ubyte2(src1) x ubyte2(src2)) + (ubyte3(src1) x ubyte3(src2)) dst } else nop Pipeline __________________________________________ Pipeline Stage E1 E2 E3 E4
src1, src2 dst
__________________________________________ Instruction Type Delay Slots See Also Example Four-cycle 3 DOTPSU4 DOTPU4 .M1 A5, A6, A8
4 cycles after instruction 106 50 17 147 unsigned A6 B1 74 6C A4h 177 116 108 164 unsigned A8 XXXX XXXXh A6 . A8 0000 C54Ah B1 74 6C A4h A5 6A 32 11 93h 106 50 17 147 unsigned 177 116 108 164 unsigned 50506 unsigned
5-103
GMPY4
GMPY4
Syntax
Galois Field Multiply, Packed 8-Bit

GMPY4 (.unit) src1,src2, dst .unit = .M1, .M2
For operand type... Unit u4 xu4 u4 .M1, .M2
Opfield 10001
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
x
1
op
5
s
1
p
1
Description
The GMPY4 instruction performs the Galois field multiply on four values in src1 with four parallel values in src2. The four products are packed into dst. The values in both src1 and src2 are treated as unsigned, 8-bit packed data. For each pair of 8-bit quantities in src1 and src2, the unsigned, 8-bit value from src1 is Galois field multiplied with the unsigned, 8-bit value from src2. The product of src1 byte 0 and src2 byte 0 is written to byte0 of dst. The product of src1 byte 1 and src2 byte 1 is written to byte1 of dst. The product of src1 byte 2 and src2 byte 2 is written to byte2 of dst. The product of src1 byte 3 and src2 byte 3 is written to the most significant byte in dst.
5-104
GMPY4
31 ua_3 3
24
23 ua_2 2
16
15 ua_1 1
7 ua_0 0
src1 1
GMPY4
ub_3 b 3 ub_2 b 2 ub_1 b 1 ub_0 b 0
src2 2
31
24
23
16
15
0 ua_0 gmpy ub_0
ua_3 gmpy ub_3
ua_2 gmpy ub_2
ua_1 gmpy ub_1
dst
Note:
gmpy represents the Galois Field Operation
The size and polynomial are controlled by the Galois Field Polynomial Generator Function Register in the control register file. All registers in the control register file can be written using the MVC instruction. The default field generator polynomial is 0x1D, and the default size is 7. This setting is used for many communications standards. Note that the GMPY4 instruction is commutative, so: GMPY4 .M1 A10,A12,A13 ** is equivalent to ** GMPY4 .M1 Execution if (cond) { (ubyte0(src1) gmpy ubyte0(src2)) ubyte0(dst) (ubyte1(src1) gmpy ubyte1(src2)) ubyte1(dst) (ubyte2(src1) gmpy ubyte2(src2)) ubyte2(dst) (ubyte3(src1) gmpy ubyte3(src2)) ubyte3(dst) } else nop A12,A10,A13
5-105
GMPY4
Pipeline _____________________________________________ Pipeline Stage E1 E2 E3 E4
_____________________________________________ Read Written Unit in use .M
src1, src2 dst
_____________________________________________ Instruction Type Delay Slots See Also Example 1 Four-cycle 3 MVC, XOR GMPY4 .M1 A5,A6,A7; polynomial = 0x11d
Before instruction A5 45 23 00 01h 69 35 0 1 unsigned A6 57 34 00 01h 87 52 0 1 unsigned A7 XXXX XXXXh A6 . A7 72 92 00 01h 57 34 00 01h A5 4 cycles after instruction 45 23 00 01h 69 35 0 1 unsigned 87 52 0 1 unsigned 114 146 0 1 unsigned
Example 2
GMPY4 .M1 A5,A6,A7; field size is 256

Before instruction A5 FF FE 02 1Fh 255 254 2 31 unsigned A6 FF FE 02 01h 255 254 2 1 unsigned A7 XXXX XXXXh XXXX XXXXh A6 . A7 E2 E3 04 1Fh FF FE 02 01h A5 4 cycles after instruction FF FE 02 1Fh 255 254 2 31 unsigned 255 254 2 1 unsigned 226 227 4 31 unsigned
5-106
LDDW
LDDW
Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset
LDDW (.unit) *+baseR[offsetR/ucst5], dst .unit = .D1 or .D2
Syntax Opcode
31 29 28 27
23
22
18
17
13
12
3 1 2
2 0
creg
3
z
1
dst
4
baseR
5
offsetR/ucst5
5
mode
4
r
1
y
1
ld/st
3
s
1
p
1
Description
The LDDW instruction loads a 64-bit quantity from memory into a register pair dst_o:dst_e. Table 58 describes the addressing generator options. The memory address is formed from a base address register (baseR) and an optional offset that is either a register (offsetR) or a 5-bit unsigned constant (ucst5). Both offsetR and baseR must be in the same register file and on the same side as the .D unit used. The y bit in the opcode determines the .D unit and the register file used: y = 0 selects the .D1 unit and the baseR and offsetR from the A register file, and y = 1 selects the .D2 unit and baseR and offsetR from the B register file. The s bit determines the register file into which the dst is loaded: s = 0 indicates that dst is in the A register file, and s = 1 indicates that dst is in the B register file. The r bit has a value of 1 for the LDDW instruction and a value of 0 for all other load and store instructions. The dst field must always be an even value because LDDW loads register pairs. Therefore, bit 23 is always zero. Furthermore, the value of the ld/st field is110. The bracketed offsetR/ucst5 is scaled by a left-shift of 3 to correctly represent doublewords. After scaling, offsetR/ucst5 is added to or subtracted from baseR. For the preincrement, predecrement, positive offset, and negative offset address generator options, the result of the calculation is the address to be accessed in memory. For postincrement or postdecrement addressing, the shifted value of baseR before the addition or subtraction is the address to be accessed in memory. Increments and decrements default to 1 and offsets default to 0 when no bracketed register, bracketed constant, or constant enclosed in parentheses is specified. Square brackets, [ ], indicate that ucst5 is left shifted by 3. Parentheses, ( ), indicate that ucst5 is not left shifted. In other words, parentheses indicate a byte offset rather than a doubleword offset. You must type either brackets or parathesis around the specified offset if you use the optional offset parameter.
5-107
LDDW
The addressing arithmetic that performs the additions and subtractions defaults to linear mode. However, for A4A7 and for B4B7, the mode can be changed to circular mode by writing the appropriate value to the AMR. The destination register pair must consist of a consecutive even and odd register pair from the same register file. The instruction can be used to load a double-precision floating-point value (64 bits), a pair of single-precision floating-point words (32 bits), or a pair of 32-bit integers. The least significant 32 bits are loaded into the even-numbered register and the most significant 32 bits (containing the sign bit and exponent) are loaded into the next register (which is always odd-numbered register). The register pair syntax places the odd register first, followed by a colon, then the even register (that is, A1:A0, B1:B0, A3:A2, B3:B2, etc.). All 64 bits of the double-precision floating point value are stored in big- or littleendian byte order, depending on the mode selected. When LDDW is used to load two 32-bit single-precision floating-point values or two 32-bit integer values, the order is dependent on the endian mode used. In little-endian mode, the first 32-bit word in memory is loaded into the even register. In big-endian mode, the first 32-bit word in memory is loaded into the odd register. Regardless of the endian mode, the double word address must be on a doubleword boundary (the three LSBs are zero). Table 58 summarizes the address generation options supported.

Execution
if (cond) else
mem dst nop
5-108
LDDW
Pipeline
E1 baseR offsetR baseR .D
E2
E3
E4
E5
dst
Load 4 1
LDDW .D2
Before instruction
*+B10[1],A1:A0
5 cycles after instruction A1:A0 4021 3333h 16 B10 0000 0010h mem 0x18 3333 3333h 4021 3333h 3333 3333h 16
A1:A0 XXXX XXXXh B10 0000 0010h mem 0x18 3333 3333h
XXXX XXXXh
4021 3333h
8.6
Little-endian mode
Example 2
LDDW .D1
Before instruction
*++A10[1],A1:A0
1 cycle after instruction A1:A0 XXXX XXXXh 16 A10 0000 0018h mem 0x18 4021 3333h 3333 3333h XXXX XXXXh 24
A1:A0 XXXX XXXXh A10 0000 0010h mem 0x18 4021 3333h
XXXX XXXXh
3333 3333h
8.6
5 cycles after instruction A1:A0 4021 3333h A10 0000 0018h mem 0x18 4021 3333h 3333 3333h 3333 3333h 24
Big-endian mode
5-109
LDNDW
LDNDW
Syntax
Load Non-Aligned Double Word

LDNDW (.unit) *mem, dst .unit = .D1, .D2 Opcode map field used... For operand type... Unit uint uint ullong uint ucst5 ullong .D1, .D2 Opfield
baseR offset dst baseR offset dst

Opcode
31 29 28 27 24 23 22 18 17
.D1 .D2
13
12
3 0 2
2 1
creg
3
z
1
dst
4
sc
1
baseR
5
offset
5
mode
4
r
1
y
1
ld/st
3
s
1
p
1
Description
The LDNDW instruction loads a 64-bit quantity from memory into a register pair, dst_o:dst_e. The table below describes the addressing generator options. The LDNDW instruction may read a 64-bit value from any byte boundary. Thus alignment to a 64-bit boundary is not required. The memory effective address is formed from a base address register (baseR) and an optional offset that is either a register (offsetR) or a 5-bit unsigned constant (ucst5). Both offsetR and baseR must be in the same register file, and on the same side, as the .D unit used. The y bit in the opcode determines the .D unit and register file used: y = 0 selects the .D1 unit and baseR and offsetR from the A register file, and y = 1 selects the .D2 unit and baseR and offsetR from the B register file. The LDNDW instruction supports both scaled offsets and non-scaled offsets. The sc field is used to indicate whether the offsetR/ucst5 is scaled or not. If sc is 1 (scaled), the offsetR/ucst5 is shifted left 3 bits before adding or subtracting from the baseR. If sc is 0 (non-scaled), the offsetR/ucst5 is not shifted before adding or subtracting from the baseR. For the pre-increment, pre-decrement, positive offset, and negative offset address generator options, the result of the calculation is the address to be accessed in memory. For post-increment or postdecrement addressing, the value of baseR before the addition or subtraction is the address to be accessed from memory. The addressing arithmetic that performs the additions and subtractions defaults to linear mode. However, for A4A7 and for B4B7, the mode can be changed to circular mode by writing the appropriate value to the AMR.
5-110
LDNDW
The dst field of the instruction selects a register pair, a consecutive even-numbered and odd-numbered register pair from the same register file. The instruction can be used to load a pair of 32-bit integers. The least significant 32 bits are loaded into the even-numbered register and the most significant 32 bits are loaded into the next register (which is always an odd-numbered register). The dst can be in either register file, regardless of the .D unit or baseR or offsetR used. The s bit determines which file dst will be loaded into: s = 0 indicates dst will be in the A register file and s = 1 indicates dst will be loaded in the B register file.
Table 59. LDNDW Address Generator Options

Note: No other memory access may be issued in parallel with a non-aligned memory access. The other .D unit can be used in parallel as long as it is not performing a memory access.
5-111
LDNDW
Assembler Notes When no bracketed register or constant is specified, the assembler defaults increments and decrements to 1 and offsets to 0. Loads that do no modification to the baseR can use the assembler syntax *R. Square brackets, [ ], indicate that the ucst5 offset is left-shifted by 3 for double word loads. Parentheses, ( ), can be used to tell the assembler that the offset is a nonscaled offset. For example, LDNDW (.unit) *+baseR (14) dst represents an offset of 14 bytes, and the assembler writes out the instruction with offsetC = 14 and sc = 0. LDNDW (.unit) *+baseR [16] dst represents an offset of 16 double words, or 128 bytes, and the assembler writes out the instruction with offsetC = 16 and sc = 1. Either brackets or parentheses must be typed around the specified offset if the optional offset parameter is used. Execution if (cond) { mem dst } else nop Pipeline __________________________________________ Pipeline Stage E1 E2 E3 E4 E5
__________________________________________ Read
baseR, offsetR
Written Unit in use
baseR
.D
dst
__________________________________________ Instruction Type Delay Slots Load 4 for loaded value 0 for address modification from pre/post increment/decrement LDNW, STNDW, STNW
See Also
5-112
LDNDW
Example 1
Before instruction A0 0000 1001h A0
LDNDW .D1
*A0++, A3:A2
1 cycle after instruction 0000 1009h A0 5 cycles after instruction 0000 1009h
A3:A2
XXXX XXXXh
XXXh
A3:A2
XXXX XXXXh
XXXX XXXh
A3:A2
5E1C 4F29h
A812 B6C5h little endian
Byte Memory Address Data Value
100C 11
100B 05
100A 69
1009 34
1008 5E
1007 1C
1006 4F
1005 29
1004 A8
1003 12
1002 B6
1001 C5
1000 D4
Example 2
LDNDW .D1
*A0++, A3:A2
1 cycle after instruction 5 cycles after instruction A0 0000 100Bh
A0
0000 100Bh
A3:A2
XXXX XXXXh
XXXX XXXXh
A3:A2
XXXX XXXXh
XXXX XXXXh
A3:A2
6934 5E1Ch
4F29 A812h little endian
100C 11
100B 05
100A 69
1009 34
1008 5E
1007 1C
1006 4F
1005 29
1004 A8
1003 12
1002 B6
1001 C5
1000 D4
5-113
LDNW
LDNW
Syntax
Load Non-Aligned Word

LDNW (.unit) *mem, dst .unit = .D1, .D2
For operand type... Unit uint uint int uint ucst5 int .D1, .D2
Opfield
baseR offset dst baseR offset dst

Opcode
31 29 28 27 23 22 18 17
.D1 .D2
13
12
6 0
5 1 3
4 1
3 0 2
2 1
creg
3
z
1
dst
5
baseR
5
offset
5
mode
4
r
1
y
1
s
1
p
1
Description
The LDNW instruction loads a 32-bit quantity from memory into a 32-bit register, dst. The table below describes the addressing generator options. The LDNW instruction may read a 32-bit value from any byte boundary. Thus alignment to a 32-bit boundary is not required. The memory effective address is formed from a base address register (baseR), and an optional offset that is either a register (offsetR) or a 5-bit unsigned constant (ucst5). If an offset is not given, the assembler assigns an offset of zero. Both offsetR and baseR must be in the same register file, and on the same side, as the .D unit used. The y bit in the opcode determines the .D unit and register file used: y = 0 selects the .D1 unit and baseR and offsetR from the A register file, and y = 1 selects the .D2 unit and baseR and offsetR from the B register file. The offsetR/ucst5 is scaled by a left shift of 2 bits. After scaling, offsetR/ucst5 is added to, or subtracted from, baseR. For the pre-increment, pre-decrement, positive offset, and negative offset address generator options, the result of the calculation is the address to be accessed in memory. For post-increment or post-decrement addressing, the value of baseR before the addition or subtraction is the address to be accessed from memory. The addressing arithmetic that performs the additions and subtractions defaults to linear mode. However, for A4A7 and for B4B7, the mode can be changed to circular mode by writing the appropriate value to the AMR.
5-114
LDNW
The dst can be in either register file, regardless of the .D unit or baseR or offsetR used. The s bit determines which file dst will be loaded into: s = 0 indicates dst will be in the A register file and s = 1 indicates dst will be loaded in the B register file. r is always zero.
Table 510. LDNW Address Generator Options

Note: No other memory access may be issued in parallel with a non-aligned memory access. The other .D unit can be used in parallel, as long as it is not doing a memory access. Assembler Notes When no bracketed register or constant is specified, the assembler defaults increments and decrements to 1 and offsets to 0. Loads that do no modification to the baseR can use the assembler syntax *R. Square brackets, [ ], indicate that the ucst5 offset is left-shifted by 2 for word loads. Parentheses, ( ), can be used to tell the assembler that the offset is a nonscaled, constant offset. The assember right shifts the constant by 2 bits for word loads before using it for the ucst5 field. After scaling by the LDNW instruction, this results in the same constant offset as the assembler source if the least significant two bits are zeros.
5-115
LDNW
For example, LDNW (.unit) *+baseR (12) dst represents an offset of 12 bytes (3 words), and the assembler writes out the instruction with ucst5 = 3. LDNW (.unit) *+baseR [12] dst represents an offset of 12 words, or 48 bytes, and the assembler writes out the instruction with ucst5 = 12. Either brackets or parentheses must be typed around the specified offset if the optional offset parameter is used. Execution if (cond) { mem dst } else nop Pipeline __________________________________________ Pipeline Stage E1 E2 E3 E4 E5
__________________________________________ Read
baseR, offsetR
Written Unit in use
baseR
.D
dst
__________________________________________ Instruction Type Delay Slots Load 4 for loaded value 0 for address modification from pre/post increment/decrement LDNDW, STNDW, STNW
See Also
5-116
LDNW
Example 1
Before instruction A0 0000 1001h A0
LDNW
.D1
*A0++, A2
1 cycle after instruction 0000 1005h A0 5 cycles after instruction 0000 1005h
A2
XXXX XXXXh
A2
XXXX XXXXh
A2
A812 B6C5h
Little endian
1007 1C
1006 4F
1005 29
1004 A8
1003 12
1002 B6
1001 C5
1000 D4
Example 2
LDNW
.D1
*A0++, A2
1 cycle after instruction 5 cycles after instruction A0 0000 1007h
A0
0000 1007h
A2
XXXX XXXXh
A2
XXXX XXXXh
A2
4F29 A812h
Little endian
1007 1C
1006 4F
1005 29
1004 A8
1003 12
1002 B6
1001 C5
1000 D4
5-117
MAX2
MAX2
Syntax
Maximum, Signed Packed 16-Bit

MAX2 (.unit) src1,src2, dst .unit = .L1, .L2
For operand type... Unit s2 xs2 s2 .L1, .L2
Opfield 1000010
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11
4 1
3 1 3
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
Description
The MAX2 instruction performs a maximum operation on packed signed 16-bit values. For each pair of signed 16-bit values in src1 and src2, MAX2 places the larger value in the corresponding position in dst.
16 a_hi MAX2 b_hi b_lo 15 a_lo 0
31
src1
src2
31 (a_hi > b_hi)? a_hi : b_hi
16 15 (a_lo > b_lo)? a_lo : b_lo
dst
5-118
MAX2
Execution
if (cond) {
if (lsb16(src1) >= lsb16(src2), lsb16(src1) lsb16(dst) else lsb16(src2) lsb16(dst); if (msb16(src1) >= msb16(src2)), msb16(src1) msb16(dst) else msb16(src2) msb16(dst); } else nop Pipeline __________________________ Pipeline Stage E1
src1, src2 dst

.L
__________________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 MAXU4, MIN2, MINU4 MAX2 .L1 A2, A8, A9
1 cycle after instruction 14217 3526 A2 3789 F23Ah 14217 3526
Before instruction A2 3789 F23Ah
A8
04B8 4975h
1208 18805
A8
04B8 4975h
1208 18805
A9
XXXX XXXXh
A9
3789 4975h
14217 18805
5-119
MAX2
Example 2
MAX2
.L2X
A2, B8, B12

1 cycle after instruction 292 9297 A2 0124 2451h 292 9297
B8
01A6 A051h
422 24495
B8
01A6 A051h
422 24495
B12
XXXX XXXXh
B12
01A6 2451h
422 9297
5-120
MAXU4
MAXU4
Syntax
Maximum, Unsigned Packed 8-Bit

MAXU4 (.unit) src1,src2, dst .unit = .L1, .L2
For operand type... Unit u4 xu4 u4
Opfield
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
.L1, .L2 1000011
13
12 x 1
11
4 1
3 1 3
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
Description
The MAXU4 instruction performs a maximum operation on packed, unsigned 8-bit values. For each pair of unsigned 8-bit values in src1 and src2, MAXU4 places the larger value in the corresponding position in dst.
31 ua_3 24 23 ua_2 16 15 ua_1 8 7 ua_0 0
src1
MAXU4
ub_3 ub_2 ub_1 ub_0
src2
31
24 23
16 15
8 7
ua_3 > ub_3 ? ua_3 : ub_3
ua_2 > ub_2 ? ua_2 : ub_2
ua_1 > ub_1 ? ua_1 : ub_1
ua_0 > ub_0 ? ua_0 : ub_0
dst
5-121
MAXU4
Execution if (cond) { if (ubyte0(src1) >= ubyte0(src2), ubyte0(src1) ubyte0(dst) else ubyte0(src2) ubyte0(dst); if (ubyte1(src1) >= ubyte1(src2)), ubyte1(src1) ubyte1(dst) else ubyte1(src2) ubyte1(dst); if (ubyte2(src1) >= ubyte2(src2)), ubyte2(src1) ubyte2(dst) else ubyte2(src2) ubyte2(dst); if (ubyte3(src1) >= ubyte3(src2)), ubyte3(src1) ubyte3(dst) else ubyte3(src2) ubyte3(dst); } else nop Pipeline __________________________ Pipeline Stage E1
src1, src2 dst

.L
__________________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 MAX2, MIN2, MINU4 MAXU4 .L1 A2, A8, A9
1 cycle after instruction 55 137 242 58 unsigned A8 04 B8 49 75h 4 184 73 117 unsigned A9 XXXX XXXXh A9 37 B8 F2 75h A8 04 B8 49 75h A2 37 89 F2 3Ah 55 137 242 58 unsigned 4 184 73 117 unsigned 55 184 242 117 unsigned
Before instruction A2 37 89 F2 3Ah
5-122
MAXU4
Example 2
MAXU4
.L2X
A2, B8, B12

1 cycle after instruction 1 36 36 185 unsigned A2 01 24 24 B9h 1 36 36 185 unsigned B8 01 A6 A0 51h 1 166 160 81 unsigned B12 01 A6 A0 B9h 1 166 160 185 unsigned
Before instruction A2 01 24 24 B9h
B8
01 A6 A0 51h
1 166 160 81 unsigned
B12
XXXX XXXXh
5-123
MIN2
MIN2
Syntax
Minimum, Signed Packed 16-Bit

MIN2 (.unit) src1,src2, dst .unit = .L1, .L2
For operand type s2 xs2 s2
Unit .L1, .L2
Opfield 1000001
src1 src2 dst

Opcode
31 29 28 27 23 22 21 18 17
13
12 x 1
11
4 1
3 1 3
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
Description
The MIN2 instruction performs a minimum operation on packed, signed 16-bit values. For each pair of signed 16-bit values in src1 and src2, MAX2 places the smaller value in the corresponding position in dst.
31 a_hi
16 15 a_lo MIN2 b_hi b_lo
0
src1
src2
31 (a_hi < b_hi)? a_hi : b_hi
16 15 (a_lo < b_lo)? a_lo : b_lo
0
dst
5-124
MIN2
Execution if (cond) { if (lsb16(src1) <= lsb16(src2), lsb16(src1) lsb16(dst) else lsb16(src2) lsb16(dst); if (msb16(src1) <= msb16(src2)), msb16(src1) msb16(dst) else msb16(src2) msb16(dst);
}
else nop Pipeline __________________________ Pipeline Stage E1
src1, src2 dst

.L
__________________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 MAX2, MAXU4, MINU4 MIN2 .L1 A2, A8, A9
1 cycle after instruction A2 3789 F23Ah 14217 3526
Before instruction A2 3789 F23Ah 14217 3526
A8
04B8 4975h
1208 18805
A8
04B8 4975h
1208 18805
A9
XXXX XXXX h
A9
04B8 F23Ah
1208 3526
5-125
MIN2
Example 2
MIN2
.L2X
A2, B8, B12

1 cycle after instruction A2 0124 8003h 292 32765
Before instruction A2 0124 8003h 292 32765
B8
0A37 8001h
2615 32767
B8
0A37 8001h
2615 32767
B12
XXXX XXXX h
B12
0124 8001h
292 32767
5-126
MINU4
MINU4
Syntax
Minimum, Unsigned Packed 8-Bit

MINU4 (.unit) src1,src2, dst .unit = .L1, .L2
Opfield
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
.L1, .L2 1001000
13
12 x 1
11
4 1 1 3
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
Description
The MINU4 instruction performs a minimum operation on packed, unsigned 8-bit values. For each pair of unsigned 8-bit values in src1 and src2, MAXU4 places the smaller value in the corresponding position in dst.
31 ua_3 24 23 ua_2 16 15 ua_1 8 7 ua_0 0
src1
MINU4
ub_3 ub_2 ub_1 ub_0
src2
31
24 23
16 15
8 7
ua_3 < ub_3 ? ua_3 : ub_3
ua_2 < ub_2 ? ua_2 : ub_2
ua_1 < ub_1 ? ua_1 : ub_1
ua_0 < ub_0 ? ua_0 : ub_0
dst
5-127
MINU4
Execution if (cond) { if (ubyte0(src1) <= ubyte0(src2), ubyte0(src1) ubyte0(dst) else ubyte0(src2) ubyte0(dst); if (ubyte1(src1) <= ubyte1(src2)), ubyte1(src1) ubyte1(dst) else ubyte1(src2) ubyte1(dst); if (ubyte2(src1) <= ubyte2(src2)), ubyte2(src1) ubyte2(dst) else ubyte2(src2) ubyte2(dst); if (ubyte3(src1) <= ubyte3(src2)), ubyte3(src1) ubyte3(dst) else ubyte3(src2) ubyte3(dst); } else nop Pipeline _________________________ Pipeline Stage E1
src1, src2 dst

.L
__________________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 MAX2, MAXU4, MIN2 MINU4 .L1 A2, A8, A9
1 cycle after instruction A2 37 89 F2 3Ah 55 137 242 58 unsigned A8 04 B8 49 75h 4 184 73 117 unsigned A9 04 89 49 3Ah 4 137 73 58 unsigned
Before instruction A2 37 89 F2 3Ah 55 137 242 58 unsigned A8 04 B8 49 75h 4 184 73 117 unsigned A9 XXXX XXXXh
5-128
MINU4
Example 2 MINU4 .L2 B2, B8, B12
Before instruction B2 01 24 24 B9h 1 36 36 185 unsigned B8 01 A6 A0 51h 1 166 160 81 unsigned B12 XXXX XXXXh B12 01 24 24 51h B8 01 A6 A0 51h B2 1 cycle after instruction 01 24 24 B9h 1 36 36 185 unsigned 1 166 160 81 unsigned 1 36 36 81 unsigned
5-129
MPY2
MPY2
Syntax
Multiply Signed by Signed, Packed 16-Bit

MPY2 (.unit) src1,src2, dst .unit = .M1, .M2
For operand type... Unit s2 xs2 ullong .M1, .M2
Opfield 00000
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
5
s
1
p
1
Description
The MPY2 instruction performs two 16-bit by 16-bit multiplications between two pairs of signed, packed 16-bit values. The values in src1 and src2 are treated as signed, packed 16-bit quantities. The 32-bit results are written into a 64-bit register pair. The product of the lower half-words of src1 and src2 is written to the even destination register, dst_e. The product of the upper half-words of src1 and src2 is written to the odd destination register, dst_o.
31 a_hi MPY2 b_hi b_lo
src2
16 15 a_lo
0
src1
=
63 a_hi*b_hi 32 31 a_lo*b_lo 0
dst_o:dst_e
This instruction helps reduce the number of instructions required to perform two 16-bit by 16-bit multiplies on both the lower and upper halves of two registers.
5-130
MPY2
The following code:
MPY MPYH .M1 .M1 A0, A1, A2 A0, A1, A3
may be replaced by:

MPY2 .M1 A0, A1, A3:A2
Execution
if (cond)
{ (lsb16(src1) x lsb16(src2)) dst_e (msb16(src1) x msb16(src2)) dst_o }
else nop Pipeline ______________________________________ Pipeline Stage E1 E2 E3 E4
______________________________________ Read Written Unit in use .M
src1, src2 dst
______________________________________ Instruction Type Delay Slots See Also Example 1 Four-cycle 3 MPYSU4 MPY2 .M1 A5,A6, A9:A8
4 cycles after instruction 27186 4499 A5 6A32 1193h 27186 4499
A6
B174 6CA4h
20108 27812
A6
B174 6CA4h
20108 27812
A9:A8
XXXX XXXXh
XXXX XXXXh
A9:A8
DF6A B0A8h 546,656,088
0775 462h 125,126,188
5-131
MPY2
Example 2 MPY2 .M2 B2, B5, B9:B8
Before instruction B2 1234 3497h 4660 13463 B2 4 cycles after instruction 1234 3497h 4660 13463
B5
21FF 50A7h
8703 20647
B5
21FF 50A7h
8703 20647
B9:B8
XXXX XXXXh
XXXX XXXXh
B9:B8
026A D5CCh 40,555,980
1091 7E81h 277,970,561
5-132
MPYHI
MPYHI
Syntax
Multiply 16 MSB x 32-Bit Into 64-Bit Result

MPYHI (.unit) src1,src2, dst .unit = .M1, .M2
For operand type int xint sllong
Unit .M1, .M2
Opfield 10100
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
5
s
1
p
1
Description
The MPYHI instruction performs a 16-bit by 32-bit multiply. The upper half of src1 is used as a 16-bit signed input. The value in src2 is treated as a 32-bit signed value. The result is written into the lower 48 bits of a 64-bit register pair, dst_o:dst_e, and sign extended to 64 bits. if (cond) { ((msb16 (src1)) x src2) dst_o:dst_e } else nop
Execution
5-133
MPYHI
src1, src2 dst
__________________________________________ Instruction Type Delay Slots See Also Example 1 Four-cycle 3 MPYLI MPYHI .M1 A5,A6,A9:A8
6A32 1193h
27186
6A32 1193h
27186
A6
B174 6CA4h
1,317,770,076
A6
B174 6CA4h
1,317,770,076
A9:A8
XXXX XXXXh
XXXX XXXXh
A9:A8
FFFF DF6Ah
DDB9 2008h
358,248,997,286,136
5-134
MPYHI
Example 2
MPYHI
.M2
B2,B5,B9:B8
1234 3497h
4660
1234 3497h
4660
B5
21FF 50A7h
570,380,455
B5
21FF 50A7h
570,380,455
B9:B8
XXXX XXXXh
XXXX XXXXh
B9:B8
0000 026Ah
DB88 1FECh
2,657,972,920,300
5-135
MPYHIR
MPYHIR
Multiply 16 MSB x 32-Bit, Shifted by 15 to Produce a Rounded 32-Bit Result

MPYHIR (.unit) src1,src2, dst .unit = .M1, .M2
Syntax
For operand type int xint int
Unit .M1, .M2
Opfield 10000
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
5
s
1
p
1
Description
The MPYHIR instruction performs a 16-bit by 32-bit multiply. The upper half of src1 is treated as a 16-bit signed input. The value in src2 is treated as a 32-bit signed value. The product is then rounded to a 32-bit result by adding the value 214 and then this sum is right shifted by 15. The lower 32 bits of the result are written into dst.
31 a_hi MPYHIR b_hi b_lo
src2
16 15 a_lo
0
src1
=
31 ((a_hi x b_hi:b_lo) + 0x4000) >> 15 0
dst
Execution
if (cond)
{ lsb32(((msb16(src1) x (src2)) + 0x4000)>>15) dst }
else nop
5-136
MPYHIR
src1, src2 dst
__________________________________________ Instruction Type Delay Slots See Also Example Four-cycle 3 MPYLIR MPYHIR .M2 B2,B5,B9
1234 3497h
4660
B2
1234 3497h
4660
B5
21FF 50A7h
570,380,455
B5
21FF 50A7h
570,380,455
B9
XXXX XXXXh
B9
04D5 B710h
81,114,896
5-137
MPYIH
MPYIH
Syntax
Multiply 32 x High 16-Bit Into 64-Bit Result (Pseudo-Operation)

MPYIH (.unit) src2, src1, dst .unit = .M1, .M2
Unit .M1, .M2
Opfield 10100
src1 src2 dst

Opcode Description See MPYHI instruction.
The MPYIH pseudo-operation performs a 16-bit by 32-bit multiply. The upper half of src1 is used as a 16-bit signed input. The value in src2 is treated as a 32-bit signed value. The result is written into the lower 48 bits of a 64-bit register pair, dst_o:dst_e, and sign extended to 64 bits. The assembler uses the MPYHI src1, src2, dst instruction to perform this task. if (cond) { (src2 x msb16 (src1)) dst_o:dst_e } else nop
Execution
Pipeline
__________________________________________ Pipeline Stage E1 E2 E3 E4
src1, src2 dst
__________________________________________ Instruction Type Delay Slots See Also

5-138
Four-cycle 3 MPYHI, MPYIL
MPYIHR
MPYIHR
Multiply 32-Bit X High 16-bit, Shifted by 15 to Produce a Rounded 32-Bit Result (Pseudo-Operation)
MPYIHR (.unit) src2, src1, dst .unit = .M1, .M2
Syntax
Unit .M1, .M2
Opfield 10000
src1 src2 dst

Opcode Description See MPYHIR instruction.
The MPYIHR pseudo-operation performs a 16-bit by 32-bit multiply. The upper half of src1 is treated as a 16-bit signed input. The value in src2 is treated as a 32-bit signed value. The product is then rounded to a 32-bit result by adding the value 214 and then this sum is right shifted by 15. The lower 32 bits of the result are written into dst. The assembler uses the MPYHIR src1, src2, dst instruction to perform this operation.
if (cond)
Execution
{ lsb32((((src2) x msb16(src1)) + 0x4000) >> 15) dst }
else nop Pipeline __________________________________________ Pipeline Stage E1 E2 E3 E4
src1, src2 dst
__________________________________________ Instruction Type Delay Slots See Also Four-cycle 3 MPYHIR, MPYILR
5-139
MPYIL
MPYIL
Syntax
Multiply 32 x Low 16-Bit Into 64-Bit Result (Pseudo-Operation)

MPYIL (.unit) src2, src1, dst .unit = .M1, .M2
Unit .M1, .M2
Opfield 10101
src1 src2 dst

Opcode Description See MPYLI instruction.
The MPYIL pseudo-operation performs a 16-bit by 32-bit multiply. The lower half of src1 is used as a 16-bit signed input. The value in src2 is treated as a 32-bit signed value. The result is written into the lower 48 bits of a 64-bit register pair, dst_o:dst_e, and sign extended to 64 bits. The assembler uses the MPYLI src1, src2, dst instruction to perform this operation. if (cond) { ((src2) x lsb16(src1)) dst_o:dst_e } else nop
Execution
Pipeline
src1, src2 dst
__________________________________________ Instruction Type Delay Slots See Also

5-140
Four-cycle 3 MPYIH, MPYLI
MPYILR
MPYILR
Multiply 32-Bit x Low 16, Shifted by 15 to Produce a Rounded 32-Bit Result (Pseudo-Operation)
MPYILR (.unit) src2, src1, dst .unit = .M1, .M2
Syntax
Unit .M1, .M2
Opfield 01110
src1 src2 dst

Opcode Description See MPYLIR instruction.
The MPYILR pseudo-operation performs a 16-bit by 32-bit multiply. The lower half of src1 is used as a 16-bit signed input. The value in src2 is treated as a 32-bit signed value. The product is then rounded to a 32-bit result by adding the value 214 and then this sum is right shifted by 15. The lower 32 bits of the result are written into dst. The assembler uses a MPYLIR src1, src2, dst instruction to perform this operation. if (cond) { lsb32((((src2) x lsb16(src1)) + 0x4000) >> 15) dst } else nop
Execution
Pipeline
src1, src2 dst
__________________________________________ Instruction Type Delay Slots See Also Four-cycle 3 MPYIHR, MPYLIR
5-141
MPYLI
MPYLI
Syntax
Multiply 16 LSB x 32-Bit Into 64-Bit Result

MPYLI (.unit) src1,src2, dst .unit = .M1, .M2
Unit .M1, .M2
Opfield 10101
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2 5
src1
5
op
5
s
1
p
1
Description
The MPYLI instruction performs a 16-bit by 32-bit multiply. The lower half of src1 is used as a 16 bit signed input. The value in src2 is treated as a 32-bit signed value. The result is written into the lower 48 bits of a 64-bit register pair, dst_o:dst_e, and sign extended to 64 bits. if (cond) { (lsb16(src1) x (src2)) dst_o : dst_e } else nop
Execution
Pipeline
src1, src2 dst
__________________________________________ Instruction Type Delay Slots

5-142
Four-cycle 3
MPYLI
See Also Example 1 MPYHI MPYLI .M1 A5,A6,A9:A8
6A32 1193h 4499
6A32 1193h
4499
A6
B174 6CA4h 1,317,770,076
A6 .
B174 6CA4h
1,317,770,076
A9:A8
XXXX XXXXh XXXX XXXXh
A9:A8
FFFF FA9Bh
A111 462Ch
5,928,647,571,924
Example 2
MPYLI
.M2
B2,B5,B9:B8
1234 3497h
13463
B2
1234 3497h
13463
B5
21FF 50A7h
570,380,455
B5
21FF 50A7h
570,380,455
B9:B8
XXXX XXXXh
XXXX XXXXh
B9:B8
0000 06FBh
E9FA 7E81
7,679,032,065,665
5-143
MPYLIR
MPYLIR
Multiply 16 LSB x 32-Bit, Shifted by 15 to Produce a Rounded 32-Bit Result

MPYLIR (.unit) src1,src2, dst .unit = .M1, .M2
Syntax
Unit .M1, .M2
Opfield 01110
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
5
s
1
p
1
Description
The MPYLIR instruction performs a 16-bit by 32-bit multiply. The lower half of src1 is treated as a 16-bit signed input. The value in src2 is treated as a 32-bit signed value. The product is then rounded into a 32-bit result by adding the value 214 and then this sum is right shifted by 15. The lower 32 bits of the result are written into dst.
31 a_hi MPYLIR b_hi b_lo
src2
16
15 a_lo
0
src1
=
31 ((a_lo * b_hi:b_lo) + 0x4000)) >> 15) 0
dst
Execution
if (cond)
{ lsb32(((lsb16(src1) x (src2)) + 0x4000) >> 15) dst }
else nop
5-144
MPYLIR
src1, src2 dst
__________________________________________ Instruction Type Delay Slots See Also Example Four-cycle 3 MPYHIR MPYLIR .M2 B2,B5,B9
1234 3497h
13463
1234 3497h
13463
B5
21FF 50A7h
570,380,455
B5
21FF 50A7h
570,380,455
B9
XXXX XXXXh
B9
0DF7 D3F5h
234,345,461
5-145
MPYSU4
MPYSU4
Syntax
Multiply Signed by Unsigned Packed, 8-Bit

MPYSU4 (.unit) src1,src2, dst .unit = .M1, .M2
For operand type s4 xu4 dws4
Unit .M1, .M2
Opfield 00101
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
5
s
1
p
1
Description
The MPYSU4 instruction returns the product between four sets of packed 8-bit values producing four signed 16-bit results. The four signed 16-bit results are packed into a 64-bit register pair, dst_o:dst_e. The values in src1 are treated as signed packed 8-bit quantities, whereas the values in src2 are treated as unsigned 8-bit packed data. For each pair of 8-bit quantities in src1 and src2, the signed 8-bit value from src1 is multiplied with the unsigned 8-bit value from src2. The product of src1 byte 0 and src2 byte 0 is written to the lower half of dst_e. The product of src1 byte 1 and src2 byte 1 is written to the upper half of dst_e. The product of src1 byte 2 and src2 byte 2 is written to the lower half of dst_o. The product of src1 byte 3 and src2 byte 3 is written to the upper half of dst_o.
31 sa_3 3
24
23 sa_2 2
16
15 sa_1 1
7 sa_0 0
src1 1
MPYSU4 b 3 ub_3 b 2 ub_2 b 1 ub_1 b 0 ub_0
2 src2
=
63 48 sa_3*ub_3 47 32 sa_2*ub_2 31 16 sa_1*ub_1 15 sa_0*ub_0 0
dst_o:dst_e
5-146
MPYSU4
Execution if (cond) { (sbyte0(src1) x ubyte0(src2)) lsb16(dst_e) (sbyte1(src1) x ubyte1(src2)) msb16(dst_e) (sbyte2(src1) x ubyte2(src2)) lsb16(dst_o) (sbyte3(src1) x ubyte3(src2)) msb16(dst_o) } else nop Pipeline __________________________________________ Pipeline Stage E1 E2 E3 E4
src1, src2 dst
__________________________________________
Instruction Type Delay Slots See Also Example 1
Four-cycle 3 MPYU4 MPYSU4 .M1 A5,A6,A9:A8

4 cycles after instruction 106 50 17 109 signed A5 6A 32 11 93h 106 50 17 109 signed A6 . A9:A8 49A4 16A8h 18762 5800 B1 74 6C A4h 177 116 108 164 unsigned 072C BA2Ch 1386 17876 signed
A6
B1 74 6C A4h
177 116 108 164 unsigned
A9:A8
XXXX XXXXh
XXXX XXXXh
5-147
MPYSU4
Example 2
MPYSU4
.M2
B2,B5,B9:B8
4 cycles after instruction 63 -10 80 16 signed A5 3F F6 50 10h 63 -10 80 16 signed A6 . A9:A8 2FFD FCA4h 12285 680 C3 56 02 44h 195 86 2 68 unsigned 00A0 0440h 160 1088 signed
Before instruction A5 3F F6 50 10h
A6
C3 56 02 44h
195 86 2 68 unsigned
A9:A8
XXXX XXXXh
XXXX XXXXh
5-148
MPYUS4
MPYUS4
Syntax
Multiply Unsigned by Signed Packed, 8-Bit (Pseudo-Operation)

MPYUS4 (.unit) src2, src1, dst .unit = .M1, .M2
For operand type s4 xu4 dws4
Unit .M1, .M2
Opfield 00101
src1 src2 dst

Opcode Description See MPYSU4 instruction.
The MPYUS4 pseudo-operation returns the product between four sets of packed 8-bit values, producing four signed 16-bit results. The four signed 16-bit results are packed into a 64-bit register pair, dst_o:dst_e. The values in src1 are treated as signed packed 8-bit quantities, whereas the values in src2 are treated as unsigned 8-bit packed data. The assembler uses the MPYSU4 src1, src2, dst instruction to perform this operation. For each pair of 8-bit quantities in src1 and src2, the signed 8-bit value from src1 is multiplied with the unsigned 8-bit value from src2. The product of src1 byte 0 and src2 byte 0 is written to the lower half of dst_e. The product of src1 byte 1 and src2 byte 1 is written to the upper half of dst_e. The product of src1 byte 2 and src2 byte 2 is written to the lower half of dst_o. The product of src1 byte 3 and src2 byte 3 is written to the upper half of dst_o.
Execution
if (cond)
{ (ubyte0(src2) x sbyte0(src1)) lsb16(dst_e) (ubyte1(src2) x sbyte1(src1)) msb16(dst_e) (ubyte2(src2) x sbyte2(src1)) lsb16(dst_o) (ubyte3(src2) x sbyte3(src1)) msb16(dst_o) }
else nop
5-149
MPYUS4
src1, src2 dst
__________________________________________ Instruction Type Delay Slots See Also Four-cycle 3 MPYSU4, MPYU4
5-150
MPYU4
MPYU4
Syntax
Multiply Unsigned by Unsigned Packed, 8-Bit

MPYU4 (.unit) src1,src2, dst .unit = .M1, .M2
For operand type s4 xu4 dwu4
Unit .M1, .M2
Opfield 00100
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
5
s
1
p
1
Description
The MPYU4 instruction returns the product between four sets of packed 8-bit values producing four unsigned 16-bit results that are packed into a 64-bit register pair, dst_o:dst_e. The values in both src1 and src2 are treated as unsigned 8-bit packed data. For each pair of 8-bit quantities in src1 and src2, the unsigned 8-bit value from src1 is multiplied with the unsigned 8-bit value from src2. The product of src1 byte 0 and src2 byte 0 is written to the lower half of dst_e. The product of src1 byte 1 and src2 byte 1 is written to the upper half of dst_e. The product of src1 byte 2 and src2 byte 2 is written to the lower half of dst_o. The product of src1 byte 3 and src2 byte 3 is written to the upper half of dst_o.
31 ua_3 3
24
23 ua_2 2
16
15 ua_1 1
7 ua_0 0
src1 1
MPYU4 b 3 ub_3 b 2 ub_2 b 1 ub_1 b 0 ub_0
2 src2
=
63 48 ua_3*ub_3 47 32 ua_2*ub_2 31 16 ua_1*ub_1 15 ua_0*ub_0 0
dst_o:dst_e
5-151
MPYU4
Execution if (cond) { (ubyte0(src1) x ubyte0(src2)) lsb16(dst_e) (ubyte1(src1) x ubyte1(src2)) msb16(dst_e) (ubyte2(src1) x ubyte2(src2)) lsb16(dst_o) (ubyte3(src1) x ubyte3(src2)) msb16(dst_o) } else nop Pipeline __________________________________________ Pipeline Stage E1 E2 E3 E4
src1, src2 dst
__________________________________________ Instruction Type Delay Slots See Also Example 1 Four-cycle 3 MPYSU4 MPYU4 .M1 A5,A6,A9:A8
4 cycles after instruction 104 50 193 147 unsigned A6 B1 74 2C ABh 177 116 44 171 unsigned A9:A8 XXXX XXXXh XXXX XXXXh A6 . A9:A8 47E8 16A8h 18408 5800 B1 74 2C ABh A5 68 32 C1 93h 104 50 193 147 unsigned 177 116 44 171 unsigned 212C 6231h 8492 25137 unsigned
Before instruction A5 68 32 C1 93h
5-152
MPYU4
Example 2
MPYU4
.M2
B2,B5,B9:B8
4 cycles after instruction 61 230 80 127 unsigned B2 3D E6 50 7Fh 61 230 80 127 unsigned B5 . B9:B8 2E77 4D44h 11895 19780 C3 56 02 44h 195 86 2 68 unsigned 00A0 21BCh 160 8636 unsigned
Before instruction B2 3D E6 50 7Fh
B5
C3 56 02 44h
195 86 2 68 unsigned
B9:B8
XXXX XXXXh
XXXX XXXXh
5-153
MVD
MVD
Syntax
Move From Register to Register, Delayed

MVD (.unit) src2, dst .unit = .M1, .M2
For operand type xint int
Unit .M1, .M2
Opfield 11010
src2 dst
Opcode
31 30 29 28 27 23 22 18 17
13
12 x 1
11 0
10 0
9 0
8 0
7 1 10
6 1
5 1
4 1
3 0
2 0
creg
3
z
1
dst
5
src
5
op
5
s
1
p
1
Description
The MVD instruction moves data from the src2 register to the dst register over 4 cycles. This is done using the multiplier path.
MVD NOP NOP NOP .M2x A0,B0 ; ; ; ; B0 = A0
Execution
if (cond) src2 dst else nop
Pipeline
src2 dst
__________________________________________
5-154
MVD
Instruction Type Delay Slots Example Four-cycle 3 MVD .M2X A5,B8
4 cycles after instruction A5 6A32 1193h
B8
XXXX XXXXh
B8
6A32 1193h
5-155
MVK/MVKL
MVK/MVKL
Syntax
Move a Signed Constant Into a Register and Sign-Extend

MVK (.unit) cst, dst .unit = .L1 or .L2, .S1 or .S2, .D1 or .D2
For operand type scst16 sint scst5 sint scst5 sint
Unit .S1, .S2 .L1, .L2 .D1, .D2
Opfield
cst dst cst dst cst dst

Opcode
00101 000000
.S Unit
31 29 28 27 23 22 7 6 0 5 1 4 0 5 3 1 2 0 1 0
creg
3
z
1
dst
5
scst16
16
s
1
p
1
.L Unit
31 29 28 27 23 22 18 17 13 12 x 1 11 0 10 0 9 1 8 1 7 0 10 6 1 5 0 4 1 3 1 2 0 1 0
creg
3
z
1
dst
5
scst
5
op
5
s
1
p
1
.D Unit
31 29 28 27 23 22 18 17 13 12 7 6 1 5 0 4 0 5 3 0 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1/scst
5
op
6
s
1
p
1
Description
In the MVK/MVKL instruction, the cst (constant) is sign extended and placed in dst. The .S unit form allows for a 16-bit signed constant. This is the same MVK instruction that is found on the C62x but with the added flexibility of being able to perform this operation not only on the .S unit but also on the .L and .D units when the constant is limited to a 5-bit signed constant. Since many non-address constants fall into a 5-bit sign constant range, this allows the flexibility to schedule the MVK instruction on the .L or .D units. In
5-156
MVK/MVKL
the .D unit form, the constant is in the position normally used by src1, as for address math. Only the MVK instruction is supported on the .L or .D units. The .S unit supports both MVK and MVKL. In most cases, the C6000 assembler and linker issue a warning or an error when a constant is outside the range supported by the instruction. In the case of MVK .S, a warning is issued whenever the constant is outside the signed 16-bit range, 32768 to 32767 (or 0XFFFF8000 to 0x 00007FFF). For example:
MVK .S1 0x00008000X, A0
will generate a warning, whereas

MVK .S1 0 x FFFF8000, A0
will not generate a warning. The MVKL instruction is equivalent to the MVK instruction, except that the MVKL disables the constant range checking normally performed by the assembler/linker. This allows MVKL to be paired with MVKH to generate 32-bit constants. To load 32-bit constants, such as 0x1234 ABCD, use the following pair of instructions:
MVKL .S1 0x0ABCD, A4 MVKLH .S1 0x1234, A4
This could also be used:

MVKL MVKH .S1 0x1234ABCD, A4 .S1 0x1234ABCD, A4
Use this to load the address of a label:

MVKL .S2 label, B5 MVKH .S2 label, B5
Execution
if (cond) scst dst else nop
5-157
MVK/MVKL
Pipeline ____________________________ Pipeline Stage E1
_____________________________ Read Written Unit in use
dst
.L, .S, or .D
_____________________________ Instruction Type Delay Slots See Also Example 1 Single Cycle 0 MVKH, MVKLH MVK .L2 5,B8
1 cycle after instruction B8 FFFF FFFBh
Example 2
MVK
.D2
14,B8
1 cycle after instruction B8 0000 000Eh
Example 3
MVKL
.S1
5678h,A8
1 cycle after instruction A8 0000 5678h
Example 4
MVKL
.S1
0C678h,A8
1 cycle after instruction A8 FFFF C678h
5-158
OR
OR
Syntax
Bitwise OR
OR (.unit) src1, src2, dst .unit =.D1 or .D2, .L1, .L2, .S1, .S2, Opcode map field used... For operand type... Unit uint xuint uint scst5 xuint uint uint xint uint scst5 xuint uint uint xunit uint scst5 xuint uint .D1, .D2 Opfield 0001
src src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst
Opcode
.D1, .D2
0011
.L1, .L2
1111111
.L1, .L2
1111110
.S1, .S2
011011
.S1, .S2
011010
.D unit
31 29 28 27 23 22 18 17 13 12 x 1 11 1 2 10 0 9 6 5 1 4 1 4 3 0 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1/cst5
5
op
4
s
1
p
1
.L unit
31 29 28 27 23 22 18 17 13 12 x 1 11 5 4 1 3 1 3 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1/cst5
5
op
7
s
1
p
1
.S Unit
31 29 28 27 23 22 18 17 13 12 x 1 11 6 5 1 4 0 4 3 0 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1/cst5
5
op
6
s
1
p
1
5-159
OR
Description A bitwise OR instruction is performed between src1 and src2. The result is placed in dst. The scst5 operands are sign extended to 32 bits. This is the same OR instruction that is found on the C62x, but with the added flexibility of being able to perform this operation on the .D unit as well as the .L and .S units.
if (cond) src1 or src2 dst
Execution
src1, src2 dst

.L, .S, or .D
__________________________ Instruction Type Delay Slots See Also Example 1 Single Cycle 0 AND, ANDN, XOR OR .S1 A3,A4,A5
Before instruction A3 08A3 A49Fh A3 1 cycle after instruction 08A3 A49Fh
A4
00FF 375Ah
A4
00FF 375Ah
A5
XXXX XXXX h
A5
08FF B7DFh
5-160
OR
Example 2 OR .D2 12,B2,B8
Before instruction B2 0000 3A41h B2 1 cycle after instruction 0000 3A41h
B8
XXXX XXXXh
B8
FFFF FFF5h
5-161
PACK2
PACK2
Syntax
Pack 16 LSB, 16 LSB Into Packed 16-Bit

PACK2 (.unit) src1,src2, dst .unit = .L1, .L2 or .S1, .S2
For operand type i2 xi2 i2 i2 xi2 i2
Unit .L1, .L2
Opfield 0000000

Opcode
.S1 .S2
1111
.L unit
31 29 28 27 23 22 18 17 13 12 x 1 11 5 4 1 3 1 3 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
.S Unit
31 30 29 28 27 23 22 18 17 13 12 x 1 11 1 2 10 1 9 6 5 1 1 4 0 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
4
s
1
p
1
Description
The PACK2 instruction takes the lower half-words from src1 and src2 and packs them both into dst. The lower half-word of src1 is placed in the upper half-word of dst. The lower half-word of src2 is placed in the lower half-word of dst. This instruction is useful for manipulating and preparing pairs of 16-bit values to be used by the packed arithmetic operations, such as ADD2.
5-162
PACK2
31 a_hi
16
15 a_lo
0
src1
PACK2 b_hi b_lo

src2
31 a_lo
16
15 b_lo
0
dst
Execution
if (cond)
{ lsb16(src2) lsb16(dst) lsb16(src1) msb16(dst); }
else nop Pipeline _________________________ Pipeline Stage E1
src1, src2 dst

.L, .S
__________________________ Instruction Type Delay Slots See Also Single-cycle 0 PACKH2, PACKHL2, PACKLH2, SPACK2
5-163
PACK2
Example 1
PACK2
.L1
A2,A8,A9
1 cycle after instruction A2 3789 F23Ah
A8
04B8 4975h
A8
04B8 4975h
A9
XXXX XXXX h
A9
F23A 4975h
Example 2
PACK2
.S2
B2,B8,B12
1 cycle after instruction B2 0124 2451h
Before instruction B2 0124 2451h
B8
01A6 A051h
B8
01A6 A051h
B12
XXXX XXXXh
B12
2451 A051h
5-164
PACKH2
PACKH2
Syntax
Pack 16 MSB, 16 MSB Into Packed 16-Bit

PACKH2 (.unit) src1,src2, dst .unit = .L1, .L2 or .S1, .S2
For operand type i2 xi2 i2 i2 xi2 i2
Unit .L1, .L2
Opfield 0011110

Opcode
.S1 .S2
001001
.L unit
31 29 28 27 23 22 18 17 13 12 x 1 11 5 4 1 3 1 3 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
.S unit
31 29 28 27 23 22 18 17 13 12 x 1 11 6 5 1 4 0 4 3 0 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
6
s
1
p
1
Description
The PACKH2 instruction takes the upper half-words from src1 and src2 and packs them both into dst. The upper half-word of src1 is placed in the upper half-word of dst. The upper half-word of src2 is placed in the lower half-word of dst. This instruction is useful for manipulating and preparing pairs of 16-bit values to be used by the packed arithmetic operations, such as ADD2.
5-165
PACKH2
31 a_hi
16
15 a_lo
0
src1
PACKH2 b_hi b_lo

src2
31 a_hi
16
15 b_hi
0
dst
Execution
if (cond)
{ msb16(src2) lsb16(dst) msb16(src1) msb16(dst); }
else nop Pipeline _________________________ Pipeline Stage E1
src1, src2 dst

.L, .S
__________________________ Instruction Type Delay Slots See Also Single-cycle 0 PACK2, PACKHL2, PACKLH2, SPACK2
5-166
PACKH2
Example 1
PACKH2
.L1
A2,A8,A9
A8
04B8 4975h
A8
04B8 4975h
A9
XXXX XXXX h
A9
3789 04B8h
Example 2
PACKH2
.S2
B2,B8,B12
B8
01A6 A051h
B8
01A6 A051h
B12
XXXX XXXXh
B12
0124 01A6h
5-167
PACKH4
PACKH4
Syntax
Pack High Bytes of Four Half-Words Into Packed 8-Bit

PACKH4 (.unit) src1,src2, dst .unit = .L1, .L2 Opcode map field used... For operand type i4 xi4 i4 Unit .L1, .L2 Opfield 1101001
src1 src2 dst

Opcode
.L unit
31 29 28 27 23 22 18 17 13 12 x 1 11 5 4 2 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
1 1 0 s p 3 1 1
Description
The PACKH4 instruction moves the high bytes of the two half-words in src1 and src2 and packs them into dst. The bytes from src1 will be packed into the most significant bytes of dst, and the bytes from src2 will be packed into the least significant bytes of dst. Specifically, the high byte of the upper half-word of src1 is moved to the upper byte of the upper half-word of dst. The high byte of the lower half-word of src1 is moved to the lower byte of the upper half-word of dst. The high byte of the upper half-word of src2 is moved to the upper byte of the lower half-word of dst. The high byte of the lower half-word of src2 is moved to the lower byte of the lower half-word of dst.
31 a 3 a_3
24
23 a 2 a_2
16
15 a 1 a_1
7 a 0 a_0
src1
PACKH4
b_3 b 3 b_2 b 2 b_1 b 1 b_0 b 0
src2
31 a_3
24
23 a_1
16
15 b_3
7 b_1
dst
5-168
PACKH4
Execution if (cond) { byte3(src1) byte3(dst); byte1(src1) byte2(dst); byte3(src2) byte1(dst); byte1(src2) byte0(dst); } else nop Pipeline ________________________ Pipeline Stage E1
________________________ Read Written Unit in use
src1, src2 dst

.L
________________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 PACKL4, SPACKU4 PACKH4 .L1 A2,A8,A9
1 cycle after instruction A2 37 89 F2 3Ah
Before instruction A2 37 89 F2 3Ah
A8
04 B8 49 75h
A8
04 B8 49 75h
A9
XXXX XXXXh
A9
37 F2 04 49h
5-169
PACKH4
Example 2
PACKH4
.L2
B2,B8,B12
1 cycle after instruction B2 01 24 24 51h
Before instruction B2 01 24 24 51h
B8
01 A6 A0 51h
B8
01 A6 A0 51h
B12
XXXX XXXXh
B12
01 24 01 A0h
5-170
PACKHL2
PACKHL2
Syntax
Pack 16 MSB, 16 LSB Into Packed 16-Bit

PACKHL2 (.unit) src1,src2, dst .unit = .L1, .L2 or .S1, .S2
For operand type... Unit i2 xi2 i2 i2 xi2 i2 .L1, .L2
Opfield 0011100

Opcode
.S1 . S2 001000
.L unit
31 29 28 27 23 22 18 17 13 12 x 1 11 5 4 1 3 1 3 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
.S unit
31 29 28 27 23 22 18 17 13 12 x 1 11 6 5 1 4 0 4 3 0 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
6
s
1
p
1
Description
The PACKHL2 instruction takes the upper half-word from src1 and the lower half-word from src2 and packs them both into dst. The upper half-word of src1 is placed in the upper half-word of dst. The lower half-word of src2 is placed in the lower half-word of dst. This instruction is useful for manipulating and preparing pairs of 16-bit values to be used by the packed arithmetic operations, such as ADD2.
5-171
PACKHL2
31 a_hi
16
15 a_lo
0
src1
PACKHL2 b_hi b_lo

src2
31 a_hi
16
15 b_lo
0
dst
Execution
if (cond)
{ lsb16(src2) lsb16(dst) msb16(src1) msb16(dst); }
else nop Pipeline ________________________ Pipeline Stage E1
________________________ Read Written Unit in use
src1, src2 dst

.L, .S
________________________ Instruction Type Delay Slots See Also Single-cycle 0 PACK2, PACKH2, PACKLH2, SPACK2
5-172
PACKHL2
Example 1
PACKHL2
.L1
A2,A8,A9
A8
04B8 4975h
A8
04B8 4975h
A9
XXXX XXXXh
A9
3789 4975h
Example 2
PACKHL2
.S2
B2,B8,B12
B8
01A6 A051h
B8
01A6 A051h
B12
XXXX XXXXh
B12
0124 A051h
5-173
PACKL4
PACKL4
Syntax
Pack Low Bytes of Four Half-Words Into Packed 8-Bit

PACKL4 (.unit) src1,src2, dst .unit = .L1, .L2
For operand type... Unit i4 xi4 i4
Opfield
src1 src2 dst

Opcode
.L1, .L2 1101000
.L unit
31 29 28 27 23 22 18 17 13 12 x 1 11 5 4 1 1 3 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
Description
The PACKL4 instruction moves the low bytes of the two half-words in src1 and src2, and packs them into dst. The bytes from src1 will be packed into the most significant bytes of dst, and the bytes from src2 will be packed into the least significant bytes of dst. Specifically, the low byte of the upper half-word of src1 is moved to the upper byte of the upper half-word of dst. The low byte of the lower half-word of src1 is moved to the lower byte of the upper half-word of dst. The low byte of the upper half-word of src2 is moved to the upper byte of the lower half-word of dst. The low byte of the lower half-word of src2 is moved to the lower byte of the lower half-word of dst.
31 3 a_3 24 23 2 a_2 PACKL4 b 3 b_3 b 2 b_2 b 1 b_1 b 0 b_0 16 15 1 a_1 8 7 0 a_0 0
1 src1
2 src2
31 a_2
24
23 a_0
16
15 b_2
7 b_0
dst
5-174
PACKL4
Execution if (cond) { byte2(src1) byte3(dst) byte0(src1) byte2(dst) byte2(src2) byte1(dst) byte0(src2) byte0(dst); } else nop Pipeline __________________________ Pipeline Stage E1
src1, src2 dst

.L
__________________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 PACKH4, SPACKU4 PACKL4 .L1 A2,A8,A9
Before instruction A2 37 89 F2 3Ah A2 1 cycle after instruction 37 89 F2 3Ah
A8
04 B8 49 75h
A8
04 B8 49 75h
A9
XXXX XXXXh
A9
89 3A B8 75h
5-175
PACKL4
Example 2 PACKL4 .L2 B2,B8,B12
Before instruction B2 01 24 24 51h B2 1 cycle after instruction 01 24 24 51h
B8
01 A6 A0 51h
B8
01 A6 A0 51h
B12
XXXX XXXXh
B12
24 51 A6 51h
5-176
PACKLH2
PACKLH2
Syntax
Pack 16LSB, 16MSB Into Packed 16-Bit

PACKLH2 (.unit) src1,src2, dst .unit = .L1, .L2 or .S1, .S2
For operand type... Unit i2 xi2 i2 i2 xi2 i2
Opfield

Opcode
.L1, .L2 0011011
.S1 .S2 010000
.L unit
31 29 28 27 23 22 18 17 13 12 x 1 11 5 4 1 3 1 3 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
.S unit
31 29 28 27 23 22 18 17 13 12 x 1 11 6 5 1 4 0 4 3 0 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
6
s
1
p
1
Description
The PACKLH2 instruction takes the lower half-word from src1, and the upper half-word from src2, and packs them both into dst. The lower half-word of src1 is placed in the upper half-word of dst. The upper half-word of src2 is placed in the lower half-word of dst. This instruction is useful for manipulating and preparing pairs of 16-bit values to be used by the packed arithmetic operations, such as ADD2.
5-177
PACKLH2
31 a_hi
16
15 a_lo
0
src1
PACKLH2
b_hi
b_lo
src2
31 a_lo
16
15 b_hi
0
dst
Execution
if (cond)
{ msb16(src2) lsb16(dst) lsb16(src1) msb16(dst); }
src1, src2 dst

.L, .S
__________________________ Instruction Type Delay Slots See Also Single-cycle 0 PACK2, PACKH2, PACKHL2, SPACK2
5-178
PACKLH2
Example 1 PACKLH2 .L1 A2,A8,A9
Before instruction A2 3789 F23Ah A2 1 cycle after instruction 3789 F23Ah
A8
04B8 4975h
A8
04B8 4975h
A9
XXXX XXXXh
A9
F23A 04B8h
Example 2
PACKLH2 .S2 B2,B8,B12

Before instruction B2 0124 2451h B2 1 cycle after instruction 0124 2451h
B8
01A6 A051h
B8
01A6 A051h
B12
XXXX XXXX h
B12
2451 01A6h
5-179
ROTL
ROTL
Syntax
Rotate Left
ROTL (.unit) src2,src1, dst .unit = .M1, .M2
For operand type... Unit uint xuint uint ucst5 xuint uint .M1, .M2
Opfield 11101

Opcode
31 29 28 27 23 22 18 17
.M1, .M2
11110
13
12 x 1
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1/ucst
5
op
5
s
1
p
1
Description
The ROTL instruction rotates the 32-bit value of src2 to the left, and places the result in dst. The number of bits to rotate is given in the five least-significant bits of src1. Bits 5 through 31 of src1 are ignored and may be non-zero. In the example below, src1 is equal to 8.
31 8 0
abcdefghijklmnopqrstuvwxyzABCDEF
src2
ijklmnopqrstuvwxyzABCDEFabcdefgh
dst
(for src1 = 8)
Note: The ROTL instruction is useful in cryptographic applications.
5-180
ROTL
Execution if (cond) {
(src2 << src1) | (src2 >> (32src1) dst

} else nop Pipeline ________________________________ Pipeline Stage E1 E2
_________________________________ Read Written Unit in use .M
src1, src2 dst
_________________________________ Instruction Type Delay Slots See Also Example 1 Two-cycle 1 SHL, SHLMB, SHRMB, SHR, SHRU ROTL .M2 B2,B4,B5
Before instruction B2 A6E2 C179h B2 2 cycles after instruction A6E2 C179h
B4
1458 3B69h
B4 .
1458 3B69h
B5
XXXX XXXXh
B5
C582 F34Dh
Example 2
ROTL .M1 A4,10h,A5

Before instruction A4 187A 65FCh A4 2 cycles after instruction 187A 65FCh
A5
XXXX XXXXh
A5
65FC 187Ah
5-181
SADD2
SADD2
Syntax
Add With Saturation, Signed Packed 16-Bit

SADD2 (.unit) src1,src2, dst .unit = .S1, .S2
For operand type... Unit s2 xs2 s2 .S1, .S2
Opfield 0000
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 1 2
10 1
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
4
s
1
p
1
Description
The SADD2 instruction performs 2s-complement addition between signed, packed 16-bit quantities in src1 and src2. The results are placed in a signed, packed 16-bit format into dst. For each pair of 16-bit quantities in src1 and src2, the sum between the signed 16-bit value from src1 and the signed 16-bit value from src2 is calculated and saturated to produce a signed 16-bit result. The result is placed in the corresponding position in dst.
5-182
SADD2
31 a_hi
16
15 a_lo
0
src1
SADD2
b_hi
b_lo
src2
31 sat(a_hi+b_hi)
16
15 sat(a_lo+b_lo)
0
dst
Note: This operation is performed on each half-word separately. This instruction does not affect the SAT bit in the CSR. Execution if (cond) { sat((msb16(src1) + msb16(src2))) msb16(dst) sat((lsb16(src1) + lsb16(src2))) lsb16(dst) } else nop Saturation (shown above as sat) is performed on each 16-bit result independently. For each sum, the following tests are applied:
- If the sum is in the range 2 15 to 2 15 1, inclusive, then no saturation is
performed and the sum is left unchanged.

- If the sum is greater than 2 15 1, then the result is set to 2 15 1. - If the sum is less than 2 15, then the result is set to 2 15.
5-183
SADD2
src1, src2 dst

.S
__________________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 SADD, SADDU4, SADDUS2 SADD2 .S1 A2,A8,A9
Before instruction A2 5789 F23Ah 22409 3526 A2 1 cycle after instruction 5789 F23Ah 22409 3526
A8
74B8 4975h
29880 18805
A8
74B8 4975h
29880 18805
A9
XXXX XXXXh
A9
7FFF 3BAFh
32767 15279
Example 2
SADD2 .S2 B2,B8,B12

Before instruction B2 0124 847Ch 292 31260 B2 1 cycle after instruction 0124 847Ch 292 31260
B8
01A6 A051h
422 24495
B8
01A6 A051h
422 24495
B12
XXXX XXXXh
B12
02AC 8000h
684 32768
5-184
SADDU4
SADDU4
Syntax
Add With Saturation, Unsigned, Packed 8-Bit

SADDU4 (.unit) src1,src2, dst .unit = .S1, .S2
For operand type... Unit u4 xu4 u4 .S1 ,.S2
Opfield 0011
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 1 2
10 1
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
4
s
1
p
1
Description
The SADDU4 instruction performs 2s-complement addition between unsigned, packed 8-bit quantities. The values in src1 and src2 are treated as unsigned, packed 8-bit quantities. The results are written into dst in an unsigned, packed 8-bit format. For each pair of 8-bit quantities in src1 and src2, the sum between the unsigned 8-bit value from src1 and the unsigned 8-bit value from src2 is calculated and saturated to produce an unsigned 8-bit result. The result is placed in the corresponding position in dst.
5-185
SADDU4
31
24 ua_3 3
23
16 ua_2 2
15 ua_1 1
7 ua_0 0
src1 1
SADDU4
ub_3 b 3 ub_2 b 2 ub_1 b 1 ub_0 b 0
src2 2
=
31 sat(ua_3+ub_3) 24 23 sat(ua_2+ub_2) 16 15 sat(ua_1+ub_1) 8 7 sat(ua_0+ub_0) 0
dst
Note: This operation is performed on each 8-bit quantity separately. This instruction does not affect the SAT bit in the CSR. Execution if (cond) { sat((ubyte0(src1) + ubyte0(src2))) ubyte0(dst) sat((ubyte1(src1) + ubyte1(src2))) ubyte1(dst) sat((ubyte2(src1) + ubyte2(src2))) ubyte2(dst) sat((ubyte3(src1) + ubyte3(src2))) ubyte3(dst) } else nop Saturation (shown above as sat) is performed on each 8-bit result independently. For each sum, the following tests are applied:
- If the sum is in the range 0 to 2 8 1, inclusive, then no saturation is per-
formed and the sum is left unchanged.

- If the sum is greater than 2 8 1, then the result is set to 2 8 1.
5-186
SADDU4
Pipeline __________________________ Pipeline Stage E1
src1, src2 dst

.S
__________________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 SADD, SADD2, SADDUS2 SADDU4 .S1 A2, A8, A9
Before instruction A2 57 89 F2 3Ah 87 137 242 58 unsigned A8 74 B8 49 75h 116 184 73 117 unsigned A9 XXXX XXXXh A9 CB FF FF AFh A8 74 B8 49 75h A2 1 cycle after instruction 57 89 F2 3Ah 87 137 242 58 unsigned 116 184 73 117 unsigned 203 255 255 175 unsigned
Example 2
SADDU4 .S2 B2, B8, B12

Before instruction B2 14 7C 01 24h 20 124 1 36 unsigned B8 A0 51 01 A6h 160 81 1 166 unsigned B12 XXXX XXXXh B12 B4 CD 02 CA B8 A0 51 01 A6h B2 1 cycle after instruction 14 7C 01 24h 20 124 1 36 unsigned 160 81 1 166 unsigned 180 205 2 202 unsigned
5-187
SADDSU2
SADDSU2
Add With Saturation, Signed With Unsigned Packed 16-Bit (Pseudo-Operation)

SADDSU2(.unit) src2, src1, dst .unit = .S1, .S2
Syntax
For operand type... Unit u2 xs2 u2 .S1, .S2
Opfield 0001
src1 src2 dst
Opcode Description
See SADDUS2 instruction. The SADDSU2 pseudo-operation performs 2s-complement addition between unsigned and signed packed 16-bit quantities. The values in src1 are treated as unsigned packed 16-bit quantities, and the values in src2 are treated as signed packed 16-bit quantities. The results are placed in an unsigned packed 16-bit format into dst. The assembler uses the SADDUS2 src1, src2, dst instruction to perform this operation. For each pair of 16-bit quantities in src1 and src2, the sum between the unsigned 16-bit value from src1 and the signed 16-bit value from src2 is calculated and saturated to produce a signed 16-bit result. The result is placed in the corresponding position in dst. Saturation is performed on each 16-bit result independently. For each sum, the following tests are applied:

- If the sum is greater than 2 16 1, then the result is set to 2 16 1. - If the sum is less than 0, then the result is set to 0.
Execution
if (cond)
{ SAT((smsb16(src2) + umsb16(src1))) umsb16(dst) SAT((slsb16(src2) + ulsb16(src1))) ulsb16(dst) }
else nop
5-188
SADDSU2
src1, src2 dst

.S
__________________________ Instruction Type Delay Slots See Also Single-cycle 0 SADD, SADD2, SADDUS2, SADDU4
5-189
SADDUS2
SADDUS2
Syntax
Add With Saturation, Unsigned With Signed Packed 16-Bit

SADDUS2(.unit) src1,src2, dst .unit = .S1, .S2
For operand type... Unit u2 xs2 u2 .S1 ,.S2
Opfield 0001
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 1 2
10 1
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
4
s
1
p
1
Description
The SADDUS2 instruction performs 2s-complement addition between unsigned, and signed, packed 16-bit quantities. The values in src1 are treated as unsigned, packed 16-bit quantities; and the values in src2 are treated as signed, packed 16-bit quantities. The results are placed in an unsigned, packed 16-bit format into dst. For each pair of 16-bit quantities in src1 and src2, the sum between the unsigned 16-bit value from src1 and the signed 16-bit value from src2 is calculated and saturated to produce a signed 16-bit result. The result is placed in the corresponding position in dst.
5-190
SADDUS2
31 ua_hi
16
15 ua_lo
0
src1
SADDUS2
sb_hi
sb_lo
src2
31
16
15
0
dst
sat(ua_hi+sb_hi)
sat(ua_lo+sb_lo)
Note: This operation is performed on each half-word separately. This instruction does not affect the SAT bit in the CSR. Execution if (cond) { sat((umsb16(src1) + smsb16(src2))) umsb16(dst) sat((ulsb16(src1) + slsb16(src2))) ulsb16(dst) } else nop Saturation (shown above as sat) is performed on each 16-bit result independently. For each sum, the following tests are applied:

- If the sum is greater than 2 16 1, then the result is set to 2 16 1. - If the sum is less than 0, then the result is set to 0.
5-191
SADDUS2
src1, src2 dst

.S
__________________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 SADD, SADD2, SADDU4 SADDUS2 .S1 A2, A8, A9
Before instruction A2 5789 F23Ah 22409 62010 unsigned A8 74B8 4975h 29880 18805 signed A9 XXXX XXXXh A9 CC41 FFFF A8 74B8 4975h A2 1 cycle after instruction 5789 F23Ah 22409 62010 unsigned 9880 18805 signed 52289 65535 unsigned
Example 2
SADDUS2 .S2 B2, B8, B12

Before instruction B2 147C 0124h 5244 292 unsigned B8 A051 01A6h 24495 422 signed B12 XXXX XXXXh B12 0000 02ACh B8 A051 01A6h B2 1 cycle after instruction 147C 0124h 5244 292 unsigned 24495 422 signed 0 684 unsigned
5-192
SHFL
SHFL
Syntax
Shuffle
SHFL (.unit) src2, dst .unit = .M1, .M2
For operand type... Unit xuint uint .M1, .M2
Opfield 11100
src2 dst
Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 0
10 0
9 0
8 0
7 1 10
6 1
5 1
4 1
3 0
2 0
creg
3
z
1
dst
5
src
5
op
5
s
1
p
1
Description
The SHFL instruction performs an interleave operation on the two half-words in src2. The bits in the lower half-word of src2 are placed in the even bit positions in dst, and the bits in the upper half-word of src2 are placed in the odd bit positions in dst. As a result, bits 0, 1, 2, ..., 14, 15 of src2 are placed in bits 0, 2, 4, ... , 28, 30 of dst. Likewise, bits 16, 17, 18, .. 30, 31 of src2 are placed in bits 1, 3, 5, ..., 29, 31 of dst.
5-193
SHFL
31
16
15
0
src2
abcdefghijklmnop SHFL 31 16
ABCDEFGHIJKLMNOP
15
0
dst
aAbBcCdDeEfFgGhH
iIjJkKlLmMnNoOpP
Note: The SHFL instruction is the exact inverse of the DEAL instruction. Execution if (cond) {
src231,30,29...16 dst31,29,27...1 src215,14,13...0 dst30,28,26...0

} Pipeline _________________________ Pipeline Stage E1 E2
__________________________ Read Written Unit in use .M
src2 dst
__________________________ Instruction Type Delay Slots See Also Two-cycle 1 DEAL
5-194
SHFL
Example SHFL .M1 A1,A2
Before instruction A1 B174 6CA4h A1 2 cycles after instruction B174 6CA4h
A2
XXXX XXXXh
A2
9E52 6E30h
5-195
SHLMB
SHLMB
Syntax
Shift Left and Merge Byte

SHLMB (.unit) src1,src2, dst .unit = .L1, .L2 or .S1, .S2
For operand type... Unit u4 xu4 u4 u4 xu4 u4
Opfield

Opcode
.L1, .L2 1100001
.S1 .S2 1001
.L unit
31 29 28 27 23 22 18 17 13 12 x 1 11 5 4 1 3 1 3 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
.S Unit
31 29 28 27 22 18 17 13 12 x 1 11 1 2 10 1 9 6 5 1 4 1 4 3 0 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
4
s
1
p
1
Description
The SHLMB instruction shifts the contents of src2 left by one byte, and then the most significant byte of src1 is merged into the least significant byte position. The result is placed in dst.
5-196
SHLMB
31 ua_3 ua 3
24
32 ua_2 ua 2
16
15 ua_1 ua 1
7 ua_0 ua 0
src1
SHLMB
ub_3 ub 3 ub_2 ub 2 ub_1 ub 1 ub_0 ub 0
src2
31 ub_2
24
23 ub_1
16
15 ub_0
7 ua_3
dst
Execution
if (cond)
{ ubyte2(src2) ubyte3(dst); ubyte1(src2) ubyte2(dst); ubyte0(src2) ubyte1(dst); ubyte3(src1) ubyte0(dst); }
src1, src2 dst

.L, .S
__________________________ Instruction Type Delay Slots See Also Single-cycle 0 ROTL, SHL, SHRMB, SHR, SHRU
5-197
SHLMB
Example 1 SHLMB .L1 A2, A8, A9
A8
04B8 4975h
A8
04B8 4975h
A9
XXXX XXXX h
A9
B849 7537h
Example 2
SHLMB .S2 B2,B8, B12

B8
01A6 A051h
B8
01A6 A051h
B12
XXXX XXXX h
B12
A6A0 5101h
5-198
SHR2
SHR2
Syntax
Shift Right, Signed Packed 16-Bit

SHR2 (.unit) src2,src1, dst .unit = .S1, .S2
For operand type... Unit uint xs2 s2 ucst xs2 s2
Opfield

Opcode
.S1 .S2 0111
.S1 .S2 011000
.S unit (uint form)

31 29 28 27 23 22 18 17 13 12 x 1 11 1 2 10 1 9 6 5 1 4 1 4 3 0 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
4
s
1
p
1
.S unit (cst form)

31 29 28 27 23 22 18 17 13 12 x 1 11 6 5 1 4 0 3 0 4 2 0 1 0
creg
3
z
1
dst
5
src2
5
cst
5
op
6
s
1
p
1
Description
The SHR2 instruction performs an arithmetic shift right on signed, packed 16-bit quantities. The values in src2 are treated as signed, packed 16-bit quantities. The lower five bits of src1 or ucst5 are treated as the shift amount. The results are placed in a signed, packed 16-bit format into dst. For each signed 16-bit quantity in src2, the quantity is shifted right by the number of bits specified in the lower five bits of src1 or ucst5 . Bits 5 through 31 of src1 are ignored and may be non-zero. The shifted quantity is sign-extended, and placed in the corresponding position in dst. Bits shifted out of the least-significant bit of the signed 16-bit quantity are discarded.
5-199
SHR2
31
24
16
15
abcdefghijklmnop
qrstuvwxyzABCDEF
src2
aaaaaaaaabcdefgh
qqqqqqqqqrstuvwx
dst
(for src1= +8)
Note: If the shift amount specified in src1 or ucst5 is the range 16 to 31, the behavior is identical to a shift value of 15. Execution if (cond) { smsb16(src2) >> src1 smsb16(dst) slsb16(src2) >> src1 slsb16(dst); } else nop Pipeline __________________________ Pipeline Stage E1
src1, src2 dst

.S
__________________________ Instruction Type Delay Slots See Also Single-cycle 0 SHR, SHRU2
5-200
SHR2
Example 1 SHR2 .S2 B2,B4,B5
Before instruction B2 A6E2 C179h B2 1 cycle after instruction A6E2 C179h
B4
1458 3B69h
shift value 9
B4
1458 3B69h
shift value 9
B5
XXXX XXXXh
B5
FFD3 FFE0h
Example 2
SHR2 .S1 A4,0fh,A5 ; shift value is 15

Before instruction A4 000A 87AFh A4 1 cycle after instruction 000A 87AFh
A5
XXXX XXXXh
A5
0000 FFFFh
5-201
SHRMB
SHRMB
Syntax
Shift Right and Merge Byte

SHRMB (.unit) src1,src2, dst .unit = .L1, .L2 or .S1, .S2
For operand type... Unit u4 xu4 u4 u4 xu4 u4 .L1, .L2
Opfield 1100010

Opcode
.S1, .S2
1010
.L unit
31 29 28 27 23 22 18 17 13 12 x 1 11 5 4 1 3 1 3 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
.S Unit
31 29 28 27 23 22 18 17 13 12 x 1 11 1 2 10 1 9 6 5 1 4 1 4 3 0 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
4
s
1
p
1
Description
The SHRMB instruction shifts the contents of src2 right by one byte, and then the least significant byte of src1 is merged into the most significant byte position. The result is placed in dst.
5-202
SHRMB
31 ua_3 ua 3
24
23 ua_2 ua 2
16
15 ua_1 ua 1
7 ua_0 ua 0
src1
SHRMB
ub_3 b 3 ub_2 b 2 ub_1 b 1 ub_0 b 0
src2 2
31 ua_0
24
23 ub_3
16
15 ub_2
7 ub_1
dst
Execution
if (cond)
{ ubyte0(src1) ubyte3(dst); ubyte3(src2) ubyte2(dst); ubyte2(src2) ubyte1(dst); ubyte1(src2) ubyte0(dst); }
src1, src2 dst

.L, .S
__________________________ Instruction Type Delay Slots See Also Single-cycle 0 ROTL, SHL, SHLMB, SHR, SHRU
5-203
SHRMB
Example 1 SHRMB .L1 A2,A8,A9
A8
04B8 4975h
A8
04B8 4975h
A9
XXXX XXXX h
A9
3A04 B849h
Example 2
SHRMB .S2 B2,B8,B12

B8
01A6 A051h
B8
01A6 A051h
B12
XXXX XXXX h
B12
5101 A6A0h
5-204
SHRU2
SHRU2
Syntax
Shift Right, Unsigned Packed 16-Bit

SHRU2 (.unit) src2, src1, dst .unit = .S1, .S2
For operand type... Unit uint xu2 u2 ucst xu2 u2
Opfield

Opcode
.S1 .S2 1000
.S1 .S2 011001
.S unit (uint form)

31 29 28 27 23 22 18 17 13 12 x 1 11 1 2 10 1 9 6 5 1 4 1 4 3 0 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
4
s
1
p
1
.S unit (cst form)

31 29 28 27 23 22 18 17 13 12 x 1 11 6 5 1 4 0 3 0 4 2 0 1 0
creg
3
z
1
dst
5
src2
5
cst
5
op
6
s
1
p
1
Description
The SHRU2 instruction performs an arithmetic shift right on unsigned, packed 16-bit quantities. The values in src2 are treated as unsigned, packed 16-bit quantities. The lower five bits of src1 or ucst5 are treated as the shift amount. The results are placed in an unsigned, packed 16-bit format into dst. For each unsigned 16-bit quantity in src2, the quantity is shifted right by the number of bits specified in the lower five bits of src1 or ucst5. Bits 5 through 31 of src1 are ignored and may be non-zero. The shifted quantity is zeroextended, and placed in the corresponding position in dst. Bits shifted out of the least-significant bit of the signed 16-bit quantity are discarded.
5-205
SHRU2
31
24
16
15
abcdefghijklmnop qrstuvwxyzABCDEF
src2
00000000abcdefgh
00000000qrstuvwx
dst
(for src1= +8)
Note: If the shift amount specified in src1 or ucst5 is in the range of 16 to 31, the dst will be set to all zeros. Execution if (cond) { umsb16(src2) >> src1 umsb16(dst) ulsb16(src2) >> src1 ulsb16(dst); } else nop Pipeline __________________________ Pipeline Stage E1
src1, src2 dst

.S
__________________________ Instruction Type Delay Slots See Also Single-cycle 0 SHR2, SHRU
5-206
SHRU2
Example 1 SHRU2 .S2 B2,B4,B5
Before instruction B2 A6E2 C179h B2 1 cycle after instruction A6E2 C179h
B4
1458 3B69h
Shift value 9
B4
1458 3B69h
Shift value 9
B5
XXXX XXXXh
B5
0053 0060h
Example 2
SHRU2 .S1 A4,0fh,A5 ; Shift value is 15.

Before instruction A4 000A 87AFh A4 1 cycle after instruction 000A 87AFh
A5
XXXX XXXXh
A5
0000 0001h
5-207
SMPY2
SMPY2
Syntax
Multiply Signed by Signed, with Left Shift and Saturate, Packed 16-Bit
SMPY2 (.unit) src1,src2, dst .unit = .M1, .M2
For operand type... Unit s2 xs2 ullong .M1, .M2
Opfield 00001
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
x
1
op
5
s
1
p
1
Description
The SMPY2 instruction performs two 16-bit by 16-bit multiplies between two pairs of signed packed 16-bit values, with an additional left-shift and saturate. The values in src1 and src2 are treated as signed, packed 16-bit quantities. The two 32-bit results are written into a 64-bit register pair. The SMPY2 instruction produces two 16 x 16 products. Each product is shifted left by one; and if the left-shifted result is equal to 0x80000000, the output value is saturated to 0x7FFFFFFF. The saturated product of the lower half-words of src1 and src2 is written to the even destination register, dst_e. The saturated product of the upper half-words of src1 and src2 is written to the odd destination register, dst_o.
5-208
SMPY2
31 a_hi
16 15 a_lo SMPY2 b_hi b_lo
0
src1
src2
=
63 SAT((a_hi*b_hi) << 1) 32 31 SAT((a_lo*b_lo) << 1) 0
dst_o: dst_e
Note: If either product saturates, the SAT bit is set in the CSR on the cycle that the result is written. If neither product saturates, the SAT bit in the CSR is left unaffected. This instruction helps reduce the number of instructions required to perform two 16-bit by 16-bit saturated multiplies on both the lower and upper halves of two registers. The following code:
SMPY .M1 A0, A1, A2 A0, A1, A3
SMPYH .M1
may be replaced by:

SMPY2 .M1 A0, A1, A3:A2
Execution
if (cond)
{ SAT((lsb16(src1) x lsb16(src2)) << 1) dst_e ; SAT((msb16(src1) x msb16(src2)) <<1) dst_o }
else nop
5-209
SMPY2
Pipeline ________________________________________ Pipeline Stage E1 E2 E3 E4
________________________________________ Read Written Unit in use .M
src1, src2 dst
________________________________________ Instruction Type Delay Slots See Also Example 1 Four-cycle 3 MPY2, SMPY, SMPYH SMPY2 .M1 A5,A6,A9:A8
Before instruction A5 4 cycles after instruction
6A32 1193h
27186 4499
A5
6A32 1193h
27186 4499
A6
B174 6CA4h
20108 27812
A6 .
B174 6CA4h
20108 27812
A9:A8
XXXX XXXXh
XXXX XXXXh
A9:A8
BED5 6150h
1,093,312,176
0EEA 8C58h
250,252,376
5-210
SMPY2
Example 2 SMPY2 .M2 B2, B5, B9:B8
Before instruction B2 4 cycles after instruction
1234 3497h
4660 13463
B2
1234 3497h
4660 13463
B5
21FF 50A7h
8703 20647
B5 .
21FF 50A7h
8703 20647
B9:B8
XXXX XXXXh
XXXX XXXXh
B9:B8
04D5 AB98h 81,111,960
2122 FD02h 555,941,122
5-211
SPACK2
SPACK2
Syntax
Saturate and Pack into Signed Packed 16-Bit

SPACK2 (.unit) src1,src2, dst .unit = .S1, .S2
For operand type... Unit int xint s2
Opfield
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
.S1 .S2 0010
13
12 x 1
11 1 2
10 1
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
4
s
1
p
1
Description
The SPACK2 instruction takes two signed 32-bit quantities in src1 and src2 and saturates them to signed 16-bit quantities. The signed 16-bit results are then packed into a signed, packed 16-bit format and written to dst. Specifically, the saturated 16-bit signed value of src1 is written to the upper half word of dst, and the saturated 16-bit signed value of src2 is written to the lower half word of dst. Saturation is performed on each input value independently. The input values start as signed 32-bit quantities, and are saturated to 16-bit quantities according to the following rules:
- If the value is in the range 2 15 to 2 15 1, inclusive, then no saturation
is performed and the value is merely truncated to 16 bits.

- If the value is greater than 2 15 1, then the result is set to 2 15 1. - If the value is less than 2 15, then the result is set to 2 15.
5-212
SPACK2
31 00000000ABCDEFGH
16
15 IJKLMNOPQRSTUVWX
src1
SPACK2
0000000000000000 00YZ123456789ABC
src2
0111111111111111
00YZ123456789ABC
dst
This instruction is useful in code which manipulates 16-bit data at 32-bit precision for its intermediate steps, but which requires the final results to be in a 16-bit representation. The saturate step ensures that any values outside the signed 16-bit range are clamped to the high or low end of the range before being truncated to 16 bits. Note: This operation is performed on each 16-bit value separately. This instruction does not affect the SAT bit in the CSR. Execution if (cond) { if src2 > 0x00007FFF, then 0x7FFF lsb16(dst) or if src2 < 0xFFFF8000, then 0x8000 lsb16(dst) else truncate(src2) lsb16(dst); if src1 > 0x00007FFF, then 0x7FFFF msb16(dst) or if src1 < 0xFFFF8000, then 0x8000 msb16(dst) else truncate(src1) msb16(dst); } else nop
5-213
SPACK2
src1, src2 dst

.S
_________________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 PACK2, PACKH2, PACKHL2, PACKLH2, SPACKU4 SPACK2 .S1 A2,A8,A9
Before instruction A2 3789 F23Ah 931,787,322 A2 1 cycle after instruction 3789 F23Ah 931,787,322
A8
04B8 4975h
79,186,293
A8
04B8 4975h
79,186,293
A9
XXXX XXXX h
A9
7FFF 7FFFh
32767 32767
Example 2
SPACK2 .S2 B2,B8,B12

Before instruction B2 A124 2451h 1,591,466,927 B2 1 cycle after instruction A124 2451h 1,591,466,927
B8
01A6 A051h
27,697,233
B8
01A6 A051h
27,697,233
B12
XXXX XXXX h
B12
8000 7FFFh
32768 32767
5-214
SPACKU4
SPACKU4
Syntax
Saturate and Pack into Unsigned Packed 8-Bit

SPACKU4 (.unit) src1,src2, dst .unit = .S1, .S2
For operand type... Unit s2 xs2 u4
Opfield
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
.S1 .S2 0100
13
12 x 1
11 1 2
10 1
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
4
s
1
p
1
Description
The SPACKU4 instruction takes four signed 16-bit values and saturates them to unsigned 8-bit quantities. The values in src1 and src2 are treated as signed, packed 16-bit quantities. The results are written into dst in an unsigned, packed 8-bit format. Each signed 16-bit quantity in src1 and src2 is saturated to an unsigned 8-bit quantity as described below. The resulting quantities are then packed into an unsigned, packed 8-bit format. Specifically, the upper half word of src1 is used to produce the most significant byte of dst. The lower half of src1 is used to produce the second most significant byte (bits 16 to 23) of dst. The upper half word of src2 is used to produce the third most significant byte (bits 8 to 15) of dst. The lower half word of src2 is used to produce the least significant byte of dst. Saturation is performed on each signed 16-bit input independently, producing separate unsigned 8-bit results. For each value, the following tests are applied:
- If the value is in the range 0 to 2 8 1, inclusive, then no saturation is per-
formed and the result is truncated to 8 bits.

- If the value is greater than 2 8 1, then the result is set to 2 8 1. - If the value is less than 0, the result is set to 0.
5-215
SPACKU4
31
16
15
00000000ABCDEFGH
00000001IJKLMNOP
src1 1
SPACKU4
00000000YZ123456
11111111QRSTUVWX
src2 2
31
24
23
16
15
ABCDEFGH
FFFFFFFF
YZ123456
00000000
dst
This instruction is useful in code which manipulates 8-bit data at 16-bit precision for its intermediate steps, but which requires the final results to be in an 8-bit representation. The saturate step ensures that any values outside the unsigned 8-bit range are clamped to the high or low end of the range before being truncated to 8 bits. Note: This operation is performed on each 8-bit quantity separately. This instruction does not affect the SAT bit in the CSR. Execution if (cond) { if msb16(src1) >> 0x00007FFF, then 0x7F ubyte3(dst) or if msb16(src1) << 0xFFFF8000, then 0 ubyte3(dst) else truncate(msb16(src1)) ubyte3(dst); if lsb16(src1) >> 0x00007FFF, then 0x7F ubyte2(dst) or if lsb16(src1) << 0xFFFF8000, then 0 ubyte2(dst) else truncate(lsb16(src1)) ubyte2(dst); if msb16(src2) >> 0x00007FFF, then 0x7F ubyte1(dst) or if msb16(src2) << 0xFFFF8000, then 0 ubyte1(dst) else truncate(msb16(src2)) ubyte1(dst); if lsb16(src2) >> 0x00007FFF, then 0x7F ubyte0(dst) or if lsb16(src2) << 0xFFFF8000, then 0 ubyte0(dst) else truncate(lsb16(src2)) ubyte0(dst); } else nop
5-216
SPACKU4
src1, src2 dst

.S
__________________________ Instruction Type Delay Slots See Also Example 1 Single-cycle 0 PACKH4, PACKL4, SPACK2 SPACKU4 .S1 A2,A8,A9
A8
04B8 4975h
1208 18805
A8
04B8 4975h
1208 18805
A9
XXXX XXXXh
A9
FF 00 FF FFh
255 0 255 255
Example 2
SPACKU4 .S2 B2,B8,B12

Before instruction B2 A124 2451h 24284 9297 B2 1 cycle after instruction A124 2451h 24284 9297
B8
01A6 A051h
422 24495
B8
01A6 A051h
422 24495
B12
XXXX XXXXh
B12
00 FF FF 00h
0 255 255 0
5-217
SSHVL
SSHVL
Syntax
Variable Shift Left, Signed

SSHVL(.unit) src2,src1, dst .unit = .M1, .M2
For operand type... Unit int xint int .M1, .M2
Opfield 11100
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
5
s
1
p
1
Description
The SSHVL instruction shifts the signed 32-bit value in src2 to the left or right by the number of bits specified by src1, and places the result in dst. The src1 argument is treated as a 2s-complement shift value which is automatically limited to the range 31 to 31. If src1 is positive, src2 is shifted to the left. If src1 is negative, src2 is shifted to the right by the absolute value of the shift amount, with the sign-extended shifted value being placed in dst. It should also be noted that when src1 is negative, the bits shifted right past bit 0 are lost.
31
src2
aaaaaaaaabcdefghijklmnopqrstuvwx
dst
(for src1= 8)
Note: If the shifted value is saturated, then the SAT bit is set in CSR in the same cycle that the result is written. If the shifted value is not saturated, then the SAT bit is unaffected.
5-218
SSHVL
Execution if (cond) { if 0 < = src1 < = 31 then SAT(src2 << src1) dst ; if 31 < = src1 < 0 then (src2 >> abs(src1)) dst; if src1 > 31 then SAT(src2 << 31) dst; if src1 < 31 then (src2 >> 31) dst } else nop Saturation is performed (shown as sat above) when the value is shifted left under the following conditions:
- If the shifted value is in the range 2 31 to 2 31 1, inclusive, then no satura-
tion is performed, and the result is truncated to 32 bits.

- If the shifted value is greater than 2 31 1, then the result is saturated to 2 31 1. - If the shifted value is less than 2 31, then the result is saturated to 2 31.
Pipeline
_____________________________ Pipeline Stage E1 E2
_____________________________ Read Written Unit in use .M
src1,src2 dst
_____________________________ Instruction Type Delay Slots See Also Two-cycle 1 SHL, SHRU, SSHL, SSHVR
5-219
SSHVL
Example 1 SSHVL .M2 B2, B4, B5
Before instruction B2 FFFF F000h B2 2 cycles after instruction FFFF F000h
B4
FFFF FFE1h
31
B4
FFFF FFE1h
31
B5
XXXX XXXXh
B5
FFFF FFFFh
Example 2
SSHVL .M1 A2,A4,A5

Before instruction A2 F14C 2108h A2 2 cycles after instruction F14C 2108h
A4
0000 0001Fh
31
A4
0000 0001Fh
31
A5
XXXX XXXXh
A5
8000 0000h
Note: Saturated to most negative value
Example 3
SSHVL .M2 B12, B24, B25

Before instruction B12 187A 65FCh B12 2 cycles after instruction 187A 65FCh
B24
FFFF FFFFh
B24
FFFF FFFFh
B25
XXXX XXXXh
B25
03CD 32FEh
5-220
SSHVR
SSHVR
Syntax
Variable Shift Right, Signed

SSHVR (.unit) src2,src1, dst .unit = .M1, .M2
For operand type... Unit int xint int .M1, .M2
Opfield 11101
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 0 1
10
5 1
4 1 4
3 0
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
5
s
1
p
1
Description
The SSHVR instruction shifts the signed 32-bit value in src2 to the left or right by the number of bits specified by src1, and places the result in dst. The src1 argument is treated as a 2s-complement shift value that is automatically limited to the range 31 to 31. If src1 is positive, src2 is shifted to the right by the value specified with the sign-extended shifted value being placed in dst. It should also be noted that when src1 is positive, the bits shifted right past bit 0 are lost. If src1 is negative, src2 is shifted to the left by the absolute value of the shift amount value and the result is placed in dst.
31 8 0
src2
aaaaaaaabcdefghijklmnopqrstuvwxy
dst
(for src1= 7)
Note: If the shifted value is saturated, then the SAT bit is set in CSR in the same cycle that the result is written. If the shifted value is not saturated, then the SAT bit is unaffected.
5-221
SSHVR
Execution if (cond) { if 0 < = src1 < = 31 then
(src2 >> src1) dst;

if 31 < = src1< 0 then SAT(src2 << abs(src1)) dst; if src1 > 31 then (src2 >> 31) dst; if src1 < 31 then SAT(src2 << 31) dst } else nop Saturation (shown as sat above) is performed when the value is shifted left under the following conditions:
- If the shifted value is in the range 2 31 to 2 31 1, inclusive, then no satura-
tion is performed, and the result is truncated to 32 bits.

- If the shifted value is greater than 2 31 1, then the result is saturated to 2 31 1. - If the shifted value is less than 2 31, then the result is saturated to 2 31.
Pipeline
_____________________________ Pipeline Stage E1 E2
_____________________________ Read Written Unit in use .M
src1,src2 dst
_____________________________ Instruction Type Delay Slots See Also

5-222
Two-cycle 1 SHL, SHRU, SSHL, SSHVL
SSHVR
Example 1 SSHVR .M2 B2,B4,B5
Before instruction B2 FFFF F000h B2 2 cycles after instruction FFFF F000h
B4
FFFF FFE1h
31
B4
FFFF FFE1h
31
B5
XXXX XXXXh
B5
8000 0000h
Note: Saturates to most negative value
Example 2
SSHVR .M1 A2,A4,A5

Before instruction A2 F14C 2108h A2 2 cycles after instruction F14C 2108h
A4
0000 0001Fh
31
A4
0000 0001Fh
31
A5
XXXX XXXXh
A5
FFFF FFFFh
5-223
SSHVR
Example 3 SSHVR .M2 B12, B24, B25
Before instruction B12 187A 65FCh B12 2 cycles after instruction 187A 65FCh
B24
FFFF FFFFh
B24
FFFF FFFFh
B25
XXXX XXXXh
B25
30F4 CBF8h
5-224
STDW
STDW
Syntax
Store Double Word

STDW (.unit) src,*mem .unit = .D1, .D2
For operand type... Unit ullong uint uint ullong uint ucst5 .D1, .D2,
srcd baseR offset srcd baseR offset

Opcode
31 29 28 27 23 22 18 17
.D1 .D2
13
12
6 1
5 0 3
4 0
3 0 2
2 1
creg
3
z
1
dst
5
baseR
5
offset
5
mode
4
r
1
y
1
s
1
p
1
Description
The STDW instruction stores a 64-bit quantity to memory from a 64-bit register, srcd. The table below describes the addressing generator options. Alignment to a 64-bit boundary is required. The effective memory address is formed from a base address register (baseR) and an optional offset that is either a register (offsetR) or a 5-bit unsigned constant (ucst5). If an offset is not given, the assembler assigns an offset of zero. Both offsetR and baseR must be in the same register file, and on the same side, as the .D unit used. The y bit in the opcode determines the .D unit and register file used: y = 0 selects the .D1 unit and baseR and offsetR from the A register file, and y = 1 selects the .D2 unit and baseR and offsetR from the B register file. The offsetR/ucst5 is scaled by a left shift of 3 bits. After scaling, offsetR/ucst5 is added to, or subtracted from, baseR. For the pre-increment, pre-decrement, positive offset, and negative offset address generator options, the result of the calculation is the address to be accessed in memory. For post-increment or post-decrement addressing, the value of baseR before the addition or subtraction is the address to be accessed from memory. The addressing arithmetic that performs the additions and subtractions defaults to linear mode. However, for A4A7 and for B4B7, the mode can be changed to circular mode by writing the appropriate value to the AMR.
5-225
STDW
The srcd pair can be in either register file, regardless of the .D unit or baseR or offsetR used. The s bit determines which file srcd will be loaded from: s = 0 indicates srcd will be in the A register file and s = 1 indicates srcd will be in the B register file. r is always zero.
Table 511. STDW Address Generator Options

Assembler Notes
When no bracketed register or constant is specified, the assembler defaults increments and decrements to 1 and offsets to 0. Stores that do no modification to the baseR can use the assembler syntax *R. Square brackets, [ ], indicate that the ucst5 offset is left-shifted by 3 for doubleword stores. Parentheses, ( ), can be used to tell the assembler that the offset is a nonscaled, constant offset. The assember right shifts the constant by 3 bits for double word stores before using it for the ucst5 field. After scaling by the STDW instruction, this results in the same constant offset as the assembler source if the least significant three bits are zeros. For example, STDW (.unit) src, *+baseR (16) represents an offset of 16 bytes (2 double words), and the assembler writes out the instruction with ucst5 = 2. STDW (.unit) src, *+baseR [16] represents an offset of 16 double words, or 128 bytes, and the assembler writes out the instruction with ucst5 = 16.
5-226
STDW
Either brackets or parentheses must be typed around the specified offset if the optional offset parameter is used. The register pair syntax always places the odd-numbered register first, a colon, followed by the even-numbered register (that is, A1:A0, B1:B0, A3:A2, B3:B2, etc.). Execution if (cond) {
src mem
} else nop Pipeline _________________________________ Pipeline Stage E1
_________________________________ Read Written Unit in use
baseR, offsetR, srcd baseR

.D
_________________________________ Instruction Type Delay Slots See Also Example 1 Store 0 LDDW, STW STDW .D1 A3:A2,*A0++
Before instruction A0 0000 1000h A0 1 cycle after instruction 0000 1008h
A3:A2
A176 3B28h
6041 AD65h
A3:A2
A176 3B28h
6041 AD65h
Byte Memory Address Data Value Before Store Data Value After Store
1009 00 00
1008 00 00
1007 00 A1
1006 00 76
1005 00 3B
1004 00 28
1003 00 60
1002 00 41
1001 00 AD
1000 00 65
5-227
STDW
Example 2 STDW .D1 A3:A2, *A0++
1 cycle after instruction A0 0000 100Ch
A3:A2
A176 3B28h
6041 AD65h
A3:A2
A176 3B28h
6041 AD65h
100D 00 00
100C 00 00
100B 00 A1
100A 00 76
1009 00 3B
1008 00 28
1007 00 60
1006 00 41
1005 00 AD
1004 00 65
1003 00 00
5-228
STNDW
STNDW
Syntax
Store Non-Aligned Double Word

STNDW (.unit) src,*mem .unit = .D1, .D2 Opcode map field used... For operand type... Unit ullong uint uint ullong uint ucst5 .D1, .D2
srcd baseR offset srcd baseR offset

Opcode
31 29 28 27 24 23 22 18 17
.D1, .D2
13
12
6 1
5 1 3
4 1
3 0 2
2 1
creg
3
z
1
dst
4
sc
1
baseR
5
offset
5
mode
4
r
1
y
1
s
1
p
1
Description
The STNDW instruction stores a 64-bit quantity to memory from a 64-bit register pair, srcd. The table below describes the addressing generator options. The STNDW instruction may write a 64-bit value to any byte boundary. Thus alignment to a 64-bit boundary is not required. The effective memory address is formed from a base address register (baseR) and an optional offset that is either a register (offsetR) or a 5-bit unsigned constant (ucst5). Both offsetR and baseR must be in the same register file and on the same side as the .D unit used. The y bit in the opcode determines the .D unit and register file used: y = 0 selects the .D1 unit and baseR and offsetR from the A register file, and y = 1 selects the .D2 unit and baseR and offsetR from the B register file. The STNDW instruction suppports both scaled offsets and non-scaled offsets. The sc field is used to indicate whether the offsetR/ucst5 is scaled or not. If sc is 1 (scaled), the offsetR/ucst5 is shifted left 3 bits before adding or subtracting from the baseR. If sc is 0 (non-scaled), the offsetR/ucst5 is not shifted before adding to or subtracting from the baseR. For the pre-increment, pre-decrement, positive offset, and negative offset address generator options, the result of the calculation is the address to be accessed in memory. For post-increment or postdecrement addressing, the value of baseR before the addition or subtraction is the address to be accessed from memory. The addressing arithmetic that performs the additions and subtractions defaults to linear mode. However, for A4A7 and for B4B7, the mode can be changed to circular mode by writing the appropriate value to the AMR.
5-229
STNDW
The srcd pair can be in either register file, regardless of the .D unit or baseR or offsetR used. The s bit determines which file srcd will be loaded from: s = 0 indicates srcd will be in the A register file and s = 1 indicates srcd will be in the B register file. r is always zero.
Table 512. STNDW Address Generator Options

Note: No other memory access may be issued in parallel with a non-aligned memory access. The other .D unit can be used in parallel, as long as it is not performing a memory access. Assembler Notes When no bracketed register or constant is specified, the assembler defaults increments and decrements to 1, and offsets to 0. Loads that do no modification to the baseR can use the assembler syntax *R. Square brackets, [ ], indicate that the ucst5 offset is left-shifted by 3 for double word stores. Parentheses, ( ), can be used to tell the assembler that the offset is a nonscaled offset. For example, STNDW (.unit) src, *+baseR (12) represents an offset of 12 bytes and the assembler writes out the instruction with offsetC = 12 and sc = 0.
5-230
STNDW
STNDW (.unit) src, *+baseR [16] represents an offset of 16 double words, or 128 bytes, and the assembler writes out the instruction with offsetC = 16 and sc = 1. Either brackets or parentheses must be typed around the specified offset if the optional offset parameter is used. Execution if (cond) {
src mem
} else nop Pipeline ___________________________________________________ Pipeline Stage E1 E2 E3
___________________________________________________ Read Written Unit in use

.D
____________________________________________________ Instruction Type Delay Slots See Also Example 1 Store 0 LDNW, LDNDW, STNW STNDW .D1 A3:A2, *A0++
A3
A176 3B28h
6041 AD65h
A3:A2
A176 3B28h
6041 AD65h
1009 00
1008 00
1007 00
1006 00
1005 00
1004 00
1003 00
1002 00
1001 00
1000 00
00
A1
76
3B
28
60
41
AD
65
00
5-231
STNDW
Example 2 STNDW .D1 A3:A2, *A0++
1 cycle after instruction A0 0000 100Bh
A3:A2
A176 3B28h
6041 AD65h
A3:A2
A176 3B28h
6041 AD65h
100B 00 00
100A 00 A1
1009 00 76
1008 00 3B
1007 00 28
1006 00 60
1005 00 41
1004 00 AD
1003 00 65
1002 00 00
1001 00 00
1000 00 00
5-232
STNW
STNW
Syntax
Store Non-Aligned Word

STNW(.unit) src,*mem .unit = .D1, .D2
For operand type... Unit uint uint uint uint uint ucst5 .D1, .D2
src baseR offset src baseR offset

Opcode
31 29 28 27 23 22 18 17
.D1, .D2
13
12
6 1
5 0 3
4 1
3 0 2
2 1
creg
3
z
1
dst
5
baseR
5
offset
5
mode
4
r
1
y
1
s
1
p
1
Description
The STNW instruction stores a 32-bit quantity to memory from a 32-bit register, src. The table below describes the addressing generator options. The STNW instruction may write a 32-bit value to any byte boundary. Thus alignment to a 32-bit boundary is not required. The effective memory address is formed from a base address register (baseR),and an optional offset that is either a register (offsetR) or a 5-bit unsigned constant (ucst5). Both offsetR and baseR must be in the same register file, and on the same side, as the .D unit used. The y bit in the opcode determines the .D unit and register file used: y = 0 selects the .D1 unit and baseR and offsetR from the A register file, and y = 1 selects the .D2 unit and baseR and offsetR from the B register file. The offsetR/ucst5 is scaled by a left shift of 2 bits. After scaling, offsetR/ucst5 is added to, or subtracted from, baseR. For the pre-increment, pre-decrement, positive offset, and negative offset address generator options, the result of the calculation is the address to be accessed in memory. For post-increment or post-decrement addressing, the value of baseR before the addition or subtraction is the address to be accessed from memory. The addressing arithmetic that performs the additions and subtractions defaults to linear mode. However, for A4A7 and for B4B7, the mode can be changed to circular mode by writing the appropriate value to the AMR.
5-233
STNW
The src can be in either register file, regardless of the .D unit or baseR or offsetR used. The s bit determines which file src will be loaded from: s = 0 indicates src will be in the A register file and s = 1 indicates src will be in the B register file. is always zero.
Table 513. STNW Address Generator Options

Note: No other memory access may be issued in parallel with a non-aligned memory access. The other .D unit can be used in parallel as long as it is not performing memory access. Assembler Notes When no bracketed register or constant is specified, the assembler defaults increments and decrements to 1 and offsets to 0. Loads that do no modification to the baseR can use the assembler syntax *R. Square brackets, [ ], indicate that the ucst5 offset is left-shifted by 2 for word stores. Parentheses, ( ), can be used to tell the assembler that the offset is a nonscaled, constant offset. The assember right shifts the constant by 2 bits for word stores before using it for the ucst5 field. After scaling by the STNW in5-234
STNW
struction, this results in the same constant offset as the assembler source if the least significant two bits are zeros. For example, STNW (.unit) src,*+baseR (12) represents an offset of 12 bytes (3 words), and the assembler writes out the instruction with ucst5 = 3.
STNW (.unit) src,*+baseR [12] represents an offset of 12 words, or 48 bytes, and the assembler writes out the instruction with ucst5 = 12. Either brackets or parentheses must be typed around the specified offset if the optional offset parameter is used. Execution if (cond) {
src mem
} else nop Pipeline ________________________________________________ Pipeline Stage E1 E2 E3
________________________________________________ Read Written Unit in use

.D
________________________________________________ Instruction Type Delay Slots See Also Store 0 LDNW, LDNDW, STNDW
5-235
STNW
Example 1 STNW .D1 A3, *A0++
A3
A176 3B28h
A3
A176 3B28h
1007 00 00
1006 00 00
1005 00 00
1004 00 A1
1003 00 76
1002 00 3B
1001 00 28
1000 00 00
Example 2
STNW .D1
A3, *A0++
A3
A176 3B28h
A3
A176 3B28h
1007 00 00
1006 00 A1
1005 00 76
1004 00 3B
1003 00 28
1002 00 00
1001 00 00
1000 00 00
5-236
SUB2
SUB2
Syntax
Two 16-Bit Integer Subtractions on Upper and Lower Register Halves

SUB2(.unit) src1,src2, dst .unit = .L1, .L2, .S1, .S2, .D1, .D2
For operand type... Unit i2 xi2 i2 i2 xi2 i2 i2 xi2 i2 .L1, .L2
Opfield 0000100

Opcode
.S1, .S2
010001
.D1, .D2
0101
.L unit
31 29 28 27 23 22 18 17 13 12 x 1 11 5 4 1 3 1 3 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
.S unit
31 29 28 27 23 22 18 17 13 12 x 1 11 6 5 1 4 0 3 0 4 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
6
s
1
p
1
.D unit
31 29 28 27 23 22 18 17 13 12 x 1 11 1 2 10 0 9 6 5 1 4 1 3 0 4 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1
5
op
4
s
1
p
1
Description
In the SUB2 instruction, the upper and lower halves of src2 are subtracted from the upper and lower halves of src1 and the result is placed in dst. Any borrow from the lower-half subtraction does not affect the upper-half subtraction. Specifically, the upper-half of src2 is subtracted from the upper-half of src1 and
5-237
SUB2
placed in the upper-half of dst. The lower-half of src2 is subtracted from the lower-half of src1 and placed in the lower-half of dst. This is the same SUB2 instruction found on the C62, but with the added flexibility of being able to perform this instruction on the .L and .D units as well as the .S unit.
31 a_hi SUB2 b_hi b_lo
src2
16
15 a_lo
0
src1
31
16
15 a_lob_lo
0
dst
a_hib_hi
Note: Unlike the SUB instruction, the argument ordering on the .D unit form of .S2 is consistent with the argument ordering for the .L and .S unit forms. Execution if (cond) { (lsb16(src1) lsb16(src2)) lsb16(dst); (msb16(src1) msb16(src2)) msb16(dst); } else nop Pipeline _________________________ Pipeline Stage E1
src1, src2 dst

.L,.S,.D
__________________________
5-238
SUB2
Instruction Type Delay Slots See Also Example 1 Single-cycle 0 ADD2, SUB, SUB4 SUB2 .S1 A3, A4, A5
Before instruction A3 1105 6E30h 4357 28208 A3 1 cycle after instruction 1105 6E30h 4357 28208
A4
1105 6980h
4357 27008
A4
1105 6980h
4357 27008
A5
XXXX XXXXh
A5
0000 04B0h
0 1200
Example 2
SUB2 .D2 B2, B8, B15

Before instruction B2 F23A 3789h 3526 14217 B2 1 cycle after instruction F23A 3789h 3526 14217
B8
04B8 6732h
1208 26418
B8
04B8 6732h
1208 26418
B15
XXXX XXXXh
B15
ED82 D057h
4734 12201
5-239
SUB4
SUB4
Syntax
Subtract Without Saturation, Signed Packed 8-Bit

SUB4 (.unit) src1,src2, dst .unit = .L1, .L2
For operand type... Unit i4 xi4 i4 .L1, .L2
Opfield 1100110
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11
4 1
3 1 3
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
Description
The SUB4 instruction performs 2s-complement subtraction between packed 8-bit quantities. The values in src1 and src2 are treated as packed 8-bit quantities, and the results are written into dst in a packed 8-bit format. For each pair of 8-bit quantities in src1 and src2, the difference between the 8-bit value from src1 and the 8-bit value from src2 is calculated to produce an 8-bit result. The result is placed in the corresponding position in dst. Specifically, the difference between src1 byte0 and src2 byte0 is placed byte0 of dst. The difference between src1 byte1 and src2 byte1 is placed byte1 of dst. The difference between src1 byte2 and src2 byte2 is placed byte2 of dst. The difference between src1 byte3 and src2 byte3 is placed byte3 of dst. No saturation is performed.
31 a_3 3 24 23 a_2 2 16 15 a_1 1 8 7 a_0 0 0
in in in in
src1 1
SUB4
b_3 b 3 b_2 b 2 b_1 b 1 b_0 b 0
src2 2
31 a_3b_3
24
23 a_2b_2
16
15 a_1b_1
7 a_0b_0
dst
5-240
SUB4
Execution if (cond) { (byte0(src1) byte0(src2)) byte0(dst); (byte1(src1) byte1(src2)) byte1(dst); (byte2(src1) byte2(src2)) byte2(dst); (byte3(src1) byte3(src2)) byte3(dst); } else nop Pipeline _________________________ Pipeline Stage E1
src1, src2 dst

.L
__________________________ Instruction Type Delay Slots See Also Example Single-cycle 0 ADD4, SUB, SUB2 SUB4 .L1 A2, A8, A9
Before instruction A2 37 89 F2 3Ah A2 1 cycle after instruction 37 89 F2 3Ah
A8
04 B8 49 75h
A8
04 B8 49 75h
A9
XXXX XXXXh
A9
33 D1 A9 C5h
5-241
SUBABS4
SUBABS4
Syntax
Subtract With Absolute Value, Unsigned Packed 8-Bit

SUBABS4 (.unit) src1,src2, dst .unit = .L1, .L2
Opfield
src1 src2 dst

Opcode
31 29 28 27 23 22 18 17
.L1, .L2 1011010
13
12 x 1
11
4 1
3 1 3
2 0
creg
3
z
1
dst
5
src2
5
src1
5
op
7
s
1
p
1
Description
The SUBABS4 instruction calculates the absolute value of the differences between the packed 8-bit data contained in the source registers. The values in src1 and src2 are treated as unsigned, packed 8-bit quantities. The result is written into dst in an unsigned, packed 8-bit format. For each pair of unsigned 8-bit values in src1 and src2, the absolute value of the difference is calculated. This result is then placed in the corresponding position in dst. Specifically, the absolute value of the difference between src1 byte0 and src2 byte0 is placed in byte0 of dst. The absolute value of the difference between src1 byte1 and src2 byte1 is placed in byte1 of dst. The absolute value of the difference between src1 byte2 and src2 byte2 is placed in byte2 of dst. And the absolute value of the difference between src1 byte3 and src2 byte3 is placed in byte3 of dst.
5-242
SUBABS4
31 ua_3 3
24
23 ua_2 2
16
15 ua_1 1
7 ua_0 0
src1 1
SUBABS4
ub_3 b 3 ub_2 b 2 ub_1 b 1 ub_0 b 0
src2 2
31
24
23
16
15 ABS(ua_1ub_1)
7 ABS(ua_0ub_0)
ABS(ua_3ub_3)
ABS(ua_2ub_2)
dst
The SUBABS4 instruction aids in motion-estimation algorithms, and other algorithms, that compute the best match between two sets of 8-bit quantities. Execution if (cond) { ABS(ubyte0(src1) ubyte0(src2)) ubyte0(dst); ABS(ubyte1(src1) ubyte1(src2)) ubyte1(dst); ABS (ubyte2(src1) ubyte2(src2)) ubyte2(dst); ABS (ubyte3(src1) ubyte3(src2)) ubyte3(dst); } else nop Pipeline _________________________ Pipeline Stage E1
src1, src2 dst

.L
__________________________ Instruction Type Delay Slots See Also Single-cycle 0 ABS, SUB, SUB4
5-243
SUBABS4
Example SUBABS4 .L1 A2, A8, A9
Before instruction A2 37 89 F2 3Ah 55 137 242 58 unsigned A8 04 B8 49 75h 4 184 73 117 unsigned A9 XXXX XXXXh A9 33 2F A9 3Bh A8 04 B8 49 75h A2 1 cycle after instruction 37 89 F2 3Ah 55 137 242 58 unsigned 4 184 73 117 unsigned 51 47 169 59 unsigned
5-244
SWAP2
SWAP2
Syntax
Swap Bytes in Each Half-Word (Pseudo-Operation)

SWAP2 (.unit) src2, dst .unit = .L1, .L2 or .S1, .S2
For operand type... Unit s2 s2 s2 s2 .L1, .L2 .S1, .S2
Opfield 0011011 010000
src2 dst src2 dst

Opcode Description See PACKLH2 instruction.
The SWAP2 is a pseudo-operation that takes the lower half-word from src2 and places it in the upper half-word of dst, while the upper-half word from src2 is placed in the lower half-word of dst.
31 b_hi
16
15 b_lo
src2
SWAP2
b_lo b_hi
dst
The SWAP2 instruction can be used in conjunction with the SWAP4 instruction to change the byte ordering (and therefore, the endianess) of 32-bit data. Execution if (cond) { msb16(src2) lsb16(dst); lsb16(src2) msb16(dst); } else nop
5-245
SWAP2
src2 dst
.L, .S
__________________________ Instruction Type Delay Slots Example 1 Single-cycle 0 SWAP2 .L1 A2,A9
A9
XXXX XXXXh
A9
F23A 3789h
3526 14217
Example 2
SWAP2 .S2 B2,B12

Before instruction B2 0124 2451h 292 9297 B2 1 cycle after instruction 0124 2451h 292 9297
B12
XXXX XXXXh
B12
2451 0124h
9297 292
5-246
SWAP4
SWAP4
Syntax
Swap Bytes in Each Half-Word

SWAP4 (.unit) src2, dst .unit = .L1, .L2
For operand type... Unit xu4 u4 .L1, .L2
Opfield 00001
src2 dst
Opcode
31 29 28 27 23 22 18 17
13
12 x 1
11 0
10 0
9 1
8 1
7 0 10
6 1
5 0
4 1
3 1
2 0
creg
3
z
1
dst
5
src
5
op
5
s
1
p
1
Description
The SWAP4 instruction exchanges pairs of bytes within each half-word of src2, placing the result in dst. The values in src2 are treated as unsigned, packed 8-bit values. Specifically the upper byte in the upper half-word is placed in the lower byte in the upper halfword, while the lower byte of the upper half-word is placed in the upper byte of the upper half-word. Also the upper byte in the lower halfword is placed in the lower byte of the lower half-word, while the lower byte in the lower half-word is placed in the upper byte of the lower half word.
31 ub_3 b 3
24
23 ub_2 b 2
16
15 ub_1 b 1
7 ub_0 b 0
src2 2
SWAP4
ub_2 b 2 ub_3 b 3 ub_0 b 0 ub_1 b 1
dst d t
By itself, this instruction changes the ordering of bytes within half words. This effectively changes the endianess of 16-bit data packed in 32-bit words. The endianess of full 32-bit quantities can be changes by using the SWAP4 instruction in conjunction with the SWAP2 instruction.
5-247
SWAP4
Execution if (cond) { ubyte0(src2) ubyte1(dst); ubyte1(src2) ubyte0(dst); ubyte2(src2) ubyte3(dst); ubyte3(src2) ubyte2(dst); } else nop Pipeline _________________________ Pipeline Stage E1
src2 dst
.L
__________________________ Instruction Type Delay Slots See Also Example Single-cycle 0 SWAP2 SWAP4 .L1 A1,A2
1 cycle after instruction A1 9E 52 6E 30h
Before instruction A1 9E 52 6E 30h
A2
XXXX XXXXh
A2
52 9E 30 6Eh
5-248
UNPKHU4
UNPKHU4
Syntax
Unpack High Unsigned Packed 8-Bit to Unsigned Packed 16-Bit

UNPKHU4 (.unit) src2, dst .unit = .L1, .L2, .S1, .S2
For operand type... Unit xu4 u2 xu4 u2 .L1, .L2 .S1, .S2
Opfield 00011 00011
src2 dst src2 dst

Opcode
.L unit
31 29 28 27 23 22 18 17 13 12 x 1 11 0 10 0 9 1 8 1 7 0 10 6 1 5 0 4 1 3 1 2 0 1 0
creg
3
z
1
dst
5
src
5
op
5
s
1
p
1
.S unit
31 29 28 27 23 22 18 17 13 12 x 1 11 1 10 1 9 1 8 1 7 0 10 6 0 5 1 4 0 3 0 2 0 1 0
creg
3
z
1
dst
5
src
5
op
5
s
1
p
1
Description
The UNPKHU4 instruction moves the two most significant bytes of src2 into the two low bytes of the two half-words of dst. Specifically the upper byte in the upper half-word is placed in the lower byte in the upper halfword, while the lower byte of the upper half-word is placed in the lower byte of the lower half-word. The src2 bytes are zero-extended when unpacked, filling the two high bytes of the two half-words of dst with zeros.
31 ub_3 b 3
24
23 ub_2 b 2
16
15 ub_1 b 1
7 ub_0 b 0
src2 2
UNPKHU4 00000000 ub_3 b 3 00000000 ub_2 b 2
dst d t
5-249
UNPKHU4
Execution if (cond) { ubyte3(src2) ubyte2(dst); 0 ubyte3(dst); ubyte2(src2) ubyte0(dst); 0 ubyte1(dst); } else nop Pipeline _________________________ Pipeline Stage E1
src2 dst
.L, .S
__________________________ Instruction Type Delay Slots See Also Example 1 Single cycle 0 UNPKLU4 UNPKHU4 .L1 A1,A2
Before instruction A1 9E 52 6E 30h A1 1 cycle after instruction 9E 52 6E 30h
A2
XXXX XXXXh
A2
00 9E 00 52h
Example 2
UNPKHU4 .L2 B17,B18

B18
XXXX XXXXh
B18
00 11 00 05h
5-250
UNPKLU4
UNPKLU4
Syntax
Unpack Low Unsigned Packed 8-Bit to Unsigned Packed 16-Bit

UNPKLU4 (.unit) src2, dst .unit = .L1, .L2, .S1, .S2
For operand type... Unit xu4 u2 xu4 u2 .L1, .L2 .S1, .S2
Opfield 00010 00010
src2 dst src2 dst

Opcode
.L unit
31 29 28 27 23 22 18 17 13 12 x 1 11 0 10 0 9 1 8 1 7 0 10 6 1 5 0 4 1 3 1 2 0 1 0
creg
3
z
1
dst
5
src
5
op
5
s
1
p
1
.S unit
31 29 28 27 23 22 18 17 13 12 x 1 11 1 10 1 9 1 8 1 7 0 10 6 0 5 1 4 0 3 0 2 0 1 0
creg
3
z
1
dst
5
src
5
op
5
s
1
p
1
Description
The UNPKLU4 instruction moves the two least significant bytes of src2 into the two low bytes of the two half-words of dst. Specifically the upper byte in the lower half-word is placed in the lower byte in the upper halfword, while the lower byte of the lower half-word is kept in the lower byte of the lower half-word. The src2 bytes are zero-extended when unpacked, filling the two high bytes of the two half-words of dst with zeros.
31 ub_3 b 3
24
23 ub_2 b 2
16
15 ub_1 b 1
7 ub_0 b 0
src2 2
UNPKLU4 00000000 ub_1 b 1 00000000 ub_0 b 0
dst d t
5-251
UNPKLU4
Execution if (cond) { ubyte0(src2) ubyte0(dst); 0 ubyte1(dst); ubyte1(src2) ubyte2(dst); 0 ubyte3(dst); } else nop Pipeline _________________________ Pipeline Stage E1
src2 dst
.L, .S
__________________________ Instruction Type Delay Slots See Also Example 1 Single cycle 0 UNPKHU4 UNPKLU4 .L1 A1,A2
Before instruction A1 9E 52 6E 30h A1 1 cycle after instruction 9E 52 6E 30h
A2
XXXX XXXXh
A2
00 6E 00 30h
5-252
UNPKLU4
Example 2 UNPKLU4 .L2 B17,B18
B18
XXXX XXXXh
B18
00 69 00 34h
5-253
XOR
XOR
Syntax
Bitwise XOR
XOR (.unit) src1, src2, dst .unit = .L1, .L2, .S1, .S2, .D1 or .D2 Opcode map field used... For operand type... Unit uint xint uint scst5 xuint uint uint xunit uint scst5 xuint uint uint xuint uint scst5 xuint uint .L1, .L2 Opfield 1101111
src1 src2 dst src1 src2 dst src1 src2 dst src1 src2 dst src src2 dst src1 src2 dst
Opcode
.L1, .L2
1101110
.S1, .S2
001011
.S1, .S2
001010
.D1, .D2
1110
.D1, .D2
1111
.L unit
31 29 28 27 23 22 18 17 13 12 x 1 11 5 4 1 3 1 3 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1/cst5
5
op
7
s
1
p
1
.S unit
31 29 28 27 23 22 18 17 13 12 x 1 11 6 5 1 4 0 4 3 0 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1/cst5
5
op
6
s
1
p
1
.D unit
31 29 28 27 23 22 18 17 13 12 x 1 11 1 2 10 0 9 8 7 6 5 1 4 1 4 3 0 2 0 1 0
creg
3
z
1
dst
5
src2
5
src1/cst5
5
op
4
s
1
p
1
5-254
XOR
Description In the XOR instruction, a bitwise exclusive OR is performed between src1 and src2. The result is placed in dst. The scst5 operands are sign extended to 32 bits. This is the same XOR instruction that is found on the C62x, but with the added flexibility of being able to perform this operation on the .D unit as well as the .L and .S units. if (cond) src1 XOR src2 dst else nop Pipeline _________________________ Pipeline Stage E1
Execution
src1, src2 dst

.L, .S, or .D
__________________________ Instruction Type Delay Slots See Also Example 1 Single cycle 0 AND, ANDN, OR XOR .S1 A3, A4, A5
Before instruction A3 0721 325Ah A3 1 cycle after instruction 0721 325Ah
A4
0019 0F12h
A4
0019 0F12h
A5
XXXX XXXXh
A5
0738 3D48h
5-255
XOR
Example 2 XOR .D2 B1,0dh,B8
B8
XXXX XXXXh
B8
0000 102Eh
5-256
XPND2
XPND2
Syntax
Expand Bits to Packed 16-Bit Masks

XPND2 (.unit) src2, dst .unit = .M1, .M2
For operand type... Unit xuint uint
Opfield
src2 dst
Opcode
31 29 28 27 23 22 18 17
.M1, .M2 11001
13
12 x 1
11 0
10 0
9 0
8 0
7 1 10
6 1
5 1
4 1
3 0
2 0
creg
3
z
1
dst
5
src
5
op
5
s
1
p
1
Description
The XPND2 instruction reads the two least-significant bits of src2 and expands them into two half-word masks written to dst. Bit 1 of src2 is replicated and placed in the upper half-word of dst. Bit 0 of src2 is replicated and placed in the lower half-word of dst. Bits 2 through 31 of src2 are ignored.
24 23 XXXXXXXX 16 15 XXXXXXXX 8 7 XXXXXX10 0
31 XXXXXXXX
src2 2
31 11111111 11111111
16
15 00000000
7 00000000
d t dst
The XPND2 instruction is useful, when combined with the output of CMPGT2 or CMPEQ2, for generating a mask that corresponds to the individual halfword positions that were compared. That mask may then be used with ANDN, AND or OR instructions to perform other operations like compositing. This is an example: CMPGT2 XPND2 NOP AND .D1 A2, A7, A8 ; Apply the mask to a value to create result.
5-257
.S1 A3, A4, A5 ; Compare two registers, both upper and ; lower halves. .M1 A5, A2 ; Expand the compare results into two 16-bit ;masks.
XPND2
Because XPND2 only examines the two least-significant bits of src2, it is possible to store a large bit mask in a single 32-bit word and expand it using multiple SHR and XPND2 pairs. This can be useful for expanding a packed 1-bit per pixel bitmap into full 16-bit pixels in imaging applications. Execution if (cond) { XPND2(src2 & 1) lsb16(dst); XPND2(src2 & 2) msb16(dst); } else nop Pipeline __________________________ Pipeline Stage E1 E2
src2 dst
__________________________ Instruction Type Delay Slots See Also Example 1 Two-cycle 1 CMPEQ2, CMPGT2, XPND4 XPND2 .M1 A1,A2
Before instruction A1 B174 6CA1h 2 LSBs are 01 A1 2 cycles after instruction B174 6CA1h 2 LSBs are 01
A2
XXXX XXXXh
A2
0000 FFFFh
5-258
XPND2
Example 2 XPND2 .M2 B1,B2
Before instruction B1 0000 0003h 2 LSBs are 11 B1 2 cycles after instruction 0000 0003h 2 LSBs are 11
B2
XXXX XXXXh
B2
FFFF FFFFh
5-259
XPND4
XPND4
Syntax
Expand Bits to Packed 8-Bit Masks

XPND4 (.unit) src2, dst .unit = .M1, .M2
For operand type... Unit xuint uint
Opfield
src2 dst
Opcode
31 29 28 27 23 22 18 17
.M1, .M2 11000
13
12 x 1
11 0
10 0
9 0
8 0
7 1 10
6 1
5 1
4 1
3 0
2 0
creg
3
z
1
dst
5
src
5
op
5
s
1
p
1
Description
The XPND4 instruction reads the four least-significant bits of src2 and expands them into four-byte masks written to dst. Bit 0 of src2 is replicated and placed in the least significant byte of dst. Bit 1 of src2 is replicated and placed in second least significant byte of dst. Bit 2 of src2 is replicated and placed in second most significant byte of dst. Bit 3 of src2 is replicated and placed in most significant byte of dst. Bits 4 through 31 of src2 are ignored.
24 23 XXXXXXXX 16 15 XXXXXXXX 8 7 XXXX1001 0
31 XXXXXXXX
2 src2
31 11111111
24
23 00000000
16
15 00000000
7 11111111
dst
5-260
XPND4
The XPND4 instruction is useful, when combined with the output of CMPGT4 or CMPEQ4, for generating a mask that corresponds to the individual byte positions that were compared. That mask may then be used with ANDN, AND or OR instructions to perform other operations like compositing. This is an example: CMPEQ4 XPND4 NOP AND .D1 A2, A7, A8 ; Apply the mask to a value to create result. .S1 A3, A4, A5 ; Compare two 32-bit registers all four bytes. .M1 A5, A2 ; Expand the compare results into four 8-bit ; masks.
Because XPND4 only examines the four least-significant bits of src2, it is possible to store a large bit mask in a single 32-bit word and expand it using multiple SHR and XPND4 pairs. This can be useful for expanding a packed, 1-bit per pixel bitmap into full 8-bit pixels in imaging applications. Execution if (cond) { XPND4(src2 & 1) byte0(dst); XPND4(src2 & 2) byte1(dst); XPND4(src2 & 4) byte2(dst); XPND4(src2 & 8) byte3(dst); } else nop Pipeline __________________________ Pipeline Stage E1 E2
src2 dst
__________________________ Instruction Type Delay Slots See Also Two-cycle 1 CMPEQ4, CMPGTU4, XPND2
5-261
XPND4
Example 1 XPND4 .M1 A1,A2
Before instruction A1 B174 6CA4h 4 LSBs are 0100 A1 2 cycles after instruction B174 6CA4h 4 LSBs are 0100
A2
XXXX XXXXh
A2
00 FF 00 00h
Example 2
XPND4 .M2 B1,B2

Before instruction B1 0000 000Ah 4 LSBs are 1010 B1 2 cycles after instruction 00 00 00 0Ah 4 LSBs are 1010
B12
XXXX XXXXh
B2
FF 00 FF 00h
5-262
Chapter 6
TMS320C62x/C64x Pipeline
The TMS320C62x/TMS320C64x DSP pipeline provides flexibility to simplify programming and improve performance. These two factors provide this flexibility: 1) Control of the pipeline is simplified by eliminating pipeline interlocks. 2) Increased pipelining eliminates traditional architectural bottlenecks in program fetch, data access, and multiply operations. This provides singlecycle throughput. This chapter starts with a description of the pipeline flow. Highlights are:
- The pipeline can dispatch eight parallel instructions every cycle. - Parallel instructions proceed simultaneously through each pipeline
phase. - Serial instructions proceed through the pipeline with a fixed relative phase difference between instructions. - Load and store addresses appear on the CPU boundary during the same pipeline phase, eliminating read-after-write memory conflicts. All instructions require the same number of pipeline phases for fetch and decode, but require a varying number of execute phases. This chapter contains a description of the number of execution phases for each type of instruction. The C62x/C64x generally requires fewer execution phases than the C67x because the C62x/C64x executes only fixed-point instructions. Finally, the chapter contains performance considerations for the pipeline. These considerations include the occurrence of fetch packets that contain multiple execute packets, execute packets that contain multicycle NOPs, and memory considerations for the pipeline. For more information about fully optimizing a program and taking full advantage of the pipeline, see the TMS320C6000 Programmers Guide (SPRU198).
Topic
6.1 6.2 6.3
Page
Pipeline Operation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Pipeline Execution of Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Performance Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
August 1996
6-1
Pipeline Operation Overview
6.1 Pipeline Operation Overview

The pipeline phases are divided into three stages:
- Fetch - Decode - Execute
All instructions in the C62x/C64x instruction set flow through the fetch, decode, and execute stages of the pipeline. The fetch stage of the pipeline has four phases for all instructions, and the decode stage has two phases for all instructions. The execute stage of the pipeline requires a varying number of phases, depending on the type of instruction. The stages of the C62x/C64x pipeline are shown in Figure 61.
Figure 61. Fixed-Point Pipeline Stages

Fetch Decode Execute
6.1.1
Fetch
The fetch phases of the pipeline are:
-
PG: Program address generate PS: Program address send PW: Program access ready wait PR: Program fetch packet receive
The C62x/C64x uses a fetch packet (FP) of eight instructions. All eight of the instructions proceed through fetch processing together, through the PG, PS, PW, and PR phases. Figure 62(a) shows the fetch phases in sequential order from left to right. Figure 62(b) is a functional diagram of the flow of instructions through the fetch phases. During the PG phase, the program address is generated in the CPU. In the PS phase, the program address is sent to memory. In the PW phase, a memory read occurs. Finally, in the PR phase, the fetch packet is received at the CPU. Figure 62(c) shows fetch packets flowing through the phases of the fetch stage of the pipeline. In Figure 62(c), the first fetch packet (in PR) is made up of four execute packets, and the second and third fetch packets (in PW and PS) contain two execute packets each. The last fetch packet (in PG) contains a single execute packet of eight instructions.
6-2
Figure 62. Fetch Phases of the Pipeline

CPU
(a)
PG PS PW PR
(b)
Functional units
Registers PR PG PS Memory
PW
(c)
Fetch LDW LDW LDW LDW LDW LDW LDW LDW SHR SMPYH MVKLH MVK SHR SMPY MV ADD
256 SMPYH SADD SMPYH SHL SMPYH SADD SMPY LDW MV B B LDW NOP MVK MVK MVK PG PS PW PR
Decode
6-3
6.1.2
Decode
The decode phases of the pipeline are:
- DP: Instruction dispatch - DC: Instruction decode
In the DP phase of the pipeline, the fetch packets are split into execute packets. Execute packets consist of one instruction or from two to eight parallel instructions. During the DP phase, the instructions in an execute packet are assigned to the appropriate functional units. In the DC phase, the the source registers, destination registers, and associated paths are decoded for the execution of the instructions in the functional units. Figure 63(a) shows the decode phases in sequential order from left to right. Figure 63(b) shows a fetch packet that contains two execute packets as they are processed through the decode stage of the pipeline. The last six instructions of the fetch packet (FP) are parallel and form an execute packet (EP). This EP is in the dispatch phase (DP) of the decode stage. The arrows indicate each instructions assigned functional unit for execution during the same cycle. The NOP instruction in the eighth slot of the FP is not dispatched to a functional unit because there is no execution associated with it. The first two slots of the fetch packet (shaded below) represent an execute packet of two parallel instructions that were dispatched on the previous cycle. This execute packet contains two MPY instructions that are now in decode (DC) one cycle before execution. There are no instructions decoded for the .L, .S, and .D functional units for the situation illustrated.
Figure 63. Decode Phases of the Pipeline

(a)
DP
(b)
DC
Decode
32
32
32 ADD
32 ADD
32 STW
32 STW
32 ADDK
32 NOP
DP
MPYH
MPYH
DC
.L1
.S1
.M1
.D1
Functional units
.D2
.M2
.S2
.L2
NOP is not dispatched to a functional unit.
6-4
6.1.3
Execute
The execute portion of the fixed-point pipeline is subdivided into five phases (E1E5). Different types of instructions require different numbers of these phases to complete their execution. These phases of the pipeline play an important role in your understanding the device state at CPU cycle boundaries. The execution of different types of instructions in the pipeline is described in section 6.2, Pipeline Execution of Instruction Types. Figure 64(a) shows the execute phases of the pipeline in sequential order from left to right. Figure 64(b) and (c) show the portion of the functional block diagram in which execution occurs on the C62x and C64x, respectively.
6-5
Figure 64. Execute Phases of the Pipeline and Functional Block Diagram of the TMS320C62x/C64x
(a)
E1 E2 E3 E4 E5
(b) C62x
Execute SADD .L1 B .S1 SMPY .M1 STH .D1 E1 STH .D2 SMPYH .M2 SUB .S2 SADD .L2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Register file A ST1 LD1 32
32
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 Register file B ST2 32 LD2
Data memory interface control 32 0 8 16 1 9 2 16 3 4 16 5 6 16 7 DA2 Data address 2 32
DA1 Data address 1
Internal data memory (byte addressable)
6-6
Figure 64.Execute Phases of the Pipeline and Functional Block Diagram of the TMS320C62x/C64x (Continued)
(c) C64x
Execute SADD .L1 B .S1 SMPY .M1 STH .D1
E1 STH .D2 SMPYH .M2 SUB .S2 SADD .L2
..
31 30 29 28 10 9 8 7 6 5 4 3 2 1 0 Register file A 64 64 LD1 ST1 32 DA1 Data address 1
32
..
31 30 29 28 LD2 64 64 ST2 DA2 Data address 2 32 10 9 8 7 6 5 4 3 2 1 0 Register file B
L1 Data cache control
6.1.4
Summary of Pipeline Operation

Figure 65 shows all the phases in each stage of the C62x/C64x pipeline in sequential order, from left to right.
Figure 65. Fixed-Point Pipeline Phases

Fetch PG PS PW PR Decode DP DC E1 E2 Execute E3 E4 E5
Figure 66 shows an example of the pipeline flow of consecutive fetch packets that contain eight parallel instructions. In this case, where the pipeline is full, all instructions in a fetch packet are in parallel and split into one execute packet per fetch packet. The fetch packets flow in lockstep fashion through each phase of the pipeline. For example, examine cycle 7 in Figure 66. When the instructions from FP n reach E1, the instructions in the execute packet from FPn +1 are being decoded. FP n + 2 is in dispatch while FPs n + 3, n + 4, n + 5, and n + 6 are each in one of four phases of program fetch. See section 6.3, Performance Considerations, on page 6-21 for additional detail on code flowing through the pipeline.
6-7
Figure 66. Pipeline Operation: One Execute Packet per Fetch Packet

Clock cycle 6 7 Fetch packet n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 1 2 3 4 5 8 9 10
E4 E3 E2 E1
11
E5 E4 E3 E2 E1
12
E5 E4 E3 E2 E1
13
PG
PS
PW PS
PR
DP PR
DC DP
E1
E2 E1
E3 E2 E1
PG
PW PS
DC DP PR
PG
PW PS
PR
DC DP PR
E5 E4 E3 E2 E1
PG
PW PS
DC DP PR
PG
PW PS
DC DP PR
PG
PW PS
DC DP PR
PG
PW PS
DC DP PR
PG
PW PS
DC DP PR
PG
PW PS
PG
PW PS
PG
PW
Table 61 summarizes the pipeline phases and what happens in each.
Table 61. Operations Occurring During Fixed-Point Pipeline Phases

Stage Phase Symbol During This Phase PG PS Instruction Type Completed Program fetch Program address generate Program address send Program wait Program data receive Dispatch The address of the fetch packet is determined. PW PR DP The address of the fetch packet is sent to memory. A program memory access is performed. The fetch packet is at the CPU boundary. Program decode Execute Decode Execute 1 DC E1 The next execute packet in the fetch packet is determined and sent to the appropriate functional units to be decoded. Instructions are decoded in functional units. For all instruction types, the conditions for the instructions are evaluated and operands are read. For load and store instructions, address generation is performed and address modifications are written to a register file. Single cycle For branch instructions, branch fetch packet in PG phase is affected. For single-cycle instructions, results are written to a register file. 6-8
Table 61. Operations Occurring During Fixed-Point Pipeline Phases (Continued)

Stage Phase Symbol During This Phase E2 Instruction Type Completed Execute 2 For load instructions, the address is sent to memory. For store instructions, the address and data are sent to memory. Single-cycle instructions that saturate results set the SAT bit in the control status register (CSR) if saturation occurs. Execute 3 E3
Execute 4
E4
Execute 5
E5
For single 16 x 16 multiply instructions, results are written to a register file. For C64x multiply unit non-multiply instructions, results are written to a register file.} Data memory accesses are performed. Any multiply instruction that saturates results sets the SAT bit in the control status register (CSR) if saturation occurs. For load instructions, data is brought to the CPU boundary. For C64x multiply extensions, results are written to a register file. For load instructions, data is written into a register.
Multiply
Store
Multiply Extensions Load
This assumes that the conditions for the instructions are evaluated as true. If the condition is evaluated as false, the instruction does not write any results or have any pipeline operation after E1. Multiply unit, non-multiply instructions are AVG2, AVG4, BITC4, BITR, DEAL, ROT, SHFL, SSHVL, and SSHVR. Multiply extensions include MPY2, MPY4, DOTPx2, DOTPU4, MPYHIx, MPYLIx, and MVD.
6-9
Figure 67 shows a C62x functional block diagram laid out vertically by stages of the pipeline.
Figure 67. Functional Block Diagram of TMS320C62x Based on Pipeline Phases

Fetch STH LDW STH LDW Decode 32 STH STH LDW STH LDW 32 STH SADD SADD SADD SADD 32 SADD SADD SADD SADD SADD 32 SADD 256 SMPYH SMPYH SMPYH SMPYH 32 SMPYH SMPY SMPYH SMPY SMPYH 32 SMPY SUB SHR SUB SHR 32 SUB B SHR B SHR 32 B PG PS PW PR
DP
SHR Execute SADD .L1 B .S1
SMPYH
LDW
LDW
SMPYH
SHR
MV
DC
SMPY .M1
.D1
.D2
SMPYH .M2
MVK .S2
SADD .L2
E1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST 1 LD 1 Register file A 32 Data 1 32 DA 1
32
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST 2 LD 2 Register file B 32 Data 2 32 DA 2
Data memory interface control 32 0 8 Data address 1 16 1 9 2 16 3 4 16 5 6 16 7 Data address 2 32
6-10
Figure 68 shows a C64x functional block diagram laid out vertically by stages of the pipeline. It is identical to Figure 67 except for the additional registers and functional unit hardware that are not being used in the code example being shown.

Fetch STH LDW STH LDW Decode 32 STH STH LDW STH LDW 32 STH SADD SADD SADD SADD 32 SADD SADD SADD SADD SADD 32 SADD 256 SMPYH SMPYH SMPYH SMPYH 32 SMPYH SMPY SMPYH SMPY SMPYH 32 SMPY SUB SHR SUB SHR 32 SUB B SHR B SHR 32 B PG PS PW PR
DP
SHR Execute SADD .L1 B .S1
SMPYH
LDW
LDW
SMPYH
SHR
MV
DC
SMPY .M1
.D1
.D2
SMPYH .M2
MVK .S2
SADD .L2
E1
..
31 30 29 28 10 9 8 7 6 5 4 3 2 1 0 ST 1 Data 1 LD 1 Register file A 64 64 32 DA 1
32
..
31 30 29 28 10 9 8 7 6 5 4 3 2 1 0 Data 2 ST 2 LD 2 Register file B 64 64 DA 2 32
Data cache control
6-11
The pipeline operation is based on CPU cycles. A CPU cycle is the period during which a particular execute packet is in a particular pipeline phase. CPU cycle boundaries always occur at clock cycle boundaries. As code flows through the pipeline phases, it is processed by different parts of the C62x/C64x. Figure 67 and Figure 68 show a full pipeline with a fetch packet in every phase of fetch. One execute packet of eight instructions is being dispatched at the same time that a 7-instruction execute packet is in decode. The arrows between DP and DC correspond to the functional units identified in the code in Example 61.
Example 61. Execute Packet in Figure 67 and Figure 68

|| || || || || SADD SADD SMPYH SMPY B MVK LDW LDW MV SMPYH SMPYH SHR SHR .L1 .L2 .M2X .M1X .S1 .S2 .D2 .D1 .L2X .M1 .M2 .S1 .S2 A2,A7,A2 B2,B7,B2 B3,A3,B2 B3,A3,A2 LOOP1 117,B1 *B4++,B3 *A4++,A3 A1,B0 A2,A2,A0 B2,B2,B10 A2,16,A5 B2,16,B5 ; E1 Phase
; DC Phase
|| || || || || || LOOP1:
STH Phases || || || || || || [B1] || [B1] STH SADD SADD SMPYH SMPY B SUB LDW LDW SADD SADD SMPYH SMPYH SHR SHR
.D1 .D2 .L1 .L2 .M2X .M1X .S1 .S2 .D2 .D1 .L1 .L2 .M1 .M2 .S1 .S2
A5,*A8++[2] B5,*B8++[2] A2,A7.A2 B2,B7,B2 B3,A3,B2 B3,A3,A2 LOOP1 B1,1,B1 *B4++,B3 *A4++,A3 A0,A1,A1 B10,B0,B0 A2,A2,A0 B2,B2,B10 A2,16,A5 B2,16,B5
; DP, PW, and PG
: PR and PS Phases
|| || || || || || ||
6-12
In the DC phase portion of Figure 67 and Figure 68, one box is empty because a NOP was the eighth instruction in the fetch packet in DC and no functional unit is needed for a NOP. Finally, the figure shows six functional units processing code during the same cycle of the pipeline. Registers used by the instructions in E1 are shaded in Figure 67 and Figure 68. The multiplexers used for the input operands to the functional units are also shaded in the figure. The bold crosspaths are used by the MPY instructions. Most C62x/C64x instructions are single-cycle instructions, which means they have only one execution phase (E1). A small number of instructions require more than one execute phase. The types of instructions, each of which require different numbers of execute phases, are described in section 6.2, Pipeline Execution of Instruction Types.
6-13
Pipeline Execution of Instruction Types
6.2 Pipeline Execution of Instruction Types

The pipeline operation of the C62x/C64x instructions can be categorized into seven instruction types. Six of these are shown in Table 62 (NOP is not included in the table), which is a mapping of operations occurring in each execution phase for the different instruction types. The delay slots associated with each instruction type are listed in the bottom row.
Table 62. Execution Stage Length Description for Each Instruction Type

Instruction Type Single Cycle 16 X 16 Single Multiply/ C64x .M Unit Non-Multiply Store C64x Multiply Extensions Load Branch Execution E1 Compute phases result and write to register E2 Read operands and start computations Compute address Reads operands and start computations Compute address Targetcode in PG

Compute result and write to register Send address and data to memory Access memory Send address to memory Access memory E3 E4 Write results to register Send data back to CPU Write data into register 4 E5 Delay slots 0 1 0 3 5
See sections 6.2.3 and 6.2.5 for more information on execution and delay slots for stores and loads. See section 6.2.6 for more information on branches. Notes: 2) NOP is not shown and has no operation in any of the execution phases.
1) This table assumes that the condition for each instruction is evaluated as true. If the condition is evaluated as false, the instruction does not write any results or have any pipeline operation after E1.
The execution of instructions can be defined in terms of delay slots. A delay slot is a CPU cycle that occurs after the first execution phase (E1) of an instruction. Results from instructions with delay slots are not available until the end of the last delay slot. For example, a multiply instruction has one delay slot, which means that one CPU cycle elapses before the results of the multiply are available for use by a subsequent instruction. However, results are available
6-14
from other instructions finishing execution during the same CPU cycle in which the multiply is in a delay slot.
6.2.1
Single-Cycle Instructions
Single-cycle instructions complete execution during the E1 phase of the pipeline. Figure 69 shows the fetch, decode, and execute phases of the pipeline that single-cycle instructions use.
Figure 69. Single-Cycle Instruction Phases

PG PS PW PR DP DC E1
Figure 610 shows the single-cycle execution diagram. The operands are read, the operation is performed, and the results are written to a register, all during E1. Single-cycle instructions have no delay slots.
Figure 610. Single-Cycle Execution Block Diagram
Operands (data)
6.2.2
Two-Cycle Instructions and C64x Non-multiply .M Unit Operations

Multiply instructions use both the E1 and E2 phases of the pipeline to complete their operations. Figure 611 shows the pipeline phases two-cycle instructions use.
Figure 611.Instruction Phases

PG PS PW PR DP DC E1 E2 1 delay slot

Functional unit .L, .S, .M, or .D Register file
Write results E1
6-15
Figure 612 shows the operations occurring in the pipeline for a multiply. In the E1 phase, the operands are read and the multiply begins. In the E2 phase, the multiply finishes, and the result is written to the destination register. Multiply instructions have one delay slot. This execution block diagram also applies to the other C64x non-multiply .M unit operations.
Figure 612. Single 16 x 16 Multiply Execution Block Diagram
Operands (data)
6.2.3
Store Instructions
Store instructions require phases E1 through E3 to complete their operations. Figure 613 shows the pipeline phases the store instructions use.
Figure 613. Store Instruction Phases

PG PS PW PR DP DC E1 Address modification E2 E3
Figure 614 shows the operations occurring in the pipeline phases for a store. In the E1 phase, the address of the data to be stored is computed. In the E2 phase, the data and destination addresses are sent to data memory. In the E3 phase, a memory write is performed. The address modification is performed in the E1 stage of the pipeline. Even though stores finish their execution in the E3 phase of the pipeline, they have no delay slots.
6-16

Functional unit .M E1 Register file
Write results E2
Figure 614. Store Execution Block Diagram

Functional unit .D E1 Register file Data E2 Memory controller Address E3 Memory E2
When you perform a load and a store to the same memory location, these rules apply (i = cycle):
- When a load is executed before a store, the old value is loaded and the
new value is stored. i LDW i+1 STW

- When a store is executed before a load, the new value is stored and the
new value is loaded. i STW i+1 LDW

- When the instructions are executed in parallel, the old value is loaded first
and then the new value is stored, but both occur in the same phase. i STW i || LDW There is additional explanation of why stores have zero delay slots in section 6.2.5.
6-17
6.2.4
Extended Multiply Instructions

The extended multiply instructions use phases E1 E4 to complete their operations. Figure 615 shows the pipeline phases used by the extended multiply instructions.
Figure 615. Extended Multiply Instruction Phases

PG PS PW PR DP DC E1 E2 E3 E4
3 delay slots
Figure 616 shows the operations occurring in the pipeline for the multiply extensions. In the E1 phase, the operands are read and the multiplies begin. In the E4 phase, the multiplies finish, and the results are written to the destination register. Extended multiply instructions have three delay slots.
Figure 616. Multiply Extensions Execution Block Diagram
Operands (data)
Functional unit .M Write results
6.2.5
Load Instructions
Data loads require all five of the pipeline execute phases to complete their operations. Figure 617 shows the pipeline phases the load instructions use.
Figure 617. Load Instruction Phases

PG PS PW PR DP DC E1 Address modification E2 E3 E4 E5
6-18

Register file
E4
4 delay slots
Figure 618 shows the operations occurring in the pipeline phases for a load. In the E1 phase, the data address pointer is modified in its register. In the E2 phase, the data address is sent to data memory. In the E3 phase, a memory read at that address is performed.
Figure 618. Load Execution Block Diagram

Functional unit .D E1 E5 Register file Data E4 Memory controller Address E2
E3 Memory
In the E4 stage of a load, the data is received at the CPU core boundary. Finally, in the E5 phase, the data is loaded into a register. Because data is not written to the register until E5, load instructions have four delay slots. Because pointer results are written to the register in E1, there are no delay slots associated with the address modification. In the following code, pointer results are written to the A4 register in the first execute phase of the pipeline and data is written to the A3 register in the fifth execute phase.
LDW .D1 *A4++,A3
Because a store takes three execute phases to write a value to memory and a load takes three execute phases to read from memory, a load following a store accesses the value placed in memory by that store in the cycle after the store is completed. This is why the store is considered to have zero delay slots.
6-19
6.2.6
Branch Instructions
Although branch takes one execute phase, there are five delay slots between the execution of the branch and execution of the target code. Figure 619 shows the pipeline phases used by the branch instruction and branch target code. The delay slots are shaded.
Figure 619. Branch Instruction Phases

PG PS PW PR DP DC E1 PG PS PW PR DP DC E1
Branch target
5 delay slots
Figure 620 shows a branch execution block diagram. If a branch is in the E1 phase of the pipeline (in the .S2 unit in the figure), its branch target is in the fetch packet that is in PG during that same cycle (shaded in the figure). Because the branch target has to wait until it reaches the E1 phase to begin execution, the branch takes five delay slots before the branch target code executes.
Figure 620. Branch Execution Block Diagram

Fetch STH SADD STH LDW Decode 32 STH SADD STH LDW 32 SADD SHR SADD SHR 32 SMPYH SADD SHR SADD SHR 32 SMPY 256 SMPYH SMPYH SMPYH SMPYH 32 SADD SMPY SMPYH SMPY SMPYH 32 SADD SUB LDW SUB MV 32 B B LDW B NOP 32 MVK PG PS PW PR
DP
LDW Execute .L1 MVK .S1 SMPY .M1 .D1
LDW
DC
E1 .D2 SMPYH .M2 B .S2 .L2
6-20
Performance Considerations
6.3 Performance Considerations

The C62x/C64x pipeline is most effective when it is kept as full as the algorithms in the program allow it to be. It is useful to consider some situations that can affect pipeline performance. A fetch packet (FP) is a grouping of eight instructions. Each FP can be split into from one to eight execute packets (EPs). Each EP contains instructions that execute in parallel. Each instruction executes in an independent functional unit. The effect on the pipeline of combinations of EPs that include varying numbers of parallel instructions, or just a single instruction that executes serially with other code, is considered here. In general, the number of execute packets in a single FP defines the flow of instructions through the pipeline. Another defining factor is the instruction types in the EP. Each type of instruction has a fixed number of execute cycles that determines when this instructions operations are complete. Section 6.3.2 covers the effect of including a multicycle NOP in an individual EP. Finally, the effect of the memory system on the operation of the pipeline is considered. The access of program and data memory is discussed, along with memory stalls.
6.3.1
Pipeline Operation With Multiple Execute Packets in a Fetch Packet

Again referring to Figure 66 on page 6-8, pipeline operation is shown with eight instructions in every fetch packet. Figure 621, however, shows the pipeline operation with a fetch packet that contains multiple execute packets. Code for Figure 621 might have this layout:
instruction A ; EP k || instruction B ; instruction C ; EP k + 1 || instruction D || instruction E instruction F ; EP k + 2 || instruction G || instruction H || || || || || || || instruction instruction instruction instruction instruction instruction instruction instruction I ; EP k + 3 J K L M N O P FP n FP n
FP n
FP n + 1
... continuing with EPs k + 4 through k + 8, which have eight instructions in parallel, like k + 3.
6-21
Figure 621. Pipeline Operation: Fetch Packets With Different Numbers of Execute Packets
Clock cycle Fetch packet (FP) n n n n+1 n+2 n+3 n+4 n+5 n+6 Execute packet (EP) k k+1 k+2 k+3 k+4 k+5 k+6 k+7 k+8
1
PG
2
PS
3
PW
4
PR
5
DP
6
DC DP
7
E1 DC DP
8
E2 E1 DC DP PR PW PS PG
9
E3 E2 E1 DC DP PR PW PS PG
10
E4 E3 E2 E1 DC DP PR PW PS
11
E5 E4 E3 E2 E1 DC DP PR PW
12
E5 E4 E3 E2 E1 DC DP PR
13
PG
PS PG
PW PS PG
In Figure 621, fetch packet n, which contains three execute packets, is shown followed by six fetch packets (n + 1 through n + 6), each with one execute packet (containing eight parallel instructions). The first fetch packet (n) goes through the program fetch phases during cycles 14. During these cycles, a program fetch phase is started for each of the fetch packets that follow. In cycle 5, the program dispatch (DP) phase, the CPU scans the p-bits and detects that there are three execute packets (k through k + 2) in fetch packet n. This forces the pipeline to stall, which allows the DP phase to start for execute packets k + 1 and k + 2 in cycles 6 and 7. Once execute packet k + 2 is ready to move on to the DC phase (cycle 8), the pipeline stall is released. The fetch packets n + 1 through n + 4 were all stalled so the CPU could have time to perform the DP phase for each of the three execute packets (k through k + 2) in fetch packet n. Fetch packet n + 5 was also stalled in cycles 6 and 7: it was not allowed to enter the PG phase until after the pipeline stall was released in cycle 8. The pipeline continues operation as shown with fetch packets n + 5 and n + 6 until another fetch packet containing multiple execution packets enters the DP phase, or an interrupt occurs.
6-22

PR PW PS Pipeline stall PG
E5 E4 E3 E2 E1 DC DP
6.3.2
Multicycle NOPs
The NOP instruction has an optional operand, count, that allows you to issue a single instruction for multicycle NOPs. A NOP 2, for example, fills in extra delay slots for the instructions in its execute packet and for all previous execute packets. If a NOP 2 is in parallel with an MPY instruction, the MPYs results will be available for use by instructions in the next execute packet. Figure 622 shows how a multicycle NOP can drive the execution of other instructions in the same execute packet. Figure 622(a) shows a NOP in an execute packet (in parallel) with other code. The results of the LD, ADD, and MPY will all be available during the proper cycle for each instruction. Hence NOP has no effect on the execute packet. Figure 622(b) shows the replacement of the single-cycle NOP with a multicycle NOP (NOP 5) in the same execute packet. The NOP 5 will cause no operation to perform other than the operations from the instructions inside its execute packet. The results of the LD, ADD, and MPY cannot be used by any other instructions until the NOP 5 period has completed.
Figure 622. Multicycle NOP in an Execute Packet

Cycle
(a)
Execute packet
LD
ADD
MPY
NOP
i i+1 i+2 i+3 i+4
Can use ADD results Can use MPY results
Can use LD result
i+5 Cycle
Execute packet
LD
ADD
MPY
NOP 5
i i+1 i+2 i+3 i+4
(b)
All values available on i + 5
i+5
6-23
Figure 623 shows how a multicycle NOP can be affected by a branch. If the delay slots of a branch finish while a multicycle NOP is still dispatching NOPs into the pipeline, the branch overrides the multicycle NOP and the branch target begins execution five delay slots after the branch was issued.
Figure 623. Branching and Multicycle NOPs

Pipeline Phase Cycle # 1 2 3 4 5 6 7 8 9 10 11 Normal EP7 See Figure 622(b) EP1 EP2 EP3 EP4 EP5 EP6 Branch EP7 B Branch Target E1 { { { { { PG PS PW PR DP DC E1
...
EP without branch EP without branch EP without branch
EP without branch LD MPY ADD NOP5
Branch will execute here
Delay slots of the branch
In one case, execute packet 1 (EP1) does not have a branch. The NOP 5 in EP6 will force the CPU to wait until cycle 11 to execute EP7. In the other case, EP1 does have a branch. The delay slots of the branch coincide with cycles 2 through 6. Once the target code reaches E1 in cycle 7, it executes.
6-24
6.3.3
Memory Considerations
The C62x/C64x has a memory configuration typical of a DSP, with program memory in one physical space and data memory in another physical space. Data loads and program fetches have the same operation in the pipeline, they just use different phases to complete their operations. With both data loads and program fetches, memory accesses are broken into multiple phases. This enables the C62x/C64x to access memory at a high speed. These phases are shown in Figure 624.
Figure 624. Pipeline Phases Used During Memory Accesses

Program memory accesses use these pipeline phases PG PS PW PR DP
Data load accesses use these pipeline phases
E1
E2
E3
E4
E5
To understand the memory accesses, compare data loads and instruction fetches/dispatches. The comparison is valid because data loads and program fetches operate on internal memories of the same speed on the C62x/C64x and perform the same types of operations (listed in Table 63) to accommodate those memories. Table 63 shows the operation of program fetches pipeline versus the operation of a data load.
Table 63. Program Memory Accesses Versus Data Load Accesses

Operation Program Memory Access Phase PG PS Data Load Access Phase E1 E2 E3 E4 E5 Compute address Send address to memory Memory read/write PW PR DP Program memory: receive fetch packet at CPU boundary Data load: receive data at CPU boundary Program memory: send instruction to functional units Data load: send data to register
Depending on the type of memory and the time required to complete an access, the pipeline may stall to ensure proper coordination of data and instructions. This is discussed in section 6.3.3.1, Memory Stalls.
6-25
In the instance where multiple accesses are made to a single ported memory, the pipeline will stall to allow the extra access to occur. This is called a memory bank hit and is discussed in section 6.3.3.2, Memory Bank Hits.
6.3.3.1
Memory Stalls
A memory stall occurs when memory is not ready to respond to an access from the CPU. This access occurs during the PW phase for a program memory access and during the E3 phase for a data memory access. The memory stall causes all of the pipeline phases to lengthen beyond a single clock cycle, causing execution to take additional clock cycles to finish. The results of the program execution are identical whether a stall occurs or not. Figure 625 illustrates this point.
Figure 625. Program and Data Memory Stalls

Clock cycle Fetch packet (FP) n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 1 2 3 4 5 6 7 8 9 10
E2 E1
11
E3 E2 E1
12
13
14
15
E4 E3 E2 E1
16
E5 E4 E3 E2 E1
PG
PS
PW PS
PR
DP PR
DC DP PR
E1
PG
PW PS
DC DP
PG
PW PS
Program
DC DP PR
PG
PW PS
PR
memory stall
DC DP PR
Data
PG
PW PS
memory stall
DC DP PR
PG
PW PS
DC DP PR
PG
PW PS
PG
PW PS
PG
PW PS
PG
PG
6-26
6.3.3.2
Memory Bank Hits

Most C62x devices use an interleaved memory bank scheme, as shown in Figure 626. The C6211, C6711, and C64x devices use a two-level cache memory scheme. Thus the example below does not pertain to these devices. Each number in the diagram represents a byte address. A load byte (LDB) instruction from address 0 loads byte 0 in bank 0. A load halfword (LDH) from address 0 loads the halfword value in bytes 0 and 1, which are also in bank 0. An LDW from address 0 loads bytes 0 through 3 in banks 0 and 1.
Figure 626. 4-Bank Interleaved Memory

0 8 1 9 2 10 3 11 4 12 5 13 6 14 7 15
8N
8N + 1
8N + 2 8N + 3 Bank 1
8N + 4 8N + 5 Bank 2
8N + 6 8N + 7 Bank 3
Bank 0
Because each of these banks is single-ported memory, only one access to each bank is allowed per cycle. Two accesses to a single bank in a given cycle result in a memory stall that halts all pipeline operation for one cycle, while the second value is read from memory. Two memory operations per cycle are allowed without any stall, as long as they do not access the same bank. Consider the code in Example 62. Because both loads are trying to access the same bank at the same time, one load must wait. The first LDW accesses bank 0 on cycle i + 2 (in the E3 phase) and the second LDW accesses bank 0 on cycle i + 3 (in the E3 phase). See Table 64 for identification of cycles and phases. The E4 phase for both LDW instructions is in cycle i + 4. To eliminate this extra phase, the loads must access data from different banks (B4 address would need to be in bank 1). For more information on programming topics, see the TMS320C62x/C64x/C67x Programmers Guide.
Example 62. Load From Memory Banks

LDW || LDW .D1 .D2 *A4++,A5 ; load 1, A4 address is in bank 0 *B4++,B5 ; load 2, B4 address is in bank 0
6-27
Table 64. Loads in Pipeline From Example 62

i
LDW .D1 Bank 0 LDW .D2 Bank 0 E1 E1
i+1
E2 E2
i+2
E3 {
i+3
{ E3
i+4
E4 E4
i+5
E5 E5
Stall due to memory bank hit
For devices that have more than one memory space (see Figure 627), an access to bank 0 in one space does not interfere with an access to bank 0 in another memory space, and no pipeline stall occurs.
Figure 627. 4-Bank Interleaved Memory With Two Memory Spaces

Memory space 0 0 8 1 9 2 10 3 11 4 12 5 13 6 14 7 15
8N
8N + 1
8N + 2 8N + 3 Bank 1 8M + 2 8M + 3
8N + 4 8N + 5 Bank 2 8M + 4 8M + 5
8N + 6 8N + 7 Bank 3 8M + 6 8M + 7
Bank 0 Memory space 1 8M 8M + 1
Bank 0
Bank 1
Bank 2
Bank 3
The internal memory of the C62x/C64x family varies from device to device. See the TMS320C6000 Peripherals Reference Guide to determine the memory spaces in your particular device.
6-28
Chapter 7
TMS320C67x Pipeline
The TMS320C67x DSP pipeline provides flexibility to simplify programming and improve performance. Two factors provide this flexibility:
- Control of the pipeline is simplified by eliminating pipeline interlocks. - Increased pipelining eliminates traditional architectural bottlenecks in pro-
gram fetch, data access, and multiply operations. This provides singlecycle throughput. This chapter starts with a description of the pipeline flow. Highlights are:
- The pipeline can dispatch eight parallel instructions every cycle. - Parallel instructions proceed simultaneously through each pipeline
phase.
- Serial instructions proceed through the pipeline with a fixed relative phase
difference between instructions.

- Load and store addresses appear on the CPU boundary during the same
pipeline phase, eliminating read-after-write memory conflicts. All instructions require the same number of pipeline phases for fetch and decode, but require a varying number of execute phases. This chapter contains a description of the number of execution phases for each type of instruction. The TMS320C67x generally has more execution phases than the TMS320C62x DSP because it processes floating-point instructions. Finally, the chapter contains performance considerations for the pipeline. These considerations include the occurrence of fetch packets that contain multiple execute packets, execute packets that contain multicycle NOPs, and memory considerations for the pipeline. For more information about fully optimizing a program and taking full advantage of the pipeline, see the TMS320C6000 Programmers Guide (SPRU198).
Topic
7.1 7.2 7.3 7.4
Page
Pipeline Operation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Pipeline Execution of Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . 7-13 Functional Unit Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 Performance Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-52
August 1996
7-1
7.1 Pipeline Operation Overview

The pipeline phases are divided into three stages:
- Fetch - Decode - Execute
All instructions in the C67x instruction set flow through the fetch, decode, and execute stages of the pipeline. The fetch stage of the pipeline has four phases for all instructions, and the decode stage has two phases for all instructions. The execute stage of the pipeline requires a varying number of phases, depending on the type of instruction. The stages of the C67x pipeline are shown in Figure 71.
Figure 71. Floating-Point Pipeline Stages

Fetch Decode Execute
7.1.1
Fetch
The fetch phases of the pipeline are:
-
PG: Program address generate PS: Program address send PW: Program access ready wait PR: Program fetch packet receive
The C67x uses a fetch packet (FP) of eight instructions. All eight of the instructions proceed through fetch processing together, through the PG, PS, PW, and PR phases. Figure 72(a) shows the fetch phases in sequential order from left to right. Figure 72(b) shows a functional diagram of the flow of instructions through the fetch phases. During the PG phase, the program address is generated in the CPU. In the PS phase, the program address is sent to memory. In the PW phase, a memory read occurs. Finally, in the PR phase, the fetch packet is received at the CPU. Figure 72(c) shows fetch packets flowing through the phases of the fetch stage of the pipeline. In Figure 72(c), the first fetch packet (in PR) is made up of four execute packets, and the second and third fetch packets (in PW and PS) contain two execute packets each. The last fetch packet (in PG) contains a single execute packet of eight single-cycle instructions.
7-2
Figure 72. Fetch Phases of the Pipeline

CPU
(a) (b)
PG PS PW PR
Functional units
Registers PR PG PS Memory
PW
(c)
Fetch LDW LDW LDW LDW LDW LDW LDW LDW SHR SMPYH MVKLH MVK SHR SMPY MV ADD
256 SMPYH SADD SMPYH SHL SMPYH SADD SMPY LDW MV B B LDW NOP MVK MVK MVK PG PS PW PR
Decode
TMS320C67x Pipeline
7-3
7.1.2
Decode
The decode phases of the pipeline are:
- DP: Instruction dispatch - DC: Instruction decode
In the DP phase of the pipeline, the fetch packets are split into execute packets. Execute packets consist of one instruction or from two to eight parallel instructions. During the DP phase, the instructions in an execute packet are assigned to the appropriate functional units. In the DC phase, the the source registers, destination registers, and associated paths are decoded for the execution of the instructions in the functional units. Figure 73(a) shows the decode phases in sequential order from left to right. Figure 73(b) shows a fetch packet that contains two execute packets as they are processed through the decode stage of the pipeline. The last six instructions of the fetch packet (FP) are parallel and form an execute packet (EP). This EP is in the dispatch phase (DP) of the decode stage. The arrows indicate each instructions assigned functional unit for execution during the same cycle. The NOP instruction in the eighth slot of the FP is not dispatched to a functional unit because there is no execution associated with it. The first two slots of the fetch packet (shaded below) represent an execute packet of two parallel instructions that were dispatched on the previous cycle. This execute packet contains two MPY instructions that are now in decode (DC) one cycle before execution. There are no instructions decoded for the .L, .S, and .D functional units for the situation illustrated.
Figure 73. Decode Phases of the Pipeline

(a)
DP
(b)
DC
Decode
32
32
32 ADD
32 ADD
32 STW
32 STW
32 ADDK
32 NOP
DP
MPYH
DC
MPYH
.L1
.S1
.M1
.D1
Functional units
.D2
.M2
.S2
.L2
NOP is not dispatched to a functional unit.
7-4
7.1.3
Execute
The execute portion of the floating-point pipeline is subdivided into ten phases (E1E10), as compared to the fixed-point pipelines five phases. Different types of instructions require different numbers of these phases to complete their execution. These phases of the pipeline play an important role in your understanding the device state at CPU cycle boundaries. The execution of different types of instructions in the pipeline is described in section 7.2, Pipeline Execution of Instruction Types. Figure 74(a) shows the execute phases of the pipeline in sequential order from left to right. Figure 74(b) shows the portion of the functional block diagram in which execution occurs.
Figure 74. Execute Phases of the Pipeline and Functional Block Diagram of the TMS320C67x
(a)
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
(b)
Execute SADD .L1 B .S1 SMPY .M1 STH .D1 E1 STH .D2 SMPYH .M2 SUB .S2 SADD .L2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register file A Data 1 32
32
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register file B 32 Data 2
TMS320C67x Pipeline
7-5
7.1.4
Summary of Pipeline Operation

Figure 75 shows all the phases in each stage of the C67x pipeline in sequential order, from left to right.
Figure 75. Floating-Point Pipeline Phases

Fetch PG PS PW PR Decode DP DC E1 E2 E3 E4 Execute E5 E6 E7 E8 E9 E10
Figure 76 shows an example of the pipeline flow of consecutive fetch packets that contain eight parallel instructions. In this case, where the pipeline is full, all instructions in a fetch packet are in parallel and split into one execute packet per fetch packet. The fetch packets flow in lockstep fashion through each phase of the pipeline. For example, examine cycle 7 in Figure 76. When the instructions from FP n reach E1, the instructions in the execute packet from FPn +1 are being decoded. FP n + 2 is in dispatch while FPs n + 3, n + 4, n + 5, and n + 6 are each in one of four phases of program fetch. See section 7.4, Performance Considerations, on page 7-52 for additional detail on code flowing through the pipeline.
Figure 76. Pipeline Operation: One Execute Packet per Fetch Packet

Clock cycle 8 9 Fetch packet n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 1 2 3 4 5 6 7 10
E4 E3 E2 E1
11
E5 E4 E3 E2 E1
12
E6 E5 E4 E3 E2 E1
13
E7 E6 E5 E4 E3 E2 E1
14
E8 E7 E6 E5 E4 E3 E2 E1
15
E9 E8 E7 E6 E5 E4 E3 E2 E1
16
E9 E8 E7 E6 E5 E4 E3 E2 E1
17
PG
PS
PW PS
PR
DP PR
DC DP PR
E1
E2 E1
E3 E2 E1
E10
PG
PW PS
DC DP
E10 E9 E8 E7 E6 E5 E4 E3 E2 E1
PG
PW PS
DC DP PR
PG
PW PS
PR
DC DP PR
PG
PW PS
DC DP PR
PG
PW PS
DC DP PR
PG
PW PS
DC DP PR
PG
PW PS
DC DP PR
PG
PW PS
DC DP PR
PG
PW PS
DC DP
PG
PW
DC
7-6
Table 71 summarizes the pipeline phases and what happens in each.

Table 71. Operations Occurring During Floating-Point Pipeline Phases
Stage Phase Symbol PG During This Phase Instruction Type Completed Program fetch Program address generation Program address sent Program wait The address of the fetch packet is determined. PS The address of the fetch packet is sent to the memory. A program memory access is performed. PW PR DP Program data receive Dispatch Decode Execute Execute 1 The fetch packet is at the CPU boundary. Program decode The next execute packet of the fetch packet is determined and sent to the appropriate functional unit to be decoded. Instructions are decoded in functional units. For all instruction types, the conditions for the instructions are evaluated and operands are read. For load and store instructions, address generation is performed and address modifications are written to the register file. For branch instructions, branch fetch packet in PG phase is affected. For single-cycle instructions, results are written to a register file. For DP compare, ADDDP/SUBDP, and MPYDP instructions, the lower 32-bits of the sources are read. For all other instructions, the sources are read. For 2-cycle DP instructions, the lower 32 bits of the result are written to a register file. Single-cycle DC E1

This assumes that the conditions for the instructions are evaluated as true. If the condition is evaluated as false, the instruction does not write an y results or have any pipeline operation after E1.
TMS320C67x Pipeline
7-7

Table 71. Operations Occurring During Floating-Point Pipeline Phases (Continued)
Stage Phase Symbol E2 During This Phase Instruction Type Completed Execute 2 For load instructions, the address is sent to memory. For store instructions, the address and data are sent to memory. Single-cycle instructions that saturate results set the SAT bit in the SCR if saturation occurs. For multiply, 2-cycle DP, and DP compare instructions, results are written to a register file. For DP compare and ADDDP/SUBDP instructions, the upper 32 bits of the source are read. For the MPYDP instruction, the lower 32 bits of src1 and the upper 32 bits of src2 are read. For MPYI and MPYID instructions, the sources are read. Execute 3 E3 Data memory accesses are performed. Any multiply instruction that saturates results sets the SAT bit in the CSR if saturation occurs. For MPYDP instruction, the upper 32 bits of src1 and the lower 32 bits of src2 are read. For MPYI and MPYID instructions, the sources are read. Execute 4 E4 For load instructions, data is brought to the CPU boundary For the MPYI and MPYID instructions, the sources are read. For the MPYDP instruction, the upper 32 bits of the sources are read. For MPYI and MPYID instructions, the sources are read. For 4-cycle instructions, results are written to a register file. For INTDP instruction, the lower 32 bits of the result are written to a register file. Execute 5 E5 For load instructions, data is written into a register file. For the INTDP instruction, the upper 32 bits of the result are written to a register file. Load INTDP 4-cycle Store Multiply 2-cycle DP DP compare

7-8

Table 71. Operations Occurring During Floating-Point Pipeline Phases (Continued)
Stage Phase Symbol E6 During This Phase Instruction Type Completed Execute 6 For ADDDP/SUBDP instructions, the lower 32 bits of the result are written to a register file. Execute 7 Execute 8 Execute 9 E7 E8 E9 For ADDDP/SUBDP instructions, the upper 32 bits of the result are written to a register file. Nothing is read or written. For the MPYI instruction, the result is written to a register file. For MPYDP and MPYID instructions, the lower 32 bits of the result are written to a register file. Execute 10 E10 For MPYDP and MPYID instructions, the upper 32 bits of the result are written to a register file. MPYDP MPYID MPYI ADDDP/ SUBDP

TMS320C67x Pipeline
7-9
Figure 77 shows a C67x functional block diagram laid out vertically by stages of the pipeline.

Fetch LDDW LDDW LDDW LDDW Decode 32 LDDW SUB ZERO MV SUB 32 ZERO ADDSP SUBSP ADDSP ADDSP 32 SUBSP SUBSP ADDSP ADDSP SUBSP 32 ADDSP 256 MPYSP MPYSP MPYSP MPYSP 32 MPYSP MPYSP MVK ABSSP B PG PS
MPYSP CMPLTSP MPYSP MPYSP
ABSSP CMPLTSP PW MVK ABSSP 32 B PR
32 32 MPYSP CMPLTSP
DP
ADDSP CMPLTSP Execute ADDSP .L1
MPYSP
LDDW
MPYSP
ABSSP
ADDSP DC
ABSSP .S1
MPYSP .M1
LDDW .D1
.D2
MPYSP .M2
.S2
SUBSP E1 .L2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register file A Data 1 32
32
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register file B 32 Data 2
7-10
The pipeline operation is based on CPU cycles. A CPU cycle is the period during which a particular execute packet is in a particular pipeline phase. CPU cycle boundaries always occur at clock cycle boundaries. As code flows through the pipeline phases, it is processed by different parts of the C67x. Figure 77 shows a full pipeline with a fetch packet in every phase of fetch. One execute packet of eight instructions is being dispatched at the same time that a 7-instruction execute packet is in decode. The arrows between DP and DC correspond to the functional units identified in the code in Example 71. In the DC phase portion of Figure 77, one box is empty because a NOP was the eighth instruction in the fetch packet in DC, and no functional unit is needed for a NOP. Finally, the figure shows six functional units processing code during the same cycle of the pipeline. Registers used by the instructions in E1 are shaded in Figure 77. The multiplexers used for the input operands to the functional units are also shaded in the figure. The bold crosspaths are used by the MPY and SUBSP instructions. Many C67x instructions are single-cycle instructions, which means they have only one execution phase (E1). The other instructions require more than one execute phase. The types of instructions, each of which require different numbers of execute phases, are described in section 7.2, Pipeline Execution of Instruction Types.
TMS320C67x Pipeline
7-11
Example 71. Execute Packet in Figure 77

|| || || || || LDDW ADDSP SUBSP MPYSP MPYSP ABSSP LDDW ADDSP ADDSP MPYSP MPYSP CMPLTSP ABSSP .D1 .L1 .L2X .M1X .M2 .S1 .D1 .L1 .L2 .M1X .M2X .S1 .S2 *A0[4],B5:B4 A9,A10,A12 B12,A2,B12 A6,B13,A11 B5,B13,B11 A12,A15 *A0++[5],A7:A6 A12,A11,A12 B10,B11,B12 A4,B6,A9 A7,B6,B9 A15,A8,A1 B12,B15 ; E1 Phase
; DC Phase
|| || || || || || LOOP: [!B2] ||[B2] || || || || ||[B0] ||[!B1] [!B2] ||[B0] || || || || || ||[A1] [!B2] ||[B1] || || || ||[!A1] ||
LDDW ZERO SUBSP ADDSP MPYSP MPYSP B CMPLTSP LDDW SUB ADDSP SUBSP MPYSP MPYSP ABSSP MVK LDDW MV ADDSP ADDSP MPYSP CMPLTSP ABSSP
.D1 .D2 .L1 .L2 .M1X .M2 .S1 .S2 .D1 .D2 .L1 .L2X .M1X .M2 .S1 .S2 .D1 .D2 .L1 .L2 .M1X .S1 .S2
*A0++[2],A5:A4 B0 A12,A2,A12 B9,B12,B12 A5,B7,A10 B4,B7,B10 LOOP B15,B8,B1 *A0[4],B5:B4 B0,2,B0 A9,A10,A12 B12,A2,B12 A6,B13,A11 B5,B13,B11 A12,A15 1,B2 *A0++[5],A7:A6 B1,B2 A12,A11,A12 B10,B11,B12 A4,B6,A9 A15,A8,A1 B12,B15
; DP and PS Phases
; PR and PG Phases
; PW Phase
7-12
7.2 Pipeline Execution of Instruction Types

The pipeline operation of the C67x instructions can be categorized into fourteen instruction types. Thirteen of these are shown in Table 72 (NOP is not included in the table), which is a mapping of operations occurring in each execution phase for the different instruction types. The delay slots and functional unit latency associated with each instruction type are listed in the bottom row.

Table 72. Execution Stage Length Description for Each Instruction Type
Instruction Type Store Single Cycle 16 16 Multiply Read operands and start computations Load Branch Execution phases E1 Compute result and write to register Compute address Compute address Target code in PG E2 Compute result and write to register Send address and data to memory Send address to memory Access memory Send data back to CPU Write data into register E3 E4 E5 E6 E7 E8 E9 Access memory E10 Delay slots 0 1 1 1 0 1 4 1 5 1 Functional unit latency
See sections 7.3.7 (page 7-40) and 7.3.8 (page 7-42) for more information on execution and delay slots for stores and loads. See section 7.3.9 (page 7-44) for more information on branches. Notes: 1) This table assumes that the condition for each instruction is evaluated as true. If the condition is evaluated as false, the instruction does not write any results or have any pipeline operation after E1. 2) NOP is not shown and has no operation in any of the execution phases.
TMS320C67x Pipeline
7-13
Table 72. Execution Stage Length Description for Each Instruction Type (Continued)

Instruction Type INTDP 2-Cycle DP 4-Cycle DP Compare Execution phases E1 Compute the lower results and write to register Read sources and start computation Read sources and start computation Read lower sources and start computation E2 Compute the upper results and write to register Continue computation Continue computation Read upper sources, finish computation, and write results to register E3 E4 Continue computation Continue computation Complete computa- Continue computation and write results tion and write lower to register results to register E5 Complete computation and write upper results to register E6 E7 E8 E9 E10 Delay slots 1 1 3 1 4 1 1 2 Functional unit latency
Notes: 1) This table assumes that the condition for each instruction is evaluated as true. If the condition is evaluated as false, the instruction does not write any results or have any pipeline operation after E1. 2) NOP is not shown and has no operation in any of the execution phases.
7-14
Table 72. Execution Stage Length Description for Each Instruction Type (Continued)

Instruction Type MPYID ADDDP/SUBDP MPYI MPYDP Execution phases E1 Read lower sources and start computation Read sources and start computation Read sources and start computation Read lower sources and start computation E2 Read upper sources and continue computation Continue computation Continue computation Continue computation Compute the lower results and write to register Read sources and continue computation Read sources and continue computation Read sources and continue computation Read sources and continue computation Read sources and continue computation Read sources and continue computation Read lower src1 and upper src2 and continue computation Read lower src2 and upper src1 and continue computation Read upper sources and continue computation Continue computation Continue computation Continue computation Continue computation E3 E4 E5 E6 Continue computation Continue computation Continue computation Continue computation Continue computation Continue computation Continue computation Continue computation E7 Compute the upper results and write to register

E8 E9 Complete computa- Continue computation and write results tion and write lower to register results to register Continue computation and write lower results to register E10 Complete computation and write upper results to register 9 4 Complete computation and write upper results to register 9 4 Delay slots 6 2 8 4 Functional unit latency
Notes: 1) This table assumes that the condition for each instruction is evaluated as true. If the condition is evaluated as false, the instruction does not write any results or have any pipeline operation after E1. 2) NOP is not shown and has no operation in any of the execution phases.
TMS320C67x Pipeline
7-15
The execution of instructions can be defined in terms of delay slots. A delay slot is a CPU cycle that occurs after the first execution phase (E1) of an instruction. Results from instructions with delay slots are not available until the end of the last delay slot. For example, a multiply instruction has one delay slot, which means that one CPU cycle elapses before the results of the multiply are available for use by a subsequent instruction. However, results are available from other instructions finishing execution during the same CPU cycle in which the multiply is in a delay slot. If an instruction has a multicycle functional unit latency, it locks the functional unit for the necessary number of cycles. Any new instruction dispatched to that functional unit during this locking period causes undefined results. If an instruction with a multicycle functional unit latency has a condition that is evaluated as false during E1, it still locks the functional unit for subsequent cycles. An instruction of the following types scheduled on cycle i has the following constraints: DP compare ADDDP/SUBDP MPYI MPYID MPYDP No other instruction can use the functional unit on cycles i and i + 1. No other instruction can use the functional unit on cycles i and i + 1. No other instruction can use the functional unit on cycles i, i + 1, i + 2, and i + 3. No other instruction can use the functional unit on cycles i, i + 1, i + 2, and i + 3. No other instruction can use the functional unit on cycles i, i + 1, i + 2, and i + 3.
If a cross path is used to read a source using an instruction with multicycle functional unit latency, ensure that no other instructions executing on the same side use the cross path.
7-16
An instruction of the following types scheduled on cycle i, using a cross path to read a source, has the following constraints: DP compare ADDDP/SUBDP MPYI MPYID MPYDP No other instruction on the same side can use the cross path on cycles i and i + 1. No other instruction on the same side can use the cross path on cycles i and i + 1. No other instruction on the same side can use the cross path on cycles i, i + 1, i + 2, and i + 3. No other instruction on the same side can use the cross path on cycles i, i + 1, i + 2, and i + 3. No other instruction on the same side can use the cross path on cycles i, i + 1, i + 2, and i + 3.
Other constraints exist because instructions have varying numbers of delay slots, and the instructions need the functional unit read and write ports for varying numbers of cycles. A read or write constraint occurs when two instructions on the same functional unit attempt to read or write, respectively, to the register file on the came cycle. An instruction scheduled on cycle i has the following constraints: 2-cycle DP A single-cycle instruction cannot be scheduled on the same functional unit on cycle i + 1 due to a write constraint on cycle i + 1. Another 2-cycle DP instruction cannot be scheduled on the same functional unit on cycle i + 1 due to a write constraint on cycle i + 1. A single-cycle instruction cannot be scheduled on the same functional unit on cycle i + 3 due to a write constraint on cycle i + 3. A multiply (16 16-bit) instruction cannot be scheduled on the same functional unit on cycle i + 2 due to a write constraint on cycle i + 3. INTDP A single-cycle instruction cannot be scheduled on the same functional unit on cycle i + 3 or i + 4 due to a write constraint on cycle i + 3 or i + 4, respectively. An INTDP instruction cannot be scheduled on the same functional unit on cycle i + 1 due to a write constraint on cycle i + 1. A 4-cycle instruction cannot be scheduled on the same functional unit on cycle i + 1 due to a write constraint on cycle i + 1.
4-cycle
TMS320C67x Pipeline
7-17
MPYI
A 4-cycle instruction cannot be scheduled on the same functional unit on cycle i + 4, i + 5, or i + 6. A MPYDP instruction cannot be scheduled on the same functional unit on cycle i + 4, i + 5, or i + 6. A multiply (16 16-bit) instruction cannot be scheduled on the same functional unit on cycle i + 6 due to a write constraint on cycle i + 7.
MPYID
A 4-cycle instruction cannot be scheduled on the same functional unit on cycle i + 4, i + 5, or i + 6. A MPYDP instruction cannot be scheduled on the same functional unit on cycle i + 4, i + 5, or i + 6. A multiply (16 16-bit) instruction cannot be scheduled on the same functional unit on cycle i + 7 or i + 8 due to a write constraint on cycle i + 8 or i + 9, respectively.
MPYDP
A 4-cycle instruction cannot be scheduled on the same functional unit on cycle i + 4, i + 5, or i + 6. A MPYI instruction cannot be scheduled on the same functional unit on cycle i + 4, i + 5, or i + 6. A MPYID instruction cannot be scheduled on the same functional unit on cycle i + 4, i + 5, or i + 6. A multiply (16 16-bit) instruction cannot be scheduled on the same functional unit on cycle i + 7 or i + 8 due to a write constraint on cycle i + 8 or i + 9, respectively.
ADDDP/SUBDP
A single-cycle instruction cannot be scheduled on the same functional unit on cycle i + 5 or i + 6 due to a write constraint on cycle i + 5 or i + 6, respectively. A 4-cycle instruction cannot be scheduled on the same functional unit on cycle i + 2 or i + 3 due to a write constraint on cycle i + 5 or i + 6, respectively. An INTDP instruction cannot be scheduled on the same functional unit on cycle i + 2 or i + 3 due to a write constraint on cycle i + 5 or i + 6, respectively.
The 4-cycle case is important for the following single-precision floating-point instructions:
7-18
ADDSP SUBSP SPINT SPTRUNC INTSP MPYSP
All of the preceding cases deal with double-precision floating-point instructions or the MPYI or MPYID instructions except for the 4-cycle case. A 4-cycle instruction consists of both single- and double-precision floating-point instructions. Therefore, the 4-cycle case is important for the following single-precision floating-point instructions: The .S and .L units share their long write port with the load port for the 32 most significant bits of an LDDW load. Therefore, the LDDW instruction and the .S or .L unit writing a long result cannot write to the same register file on the same cycle. The LDDW writes to the register file on pipeline phase E5. Instructions that use a long result and use the .L and .S unit write to the register file on pipeline phase E1. Therefore, the instruction with the long result must be scheduled later than four cycles following the LDDW instruction if both instructions use the same side.
TMS320C67x Pipeline
7-19
Functional Unit Constraints
7.3 Functional Unit Constraints

If you wish to optimize your instruction pipeline, consider the instructions that are executed on each unit. Sources and destinations are read and written differently for each instruction. If you analyze these differences, you can make further optimization improvements by considering what happens during the execution phases of instructions that use the same functional unit in each execution packet. The following sections provide information about what happens during each execute phase of the instructions within a category for each of the functional units.
7-20
7.3.1
.S-Unit Constraints
Table 73 shows the instruction constraints for single-cycle instructions executing on the .S unit.
Table 73. Single-Cycle .S-Unit Instruction Constraints

Instruction Execution Cycle Single-cycle Instruction Type Single-cycle DP compare 2-cycle DP Branch Instruction Type Single-cycle Load Store INTDP ADDDP/SUBDP 16 16 multiply 4-cycle MPYI MPYID MPYDP
Legend: R W
1 RW
Subsequent Same-Unit Instruction Executable n n n n Same Side, Different Unit, Both Using Cross Path Executable n n n n n n n n n n
E1 phase of the single-cyle instruction Sources read for the instruction Destinations written for the instruction Next instruction can enter E1 during cycle
TMS320C67x Pipeline
7-21
Table 74 shows the instruction constraints for DP compare instructions executing on the .S unit.
Table 74. DP Compare .S-Unit Instruction Constraints

Instruction Execution Cycle DP compare 1 R 2 RW 3
Instruction Type Single-cycle DP compare 2-cycle DP Branch Instruction Type Single-cycle Load Store INTDP ADDDP/SUBDP 16 16 multiply 4-cycle MPYI MPYID MPYDP
Legend: R W
Subsequent Same-Unit Instruction Executable Xrw Xr Xrw Xr n n n n n n n n n n n n n n
Same Side, Different Unit, Both Using Cross Path Executable Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr
n
Xr Xrw
E1 phase of the single-cyle instruction Sources read for the instruction Destinations written for the instruction Next instruction can enter E1 during cycle Next instruction cannot enter E1 during cycleread/decode constraint Next instruction cannot enter E1 during cycleread/decode/write constraint The branch on register instruction is the only branch instruction that reads a general-purpose register
7-22
Table 75 shows the instruction constraints for 2-cycle DP instructions executing on the .S unit.
Table 75. 2-Cycle DP .S-Unit Instruction Constraints

Instruction Execution Cycle 2-cycle Instruction Type Single-cycle DP compare 2-cycle DP Branch Instruction Type Single cycle Load Store INTDP ADDDP/SUBDP 16 16 multiply 4-cycle MPYI MPYID MPYDP
Legend: R W
1 RW
2 W
Subsequent Same-Unit Instruction Executable Xw n Xw n n n n n n n n n n n n n n n n n n n n n n n n n
Same Side, Different Unit, Both Using Cross Path Executable
n
Xw
E1 phase of the single-cyle instruction Sources read for the instruction Destinations written for the instruction Next instruction can enter E1 during cycle Next instruction cannot enter E1 during cyclewrite constraint
TMS320C67x Pipeline
7-23
Table 76 shows the instruction constraints for branch instructions executing on the .S unit.
Table 76. Branch .S-Unit Instruction Constraints

Instruction Execution Cycle Branch Instruction Type Single-cycle DP compare 2-cycle DP Branch Instruction Type Single-cycle Load Store INTDP ADDDP/SUBDP 16 16 multiply 4-cycle MPYI MPYID MPYDP
Legend: R
1 R
Subsequent Same-Unit Instruction Executable n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
E1 phase of the single-cyle instruction Sources read for the instruction Next instruction can enter E1 during cycle The branch on register instruction is the only branch instruction that reads a general-purpose register
7-24
7.3.2
.M-Unit Constraints
Table 77 shows the instruction constraints for 16 X 16 multiply instructions executing on the .M unit.
Table 77. 16 X 16 Multiply .M-Unit Instruction Constraints

Instruction Execution Cycle 16 X 16 multiply Instruction Type 16 X 16 multiply 4-cycle MPYI MPYID MPYDP Instruction Type Single-cycle Load Store DP compare 2-cycle DP Branch 4-cycle INTDP ADDDP/SUBDP
Legend: R W
1 R
2 W
Subsequent Same-Unit Instruction Executable n n n n n n n n n n n n n n n n n n n n n n n n n n n n
TMS320C67x Pipeline
7-25
Table 78 shows the instruction constraints for 4-cycle instructions executing on the .M unit.
Table 78. 4-Cycle .M-Unit Instruction Constraints

Instruction Execution Cycle 4-cycle Instruction Type 16 16 multiply 4-cycle MPYI MPYID MPYDP Instruction Type Single-cycle Load Store DP compare 2-cycle DP Branch 4-cycle INTDP ADDDP/SUBDP
Legend: R W
1 R
4 W
Subsequent Same-Unit Instruction Executable n n n n n n n n n n n n n n Xw n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
n
Xw
7-26
Table 79 shows the instruction constraints for MPYI instructions executing on the .M unit.
Table 79. MPYI .M-Unit Instruction Constraints

Instruction Execution Cycle MPYI Instruction Type 16 16 multiply 4-cycle MPYI MPYID MPYDP Instruction Type Single-cycle Load Store DP compare 2-cycle DP Branch 4-cycle INTDP ADDDP/SUBDP
Legend: R W
1 R
2 R
3 R
4 R
9 W
10
Subsequent Same-Unit Instruction Executable Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr n Xu n n Xu n n n n n n n n n n Xw n n Xu n n n n n n n n n n Xu n n Xu n n n n n n n n n Xw n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
Same Side, Different Unit, Both Using Cross Path Executable Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr
n
Xr Xw Xu
E1 phase of the single-cyle instruction Sources read for the instruction Destinations written for the instruction Next instruction can enter E1 during cycle Next instruction cannot enter E1 during cycleread/decode constraint Next instruction cannot enter E1 during cyclewrite constraint Next instruction cannot enter E1 during cycleother resource conflict
TMS320C67x Pipeline
7-27
Table 710 shows the instruction constraints for MPYID instructions executing on the .M unit.
Table 710. MPYID .M-Unit Instruction Constraints

Instruction Execution Cycle MPYID Instruction Type 16 16 multiply 4-cycle MPYI MPYID MPYDP Instruction Type Single-cycle Load Store DP compare 2-cycle DP Branch 4-cycle INTDP ADDDP/SUBDP
Legend: R W
1 R
2 R
3 R
4 R
9 W
10 W n n n n n n n n n n n n n n
11
Subsequent Same-Unit Instruction Executable Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr n Xu n n Xu n n n n n n n n n n Xw n n Xu n n n n n n n n n n Xw n n Xu n n n n n n n n n Xw n n n n n n n n n n n n n Xw n n n n n n n n n n n n n n n n n n n n n n n n n n n
n
Xr Xw Xu
7-28
Table 711 shows the instruction constraints for MPYDP instructions executing on the .M unit.
Table 711. MPYDP .M-Unit Instruction Constraints

Instruction Execution Cycle MPYDP Instruction Type 16 16 multiply 4-cycle MPYI MPYID MPYDP Instruction Type Single-cycle Load Store DP compare 2-cycle DP Branch 4-cycle INTDP ADDDP/SUBDP
Legend: R W
1 R
2 R
3 R
4 R
9 W
10 W n n n n n n n n n n n n n n
11
Subsequent Same-Unit Instruction Executable Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr n Xu Xu Xu n n n n n n n n n n n Xw Xu Xu n n n n n n n n n n n Xw Xu Xu n n n n n n n n n n Xw n n n n n n n n n n n n n Xw n n n n n n n n n n n n n n n n n n n n n n n n n n n
n
Xr Xw Xu
TMS320C67x Pipeline
7-29
7.3.3
.L-Unit Constraints
Table 712 shows the instruction constraints for single-cycle instructions executing on the .L unit.
Table 712. Single-Cycle .L-Unit Instruction Constraints

Instruction Execution Cycle Single-cycle Instruction Type Single-cycle 4-cycle INTDP ADDDP/SUBDP Instruction Type Single-cycle DP compare 2-cycle DP 4-cycle Load Store Branch 16 16 multiply MPYI MPYID MPYDP
Legend: R W
1 RW
Subsequent Same-Unit Instruction Executable n n n n Same Side, Different Unit, Both Using Cross Path Executable n n n n n n n n n n n
7-30
Table 713 shows the instruction constraints for 4-cycle instructions executing on the .L unit.
Table 713. 4-Cycle .L-Unit Instruction Constraints

Instruction Execution Cycle 4-cycle Instruction Type Single-cycle 4-cycle INTDP ADDDP/SUBDP Instruction Type Single-cycle DP compare 2-cycle DP 4-cycle Load Store Branch 16 16 multiply MPYI MPYID MPYDP
Legend: R W
1 R
4 W
Subsequent Same-Unit Instruction Executable n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n Xw n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
n
Xw
TMS320C67x Pipeline
7-31
Table 714 shows the instruction constraints for INTDP instructions executing on the .L unit.
Table 714. INTDP .L-Unit Instruction Constraints

Instruction Execution Cycle INTDP Instruction Type Single-cycle 4-cycle INTDP ADDDP/SUBDP Instruction Type Single-cycle DP compare 2-cycle DP 4-cycle Load Store Branch 16 16 multiply MPYI MPYID MPYDP
Legend: R W
1 R
4 W
5 W
Subsequent Same-Unit Instruction Executable n Xw Xw n n n n n n n n n n n n n n n n n n n n n n n n n n n Xw n n n n n n n n n n n n n n Xw n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
n
Xw
7-32
Table 715 shows the instruction constraints for ADDDP/SUBDP instructions executing on the .L unit.
Table 715. ADDDP/SUBDP .L-Unit Instruction Constraints

Instruction Execution Cycle ADDDP/SUBDP Instruction Type Single-cycle 4-cycle INTDP ADDDP/SUBDP Instruction Type Single-cycle DP compare 2-cycle DP 4-cycle Load Store Branch 16 16 multiply MPYI MPYID MPYDP
Legend: R W
1 R
2 R
6 W
7 W
Subsequent Same-Unit Instruction Executable Xr Xr Xrw Xr n Xw Xw n n n n n n n n n n n n n Xw Xw n n n n n n n n n n n n n n n n n n n n n n n n n n n Xw n n n n n n n n n n n n n n Xw n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
Same Side, Different Unit, Both Using Cross Path Executable Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr Xr
n
Xr Xw Xrw
E1 phase of the single-cyle instruction Sources read for the instruction Destinations written for the instruction Next instruction can enter E1 during cycle Next instruction cannot enter E1 during cycleread/decode constraint Next instruction cannot enter E1 during cyclewrite constraint Next instruction cannot enter E1 during cycleread/decode/write constraint
TMS320C67x Pipeline
7-33
7.3.4
D-Unit Instruction Constraints

Table 716 shows the instruction constraints for load instructions executing on the .D unit.
Table 716. Load .D-Unit Instruction Constraints

Instruction Execution Cycle Load Instruction Type Single-cycle Load Store Instruction Type 16 16 multiply MPYI MPYID MPYDP Single-cycle DP compare 2-cycle DP Branch 4-cycle INTDP ADDDP/SUBDP
Legend: R W
1 RW
5 W
Subsequent Same-Unit Instruction Executable n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
7-34
Table 717 shows the instruction constraints for store instructions executing on the .D unit.
Table 717. Store .D-Unit Instruction Constraints

Instruction Execution Cycle Store Instruction Type Single-cycle Load Store Instruction Type 16 16 multiply MPYI MPYID MPYDP Single-cycle DP compare 2-cycle DP Branch 4-cycle INTDP ADDDP/SUBDP
Legend: R W
1 RW
Subsequent Same-Unit Instruction Executable n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
TMS320C67x Pipeline
7-35
Table 718 shows the instruction constraints for single-cycle instructions executing on the .D unit.
Table 718. Single-Cycle .D-Unit Instruction Constraints

Instruction Execution Cycle Single-cycle Instruction Type Single-cycle Load Store Instruction Type 16 16 multiply MPYI MPYID MPYDP Single-cycle DP compare 2-cycle DP Branch 4-cycle INTDP ADDDP/SUBDP
Legend: R W
1 RW
Subsequent Same-Unit Instruction Executable n n n Same Side, Different Unit, Both Using Cross Path Executable n n n n n n n n n n n
7-36
Table 719 shows the instruction constraints for LDDW instructions executing on the .D unit.
Table 719. LDDW Instruction With Long Write Instruction Constraints

Instruction Execution Cycle LDDW Instruction Type Instruction with long result
Legend: R W
1 RW
5 W
Subsequent Same-Unit Instruction Executable n n n Xw n
n
Xw
TMS320C67x Pipeline
7-37
7.3.5
Single-Cycle Instructions
Single-cycle instructions complete execution during the E1 phase of the pipeline (see Table 720). Figure 78 shows the fetch, decode, and execute phases of the pipeline that single-cycle instructions use. Figure 79 is the single-cycle execution diagram. The operands are read, the operation is performed, and the results are written to a register, all during E1. Single-cycle instructions have no delay slots.
Table 720. Single-Cycle Execution

src1 src2 dst

.L, .S., .M, or .D
Figure 78. Single-Cycle Instruction Phases

PG PS PW PR DP DC E1
Figure 79. Single-Cycle Execution Block Diagram
Operands (data)
7-38

Functional unit .L, .S, .M, or .D Register file
Write results E1
7.3.6
16
16-Bit Multiply Instructions

The 16 16-bit multiply instructions use both the E1 and E2 phases of the pipeline to complete their operations (see Table 721). Figure 710 shows the pipeline phases the multiply instructions use. Figure 711 shows the operations occurring in the pipeline for a multiply. In the E1 phase, the operands are read and the multiply begins. In the E2 phase, the multiply finishes, and the result is written to the destination register. Multiply instructions have one delay slot.
Table 721. 16 16-Bit Multiply Execution

Pipeline Stage Read Written Unit in use .M E1 E2
src1 src2 dst
Figure 710. Multiply Instruction Phases

Figure 711.Multiply Execution Block Diagram
Operands (data)

Functional unit .M E1 Register file
Write results E2
TMS320C67x Pipeline
7-39
7.3.7
Store Instructions
Store instructions require phases E1 through E3 to complete their operations (see Table 722). Figure 712 shows the pipeline phases the store instructions use. Figure 713 shows the operations occurring in the pipeline phases for a store. In the E1 phase, the address of the data to be stored is computed. In the E2 phase, the data and destination addresses are sent to data memory. In the E3 phase, a memory write is performed. The address modification is performed in the E1 stage of the pipeline. Even though stores finish their execution in the E3 phase of the pipeline, they have no delay slots.
Table 722. Store Execution

Pipeline Stage Read E1 E2 E3
baseR, offsetR src baseR

.D2
Written Unit in use
Figure 712. Store Instruction Phases

PG PS PW PR DP DC E1 Address modification E2 E3
7-40
Figure 713. Store Execution Block Diagram

Functional unit .D E1 Register file Data E2 Memory controller Address E3 Memory E2
When you perform a load and a store to the same memory location, these rules apply (i = cycle):
- When a load is executed before a store, the old value is loaded and the
new value is stored. i LDW i+1 STW

- When a store is executed before a load, the new value is stored and the
new value is loaded. i STW i+1 LDW

- When the instructions are executed in parallel, the old value is loaded first
and then the new value is stored, but both occur in the same phase. i STW i || LDW There is additional explanation of why stores have zero delay slots in section 7.3.8.
TMS320C67x Pipeline
7-41
7.3.8
Load Instructions
Data loads require five of the pipeline execute phases to complete their operations (see Table 723). Figure 714 shows the pipeline phases the load instructions use.
Table 723. Load Execution

Pipeline Stage Read Written Unit in use E1 E2 E3 E4 E5
baseR offsetR baseR

.D
dst
Figure 714. Load Instruction Phases

PG PS PW PR DP DC E1 Address modification E2 E3 E4 E5
4 delay slots
Figure 715 shows the operations occurring in the pipeline phases for a load. In the E1 phase, the data address pointer is modified in its register. In the E2 phase, the data address is sent to data memory. In the E3 phase, a memory read at that address is performed.
7-42
Figure 715. Load Execution Block Diagram

Functional unit .D E1 Register file Data Memory controller E4 Address E3 Memory E5 E2
In the E4 stage of a load, the data is received at the CPU core boundary. Finally, in the E5 phase, the data is loaded into a register. Because data is not written to the register until E5, load instructions have four delay slots. Because pointer results are written to the register in E1, there are no delay slots associated with the address modification. In the following code, pointer results are written to the A4 register in the first execute phase of the pipeline and data is written to the A3 register in the fifth execute phase.
LDW .D1 *A4++,A3
Because a store takes three execute phases to write a value to memory and a load takes three execute phases to read from memory, a load following a store accesses the value placed in memory by that store in the cycle after the store is completed. This is why the store is considered to have zero delay slots.
TMS320C67x Pipeline
7-43
7.3.9
Branch Instructions
Although branch takes one execute phase, there are five delay slots between the execution of the branch and execution of the target code (see Table 724). Figure 716 shows the pipeline phases used by the branch instruction and branch target code. The delay slots are shaded.
Table 724. Branch Execution

Pipeline Stage Read Written Branch Taken Unit in use .S2 n E1 PS PW PR DP DC E1
src2
Figure 716. Branch Instruction Phases

PG PS PW PR DP DC E1 PG PS PW PR DP DC E1
Branch target
5 delay slots
7-44
Figure 717 shows a branch execution block diagram. If a branch is in the E1 phase of the pipeline (in the .S2 unit in the figure), its branch target is in the fetch packet that is in PG during that same cycle (shaded in the figure). Because the branch target has to wait until it reaches the E1 phase to begin execution, the branch takes five delay slots before the branch target code executes.
Figure 717. Branch Execution Block Diagram

Fetch STH SADD STH LDW Decode 32 STH SADD STH LDW 32 SADD SHR SADD SHR 32 SMPYH SADD SHR SADD SHR 32 SMPY 256 SMPYH SMPYH SMPYH SMPYH 32 SADD SMPY SMPYH SMPY SMPYH 32 SADD SUB LDW SUB MV 32 B B LDW B NOP 32 MVK PG PS PW PR
DP
LDW Execute .L1 MVK .S1 SMPY .M1 .D1
LDW
DC
.D2
SMPYH .M2
B .S2
E1 .L2
TMS320C67x Pipeline
7-45
7.3.10 2-Cycle DP Instructions

Two-cycle DP instructions use the E1 and E2 phases of the pipeline to complete their operations (see Table 725). The following instructions are twocycle DP instructions:
-
ABSDP RCPDP RSQDP SPDP
The lower and upper 32 bits of the DP source are read on E1 using the src1 and src2 ports, respectively. The lower 32 bits of the DP source are written on E1 and the upper 32 bits of the DP source are written on E2. The 2-cycle DP instructions are executed on the .S units. The status is written to the FAUCR on E1. Figure 718 shows the pipeline phases the 2-cycle DP instructions use.
Table 725. 2-Cycle DP Execution

Pipeline Stage Read Written Unit in use E1 E2
src2_l src2_h dst_l

.S
dst_h
Figure 718. 2-Cycle DP Instruction Phases

7-46
7.3.11 4-Cycle Instructions

Four-cycle instructions use the E1 through E4 phases of the pipeline to complete their operations (see Table 726). The following instructions are 4-cycle instructions:
-
ADDSP DPINT DPSP DPTRUNC INTSP MPYSP SPINT SPTRUNC SUBSP
The sources are read on E1 and the results are written on E4. The 4-cycle instructions are executed on the .M or .L units. The status is written to the FMCR or FADCR on E4. Figure 719 shows the pipeline phases the 4-cycle instructions use.
Table 726. 4-Cycle Execution

Pipeline Stage Read Written Unit in use .L or .M E1 E2 E3 E4
src1 src2 dst
Figure 719. 4-Cycle Instruction Phases

PG PS PW PR DP DC E1 E2 E3 E4
3 delay slots
7.3.12 INTDP Instruction

The INTDP instruction uses the E1 through E5 phases of the pipeline to complete its operations (see Table 727). src2 is read on E1, the lower 32 bits of the result are written on E4, and the upper 32 bits of the result are written on E5. The INTDP instruction is executed on the .L units. The status is written to the FADCR on E4. Figure 720 shows the pipeline phases the INTDP instructions use.
TMS320C67x Pipeline
7-47
Table 727. INTDP Execution

Pipeline Stage Read Written Unit in use .L E1 E2 E3 E4 E5
src2 dst_l dst_h
Figure 720. INTDP Instruction Phases

PG PS PW PR DP DC E1 E2 E3 E4 E5
4 delay slots
7.3.13 DP Compare Instructions

The DP compare instructions use the E1 and E2 phases of the pipeline to complete their operations (see Table 728). The lower 32 bits of the sources are read on E1, the upper 32 bits of the sources are read on E2, and the results are written on E2. The following instructions are DP compare instructions:
- CMPEQDP - CMPLTDP - CMPGTDP
The DP compare instructions are executed on the .S unit. The functional unit latency for DP compare instructions is 2. The status is written to the FAUCR on E2. Figure 721 shows the pipeline phases the DP compare instructions use.
Table 728. DP Compare Execution

Pipeline Stage Read Written Unit in use .S E1 E2
src1_l src2_l
src1_h src2_h dst

.S
Figure 721. DP Compare Instruction Phases

7-48
7.3.14 ADDDP/SUBDP Instructions

The ADDDP/SUBDP instructions use the E1 through E7 phases of the pipeline to complete their operations (see Table 729). The lower 32 bits of the result are written on E6, and the upper 32 bits of the result are written on E7. The ADDDP/SUBDP instructions are executed on the .L unit. The functional unit latency for ADDDP/SUBDP instructions is 2. The status is written to the FADCR on E6. Figure 722 shows the pipeline phases the ADDDP/SUBDP instructions use.
Table 729. ADDDP/SUBDP Execution

Pipeline Stage Read Written Unit in use .L .L E1 E2 E3 E4 E5 E6 E7
src1_l src2_l
Figure 722. ADDDP/SUBDP Instruction Phases

PG PS PW PR DP DC E1 E2 E3 E4 E5 E6 E7
6 delay slots
TMS320C67x Pipeline
7-49
7.3.15 MPYI Instructions

The MPYI instruction uses the E1 through E9 phases of the pipeline to complete its operations (see Table 730). The sources are read on cycles E1 through E4 and the result is written on E9. The MPYI instruction is executed on the .M unit. The functional unit latency for the MPYI instruction is 4. Figure 723 shows the pipeline phases the MPYI instructions use.
Table 730. MPYI Execution

Pipeline Stage Read Written Unit in use .M .M .M .M E1 E2 E3 E4 E5 E6 E7 E8 E9
src1 src2
src1 src2
src1 src2
src1 src2 dst
Figure 723. MPYI Instruction Phases

PG PS PW PR DP DC E1 E2 E3 E4 E5 E6 E7 E8 E9
8 delay slots
7.3.16 MPYID Instructions

The MPYID instruction uses the E1 through E10 phases of the pipeline to complete its operations (see Table 731). The sources are read on cycles E1 through E4, the lower 32 bits of the result are written on E9, and the upper 32 bits of the result are written on E10. The MPYID instruction is executed on the .M unit. The functional unit latency for the MPYID instruction is 4. Figure 724 shows the pipeline phases the MPYID instructions use.
Table 731. MPYID Execution

Pipeline Stage Read Written Unit in use .M .M .M .M E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
src1 src2
src1 src2
src1 src2
src1 src2 dst_l dst_h
7-50
Figure 724. MPYID Instruction Phases

PG PS PW PR DP DC E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
9 delay slots
7.3.17 MPYDP Instructions

The MPYDP instruction uses the E1 through E10 phases of the pipeline to complete its operations (see Table 732). The lower 32 bits of src1 are read on E1 and E2, and the upper 32 bits of src1 are read on E3 and E4. The lower 32 bits of src2 are read on E1 and E3, and the upper 32 bits of src2 are read on E2 and E4. The lower 32 bits of the result are written on E9, and the upper 32 bits of the result are written on E10. The MPYDP instruction is executed on the .M unit. The functional unit latency for the MPYDP instruction is 4. The status is written to the FMCR on E9. Figure 725 shows the pipeline phases the MPYDP instructions use.
Table 732. MPYDP Execution

Pipeline Stage Read Written Unit in use .M .M .M .M E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
src1_l src1_l src1_h src1_h src2_l src2_h src2_l src2_h dst_l dst_h
Figure 725. MPYDP Instruction Phases

PG PS PW PR DP DC E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
9 delay slots
TMS320C67x Pipeline
7-51

The C67x pipeline is most effective when it is kept as full as the algorithms in the program allow it to be. It is useful to consider some situations that can affect pipeline performance. A fetch packet (FP) is a grouping of eight instructions. Each FP can be split into from one to eight execute packets (EPs). Each EP contains instructions that execute in parallel. Each instruction executes in an independent functional unit. The effect on the pipeline of combinations of EPs that include varying numbers of parallel instructions, or just a single instruction that executes serially with other code, is considered here. In general, the number of execute packets in a single FP defines the flow of instructions through the pipeline. Another defining factor is the instruction types in the EP. Each type of instruction has a fixed number of execute cycles that determines when this instructions operations are complete. Section 7.4.2 covers the effect of including a multicycle NOP in an individual EP. Finally, the effect of the memory system on the operation of the pipeline is considered. The access of program and data memory is discussed, along with memory stalls.
7.4.1
Pipeline Operation With Multiple Execute Packets in a Fetch Packet

Again referring to Figure 76 on page 7-6, pipeline operation is shown with eight instructions in every fetch packet. Figure 726, however, shows the pipeline operation with a fetch packet that contains multiple execute packets. Code for Figure 726 might have this layout:
instruction A ; EP k || instruction B ; instruction C ; EP k + 1 || instruction D || instruction E instruction F ; EP k + 2 || instruction G || instruction H || || || || || || || instruction instruction instruction instruction instruction instruction instruction instruction I ; EP k + 3 J K L M N O P FP n FP n
FP n
FP n + 1
... continuing with EPs k + 4 through k + 8, which have eight instructions in parallel, like k + 3.
7-52
Figure 726. Pipeline Operation: Fetch Packets With Different Numbers of Execute Packets
Clock cycle Fetch packet (FP) n n n n+1 n+2 n+3 n+4 n+5 n+6 Execute packet (EP) k k+1 k+2 k+3 k+4 k+5 k+6 k+7 k+8
1
PG
2
PS
3
PW
4
PR
5
DP
6
DC DP
7
E1 DC DP
8
E2 E1
9
10
E4 E3 E2 E1 DC DP PR PW PS
11
E5 E4 E3 E2 E1 DC DP PR PW
12
E6 E5 E4 E3 E2 E1 DC DP PR
13
E7 E6 E5 E4 E3 E2 E1 DC DP
14
E8 E7 E6 E5 E4 E3 E2 E1 DC
15
E9 E8 E7 E6 E5 E4 E3 E2 E1
16
E10 E9 E8 E7 E6 E5 E4 E3 E2
17
E10 E9 E8 E7 E6 E5 E4 E3
PG
PS PG
PW PS PG
In Figure 726, fetch packet n, which contains three execute packets, is shown followed by six fetch packets (n + 1 through n + 6), each with one execute packet (containing eight parallel instructions). The first fetch packet (n) goes through the program fetch phases during cycles 14. During these cycles, a program fetch phase is started for each of the fetch packets that follow. In cycle 5, the program dispatch (DP) phase, the CPU scans the p-bits and detects that there are three execute packets (k through k + 2) in fetch packet n. This forces the pipeline to stall, which allows the DP phase to start for execute packets k + 1 and k + 2 in cycles 6 and 7. Once execute packet k + 2 is ready to move on to the DC phase (cycle 8), the pipeline stall is released. The fetch packets n + 1 through n + 4 were all stalled so the CPU could have time to perform the DP phase for each of the three execute packets (k through k + 2) in fetch packet n. Fetch packet n + 5 was also stalled in cycles 6 and 7: it was not allowed to enter the PG phase until after the pipeline stall was released in cycle 8. The pipeline continues operation as shown with fetch packets n + 5 and n + 6 until another fetch packet containing multiple execution packets enters the DP phase, or an interrupt occurs.

PR PW PS Pipeline stall PG
DC DP PR
PW PS PG
TMS320C67x Pipeline
7-53
7.4.2
Multicycle NOPs
The NOP instruction has an optional operand, count, that allows you to issue a single instruction for multicycle NOPs. A NOP 2, for example, fills in extra delay slots for the instructions in its execute packet and for all previous execute packets. If a NOP 2 is in parallel with an MPY instruction, the MPYs results will be available for use by instructions in the next execute packet. Figure 727 shows how a multicycle NOP can drive the execution of other instructions in the same execute packet. Figure 727(a) shows a NOP in an execute packet (in parallel) with other code. The results of the LD, ADD, and MPY will all be available during the proper cycle for each instruction. Hence NOP has no effect on the execute packet. Figure 727(b) shows the replacement of a single-cycle NOP with a multicycle NOP (NOP 5) in the same execute packet. The NOP 5 will cause no operation to perform other than the operations from the instructions inside its execute packet. The results of the LD, ADD, and MPY cannot be used by any other instructions until the NOP 5 period has completed.
Figure 727. Multicycle NOP in an Execute Packet

(a)
Cycle Execute packet LD ADD MPY NOP i i+1 i+2 i+3 i+4 Can use LD result i+5 Cycle
Can use ADD results Can use MPY results
(b)
Execute packet
LD
ADD
MPY
NOP 5
i i+1 i+2 i+3 i+4
All values available on i + 5
i+5
7-54
Figure 728 shows how a multicycle NOP can be affected by a branch. If the delay slots of a branch finish while a multicycle NOP is still dispatching NOPs into the pipeline, the branch overrides the multicycle NOP and the branch target begins execution five delay slots after the branch was issued.
Figure 728. Branching and Multicycle NOPs

Pipeline Phase Cycle # 1 2 3 4 5 6 7 8 9 10 11 Normal EP7 See Figure 727(b) EP1 EP2 EP3 EP4 EP5 EP6 Branch EP7 B Branch Target E1 { { { { { PG PS PW PR DP DC E1
...
EP without branch EP without branch EP without branch
EP without branch LD MPY ADD NOP5
Branch will execute here
Delay slots of the branch
In one case, execute packet 1 (EP1) does not have a branch. The NOP 5 in EP6 will force the CPU to wait until cycle 11 to execute EP7. In the other case, EP1 does have a branch. The delay slots of the branch coincide with cycles 2 through 6. Once the target code reaches E1 in cycle 7, it executes.
TMS320C67x Pipeline
7-55
7.4.3
Memory Considerations
The C67x has a memory configuration typical of a DSP, with program memory in one physical space and data memory in another physical space. Data loads and program fetches have the same operation in the pipeline, they just use different phases to complete their operations. With both data loads and program fetches, memory accesses are broken up into multiple phases. This enables the C67x to access memory at a high speed. These phases are shown in Figure 729.
Figure 729. Pipeline Phases Used During Memory Accesses

Program memory accesses use these pipeline phases PG PS PW PR DP
Data load accesses use these pipeline phases
E1
E2
E3
E4
E5
To understand the memory accesses, compare data loads and instruction fetches/dispatches. The comparison is valid because data loads and program fetches operate on internal memories of the same speed on the C67x and perform the same types of operations (listed in Table 733) to accommodate those memories. Table 733 shows the operation of program fetches pipeline versus the operation of a data load.
Table 733. Program Memory Accesses Versus Data Load Accesses
7-56

Operation Program Memory Access Phase PG PS Data Load Access Phase E1 E2 E3 E4 E5 Compute address Send address to memory Memory read/write PW PR DP Program memory: receive fetch packet at CPU boundary Data load: receive data at CPU boundary Program memory: send instruction to functional units Data load: send data to register
Depending on the type of memory and the time required to complete an access, the pipeline may stall to ensure proper coordination of data and instructions. This is discussed in section 7.4.3.1, Memory Stalls.
In the instance where multiple accesses are made to a single ported memory, the pipeline will stall to allow the extra access to occur. This is called a memory bank hit and is discussed in section 7.4.3.2, Memory Bank Hits.
7.4.3.1
Memory Stalls
A memory stall occurs when memory is not ready to respond to an access from the CPU. This access occurs during the PW phase for a program memory access and during the E3 phase for a data memory access. The memory stall causes all of the pipeline phases to lengthen beyond a single clock cycle, causing execution to take additional clock cycles to finish. The results of the program execution are identical whether a stall occurs or not. Figure 730 illustrates this point.
Figure 730. Program and Data Memory Stalls

Clock cycle Fetch packet (FP) n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 1 2 3 4 5 6 7 8 9 10
E2 E1
11
E3 E2 E1
12
13
14
15
E4 E3 E2 E1
16
E5 E4 E3 E2 E1
PG
PS
PW PS
PR
DP PR
DC DP
E1
PG
PW PS
DC DP PR
PG
PW PS
PR
Program
DC DP PR
PG
PW PS
memory stall
DC DP PR
Data
PG
PW PS
memory stall
DC DP PR
PG
PW PS
DC DP PR
PG
PW PS
PG
PW PS
PG
PW PS
PG
PG
TMS320C67x Pipeline
7-57
7.4.3.2
Memory Bank Hits

Most C67x devices use an interleaved memory bank scheme, as shown in Figure 731. Each number in the diagram represents a byte address. A load byte (LDB) instruction from address 0 loads byte 0 in bank 0. A load halfword (LDH) instruction from address 0 loads the halfword value in bytes 0 and 1, which are also in bank 0. A load word (LDW) instruction from address 0 loads bytes 0 through 3 in banks 0 and 1. A load double-word (LDDW) instruction from address 0 loads bytes 0 through 7 in banks 0 through 3.
Figure 731. 8-Bank Interleaved Memory

0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31
16N 16N +1 16N +2 16N +3 16N +4 16N +5 16N +6 16N +7 16N +8 16N +9 16N + 0 16N + 1 16N + 16N + 16N + 16N +15 1 1 12 13 14 Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7
Because each of these banks is single-ported memory, only one access to each bank is allowed per cycle. Two accesses to a single bank in a given cycle result in a memory stall that halts all pipeline operation for one cycle, while the second value is read from memory. Two memory operations per cycle are allowed without any stall, as long as they do not access the same bank. Consider the code in Example 72. Because both loads are trying to access the same bank at the same time, one load must wait. The first LDW accesses bank 0 on cycle i + 2 (in the E3 phase) and the second LDW accesses bank 0 on cycle i + 3 (in the E3 phase). See Table 734 for identification of cycles and phases. The E4 phase for both LDW instructions is in cycle i + 4. To eliminate this extra phase, the loads must access data from different banks (B4 address would need to be in bank 1). For more information on programming topics, see the TMS320C62x/C67x Programmers Guide.
Example 72. Load From Memory Banks

LDW || LDW .D1 .D2 *A4++,A5 ; load 1, A4 address is in bank 0 *B4++,B5 ; load 2, B4 address is in bank 0
7-58
Table 734. Loads in Pipeline From Example 72

i
LDW .D1 Bank 0 LDW .D2 Bank 0 E1 E1
i+1
E2 E2
i+2
E3
i+3
E3
i+4
E4 E4
i+5
E5 E5
For devices that have more than one memory space (see Figure 732), an access to bank 0 in one space does not interfere with an access to bank 0 in another memory space, and no pipeline stall occurs. The internal memory of the C67x family varies from device to device. See the TMS320C62x/C67x Peripherals Reference Guide to determine the memory spaces in your particular device.
Figure 732. 8-Bank Interleaved Memory With Two Memory Spaces

Memory space 0
0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31
16N 16N +1 16N +2 16N +3 16N +4 16N +5 16N +6 16N +7 16N +8 16N +9 16N + 0 16N + 1 16N + 16N + 16N + 16N +15 1 1 12 13 14 Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7
Memory space 1
16M 16M +1 16M +2 16M +3 16M +4 16M +5 16M +6 16M +7 16M +8 16M +9 16M+ 0 16M + 1 16M+ 16M + 16M+ 16M+15 1 1 12 13 14
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
TMS320C67x Pipeline
7-59
Chapter 89
Interrupts
This chapter describes CPU interrupts, including reset and the nonmaskable interrupt (NMI). It details the related CPU control registers and their functions in controlling interrupts. It also describes interrupt processing, the method the CPU uses to detect automatically the presence of interrupts and divert program execution flow to your interrupt service code. Finally, the chapter describes the programming implications of interrupts.
Topic
8.1 8.2 8.3 8.4 8.5 8.6
Page
Overview of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Globally Enabling and Disabling Interrupts (Control Status RegisterCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Individual Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 Interrupt Detection and Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Performance Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
8-1
Overview of Interrupts
8.1 Overview of Interrupts

Typically, DSPs work in an environment that contains multiple external asynchronous events. These events require tasks to be performed by the DSP when they occur. An interrupt is an event that stops the current process in the CPU so that the CPU can attend to the task needing completion because of the event. These interrupt sources can be on chip or off chip, such as timers, analog-to-digital converters, or other peripherals. Servicing an interrupt involves saving the context of the current process, completing the interrupt task, restoring the registers and the process context, and resuming the original process. There are eight registers that control servicing interrupts. An appropriate transition on an interrupt pin sets the pending status of the interrupt within the interrupt flag register (IFR). If the interrupt is properly enabled, the CPU begins processing the interrupt and redirecting program flow to the interrupt service routine.
8.1.1
Types of Interrupts and Signals Used

There are three types of interrupts on the CPUs of the TMS320C6000 DSPs. These three types are differentiated by their priorities, as shown in Table 81. The reset interrupt has the highest priority and corresponds to the RESET signal. The nonmaskable interrupt is the interrupt of second highest priority and corresponds to the NMI signal. The lowest priority interrupts are interrupts 415. They correspond to the INT4INT15 signals. RESET, NMI, and some of the INT4INT15 signals are mapped to pins on C6000 devices. Some of the INT4INT15 interrupt signals are used by internal peripherals and some may be unavailable or can be used under software control. Check your data sheet to see your devices interrupt specifications.
8-2
Table 81. Interrupt Priorities
8.1.1.1
Reset (RESET)
Reset is the highest priority interrupt and is used to halt the CPU and return it to a known state. The reset interrupt is unique in a number of ways:
- RESET is an active-low signal. All other interrupts are active-high signals. - RESET must be held low for 10 clock cycles before it goes high again to
reinitialize the CPU properly.

- The instruction execution in progress is aborted and all registers are re-
turned to their default states.

- The reset interrupt service fetch packet must be located at address 0. - RESET is not affected by branches.
8.1.1.2
Nonmaskable Interrupt (NMI)

NMI is the second-highest priority interrupt and is generally used to alert the CPU of a serious hardware problem such as imminent power failure. For NMI processing to occur, the nonmaskable interrupt enable (NMIE) bit in the interrupt enable register must be set to 1. If NMIE is set to 1, the only condition that can prevent NMI processing is if the NMI occurs during the delay slots of a branch (whether the branch is taken or not). NMIE is cleared to 0 at reset to prevent interruption of the reset. It is cleared at the occurrence of an NMI to prevent another NMI from being processed. You cannot manually clear NMIE, but you can set NMIE to allow nested NMIs. While NMI is cleared, all maskable interrupts (INT4INT15) are disabled.
Interrupts
8-3

Priority Highest Interrupt Name Reset NMI INT4 INT5 INT6 INT7 INT8 INT9 INT10 INT11 INT12 INT13 INT14 INT15 Lowest
8.1.1.3
Maskable Interrupts (INT4INT15)

The CPUs of the C6000 DSPs have 12 interrupts that are maskable. These have lower priority than the NMI and reset interrupts. These interrupts can be associated with external devices, on-chip peripherals, software control, or not be available. Assuming that a maskable interrupt does not occur during the delay slots of a branch (this includes conditional branches that do not complete execution due to a false condition), the following conditions must be met to process a maskable interrupt:
- The global interrupt enable bit (GIE) bit in the control status register (CSR) is
set to1.
- The NMIE bit in the interrupt enable register (IER) is set to1. - The corresponding interrupt enable (IE) bit in the IER is set to1. - The corresponding interrupt occurs, which sets the corresponding bit in
the IFR to 1 and there are no higher priority interrupt flag (IF) bits set in the IFR.
8.1.1.4
Interrupt Acknowledgment (IACK and INUMx)

The IACK and INUMx signals alert hardware external to the C6000 that an interrupt has occurred and is being processed. The IACK signal indicates that the CPU has begun processing an interrupt. The INUMx signals (INUM3INUM0) indicate the number of the interrupt (bit position in the IFR) that is being processed. For example: INUM3 = 0 (MSB) INUM2 = 1 INUM1 = 1 INUM0 = 1 (LSB) Together, these signals provide the 4-bit value 0111, indicating INT7 is being processed.
8-4
8.1.2
Interrupt Service Table (IST)

When the CPU begins processing an interrupt, it references the interrupt service table (IST). The IST is a table of fetch packets that contain code for servicing the interrupts. The IST consists of 16 consecutive fetch packets. Each interrupt service fetch packet (ISFP) contains eight instructions. A simple interrupt service routine may fit in an individual fetch packet. The addresses and contents of the IST are shown in Figure 81. Because each fetch packet contains eight 32-bit instruction words (or 32 bytes), each address in the table is incremented by 32 bytes (20h) from the one adjacent to it.
Figure 81. Interrupt Service Table

Interrupt service table (IST) 000h 020h 040h 060h 080h 0A0h 0C0h 0E0h 100h 120h 140h 160h 180h 1A0h 1C0h 1E0h RESET ISFP NMI ISFP Reserved Reserved INT4 ISFP INT5 ISFP INT6 ISFP INT7 ISFP INT8 ISFP INT9 ISFP INT10 ISFP INT11 ISFP INT12 ISFP INT13 ISFP INT14 ISFP INT15 ISFP Program memory
Interrupts
8-5
8.1.2.1
Interrupt Service Fetch Packet (ISFP)

An ISFP is a fetch packet used to service an interrupt. Figure 82 shows an ISFP that contains an interrupt service routine small enough to fit in a single fetch packet (FP). To branch back to the main program, the FP contains a branch to the interrupt return pointer instruction (B IRP). This is followed by a NOP 5 instruction to allow the branch target to reach the execution stage of the pipeline. Note: If the NOP 5 was not in the routine, the CPU would execute the next five execute packets that are associated with the next ISFP.
Figure 82. Interrupt Service Fetch Packet

Interrupt service table (IST) 000h 020h 040h ISFP for INT6 0C0h 0C4h 0C8h 0CCh 0D0h 0D4h 0D8h 0DCh Instr1 Instr2 Instr3 Instr4 Instr5 Instr6 B IRP NOP 5 060h 080h 0A0h 0C0h 0E0h 100h 120h 140h 160h 180h 1A0h 1C0h 1E0h RESET ISFP NMI ISFP Reserved Reserved INT4 ISFP INT5 ISFP INT6 ISFP INT7 ISFP INT8 ISFP INT9 ISFP INT10 ISFP INT11 ISFP INT12 ISFP INT13 ISFP INT14 ISFP INT15 ISFP Program memory
The interrupt service routine for INT6 is short enough to be contained in a single fetch packet.
If the interrupt service routine for an interrupt is too large to fit in a single FP, a branch to the location of additional interrupt service routine code is required. Figure 83 shows that the interrupt service routine for INT4 was too large for a single FP, and a branch to memory location 1234h is required to complete the interrupt service routine.
8-6
Figure 83. IST With Branch to Additional Interrupt Service Code Located Outside the IST
IST 000h 020h The interrupt service routine for INT4 includes this 7-instruction extension of the interrupt ISFP. 1220h 1224h 1228h 122Ch 1230h 1234h 1238h 123Ch Instr9 B IRP Instr11 040h 060h 080h 0A0h 0C0h 0E0h 100h 120h 140h 160h 180h 1A0h 1C0h 1240h 1244h 1248h 124Ch 1250h 1254h 1258h 125Ch Instr12 Instr13 Instr14 Instr15 Additional ISFP for INT4 Additional ISFP for INT4 Program memory 1E0h RESET ISFP NMI ISFP Reserved Reserved INT4 ISFP INT5 ISFP INT6 ISFP INT7 ISFP INT8 ISFP INT9 ISFP INT10 ISFP INT11 ISFP INT12 ISFP INT13 ISFP INT14 ISFP INT15 ISFP ISFP for INT4 080h 084h 088h 08Ch 090h 094h 098h 09Ch Instr1 Instr2 B 1234h Instr4 Instr5 Instr6 Instr7 Instr8
Note: The instruction B 1234h branches into the middle of a fetch packet (at 1220h) and processes code starting at address 1234h. The CPU ignores code from address 12201230h, even if it is in parallel to code at address 1234h.
Interrupts
8-7
8.1.2.2
Interrupt Service Table Pointer Register (ISTP)

The interrupt service table pointer (ISTP) register is used to locate the interrupt service routine. One field, ISTB identifies the base portion of the address of the IST; another field, HPEINT, identifies the specific interrupt and locates the specific fetch packet within the IST. Figure 84 shows the fields of the ISTP. Table 82 describes the fields and how they are used.
Figure 84. Interrupt Service Table Pointer (ISTP)

31 ISTB R, W, +0 10 9 HPEINT 5 4 0 R, +0 0 0 0 0 0
Legend: R W +0
Readable by the MVC instruction Writeable by the MVC instruction Value is cleared at reset
Table 82. Interrupt Service Table Pointer (ISTP) Field Descriptions

Bits 04 59 Field Name Description Set to 0 (fetch packets must be aligned on 8-word (32-byte) boundaries). HPEINT Highest priority enabled interrupt. This field gives the number (related bit position in the IFR) of the highest priority interrupt (as defined in Table 81) that is enabled by its bit in the IER. Thus, the ISTP can be used for manual branches to the highest priority enabled interrupt. If no interrupt is pending and enabled, HPEINT contains the value 00000b. The corresponding interrupt need not be enabled by NMIE (unless it is NMI) or by GIE. Interrupt service table base portion of the IST address. This field is set to 0 on reset. Thus, upon startup the IST must reside at address 0. After reset, you can relocate the IST by writing a new value to ISTB. If relocated, the first ISFP (corresponding to RESET) is never executed via interrupt processing, because reset sets the ISTB to 0. See Example 81. 1031 ISTB 8-8
The reset fetch packet must be located at address 0, but the rest of the IST can be at any program memory location that is on a 256-word boundary. The location of the IST is determined by the interrupt service table base (ISTB) field of the ISTP. Example 81 shows the relationship of the ISTB to the table location.
Example 81. Relocation of Interrupt Service Table

IST
(a) Relocating the IST to 800h

1) Copy the IST, located between 0h and 200h, to the memory location between 800h and A00h. Write 800h to the ISTP register: MVK 800h, A2 MVC A2, ISTP
RESET ISFP
2)
800h 820h 840h 860h 880h 8A0h
RESET ISFP NMI ISFP Reserved Reserved INT4 ISFP INT5 ISFP INT6 ISFP INT7 ISFP INT8 ISFP INT9 ISFP INT10 ISFP INT11 ISFP INT12 ISFP INT13 ISFP INT14 ISFP INT15 ISFP Program memory
ISTP = 800h = 1000 0000 0000b
(b) How the ISTP directs the CPU to the appropriate ISFP in the relocated IST
Assume: IFR = BBC0h = 1011 1011 1100 0000b IER = 1230h = 0001 0010 0011 0001b 2 enabled interrupts pending: INT9 and INT12 The 1s in the IFR indicate pending interrupts; the 1s in the IER indicate the interrupts that are enabled. INT9 has a higher priority than INT12, so HPEINT is encoded with the value for INT9, 01001b. HPEINT corresponds to bits 95 of the ISTP: ISTP = 1001 0010 0000b = 920h = address of INT9
8C0h 8E0h 900h 920h 940h 96h0 980h 9A0h 9C0h 9E0h
Interrupts
8-9
8.1.3
Summary of Interrupt Control Registers

Table 83 lists the eight interrupt control registers on the C6000 devices. The control status register (CSR) and the interrupt enable register (IER) enable or disable interrupt processing. The interrupt flag register (IFR) identifies pending interrupts. The interrupt set register (ISR) and interrupt clear register (ICR) can be used in manual interrupt processing. There are three pointer registers. ISTP points to the interrupt service table. NRP and IRP are the return pointers used when returning from a nonmaskable or a maskable interrupt, respectively. More information on all the registers can be found at the locations listed in the table.
Table 83. Interrupt Control Registers

Abbreviation CSR IER IFR ISR ICR ISTP NRP Name Control status register Interrupt enable register Interrupt flag register Interrupt set register Interrupt clear register Interrupt service table pointer Nonmaskable interrupt return pointer Interrupt return pointer Description Allows you to globally set or disable interrupts Allows you to enable interrupts Shows the status of interrupts Allows you to set flags in the IFR manually Allows you to clear flags in the IFR manually Pointer to the beginning of the interrupt service table Contains the return address used on return from a nonmaskable interrupt. This return is accomplished via the B NRP instruction. Contains the return address used on return from a maskable interrupt. This return is accomplished via the B IRP instruction. Page Number 8-11 8-13 8-14 8-14 8-14 8-8 8-16
IRP
8-17
8-10
Globally Enabling and Disabling Interrupts Globally Enabling and Disabling Interrupts (Control Status RegisterCSR)
8.2 Globally Enabling and Disabling Interrupts (Control Status RegisterCSR)

The control status register (CSR) contains two fields that control interrupts: GIE and PGIE, as shown in Figure 85 and Table 84. The other fields of the registers serve other purposes and are discussed in section 2.6.3 on page 2-17.
Figure 85. Control Status Register (CSR)

31 CPU ID
R
24
23 Revision ID
16
15 PWRD
R, W, +0
10
9 SAT
R, C, +0
8 EN
R, +x
7 PCC
4 DCC
1 PGIE
0 GIE
R, W, +0
Legend: R W +x +0 C
Readable by the MVC instruction Writeable by the MVC instruction Value undefined after reset Value is zero after reset Clearable using the MVC instruction
Table 84. Control Status Register (CSR) Interrupt Control Field Descriptions
Bit 0 Field Name GIE Description Global interrupt enable; globally enables or disables all maskable interrupts. GIE = 1: maskable interrupts globally enabled GIE = 0: maskable interrupts globally disabled Previous GIE; saves the value of GIE when an interrupt is taken. This value is used on return from an interrupt.
PGIE
The global interrupt enable (GIE) allows you to enable or disable all maskable interrupts by controlling the value of a single bit. GIE is bit 0 of the control status register (CSR).
- GIE = 1 enables the maskable interrupts so that they are processed. - GIE = 0 disables the maskable interrupts so that they are not processed.
Bit 1 of the CSR is PGIE and contains the previous value of GIE. During processing of a maskable interrupt, PGIE is loaded with GIE and GIE is cleared. GIE is cleared during a maskable interrupt to keep another maskable interrupt from occurring before the device state has been saved. Upon return from an interrupt, by way of the B IRP instruction, the PGIE value is copied back to GIE and remains unchanged. The purpose of PGIE is to allow proper clearing of GIE when an interrupt has already been detected for processing.
Interrupts
8-11
Globally Enabling and Disabling Interrupts (Control Status RegisterCSR) Globally Enabling and Disabling Interrupts
Suppose the CPU begins processing an interrupt. Just as the interrupt processing begins, GIE is being cleared by you writing a 0 to bit 0 of the CSR with the MVC instruction. GIE is cleared by the MVC instruction prior to being copied to PGIE. Upon returning from the interrupt, PGIE is copied back to GIE, resulting in GIE being cleared as directed by your code. Example 82 shows how to disable maskable interrupts globally and Example 83 shows how to enable maskable interrupts globally.
Example 82. Code Sequence to Disable Maskable Interrupts Globally

MVC AND MVC CSR,B0 -2,B0,B0 B0,CSR ; get CSR ; get ready to clear GIE ; clear GIE
Example 83. Code Sequence to Enable Maskable Interrupts Globally

MVC OR MVC CSR,B0 1,B0,B0 B0,CSR ; get CSR ; get ready to set GIE ; set GIE
8-12
Individual Interrupt Control
8.3 Individual Interrupt Control

Servicing interrupts effectively requires individual control of all three types of interrupts: reset, nonmaskable, and maskable. Enabling and disabling individual interrupts is done with the interrupt enable register (IER). The status of pending interrupts is stored in the interrupt flag register (IFR). Manual interrupt processing can be accomplished through the use of the interrupt set register (ISR) and interrupt clear register (ICR). The interrupt return pointers restore context after servicing nonmaskable and maskable interrupts.
8.3.1
Enabling and Disabling Interrupts (Interrupt Enable Register IER)

You can enable and disable individual interrupts by setting and clearing bits in the IER that correspond to the individual interrupts. An interrupt can trigger interrupt processing only if the corresponding bit in the IER is set. Bit 0, corresponding to reset, is not writeable and is always read as 1, so the reset interrupt is always enabled. You cannot disable the reset interrupt. Bits IE4IE15 can be written as 1 or 0, enabling or disabling the associated interrupt, respectively. The IER is shown in Figure 86.
Figure 86. Interrupt Enable Register (IER)

31 16
Reserved
15 IE15 IE14 IE13 IE12 IE11 IE10 IE9 IE8 IE7 IE6 IE5 IE4 Rsv Rsv NMIE 1 R, +1
R, W, +0
Legend: R = Readable by the MVC instruction W = Writeable by the MVC instruction Rsv = Reserved +1 = Value after reset +0 = Value after reset
When NMIE = 0, all nonreset interrupts are disabled, preventing interruption of an NMI. NMIE is cleared at reset to prevent any interruption of processor initialization until you enable NMI. After reset, you must set NMIE to enable the NMI and to allow INT15INT4 to be enabled by GIE and the appropriate IER bit. You cannot manually clear the NMIE; the bit is unaffected by a write of 0. NMIE is also cleared by the occurrence of an NMI. If cleared, NMIE is set only by completing a B NRP instruction or by a write of 1 to NMIE. Example 84 and Example 85 show code for enabling and disabling individual interrupts, respectively.
Interrupts
8-13
Example 84. Code Sequence to Enable an Individual Interrupt (INT9)

MVK MVC OR MVC 200h,B1 ; set bit 9 IER,B0 ; get IER B1,B0,B0 ; get ready to set IE9 B0,IER ; set bit 9 in IER
Example 85. Code Sequence to Disable an Individual Interrupt (INT9)

MVK MVC AND MVC FDFFh,B1 ; clear bit 9 IER,B0 B1,B0,B0 ; get ready to clear IE9 B0,IER ; clear bit 9 in IER
8.3.2
Status of, Setting, and Clearing Interrupts (Interrupt Flag, Set, and Clear RegistersIFR, ISR, ICR)
The interrupt flag register (IFR) contains the status of INT4INT15 and NMI. Each interrupts corresponding bit in the IFR is set to 1 when that interrupt occurs; otherwise, the bits have a value of 0. If you want to check the status of interrupts, use the MVC instruction to read the IFR. Figure 87 shows the IFR.
Figure 87. Interrupt Flag Register (IFR)

31 Reserved R, +0 16
15 IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 R, +0 IF6 IF5 IF4 Rsv Rsv NMIF 0
Legend: R = Readable by the MVC instruction +0 = Cleared at reset rsv = Reserved
The interrupt set register (ISR), shown in Figure 88, and the interrupt clear register (ICR), shown in Figure 89, allow you to set or clear maskable interrupts manually in the IFR. Writing a 1 to IS4IS15 of the ISR causes the corresponding interrupt flag to be set in the IFR. Similarly, writing a 1 to a bit of the ICR causes the corresponding interrupt flag to be cleared. Writing a 0 to any bit of either the ISR or the ICR has no effect. Incoming interrupts have priority and override any write to the ICR. You cannot set or clear any bit in the ISR or ICR to affect NMI or reset.
8-14
Note: Any write to the ISR or ICR (by the MVC instruction) effectively has one delay slot because the results cannot be read (by the MVC instruction) in the IFR until two cycles after the write to the ISR or ICR. Any write to the ICR is ignored by a simultaneous write to the same bit in the ISR. Example 86 and Example 87 show code examples to set and clear individual interrupts.
Figure 88. Interrupt Set Register (ISR)

31 Reserved 16
15 IS15 IS14 IS13 IS12 IS11 IS10 IS9 IS8 W IS7 IS6 IS5 IS4 Rsv Rsv Rsv Rsv
Legend: W = Writeable by the MVC instruction Rsv = Reserved
Figure 89. Interrupt Clear Register (ICR)

31 Reserved 16
15 IC15 IC14 IC13 IC12 IC11 IC10 IC9 IC8 W IC7 IC6 IC5 IC4 Rsv Rsv Rsv
0 Rsv
Legend: W = Writeable by the MVC instruction Rsv = Reserved
Example 86. Code to Set an Individual Interrupt (INT6) and Read the Flag Register
MVK MVC NOP MVC 40h,B3 B3,ISR IFR,B4
Example 87. Code to Clear an Individual Interrupt (INT6) and Read the Flag Register
MVK MVC NOP MVC 40h,B3 B3,ICR IFR,B4
Interrupts
8-15
8.3.3
Returning From Interrupt Servicing

After RESET goes high, the control registers are brought to a known value and program execution begins at address 0h. After nonmaskable and maskable interrupt servicing, use a branch to the corresponding return pointer register to continue the previous program execution.
8.3.3.1
CPU State After RESET

After RESET, the control registers and bits will contain the corresponding values: - AMR, ISR, ICR, IFR, and ISTP = 0h - IER = 1h - IRP and NRP = undefined - Bits 150 of the CSR = 100h in little-endian mode = 000h in big-endian mode
8.3.3.2
Returning From Nonmaskable Interrupts (NMI Return Pointer RegisterNRP)

The NMI return pointer register (NRP) contains the return pointer that directs the CPU to the proper location to continue program execution after NMI processing. A branch using the address in the NRP (B NRP) in your interrupt service routine returns to the program flow when NMI servicing is complete. Example 88 shows how to return from an NMI.
Example 88. Code to Return From NMI

B NOP NRP 5 ; return, sets NMIE ; delay slots
The NRP contains the 32-bit address of the first execute packet in the program flow that was not executed because of a nonmaskable interrupt. Although you can write a value to this register, any subsequent interrupt processing may overwrite that value. Figure 810 shows the NRP register.
Figure 810. NMI Return Pointer (NRP)

31 NRP R, W, +x 15 NRP R, W, +x Legend: R = Readable by the MVC instruction W = Writeable by the MVC instruction +x = value undefined after reset 0 16
8-16
8.3.3.3
Returning From Maskable Interrupts (Interrupt Return Pointer RegisterIRP)

The interrupt return pointer register (IRP) contains the return pointer that directs the CPU to the proper location to continue program execution after processing a maskable interrupt. A branch using the address in the IRP (B IRP) in your interrupt service routine returns to the program flow when interrupt servicing is complete. Example 89 shows how to return from a maskable interrupt.
Example 89. Code to Return from a Maskable Interrupt

B NOP IRP 5 ; return, moves PGIE to GIE ; delay slots
The IRP contains the 32-bit address of the first execute packet in the program flow that was not executed because of a maskable interrupt. Although you can write a value to this register, any subsequent interrupt processing may overwrite that value. Figure 811 shows the IRP register.
Figure 811.Interrupt Return Pointer (IRP)

31 IRP R, W, +x 15 IRP R, W, +x Legend: R = Readable by the MVC instruction W = Writeable by the MVC instruction +x = Value undefined after reset 0 16
Interrupts
8-17
Interrupt Detection and Processing
8.4 Interrupt Detection and Processing

When an interrupt occurs, it sets a flag in the IFR. Depending on certain conditions, the interrupt may or may not be processed. This section discusses the mechanics of setting the flag bit, the conditions for processing an interrupt, and the order of operation for detecting and processing an interrupt. The similarities and differences between reset and nonreset interrupts are also discussed.
8.4.1
Setting the Nonreset Interrupt Flag

Figure 812 and Figure 813 show the processing of a nonreset interrupt (INTm) for the TMS320C62x /TMS320C64x and TMS320C67x DSPs, respectively. The flag (IFm) for INTm in the IFR is set following the low-to-high transition of the INTm signal on the CPU boundary. This transition is detected on a clock-cycle by clock-cycle basis and is not affected by memory stalls that might extend a CPU cycle. Once there is a low-to-high transition on an external interrupt pin (cycle 1), it takes two clock cycles for the signal to reach the CPU boundary (cycle 3). When the interrupt signal enters the CPU, it is has been detected (cycle 4). Two clock cycles after detection, the interrupts corresponding flag bit in the IFR is set (cycle 6). In Figure 812 and Figure 813, IFm is set during CPU cycle 6. You could attempt to clear bit IFm by using an MVC instruction to write a 1 to bit m of the ICR in execute packet n + 3 (during CPU cycle 4). However, in this case, the automated write by the interrupt detection logic takes precedence and IFm remains set. Figure 812 and Figure 813 assume INTm is the highest priority pending interrupt and is enabled by GIE and NMIE as necessary. If it is not the highest priority pending interrupt, IFm remains set until either you clear it by writing a 1 to bit m of the ICR, or the processing of INTm occurs.
8.4.2
Conditions for Processing a Nonreset Interrupt

In clock cycle 4 of Figure 812 and Figure 813, a nonreset interrupt in need of processing is detected. For this interrupt to be processed, the following conditions must be valid on the same clock cycle and are evaluated every clock cycle:
- IFm is set during CPU cycle 6. (This determination is made in CPU cycle 4
by the interrupt logic.)

- There is not a higher priority IFm bit set in the IFR. - The corresponding bit in the IER is set (IEm = 1). 8-18
- GIE = 1 - NMIE = 1 - The five previous execute packets (n through n + 4) do not contain a
branch (even if the branch is not taken) and are not in the delay slots of a branch. Any pending interrupt will be taken as soon as pending branches are completed.
Figure 812. TMS320C62x/C64x Nonreset Interrupt Detection and Processing: Pipeline Operation
Clock cycle 0 External INTm at pin IFm IACK INUM Execute packet n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 0 0 0 0 E3 E2 E1 DC DP PR PW PS PG 0 E4 E3 E2 E1 DC DP PR PW PS PG 0 E5 E4 E3 E2 E1 DC DP PR PW PS PG 0 m 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 { 6 7 8 9 10 11 12 13 14 15 16 17
DC E1 E2 DP DC E1 PR DP DC PW PR DP PS PW PR PG PS PW PG PS PG
E5 E4 E3 E2 E1 DC DP PR PW PS PG
E5 E4 E3
Contains no branch E5 E4 E5
Annulled Instructions
Cycles 6 12: Nonreset interrupt processing is disabled.
ISFP
PG
PS PW
PR
DP
DC
E1
E2
E3
E4
E5
CPU cycle 0 1 3 4 5 6 7 8 9 10 11 14 15 16 17 2 12 13 IFm is set on the next CPU cycle boundary after a 4-clock cycle delay after the rising edge of INTm. After this point, interrupts are still disabled. All nonreset interrupts are disabled when NMIE = 0. All maskable interrupts are disabled when GIE = 0.
Interrupts
8-19
Figure 813. TMS320C67x Nonreset Interrupt Detection and Processing: Pipeline Operation
CPU cycle External INTm at pin IFm IACK INUM Execute packet n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 0 0 0 0 0 0 0 m 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
DC DP PR PW PS PG
E1 DC DP PR PW PS PG
E2 E1 DC DP PR PW PS PG
E4 E3 E2 E1 DC DP PR PW PS PG
E5 E4 E3 E2 E1 DC DP PR PW PS PG
E6 E5 E4 E3 E2 E1 E2 DP PR PW PS PG
E7 E6 E5 E4 E3
E8 E7 E6 E5 E4
E9 E8 E7 E6 E5
E10 E9 E8 E7 E6
E10 E9 E8 E7
E10 E9 E8
Contains no branch E10 E9 E10
Annulled Instructions
Cycles 614: Nonreset interrupt processing is disabled ISFP CPU cycle 0 1 3 4 5 6 7 8 PG 9 PS 10 PW 11 PR 12 DP 13 DC 14
E1 15 E2 16 E3 17 E4 18 E5 19 E6 20 E7 21 E8 22
IFm is set on the next CPU cycle boundary after a 4-clock cycle delay after the rising edge of INTm. After this point, interrupts are still disabled. All nonreset interrupts are disabled when NMIE = 0. All maskable interrupts are disabled when GIE = 0.
8-20
8.4.3
Actions Taken During Nonreset Interrupt Processing

During CPU cycles 612 of Figure 812 and cycles 614 of Figure 813, the following interrupt processing actions occur:
- Processing of subsequent nonreset interrupts is disabled. - For all interrupts except NMI, PGIE is set to the value of GIE and then GIE
is cleared.
- For NMI, NMIE is cleared. - The next execute packets (from n + 5 on) are annulled. If an execute pack-
et is annulled during a particular pipeline stage, it does not modify any CPU state. Annulling also forces an instruction to be annulled in future pipeline stages.
- The address of the first annulled execute packet (n+5) is loaded in to the
NRP (in the case of NMI) or IRP (for all other interrupts).
- A branch to the address held in ISTP (the pointer to the ISFP for INTm)
is forced into the E1 phase of the pipeline during cycle 7 for the C62x /C64x and cycle 9 for the C67x .
- During cycle 7, IACK is asserted and the proper INUMx signals are as-
serted to indicate which interrupt is being processed. The timings for these signals in Figure 812 and Figure 813 represent only the signals characteristics inside the CPU. The external signals may be delayed and be longer in duration to handle external devices. Check the data sheet for your specific device for particular timing values.
- IFm is cleared during cycle 8.
Interrupts
8-21
8.4.4
Setting the RESET Interrupt Flag for the TMS320C6000

RESET must be held low for a minimum of ten clock cycles. Four clock cycles after RESET goes high, processing of the reset vector begins. The flag for RESET (IF0) in the IFR is set by the low-to-high transition of the RESET signal on the CPU boundary. In Figure 814, IF0 is set during CPU cycle 15. This transition is detected on a clock-cycle by clock-cycle basis and is not affected by memory stalls that might extend a CPU cycle.
Figure 814. RESET Interrupt Detection and Processing: Pipeline Operation

Clock cycle 0 RESET at pin IF0 IACK INUM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 { 16 17 18 19 20 21 22
Execute packet n E1 E2 n+1 DC E1 n+2 n+3 n+4 n+5 n+6 n+7 DP PR PW PS DC DP PR PW Pipeline flush Cycles 15 21: Nonreset interrupt processing is disabled
PG PS PG
Reset ISFP CPU cycle 0
10
11
12 13
14
15
PG PS PW PR DP DC E1 16 17 18 19 20 21 22
IF0 is set on the next CPU cycle boundary after a 4-clock cycle delay after the rising edge of RESET. After this point, interrupts are still disabled. All nonreset interrupts are disabled when NMIE = 0. All maskable interrupts are disabled when GIE = 0.
8-22
8.4.5
Actions Taken During RESET Interrupt Processing

A low signal on the RESET pin is the only requirement to process a reset. Once RESET makes a high-to-low transition, the pipeline is flushed and CPU registers are returned to their reset values. GIE, NMIE, and the ISTB in the ISTP are cleared. For the CPU state after reset, see section 8.3.3.1 on page 8-16. During CPU cycles 1521 of Figure 814, the following reset processing actions occur:
- Processing of subsequent nonreset interrupts is disabled because GIE
and NMIE are cleared.

- A branch to the address held in ISTP (the pointer to the ISFP for INT0) is
forced into the E1 phase of the pipeline during cycle 16.

- During cycle 16, IACK is asserted and the proper INUMx signals are as-
serted to indicate a reset is being processed.

- IF0 is cleared during cycle 17.
Note: Code that starts running after reset must explicitly enable GIE, NMIE, and IER to allow interrupts to be processed.
Interrupts
8-23

The interaction of the C6000 CPU and sources of interrupts present performance issues for you to consider when you are developing your code.
8.5.1
General Performance
- Overhead. Overhead for all CPU interrupts is seven cycles for the
C62x/C64x and nine cycles for the C67x. You can see this in Figure 812 and Figure 813, where no new instructions are entering the E1 pipeline phase during CPU cycles 6 through 12 for the C62x/C64x and CPU cycles 6 through 14 for the C67x.
- Latency. Interrupt latency is 11 cycles for the C62x/C64x and 13 cycles
for the C67x (21 cycles for RESET). In Figure 813, although the interrupt is active in cycle 2, execution of interrupt service code does not begin until cycle 13 for the C62x//C64x and cycle 15 for the C67x.
- Frequency. The logic clears the nonreset interrupt (IFm) on cycle 8, with
any incoming interrupt having highest priority. Thus, an interrupt can be recognized every second cycle. Also, because a low-to-high transition is necessary, an interrupt can occur only every second cycle. However, the frequency of interrupt processing depends on the time required for interrupt service and whether you reenable interrupts during processing, thereby allowing nested interrupts. Effectively, only two occurrences of a specific interrupt can be recognized in two cycles.
8.5.2
Pipeline Interaction
Because the serial or parallel encoding of fetch packets does not affect the DC and subsequent phases of the pipeline, no conflicts between code parallelism and interrupts exist. There are three operations or conditions that can affect, or are affected by, interrupts:
- Branches. Nonreset interrupts are delayed if any execute packets n
through n + 4 in Figure 812 or Figure 813 contain a branch or are in the delay slots of a branch.
- Memory stalls. Memory stalls delay interrupt processing, because they
inherently extend CPU cycles.

- Multicycle NOPs. Multicycle NOPs (including IDLE) operate like other in-
structions when interrupted, except when an interrupt causes annulment of any but the first cycle of a multicycle NOP. In that case, the address of the next execute packet in the pipeline is saved in the NRP or the IRP. This prevents returning to an IDLE instruction or a multicycle NOP that was interrupted.
8-24
Programming Considerations
8.6 Programming Considerations

The interaction of the C6000 CPUs and sources of interrupts present programming issues for you to consider when you are developing your code.
8.6.1
Single Assignment Programming

Example 810 shows code without single assignment and Example 811 shows code using the single assignment programming method. To avoid unpredictable operation, you must employ the single assignment method in code that can be interrupted. When an interrupt occurs, all instructions entering E1 prior to the beginning of interrupt processing are allowed to complete execution (through E5). All other instructions are annulled and refetched upon return from interrupt. The instructions encountered after the return from the interrupt do not experience any delay slots from the instructions prior to processing the interrupt. Thus, instructions with delay slots prior to the interrupt can appear, to the instructions after the interrupt, to have fewer delay slots than they actually have. For example, suppose that register A1 contains 0 and register A0 points to a memory location containing a value of 10 before reaching the code in Example 810. The ADD instruction, which is in a delay slot of the LDW, sums A2 with the value in A1 (0) and the result in A3 is just a copy of A2. If an interrupt occurred between the LDW and ADD, the LDW would complete the update of A1 (10), the interrupt would be processed, and the ADD would sum A1 (10) with A2 and place the result in A3 (equal to A2 + 10). Obviously, this situation produces incorrect results. In Example 811, the single assignment method is used. The register A1 is assigned only to the ADD input and not to the result of the LDW. Regardless of the value of A6 with or without an interrupt, A1 does not change before it is summed with A2. Result A3 is equal to A2.
Example 810. Code Without Single Assignment: Multiple Assignment of A1

LDW ADD NOP MPY .D1 .L1 .M1 *A0,A1 A1,A2,A3 3 A1,A4,A5
; uses new A1
Example 811. Code Using Single Assignment

LDW ADD NOP MPY .D1 .L1 .M1 *A0,A6 A1,A2,A3 3 A6,A4,A5 ; uses A6
Interrupts
8-25
8.6.2
Nested Interrupts
Generally, when the CPU enters an interrupt service routine, interrupts are disabled. However, when the interrupt service routine is for one of the maskable interrupts (INT4INT15), an NMI can interrupt processing of the maskable interrupt. In other words, an NMI can interrupt a maskable interrupt, but neither an NMI nor a maskable interrupt can interrupt an NMI. There may be times when you want to allow an interrupt service routine to be interrupted by another (particularly higher priority) interrupt. Even though the processor by default does not allow interrupt service routines to be interrupted unless the source is an NMI, it is possible to nest interrupts under software control. The process requires you to save the original IRP (or NRP) and IER to memory or registers (either registers not used, or registers saved if they are used by subsequent interrupts), and if you desire, to set up a new set of interrupt enables once the ISR is entered, and save the CSR. Then you could set the GIE bit, which would reenable interrupts inside the interrupt service routine.
8.6.3
Manual Interrupt Processing

You can poll the IFR and IER to detect interrupts manually and then branch to the value held in the ISTP as shown below in Example 812. The code sequence begins by copying the address of the highest priority interrupt from the ISTP to the register B2. The next instruction extracts the number of the interrupt, which is used later to clear the interrupt. The branch to the interrupt service routine comes next with a parallel instruction to set up the ICR word. The last five instructions fill the delay slots of the branch. First, the 32-bit return address is stored in the B2 register and then copied to the interrupt return pointer (IRP). Finally, the number of the highest priority interrupt, stored in B1, is used to shift the ICR word in B1 to clear the interrupt.
Example 812. Manual Interrupt Processing

MVC EXTU [B1] B || [B1] MVK [B1] MVK [B1] MVKH [B1] MVC [B1] SHL [B1] MVC RET_ADR: ISTP,B2 ; get related ISFP address B2,23,27,B1 ; extract HPEINT B2 ; branch to interrupt 1,A0 ; setup ICR word RET_ADR,B2 ; create return address RET_ADR,B2 ; B2,IRP ; save return address A0,B1,B1 ; create ICR word B1,ICR ; clear interrupt flag (Post interrupt service routine Code)
8-26
8.6.4
Traps
A trap behaves like an interrupt, but is created and controlled with software. The trap condition can be stored in any one of the conditional registers: A1, A2, B0, B1, or B2. If the trap condition is valid, a branch to the trap handler routine processes the trap and the return. Example 813 and Example 814 show a trap call and the return code sequence, respectively. In the first code sequence, the address of the trap handler code is loaded into register B0 and the branch is called. In the delay slots of the branch, the context is saved in the B0 register, the GIE bit is cleared to disable maskable interrupts, and the return pointer is stored in the B1 register. If the trap handler were within the 21-bit offset for a branch using a displacement, the MVKH instructions could be eliminated, thus shortening the code sequence. The trap is processed with the code located at the address pointed to by the label TRAP_HANDLER. If the B0 or B1 registers are needed in the trap handler, their contents must be stored to memory and restored before returning. The code shown in Example 814 should be included at the end of the trap handler code to restore the context prior to the trap and return to the TRAP_RETURN address.
Example 813. Code Sequence to Invoke a Trap

[A1] MVK [A1] MVKH [A1] B [A1] MVC [A1] AND [A1] MVC [A1] MVK [A1] MVKH TRAP_RETURN:
Note:
TRAP_HANDLER,B0 TRAP_HANDLER,B0 B0 CSR,B0 -2,B0,B1 B1,CSR TRAP_RETURN,B1 TRAP_RETURN,B1 (post-trap code)
; load 32-bit trap address ; ; ; ; ; branch to trap handler read CSR disable interrupts: GIE = 0 write to CSR load 32-bit return address
A1 contains the trap condition.
Example 814. Code Sequence for Trap Return

B MVC NOP B1 B0,CSR 4 ; return ; restore CSR ; delay slots
Interrupts
8-27
Appendix A Appendix A
Glossary
A
address: The location of a word in memory. addressing mode: The method by which an instruction calculates the location of an object in memory. ALU: arithmetic logic unit. The part of the CPU that performs arithmetic and logic operations. annul: To cause an instruction to not complete its execution.
B
bootloader: A built-in segment of code that transfers code from an external source to program memory at power-up.
C
clock cycles: Cycles based on the input from the external clock. code: A set of instructions written to perform a task; a computer program or part of a program. CPU cycle: The period during which a particular execute packet is in a particular pipeline stage. CPU cycle boundaries always occur on clock cycle boundaries; however, memory stalls can cause CPU cycles to extend over multiple clock cycles.
D
data memory: A memory region used for storing and manipulating data. delay slot: A CPU cycle that occurs after the first execution phase (E1) of an instruction in which results from the instruction are not available.
A-1
Glossary
E
execute packet (EP): A block of instructions that execute in parallel. external interrupt: A hardware interrupt triggered by a specific value on a pin.
F
fetch packet (FP): A block of program data containing up to eight instructions.
G
global interrupt enable (GIE): A bit in the control status register (CSR) used to enable or disable maskable interrupts.
H
hardware interrupt: An interrupt triggered through physical connections with on-chip peripherals or external devices.
I
interrupt: A condition causing program flow to be redirected to a location in the interrupt service table (IST). interrupt service fetch packet (ISFP): See also fetch packet (FP). A fetch packet used to service interrupts. If eight instructions are insufficient, the user must branch out of this block for additional interrupt service. If the delay slots of the branch do not reside within the ISFP, execution continues from execute packets in the next fetch packet (the next ISFP). interrupt service table (IST): Sixteen contiguous ISFPs, each corresponding to a condition in the interrupt flag register (IFR). The IST resides in memory accessible by the program memory system. The IST must be aligned on a 256-word boundary (32 fetch packets 8 words/fetch packet). Although only 16 interrupts are defined, space in the IST is reserved for 32 for future expansion. The ISTs location is determined by the interrupt service table pointer (ISTP) register.
A-2
Glossary
L
latency: The delay between when a condition occurs and when the device reacts to the condition. Also, in a pipeline, the necessary delay between the execution of two instructions to ensure that the values used by the second instruction are correct. LSB: least significant bit. The lowest-order bit in a word.
M
maskable interrupt: A hardware interrupt that can be enabled or disabled through software. memory stall: When the CPU is waiting for a memory load or store to finish. MSB: most significant bit. The highest-order bit in a word.
N
nested interrupt: A higher-priority interrupt that must be serviced before completion of the current interrupt service routine. nonmaskable interrupt: An interrupt that can be neither masked nor manually disabled.
O
overflow: A condition in which the result of an arithmetic operation exceeds the capacity of the register used to hold that result.
P
pipeline: A method of executing instructions in an assembly-line fashion. program memory: A memory region used for storing and executing programs.
R
register: A group of bits used for holding data or for controlling or specifying the status of a device. reset: A means of bringing the CPU to a known state by setting the registers and control bits to predetermined values and signaling execution to start at a specified address.
Glossary
A-3
Glossary
S
shifter: A hardware unit that shifts bits in a word to the left or to the right. sign extension: An operation that fills the high order bits of a number with the sign bit.
W
wait state: A period of time that the CPU must wait for external program, data, or I/O memory to respond when reading from or writing to that external memory. The CPU waits one extra cycle for every wait state.
Z
zero fill: A method of filling the low- or high-order bits with zeros when loading a 16-bit number into a 32-bit field.
A-4
Index
Index
[ ] in code 3-16 || in code 3-15 1X and 2X cross paths. See cross paths 1X and 2X paths. See crosspaths 40-bit data conflicts 3-18 40-bit data 2-6 to 2-8 8-bank interleaved memory 7-58 8-bank interleaved memory with two memory spaces 7-59 address A-1 address generation for load/store 3-23 address paths 2-12 addressing mode circular mode 3-21 definition A-1 linear mode 3-21 addressing mode register (AMR) 2-13, 2-14 field encoding table 2-15 figure 2-15 Addressing modes 5-18 ADDSP instruction 4-25 to 4-28 ADDU instruction 3-30 to 3-34 AMR. See addressing mode register (AMR) AND instruction 5-35 AND instruction 3-38 to 3-40 ANDN instruction 5-38 architecture 1-7 assembler conflict detectability for writes 3-20 AVG2 instruction 5-40 AVGU4 instruction 5-42
A
ABS instruction 3-28 ABS2 instruction 5-23 ABSDP instruction 4-16 to 4-18 ABSSP instruction 4-18 to 4-20 ADD instruction 3-30 to 3-34, 8-25 add instructions using circular addressing 3-22 using linear addressing 3-21 ADD2 instruction 5-25 ADD2 instruction 3-37 ADD4 instruction 5-28 ADDAB instruction 3-22, 3-34 to 3-36 ADDAD instruction 4-20 to 4-22, 5-31 to 5-33 ADDAH instruction 3-22, 3-34 to 3-36 ADDAW instruction 3-22, 3-34 to 3-36 ADDDP instruction 4-22 to 4-25 ADDDP instruction .L-unit instruction hazards 7-33 execution 7-49 figure of phases 7-49 pipeline operation 7-49 ADDK instruction 3-36 ADDKPC instruction 5-33
B
B instruction using a displacement 3-40 to 3-42 using a register 3-42 to 3-44 B IRP instruction 3-44 to 3-46, 8-6, 8-12, 8-17 B NRP instruction 3-46 to 3-48, 8-13, 8-16 base + index addressing syntax 3-23 BDEC instruction 5-44 BITC4 instruction 5-47 BITR instruction 5-49 block size calculations 2-16 BNOP instruction 5-51, 5-54
Index-1
Index
BPOS instruction 5-57 branch instruction .S-unit instruction hazards 7-24 execution block diagram 6-19, 7-45 figure of phases 6-19, 7-44 pipeline operation 6-19, 7-44 using a displacement 3-40 to 3-42 using a register 3-42 to 3-44 branching and multicycle NOPs 6-23, 7-55 performance considerations 8-24 to additional interrupt service routine 8-6 to the middle of an execute packet 3-15
conditional registers conflict detectability
3-16, 5-12, 5-16 3-20 4-12 to 4-15
constraints on floating-point instructions
C
circular addressing block size calculations 2-16 block size specification 3-21 registers that perform 2-14 clearing an individual interrupt 8-14 interrupts 8-14 clock cycle 6-11, 7-11 CLR instruction 3-48 to 3-51 CMPEQ instruction 3-51 to 3-53 CMPEQ2 instruction 5-59 CMPEQ4 instruction 5-62 CMPEQDP instruction 4-28 to 4-31 CMPEQSP instruction 4-31 to 4-34 CMPGT instruction 3-53 to 3-57 CMPGT2 instruction 5-66 CMPGTDP instruction 4-34 to 4-37 CMPGTSP instruction 4-37 to 4-40 CMPGTU instruction 3-53 to 3-57 CMPGTU4 instruction 5-69 CMPLT instruction 3-57 to 3-61 CMPLT2 instruction 5-73 CMPLTDP instruction 4-40 to 4-43 CMPLTSP instruction 4-43 to 4-46 CMPLTU instruction 3-57 to 3-61 CMPLTU4 instruction 5-75 code definition A-1 conditional operations 3-16, 5-12 Index-2
contraints on crosspaths 3-17 on floatin-point instructions 7-16 to 7-19 on general-purpose registers 3-19 to 3-21 on instructions using the same functional unit 3-17 on LDDW instruction 4-14 on loads and stores 3-18 on long data 3-18 on register reads 3-19 on resources 3-17, 5-13 control individual interrupts of interrupts 8-11 8-13
control register file extension (C67x) 2-20 interrupt 8-10 list of 2-13 register addresses for accessing control status register (CSR) 8-10 description 2-13, 2-18 figure 2-17, 8-11 interrupt control fields 8-11 CPU control register file 2-13 cycle 6-11, 6-14, 7-11, 7-16 data paths TMS320C62x 2-2 TMS320C64x 2-4 TMS320C67x 2-3 functional units 2-7 general-purpose register files 2-5 introduction 1-8 load and store paths 2-11 TMS320C62x block diagram 6-5 TMS320C67x block diagram 7-5 CPU data paths relationship to register files TMS320C62x 2-2 TMS320C64x 2-4 TMS320C67x 2-3 CPU ID field (CSR) cross paths 2-18 3-16 creg opcode field defined 2-10, 3-17 2-10
3-89
Index
CSR. See control status register (CSR)
DOTPRSU2 instruction DOTPRUS2 instruction DOTPSU4 instruction DOTPU4 instruction DOTPUS4 instruction
5-92 5-95 5-97
D
.D functional unit load hazard 7-34 store hazard 7-35 LDDW instruction with long write hazard 7-37 single-cycle 7-36 .D functional units 2-9 .D unit hazards LDDW instruction with long write instruction 7-37 load instruction 7-34 single-cycle instruction 7-36 store instruction 7-35 DA1 and DA2. See data address paths data address paths 2-12 data address pointer 6-17, 6-18, 7-42 data format (IEEE standard) 4-6 data load accesses versus program memory accesses 6-24, 7-56 data storage format 40-bit 2-6 DC pipeline phase 6-4, 7-4 DCC field (CSR) 2-18 Deal instruction 5-78 decode pipeline stage 6-4, 7-4 decoding instructions 6-4, 7-4 delay slots description 5-11, 6-14, 7-16 fixed-point instructions 3-12 floating-point instructions 4-11 stores 6-18, 7-43 DEN1,DEN2 fields FADCR 2-20 to 2-22 FAUCR 2-22 to 2-24 FMCR 2-24 to 2-26 detection of interrupts 8-18 disabling an individual interrupt 8-14 disabling maskable interrupts globally 8-12 DIV0 fields (FAUCR) 2-22 to 2-24 DOTP2 instruction 5-80 DOTPN2 instruction 5-84 DOTPNRSU2 instruction 5-87
5-102 5-100 4-6 7-22
double-precision data format DP compare instructions .S-unit instruction hazards execution 7-48 figure of phases 7-48 pipeline operation 7-48 DP pipeline phase DPINT instruction DPSP instruction
6-4, 6-21, 7-4, 7-53 4-46 to 4-48 4-48 to 4-51 4-51 to 4-53
DPTRUNC instruction
E
E1 phase program counter (PCE1) E1E5 (or E10) pipeline phases E1E5 pipeline phases Empty 5-90 2-18 8-14 8-12 EN field (CSR) 6-5 2-19 7-5
enabling an individual interrupt
enabling maskable interrupts globally execute packet multicycle NOPs in 6-22, 7-54 parallel operations 3-13 performance considerations (C67x) pipeline operation 6-20 execute phases of the pipeline figure 6-5, 7-5
7-52
6-24, 7-56
execution notations fixed-point instructions 3-2 fixed-point instructions 5-2 floating-point instructions 4-2 execution table ADDDP/SUBDP INTDP 7-48 MPYDP 7-51 MPYI 7-50 MPYID 7-50 EXT instruction EXTU instruction 7-49
3-61 to 3-64 3-64 to 3-67
Index-3
Index
F
FADCR. See floating-point adder configuration register (FADCR) FAUCR. See floating-point auxiliary configuration register (FAUCR) fetch packet (FP) 3-13, 6-20, 7-52, 8-6 6-24 6-2, 7-56 fetch phases of the pipeline fetch pipeline phase fetch pipline phase TMS320C62x 6-3 TMS320C67x 7-2, 7-3 fixed-point instruction set 5-139 flag interrupt 8-18, 8-22 floating-point instruction constraints floating-point instruction set 4-12 4-1 to 4-83 3-1 to 3-139, 5-1 to
G
general-purpose register files cross paths 2-10 data address paths 2-12 description 2-5 memory, load, and store paths 2-11 GIE bit 2-18, 8-4, 8-11, 8-19, 8-21 GMPY4 instruction 5-104
H
HPEINT bit 8-8
I
IACK signal 8-4, 8-21, 8-23 ICR. See interrupt clear register (ICR) IDLE instruction 3-67 IEEE standard formats 4-6 IEm bit 8-18 IER. See interrupt enable register (IER) IFm bits 8-21, 8-23 IFR. See interrupt flag register (IFR) individual interrupt control 8-13 INEX fields FADCR 2-20 to 2-22 FAUCR 2-22 to 2-24 FMCR 2-24 to 2-26 INFO fields FADCR 2-20 FAUCR 2-22 FMCR 2-24 instruction constraints 4-12 instruction descriptions fixed-point instruction set 3-24, 5-22 floating-point instruction set 4-15 constraints 4-12 instruction operation fixed-point notations for 3-2, 5-2 floating-point notations for 4-2 instruction to functional unit mapping 3-4, 4-4, 5-5 instruction types 2-cycle DP instructions 7-46 4-cycle instructions 7-47
floating-point adder configuration register (FADCR) 2-20 to 2-22 floating-point auxiliary configuration register (FAUCR) 2-20, 2-22 to 2-24 floating-point multiplier configuration register (FMCR) 2-20, 2-24 to 2-26 floating-point field definitions double-precision 4-9 single-precision 4-8 floating-point operands double precision 4-6 single precision 4-6 FMCR. See floating-point multiplier configuration register (FMCR) 4-cycle instructions .L-unit instruction hazards 7-31 .M-unit instruction hazards 7-26 execution 7-47 figure of phases 7-47 pipeline operation 7-47 Functional Unit Hazards 7-20 3-5, 4-4, 5-6 functional unit to instruction mapping functional units 2-7 constraints on instructions 3-17 fixed-point operations 2-8 list of 2-8 operations performed on 2-8 Index-4
Index
instruction types (continued) ADDDP instructions 7-49 ADDDP/SUBDP instructions 4-22 to 4-25, 4-84 branch instructions 6-19, 7-44 DP compare instructions 7-48 execution phases 6-13, 7-13 INTDP 4-53 to 4-55 INTDP instructions 7-47 load instructions 6-17, 7-42 MPYDP 4-60 to 4-62 MPYDP instructions 7-51 MPYI 4-62 MPYI instructions 7-50 MPYID 4-64 to 4-66 MPYID instructions 7-50 multiply instructions 6-14, 7-39 operation phases 7-7 pipeline execution 6-13, 7-13 single-cycle 6-14, 7-38 store instructions 6-15, 7-40 SUBDP instructions 7-49 INT4INT15 interrupt signals 8-4 INTDP instruction 4-53 to 4-55 execution 7-48 figure of phases 7-48 .L-unit instruction hazards 7-32 pipeline operation 7-47 INTDPU instruction 4-53 to 4-55 interleaved memory bank scheme 6-26, 7-58 4-bank memory 6-26, 6-27 8-bank memory single memory space 7-58 with two memory spaces 7-59 interrupt clear register (ICR) 2-13, 8-10, 8-14 figure 8-15 writing to 8-14 interrupt control 8-11 individual 8-13 interrupt control registers 8-10 interrupt detection and processing 8-18 to 8-23 actions taken during nonreset 8-21 actions taken during RESET 8-23 figure 8-22 interrupt enable register (IER) 2-13, 8-4, 8-10, 8-13 polling 8-26 interrupt flag setting 8-18, 8-22 interrupt flag register (IFR)
interrupt flag register (IFR) (continued) description 2-13, 8-10 figure 8-14 maskable interrupts 8-4 overview 8-2 polling 8-26 reading from 8-15 writing to 8-14 interrupt performance frequency 8-24 latency 8-24 overhead 8-24 interrupt pipeline interaction branching 8-24 code parallelism 8-24 memory stalls 8-24 multicycle NOPs 8-24 interrupt return pointer (IRP) 2-13, 8-10, 8-17, 8-26 interrupt service fetch packet (ISFP) 8-6 interrupt service table (IST) figure 8-5 relocation of 8-9 interrupt service table pointer (ISTP) 2-13, 8-21, 8-23, 8-26 description 8-10 description of fields 8-8 figure 8-8 overview 8-8 interrupt set register (ISR) 2-13, 8-10, 8-14 figure 8-15 interrupts branching 8-21, 8-23 clearing 8-14 control 8-13 to 8-17 detection 8-18 to 8-23 globally disabling 8-11 to 8-12 globally enabling 8-11 to 8-12 list of control registers 8-10 nesting 8-26 overview 8-2 to 8-10 performance considerations 8-24 priorities 8-3 processing 8-18 to 8-23 programming considerations 8-25 to 8-28 setting 8-14 signals used 8-2 traps 8-27 types of 8-2 INTSP instruction 4-55 to 4-57
Index-5
Index
INTSPU instruction
4-55 to 4-57 8-4, 8-21, 8-23
INUM3INUM0 signals INVAL fields FADCR 2-20 to 2-22 FAUCR 2-22 to 2-24 FMCR 2-24 to 2-26 invoking a trap 8-27
IRP. See interrupt return pointer (IRP) ISFP. See interrupt service fetch packet (ISFP) ISR. See interrupt set register (ISR) IST. See interrupt service table (IST) ISTB field 8-8, 8-9 ISTP. See interrupt service table pointer (ISTP)
L
.L functional units 2-8, 2-20 .L unit hazards ADDDP instruction 7-33 4-cycle .L-unit instruction hazards INTDP instruction 7-32 single-cycle instruction 7-30 SUBDP instruction 7-33 latency fixed-point instructions 3-12 floating-point instructions 4-11 LDB instruction 15-bit constant offset 3-73 to 3-76 5-bit unsigned constant offset or register offset 3-68 to 3-73 using circular addressing 3-21 LDBU instruction 15-bit constant offset 3-73 to 3-76 5-bit unsigned constant offset or register offset 3-68 to 3-73 LDDW instruction 5-107 to 5-129 LDDW instruction 4-57 to 4-60 instruction with long write instruction hazards 7-37 LDH instruction 15-bit constant offset 3-73 to 3-76 5-bit unsigned constant offset or register offset 3-68 to 3-73 using circular addressing 3-21 Index-6
7-31
LDHU instruction 15-bit constant offset 3-73 to 3-76 5-bit unsigned constant offset or register offset 3-68 to 3-73 LDNW instruction 5-114 LDW instruction 8-25 15-bit constant offset 3-73 to 3-76 5-bit unsigned constant offset or register offset 3-68 to 3-73 using circular addressing 3-21 linear addressing mode 3-21 LMBD instruction 3-76 to 3-78 load address generation syntax 3-23 load and store paths CPU 2-11 load from memory banks example 6-26, 7-58 load instructions conflicts 3-18 .D-unit instruction hazards 7-34 execution block diagram 6-17, 6-18, 7-43 figure of phases 7-42 phases 6-17 pipeline operation 6-17, 7-42 syntax for indirect addressing 3-23 types 6-17 using circular addressing 3-21 using linear addressing 3-21 load or store to the same memory location rules 6-16, 7-41 load paths 2-11 loads and memory banks 6-26, 7-58 long (40-bit) data 3-18 register pairs 2-6 to 2-8
M
.M functional units 2-9, 2-20 .M unit hazards 4-cycle instruction 7-26 MPYDP instruction 7-29 MPYI instruction 7-27 MPYID instruction hazards 7-28 multiply instruction 7-25 mapping functional unit to instruction 3-5, 4-4, 5-6 instruction to functional unit 3-4, 4-4, 5-5
Index
maskable interrupt description 8-4 return from 8-17 MAX2 instruction 5-118 MAXU4 instruction 5-121 memory considerations 6-24 internal 1-8 paths 2-11 pipeline phases used during access 6-24, 7-56 stalls 6-25, 7-57 memory bank hits 6-26, 7-58 memory paths 2-11 memory stalls 6-25, 7-57 million instructions per second (MIPS) 1-4 MIN2 instruction 5-124 MINU4 instruction 5-127 MPY instruction 3-78 to 3-81 MPY2 instruction 5-130 MPYDP instruction 4-60 to 4-62 .M-unit instruction hazards 7-29 execution 7-51 figure of phases 7-51 pipeline operation 7-51 MPYH instruction 3-81 to 3-83 MPYHI instruction 5-133 MPYHIR instruction 5-136 MPYHL instruction 3-83 to 3-85 MPYHLU instruction 3-83 to 3-85 MPYHSLU instruction 3-83 to 3-85 MPYHSU instruction 3-81 to 3-83 MPYHU instruction 3-81 to 3-83 MPYHULS instruction 3-83 to 3-85 MPYHUS instruction 3-81 to 3-83 MPYI instruction 4-62 to 4-64 .M-unit instruction hazards 7-27 execution 7-50 figure of phases 7-50 pipeline operation 7-50 MPYID instruction 4-64 to 4-66 .M-unit instruction hazards 7-28 execution 7-50 figure of phases 7-51 pipeline operation 7-50 MPYIH pseudo operation 5-138 MPYIHR pseudooperation 5-139
MPYIL pseudooperation 5-140 MPYILR pseudooperation 5-141 MPYLH instruction 3-85 to 3-87 MPYLHU instruction 3-85 to 3-87 MPYLI instruction 5-142 MPYLIR instruction 5-144 MPYLSHU instruction 3-85 to 3-87 MPYLUHS instruction 3-85 to 3-87 MPYSP instruction 4-66 to 4-68 MPYSU instruction 3-78 to 3-81 MPYSU4 instruction 5-146 MPYU instruction 3-78 to 3-81 MPYU4 instruction 5-151 MPYUS instruction 3-78 to 3-81 MPYUS4 pseudooperation 5-149 multicycle NOPs 6-22, 7-54 in execute packets 6-22, 7-54 multiply execution execution block diagram 6-15 multiply instructions .M-unit instruction hazards 7-25 execution 7-39 execution block diagram 7-39 figure of phases 6-14, 7-39 pipeline operation 6-14, 7-39 MV instruction 3-87 MVC instruction 3-88 to 3-91, 8-18 writing to IFR or ICR 8-14 MVD instruction 5-154 MVK instruction 5-156 MVK instruction 3-91 to 3-93, 3-95 to 3-97 MVKH instruction 3-93 to 3-95 MVKLH instruction 3-93 to 3-95
N
NEG instruction 3-97 nesting interrupts 8-26 NMI. See nonmaskable interrupt (NMI) NMIE bit 8-4, 8-13, 8-19 nonmaskable interrupt (NMI) 8-3, 8-21, 8-26 return from 8-16 nonmaskable interrupt return pointer (NRP) 2-13, 8-10, 8-16 figure 8-16 NOP instruction 3-98 to 3-100, 6-4, 7-4, 8-6 NORM instruction 3-100 to 3-102
Index-7
Index
NOT instruction 3-102 notations for fixed-point instructions 3-2 to 3-3, 5-2 to 5-4 for floating-point instructions 4-2 NRP. See nonmaskable interrupt return pointer (NRP)
O
opcode map 3-9 figure 3-10 to 3-11 symbols and meanings 3-9, 5-10 operands examples 3-25 OR instruction 5-159 OR instruction 3-103 to 3-105 overview TMS320 family 1-2
P
p-bit 3-13 PACK2 instruction 5-162 PACKH2 instruction 5-165 PACKH4 instruction 5-168 PACKHL2 instruction 5-171 PACKL4 instruction 5-174 PACKLH2 instruction 5-177 parallel code example 3-15 parallel fetch packets 3-14 parallel operations 3-13 partially serial fetch packets 3-15 PCC field (CSR) 2-18 PCE1. See program counter (PCE1) performance considerations pipeline 6-20, 7-52 PG pipeline phase 6-2, 7-2 PGIE bit 2-18, 8-11, 8-21 pipeline decode stage 6-2, 6-4, 7-2, 7-4 execute stage 6-2, 6-5, 7-2, 7-5 execution 6-14, 7-13 factors that provide programming flexibility 7-1 Index-8
6-1,
pipeline (continued) fetch stage 6-2, 7-2 operation overview 6-2, 7-2 performance considerations 6-21, 7-52 phases 6-2, 6-6, 7-2, 7-6 stages 6-2, 7-2 pipeline execution 6-12, 7-13 pipeline operation 2-cycle DP instructions 7-46 4-cycle instructions 7-47 ADDDP instructions 7-49 branch instructions 6-20, 7-44 description 6-7 to 6-13, 7-6 to 7-12 DP compare instructions 7-48 fetch packets with different numbers of execute packets 6-21, 7-53 INTDP instructions 7-47 load instructions 6-18, 7-42 MPYDP instructions 7-51 MPYI instructions 7-50 MPYID instructions 7-50 multiple execute packets in a fetch packet 6-21, 7-52 multiply instructions 6-15, 7-39 one execute packet per fetch packet 6-7, 7-6 single-cycle instructions 6-15, 7-38 store instructions 6-15, 7-40 SUBDP instructions 7-49 pipeline phases functional block diagram 6-10, 6-11, 7-10 operations occurring during 6-8 used during memory accesses 6-25, 7-56 PR pipeline phase 6-2, 7-2 program access ready wait. See PW pipeline phase program address generate. See PG pipeline phase program address send. See PS pipeline phase program counter (PCE1) 2-13, 2-19, 3-40 figure 2-19 program fetch counter (PFC) 3-40 program fetch packet receive. See PR pipeline phase program memory accesses versus data load accesses 6-24, 7-56 PS pipeline phase 6-2, 7-2 push definition A-3 PW pipeline phase 6-2, 7-2 PWRD field (CSR) 2-18
Index
R
RCPDP instruction 4-68 to 4-70 RCPSP instruction 4-70 to 4-72 register files cross paths 2-10 data address paths 2-12 general-purpose 2-5 memory, load, and store paths 2-11 relationship to data paths 2-10 register storage scheme 40-bit data figure 2-6 registers AMR. See addressing mode register (AMR) CSR. See control status register (CSR) FADCR. See floating-point adder configuration register (FADCR) FAUCR. See floating-point auxiliary configuration register (FAUCR) FMCR. See floating-point multiplier configuration register (FMCR) ICR. See interrupt clear register (ICR) IER. See interrupt enable register (IER) IFR. See interrupt flag register (IFR) IRP. See interrupt return pointer (IRP) ISR. See interrupt set register (ISR) ISTP. See interrupt service table pointer (ISTP) NRP. See nonmaskable interrupt return pointer (NRP) PCE1. See program counter (PCE1) read constraints 3-19 write constraints 3-19 relocation of the interrupt service table (IST) 8-9 reset interrupt 8-3 RESET signal as an interrupt 8-3 CPU state after 8-16 resource constraints 3-17, 5-13 using the same functional unit 3-17 returning from a trap 8-27 returning from interrupt servicing 8-16 returning from maskable interrupt 8-17 returning from NMI 8-16 ROTL instruction 5-180 RSQRDP instruction 4-72 to 4-75 RSQRSP instruction 4-75 to 4-78
S
.S functional units 2-8 .S unit hazards 2-cycle DP instruction 7-23 branch instruction 7-24 DP compare instruction 7-22 single-cycle instruction 7-21 SADD instruction 3-105 to 3-108 SADD2 instruction 5-182 SADDSU2 pseudooperation 5-188 SADDU4 instruction 5-185 SADDUS2 instruction 5-190 SAT field (CSR) 2-18 SAT instruction 3-108 to 3-110 serial fetch packets 3-14 SET instruction 3-110 to 3-113 setting an individual interrupt example 8-15 setting interrupts 8-14 setting the interrupt flag 8-18, 8-22 SHFL instruction 5-193 SHL instruction 3-113 to 3-115 SHLMB instruction 5-196 SHR instruction 3-115 to 3-117 SHR2 instruction 5-199 SHRMB instruction 5-202 SHRU instruction 3-117 to 3-119 SHRU2 instruction 5-205 single-cycle instructions .L-unit instruction hazards 7-30 .S-unit instruction hazards 7-21 .D-unit instruction hazards 7-36 execution 7-38 execution block diagram 7-38 figure of phases 7-38 pipeline operation 7-38 single-cycle instructions execution block diagram 6-14 figure of phases 6-14 pipeline operation 6-14 SMPY instruction 3-119 to 3-122 SMPY2 instruction 5-208 SMPYH instruction 3-119 to 3-122 SMPYHL instruction 3-119 to 3-122 SMPYLH instruction 3-119 to 3-122
Index-9
Index
SPACK2 instruction 5-212 SPACKU4 instruction 5-215 SPDP instruction 4-78 to 4-80 SPINT instruction 4-80 to 4-82 SPTRUNC instruction 4-82 to 4-84 SSHL instruction 3-122 to 3-124 SSHVL instruction 5-218 SSHVR instruction 5-221 SSUB instruction 3-124 STB instruction 15-bit offset 3-130 to 3-132 register offset or 5-bit unsigned constant offset 3-126 to 3-130 using circular addressing 3-21 STDW instruction 5-225 STH instruction 15-bit offset 3-130 to 3-132 register offset or 5-bit unsigned constant offset 3-126 to 3-130 using circular addressing 3-21 STNDW instruction 5-229 STNW instruction 5-233 store address generation syntax 3-23 store instructions conflicts 3-18 .D-unit instruction hazards 7-35 execution block diagram 6-16, 7-41 figure of phases 6-15, 7-40 pipeline operation 6-15, 7-40 syntax for indirect addressing 3-23 using circular addressing 3-21 using linear addressing 3-21 store or load to the same memory location rules 6-16, 7-41 store paths 2-11 STW instruction 15-bit offset 3-130 to 3-132 register offset or 5-bit unsigned constant offset 3-126 to 3-130 using circular addressing 3-21 SUB instruction 3-132 to 3-135 SUB2 instruction 5-237 SUB2 instruction 3-139 SUB4 instruction 5-240 SUBAB instruction 3-22, 3-135 to 3-137 Index-10
SUBABS4 instruction 5-242 SUBAH instruction 3-22, 3-135 to 3-137 SUBAW instruction 3-22, 3-135 to 3-137 SUBC instruction 3-137 to 3-139 SUBDP instruction 4-84 to 4-87 .L-unit instruction hazards 7-33 execution 7-49 figure of phases 7-49 pipeline operation 7-49 SUBSP instruction 4-87 to 4-89 subtract instructions using circular addressing 3-22 using linear addressing 3-21 SUBU instruction 3-132 to 3-135 SWAP2 instruction 5-245 SWAP4 instruction 5-247
T
TMS320 family advantages 1-2 applications 1-2 to 1-3 history 1-2 overview 1-2 TMS320C62x devices architecture 1-7 to 1-10 block diagram 1-7 features 1-5 options 1-5 to 1-6 performance 1-4 TMS320C67x devices architecture 1-7 to 1-10 block diagram 1-7 features 1-5 options 1-5 to 1-6 performance 1-4 traps 8-27 2-cycle DP instructions .S-unit instruction hazards figure of phases 7-46 pipeline operation 7-46
7-23
U
UNPKHU4 instruction 5-249 UNPKLU4 instruction 5-251
Index
V
VelociTI architecture 1-1 VLIW (very long instruction word) architecture 1-1
XOR instruction
3-140 to 3-142 5-257 5-260
XPND2 instruction XPND4 instruction
X
XOR instruction 5-254
Z
ZERO instruction 3-142
Index-11

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TMS320C6000 CPU and Instruction Set Reference Guide

Literature Number: SPRU189F October 2000

Printed on Recycled Paper

Copyright 2000, Texas Instruments Incorporated

Read This First

How to Use This Manual

How to Use This Manual How to Use This Manual

The following table gives chapter references for specific information:

Control registers CPU architecture and data paths Delay slots

General-purpose register files Instruction set

Interrupts and control registers

Pipeline phases and operation

Chapter 6, TMS320C62x/C64x Pipeline Chapter 7, TMS320C67x Pipeline

Here is a sample program listing:

- To help you easily recognize instructions and parameters throughout the

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least significant bit.

Related Documentation From Texas Instruments

Related Documentation From Texas Instruments

Read This First

1.2 1.3 1.4

84 85 86 87 88 89 810 811 812 813 814

TMS320 Family Overview

1.1 TMS320 Family Overview

History of TMS320 DSPs

Typical Applications for the TMS320 Family

TMS320 Family Overview

Table 11. Typical Applications for the TMS320 DSPs

Industrial Numeric control Power-line monitoring Robotics Security access

Overview of the TMS320C6x Generation of Digital Signal Processors

1.2 Overview of the TMS320C6x Generation of Digital Signal Processors

Features and Options of the TMS320C62x/C64x/C67x

1.3 Features and Options of the TMS320C62x/C64x/C67x

and six arithmetic units

- Conditional execution of all instructions J J J J

- Efficient code execution on independent functional units

- 8/16/32-bit data support, providing efficient memory support for a variety

putationally intensive applications

Features and Options of the TMS320C62x/C64x/C67x

- Saturation and normalization provide support for key arithmetic opera-

(64-bit) IEEE floating-point operations

The C64x additional features include:

common operations in error-correcting codes.

1.4 TMS320C62x/C64x/C67x Architecture

Figure 11. TMS320C62x/C64x/C67x Block Diagram

Instruction dispatch (See Note) Instruction decode

Additional peripherals: Timers, serial ports, etc.

Data cache/data memory 32-bit address

8-, 16-, 32-bit data (64-bit data, C64x only)

Central Processing Unit (CPU)

Memory and Peripheral Options

for these functions:

- Power-down logic allows reduced clocking to reduce power consumption.

CPU Data Paths and Control

CPU Data Paths and Control

Figure 21. TMS320C62x CPU Data Paths

long src long dst dst .S1 src1

long src long dst dst .L2 src2

src1 dst long dst long src

dst long dst long src