Computer

Architecture
MIPS Architecture Part I: Instruction
Set

Prof. Roger Luis Uy

De La Salle University
College of Computer Studies
 The MIPS Architecture

MIPS – Microprocessor without Interlocked

Pipeline Stages
 Reduced Instruction Set Computer (RISC)
developed by MIPS technologies
 MIPS32 (32-bit) & MIPS64 (64-bit)

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture
The architecture was developed based from the
following observations:
 Use general purpose register with a load-store
architecture
 Addressing modes: displacement (12/16 bits),
immediate (8/16 bits), register indirect
 Simple instructions: load, store, add, subtract,
move register-register, shift, compare equal,
compare not equal, compare less, conditional
branch, jump, call and return

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture
The architecture was developed based from the
following observations:
 Data types and sizes: 8/16/32/64-bit integers and
64-bit IEEE 754 Floating-point numbers
 Use fixed encoding
 Provide at least 16 GPR & separate FPR,
orthogonality for all data transfer instructions and
minimal instruction set

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Registers
 32* 64-bit GPRs (R0, R1, …, R31)
 32*64-bit Double Precision FPR (F0,F1, …, F31)
or 32*32-bit Single Precision FPR (the lower half
of the FPR is unused or can be viewed 2* 32-bit
Single Precision operands known as paired-
single)
 The value of R0 is always 0
 R0 can be used as a destination operand if the
result of the executed instruction will not be
needed

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Registers
 Register are sometimes used with $ instead
(i.e., $1, $2, …, $31)($f0, $f1, $f31)
 Registers are also given conventional
names with its specific function

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Registers
Reg # Name Use for
0 zero Always return 0
1 at (assembly temporary) Reserved for use by
assembly
2-3 v0, v1 Value returned by subroutine
4-7 a0-a3 (arguments) First few parameters for a
subroutine
8-15, t0-t7, (temporaries) Subroutines can use w/o saving
24-25 t8-t9
16-23 s0-s7 Subroutine register variables. Subroutine
should preserved the value of these registers
Course Notes on Computer Architecture
Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Registers
Reg # Name Use for
26, 27 k0, k1 Reserved for use by interrupt/trap handler
28 gp Global pointer; some runtime systems
maintain this to give easy access to (some)
static or extern variables
29 sp Stack pointer
30 s8/fp Ninth register variable; subroutines that need
one can use this as a frame pointer
31 ra Return address for subroutine

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Special Registers
Special registers:
– Program counter (PC)
• Contains the address of the instruction currently being retrieved
from memory for execution
– hi & lo
• Use in integer multiplication. Multiplying 2 register-sized values
produce a twice-register-sized result. Result is placed in special
register hi & lo
• Use in integer division. register lo stores the quotient and register hi
stores the remainder
– CPU status register (c0)
– Floating-point status register (c1)
• Used to hold information about the results of floating-point
operations

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Data Types
 Integer
– 8-bit bytes
– 16-bit half words
– 32-bit words
– 64-bit double words
 Floating Point
– 32-bit Single Precision
– 64-bit Double Precision
 Note: MIPS operates on 64-bit integers. Bytes, half
words and words are loaded into registers with either
zeros or the sign-bit replicated to fill the register
Course Notes on Computer Architecture
Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Addressing Mode
 Immediate (16-bit)
 Displacement (16-bit) i.e.,1000(R2)
 (Indirectly) Register Indirect - by placing
0 to the displacement field i.e., 0000(R2)
 (Indirectly) Absolute - using Register 0 as
the base register i.e., 1000(R0)

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Memory Model
 Byte Addressable
 Supports both big and little Endian mode
 Bit convention use:
b0 b1 b2 b3 b4 … … … b62 b63

 All memory accesses are aligned

 All memory references are through load and
stores only
Course Notes on Computer Architecture
Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Sets
 MIPS instruction set is categorized into 4
broad classes of instructions:
– Load and store instructions
– Arithmetic and logical instructions
– Floating-point instructions
– Jump and branch instructions

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Load/Store)
 LB, LBU, SB – Load byte, load byte unsigned,
store byte
 LH, LHU, SH – Load half word, load half word
unsigned, store half word
 LW, LWU, SW – Load word, store word
 LD, SD – Load double word, store double word
 L.S, L.D, S.S, S.D – load SP float, load DP float,
store SP float, store DP float
– format: L* rd, offset(rs) ; rd  Mem[offset+(rs)]
– format: S* rt, offset(rs) ; Mem[offset+(rs)]  rt
Course Notes on Computer Architecture
Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Load/Store)
LD R1, 30(R2) Regs[R1] 64 Mem[30+Regs[R2]]
LW R1, 60(R2) Regs[R1] 64 Mem[[60+Regs[R2]]0]32 ##
Mem[60+Regs[R2]]
LH R1, 40(R3) Regs[R1] 64 Mem[[40+Regs[R3]]0]48 ##
Mem[40+Regs[R3]] ## Mem[41+Regs[R3]]

LB R1, 40(R3) Regs[R1] 64 Mem[[40+Regs[R3]]0]56 ##

Mem[40+Regs[R3]]

LBU R1, 40(R3) Regs[R1] 64 056 ## Mem[40+Regs[R3]]

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Load/Store)
SD R3, 500(R4) Mem[500+Regs[R4]] 64 Regs[R3]
SW R3, 500(R4) Mem[500+Regs[R4]] 32 Regs[R3]32..63
SH R3, 502(R2) Mem[502+Regs[R2]] 16 Regs[R3]48..63
SB R3, 41(R3) Mem[41+Regs[R3]] 8 Regs[R3]56..63

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Load/Store)
L.S F0, 50(R3) Regs[F0] 64 Mem[50+Regs[R3]] ## 032
L.D F0, 50(R3) Regs[F0] 64 Mem[50+Regs[R3]]

S.S F0, 40(R3) Mem[40+Regs[R3]] 32 Regs[F0] 0..31

S.D F0, 40(R3) Mem[40+Regs[R3]] 64 Regs[F0]

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Load/Store)
 Move data between GPRs and memory (integer
load/store)
 Move data between FPRs and memory (floating-
point load/store)
 Memory addressing mode available is the
displacement mode (i.e., effective address is
obtained by adding a 16-bit signed offset to the
contents of one of the general-purpose registers)

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Load & Store)
 Integer loads maybe performed with any of the GPRs as
the destination register. Note loading to R0 has no effect
(i.e., result is discarded)
 Byte, half-word & word LOAD place the loaded byte,
half-word and word on the least significant portion of the
destination register
 The remaining portion of the destination register is filled
with either sign extension (LB/LH/LW) or „0‟
(LBU/LHU/LWU)

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Load & Store)
 Integer stores may use any of the GPRs as the
source of the data to be store
 Byte, half-word & word STORE (SB/SH/SW)
write the least significant portion of the contents
of the source register to memory at the effective
address

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Load & Store)
 Floating-point loads maybe performed with any
of the FPRs as the destination register
 Single Precision Floating-point STORE writes
the most significant portion of the contents of
the source register to memory at the effective
address

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Arithmetic)
 DADDU, DADDIU – Add, Add immediate (16-
bit, 2s complement)
– format: DADDU rd,rs,rt ; rd = rs + rt
– format: DADDIU rd,rs,imm ; rd = rs+imm
 DSUBU – Subtract
– format: DSUBU rd,rs,rt ; rd = rs – rt

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Arithmetic)
 The “U” in DADDU/DADDIU/DSUBU does not refer to
“unsigned”. The operation is a 64-bit modulo arithmetic
that does not trap on overflow. It is appropriate for
unsigned arithmetic such as address arithmetic, or integer
arithmetic environments that ignore overflow, such as C
language arithmetic.

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Arithmetic)
 DMULT, DMULTU – 64-bit integer
(signed/unsigned) multiply instruction,
result in hilo
– format: DMULT/DMULTU rs, rt ; hilo = rs*rt
 DDIV, DDIVU – 64-bit (signed/unsigned)
divide instruction, result in hi/lo
– format: DDIV/DDIVU rs, rt ; lo = rs/rt;
; hi = rs mod rt
Course Notes on Computer Architecture
Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Arithmetic)
 MADD – Integer multiply-accumulate,
result in hilo
– format: MADD rs,rt ; hilo = hilo + (rs*rt)

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Move)
 MFHI, MFLO – move multiplication / division
result (located in lo/hi) to GPR
– format: MFHI rd ; rd  hi
– format: MFLO rd ; rd  lo
• Example: MFHI R2 ; R2 hi
• Note:
• lo: (mul) the least significant result; (div) the quotient
• hi: (mul) the most significant result; (div) the
remainder

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Move)
 MTHI, MTLO – move contents of GPR to
lo/hi
– format: MTHI rs ; hi  rs
– format: MTLO rs ; lo  rs
• Example: MTHI R2 ; hi  R2

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Move)
 DMFC0 (64-bit), DMTC0 (64-bit), MFC0 (32-
bit), MTC0 (32-bit) – copy from/to GPR to/from
a C0 (C0: system control coprocessor)
– format: D/MFC0 rd, cs (move from CPU control
register cs into GPR rd)
• Example: MFC0 R1, $12 ; R1  $12
• CPU control register 12 is the status register (can be written
as MFC0 R1, SR)
– format: D/MTC0 rs, cd (move from GPR rs to CPU
control register cd)
• Example MTC0 R1, $12 ; $12  R1
• or MTCO R1, SR
Course Notes on Computer Architecture
Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Move)
 DMFC1, DMTC1 – copy 64 bits to/from
FP registers to/from integer registers
 C1: floating-point coprocessor
– format: DMFC1 rd, fs
• Example: DMFC1 R1, F1 ; R1 F1
– format: DMTC1 rs, fd
• Example: DMTC1 R1, F1 ; F1  R1

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Move)
 MOV.S, MOV.D – Copy one SP or DP FP
register to another FP register
– format: MOV.S fd, fs ; fd  fs (32-bit)
– format: MOV.D fd, fs ; fd fs (64-bit)
• Example: MOV.D F4, F2

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Logical)
 AND, ANDI - AND, AND immediate
 OR, ORI - OR, OR Immediate
 XOR, XORI - XOR, XOR Immediate
 NOR - NOR
– format: AND/OR/XOR/NOR rd, rs, rt
– format: ANDI/ORI/XORI rd, rs, imm
 Note: immediate is treated as unsigned
and therefore zero-extended
Course Notes on Computer Architecture
Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Logical)
 LUI – Load upper immediate - load bits 32
to 47 of register w/immediate, then sign
extends.
– format: LUI rd, imm
• Example: LUI R2, 1234 ; R2=0000000012340000
• Example: LUI R4, FF ; R4=0000000000FF0000
• Example: LUI R4, 8FFF ; R4=FFFFFFFF8FFF0000

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Sets
 Since MIPS architecture is a load-store
architecture, that means that load
immediate and register-register move are
not available. To circumvent:
– For register-register move: perform an
ADD/OR operation where one of the source
operand is R0 (i.e., DADDU R1, R0, R3) (OR
R1, R0, R3)

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Sets
 Since MIPS architecture is a load-store
architecture, that means that load immediate and
register-register move are not available. To
circumvent:
– For load immediate (16-bit, signed): add immediate
where one of the source operands is R0 (i.e.,
DADDIU R1, R0, #FFFF)
– For load immediate (16-bit, unsigned): use ORI where
one of the source operands is R0 (i.e., ORI R1, R0,
#FFFF)

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Sets
 Since MIPS architecture is a load-store
architecture, that means that load immediate and
register-register move are not available. To
circumvent:
– For load immediate (32-bit): use lui and ori
instructions
• Example LUI R4, #1234
ORI R4, R4, #5678
• R4 will be initialize with the value of 0000000012345678

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Sets
For load immediate (64-bit): use combination of lui, dsll
and ori instructions
• Example LUI R4, #1234
ORI R4, R4, #5678
DSLL R4, R4, #0010
ORI R4, R4, #9ABC
DSLL R4, R4, #0010
ORI R4, R4, #DEF0
• R4 will be initialize with the value of 123456789ABCDEF0

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Shift)
 DSLLV, DSLL – Shift left logical variable &
immediate
 DSRLV, DSRL – Shift right logical variable &
immediate
 DSRAV, DSRA – Shift right arithmetic variable
& immediate
– format: DSLLV/DSRLV/DSRAV rd, rs, rt
– Format DSLL/DSRL/DSRA rd, rs, imm

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Shift)
 The number of shift are specified by either the
value of the contents of a GPR
(DSLLV/DSRLV/DSRAV) or the value of
immediate value (DSLL/DSRL/DSRA)
 For the GPR, only the 6 low-order bits are
considered (treated as unsigned). Thus,
maximum shift amount is 63
 For the immediate value, the valid value is from
0 to 31 (00h to 1Fh) only.
Course Notes on Computer Architecture
Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Shift)
 Logical shift left or logical shift right shifts the
contents and place 0s into it.
 Arithmetic shift right shifts the contents to the
right and place the sign bits into it.

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Set-On-
Comparison)
 SLT, SLTU: Set Less Than (signed), Set Less
Than (unsigned)
 SLTI, SLTIU: Set Less Than Immediate (signed),
Set Less Than Immediate (unsigned)
– format: SLT/SLTU rd, rs, rt ; rd = rs < rt ?1 :0
– format: SLTI/SLTUI rd, rs, imm ; rd = rs< imm
?1:0

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Set-On-
Comparison)

 Set-on-comparison instructions set the

destination register to a value of 1 when the
comparison result is “true” and set the destination
register to a value of 0 when the comparison
result is “false”

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Set-On-
Comparison)
 SEQ, SGE, SGEU, SGT, SGTU, SLE, SLEU, SNE: need to be
simulated
 SEQ d,s,t  xor d,s,t / sltiu d,d,1
 SGE d,s,t  slt d,s,t / xori d,d, 1
 SGEU d,s,t  sltu d,s,t / xori d,d,1
 SGT d,s,t  slt d,t,s
 SGTU d,s,t  sltu d,t,s
 SLE d,s,t  slt d,t,s / xori d,d,1
 SLEU d,s,t  sltu d,t,s / xori d,d, 1
 SNE d,s,t  xor d,s,t
Course Notes on Computer Architecture
Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set
(Control/Integer)
 J – transfers control unconditionally to an absolute
address (26-bit). The address value (label) is left shifted
twice and replaced the lower 28-bit of the program
counter. Thus, the label is computed as target address
divided by 4
– format: J label
 JR – transfers control unconditionally to an address
specified in the register
– format: JR RS
 JAL, JALR – Jump and link: save PC+4* in R31, target is
an absolute address, (JAL) or a register (JALR)
– format: JAL label *if no branch delay slot else
– format: JALR RS PC+8
Course Notes on Computer Architecture
Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set
(Control/Integer)
 BLEZ, BLTZ, BGEZ, BGTZ – Branch if GPR <=, <, >, >= to 0,
signed 16-bit offset is shifted twice and added to PC. Thus, the offset
can also be viewed as the distance of instruction to a label. The next
instruction after the branch is viewed as offset 0
– format: BLEZ/BLTZ/BGEZ/BGTZ RS, label

 BEQ, BNE- Branch GPR equal/not equal; signed 16-bit offset is

shifted twice and added to PC
– format: BEQ/BNE RS, RT, label

 MOVN, MOVZ – Copy GPR to another GPR if third GPR is

negative/Zero
– format: MOVN RD, RS, RT ; (if RT <>0) RD = RS
– format: MOVZ RD, RS, RT ; (if RT=0) RD = RS
Course Notes on Computer Architecture
Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Control/Integer)
J name PC36..63  name
Internally, name (which is 26-bit) is shifted twice and then
replace the lower 28 bits of the PC. Thus, name can be viewed
as target address div 4
JAL name Regs[R31] PC+4*; PC36..63  name
*if delay slot branch is not used else PC+8
JALR R2 Regs[R31] PC+4*; PC Regs[R2]
*if delay slot branch is not used else PC+8
JR R3 PC  Regs[R3]

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Control/Integer)
BLEZ R4, name If (Regs[R4] <= 0) PC  PC + name
Internally, name (which is 16-bit signed offset) is shifted twice
and then added to the program counter. Thus, the offset can also
be viewed as the distance of instruction to a label. The next
instruction after the branch is viewed as offset 0
MOVZ R1, R2, R3 If (Regs[R3] == 0) Regs[R1]  Regs[R2]

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set
(Floating-Point Arithmetic)
 ADD.D, ADD.S, ADD.PS – Add DP, SP and pairs of SP numbers
 SUB.D, SUB.S, SUB.PS – Subtract DP, SP and pairs of SP numbers
 MUL.D, MUL.S, MUL.PS – Multiply DP, SP and pairs of SP
numbers
 DIV.D, DIV.S, DIV.PS – Divide DP, SP and pairs of SP numbers
 MADD.D, MADD.S, MADD.PS – Multiply-add DP, SP and pairs of
SP numbers
– format: mnemonic fd, fs, ft
• example: ADD.D F0, F2, F4 ; F0  F2+F4
– format: MADD.* fd, fr, fs,ft ; fd  fr+(fs*ft)
• example: MADD.S F0, F2, F4, F6 ; F0  F2+(F4*F6)

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set
(Floating-Point Conversion)
CVT.x.y –converts from type y to type x; where x
and y can be s (SP floating point), d (DP floating
point), w (32-bit integer) & l (64-bit integer).
Both operands are FPRs
– format: CVT.x.y fd, fs ; fd  fs
– Example: CVT.s.d f4, f2; f4 (SP FP)  f2 (DP FP)

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set
(Floating-Point Set-On-
Comparison)
 C._.S: Set conditional-On for single-precision
 C._.D: Set conditional-On for double-precision
 “_” = LT, GT, LE, GE, EQ, NE
 There are 8 FCC (Floating-point Condition Code)
that user can store the result. Default is FCC(0)
 FCC is stored in the Floating-point Status
Register (FCSR)

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set
(Floating-Point Set-On-
Comparison)
 All of these instructions set one of the FCC to 1
when the comparison result is “true” and set to 0
when the comparison result is “false”
 If the FCC is not stated, it defaults to FCC(0)
– format : mnemonic fs, ft
– Format: mnemonic cc, fs1, fs2
• example: C.LT.S F0, F2 ; FCC0 = F0 < F2 ? 1 : 0
• Example C.LT.S 7, F0, F2; FCC7 = F0<F2 ?1:0

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
FCSR Register Format

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Control/FP)
 BC1T, BC1F – Test FCC and branch,
signed 16-bit offset is shifted twice and
added to PC.
– format: BC1T/BC1F label
– Format: BC1T/BC1F cc, label

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS
 The MIPS Architecture –
Instruction Set (Special)
 TRAP – Transfer to operating system at a
vectored address
 ERET – Return to user code from an exception;
restore user mode
 NOP – No operation

Course Notes on Computer Architecture

Roger Luis Uy DLSU-CCS