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    3171111

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    feyayel988
    This document is an exam for a course on Testing and Verification. It contains 5 questions assessing various topics: 1. Definitions of manufacturing process yield, fault coverage, and fault detection efficiency. Differences between testing and verification. Determining single stuck-at faults and test vectors for a combinational logic circuit. 2. Requirements for fault modelling and transistor faults in a CMOS NOR gate. Explanations of Mux-D scan cell design and advantages/disadvantages. 3. Definitions of controllability and observability in the context of design for testability. Combinational testability analysis using necessary equations. Explanation of partial scan design and comparison to full scan design.

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    3171111

    Uploaded by

    feyayel988
    61 views2 pages
    This document is an exam for a course on Testing and Verification. It contains 5 questions assessing various topics: 1. Definitions of manufacturing process yield, fault coverage, and fault detection efficiency. Differences between testing and verification. Determining single stuck-at faults and test vectors for a combinational logic circuit. 2. Requirements for fault modelling and transistor faults in a CMOS NOR gate. Explanations of Mux-D scan cell design and advantages/disadvantages. 3. Definitions of controllability and observability in the context of design for testability. Combinational testability analysis using necessary equations. Explanation of partial scan design and comparison to full scan design.

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    This document is an exam for a course on Testing and Verification. It contains 5 questions assessing various topics: 1. Definitions of manufacturing process yield, fault coverage, and fault detection efficiency. Differences between testing and verification. Determining single stuck-at faults and test vectors for a combinational logic circuit. 2. Requirements for fault modelling and transistor faults in a CMOS NOR gate. Explanations of Mux-D scan cell design and advantages/disadvantages. 3. Definitions of controllability and observability in the context of design for testability. Combinational testability analysis using necessary equations. Explanation of partial scan design and comparison to full scan design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    61 views2 pages

    3171111

    Uploaded by

    feyayel988
    This document is an exam for a course on Testing and Verification. It contains 5 questions assessing various topics: 1. Definitions of manufacturing process yield, fault coverage, and fault detection efficiency. Differences between testing and verification. Determining single stuck-at faults and test vectors for a combinational logic circuit. 2. Requirements for fault modelling and transistor faults in a CMOS NOR gate. Explanations of Mux-D scan cell design and advantages/disadvantages. 3. Definitions of controllability and observability in the context of design for testability. Combinational testability analysis using necessary equations. Explanation of partial scan design and comparison to full scan design.

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    © All Rights Reserved
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    of 2

    Seat No.: ________ Enrolment No.

    ___________

    GUJARAT TECHNOLOGICAL UNIVERSITY


    BE - SEMESTER–VII (NEW) EXAMINATION – WINTER 2021
    Subject Code:3171111 Date:17/12/2021
    Subject Name:Testing and Verification
    Time:10:30 AM TO 01:00 PM Total Marks: 70
    Instructions:
    1. Attempt all questions.
    2. Make suitable assumptions wherever necessary.
    3. Figures to the right indicate full marks.
    4. Simple and non-programmable scientific calculators are allowed.

    MARKS
    Q.1 (a) Define (i) Manufacturing process yield, (ii) fault coverage and (iii) 03
    Fault detection efficiency
    (b) Differentiate following terms: Testing and Verification 04
    (c) Consider the combinational logic circuit in Figure. How many possible 07
    single stuck-at faults does this circuit have? How many collapsed single
    stuck at faults does this circuit have? Determine optimum input test
    vectors that can detect all single stuck-at faults.

    x1 a
    d
    x2 b g
    x3 i y
    e f h
    c

    Q.2 (a) What is Fault modelling and its requirement? 03


    (b) Discuss all the possible transistor faults in two-input CMOS NOR gate 04
    and the method of testing each of them.
    (c) What is Mux-D scan cell design? Explain in detail. Write advantages 07
    and disadvantages of Mux-D scan cell design. Draw level-sensitive
    muxed-D scan cell design.
    OR
    (c) Explain Muxed-D full scan design architecture in detail. 07
    Q.3 (a) Define the terms: (i) Controllability (ii) Observability in context of 03
    Design for Testability
    (b) Discuss combinational testability analysis by using necessary 04
    equations of controllability and observability of different logic
    gates.
    (c) Explain partial scan design. Mention merits and demerits of partial scan 07
    design compare to full scan design.
    OR
    Q.3 (a) Compare Muxed D , Cloked and LSSD scan cells 03
    (b) What is scan design rule for Derived clock design style and its 04
    recommended solution?
    (c) Draw and explain scan design flow. 07
    1
    Q.4 (a) Differentiate fault simulation and logic simulation. 03
    (b) Enlist Logic element evaluation methods. Draw input scanning 04
    algorithm. What is the value of controlling and inversion for the
    different logic gates?
    (c) Draw compile code simulation flow chart and explain all the steps of 07
    compile code simulation in detail.
    OR
    Q.4 (a) What is Functional Verification? 03
    (b) Enlist different approaches of functional verification and define all. 04
    (c) Explain code coverage in detail. 07

    Q.5 (a) What is function of linting tools? 03


    (b) Design 4x1 multiplexer and write it test bench using any hardware 04
    description language.
    (c) Describe simulation based verification method in detail. 07
    OR
    Q.5 (a) What does 100% function coverage mean? 03
    (b) What is mean by assertions in verification and explain implementation 04
    assertions and specification assertions.
    (c) Draw serial fault simulation algorithm flow chart and explain it with an 07
    example.

    *************

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