Csa

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Q1.->Calculate the gate delays to produce C48 and S47 in the following 48-bit adders:
a) 48-bit ripple carry adder.
b) 48-bit adder by cascading 4-bit CLA (Carry Look Ahead) adders. Here, 4-bit CLA are
developed using first level Generate and Propagate functions. Also write the
expressions for C4, C8, C12, C16, C20, C24, C28 and C32.
Ans:a) For Carry C48 = 2 * 48 = 96 gate delays (GD) For Sum S47 = 95 GD
Ans:b) For Carry C48 = 3 + 11 * 2 = 25 GD For Sum S47 = 26 GD
Q2.-> How many CSA levels are needed to reduce 24 summands to 2 summands in
carry-save addition of summands method? Also calculate the gate delays for 24 bit ×
24 bit multiplication in Carry save addition of summands method.
Ans:7 CSA levels are needed to reduce 24 summands to 2 summands in carry-save
addition of summands method. Gate Delay = 1 (one AND gate delay for getting all
summands) + 7 × 2 (2 gate delays for each CSA level) + 12 (for final 48-bit addition) =
27 Gate delay
Q3.-> Use non-restoring division algorithm to perform 11 ÷4
Q 4->A 2-bit binary adder sums two numbers, A1A0and B1B0to yield the unsigned result
Y2Y1Y0, where the zero subscript indicates the least significant bit (LSB).
(i)Write down the truth table for the required outputs Y2, Y1and Y0.
(ii)Using a Karnaugh map (K map), give the simplified sum ofproducts expression for Y2.
(iii)Using a K map, determine a

simplified product of sums expression for Y2and show how the circuit can be implemented using only
NOR gates.
Q 5->A byte-addressable processor uses the big-endian representation and 32-bit integer
value -13 is stored at the memory address 100 and same value is stored at register
R0 and R1.
i. Determine the 8-bit binary contents of memory locations 100, 101, 102
and 103?
ii. Show the integer value in R0 and R1 after execution of instruction
Compare R0, R1?
iii. What will be the integer value in R0 after execution of instruction AShiftR
#2, R0?
ans(i) 8-bit binary contents of memory locations 100, 101 and 102 are 11111111 8-bit binary contents of
memory location103 are 11110011
(ii) R0 = R1 = -13
(iii) R0 will contain -4after execution of instruction AShiftR #2, R0
Q 6->Calculate the gate delays for 32-bit × 32-bit multiplication in Carry save addition
of summands method, given that 8 CSA levels are needed to reduce 32 summands
to 2 summands. For final addition of 2 summands of 64 bits, use 64 -bit adder built
from a cascade of four 16-bit CLA adders. Here, 16-bit CLA are developed using
second-level block generate and propagate function.
Ans Gi,Pi = 1 GD, Gi`,Pi`= Next 2 GD = 3
C4, C8, C12, C16 = Next 2 GD = 5
C20, C24, C28, C32= Next 2 GD = 7
C36, C40, C44, C48= Next 2 GD = 9
C52, C56, C60, C64 = Next 2 GD = 11
AllCarry’s= Next 2 GD = 13SumS63= one more GD = 14So, gate delays for 32-bit × 32-bitmultiplication in
Carry save additionis1 + 8 ×2 +14 = 31 Gate Delay
Q 7->Use non-restoring division algorithmto perform 29 ÷ 3

Q8->Convert the Multiplicand M = (+31)10and Multiplier Q= (-24)10 represented as decimal numbers,
in6-bit, signed, 2’s complement binary numbers.Use Booth and bit-pair multiplication methods
to multiply them.
Consider byte addressable machine with 32-bit word size. An integer array of order m × n is stored
starting from memory location LISTin column major order (that is,the elements of array are stored
column-wise at successive memory location starting from LIST)
. i.Write an assembly language program for computing the sum of integers of each row of the array and
store these sums in the memory word locations at addresses SUM, SUM+4, SUM +8.... (. i.e.,m
successive locations starting from SUM). Assume that values of m and n are stored at
memory location M and N respectively.
ii.The assembly code of part (i) is executed on a processor having a clock rate of 1 GHz. The processor can
execute an instruction that access memory for reading or writing data with an average of 5 steps, and
other instructions that do not require operand access from or to main memory can execute with an
average of 3 steps (each step completes in one clock cycle). Calculate the execution time
for the assembly code
Ans If 50 alphabets are lowercase and 50 are uppercase:
N × S
MOV#LIST, R0 1 × 3 MOV #100,
R1 1 × 3 LOOP CMP (R0), #97
100 × 5 BRANCH > 0 NEXT 100 × 5
SUB #32, (R0) 50 × 5 NEXT INC R0
100 × 5 DEC R1 100 × 5
BRANCH > 0 LOOP 100 × 5 T = N×S / R
T = 1.63 microseconds
Note that answer may be different if all 100 alphabets are uppercase or all 100 are
lowercase. Full Marks will be given based on the assumption made by student.
Q 10-> Perform 7 ÷ 3 by restoring division algorithm . One mark for each cycle.
Q 11->Consider a byte addressable computer with 32-bit word size. Starting from memory location
LIST, 100 integer values are stored insuccessive memory words. Write assembly code to
modify the contents of these 100 memory words as per the following condition:If stored integer value
is less than 2000 in a memory word, add 200 to the value, else add 400 to the stored value.

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ETE PAPER

(iii)Using a K map, determine a

ii. Show the integer value in R0 and R1 after execution of instruction

Compare R0, R1?

(iii) R0 will contain -4after execution of instruction AShiftR #2, R0

second-level block generate and propagate function.

Ans Gi,Pi = 1 GD, Gi`,Pi`= Next 2 GD = 3

C4, C8, C12, C16 = Next 2 GD = 5

C20, C24, C28, C32= Next 2 GD = 7

C36, C40, C44, C48= Next 2 GD = 9

C52, C56, C60, C64 = Next 2 GD = 11

Q 7->Use non-restoring division algorithmto perform 29 ÷ 3

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