OS Task 1

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THE MINISTRY OF EDUCATION AND SCIENCE OF NIGERIA

CRESCENT UNIVERSITY

“CUAB”

Computer Science Department

Task № 1
from discipline «CPS 205»

Topic: «OPERATING SYSTEM INTERFACE WITH THE


HARDWARE; INTERRUPTS I/O CHANNEL,
MULTIPLEXER, REGISTERS AND STATUS WORD»

MATRIC NO: S1022202066

Executed by the student of 200 level:


_________Aremu Faizal Oluwatosin
(sign, date) (name, surname)

Supervisedby: ___________________

(sign, date) (name, surname)

2022
CONTENTS
INTRODUCTION
1.1 Operating system
1.2 I/O Systems
1.3 I/O Channels and types
1.4 Registers
1.5 Status Word
1.1 OPERATING SYSTEM
The operating system acts as an interface between the hardware and the
programs requesting I/O. It is the most fundamental of all system software
programs.

Responsibilities of the OS include:


 Hiding the complexities of hardware from the user.
 Managing between the hardware's resources which include the
processors, memory, data storage and I/O devices.
 Handling "interrupts" generated by the I/O controllers.
 Sharing of I/O between many programs using the CPU.

There are two types of software:


 System Software - programs that manage the operation of a computer.
 Application Software - programs that help the user perform a particular
task.

User Interface:
The User Interface is the interaction between the User and the Machine, letting
the user send commands with the expected results. Two forms of the Interface
User are the Command Line Interface and the Graphical User interface.

Command Line Interface (CLI):


The greater primitive consumer Interface, the user could type in a line of
command or a single phrase accompanied by way of pressing the return key.
The computer then willingly follows that actual command, informing the user of
its result. for instance, the user might also need to type within the command to
print a document. The user will type the declaration Print, then the name of the
Printer and subsequently the name of the file to be printed:
Figure 1.0 Modern Command Line Interface Example

Advantage
 CLIs can run on simple hardware with limited resources.
 Some commands may be simpler to perform in a CLI than in a GUI.

Disadvantage
 Learning the commands may make it not suitable for a new user.
 Some commands may be harder to perform in a CLI than in a GUI.

Graphical User Interface (GUI):


The GUI is made up of boxes or Windows which will display as an array of
usually colorful tiny blocks called Pixels, and a group of pixels is a called an
image. The maximum number of colors that can be used are called the
Graphics. This User interface will display a Main window (also known as the
Desktop) which then can be accompanied by more windows. GUI is the most
common of the User interfaces, and the most user friendly, made up of event
driven software. This type of UI is best for users lacking in computer coding
skills, since GUI only needs you to make use of the mouse's events.
Figure 1.1: Example of Graphic User Interface (GUI)

Advantage
 Simple and intuitive for new users
 Some commands may be simpler to perform in a GUI than in a CLI
Disadvantage
 GUIs require system resources and more complex hardware than CLIs
 Some commands may be harder to perform in a GUI than in a CLI

1.2 I/O Systems


The operating system's management of I/O devices is so crucial and diverse that
entire I/O subsystems are devoted to its management. (Take into account the
wide variety of peripherals found on a modern computer, including mouse,
keyboards, disk drives, display adapters, USB devices, network connections,
audio I/O, printers, special equipment for the disabled, and many others.)
1.2.1 I/O Hardware
 I/O devices can be roughly categorized as storage, communications, user-
interface, and other
 Devices communicate with the computer via signals sent over wires or
through the air.
 Devices connect with the computer via ports, e.g., a serial or parallel port.
 A common set of wires connecting multiple devices is termed a bus.

 Buses include rigid protocols for the types of messages that can be
sent across the bus and the procedures for resolving contention
issues.
 Figure 1.2 below illustrates three of the four bus types commonly
found in a modern PC:

Figure 1.2: - A typical Bus Structure

 The PCI bus connects high-speed high-bandwidth devices to the


memory subsystem (and the CPU.)
 The expansion bus connects slower low-bandwidth devices, which
typically deliver data one character at a time (with buffering.)
 The SCSI bus connects a number of SCSI devices to a common
SCSI controller.
One way of communicating with devices is through REGISTERS associated
with each port. Registers may be one to four bytes in size, and may typically
include (a subset of) the following four:
 The data-in register is read by the host to get input from the device.
 The data-out register is written by the host to send output.
 The status register has bits read by the host to ascertain the status of the
device, such as idle, ready for input, busy, error, transaction complete,
etc.
 The control register has bits written by the host to issue commands or to
change settings of the device such as parity checking, word length, or
full- versus half-duplex operation.

Figure 1.4 shows some of the most common I/O port address ranges.

Figure 1.3: - Device I/O port locations on PCs (partial).

Another technique for communicating with devices is memory-mapped I/O.


 In this case a certain portion of the processor's address space is mapped to
the device, and communications occur by reading and writing directly
to/from those memory areas.
 Memory-mapped I/O is suitable for devices which must move large
quantities of data quickly, such as graphics cards.
 Memory-mapped I/O can be used either instead of or more often in
combination with traditional registers. For example, graphics cards still
use registers for control information such as setting the video mode.
 A potential problem exists with memory-mapped I/O, if a process is
allowed to write directly to the address space used by a memory-mapped
I/O device.
(Note: Memory-mapped I/O is not the same thing as direct memory access,
DMA. See section 13.2.3 below.)
1.2.3 Interrupts:
 Interrupts allow devices to notify the CPU when they have data to
transfer or when an operation is complete, allowing the CPU to perform
other duties when no I/O transfers need its immediate attention.
 The CPU has an interrupt-request line that is sensed after every
instruction.
o A device's controller raises an interrupt by asserting a signal on the
interrupt request line.
o The CPU then performs a state save, and transfers control to
the interrupt handler routine at a fixed address in memory. ( The
CPU catches the interrupt and dispatches the interrupt handler. )
o The interrupt handler determines the cause of the interrupt,
performs the necessary processing, performs a state restore, and
executes a return from interrupt instruction to return control to the
CPU. (The interrupt handler clears the interrupt by servicing the
device.)
(Note that the state restored does not need to be the same state as the one that
was saved when the interrupt went off. See below for an example involving
time-slicing.)
 Figure 1.4 illustrates the interrupt-driven I/O procedure:
Figure 1.4: - Interrupt-driven I/O cycle.

The above description is adequate for simple interrupt-driven I/O, but there
are three needs in modern computing which complicate the picture:
 The need to defer interrupt handling during critical processing,
 The need to determine which interrupt handler to invoke, without
having to poll all devices to see which one needs attention, and
 The need for multi-level interrupts, so the system can differentiate
between high- and low-priority interrupts for proper response.
 These issues are handled in modern computer architectures with
interrupt-controller hardware.
 Most CPUs now have two interrupt-request lines: One that is non-
maskable for critical error conditions and one that is maskable, that
the CPU can temporarily ignore during critical processing.
These issues are handled in modern computer architectures with interrupt-
controller hardware.
 Most CPUs now have two interrupt-request lines: One that is non-
maskable for critical error conditions and one that is maskable, that the
CPU can temporarily ignore during critical processing.
 The interrupt mechanism accepts an address, which is usually one of a
small set of numbers for an offset into a table called the interrupt vector.
This table ( usually located at physical address zero ? ) holds the
addresses of routines prepared to process specific interrupts.
 The number of possible interrupt handlers still exceeds the range of
defined interrupt numbers, so multiple handlers can be interrupt chained.
Effectively the addresses held in the interrupt vectors are the head
pointers for linked-lists of interrupt handlers.
 Figure 1.5 shows the Intel Pentium interrupt vector. Interrupts 0 to 31 are
non-maskable and reserved for serious hardware and other errors.
Maskable interrupts, including normal device I/O interrupts begin at
interrupt 32.

Figure 1.5: - Intel Pentium processor event-vector table.


1.2.4 Application I/O Interface
User application access to a wide variety of different devices is accomplished
through layering, and through encapsulating all of the device-specific code into
device drivers, while application layers are presented with a common interface
for all (or at least large general categories of) devices.

Figure 1.6: - A kernel I/O structure.

I/O Scheduling
 Scheduling I/O requests can greatly improve overall efficiency. Priorities
can also play a part in request scheduling.
 The classic example is the scheduling of disk accesses, as discussed in
detail in chapter 12.
 Buffering and caching can also help, and can allow for more flexible
scheduling options.
 On systems with many devices, separate request queues are often kept for
each device:
Buffering:
 Buffering of I/O is performed for (at least) 3 major reasons:

1. Speed differences between two devices. (See Figure 13.10 below.) A


slow device may write data into a buffer, and when the buffer is full, the
entire buffer is sent to the fast device all at once. So that the slow device
still has somewhere to write while this is going on, a second buffer is
used, and the two buffers alternate as each becomes full. This is known as
double buffering. (Double buffering is often used in (animated) graphics,
so that one screen image can be generated in a buffer while the other
(completed) buffer is displayed on the screen. This prevents the user from
ever seeing any half-finished screen images.)
2. Data transfer size differences. Buffers are used in particular in
networking systems to break messages up into smaller packets for
transfer, and then for re-assembly at the receiving side.
3. To support copy semantics. For example, when an application makes a
request for a disk write, the data is copied from the user's memory area
into a kernel buffer. Now the application can change their copy of the
data, but the data which eventually gets written out to disk is the version
of the data at the time the write request was made.
Caching:
 Caching involves keeping a copy of data in a faster-access location than
where the data is normally stored.
 Buffering and caching are very similar, except that a buffer may hold the
only copy of a given data item, whereas a cache is just a duplicate copy of
some other data stored elsewhere.
 Buffering and caching go hand-in-hand, and often the same storage space
may be used for both purposes. For example, after a buffer is written to
disk, then the copy in memory can be used as a cached copy, (until that
buffer is needed for other purposes.)
Spooling and Device Reservation
 A spool (Simultaneous Peripheral Operations On-Line) buffers data for
(peripheral) devices such as printers that cannot support interleaved data
streams.
 If multiple processes want to print at the same time, they each send their
print data to files stored in the spool directory. When each file is closed,
then the application sees that print job as complete, and the print
scheduler sends each file to the appropriate printer one at a time.
 Support is provided for viewing the spool queues, removing jobs from the
queues, moving jobs from one queue to another queue, and in some cases
changing the priorities of jobs in the queues.
 Spool queues can be general (any laser printer) or specific (printer
number 42.)
 OSes can also provide support for processes to request / get exclusive
access to a particular device, and/or to wait until a device becomes
available.
Error Handling
 I/O requests can fail for many reasons, either transient (buffers overflow)
or permanent (disk crash).
 I/O requests usually return an error bit (or more) indicating the problem.
UNIX systems also set the global variable errno to one of a hundred or so
well-defined values to indicate the specific error that has occurred. (See
errno.h for a complete listing, or man errno.)
 Some devices, such as SCSI devices, are capable of providing much more
detailed information about errors, and even keep an on-board error log
that can be requested by the host.
I/O Protection
 The I/O system must protect against either accidental or deliberate
erroneous I/O.
 User applications are not allowed to perform I/O in user mode - All I/O
requests are handled through system calls that must be performed in
kernel mode.
 Memory mapped areas and I/O ports must be protected by the memory
management system, but access to these areas cannot be totally denied to
user programs. (Video games and some other applications need to be able
to write directly to video memory for optimal performance for example.)
Instead, the memory protection system restricts access so that only one
process at a time can access particular parts of memory, such as the
portion of the screen memory corresponding to a particular window.
1.3 I/O Channels and its types:
I/O Channel is an extension of the DMA concept. It has ability to execute
I/O instructions using special-purpose processor on I/O channel and complete
control over I/O operations. Processor does not execute I/O instructions itself.
Processor initiates I/O transfer by instructing the I/O channel to execute a
program in memory.

Types of I/O Channels

1. Selector Channel:
Selector channel controls multiple high-speed devices. It is dedicated to the
transfer of data with one of the devices. In selector channel, each device is
handled by a controller or I/O module. It controls the I/O controllers shown in
the figure.
2. Multiplexer channel is a DMA controller that can handle multiple devices
at the same time. It can do block transfers for several devices at once.

Two types of multiplexers are used in this channel:

 Byte Multiplexer
It is used for low-speed devices. It transmits or accepts characters.
Interleaves bytes from several devices.

 Block Multiplexer –
It accepts or transmits block of characters. Interleaves blocks of
bytes from several devices. Used for high-speed devices.
1.4 Registers:
Registers are a type of computer memory used to quickly accept, store, and
transfer data and instructions that are being used immediately by the CPU. The
registers used by the CPU are often termed as Processor registers.
A processor register may hold an instruction, a storage address, or any data
(such as bit sequence or individual characters).
The computer needs processor registers for manipulating data and a register for
holding a memory address. The register holding the memory location is used to
calculate the address of the next instruction after the execution of the current
instruction is completed.
Following is the list of some of the most common registers used in a basic
computer:
Register Symbol Number Function
of bits

Data register DR 16 Holds


memory
operand

Address AR 12 Holds
register address for The following image
the memory shows the register and
memory configuration
Accumulator AC 16 Processor
for a basic computer.
register

Instruction IR 16 Holds Figure 1.7: - Registers and


memory configuration for a
register instruction
basic computer
code
 The Memory
Program PC 12 Holds unit has a
counter address of
capacity of 4096
the
words, and each
instruction
word contains 16
Temporary TR 16 Holds bits.
register temporary
data

Input INPR 8 Carries


register input
character

Output OUTR 8 Carries


register output
character
 The Data Register (DR) contains 16 bits which hold the operand read
from the memory location.
 The Memory Address Register (MAR) contains 12 bits which hold the
address for the memory location.
 The Program Counter (PC) also contains 12 bits which hold the address
of the next instruction to be read from memory after the current
instruction is executed.
 The Accumulator (AC) register is a general purpose processing register.
 The instruction read from memory is placed in the Instruction register
(IR).
 The Temporary Register (TR) is used for holding the temporary data
during the processing.
 The Input Registers (IR) holds the input characters given by the user.
 The Output Registers (OR) holds the output after processing the input
data.

1.5 Program Status Word (PSW):


The Program Status Word or PSW is a collection of data 8 bytes (or 64 bits)
long, maintained by the operating system. It keeps track of the current state of
the system.

We can usually ignore the PSW unless an ABEND has occurred. When an
ABEND does occur, ASSIST will print out various information for us including
the PSW. The PSW is printed out as 16 hex digits in two groups of 8.

What information is in the PSW?

You can find a detailed list of the fields in the PSW in the yellow card. We use
the "BC Mode" of the PSW. Here is a list of some fields we will need in this
course:

Bytes Contents
1 & 2: assorted data we can ignore for now
3 & 4: Interruption Code
5: 2 bits = Instruction Length Code (ILC)
2 bits = Condition Code (CC)
4 bits we can ignore for now
6 - 8: Address of the next instruction
What are all these?

 The Interruption Code indicates the type of ABEND that has occurred.
 The ILC gives us the length of the current instruction, measured in
halfwords,
 The CC gives us the condition code as set most recently.
 The address of the next instruction gives us the location of the instruction
that would have been executed if the program had not ABENDed.

So, what do we do with all this?


One problem with an ABEND is to determine which instruction caused the
ABEND. We can find it using the information in the PSW:

Address of ABENDing instruction = Address of next instruction - 2 * ILC


Example
Suppose an ABEND occurs and the PSW has the value FFC50001 8000001A.

We can look at this and know that:


 The interrupt code is 0001 (Operation Exception).
 The ILC is 10 (binary) or 2 (decimal), so the ABENDing instruction is 4
bytes long.
 The CC is 00.
 The address of the next instruction is 00001A.
 The address of the ABENDing instruction is 00001A - 4 = 000016.

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