OS Task 1
OS Task 1
OS Task 1
CRESCENT UNIVERSITY
“CUAB”
Task № 1
from discipline «CPS 205»
Supervisedby: ___________________
2022
CONTENTS
INTRODUCTION
1.1 Operating system
1.2 I/O Systems
1.3 I/O Channels and types
1.4 Registers
1.5 Status Word
1.1 OPERATING SYSTEM
The operating system acts as an interface between the hardware and the
programs requesting I/O. It is the most fundamental of all system software
programs.
User Interface:
The User Interface is the interaction between the User and the Machine, letting
the user send commands with the expected results. Two forms of the Interface
User are the Command Line Interface and the Graphical User interface.
Advantage
CLIs can run on simple hardware with limited resources.
Some commands may be simpler to perform in a CLI than in a GUI.
Disadvantage
Learning the commands may make it not suitable for a new user.
Some commands may be harder to perform in a CLI than in a GUI.
Advantage
Simple and intuitive for new users
Some commands may be simpler to perform in a GUI than in a CLI
Disadvantage
GUIs require system resources and more complex hardware than CLIs
Some commands may be harder to perform in a GUI than in a CLI
Buses include rigid protocols for the types of messages that can be
sent across the bus and the procedures for resolving contention
issues.
Figure 1.2 below illustrates three of the four bus types commonly
found in a modern PC:
Figure 1.4 shows some of the most common I/O port address ranges.
The above description is adequate for simple interrupt-driven I/O, but there
are three needs in modern computing which complicate the picture:
The need to defer interrupt handling during critical processing,
The need to determine which interrupt handler to invoke, without
having to poll all devices to see which one needs attention, and
The need for multi-level interrupts, so the system can differentiate
between high- and low-priority interrupts for proper response.
These issues are handled in modern computer architectures with
interrupt-controller hardware.
Most CPUs now have two interrupt-request lines: One that is non-
maskable for critical error conditions and one that is maskable, that
the CPU can temporarily ignore during critical processing.
These issues are handled in modern computer architectures with interrupt-
controller hardware.
Most CPUs now have two interrupt-request lines: One that is non-
maskable for critical error conditions and one that is maskable, that the
CPU can temporarily ignore during critical processing.
The interrupt mechanism accepts an address, which is usually one of a
small set of numbers for an offset into a table called the interrupt vector.
This table ( usually located at physical address zero ? ) holds the
addresses of routines prepared to process specific interrupts.
The number of possible interrupt handlers still exceeds the range of
defined interrupt numbers, so multiple handlers can be interrupt chained.
Effectively the addresses held in the interrupt vectors are the head
pointers for linked-lists of interrupt handlers.
Figure 1.5 shows the Intel Pentium interrupt vector. Interrupts 0 to 31 are
non-maskable and reserved for serious hardware and other errors.
Maskable interrupts, including normal device I/O interrupts begin at
interrupt 32.
I/O Scheduling
Scheduling I/O requests can greatly improve overall efficiency. Priorities
can also play a part in request scheduling.
The classic example is the scheduling of disk accesses, as discussed in
detail in chapter 12.
Buffering and caching can also help, and can allow for more flexible
scheduling options.
On systems with many devices, separate request queues are often kept for
each device:
Buffering:
Buffering of I/O is performed for (at least) 3 major reasons:
1. Selector Channel:
Selector channel controls multiple high-speed devices. It is dedicated to the
transfer of data with one of the devices. In selector channel, each device is
handled by a controller or I/O module. It controls the I/O controllers shown in
the figure.
2. Multiplexer channel is a DMA controller that can handle multiple devices
at the same time. It can do block transfers for several devices at once.
Byte Multiplexer
It is used for low-speed devices. It transmits or accepts characters.
Interleaves bytes from several devices.
Block Multiplexer –
It accepts or transmits block of characters. Interleaves blocks of
bytes from several devices. Used for high-speed devices.
1.4 Registers:
Registers are a type of computer memory used to quickly accept, store, and
transfer data and instructions that are being used immediately by the CPU. The
registers used by the CPU are often termed as Processor registers.
A processor register may hold an instruction, a storage address, or any data
(such as bit sequence or individual characters).
The computer needs processor registers for manipulating data and a register for
holding a memory address. The register holding the memory location is used to
calculate the address of the next instruction after the execution of the current
instruction is completed.
Following is the list of some of the most common registers used in a basic
computer:
Register Symbol Number Function
of bits
Address AR 12 Holds
register address for The following image
the memory shows the register and
memory configuration
Accumulator AC 16 Processor
for a basic computer.
register
We can usually ignore the PSW unless an ABEND has occurred. When an
ABEND does occur, ASSIST will print out various information for us including
the PSW. The PSW is printed out as 16 hex digits in two groups of 8.
You can find a detailed list of the fields in the PSW in the yellow card. We use
the "BC Mode" of the PSW. Here is a list of some fields we will need in this
course:
Bytes Contents
1 & 2: assorted data we can ignore for now
3 & 4: Interruption Code
5: 2 bits = Instruction Length Code (ILC)
2 bits = Condition Code (CC)
4 bits we can ignore for now
6 - 8: Address of the next instruction
What are all these?
The Interruption Code indicates the type of ABEND that has occurred.
The ILC gives us the length of the current instruction, measured in
halfwords,
The CC gives us the condition code as set most recently.
The address of the next instruction gives us the location of the instruction
that would have been executed if the program had not ABENDed.