Al-Farabi University College Computer Architecture I

Lecture 3_1

(Basic Computer Organization and Design)

Third Stage

Computer Architecture I

Dr. Qasim Hadi

Computer Engineering Department

AL-Farabi University College

2022-2023
Al-Farabi University College Computer Architecture

Chapter Five
Basic Computer Organization and Design:

5.1 Instruction Codes

The organization of a digital computer defined by:
1. The set of registers it contains and their function.
2. The set of instructions used.
3. The timing and control structure.
The user of a computer can control the process by means of a program.
A Program can be defined as a set of instructions that specify the
operations, operands, and the sequence by which processing has to occur.
A Computer Instruction is a binary code that specifies a sequence of
microoperations for the computer.
An Instruction Code is a group of bits that leads the computer to perform
a specific operation. The instruction code usually divided into many parts,
each having its own particular interpretation. The most basic part of an
instruction code is its operation part.
The Operation Code is groups of bits that define operations such as add,
subtract, multiply, shift, and complement. The number of bits required
for the operation code of an instruction depends on the total number of
operations available in the computer. For example, a computer with 32
distinct operations needs an operation code that consists of five bits.

5.2 Stored Program Organization and Addressing

Suppose that we have a computer with one processor register named
Accumulator (abbreviated AC) and an instruction code format with two

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parts, one part for the type of operation to be performed and the second
specifies an address. The memory address indicates the control where to find
the operand in memory. The operand is read from memory and used as the
data to be operated on together with the data stored in the processor register.
Figure 5.1 illustrates this type of organization. For this example, it is shown
that the set of instructions (programs) are stored in one section of memory
and data in another section.
For a memory unit with 4096 words, we need 12 bits to specify an address
since 212 = 4096 and 4 bits for the operation code (Opcode) to specify one
out of 16 possible operations.
To execute the program, the control reads the first 16-bit instruction from
the program portion of memory. The 12-bit address part of the instruction is
used to read a 16-bit operand from the data portion of memory. The control
then executes the operation specified by the operation code. The operation
is performed with the memory operand and the content of AC.
In case the operation indicated by the instruction code does not need an
operand from memory, the 12-bits used to specify the address of the operand
are not used and therefore can be used for other purpose. Examples of these
operations that operate on data stored in the Accumulator register (AC) are,
clear AC, complement AC, and increment AC.

Direct and Indirect Addressing

When the second part of an instruction code specifies an operand, the
instruction is said to have an Immediate Operand and this type of
instructions are called Immediate Instructions.
When the second part of an instruction code specifies the address of an
operand, the instruction is said to have a Direct Address.
When the second part of an instruction code designates an address of a
memory word, in which the address of the operand is found, the instruction

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is said to have an Indirect Address.

The memory word that holds the address of the operand is used as a pointer
to an array of data. The pointer could be placed in a processor register
instead of memory as done in commercial computers.
To distinguish between a direct and indirect address, the most significant bit
(bit 15) of the instruction code is used, in which 0 indicates direct address,
while 1 indicates indirect address.
To illustrate these configurations, we consider the instruction code format
shown in figure 5.2(a). The instruction consists of a one bit designated by I
for addressing mode, 3-bit for operation code, and the remaining 12 bits
for an address.
A direct address instruction is shown in figure 5.2(b), where I = 0. This
instruction is placed in address 10 in memory. The Opcode specifies an
ADD instruction, and the address part is the binary equivalent of 1020. The

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control finds the operand in memory at address 1020 and adds it to the
content of AC.
An indirect address instruction is shown in figure 5.2(c), where I = 1. This
instruction is placed in address 20 in memory. The Opcode specifies an
ADD instruction, and the address part is the binary equivalent of 90. The
control goes to the word at address 90 to find the address of the operand in
memory at address 1340 and adds it to the content of AC. It is clear that, the
indirect address instruction needs two references to memory to fetch an
operand.
From the above examples, it is shown that there is what is called Effective
Address, which can be defined as the address of the operand in a
computation-type instruction or the target address in a branch-type
instruction. Thus, the effective address in the instruction of figure 5.2(b) is
1020 and the effective address in the instruction of figure 5.2(c) is 1340.

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5.3 Computer Registers

As shown in the previous section, computer instructions are stored in
consecutive memory locations and are executed sequentially one at a time.
Therefore, in this case, a counter is needed to calculate the address of the
next instruction after execution of the current instruction is completed. In
addition, it is necessary to provide a register in the control unit for storing
the instruction code after reading it from memory. The computer needs
processor register for manipulating data and a register for holding a memory
address.

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From table 5.1, it is indicated that the memory address register (AR) has 12
bits since this is the width of memory address. The program counter (PC)
has also12 bits since it holds the address of the next instruction to be read
from memory after the current instruction is executed. The PC goes through
a counting sequence and causes the computer to read sequential instructions
previously stored in memory. Instruction words are read and executed in
sequence unless a branch instruction is encountered. A branch instruction
calls for a transfer to a nonconsecutive instruction in the program. The

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address part of a branch instruction is transferred to PC to become the

address of the next instruction.
The input and output register [(INPR) and (OUTR)] have 8 bits since each
holds an 8-bits character.

Examples
1) A computer uses a memory unit with 256K words of 32 bits each. A
binary instruction code is stored in one word of memory. The instruction has
four parts: an indirect bit, an operation code, a register code part to specify
one of 64 registers, and an address part.
a. How many bits are there in the operation code, the register code part, and
the address part?
b. Draw the instruction word format and indicate the number of bits in each
part.
c. How many bits are there in the data and address inputs of the memory?
Ans.

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2) What is the difference between a direct and an indirect address

instruction? How many references to memory are needed for each type of
instruction to bring an operand into a processor register?
Ans.

3) The following control inputs are active in the bus system shown in Figure
5-4. For each case, specify the register transfer that will be executed during
the next clock transition.

Common Bus System

Figure 5.4 shows the basic computer in which it has eight registers, a
memory unit, and a control unit. Paths must be provided to transfer
information from one register to another and between memory and registers
via a common bus.
The outputs of six registers and memory are connected to the common bus.
The selection variables S2, S1, and S0 are used to select the output of one
of the six registers or memory at a given time.

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The number shown along each output indicates the decimal equivalent of
the required binary selection. For example, the number along the output of
memory unit is 7, and that along the output of register PC is 2. The 12-bit
outputs of PC are placed on the bus lines when S2S1S0 = 010.
The lines from the common bus are connected to the inputs of each register
and the data inputs of the memory. The particular register whose LD (Loud)
input is enabled receives the data from the bus during the next clock pulse
transition.
The memory receives the contents of the bus when its write input is activated
and S2S1S0 = 111. The memory places its 16-bit output onto the bus when
the read input is activated.
Two registers, AR & PC, have 12 bits each since as mentioned before they
hold a memory address. When their contents are applied to the 16-bit
common bus, the four most significant bits are set to 0's. When AR & PC
receive information from the common bus, only the 12 least significant bits
of the bus are transferred into these registers.

Four registers, DR, AC, IR, and TR, each have 16 bits. They receive and
transfer 16 bits from and to the common bus.
The input and output registers (INPR & OUTR) have 8 bits each and
communicate with the eight least significant bits in the bus. The input
register (INPR) receives a character from an input device and it is connected
in such a case to provide information to the bus via the accumulator. The
output register (OUTR) can only receive information from the accumulator
via the bus and delivers it to an output device.
The common bus receives information from six registers (AR, PC, DR, AC,
IR, and TR) and the memory, in other hand the common bus is connected to
the inputs of six registers (AR, PC, DR, IR, TR, and OUTR) and the
memory.

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Registers (AR, PC, DR, AC, and TR) have three control inputs, LD (load
register), INR (increment register), and CLR (clear or reset register), while
registers (IR, and OUTR) have only one control input (LD).
The input and output data of the memory are connected to the common bus,
while the memory address is connected to address register (AR). The content
of any register except INPR & OUTR can be specified for the memory
during a write operation. Similarly, any register can receive the data from
memory after a read operation except AC & INPR.
The output of adder and logic circuit goes to the input of the 16-bit AC.
There are three sets of inputs to the adder and logic circuit:

1. A set of 16-bit comes from the outputs of the accumulator AC. They are
used to implement register microoperations such as complement AC, and
shift AC.
2. A set of 16-bit comes from the data register DR. the inputs from DR and
AC are used for arithmetic and logic microoperations, such as add DR to
AC or AND DR to AC. The result of an addition is transferred to AC and
the end carry out of the addition is transferred to flip-flop E (extended AC
bit).
3. A set of 8-bit comes from the input register INPR.
From the diagram, it is clear that the content of any register can be applied
onto the bus and an operation can be performed in the adder and logic circuit
during the same clock cycle. The clock transition at the end of the cycle
transfers the content of the bus into the designated destination register and
the output of the adder and logic circuit into AC. For example, the following
two microoperations can be executed at the same time.
DR ← AC and AC ← DR
This can be done by placing the content of AC on the bus (with S2S1S0 =
100) enabling the LD (load) input of DR, transferring the content of DR
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through the adder and logic circuit into AC , and enabling the LD (load)
input of AC, all during the same clock cycle. The two transfers occur upon
the arrival of the clock pulse transition at the end of the clock cycle.

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5.4 Computer Instructions

The basic computer has three instruction code formats. The type of
instruction is recognized by the computer control from the four bits in
positions 12 through 15 of the instruction as follows:
1. Memory-Reference Instruction
For this type of instructions, the three Opcode bits in position 12 through 14
may be any combination except 111, and bit 15 is designate the addressing
mode I. when I = 0 indicates direct address and when I = 1 indicates indirect
address. The 12 bits in position 0 through 11 are used to specify an address.
See figure 5.5(a).
2. Register-Reference Instruction
For this type of instructions, the three Opcode bits in position 12 through 14
is equal to 111 and the bit in position 15 equals to 0. This type of instructions
specifies an operation on or a test of the AC register. An operand from
memory is not needed; therefore, the other 12 bits are used to specify the
operation or test to be executed. See figure 5.5(b).
3. Input-Output Instruction
For this type of instructions, the three Opcode bits in position 12 through 14
is equal to 111 and the bit in position 15 equals to 1. This type of instructions
does not need a reference to memory. The remaining 12 bits are used to
specify the type of input-output operation or test performed. See figure
5.5(c).
Table 5.2 shows the instructions used by the computer. Three letters are used
to represent each instruction. The hexadecimal code is equal to the
equivalent hexadecimal number of the binary code used for the instruction.

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A computer should have a set of instructions so that the user can construct
machine language programs to evaluate any function that is known to be
computable.
This set of instructions is distributed on the following categories:
1. Arithmetic, logical, and shift instructions.
2. Moving information to and from memory and processor registers
Instructions.
3. Program control instructions together with instructions that check status
conditions.
4. Input and output instructions.

5.5 Timing and Control

A master clock generator controls the timing of all registers in the basic
computer. However, the clock pulses do not change the state of a register
unless the register is enabled by a control signal.
The control signals are generated in the control unit and provide control
inputs for the multiplexers in the common bus, control inputs in processor
registers, and microoperations for the accumulator.
There are two major types of control organization:
1. Hardware Organization Control
In this type of organization, the control logic is implemented with gates, flip-
flops, decoders, and other digital circuits. It has the advantage that it can be
optimized to produce a fast mode of operation. It has the disadvantage that
it requires changes in the wiring among the various components if the design
has to be modified or changed.
2. Microprogrammed Organization Control

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In this type of organization, the control information is stored in a sequence

of microoperations. It has the advantage that any required changes or
modifications could be done by updating the microprogram in control
memory.
In this section, we present the hardware control for the basic computer,
while the microprogrammed control the same computer will be studied later.
Figure 5.6 presents the block diagram of the control unit. The control unit
consists of two decoders, a sequence counter, and a number of control logic
gates. The instruction register (IR) is shown in the diagram is divided into
three parts:
1. Bit 15 is transferred to a flip-flop designated by the symbol I, and its
function is as mentioned before.
2. Bits 12 through 14 presents the operation code are decoded by a 3 × 8
decoder. The eight outputs of the decoder are designated by the symbols D0
through D7. Note that the subscripted decimal number is equivalent to the
binary value of the corresponding operation code.
3. Bits 0 through 11 are applied to the control logic gates.
The 4-bit sequence counter can count in binary from 0 through 15. The
outputs of the counter are decoded into 16 timing signals T0 through T15.

The sequence counter (SC) can be incremented and cleared synchronously.

Most of the time, the counter is incremented to provide the sequence of
timing signals out of the 4 ×16 decoder.

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The timing diagram of figure 5.7 shows the time relationship of the control
signals. The sequence counter SC responds to the positive transition of the
clock. Initially, the CLR input of SC is active. The first positive transition
of the clock clears SC to 0, which in turn activates the timing signal T0 out
of the decoder. T0 is active during one clock cycle. SC is incremented with
every positive clock transition, unless its clear (CLR) input is active. This
produces the sequence of timing signals T0, T1, T2, T3, T4, and so on. If
SC is not cleared, the timing signals will continue with T5, T6, up to T15
and back to T0. For example, suppose that SC is incremented so that it
provides timing signals T0, T1, T2, T3, and T4 in sequence. At time T4, SC

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is cleared to 0 if the decoder output D3 is active. This is expressed

symbolically by the statement D3T4: SC ← 0.

A memory read or write cycle will be initiated with the rising edge of a
timing signal. It will be assumed that a memory cycle time is less than the
clock cycle time. According to this assumption, a memory read or write
cycle initiated by a timing signal will be completed by the time the next
clock goes through its positive transition. The clock transition will then be
used to load the memory word into a register.
To understand the operation of the computer, it's necessary to understands
the timing relationship between the clock transition and the timing signals.
For example, the register transfer statement T0: AR ← PC specifies a
transfer of the content of PC into AR if timing signal T0 is active. T0 is
active during an entire clock cycle interval. During this time the content of
PC is placed onto the bus (with S2S1S0 = 010) and the LD (load) input of
AR is enabled. The actual transfer does not occur until the end of the clock
cycle when the clock goes through a positive transition. This same positive
clock transition increments the sequence counter SC from 0000 to 0001.

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The next clock cycle has T1 active and T0 inactive.

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