Module 1 VLSI Design(18EC72)

MODULE 1
SYLLABUS:
Introduction: A Brief History, MOS Transistors, CMOS Logic (1.1 to 1.4 of TEXT2)
MOS Transistor Theory: Introduction, Long-channel I-V Characteristics, Non-ideal I-V
Effects, DC Transfer Characteristics (2.1, 2.2, 2.4 and 2.5 of TEXT2).

Table of Contents
1.1. Introduction ..................................................................................................................... 2
1.2. MOS Transistor as a switch: ........................................................................................... 4
1.3. CMOS Logic ................................................................................................................... 4
1.3.1. The Inverter............................................................................................................................... 4
1.3.2. The NAND Gate ......................................................................................................................... 5
1.3.3. The NOR Gate............................................................................................................................ 5
1.3.4. Compound Gates ...................................................................................................................... 6
1.4. Pass Transistors and Transmission Gates ....................................................................... 7
1.5. Tristates ........................................................................................................................... 8
1.6. Multiplexers .................................................................................................................. 10
1.7. Sequential Circuits ........................................................................................................ 10
1.8. MOS Transistors ........................................................................................................... 12
1.8.1. Structure of nMOS transistor .................................................................................................. 13
1.8.2. Structure of pMOS transistor .................................................................................................. 17
1.9. Long-Channel I-V Characteristics ................................................................................ 21
1.10. Nonideal I-V Effects ..................................................................................................... 23
1.10.1. Mobility Degradation and Velocity Saturation ....................................................................... 23
1.10.2. Channel Length Modulation ................................................................................................... 24
1.10.3. Threshold Voltage Effects ....................................................................................................... 25
1.10.4. Drain-Induced Barrier Lowering (DIBL) ................................................................................... 26
1.11. CMOS Inverter DC Characteristics .............................................................................. 28
1.11.1. βn/βp Ratio ............................................................................................................................... 32
1.11.2. Noise Margin ........................................................................................................................... 33
1.12. Pass Transistor DC Characteristics ............................................................................... 35

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1.13. Question Bank ............................................................................................................... 38

TEXT, REFERENCE & ADDITIONAL REFERENCE BOOKS

Book Title/Authors/Publication /Web links/Channel

“CMOS Digital Integrated Circuits: Analysis and Design” - Sung Mo Kang &
T-1.
Yosuf Leblebici, Third Edition, Tata McGraw-Hill.

“CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H. E. Weste,

T-2.
and David Money Harris4th Edition, Pearson Education.

1.1. Introduction
➢ Silicon (Si) forms the basic starting material for most integrated circuits. Silicon is a
group IV element of the periodic table, so it forms covalent bonds with four adjacent
atoms, as shown in Fig.1.1 (a).
➢ Valence electrons of silicon are involved in chemical bonds; pure silicon is a poor
conductor.

Fig.1.1: Silicon and dopant atoms

➢ The conductivity can be raised by introducing small amounts of impurities, called
dopants, into the silicon lattice.
➢ A dopant from Group V of the periodic table, such as arsenic, has five valence electrons.
It replaces a silicon atom in the lattice and still bonds to four neighbors, so the fifth
valence electron is loosely bound to the arsenic atom, as shown in Fig.1.1 (b).

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➢ Thermal vibration of the lattice at room temperature is enough to set the electron free to
move, leaving a positively charged As+ ion and a free electron.
➢ The free electron can carry current so the conductivity is higher. We call this an n-type
semiconductor because the free carriers are negatively charged electrons.
➢ Similarly, a dopant from Group III of the periodic table, such as boron, has three valence
electrons, as shown in Fig.1.1 (c). The dopant atom can borrow an electron from a
neighboring silicon atom, which in turn becomes short by one electron. That atom in turn
can borrow an electron, and so forth, so the missing electron, or hole, can propagate
about the lattice. The hole acts as a positive carrier so we call this a p-type
semiconductor.
➢ A Metal-Oxide-Semiconductor (MOS) structure is created by superimposing several
layers of conducting and insulating materials to form a sandwich-like structure.
➢ These structures are manufactured using a series of chemical processing steps involving
oxidation of the silicon, selective introduction of dopants, and deposition and etching of
metal wires and contacts.
➢ CMOS technology provides two types of transistors (also called devices): an n-type
transistor (nMOS) and a p-type transistor (pMOS) as shown in Fig.1.2.
➢ Transistor operation is controlled by electric fields so the devices are also called Metal
Oxide Semiconductor Field Effect Transistors (MOSFETs) or simply FETs.

Fig.1.2: MOSFET
➢ The n+ and p+ regions in fig.1.2 indicate heavily doped n- type or p-type silicon.
➢ Each transistor consists of a stack of the conducting gate, an insulating layer of silicon
dioxide (SiO2), and the silicon wafer, also called the substrate or body or bulk.

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➢ Gates of early transistors were built from metal, so the stack was called metal-oxide-
semiconductor, or MOS. Since the 1970s, the gate has been formed from polycrystalline
silicon (known as polysilicon).
➢ An nMOS transistor is built with a p-type body and has regions of n-type semiconductor
adjacent to the gate called the source and drain.
➢ A pMOS transistor is just the opposite, consisting of p-type source and drain regions with
an n-type body.
➢ The gate is a control input: It affects the flow of electrical current between the source and
drain.

1.2. MOS Transistor as a switch:

MOS transistors can be viewed as simple ON/OFF switches. When the gate of an nMOS
transistor is 1, the transistor is ON and there is a conducting path from source to drain. When the
gate is low, the nMOS transistor is OFF and almost zero current flows from source to drain. A
pMOS transistor is just the
opposite, being ON when the
gate is low and OFF when the
gate is high. This switch model
is illustrated in Fig 1.3, where g,
s, and d indicate gate, source,
and drain.
Fig 1.3 Transistor symbols and switch-level models

1.3. CMOS Logic

1.3.1. The Inverter
Figure 1.4 shows the schematic and
symbol for a CMOS inverter or NOT
gate using one nMOS transistor and one
pMOS transistor. The bar at the top
indicates VDD and the triangle at the bottom indicates GND. When the input
A is 0, the nMOS transistor is OFF and the pMOS transistor is ON. Thus, the

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output Y is pulled up to 1 because it is connected to VDD but not to GND. Conversely, when A
is 1, the nMOS is ON, the pMOS is OFF, and Y is pulled down to ‘0.’ This is summarized in
Table 1.1.

1.3.2. The NAND Gate

Figure 1.5(a) shows a 2-input CMOS NAND gate. It consists of two series nMOS transistors

between Y and GND and two parallel pMOS transistors between

Y and VDD. If either input A or B is 0, at least one of the nMOS
transistors will be OFF, breaking the path from Y to GND. But at
least one of the pMOS transistors will be ON, creating a path
from Y to VDD. Hence, the output Y will be 1. If both inputs are 1, both of the nMOS transistors
will be ON and both of the pMOS transistors will be OFF. Hence, the output will be 0. The truth
table is given in Table 1.2 and the symbol is shown in Figure 1.5(b).

1.3.3. The NOR Gate

A 2-input NOR gate is
shown in Figure 1.6. The
nMOS transistors are in
parallel to pull the output
low when either input is
high. The pMOS
transistors are in series to pull the output high when both inputs
are low, as indicated in Table 1.4.

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The inverter, NAND and NOR gates are examples of static CMOS logic gates, also called
complementary CMOS gates. In general, a static CMOS gate has an nMOS pull-down network
to connect the output to 0 (GND) and pMOS pull-up network to connect the output to 1 (VDD),
as shown in Fig 1.7. The networks are arranged such that one is ON and the other OFF for any
input pattern.

Fig. 1.7: General logic gate using

pull-up and pull-down networks

1.3.4. Compound Gates

A compound gate performing a more complex logic function in a single stage of logic is formed
by using a combination of series and parallel switch structures. For example, the derivation of
the circuit for the function 𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴. 𝐵) + (𝐶. 𝐷) is shown in Fig 1.8. This function is sometimes
called AND-OR-INVERT-22, or AOI22 because it performs the NOR of a pair of 2-input ANDs.
For the nMOS pull-down network, take the uninverted expression ((A · B) + (C · D)) indicating
when the output should be pulled to ‘0.’ The AND expressions (A · B) and (C · D) may be
implemented by series connections of switches, as shown in Fig 1.8(a). Now ORing the result
requires the parallel connection of these two structures, which is shown in Fig 1.8(b). For the
pMOS pull-up network, we must compute the complementary expression using switches that
turn on with inverted polarity. By DeMorgan’s Law, this is equivalent to interchanging AND and
OR operations. Hence, transistors that appear in series in the pull-down network must appear in

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parallel in the pull-up network. Transistors that appear in parallel in the pulldown network must
appear in series in the pull-up network. In the pull-up network, the parallel combination of A and
B is placed in series with the parallel combination of C and D. This progression is evident in Fig
1.8(c) and Fig 1.8(d). Putting the networks together yields the full schematic (Fig 1.8(e)). The
symbol is shown in Fig 1.8(f ).

Fig 1.8 CMOS compound gate for function 𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅

(𝐴. 𝐵) + (𝐶. 𝐷)

1.4. Pass Transistors and Transmission Gates

When an nMOS or pMOS is used alone as a switch, it is called a pass transistor An nMOS
transistor is an almost perfect switch when passing a 0 and thus it passes a strong 0. However,
the nMOS transistor is imperfect at passing a 1. The high voltage level is somewhat less than
VDD, and hence it passes a degraded or weak 1. A pMOS transistor has the opposite behavior of
passing strong 1s but degraded 0s. The transistor symbols and behaviors are summarized in Fig
1.9 with g, s, and d indicating gate, source, and drain.

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Fig 1.9 Pass transistor strong and degraded outputs

By combining an nMOS and a pMOS transistor in parallel (Fig 1.10(a)), we obtain a switch that
turns on when a 1 is applied to g (Figure 1.10(b)) in which 0s and 1s are both passed in an
acceptable fashion (Fig 1.10(c)). We term this a transmission gate or pass gate. Note that both
the control input and its complement are required by the transmission gate. This is called double
rail logic. Some circuit symbols for the transmission gate are shown in Fig 1.10(d).

Fig 1.10 Transmission gate

In complementary CMOS circuits, the nMOS transistors only need to pass 0s and the pMOS only
pass 1s, so the output is always strongly driven and the levels are never degraded. This is called a
fully restored logic gate and simplifies circuit design considerably. Moreover, there is never a
path through ‘ON’ transistors from the 1 to the 0 supplies for any combination of inputs.

1.5. Tristates

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Fig 1.11 shows symbols for a tristate buffer. When the enable input EN is 1, the output Y equals

the input A. When the EN is 0, Y is left floating (a ‘Z’ value). This is summarized in Table

1.5.

Fig 1.11 Tristate buffer symbol

The transmission gate in Fig 1.12 has the same truth table as a
tristate buffer. It only requires two transistors but it is a nonrestoring
circuit. If the input is noisy or otherwise degraded, the output will
receive the same noise.
Fig 1.13(a) shows a tristate inverter. The output is actively driven
from VDD or GND, so it is a restoring logic gate. Unlike any of the gates considered so far, the
tristate inverter does not obey the conduction complements rule because it allows the output to
float under certain input combinations. When EN is 0 (Fig 1.13(b)), both enable transistors are
OFF, leaving the output floating. When EN is 1 (Fig 1.13(c)), both enable transistors are ON.
They are conceptually removed from the circuit, leaving a simple inverter. Fig 1.13(d) shows
symbols for the tristate inverter. A tristate buffer can be built as an ordinary inverter followed by
a tristate inverter.

Fig 1.13 Tristate Inverter

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1.6. Multiplexers
A multiplexer chooses the output from among several inputs based on a select signal. A 2-input,
or 2:1 multiplexer, chooses input D0 when the select is 0 and input D1 when the select is 1. The
truth table is given in Table 1.6; the logic function is 𝑌 = 𝑆̅𝐷0 + 𝑆𝐷1 . Two transmission gates
can be tied together to form a compact 2-input multiplexer, as shown in Fig 1.14(a). The select
and its complement enable exactly one of the two transmission gates at any given time. The
complementary select S is often not drawn in the symbol, as shown in Fig 1.14(b). Again, the
transmission gates produce a nonrestoring multiplexer. We could build a restoring, inverting
multiplexer out of the compound gate as shown in Fig 1.15(a). Another is to gang together two
tristate inverters, as shown in Fig 1.15(b).

Fig 1.15 Inverting multiplexer

1.7. Sequential Circuits

Sequential circuits have memory: their outputs depend on both current and previous inputs. A D
latch is transparent when CLK = 1, meaning that Q follows D. It becomes opaque when CLK =
0, meaning Q retains its previous value and ignores changes in D. An edge-triggered flip-flop
copies D to Q on the rising edge of CLK and remembers its old value at other times.
Latches - A D latch built from a 2-input multiplexer and two inverters is shown in Fig 1.16(a).
The multiplexer can be built from a pair of transmission gates, shown in Fig 1.16(b), because the
inverters are restoring. This latch also produces a complementary output, Q. When CLK = 1, the
latch is transparent and D flows through to Q (Fig 1.16(c)). When CLK falls to 0, the latch
becomes opaque. A feedback path around the inverter pair is established (Fig 1.16(d)) to hold the

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current state of Q indefinitely. The D latch is also known as a level-sensitive latch because the
state of the output is dependent on the level of the clock signal, as shown in Fig 1.16(e).

Fig 1.16 CMOS positive-level-sensitive D latch

Flip-Flops - By combining two level-
sensitive latches, one negative-sensitive
and one positive-sensitive, we construct
the edge-triggered flip-flop shown in

Fig 1.17(a–b). The first latch stage is

called the master and the second is

called the slave. While CLK is low, the
master negative-level-sensitive latch
output (QM) follows the D input while
the slave positive-level-sensitive latch
holds the previous value (Fig 1.17(c)).
When the clock transitions from 0 to 1,
the master latch becomes opaque and
holds the D value at the time of the
clock transition. The slave latch
becomes transparent, passing the stored
master value (QM) to the output of the

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slave latch (Q). The D input is blocked from

affecting the output because the
master is disconnected from the D input
(Fig 1.17(d)). When the clock transitions from 1 to 0, the slave latch holds its value and the
master starts sampling the input again.
1.8. MOS Transistors
Structure of MOS layer

➢ Metal Oxide Semiconductor comprises of three layers, the top layer is a good conductor
called the gate, the middle layer is a very thin insulating film of SiO2 called the gate
oxide and the bottom layer is the doped silicon body. The Fig.1.18 shows a p-type body
in which the carriers are holes.

➢ Normally the body is grounded and a voltage is applied to the gate. As the gate oxide is a
good insulator, almost zero current flows from the gate to the body.

➢ A negative voltage is applied to the gate, so there is negative charge on the gate. The
positively charged holes are attracted to the region beneath the gate. This is called the
accumulation mode as shown in Fig.1.18 (a).

➢ In Fig.1.18 (b), a small positive voltage is applied to the gate, resulting in some positive
charge on the gate. The holes in the body are repelled from the region directly beneath
the gate, resulting in a depletion region forming below the gate.

➢ In Fig.1.18 (c), a higher positive potential exceeding a critical threshold voltage Vt is

applied, attracting more positive charge to the gate. The holes are repelled further and
some free electrons in the body are attracted to the region beneath the gate. This
conductive layer of electrons in the p-type body is called the inversion layer.

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Fig.1.18: MOS structure demonstrating (a) accumulation, (b) depletion, and (c) inversion

1.8.1. Structure of nMOS transistor

➢ nMOS enhancement transistor as shown in the Fig.1.19 consists of lightly doped p-
substrate.
➢ Two highly doped n-type regions are formed in the p-substrate by diffusing n-impurities.
These regions forms the source and drain terminal of the transistor.
➢ A thin layer of silicon dioxide (SiO2) is grown on the surface of the substrate which acts
as an excellent insulator.
➢ A polysilicon gate is deposited above the substrate and is separated from the substrate by
an oxide layer.
➢ Metal contacts are made for gate (G), source (S), drain (D) and substrate (B) regions.

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➢ Substrate (also known as body) region forms p-n junctions with source and drain region
and these p-n junctions are reverse biased.

Operation of nMOS transistor

➢ For transistor operation a channel should be established between source and drain for the
conduction of the majority carries.
➢ To form a channel a positive gate voltage should be applied with respect to source (i.e.
gate to source voltage Vgs).
➢ When a positive gate voltage (Vgs) is applied, an electric field is established between the
gate and the substrate which helps for the inversion of the charges at the gate-substrate
interface.
➢ The holes repel from the interface of gate-substrate region and the electrons from the n+
source and n+ drain region gets attracted towards the interface of gate-substrate region.
➢ When sufficient number of electrons accumulates at the interface of gate-substrate region,
an n-region will be formed between n+ source and n+ drain which acts as a channel for the
current conduction between drain and source.
➢ The channel is created by inverting the interface of gate-substrate region from p-type to
n-type. Hence this induced channel is also called as an inversion layer.
➢ The amount of gate voltage which is required to create a conducting channel between n+
source and n+ drain is called threshold voltage (Vt).

Vgs < Vt

Fig.1.19: Cutoff region of nMOS transistor

➢ Hence the region of operation in which the gate to source voltage (Vgs) is less than
threshold voltage (Vt) is known as cutoff region as shown in Fig.1.19 where the MOS
transistor is in off state.

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➢ Now keep the gate to source voltage (Vgs) constant and apply a small amount of positive
voltage to drain with respect to source (Vds). An electric field is established between the
drain and the source, causing electrons to move from source to drain in the channel.
➢ The current Id will flow from drain to source which is opposite to the flow of electrons.
➢ The magnitude of current Id depends on the density of electrons in the channel which in
turn depends on the magnitude of Vgs.
➢ The current Id will increase if magnitude of Vgs is increased above Vt, This voltage is
called as excess gate voltage (Vgs - Vt) also called as overdrive voltage (VOV).
➢ The voltage Vds appears as a voltage drop across the length of the channel. The voltage
between the gate and the points along the channel decreases from Vgs at the source end to
Vgs – Vds at the drain end.
➢ Since the channel depth depends on this voltage, we find that the channel is no longer of
uniform depth; rather, the channel will take the tapered form.
➢ As Vds is increased further, the channel becomes more tapered and its resistance increases
correspondingly.

Fig.1.20: Linear region of nMOS transistor

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➢ The device is said to operate in linear region (triode region) if Vds < Vdssat as shown in
the Fig1.20.
➢ When Vds is increased further it reduces the voltage between gate and channel at the drain
end to Vt, i.e, Vgd = Vt, or Vgs – Vds = Vt or Vds = Vgs - Vt, the channel depth at the drain
end decreases to almost zero, and the channel is now said to be pinched off.
➢ Increasing Vds further shifts the pinch-off point towards the source region, and the current
through the channel remains constant at the value obtained for Vds = Vgs - Vt.
➢ The drain current thus saturates at this value, and the MOSFET is said to have entered the
saturation region of operation.
➢ The voltage Vds at which saturation occurs is denoted Vdssat and Vdssat = Vgs - Vt.
➢ The device operates in the saturation region if Vds ≥ Vdssat as shown in the Fig1.21

Fig.1.21: Saturation region of nMOS transistor

➢ Thus the Id - Vds curve does not continue as a straight line but bends eventually as shown
in Fig.1.22.

Fig.1.22: Id - Vds characteristics of nMOS with regions of operations

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1.8.2. Structure of pMOS transistor

➢ pMOS enhancement transistor is as shown in the Fig.1.23 which consists of lightly doped
n-substrate.
➢ Two highly doped p-type regions are formed in the n-substrate by diffusing p-impurities.
These regions forms the source and drain terminal of the transistor.
➢ A thin layer of silicon dioxide (SiO2) is grown on the surface of the substrate which acts
as an excellent insulator.
➢ A polysilicon gate is deposited above the substrate and is separated from the substrate by
an oxide layer.
➢ Metal contacts are made for gate (G), source (S), drain (D) and substrate (B) regions.
➢ Substrate (also known as body) region forms pn junctions with source and drain region
and these pn junctions are reverse biased.

Gate

Source Drain
Polysilicon

p+ p+ Diffusion Region
Depletion Region

Oxide
n-substrate layer

Metal

Body
Fig. 1.23: Structure of pMOS enhancement transistor

Operation of pMOS transistor

➢ To form a channel a negative gate voltage should be applied with respect to source (i.e.
gate to source voltage Vgs).
➢ When a negative gate voltage (Vgs) with source connected to ground is applied, an
electric field is established between the gate and the substrate. The vertical component of
the electric field helps for the inversion of the charges at the gate-substrate interface.

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➢ The electrons repel from the interface of gate-substrate region and the holes from the p+
source and p+ drain region gets attracted towards the interface of gate-substrate region.
➢ When sufficient number of holes accumulates at the interface of gate-substrate region, a
p-region will be formed between p+ source and p+ drain which acts as a channel for the
current conduction from drain to source.
➢ The channel is created by inverting the interface of gate-substrate region from n-type to
p-type. Hence this induced channel is also called as an inversion layer.
➢ The amount of gate voltage which is required to create a conducting channel between p+
source and p+ drain is called threshold voltage (Vt).

S D

p+ p+

n-substrate

Vgs > Vt
Fig. 1.24: Cutoff region of pMOS transistor
➢ Hence the region of operation in which the gate to source voltage (Vgs) is greater
than threshold voltage (Vt) is known as cutoff region as shown in Fig 1.24 where the
MOS transistor is in off state.
➢ Now keep the gate to source voltage (Vgs) constant and apply a small amount of negative
voltage to drain with respect source (Vds). An electric field is established between the
drain and the source, acting towards source terminal which supplies energy to the holes
present in the source.
➢ The holes move towards drain, which causes a small amount of current Id to flow in the
channel.
➢ The current Id will flow from source to drain which is opposite to the flow of electrons.

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➢ The magnitude of current Id depends on the density of electrons in the channel which in
turn depends on the magnitude of Vgs.
➢ The current Id will decrease if magnitude of Vgs is decreased below Vt, This voltage is
called as excess gate voltage (Vgs - Vt), also called as overdrive voltage (Vov).
➢ The voltage Vds appears as a voltage drop across the length of the channel. The voltage
between the gate and the points along the channel increases from Vgs at the source end to
Vgs - Vds at the drain end.
➢ Since the channel depth depends on this voltage, we find that the channel is no longer of
uniform depth; rather, the channel will take the tapered form.
➢ As Vds is decreased further, the channel becomes more tapered and its resistance
increases correspondingly.
➢ Thus the Id - Vds curve does not continue as a straight line but bends eventually as shown
in Fig.1.27, when Vds is decreased to the value which reduces the voltage between gate
and channel at the drain end to Vt, i.e, Vgd = Vt, or Vgs - Vds = Vt or Vds = Vgs - Vt
➢ The channel depth at the drain end decreases to almost zero, and the channel is said to be
pinched off.
➢ Decreasing Vds further shifts the pinch-off point towards the source region, and the
current through the channel remains constant at the value obtained for Vds = Vgs - Vt.

G G

S D S D

p+ p+ p+ p+

n-substrate nsubstrate

B B

Vgs ≤ Vt; Vds = 0 Vgs ≤ Vt; Vds > Vgs - Vt

Fig. 1.25: Linear region of pMOS transistor

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➢ The drain current thus saturates at this value, and the MOSFET is said to have entered the
saturation region of operation.
➢ The voltage Vds at which saturation occurs is denoted Vdssat and Vdssat = Vgs - Vt.
➢ The device operates in the saturation region if Vds ≤ Vdssat as shown in the Fig 1.26
and it operates in linear region (triode region) if Vds > Vdssat as shown in the Fig. 1.25.

G G

S D S D

p+ p+ p+ p+

n-substrate n-substrate

B B

Vgs ≤ Vt; Vds = Vgs - Vt Vgs ≤ Vt; Vds < Vgs - Vt

Fig. 1.26: Saturation region of pMOS transistor

Fig. 1.27: Id – Vds characteristics of pMOS with regions of operations

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Symbol of nMOS transistor

D D D D

G G G B G B

S S S S

Fig. 1.28: Symbol of nMOS transistor

Symbol of pMOS transistor

S S S S

G G G B G B

D D D D

Fig. 1.29: Symbol of pMOS transistor

1.9. Long-Channel I-V Characteristics

Consider a nMOS (Fig. 1.30) and assume that a voltage Vgs is applied between gate and source
with Vgs > Vt to induce a channel. Vgs - Vt is the overdrive voltage and hence the inversion
charge density is proportional to Vgs - Vt.
i.e. Q = CoxW [ Vgs - Vt]
where W -> width of the device, Cox – gate oxide per unit area
Consider voltage Vds is applied between drain and source. First, we shall consider operation in
the triode region, for which the channel must be continuous and thus, Vds < Vgs - Vt.
As there is voltage difference in the channel, at any point x, the charge density can be defined as,
Q(x) = CoxW [ Vgs - V(x) - Vt]
where V(x) is the channel potential at x.
Therefore, current is given by,

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𝐈𝐝𝐬 = - CoxW [ Vgs - V(x) - Vt]v

(-ve sign because conventionl current is opposite of electrons)
where velocity v = 𝛍𝐧 E = 𝛍𝐧 (-dV(x)/dx), and 𝛍𝐧 -> mobility of the electrons.
i.e., 𝐈𝐝𝐬 = CoxW [ Vgs - V(x) - Vt] 𝛍𝐧 (dV(x)/dx)
= 𝛍𝐧 CoxW [ Vgs - V(x) - Vt] (dV(x)/dx)
𝒊. 𝒆. , 𝐈𝐝𝐬 𝐝𝐱 = 𝛍𝐧 𝐂𝐨𝐱 𝐖[𝐕𝐠𝐬 − 𝐕(𝐱) − 𝐕𝐭 ]𝐝𝐯(𝐱)

Fig. 1.30: Derivation of iD - vDS characteristics of the nMOS transistor

Integrating on both sides from x = 0 to x = L and correspondingly for V(0) = 0 to V(L) =

VDS,
𝐋 𝐯𝐃𝐒
∫ 𝐈𝐝𝐬 𝐝𝐱 = ∫ 𝛍𝐧 𝐂𝐨𝐱 𝐖[𝐕𝐠𝐬 − 𝐯(𝐱) − 𝐕𝐭 ]𝐝𝐯(𝐱)
𝟎 𝟎

𝐖 𝟏
𝐈𝐝𝐬 = 𝛍𝐧 𝐂𝐨𝐱 [ (𝐕𝐠𝐬 − 𝐕𝐭 )𝐕𝐝𝐬 − 𝐕𝐝𝐬 𝟐 ]
𝐋 𝟐
The above equation gives the I - V characteristic in the linear (triode) region. The value
of the current at the edge of the triode region or at the beginning of the saturation region can
be obtained by substituting Vds = Vgs – Vt in the above equation
𝐖 𝟏 𝟐
𝐈𝐝𝐬 = 𝛍𝐧 𝐂𝐨𝐱 [ (𝐕𝐠𝐬 − 𝐕𝐭 )(𝐕𝐠𝐬 − 𝐕𝐭 ) − (𝐕𝐠𝐬 − 𝐕𝐭 ) ]
𝐋 𝟐
𝟏 𝐖 𝟐
𝐈𝐝𝐬 = 𝛍𝐧 𝐂𝐨𝐱 (𝐕𝐠𝐬 − 𝐕𝐭 )
𝟐 𝐋

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This equation gives the I - V characteristic in the saturation region.

The triode region and saturation region current can also be expressed as
𝟏
𝐈𝐝𝐬 = 𝛃 [ (𝐕𝐠𝐬 − 𝐕𝐭 )𝐕𝐝𝐬 − 𝐕𝐝𝐬 𝟐 ]
𝟐
𝟐
(𝐕𝐠𝐬 − 𝐕𝐭 )
𝐈𝐝𝐬 =𝛃
𝟐
𝐖
where, 𝛃 = 𝛍𝐧 𝐂𝐨𝐱 𝐋

1.10. Nonideal I-V Effects

The long-channel I-V model neglects many effects that are important to devices with channel
lengths below 1 micron.
1.10.1. Mobility Degradation and Velocity Saturation
We know that, V = µE, where V- velocity of charge carriers, µ - mobility of charge carriers and
E – electric field
But when we increase the electric field beyond EC
called critical field, the velocity of the charge carrier
does not change with electric field as shown in
Figure 3. In MOSFETs when electrical field along
the channel reaches a critical value the velocity of
carriers tends to saturate and the mobility degrades.
As the velocity increases, it scatters the charge
carriers. This scattering in transverse direction works
against the electric field in the longitudinal direction. As a result the velocity becomes saturated

where, by continuity, the critical electric field is

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A high voltage at the gate of the transistor attracts the carriers to the edge of the channel, causing
collisions with the oxide interface that slow the carriers. This is called mobility degradation

1.10.2. Channel Length Modulation

The saturation-region relationship between gate-to-source voltage (VGS) and drain current (Ids) is
expressed as follows
𝟏 𝐖 𝟐
𝐈𝐝𝐬 = 𝟐 𝛍𝐧 𝐂𝐨𝐱 (𝐕𝐠𝐬 − 𝐕𝐭 )
𝐋

Ideally, Ids is independent of Vds for a transistor in saturation, making the transistor a perfect
current source. But as we know, the p–n junction between the drain and body forms a depletion
region with a width L that increases with Vds , as shown in Fig 1.33. The depletion region
effectively shortens the channel length to L-L.

Fig 1.33 Channel Length Modulation

Hence practically the current in the saturation region does not remain constant as shown in
Figure 5. The effective channel length gets modulated by Vds and hence the drain current is given
by,
𝐈𝐝𝐬
𝟏 𝐖 𝟐
= 𝛍𝐧 𝐂𝐨𝐱 (𝐕𝐠𝐬 − 𝐕𝐭 ) (𝟏 + Vds )
𝟐 𝐋

where  - channel length modulation parameter (generally <1)

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Figure 5 : Drain current with CLM

1.10.3. Threshold Voltage Effects

The threshold voltage, Vt increases with the source voltage, decreases with the body voltage,
decreases with the drain voltage, and increases with channel length].
Body Effect
In I-V analysis we assumed that the bulk and
source of transistor were tied to ground, what
happens if the bulk voltage of NMOS is drops
below the source voltage? To understand this
effect suppose VS = 0 and VD = 0 and VG is
somewhat less than VTH so that depletion region is
formed under the gate but inversion channel does
not exist as shown in the Figure (a). As VB
becomes more negative (i.e. VB < VS where VS =
0) more holes are attracted to the substrate
connection leaving a larger negatively charged
ions behind i.e. the depletion region becomes
wider as shown in Figure (b). As we know that the

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threshold voltage is a function of the total charge in the depletion region, thus as the body
voltage VB drops then depletion charge increases which increases the threshold voltage (VTH).
This effect is called as the body effect
. The threshold voltage can be modeled as

where Vt0 is the threshold voltage when the source is at the body potential, ϕs is the surface
potential at threshold, and γ is the body effect coefficient.
1.10.4. Drain-Induced Barrier Lowering (DIBL)
The drain voltage Vds creates an electric field that affects the threshold voltage. This drain-
induced barrier lowering (DIBL) effect is especially pronounced in short-channel transistors. It
can be modeled as

where η is the DIBL coefficient.

Drain-induced barrier lowering causes Ids to increase with Vds in saturation, in much the same
way as channel length modulation does.
Short Channel Effect
The threshold voltage typically increases with channel length. This phenomenon is especially
pronounced for small L where the source and drain depletion regions extend into a significant
portion of the channel, and hence is called the short channel effect or Vt rolloff.
Leakage
Even when transistors are nominally OFF, they leak small
amounts of current. Leakage mechanisms include subthreshold
conduction between source and drain, gate leakage from the
gate to body, and junction leakage from source to body and drain
to body, as illustrated in Fig 1.34. Subthreshold conduction is
caused by thermal emission of carriers over the potential barrier
set by the threshold. Gate leakage is a quantum-mechanical
effect caused by tunneling through the extremely thin gate
dielectric. Junction leakage is caused by current through the p-n
junction between the source/drain diffusions and the body.

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Subthreshold Leakage The long-channel transistor I-V model assumes current only flows from
source to drain when Vgs > Vt. In
real transistors, current does not
abruptly cut off below threshold,
but rather drops off exponentially,
as seen in Fig 1.35. When the gate
voltage is high, the transistor is
strongly ON. When the gate falls
below Vt, the exponential decline in
current appears as a straight line on
the logarithmic scale. This regime
of Vgs < Vt is called weak
inversion. The subthreshold leakage
current increases significantly with Vds because of drain-induced barrier lowering.
Gate Leakage According to quantum mechanics, the electron cloud surrounding an atom has a
probabilistic spatial distribution. For gate oxides thinner than 15–20 Å, there is a nonzero
probability that an electron in the gate will find itself on the wrong side of the oxide, where it
will get whisked away through the channel. This effect of carriers crossing a thin barrier is called
tunneling, and results in leakage current through the gate.
Junction Leakage The p–n
junctions between diffusion
and the substrate or well
form diodes, as shown in
Fig 1.36. The well-to-
substrate junction is another diode. The substrate and well are tied to GND or VDD to ensure
these diodes do not become forward biased in normal operation. However, reverse-biased diodes
still conduct a small amount of current ID.
Temperature Dependence
Transistor characteristics are influenced by temperature. Carrier mobility decreases with
temperature. An approximate relation is

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where T is the absolute temperature, Tr is room temperature, and kμ is a fitting parameter with a
typical value of about 1.5. vsat also decreases with temperature, dropping by about 20% from
300 to 400 K. The magnitude of the threshold voltage decreases nearly linearly with temperature.
At high Vgs, the current has a negative temperature coefficient; i.e., it decreases with
temperature. At low Vgs, the current has a positive temperature coefficient. Thus, OFF current
increases with temperature. ON current Idsat normally decreases with temperature.
Geometry Dependence
The layout designer draws transistors with width and length Wdrawn and Ldrawn. The actual
gate dimensions may differ by some factors XW and XL. For example, the manufacturer may
create masks with narrower polysilicon or may overetch the polysilicon to provide shorter
channels (negative XL) without changing the overall design rules or metal pitch. Moreover, the
source and drain tend to diffuse laterally under the gate by LD, producing a shorter effective
channel length that the carriers must traverse between source and drain. Similarly, WD accounts
for other effects that shrink the transistor width. Putting these factors together, we can compute
effective transistor lengths and widths that should be used in place of L and W in the current and
capacitance equations given elsewhere in the book. The factors of two come from lateral
diffusion on both sides of the channel.

1.11. CMOS Inverter DC Characteristics

➢ For the static CMOS inverter shown in Fig.1.37, Vtn is the threshold voltage of the n-
channel device, and Vtp is the threshold voltage of the p-channel device. Note that Vtn is
positive and Vtp is negative.

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Fig. 1.37: CMOS inverter

➢ The source of the nMOS transistor is grounded, hence Vgsn = Vin and Vdsn = Vout.
➢ The source of the pMOS transistor is tied to VDD, hence Vgsp = Vin – VDD and Vdsp = Vout
– VDD.
➢ The operating conditions of CMOS inverter in three regions is given by the following
expressions

Cutoff Linear Saturation

Vgsn ≥ Vtn Vgsn ≥ Vtn
Vgsn < Vtn Vin ≥ Vtn Vin ≥ Vtn
nMOS
Vin < Vtn Vdsn < Vgsn - Vtn Vdsn ≥ Vgsn - Vtn
Vout < Vin - Vtn Vout ≥Vin - Vtn
Vgsp ≤ Vtp Vgsp ≤ Vtp
Vgsp > Vtp Vin ≤ Vtp + VDD Vin ≤ Vtp + VDD
pMOS
Vin > Vtp + VDD Vdsp > Vgsp - Vtp Vdsp ≤ Vgsp - Vtp
Vout > Vin - Vtp Vout ≤ Vin - Vtp
Graphical derivation of CMOS inverter characteristics
➢ First the characteristics of pMOS and nMOS are plotted for different values of Vgs and
Vds as shown in the Fig. 1.38.

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Fig. 1.38: Id - Vds characteristics of pMOS and nMOS

➢ Absolute value of drain current for pMOS transistor is obtained, which inverts the
characteristics (i.e. characteristics is reflected over the horizontal axis) as shown in the
Fig.1.39. Vgs of pMOS transistor is balance by adding VDD to Vgs.

Fig.1.39: Characteristics of pMOS is reflected over the horizontal axis

➢ The characteristics of pMOS are now superimposed on the characteristics of nMOS as
shown in the Fig.1.40. Vds of pMOS transistor is balance by adding VDD to Vds

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Fig.1.40: Superimposition of pMOS and nMOS characteristics

➢ The transfer curve of CMOS inverter is now determined by the taking common Vgs
intersection points from fig.1.21 as shown in the Fig.1.41.

Fig.1.41: CMOS inverter characteristics

➢ The CMOS inverter characteristic is obtained and the operation of CMOS inverter can be
divided into five regions as shown in the Fig.1.42.

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Fig.1.42: CMOS inverter characteristics with different regions of operation

CMOS inverter operation can be summarized as follows

Region Condition pMOS nMOS Output

A 0 ≤ Vin < Vtn Linear Cutoff Vout = VDD
Decrease in output but greater
B Vtn ≤ Vin < VDD /2 Linear Saturation
than VDD /2
C Vin = VDD /2 Saturation Saturation Output drops sharply
Decrease in output but lesser
D VDD /2 < Vin ≤ VDD + Vtp Saturation Linear
than VDD /2
E VDD + Vtp < Vin ≤ VDD Cutoff Linear Vout = 0

1.11.1. βn/βp Ratio

➢ When beta ratio changes, the switching threshold also changes. If βp = βn, the switching
threshold voltage Vinv is VDD/2.
➢ Inverters with different beta ratios βp / βn are called skewed inverters and its
characteristics are shown in Fig.1.43.

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Fig.1.43: CMOS inverter with different βn/βp ratio

➢ If βp / βn > 1, the inverter is HI-skewed.
➢ If βp / βn < 1, the inverter is LO-skewed.
➢ If βp / βn = 1, the inverter has normal skew or is unskewed.

1.11.2. Noise Margin

➢ Noise margin allow us to determine the allowable noise voltage on the input of the gate
so that the output will not be corrupted.
➢ Noise margin is determined by two parameters
1. Low Noise Margin NML
2. High Noise Margin NMH
➢ Noise margin is determined as shown in the Fig.1.44.
➢ Low Noise Margin is defined as the difference in maximum LOW input voltage
recognized by the receiving gate and the maximum LOW output voltage produced by the
driving gate.
NML = VIL – VOL

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Fig.1.44: Noise Margin of a CMOS gate

➢ High Noise Margin is defined as the difference between the minimum HIGH output
voltage of the driving gate and the minimum HIGH input voltage recognized by the
receiving gate.
NMH = VOH – VIH 1.39
where,
VIH = minimum HIGH input voltage
VIL = maximum LOW input voltage
VOH = minimum HIGH output voltage
VOL = maximum LOW output voltage
➢ For calculating noise margins from the transfer characteristic of the inverter the different
voltage levels VIL, VOL, VIH, and VOH are as shown in Fig. 1.45.

Fig.1.45: CMOS inverter noise margins

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1.12. Pass Transistor DC Characteristics

➢ CMOS transmission gate consists of an nMOS transistor and pMOS transistor with
separate gate connections and common source and drain connections as shown in the
Fig.1.46.

Fig.1.46: CMOS transmission gate

➢ A control signal is applied to the gate of the nMOS transistor and its compliment is
applied to the gate of pMOS transistor.
➢ To study the operation of transmission gate, a load capacitance is considered and it’s
charging and discharging is controlled by transmission gate.
➢ Consider the nMOS transistor and pMOS transistor separately as a pass transistor and the
current flow direction is controlled by transmission gate.
Operation of nMOS pass transistor
➢ nMOS pass transistor (Fig 1.47) is turned on by applying the gate voltage higher than the
either terminal voltage by the threshold voltage and is turned off by applying the gate
voltage lower than the either terminal voltage by the threshold voltage.

Fig.1.47: nMOS pass transistor

➢ To turn on Vg > Vin + Vt or Vg > Vout + Vt (i.e. Vgs > Vt)
➢ To turn off Vg < Vin + Vt or Vg < Vout + Vt (i.e. Vgs < Vt)
➢ To analyze the operation consider three cases
case (I): Vg = 0V (or S = 0V); Vin = 0V or 5V; Vout = 0V or 5V
➢ Since Vg is less than the either terminal voltage the transistor is in cutoff state and the
capacitor will hold its charge.

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case (II): Vg = 5V; Vin = 5V; Vout = 0V (initially)

➢ Since Vg is greater than Vout by the threshold voltage the transistor conducts and
capacitor charges.
➢ Since Vin is at higher potential than Vout the current flows through the device from left to
right (i.e. from Vin to Vout).
➢ When the output voltage becomes 5V - Vtn the nMOS transistor enters into cutoff region,
hence the output remains at 5V - Vtn.
➢ Therefore the transmission of logic one is degraded.
case (III): Vg = 5V; Vin = 0V; Vout = 5V - Vt (initially)
➢ Since Vg is greater than Vin by the threshold voltage the transistor conducts and capacitor
discharges.
➢ Since Vin is at lower potential than Vout the current flows through the device from right to
left (i.e. from Vout to Vin).
➢ The nMOS transistor discharges the output to VSS and the transmission of logic zero is
not degraded.
➢ Since Vg > Vin + Vt always, the output voltage of the nMOS transistor will discharge
completely to zero.
Operation of pMOS pass transistor
➢ pMOS pass transistor (Fig 1.48) is turned on by applying the gate voltage lower than the
either terminal voltage by the threshold voltage and is turned off by applying the gate
voltage higher than the either terminal voltage by the threshold voltage.

Fig.1.48: pMOS pass transistor

➢ To turn on Vg < Vin + Vt or Vg < Vout + Vt (i.e. Vgs < Vt)
➢ To turn off Vg > Vin + Vt or Vg > Vout + Vt (i.e. Vgs > Vt)
➢ To analyze the operation consider three cases
case (I): Vg = 5V (or S = 5V); Vin = 0V or 5V; Vout = 0V or 5V

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➢ Since Vg is greater than the either terminal voltage the transistor is in cutoff state and the
capacitor will hold its charge.
case (II): Vg = 0V; Vin = 5V; Vout = 0V (initially)
➢ Since Vg is lesser than Vin by the threshold voltage the transistor conducts and capacitor
charges.
➢ Since Vin is at higher potential than Vout the current flows through the device from left to
right (i.e. from Vin to Vout).
➢ The pMOS transistor charges the output to 5V and the transmission of logic one is not
degraded.
➢ Since Vg < Vout + Vt always, the output voltage of the pMOS transistor will charge
completely to 5V.
case (III): Vg = 0V; Vin = 0V; Vout = 5V (initially)
➢ Since Vg is less than Vout by the threshold voltage the transistor conducts and capacitor
discharges.
➢ Since Vin is at lower potential than Vout the current flows through the device from right to
left (i.e. from Vout to Vin).
➢ When the output voltages reaches Vout = Vt the pMOS transistor enters into cutoff region,
hence the output remains at Vt.
➢ Therefore the transmission of logic zero is degraded.
The operation of pass transistor can be summarized as

Device Transmission of ‘1’ Transmission of ‘0’

n poor good
p good poor
The operation of transmission gate can be summarized as

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➢ When nMOS pass transistor are connected in series with VDD as input then at the nth stage
output will be VDD - Vtn as shown in the Fig.1.49.

Fig.1.49 Voltage degradation of pass transistor when connected in series

➢ When nMOS pass transistor is driving an nMOS pass transistor with VDD as input then at
the nth stage output will be VDD - nVtn. For two stage output will be VDD - 2Vtn as shown
in the Fig.1.50.

Fig.1.50: Voltage degradation of pass transistor when output is driving next stage

1.13. Question Bank

1. With necessary circuit diagram, explain the operation of tristate inverter. Also realize a
2:1 multiplexer using tristate inverter.
2. Implement a D flipflop using transmission gates and explain its operation with necessary
timing diagram
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3. Realise CMOS compound gate for the function ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅

𝐴(𝐵 + 𝐶) + 𝐷𝐸
4. Derive the CMOS inverter DC characteristics graphically from p device and n device
characteristics and show all operating regions.
5. Explain the nMOS enhancement mode transistor operation for different values of Vgs and
Vds with neat diagrams.
6. Derive a first order expression relating the current and voltage (I-V) for an NMOS
transistor in linear region.
7. Explain only two non ideal I-V effects in a MOS device.
8. Explain noise margin with respect to CMOS inverter.
9. Explain the following:
i) Channel length modulation
ii) Noise Margin
iii) Mobility Degradation
10. Explain body effect as non -ideal I-V effects of MOSFET.
11. Draw the CMOS logic schematic for a compound gate:
12. Explain with example why NMOS pass transistor is said to pass a strong 0 and PMOS a
strong 1.
13. Explain the working of a tristate buffer with neat circuit diagrams.
14. Realize a 2:1 multiplexer using tristate buffer.
15. Realize a negative sensitive D-latch using CMOS logic.
16. Sketch a transistor-level schematic for a CMOS 4-input NOR gate.
17. Sketch a transistor-level schematic for a compound CMOS logic gate for each of
the following functions:

18. Use a combination of CMOS gates (represented by their symbols) to generate the
following functions from A, B, and C.

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19. Sketch a transistor-level schematic of a CMOS 3-input XOR gate. You may assume
you have both true and complementary versions of the inputs available.

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