16 Bit Microprocessor Architecture Analysis Using VHDL

Volume 8, Issue 1, January – 2023 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
16 Bit Microprocessor Architecture

Analysis using VHDL
Kale Swarnita Gorakshanth 1 ,Donagre Avinash Sudhakar 2, Kale Gorakshnath Bhgwatrao3
1,2
Professor, 3Vice-Principal & HOD,
Department of Computer Technoogy, Amrutvahini Polytechnic, Sangamner
Abstract:- This paper involves the design and different levels of abstraction, from system through to
simulation of 16 bit microprocessor architecture on logic gates. At each level of this hierarchy the overall
FPGA using VHDL. Significant features such as the , inputs and outputs remain the same but the functionality of
increased speed ,minimal implementation real-estate, distinct sections become clearer with the help of detailed
reduction in power and maximum configurability are schematics.
provided by several FPGAs. Where earlier a design
may have included 6 to 10 ASICs, but today the same IC design indulges in more complex computations as
design can be achieved using only single FPGA.VHDL compare with the software version and found to be time
is used in order to programme FPGA.VHDL is very consuming .The design needed to develop such as
High Speed Integrated Circuit Hardware Description microprocessor of required specification by conventional
Language. This model actually represents the textual approach will lead to reduction in machine cycle, variation
description of a hardware design or a piece of design in data bus size, reduction in cost, and implementation of
which, when simulated mimics the design behaviour all numbering system. After implementing such a system,
.The processor contains a number of basic modules. major questions raises in the shape of its integration and
These modules are register array of 8X16 bit register, optimization. These problems have been eliminated by
an ALU, shift register, program counter , an Field Programmable Gate Array (FPGA) technology and
instruction register ,an address register, a comparator by Hardware Descriptive Language(HDL).The software
and control unit. All of these units or modules are interface along with chip design and planner reduces the
assembled together and communicate through a complexity and enhances the ease of computations
common 16 bit tristate data bus. .[5],[6],[7].
Keywords:- Register transfer level, Reduced instruction set With the proposed design in this paper, the 64 KB
computer(RISC), Very high speed integrated memory is interfaced with the CPU and the minimised
circuit(VHSIC) hardware description language , delay, clock period, path delay are obtained. The proposed
Arithmetic logic unit(ALU), Field programmable gate design has been tested with some application programs of
array(FPGA). memory- related operations (load, store, move, and
branch).
I. INTRODUCTION
II. TECHNICAL WORK PREPARATION
The requirements for the language were being first
generated in 1980s, under the title Very High Speed Various tools are put forth in designing of this
Integrated Circuit (VHSIC) project of US government, in system. In the present case microprocessor is bricked up
order to enhance the electronic technology, design using synthesized operations in the form of objectives and
process, and procurement, as well as the development of broader aspects. Fig. 1.shows the organization of the paper
many advanced IC process technologies. Any hardware design that is needed to implement:
design can be described in terms of its operations at
IJISRT23JAN442 www.ijisrt.com 875

ISSN No:-2456-2165
Application Range
Aims Objectives
Designing 16 bit Design and Simulation of

Microprocessor using various functions as
VHDL arithmetic and logical
16-bit functions.
Microprocessor
Input and Output of 16 bit
Design and simulation of

various control functions
Simulation by using and memory
Xilinx and tested on
FPGA Board
Fig 1. Composition of paper design with aims and objectives.
A. System overview D. Hardware overview

The main focus amongst them for Operational Design , The Fundamental building block of microprocessor is
Software Design and Hardware Design. shown in fig 2. This model instantiates components CPU
and memory and specifies the necessary signals to connect
B. Operational overview the components, as shown in figure below.
The operational view deals with various kinds of
operation which a microprocessor can perform. The CPU
(Central Processing Unit) is the “brain” of computer. It is VMA
composed of several parts , like data path, control path and
memory units. At each clock cycle, Control Unit is needed READY
to generate the control signals automatically for operating
the data path. It is based on the finite state machine concept. R/W
The control unit for a processor basically cycles through CPU MEMORY
three main steps, usually referred to as the instruction cycle ADDR
i.e Fetch an instruction, Decodes the instruction and
Executes the instruction. Second part deals with the DATA
Arithmetic Logic Unit which perform arithmetic
computations such as addition ,subtraction, multiplication,
division, increment, decrement and logical functions such as
AND ,OR , XOR ,left shift ,right shift etc [7].
C. Software overview CLOCK RESET

Interfacing with VHDL software used in this system,
reduces the complexity and also provide the graphic Fig. 2: Hardware representation of 16 bit microprocessor
presentation of the system.VHDL is advantageous when Component mem is a memory device and contains the
used for systems design is that it allows the behavior of the instructions and data for the CPU to execute. Component
required system to be described(modeled) and verified cpu is an RTL implementation of the CPU device that is
(simulated) before synthesis tools translate the design into simulated for correctness and synthesized to implement the
real hardware (gates and wires).This not only indulge in design. It includes clock signal ,reset valid memory
compilation but also produces waveform results. For
address(VMA),address register,ready signal and data is
performing compilation and simulation of any logic circuit
required for operation.A final point is that when a VHDL
design, few sophisticated Computer Aided Design(CAD) model [11] is translated into the "gates and wires" that are
tools such as Alteras II and Xilinx web pack are used [10]. mapped onto a programmable logic device such as a CPLD
or FPGA, and then it is the actual hardware being
configured, rather than the VHDL code being "executed" as
if on some form of a processor chip.

ISSN No:-2456-2165
Instruction register is for storing the instruction being III. RESULTS
fetched from the memory. The program counter holds the
address of the memory of the current instruction. After the Synthesis and simulation of the VHDL code of the
execution of instruction, the program counter move to the processor using Xilinx Software (Version 9.1) is presented.
next instruction. If there is branch instruction, the program The synthesis and simulation results are presented for
counter is loaded with the address of the next instruction . justification .Using Xilinx ISE 9.1 software the code is
Then the value of the program counter is copied by the tested and checked. The simulation results are compared
control unit to the address register, which gives the new with the theoretical results. Before the start of simulation,
address in address bus .The process of storing data into the instructions and data are written and loaded into the
memory is called writing and retrieving data or opcode memory. The processor with memory is tested for arithmetic
from the memory is called reading. and logical operations . When the VHDL code is fully
synthesized, then the code is loaded to the Spartan FPGA
device[8].
IV. SIMULATION RESULTS OF MICROPROCESSOR
Fig. 3: reset state
This state executes according to the state machine ‘1’, the state machine is in state reset1. Moving further control
modelling as the sequential process sets signal current_state passes to state reset 2,reset3,reset 4,reset 5 and finally goes to
to state value reset1. This is the first state of the reset sequence reset 6 and, depending on the value of the ready signal from
for the CPU which starts the process of getting the CPU ready the memory, either stays in reset6 or writes the memory data
to execute instructions. the CPU ready to execute instructions value to register InstrReg and goes to state execute. At this
.If the reset signal is not ‘1’ and there is a rising edge on the point, the state machine has reset the state of the CPU to a
clock signal, then the next state signal generated by the known state and loaded the first instruction into register
combinational process is copied to signal current _state. This InstrReg. From this point forward, the state machine changes
is the method for the state machine to advance from one state state depending on the instructions encountered.
to another. After the reset signal is set to a value other than
Fig. 4: load instruction
In the above figure, the load instruction is executed. instruction .The load instruction is executed in the state
With the help of this instruction the data is loaded from the machine manner where the current state starts from load 1 and
external memory to the microprocessor. The load instruction end at load 6.
can be immediate where the data to be loaded is the part of the

ISSN No:-2456-2165
Fig. 5: Store Instruction
In the above figure ,the store instruction is executed. With the help of this instruction the data is loaded from the
microprocessor to the external memory.
Fig. 6: branch instruction
In this execution, the data is compared with the defined value and if the condition is true, the control jumps to the defined
label(address) and if the condition become false, the next instruction is executed.
Fig. 7: RTL schematic of 16 bit Microprocessor

ISSN No:-2456-2165
V. CONCLUSION
Some additional features in CPU have been added like

complex addition ,complex multiplication and other logical
operation etc. Other Modules can be added like timer , counter
,interrupt in this which can enhance the features of the
processor .Since this processor is 16 bit so it is capable of
accessing 16kb of external memory. More number of input
output devices can be accessed simultaneously.
REFERENCES
[1.] Jurado-Carmona, F.J., Tombs, J., Aguirre, M.A.,

Torralba, A., “Implementation of a fully pipelined
ARM compatible microprocessor core” XVII Design on
Circuits and Integrated Systems Conference, 2002, pp.
559-563.
[2.] Hamblen J. “Using Synthesis, Simulation, and
Hardware Emulation to Prototype a Pipelined RISC
Computer System”. Atlanta, Georgia.
[3.] Zainalabedin N.” Using VHDL for Modeling and
Design of Processing Units”. Pp.315- 326, Boston,
Massachusetts.
[4.] Manoranjan Pradhan,” Simulation and Verification of
Self Test 16-Bit Processor”, International Journal of
Computer Applications (0975 – 8887) Volume 20–
No.1, pp.42-45,April 2011.
[5.] Davidson, J. “FPGA Implementation of a
Reconfigurable Microprocessor” IEEE Custom
Integrated Circuits Conference, 1993, pp. 3.2.1- 3.2.4
[6.] Sueyoshi, T., Kuga, M., and Shibamura, H.,“KITE
Microprocessor and CAE for Computer Science”,
Systems and Computers in Japan, Vol. 33, No. 8, 2002,
pp.64-74.
[7.] Pastor, J. S., Gonzalez, I., Lopez, J., Arribas ,F.G,
Martinez, J. “A Remote Laboratory for Debugging
FPGA-Based Microprocessor Prototypes”
[8.] ,Proceedings of the IEEE International Conference on
Advanced Learning Technologies (ICALT’04),2004.
[9.] S. Kaliamurthy , R .Muralidharan , “VHDL Design of
FPGA Arithmetic Processor” International Conference
on Engineering and ICT, 2007.
[10.] Allen Dewey, “Analysis and design of digital system
with VHDL”, PWS publishing company, 1997.
[11.] Data sheet of Spartan-II 2.5 FPGA Family. 2003.
XILINX, DS001-2 (V2.2).
[12.] Weijun Z. 2001. VHDL Tutorial, Learn by Example.

16 Bit Microprocessor Architecture Analysis Using VHDL

Uploaded by

Copyright:

Available Formats

16 Bit Microprocessor Architecture Analysis Using VHDL

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

16 Bit Microprocessor Architecture Analysis Using VHDL

Uploaded by

Copyright:

Available Formats

Volume 8, Issue 1, January – 2023 International Journal of Innovative Science and Research Technology

16 Bit Microprocessor Architecture

IJISRT23JAN442 www.ijisrt.com 875

Designing 16 bit Design and Simulation of

Design and simulation of

Fig 1. Composition of paper design with aims and objectives.

A. System overview D. Hardware overview

C. Software overview CLOCK RESET

IJISRT23JAN442 www.ijisrt.com 876

Fig. 3: reset state

Fig. 4: load instruction

IJISRT23JAN442 www.ijisrt.com 877

Fig. 5: Store Instruction

Fig. 6: branch instruction

Fig. 7: RTL schematic of 16 bit Microprocessor

IJISRT23JAN442 www.ijisrt.com 878

Some additional features in CPU have been added like

[1.] Jurado-Carmona, F.J., Tombs, J., Aguirre, M.A.,

IJISRT23JAN442 www.ijisrt.com 879

You might also like