A Quasi-Resonant SPICE model eases feedback loop designs

Christophe BASSO, Joël TURCHI

ON Semiconductor
14, rue Paul Mesplé - BP1112 - 31035 TOULOUSE Cedex 1 - France
33 (0)5 34 61 11 54 e-mail: christophe.basso@onsemi.com, joel.turchi@onsemi.com

Within the wide family of Switch Mode Power Supplies (SMPS), the Flyback converters represent the
structure of choice for use in small and medium power applications. For compact designs and radio-frequency
sensitive applications, e.g. TV sets or set-top boxes, Quasi-Resonant power supplies start to take a significant
market share over the traditional fixed frequency topology. However, if the feedback loop control is well
understood with this latter, for instance via a comprehensive literature and SPICE models, the situation differs
for self-oscillating variable switching frequency structures where no model still exists. This article will show
how a simple large-signal averaged SPICE model can be derived and used to ease the design work during
stability analysis.

Quasi-resonant operation
It is difficult to carry out the analysis without having a basic idea on the operation of a converter
working in Quasi-Resonance (QR). Figure 1 depicts a typical FLYBACK converter drain-source waveform as
you probably have already observed. When the switch is closed, the drain-source voltage Vds is near zero volt
and the input voltage Vg appears across the primary inductance Lp: the current in Lp ramps up with a slope of
Vg (eq. 1). When the controller instructs the switch opening, the drain-source quickly rises and the energy
Lp
transfer between primary and secondary takes place: the secondary diode conducts and the output voltage flies
back on the primary side, over Lp. This “Flyback” plateau is equal to Vg + (V + Vf) / N, where N is the primary
to secondary turn ratio, V the output voltage and Vf the diode forward voltage drop. During this time, the

primary current decreases with a slope now imposed by the reflected voltage
(V +Vf ) (eq. 2). Figure 2 zooms
N ×Lp
on the primary current, showing how it moves over one switching cycle.
Leakage
inductance

Ipeak
Core is reset
Plateau : Soff = (V + Vf) / (Lp x N)
(Vout + Vf)/N Son = Vg / Lp

Vin

ON OFF Ip = 0, reset

ON OFF 0
Valleys

Figure 1 Figure 2
A typical FLYBACK drain-source waveform The primary current ramps up and down to zero in DCM

When the primary current reaches zero, the transformer core is fully demagnetized: we are in
Discontinuous Conduction Mode (DCM). The primary inductance Lp together with all the surrounding
capacitive elements Ctot create a LC resonator. When the secondary diode stops conducting at Ip = 0, the drain
branch is left floating since the MOSFET is already open. As a result, a natural oscillation occurs, exhibiting the

following frequency value: Fring= 1 (eq. 3). As in any sinusoidal signal, there are peaks and
2⋅π ⋅ Lp⋅Ctot
valleys. When you re-start the switch in one valley, where the voltage is minimum, the turn-on loss caused by

1
the capacitance loading the drain of the MOSFET is much reduced: this is the so-called Quasi-Resonance
operation where the switching frequency depends on the peak current, the various slopes ON and OFF and the
number of valleys you choose after the core reset. In our study, we will first concentrate on a simplified SPICE
version where the power switch is actuated right after the reset detection point (parasitic ringings are neglected)
and later on, a more sophisticated declination will incorporate parasitic delays.

Modeling the switch network

Figure 3 depicts a Flyback topology where the switching elements generating the above waveforms
have been highlighted: the power switch (usually a MOSFET transistor) and a diode, performing a rectification
job. During the converter operation, the Pulse Width Modulator controller (PWM) instructs the transistor to turn
ON, in order to store energy in the primary side. The primary current builds up until the setpoint imposed by the
feedback loop is reached. At this time, the controller toggles the transistor to the OFF state and energy transfers
to the secondary side. If the ON and OFF states can be described by a set of linear equations, there exists a
discontinuity linking these two events. Despite the presence of linear elements in the converter (capacitors,
inductors and resistors), the presence of the commuting switch clearly introduces the non-linearity that prevents
us from directly writing the small-signal equations…
When learning electronic circuits at school, there were some exercises in which we were asked to reveal
the transfer function of bipolar amplifiers. At that time, we learned to replace the transistor symbol by its
equivalent small-signal model: the schematic turned into the simple association of current and voltage sources
that greatly simplified the analysis. In the average circuit modeling technique, we also follow the same
philosophy: the exercise consists in isolating and replacing the switch network with a set of current and voltage
sources whose electrical architecture do not vary with time. Therefore, plugging the equivalent model back into
the converter of interest allows us to resolve its transfer characteristics.

IL(t) 1:N
1

Lp

I1(t) I2(t)
Vg

d a
2 3

V2(t)
V1(t)
5
s k
R
C V(t)
control

Figure 3 Figure 4
A Flyback power supply where switches have been isolated… …and individual signals separately plotted.

Deriving equations

The object of deriving a model consists in writing the equations that describe the switch network
averaged input and output quantities that a) depend from each other b) obey to the control input. Let us draw the
various waveforms before starting any line of algebra (figure 4). From this picture, we can develop equations
that will finally describe the averaged evolution of the values of interest, the input / output voltage and current of
our switch network:
Ip
<I1(t)> = ×d (eq. 4)
2
Ip
<I2(t)> = × d ' (eq. 5)
2× N

2
 V + N ×Vg
<V1(t)> = × d ' (eq. 6)
N
<V2(t)> = [V + N ×Vg ]×d (eq. 7)

where : V is the output voltage, Vg the input voltage, Ip the primary peak current, N the Ns / Np turn ratio and d the duty-cycle (d’ = 1 –d).

Please note that in this first approach, we do not consider any delay occurring at the switch opening or
induced by equation 3. These events will be considered later on, in a more complex model.

Averaging input / output voltages

From the inductor volt-second balance approximation, we know that the average voltage across an
inductor operated in a steady-state converter is zero. By looking at the V(Lp) sketch, we obtain the following
equation:

<V(Lp)> =
d '( t ) ×<V ( t ) >
d ( t )×<Vg (t ) > − = d( t)×<Vg(t) >−
(1−d(t))×<V( t) > = 0 (eq. 8)
N N
<V(t) > d(t )
=N ×
which lets us extract the classical output / input voltage ratio
<Vg(t) > (1−d(t)) (eq. 9) and as a result, the
<V(t) >
duty-cycle expression: d( t)= (eq. 10).
<V( t)>+N×<Vg(t) >

Now, by plugging equation 10 in eq. 6, we obtain the average voltage across the primary switch terminal:

<V(t) >+N×<Vg(t) > <V(t) >+N×<Vg( t)>  <V( t)>  = <Vg(t)>

<V1(t)> = ×(1−d( t) ) = ×1− 
N N  <V (t )> + N× <Vg (t) > 
(eq. 11) which agrees with the inductor volt-second balance approximation (from figure 1 since, by definition,
<V(Lp)> = 0, then Vg appears across the switch terminals).

To reveal <V2(t)>, let us plug equation 10 into 7:

<V2(t)> = [<V(t)>+N×<Vg(t)>]×d(t) = [<V(t) >+N×<Vg( t)>]×<V( t)><+VN(t×)<>Vg(t)> = <V(t)> (eq. 12)

which again could be deduced from figure 3 since the average voltage across the secondary inductance is zero…

Averaging input / output currents

The peak inductor current depends on the time during which Vg is applied over Lp. If we recall that this
time (actually ton) is d x Ts, then:
Vg
Ip = ×d ×Ts (eq. 13)
Lp
From figure 4, the average current <I1(t)> can be obtained by evaluating the triangular area (charge in
Coulomb) and dividing by the switching period. This is expressed by equation 4. Now plugging equation 13 in 4,
we obtain:

<I1(t)> = 1×<Vg(t) >×d( t)×Ts×d(t )= <Vg(t )>×d(t )²×Ts (eq. 14), however, from equation 11, we
2 Lp 2×Lp
know that <V1(t)> = <Vg(t)> thus equation 14 turns into:

<V1(t) >×d(t)²×Ts
<I1(t)> = (eq. 15)
2×Lp
Applying the same technique to the secondary current I2(t), leads to:
Ts

Ts d∫.Ts
<I2(t)> =
1 I2(t)⋅dt = 1 × Ip × d '( t ) (eq. 16), plugging equation 13 in 16 leads to:
2 N

3
 <Vg(t) >×d(t)×(1−d(t))×Ts <V1( t) >×d( t)×(1−d( t))×Ts
<I2(t)> = = (eq. 17)
2×N×Lp 2×N×Lp

A 100% efficiency power transfer…

Assuming that 100% of the primary stored energy is released to the secondary side, then we can use
equations 11 and 12 to write:

<P(t)> = <V1(t)> x <I1(t)> = <V2(t)> x <I2(t)> (eq. 18)

From equation 16, we can see that a current is generated by a voltage multiplied by a term. This term is
obviously homogenous to the inverse of an impedance. By re-arranging equation 15, we obtain:

<V1(t )> 2×Lp

Re( d) = = (eq. 19) where the input impedance depends on the duty-cycle d(t). However, in
<I 1(t) > d( t)²×Ts
quasi-resonant converters, the power transfer is adjusted by varying the peak current Ip which finally imposes
the operating frequency. Since by definition ton = d x Ts, we can re-arrange equation 9 to reveal Ts =

ton ×
(N ×Vg )+V (eq. 20). By finally plugging equation 10 and 20 into 19, we obtain a ton-dependent input
V
effective resistance definition:

2× Lp ×(V + N ×Vg )
Re(ton) = (eq. 21) that figure 5 portrays:
ton ×V

<I1(t)> <I2(t)>
<I1(t)>
<P(t)>

<V1(t)> Re(ton) <V2(t)>

<V1(t)> Re(ton)

Figure 5 Figure 6
The average input waveforms of the switch can The two -port loss-free network where all the input power
be modeled via the above equivalent network transforms into output power.

As reference [1] details, the apparent power consumed by Re, Pin, is entirely transmitted to the output
since we assume a 100% efficiency. Therefore, equation 19 can be re-written by:
<V1(t )>² (eq. 22). Our switch network can thus modeled by
<P(t)> = <V1(t)> x <I1(t)> = <V2(t)> x <I2(t)> =
Re( ton)
the so-called loss-free network where all the power developed across an input resistance transfers to the output
without any loss (figure 6) [1].

A more complex model including parasitic effects

The above simplified model assumes that there are no transient times between the conduction and
demagnetisation phases. A more precise modelling approach requires that the two following delays ?t1 and ?t2
are taken into account, as highlighted by figure 7 and 8:

4
 Core is
reset !

∆ t1
∆ t2

Figure 7
The presence of a capacitive node slows -down the Vds rising and makes the drain sinusoidally ring at the core reset…

1. At the end of the ON-time, the power switch opens but the energy transfer to the secondary side does
not start immediately. The primary inductor current (Ip) that cannot flow through the power switch,

charges the surrounding capacitive elements (Ctot) until Ctot voltage exceeds Vg+ V (eq. 23). At that
N
moment, the secondary diode starts to conduct and current feeds the output capacitor. One can assume
that the Ctot charging time (?t1) is short enough to consider that the primary inductor current stays
equal to Ip during this interval. Then, ?t1 is the time necessary to charge the capacitor Ctot with a
Vg + V
current Ip from zero to Vg+ V , i.e.: ∆t1=Ctot× N (eq. 24)
N Ip

D1
V Vg

Cout

1 8

2 7
Vg
3 6

4 5 Ctot <=>
Ctot
NCP1207

Figure 8
When the power switch turns off, the primary inductor behaves like a current source that charges the Ctot capacitor. This sequence ends
when voltage developped across Ctot exceeds [Vg+(V+Vf)/N], that is when the secondary diode D1 starts to conduct.

2. At the end of the core reset, both switches (power switch and secondary diode) are off. The primary
inductor Lp together with Ctot form a LC network. Ctot voltage (and thus the drain source voltage of
the power switch) oscillates around the input voltage Vg between a peak value (the initial level:
Vg + V ) and a valley value Vg − V , the damping effects being neglected. To benefit from the
N N
quasi-resonant mode, it is recommended to turn the power switch on in the valley, where the drain-
source voltage is minimized. This naturally reduces the dV/dt and switching losses to a minimum (in
practice, an appropriate delay inserted after the core reset detection provides an effective method to
synchronize the power switch turn on with the valley event). A simple look at figure 8 shows that the
valley occurs at half the oscillation period. Therefore, the delay ?t2 between the core reset completion
and the optimal turn on time is given by the following equation:

∆t2=π × Lp×Ctot (eq. 25)

Once these delays are defined, it is about time to revise the previous equations in order to include ?t1
and ?t2 effects. The main parameters of interest are the average input and output currents, the equivalent

5
resistance and the switching period. If we combine equations (24) and (13) that express Ip as a function of the
input voltage, the inductor value and the ON-time leads to:
Vg + V
∆t 1= Lp×Ctot× N (eq. 26)
Vg×ton
If (d’xTs) is the core reset time, the equation d' = 1 -d can be expressed with ? t1 and ? t2 as:

d '=1 − d − ∆ t 1 + ∆ t 2 (eq. 27)

Ts
The inductor volt-second balance approximation of equation (8) still holds. However, it must be revised
by replacing d’(t) by its novel value as expressed by equation (27):

<V ( Lp ) >= d ×Vg −

(
1− d − ∆ t 1+ ∆ t 2 )×V
Ts =0 (eq. 28)
N
Re-arranging equation (28), one can unveil the duty cycle expression:

(1− ∆t1+∆t2)×V)
d= Ts (eq. 29)
(N ×Vg)+V

The switching period is the sum of the on-time, the core reset time (t demag), ?t1 and ?t2:

Ts =ton +t demag + ∆ t 1+ ∆t 2 (eq. 30)

The time tdemag can easily be deducted from the figure 4. Since the core reset is the time necessary to
discharge the primary inductor from Ip to zero with a (V+Vf)/N slope, it comes:

Lp×Ip N×Vg
tdemag = =ton (eq. 31)
V /N V

Substitution of equation (31) into (eq. 30), leads to the following expression where Ts is a function of
ton:

Ts =∆t1+∆t2+
[(N×Vg)+V ]×ton (eq. 32)
V

Equation (15) that defines the average input current as a function of the input voltage, the duty cycle,
the inductor value and the switching period, still holds. Substitution of equation (29) into equation (16) leads to:
Vg×( 1− ∆t 1+∆t 2)×V ×ton
< I1(t )>= Ts
2×Lp×[ (N×Vg)+V ]
(eq. 33)

Replacing Ts by its equation (33) expression, it comes:

Vg×( 1− ∆t 1+∆t 2 )×V ×ton

∆t 1+∆t 2+
[(N ×Vg) +V ]×ton
< I1(t )>= V
2×Lp×[ (N×Vg)+V ]
(eq.34)

Re-arranging this equation, one can obtain:

6
 < I1(t )>=Vg× ton2
[(N×Vg)+V ]×ton 
(eq. 35)

2×Lp×∆t 1+∆t 2+ 
 V 

Similarly to the simplified model analysis, one can note that the average input current is proportional to
the input voltage. The effective resistance Re is thus:

Re( ton)=
2×Lp  [(N×Vg)+V ]×ton  (eq. 36)
2 ×∆t1+∆t2+
ton  V 
It is reassuring to confirm that if ?t1=?t2=0, the Re(ton) expression reduces to equation 21…
Then, the equivalent circuit depicted in figure 6 and based on the loss-free resistor Re(ton) can be
applied. To complete the model, let’s calculate <I2(t)> by combining equations (17) where d’ is taken equal to
(t demag/Ts), (13) and (31):
Vg×ton ton N×Vg
< I2(t )>= 1 × × × (eq. 37)
N 2×Lp Ts V

Substitution of equation (32) giving Ts into equation (36), leads to:

Vg×ton ton Vg
< I2(t )>= × × (eq. 38)
2×Lp ∆t 1+∆t 2+ [( N×Vg)+V ]×ton V
V
This expression can be simplified as follows:

<I 2(t) >= Vg × Vg =<I1(t )>× Vg (eq. 39)

Re( ton) V +Vf V +Vf

The model assumes a 100% efficiency power transfer. To better stick to reality, the above expression
should be multiplied by the estimated efficiency to obtain the final <I2(t)> equation:

<I 2(t)>=<I1( t)>× Vg ×eff (eq. 40)

V +Vf
where eff is the efficiency.

The following table summarizes the main equations our model is based on:

Delay between the power switch opening and the

start of the energy transfer to secondary side: Vg + V
∆t 1= Lp×Ctot× N
Vg*ton
Delay between the core reset completion and the
next turn on of the power switch (note1):
∆t 2=π × Lp×Ctot
Equivalent input resistance:
Re( ton)=
2×Lp 
×∆t1+∆t2+
[(N×Vg)+V ]×ton 

ton 
2 V 
Switching Frequency:
fsw = 1
∆t 1+∆t 2+
[( N×Vg)+V ]×ton
V
Average input current: <I 1(t) >=Vg /Re( ton)
Average output current:
<I 2(t) >= Vg ×<I 1(t) >×eff
V +Vf
Note1: even if the proposed value appears to us as the optimal one, SMPS designers might make a different choice for ?t2.
That is why, if the model proposes ∆t 2=π × Lp×Ctot as a default value, you can alter this simulation parameter to stick
to your application in case valley switching is not considered

7
Implementing the SPICE model with the Loss-Free network

As exemplified by figure 6, the model shall emulate an input resistor being ton dependent and then
transmit a power following equation 23. Different ways exist to implement this topology in Spice. INTUSOFT’s
IsSpice authorizes behavioral resistors, e.g. following any particular ohmic evolution with time, voltage, current
etc. For instance, the following code would be accepted by the simulator:

R1 1 2 R = 2.0 * v(1)^0.5 + 3.0*v(2)*time + v(2)*sqrt(temp)

Unfortunately, despite its obvious interest, this code is not very portable and would constrain the model
usage to IsSpice only. Figure 7 offers a more practical association using behavioral voltage and current sources
[2]:

i1 i2

v1 Et Gd v2

Figure 7
Implementing the DCM model via two controlled elements

The input voltage source being supposed to emulate a resistance, its expression shall be in the form of:

Et = I1 x Re where Re is simply equation 22, thus:

2×Lp×(V + N ×Vg )
Et = I1 x (eq. 24) where ton is an input port of the model, imposed by the control loop. In
ton×V
the final model, this value will be derived from Lp and the peak current given by the error voltage divided by
Rsense, where V, Vg and N are to be passed or sensed by the model

The output current source together with V2 shall deliver the output power as imposed by equation 16.
Thus, i2 generation shall follow:

Rin (eq)×i 1² 2×Lp×(V + N×Vg ) i1²

I2 = = × (eq. 25). Also, one can introduce the efficiency by simply
v2 ton×V v2
multiplying the I2 current source by {eff}, where eff is a parameter entered by the user in the model. Hence, I2
can be written as:

2×Lp×(V + N×Vg ) i 1²
I2 = × ×eff (eq. 26)
ton×V v2

8
 Operating parameter calculation

FB errint ton

R9 B8 Bton
1Meg Voltage Voltage
V(errint)*{Lp}/({Rs}*V(13))
V(FB)/3 > 1 ? 1 : V(FB)/3 < 10m
? 10m : V(FB)/3
X2
XFMR
RATIO = N
System Parameter calculation
13 13
Ip toff Fsw
Lm
{Lp}
BIp BToff Bfreq
Voltage Voltage Voltage
12
V(ton)*V(13)/{Lp} {Lp}*V(Ip)*{N}/V(3) (1/(V(ton)+V(toff)))/1k
Rs
{Rlf}

1 3
1 20 1 4
Bclamp
VI1 Current V6 3
I(VI1)>0 ?
I(VI1) : BGd
7 Current
0
BEt (((2*{Lp}*(V(3)+{N}*V(13))/(V(ton)*V(3)+1u))*I(V6)^2)/(V(3,4)+1u))*{eff}
Voltage
(2*{Lp}*(V(3)+{N}*V(13))/(V(ton)*V(3)+1u))*I(V6)
4

Gnd 4

Figure 8
The final simplified model implementation where added sources reveal
operating parameters such as Ton, Fsw and the peak current Ip

Figure 8 shows the final simplifed model subcircuit where all relevant sources appear, among them,
the switching frequency, peak current and Ton calculations. For the extended model, only BGd and BEt sources
need to be changed. As you can see, there are several denominator expressions where a variable such as Ton
appears. If during the bias point calculation SPICE Ton starts or goes close to zero, the simulator can fail to
converge (or find a wrong bias point which is worse). To avoid this potential problem, a trick consists in
inserting a fixed value, small enough like 1µ or less, to clamp the maximum value the source can take if Ton
becomes null. To the opposite, the frequency expression modeled by a voltage source can deliver kV to express
kilo Hz. The simulator dynamic being bounded, mixing values of a few mV with sources delivering kV can
introduce errors in the bias point calculation. Again, a division by 1000 will limit the range. The FB pin voltage
which undergoes a division by 3 should be clamped by a 1V limiter, a classical circuitry found in most PWM
controllers (Ip max = 1V / Rsense).
DC-bias calculation always represents a difficult task for SPICE simulators running averaged models.
In order to enhance the robustness of the extended model (the one including parasitic effects), we have
constrained the BGd source to be positive only by using a simple in-line equation that differs depending on the
simulator syntax:

BGd 4 3 I= ((2*{Lp}/V(ton)) * ( ({N}*V(13)+V(3))/(V(3)+1u) + {DEL}/V(ton) +

+({Lp}*{Ctot}/V(ton))*(1+(V(3)/{N})/V(13)) ) * I(V6)^2)/(V(3,4)+1u)*{EFF} < 10m ? 10m :
+((2*{Lp}/V(ton)) * ( ({N}*V(13)+V(3))/(V(3)+1u) + {DEL}/V(ton) +
+({Lp}*{Ctot}/V(ton))*(1+(V(3)/{N})/V(13)) ) * I(V6)^2)/(V(3,4)+1u)*{EFF} IsSpice
Gd 4 3 TABLE { ((2*{Lp}/(V(ton)+10n)) * ( ({N}*V(13)+V(3))/(V(3)+1u) + {DEL}/(V(ton)+10n) +
+({Lp}*{Ctot}/(V(ton)+10n))*(1+(V(3)/{N})/V(13)) )
+ * I(V6)^2)/(V(3,4)+1u)*{EFF} } ( (10m,10m) (1000,1000) ) PSpice
Finally, the model comes with two different names:

.SUBCKT QuasiFly 13 FB Gnd 3 Ip Ton Fsw params: Lp=3.22m Rs=0.5 N=0.06 eff=0.86
the simplified model version

QuasiFlyDel 13 FB Gnd 3 Ip Ton Fsw params: Lp=3.22m Rs=0.8 N=0.06 eff=0.86 Ctot=100p
the complete model including parasitic effects

Passed parameters are:

9
Lp, the primary inductance
Rlf, the ohmic losses of the primary winding
N, the Np : Ns ratio with Np=1
Eff, the circuit estimated efficiency

Please note that for the sake of simplicity, neither models account for the secondary rectifier forward
drop Vf, whose effect is negligible in our approach, anyway.

Putting the model to work

Different ways exist to test the validity of a model. The first one is by using SPICE only, where one can
compare the transient response of the averaged model versus that of the equivalent cycle-by-cycle. The other one
implies the comparison of the averaged model results versus a real board measurement. In this paper, we will
depict both approaches, using our simplified cycle-by-cycle transient model.
Figure 9 shows the averaged template where the sources of figure 8 have been represented by a single
graphic symbol.The symbol must be fed by Lp, Efficiency, Rsense, transformer turn ratio and the primary
inductance ohmic loss. The FB pin goes to a component arrangement particular to the NCP1207 series from ON
Semiconductor where the optocoupler collector is internally pulled-up to a reference voltage.

0.868 8.68u 80.7

ip ton fsw

Ip ton Fsw (kHz)

Vin Vout
Flyback FreeRunning L3 R6
Vout
Averaged model 2.2u 10m
IN OUT 16.8
24
16.8
16.8

120 FB GND 3

9 R8 R7
Vg
60m 150m Rload
120
16.8 16.8 8.5
AC =
17 25
FB C3 C4
1mF 220u
IC = 16 IC =

X2
QuasiFly
Lp = 1.2m
Vout
Rs = 0.5
N = 0.06
eff = 0.91
Rlf = 0.5 Fb R1
V9 R10 1k
4.8 20k FB
1.30 16.7
6 1
4.80
X1
SFH615AGR

C5 15.8
1n
2

D4
BV = 15.6

Figure 9
The averaged model template featuring DC bias points which confirms the correct bias point calculation

In figure 9, once the simulation has been done, DC points are reflected to the schematic and confirm
the validity of the original calculation. The feedback loop is made of a simple zener diode to avoid any long
feedback time constants as with a standard TL431. The cycle-by-cycle circuitry uses our simplified QR transient
model which emulates a free-running controller such as ON Semiconductor NCP1207 or NCP1205 [3] (figure
10). The output stage and feedback configuration conforms to figure 9 in order to compare similar topologies.
The first test consists in testing the input audio susceptibility by stepping the input voltage from 200V to
350VDC. Figure 11a reveals the good agreement between the averaged response and the cycle-by-cycle one.
The next test is a step load change at the converter output from light to heavy load in a few µs. Figure 11b
testifies for the right behaviour on both configuration, average or cycle-by-cycle.
On the static point of view, the following data compare numbers given by the averaged model and the
cycle-by-cycle one:

10
Ip AVG = 868mA / Ip TRAN = 858mA
Ton AVG = 8.68µs / Ton TRAN = 8.78µs
Fsw AVG = 80.7kHz / Fsw AVG = 77.8kHz
X4 Iout
XFMR-AUX
Rprim RATIO_POW = -0.06 D1 L3 R5
MBR20100CT Vout
0.5 RATIO_AUX = -0.06 2.2u 10m
9 21 13 15 Vout

12

11 Icoil Resr1 R7 7
IDiode
Lprim 60m 150m
VCoil V1

∆
1.2m 31 dem
R6 14 16
Cout1 C1
C6
5 100 1mF 220u X3
100p
IC = 16.5 IC = 16.5 PSW1

Lleak
R1 1p
V3 1k
120 dem 4 1 8 6
AC = Vout
Vdrain
fb 2 7
Id Feedback Rled
3 6
1k
24
fb
4 FreeRun 5 3
17
IReso
X1 X2
X5
FreeRunDT PSW1 Creso
SFH615AGR
toffmin = 1u 10p C5
1
1n
18
Rsense
Simplified simulation of a D4
0.5
NCP1207-based board BV = 15.6

Figure 10
This simplified transient model will help to check the averaged results

16.88 16.95
Averaged Vout

16.86 16.85
∆ = 20mV

16.84 16.75

Cycle-by-cycle Vout
16.82 16.65

Cycle-by-cycle Vout Averaged Vout

16.80 16.55

2.57m 3.11m 3.65m 4.19m 4.73m 2.48m 3.04m 3.60m 4.16m 4.72m

Figure 11a Figure 11b

Audio susceptibility with a line step (200 to 350V)…… and load step response comparison between models (50Ω to
.5Ω)
Real world confrontation

Even if the above paragraph gives us the assumption that our model sticks to reality quite well, nothing
replaces a real board measurement with a network analyser. However, on the NCP1207, the collector of the
optocoupler is directly internally pulled-up to a reference via a resistor, it thus becomes difficult to open the loop
via the series transformer method. We thus went back to a simple open-loop configuration where a DC source
fixes the expected operating point. It does not cause any problem in our case since the overall gain Vcontrol to
Vout is low. The AC injection is then made via a 1000µF capacitor. Figure 12 depicts the adopted configuration
on the bench, but also replicated on the averaged model.

11
 1 8

2 7

4 3 6

4 5 5

NCP1207
R3
C1
1k
1000u

3 1
Vstim Rsense
Vbias
AC = 1 1.57

Figure 12
The AC measurement is obtained once the proper operating point is reached by adjusting
Vbias. The gain being low, there is no problem of output runaway as long as Vbias is slowly increased.

The bandwidth measurement has been carried on a board further to a 15mn warm-up. This board does
not use any clamping network but a 800V MOSFET instead and a large capacitor connected between drain and
ground Figure 12a and 12b compare the obtained results with the averaged model including valley and turn-off
delays:

High line
Low line
F0dB = 49Hz

High line
Low line

Figure 12a – Bode plot captured with a network analyzer

20.0 180
Open-loop gain :
High line
Low line
0 90.0

F0dB = 46Hz

-20.0 0

-40.0 -90.0

Open-loop phase :
High line
Low line
-60.0 -180

1 10 100 1k 10k 100k

Figure 12b – Bode plot obtained with the averaged model

12
 One can detect a slight gain difference (around 3.5dB) in DC but the overall simulated shape stays in
good agreement with the real measurement. The phase dips are imputed to the presence of the LC network
whose cut-off frequency obviously affects the results. The small-signal analysis details are available in [4].
Finally, a step-load response was performed on a real board fed back by a TL-431 network and
compared to our SPICE model, also implementing the same control loop structure. Results prove that the
proposed model accuracy is acceptable to predict board stability and final transient response:

16.93

16.87
30mV/div

16.81

16.75

2ms/div
16.69

4.50m 8.50m 12.5m 16.5m 20.5m

Figure 13a Figure 13b

The simulated step-load response on a TL431-based feedback loop… …versus real board oscilloscope shot

Conclusion

Until now a SPICE model dedicated to the AC analysis of free-running topologies was missing. The
simple model presented in this article shows that loop stabilization of QR converters becomes easy thanks to the
simulation. Furthermore, the good agreement between simulated results and hardware measurements will surely
diminish the prototype development time. As usual, the application templates of the paper examples are available
to download from the author’s website [5] in both Intusoft’s IsSpice and OrCAD’s PSpice.

References:

[1] B. Erickson, D. Maksimovic, “Fundamentals of Power Electronics”, Kluwers Academic Publishers, ISBN 0-7923-7270-0
[2] B. Erickson, D. Maksimovic, Advances in Averaged Switch Modeling and Simulation”, CoPEC.
http://schof.Colorado.EDU/~pwrelect/publications.html
[3] C. Basso, “Implementing the SOFA in AC/DC Power Supplies”, ON Semiconductor, AND8043 – www.onsemi.com -
[4] J. Chen, B. Erickson, D. Maksimovic, “Averaged Switch Modeling of Boundary Conduction Mode Dc-to-Dc converters”, the 27th Annual
Conference of the IEEE Industrial Electronics Society.
[5] http://perso.wanadoo.fr/cbasso/Spice.htm

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