Comparator Design and Analysis For Comparator-Based Switched-Capacitor Circuits

Comparator Design and Analysis for
Comparator-Based Switched-Capacitor Circuits

by
Todd C. Sepke
B.S., Michigan State University (1997)
S.M., Massachusetts Institute of Technology (2002)
Submitted to the Department of Electrical Engineering and Computer
Science in partial fulfillment of the requirements for the degree of
Doctor of Philosophy in Electrical Engineering and Computer Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
September 2006
@ Massachusetts Institute of Technology 2006. All rights reserved.
Signature of A uthor ................ .... ...........................

Department of Electrical Engineering and Computer Science
September 29, 2006
Certified by......... . . . . . . . . ... . . . . . . . . . . . . .. .. . . . . . . . . . .
Hae-Seung Lee
Professor of Electrical Engineering
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Thesis Supervisor
C ertified by . .... . ................................
Charles G. Sodini
) rofesso~e of Electrical Engineering
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Accepted by
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Arthur C. Smith
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MASSACHUSETTS INSTIUTE
OF TECHNOLOGY Chairman, Department Committee on Graduate Students
Department of Electrical Engineering and Computer Science
APR 3 0 2007
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Comparator Design and Analysis for Comparator-Based
Switched-Capacitor Circuits
by
Todd C. Sepke
Submitted to the Department of Electrical Engineering and Computer Science

on September 29, 2006, in partial fulfillment of the
requirements for the degree of
Doctor of Philosophy in Electrical Engineering and Computer Science
Abstract
The design of high gain, wide dynamic range op-amps for switched-capacitor circuits
has become increasingly challenging with the migration of designs to scaled CMOS
technologies. The reduced power supply voltages and the low intrinsic device gain
in scaled technologies offset some of the benefits of the reduced device parasitics.
An alternative comparator-based switched-capacitor circuit (CBSC) technique that
eliminates the need for high gain op-amps in the signal path is proposed. The CBSC
technique applies to switched-capacitor circuits in general and is compatible with
most known architectures. A prototype 1.5 b/stage pipeline ADC implemented in a
0.18 Fým CMOS process is presented that operates at 7.9 MHz, achieves 8.6 effective
bits of accuracy, and consumes 2.5 mW of power.
Techniques for the noise analysis of comparator-based systems are presented. Non-
stationary noise analysis techniques are applied to circuit analysis problems for white
noise sources in a framework consistent with the more familiar wide-sense-stationary
techniques. The design of a low-noise threshold detection comparator using a pream-
plifier is discussed. Assuming the preamplifier output is reset between decisions, it is
shown that. for a given noise and speed requirement, a band-limiting preamplifier is
the lowest power implementation. Noise analysis techniques are applied to the pro-
totype CBSC gain stage to arrive at, a theoretical noise power spectral density (PSD)
estimate for the prototype pipeline ADC. Theoretical predictions and measured re-
sults of the input referred noise PSD for the prototype are compared showing that
the noise contribution of the preamplifier dominates the overall noise performance.
Thesis Supervisor: Hae-Seung Lee

Title: Professor of Electrical Engineering
Thesis Supervisor: Charles G. Sodini

Title: Professor of Electrical Engineering
Acknowledgments
First, I would like to thank my wife Carrie for her patience and understanding.
Without her support, I would not have made it. I realize it was not easy having a
graduate student for a husband for 6 years. I look forward to our life after graduation.
I would, like to thank my research advisors and mentors Prof. Harry Lee and Prof.
Charlie Sodini. Their guidance and instruction during my years at MIT made my
graduate career challenging, exciting and rewarding. I am indebted to them for their
time, patience, and support.
I would also like to thank John Fiorenza for listening to me talk about noise for
the last 6 years. It has been nice to have at least one person in the office who had
some idea of what I was talking about and that I could bounce ideas off of. And in
our spare time, I think we may have actually solved some of the worlds problems over
coffee...
I would like to thank Peter Holloway for his assistance, guidance and many stim-
ulating discussions over the last couple of years of my Ph.D, and Prof. Jim Roberge
for taking the time to read my thesis and be on my committee.
I would. like to acknowledge the many members of the Sodini group during my
tenure at MIT. The group who endured the Ph.D. program with me: Anh Pham,
Andy Wang, Lunal Khuon, and Albert Jerng. The many good technical discussions,
the dinners out, the homework, the tapeouts, and finally graduation. To the many
junior members of the group, some who have come and gone and others who must still
carry on: Kevin Ryu, Farinaz Edalat, Nir Matalon, Kartik Lamba, Khoa Nguyen,
Ivan Nausieda, Albert Lin, Jit Ken Tan, Matt Powell and Johnna Powell: it has
been a pleasure to work with all of you. I also cannot forget to mention those who
were senior members when I arrived: Don Hitko, Dan McMahill, Ginger Wang, Iliana
Fujimori Chen, and Pablo Acosta Serafini for helping me when I was new.
Similarly, I would like to acknowledge the members of the H. S. Lee group: former
cube-mate Mark Peng, contemporaries Andrew Chen, Matt Guyton, Albert Chow,
fellow Big Ten alum Mark Spaeth for many great technical and non-technical con-
versations, Lane Brooks for many helpful discussions about CBSC, and the senior
members who welcomed me to the group on their way out: Kush Gulati, Ayman
Shabra, and Susan Luschas.
I have also had the pleasure of meeting many other outstanding individuals during
my time at MIT who are to numerous to name, including my colleagues in the MTL
community and the students on the second floor of Bldg 38.
I would like to acknowledge the MTL Mallards Hockey Team and especially Andy
Fan for his efforts to keep the team going and his inspirational pregame emails.
Hockey with the Mallards was an important part of my MIT education.
I would like thank the administrative assistants Kathy Patenaude, Rhonda May-
nard, and Carolyn Collins who always helped to part the MIT red tape. Marilyn
Pierce, who has been of great assistance in all departmental and institute matters.
She is always looking out for the graduate students. Debb Hodges-Pabon, her enthu-
siasm is contagious; she has made the MTL a great place to work.
I would like to thank the MTL computer and CAD support staff: Mike Hobbs,
Bill Maloney, and Mike McIlrath for keeping the computing and CAD infrastructure
functioning.
I would like to thank my parents for their continued support and encouragement.
I would like to thank my brother Scott for letting me vent my frustrations when
necessary; it is great to have someone else in the family who really understands the
life of a doctoral candidate.
The author was funded by the MARCO Focus Center for Circuits and System
Solutions (C2S2, www.c2s2.org) contract 2003-CT-888x and the MIT Center for
Integrated Circuits and Systems (CICS). The chip fabrication and packing for the
prototype in this thesis were donated by National Semiconductor.
Dedication
I dedicate this thesis to my Grandmother Beulah T. Fleming (January 6, 1912-
August 11. 2006) who passed away during my final days at MIT. Her letters and
phone calls were always a welcome respite from life as a graduate student. I could
always count on her being awake at all hours of the night, eager to hear about recent
events in my life, and willing to share her thoughts on current events or memories of
days gone by.
Contents
1 Introduction 23
1.1 Motivation ................. ............... 23
1.2 Thesis Organization. ................... ........ 25
2 Comparator-Based Switched-Capacitor Circuits 27

2.1 Overview ................... .............. 27
2.2 CBSC Basic Principle of Operation . .................. 27

2.2.1 Sampling Circuit ................... ...... 28
2.2.2 Op-amp Based Charge Transfer Phase . ............ 28
2.2.3 Comparator-Based Charge Transfer Phase . .......... 30
2.3 Practical CBSC Gain Stage Charge Transfer . ............. 31
2.3.1 Preset Phase ................... ........ 32
2.3.2 Coarse Charge Transfer Phase .......... ........ 33
2.3.3 Fine Charge Transfer Phase . .................. 35
2.3.4 Overshoot Correction ................... .... 36
2.4 Noise Analysis ................... .......... .. 38
2.5 Ramp Linearity ............ .................. 38
2.6 Summary ............... ................. 40
2.6.1 Limitations ................... ......... 40
2.6.2 Advantages ................... ......... 41
3 Noise Analysis 43
3.1 Noise Analysis Overview .........
3.2 Wide-Sense-Stationary Noise Analysis . .............. . . 45
3.2.1 WSS Frequency-domain Analysis . ............... 46
3.2.2 WSS Time-domain Analysis . ............... . . 49
3.3 Non-stationary Noise Analysis ........... ..... . ... 51
3.3.1 Non-stationary Time-domain Analysis . ............ 52
3.3.2 Noise Initial Conditions ................... .. 56
3.3.3 Non-stationary Noise Interpretation . .............. 57
3.3.4 Non-stationary Frequency-domain Analysis . .......... 58
3.4 Input Referred Noise ................... ........ 62
3.4.1 Noise Gain ................. .......... 63
3.5 Periodic Filtering Frequency Domain Model . ............. 71
3.6 Noise Aliasing ................... .......... .. 76
3.6.1 White Noise Aliasing ................... .. . 76
3.6.2 Flicker Noise Aliasing ................... .. . 78
3.6.3 Finite Summation Approximation of Aliased Noise ...... 84
3.7 Summary ................... ........... .. 85
4 Threshold Detection Comparator Design 89

4.1 Overview ......... ......... ........ ...... 89
4.2 Threshold Detection Comparators ....... ............. 91
4.2.1 Specifications . .. ... .................... 91
4.2.2 Low Noise Comparator Design .... ... ......... . 92
4.2.3 Preamplifier Design ................... ..... 98
4.2.4 Threshold Detection ................... ... 105
4.3 Summary ........... ................... ... 115
5 CBSC Prototype Pipeline ADC 117

5.1 Overview .................. .............. 117
5.2 1.5-bit/stage CBSC Pipelined ADC . .................. 117
10
5.2.1 Charging Current Sources ................... . 119
5.2.2 Bit Decision Comparators ................... . 120
5.2.3 Virtual Ground Threshold Detection Comparator ...... . 123
5.2.4 CBSC State Machine ................... .... 125
5.2.5 Prototype Test Chip ................... .... 126
5.3 Experimental Results ................ ........ 127
5.4 Summary ....... .......... ............ .. 132
6 CBSC Noise Analysis 133
6.1 Overview ....... ............ .............. 133
6.2 Total Input Referred Noise of Pipeline ADC . ............. 133

6.3 Single Pipeline Stage Input Referred Noise . .............. 135
6.3.1 Periodic Filtering Model ................... .. . . 136
6.3.2 Threshold Detection Comparator Noise . ............ 136
6.3.3 Charging Current Noise ................... .. 142
6.3.4 Switch Noise ................... ........ 149
6.4 Putting It All Together ................... ....... 152
6.4.1 Complete Noise PSD Estimate . ................. 154
6.4.2 Comparison of White Noise Voltage Contributions ....... 154
6.5 Summary ................... ............ .. 158
7 Measured Results of Noise in CBSC 159
7.1 Overview. ................... .. 159

7.2 Measurement Method ............... 159
7.3 Results ...... ............... . 161
7.3.1 ADC Input Referred Noise PSD . . . 162
7.3.2 Sensitivity of Theoretical Prediction . .. 164
7.4 Discussion ................... .. 170
7.5 Summary . .................. 172
8 Conclusion 173
8.1 Thesis Contributions . . ... . ........ ............ .. 173
8.2 Future Work ... ... . . .... ... .... .......... ... . 174
References 177
List of Figures
2-1 Bottom plate open-loop sampling (a) Sampling circuit. (b) Sampling
clocks. O1A defines sampling instant to minimize input dependent
charge injection. ................... .......... .. 28
2-2 Op-amp based switched-capacitor gain stage charge transfer phase.
(a.) Switched-capacitor circuit (b) The output voltage exponentially

settles to the final value. (c) The summing node voltage exponentially
settles to the virtual ground condition. . ................. 29
2-3 Comparator-based switched-capacitor gain stage charge transfer phase.

(a) Switched-capacitor circuit with an idealized zero delay comparator.
(b) The output voltage ramps to the final value. (c) The summing node
voltage ramps to the virtual ground condition. . ........... . 30
2-4 CBSC charge transfer phase timing ............ ....... 31
2-5 Preset phase (P). (a) Switch P closes. (b) vo grounded and vx set
below VCM .......... .... ............................... 32
2-6 Coarse charge transfer phase (E). (a) Current source I, charges out-
put. (b) vo and vx ramp and overshoot their ideal values. ...... . 34
2-7 Fine charge transfer phase (E 2 ). (a) Current source 12 discharges out-
put. (b) vo and vx ramp to their final values. . ........... . 35
2-8 Overshoot cancellation. (a) CBSC stage with overshoot cancellation.
(b) vx node voltage during the charge transfer phase without overshoot
correction. The large overshoot during the coarse phase prevents the
charge transfer operation from finishing in allowed time. (c) CBSC
stage with overshoot cancellation. ................... . 37
3-1 Overview of time-domain and frequency-domain analysis. ....... . 45
3-2 Transconductance Amplifier. ................... .... 47

3-3 Noise Bandwidth (NBW) for a one-pole system. . ............ 48
3-4 Transconductance amplifier operating as an integrator (VH > VT). . . 51
3-5 Large signal response of transconductance device with noise. ...... 51
3-6 Step noise signal x(t). Underlying WSS noise process v(t) applied at
t = 0. For tl or t 2 less than zero, the autocorrelation for x(t) is zero,
and for tl and t 2 greater than zero, the underlying WSS autocorrelation
R,,(tl, t 2 ) defines the autocorrelation of x(t). . .............. 52
3-7 Noise initial condition example: capacitor reset noise. (a) RC circuit
with capacitor reset noise (R > Rswitch). (b) Capacitor RMS noise
voltage from initial condition for t > 0. . ................. 56
3-8 In transient noise analysis, it is ensemble averages and not time av-
erages that are most important. (a) Ramp voltage plus random walk
noise. (b) Average ramp voltage. (c) Random walk noise voltage show-
ing 3o bounds. ... ....... ............... .... . 59
3-9 Windowed impulse response.... ................... . 60
3-10 Frequency Domain: Transfer function for different window widths (ti) 61
3-11 Input referred noise comparator model (a) Noisy comparator results in
timing jitter at. (b) Noiseless comparator with input referred noise v n
resulting in the same timing jitter. ................ ... 63
3-12 Transformation of voltage noise to timing jitter in the comparator de-

cision. ..... .............................. . 65
3-13 Step ramp input and corresponding step noise input. . ......... 67
3-14 Response time tj for amplifier to reach output threshold VAMo . . . . .. 68
3-15 Noise Bandwidth versus response time ti. To = 250 ps ......... 69
3-16 Periodic filtering sampler model: the output samples can be modeled
as the impulse train sampling of the input filtered by Fourier transform
of the windowed impulse response. . ................... 72
3-17 Periodic integration filter H,(f). DC gain IH,(0)I = ti/Cs and one-
sided noise bandwidth NBW = 1/(2ti). . .............. . . 75
3-18 White noise aliasing NBW = 3f, . . . . . . . . . . . . . . . . . . . . 77
3-19 Flicker noise aliasing (a) Original pre-sampled PSD with flicker and
thermal noise. (b) Folded flicker noise. . ................. 79
3-20 Total sampled flicker noise PSD showing direct feed-through contribu-
tion and apparent white folded flicker noise. . .............. 80
3-21 Maximum to minimum PSD ratio for folded flicker noise. ........ 83
3-22 Cumulative aliasing function (CAF): fraction of total noise power as a
function of the number k of normalized noise bandwidths r. ...... 86
4-1 General definition of threshold detection comparator performance. .. 90

4-2 Ideal threshold detection comparator with band-limiting preamplifier. 92
4-3 Ideal timing for comparator with preamplifier. The preamplifier output
voltage is clamped at ±VD. (a) Preamplifier input voltage where the
summing node voltage vx has crossed the virtual ground condition at
time zero. (b) Preamplifier output voltage showing the response time ti
it takes for the preamplifier output to reach the comparator threshold.
(c) Output logic signal changes stage after total comparator delay td. 93
4-4 Holding Gm and CL constant, Ro is swept, the ramp response to a given
threshold VM is faster for high Ro and the total mean-square noise is
lower for high Ro (a) Ramp response. (b) Noise bandwidth....... . 96
4-5 Holding Gm and Ci constant, Ro is swept. (a) Ramp response: time
to a given threshold VM is faster for larger Ro. (b) Noise bandwidth:
reduces for larger Ro . . . . . . . . . . . ... . . . . . . . .. . 97
4-6 Relative preamplifier band-limiting capacitance C, versus response time
relative to preamplifier time constant x = ti/To for a given noise and
speed requirement. Because Ci is relatively constant, the relative
amount of response time is approximately only a function of output
resistance Ro (x - 1/Ro). . ....................... .....
. 101
4-7 Relative preamplifier speed Gm/Ci and transconductance Gm versus

output resistance Ro. Transconductance approaches the ideal integra-
tor result versus Ro more quickly than speed. . ............. 102
4-8 Required preamplifier transconductance versus output resistance for

constant noise, speed and linearity requirements. Minimum transcon-
ductance (Gm,int) design is an ideal integrator (Ro > Ro,dim). . . . . . 103
4-9 Cascade of three amplifier stages. ................... . 106
4-10 Optimum cascade of amplifiers. (a) Optimum number of stages Nop

versus the required gain A for minimum response time ti. Approxi-
mation that the gain is a linear function of the natural logarithm of
the required gain. (b) Relative delay (ti/lI) versus required gain A
assuming the optimum number of stages Nop is used. . ......... 107
4-11 Relative delay versus number of stages for a given gain requirement A. 108
4-12 Current mirror op-amp as a comparator. . ................ 109
4-13 Bazes comparator based on a self-biased differential amplifier. ..... 110
4-14 Inverter with split NMOS and PMOS drive. A source follower is used
as a DC level shifter to drive the NMOS device. . ............ 111
4-15 Adaptively biased differential amplifier. (a) Simplified schematic. (b) Re-
quired bias current variation. When VID = 0, II = I2.......... 113
5-1 First two stages of Pipeline ADC. Note that the first stage sampling
and bit-decision clocking are controlled by the system clock, but for the
second and subsequent stages, the sampling and bit-decision clocking
are controlled by the comparator of the previous stage. . ........ 118
5-2 Coarse and fine phase current sources. Bias voltage generation not
shown. (a) Coarse phase current source II = 70 kA. (b) Fine phase
current source 12 = 3 ýA. ................... ...... 119
5-3 Bit decision comparators. (a) Typical cross-coupled inverter based
clocked latch. (b) Cross-coupled inverter based clock latch used in
prototype. Addresses the problem of having to charge node X at the
drain of Mr. (c) Latch timing diagram. . ................. 121
5-4 Bit decision comparator data valid and storage registers. ....... . 122
5-5 Schematic of prototype threshold-detection comparator with band-
limiting preamplifier. The total parasitic capacitance at the output of
the band-limiting amplifier determines the bandwidth. Resistors shown
in the schematic are implemented as PMOS devices with grounded
gates operating in the triode region. Each comparator has a power
consumption of roughly 200 kW. ................... .. 124
5-6 More detailed schematic of comparator preamplifier for prototype show-
ing the common-mode feedback circuit. . ................. 124
5-7 Current source and sampling logic and CBSC state machine. ..... 125
5-8 Die photograph. 0.18 pm CMOS process. Pipeline Area: 1.2 mm 2 . . . 126
5-9 Simplified diagram of the prototype test setup ........ . . . .. 127
5-10 ADC 10b INL and DNL for a 7.9 MHz sampling frequency. (a) DNL.
(b) INL. ............... ......... ...... 129
5-11 Output FFT for f, = 7.9 MHz sampling rate and a -1 dBFS input at
fi. = 3.8MHz .................. ....... ..... 130
5-12 SNDR and SFDR versus input frequency. . ................ 131
6-1 Single 1.5b/stage model for noise analysis. ....... ........ 134
6-2 Pipeline ADC model noise model. . ........... ........ 134
6-3 Ideal threshold detection comparator with band-limiting preamplifier. 137
6-4 Half-circuit model for band-limiting preamplifier. (a) Linear half-circuit
model. (b) Waveforms for linear half-circuit model. . .......... 138
6-5 Comparator preamplifier for prototype. . ................. 138
6-6 Preamplifier response time filter Hw,resp (f)2 for different output re-
sistances causing variation in ti relative to To. . . . . . . . . . . .. . . 141
6-7 Noise contribution from fine phase charging current 12. . ........ 143
6-8 Charging current transfer function during preamplifier response time.

Preamplifier output swept for a constant Gm and Ci. A broad-band
preamplifier, lower output resistance, results in more noise cancellation
and therefore, lower transfer function gain. . ............... 146
6-9 Noise contribution from sampling and configuration switches. ...... 149
6-10 Op-amp based charge transfer switch noise contribution for a gain of
two stage. Op-amp noise bandwidth is 1/(47,) = 2f3dB, C 1 = C2 = Cs,
and the load capacitance has been scaled by a factor of two CL = Cs/2.
(a) Schematic of op-amp based gain of two stage with switch resistances
shown. (b) Input referred noise PSD highlighting feedback v 2 , and
feed-forward v 2 FF noise paths. ................... .. 153
6-11 CBSC versus op-amp based charge transfer timing. Because ti can
potentially be made a larger fraction of Ts/2 than the op-amp closed-
loop time constant Top can be, for the same power consumption and
speed, the comparator-based design has lower noise bandwidth. . . 155
7-1 Theoretical and measured noise PSD fs = 2.4576 MHz, K = 30 . ... 162
7-2 Theoretical breakdown of PSD noise for f, = 2.4576 MHz (a) Theoret-
ical breakdown of aliased components. (b) Theoretical breakdown of
apparent white noise sources. ......... ............. 163
7-3 Theoretical and measured noise PSD f, = 983.04 kHz, K = 30..... . 165
7-4 Theoretical and measured noise PSD fs = 327.68 kHz, K = 30. ..... 165
7-5 Fit of ADC input referred noise PSD to determine preamplifier flicker
noise parameters. The flicker noise exponent a = 0.86 and the flicker
noise PSD for a single preamplifier at 1 Hz Si, (1) = 1.3 x 10-17 A 2 . . 166
7-6 ADC input referred noise PSD at f = fs/2 and f = df versus flicker
noise of preamplifier at 1 Hz Si, (1) ........ ..... ... . .. . 167
7-7 ADC input referred noise PSD at f = fs/2 and f = df versus flicker
noise exponent a. . ................. ........ . . 168
7-8 ADC input referred noise PSD at f = f,/2 and f = df versus output
resistance Ro of preamplifier. . .. .... ... ...... . . ... . 169
List of Tables
3.1 Fraction of total noise power as a function of the number k of the

normalized noise bandwidths 77 = [NBW/(f,/2)1 ............ 86
5.1 Threshold-detection comparator static bias currents. ........... 125

5.2 ADC Performance Summary ................... .... 132
7.1 Ranking of apparent white noise sources in ADC PSD estimate for
sampling frequency f, = 2.4576 MHz. . .................. 164
7.2 SNR and ENOB for prototype converter for different combinations of
noise sources and harmonic distortion. . ................. 171
Chapter 1
Introduction
1.1 Motivation
The design of switched-capacitor circuits in scaled CMOS technologies is becoming

increasingly difficult. Although parasitic capacitances are reduced at each successive
technology node allowing for faster or lower power operation of analog circuits, other
factors such as reduced power supply voltages, lower device output resistance, in-
creased flicker noise, and charge leakage paths present challenges to switched-capacitor
circuit designers.
Charge storage in scaled CMOS technologies is a looming problem. In the past,

only reverse biased diode leakage at the source and drain junction were of concern,
but sub-threshold drain current leakage and gate current leakage are becoming sig-
nificant'. Existing solutions to this problem involve controlling the bias voltages on
devices in their off state to minimize the leakage current [3] [4] [5]. Another alter-
native is to operate the circuits faster than otherwise necessary to minimize leakage
charge error (AQ Oc Iheak/fs)-
Unfortunately, the pocket (halo) implant [6] routinely used in scaled technologies
to prevent punch-through and control short channel threshold voltage effects has
1
For a good overview of leakage sources in scaled technologies see [1] [2].
the unintended side effect of increasing the flicker noise in scaled technologies [7].
Using devices with a larger gate area WL does reduce the input referred flicker noise
PSD, but it requires an increase in power consumption to maintain the same speed
of operation. Traditional techniques such as correlated double sampling or chopper
stabilization can be used to eliminate flicker noise [8], but larger amounts of flicker
noise may require performing these functions at frequencies higher than the required
Nyquist sampling rate for the input signal bandwidth.
Lower supply voltages reduce the amount of voltage headroom available for the
output voltage swing of op-amps. To maintain the same dynamic range, the input
referred noise of the op-amp must be reduced. Reducing the op-amp noise requires
an increase in the compensation capacitor Cc, but the power consumption must also
be increased to maintain the same speed of operation GI/C,.
Another major difficulty in op-amp design for scaled CMOS technologies is the
ability to obtain the required DC gain. Devices with shorter channel lengths are
expected to have lower output resistance (ro) and intrinsic device gain (gmro), but the
pocket (halo) implant [6] also causes a drain-induced threshold shift (DITS) that does
not disappear at longer channel lengths [9] [10]. The result is a lower than expected
device output resistance even at longer device lengths where DIBL effects are expected
to be negligible. Traditionally, the method of obtaining large DC gains with devices
that have low output resistance has been to cascode the transistors connected to high
impedance nodes in the op-amp. However, cascoding exacerbates the reduced supply
voltage problem. The alternative to cascoding is to cascade multiple gain stages, but
stabilizing a cascade of amplifiers in feedback is difficult. Techniques such as nested
Miller compensation [11] can be used to stabilize the op-amp in feedback, but an
increase in power consumption is required to maintain the same speed of operation2 .
To address the issues of low intrinsic device gain and lower supply voltages, a
new comparator-based switched-capacitor circuit (CBSC) technique is proposed that
eliminates the need for high gain op-amps in the signal path. The proposed tech-
2
For a good overview on sophisticated op-amp compensation techniques see [12].
nique is compatible with most known switched-capacitor architectures, but it is more
amenable to design in scaled technologies.
1.2 Thesis Organization

Chapter 2 provides an introduction to the comparator-based switched-capacitor tech-
nique. This chapter covers the basic principle of operation and a brief discussion of
accuracy limitations.
Chapter 3 covers the noise analysis techniques for comparator-based circuits that
are use throughout the thesis. The different noise analysis techniques are demon-
strated with a series of examples.
Chapter 4 discusses the design of efficient low-noise threshold detection compara-
tors. Design equations are presented for a low noise preamplifier for threshold de-
tection comparators. Basic threshold comparator design is reviewed, and the unique
requirements for threshold comparators in CBSC systems are discussed.
Chapter 5 presents the details and results of the CBSC prototype 1.5b/stage
pipeline ADC.
Chapter 6 covers the detailed noise analysis of the CBSC pipeline ADC. The
general noise power spectral density (PSD) results for both thermal and flicker noise
sources are derived, and the mean-squared noise results for thermal noise sources are
also presented.
Chapter 7 presents a comparison between the theoretical noise PSD derived in
Chapter 6 and measured results from the prototype.
Finally, Chapter 8 summarizes the contributions of this thesis and suggests areas
for future work.
Chapter 2
Comparator-Based
Switched-Capacitor Circuits
2.1 Overview
The basic operation of comparator-based switched-capacitor circuits (CBSC) is in-

troduced. After establishing the basics, a more practical comparator-based charge
transfer phase is described. Accuracy limitations are introduced, where a further
discussion of noise is deferred to later chapters. Finally, a summary of the known
limitations and potential advantages of the CBSC technique is given.
2.2 CBSC Basic Principle of Operation
Although the CBSC technique is applicable to a wide range of switched-capacitor

circuits, a simple switched-capacitor gain stage is used to illustrate the basic principle
of operation. A traditional op-amp based switched-capacitor gain stage is compared
to the proposed comparator-based implementation. Both circuits use the same input
sampling circuit. The difference is in the method of achieving the virtual ground
condition during the charge transfer or amplification phase.
VIN
II EU E u
0-2l
1A 9 A 4
VCM
(a) (b)
Figure 2-1: Bottom plate open-loop sampling (a) Sampling circuit. (b) Sampling
clocks. q1A defines sampling instant to minimize input dependent charge injection.
2.2.1 Sampling Circuit
Assume that both circuits use the same open-loop input sampling circuit shown in
Figure 2-1. During the sampling phase 01, the input voltage is sampled onto both
C1 and C2 . The opening the bottom plate switch to VCM at the falling edge of q1A
defines the sampling instant. The clock &1A is an advanced version of the sampling
phase clock 01. This sampling method minimizes signal dependent charge injection
from the sampling switch [13] [14].
2.2.2 Op-amp Based Charge Transfer Phase
In the traditional op-amp based charge transfer phase, the capacitors C 1 and C2
are reconfigured as shown in Figure 2-2. The op-amp then forces a virtual ground
condition at node vx. This forces all the charge sampled onto C2 to transfer to C1.
During the charge transfer, both the output voltage vo and the virtual ground node
vx exponentially settle to their steady-state values. In Figure 2-2, the exponential
settling neglects slew rate limitations and the effects of higher order poles in the op-
amp that would increase the required settling time. After a number of time-constants
%I
VO
- --------
vo[n] -
// ý am-m(m....
/0-
VCM
VU;M X
VCM VCM - --.-----
(a) - .11. . . .
VXo -
(c)
Figure 2-2: Op-amp based switched-capacitor gain stage charge transfer phase.
(a) Switched-capacitor circuit (b) The output voltage exponentially settles to the
final value. (c) The summing node voltage exponentially settles to the virtual ground
condition.
have passed to achieve the desired output voltage accuracy, the output of the stage
can be sampled. The relationship between the input and output samples is
vo [n] =( +C2) V[n - 1] (2.1)
and the capacitor ratio (C 2/C1 ) determines the gain of the amplifier.
Note that during the charge transfer phase, the accuracy of the output voltage
directly depends on the accuracy of the virtual ground condition. In conventional
designs, the op-amp forces the virtual ground in a continuous-time manner, but in
switched-capacitor circuits, an accurate virtual ground condition is only required at
the sampling instant. Therefore, it should be possible to detect the virtual ground
condition at a single time point using a threshold-detection comparator rather than
force it with an op-amp. Also, detecting the virtual ground condition should be more
'I
n
V0
VO[n]
L
0I.
/o- (b)
VCM 1I,VCM ,
VX,
VCM VCM -
(a)
vXo -
4.
(c)
Figure 2-3: Comparator-based switched-capacitor gain stage charge transfer phase.

(a) Switched-capacitor circuit with an idealized zero delay comparator. (b) The
output voltage ramps to the final value. (c) The summing node voltage ramps to the
virtual ground condition.
energy efficient than forcing it.
2.2.3 Comparator-Based Charge Transfer Phase
Detecting the virtual ground condition is the approach taken in the comparator-based
charge transfer phase. The procedure for implementing a comparator based charge
transfer phase is now presented.
Again, assuming the input was sampled just like in the op-amp case, and the
capacitors C1 and C 2 are reconfigured in a similar manner; the result is the circuit in
Figure 2-3. The op-amp has been replaced with a virtual-ground threshold-detection
comparator and a current source I.. Assuming for the moment that something
has been done to ensure that vx always starts below the virtual ground condition
(Vxo < VCM), the current source Ix turns on at the beginning of the charge transfer
S: Sample : Charge Transfer
•2
P El E2
Figure 2-4: CBSC charge transfer phase timing.
phase and charges up the capacitor network consisting of C 1 , C2 and CL. The ramp
voltage waveforms shown in Figure 2-3 result. The voltage vx continues to increase
until it equals VCM. At this point, the comparator detects the virtual ground con-
dition and turns off the current source I,. Therefore, the comparator defines the
sampling instant. The state of the circuit is identical to that of the op-amp based im-
plementation, and the relationship between the input and output samples is identical
to (2.1).
2.3 Practical CBSC Gain Stage Charge Transfer
Now that the basic principle of operation has been established, a more practical
version like that used in the prototype system is described. The first issue that must
be addressed is to ensure the initial condition in the charge transfer phase. The
second issue is maximizing the accuracy of the charge transfer phase. To minimize
the noise in the comparator decision, it is desirable to maximize the time available to
the comparator to do noise averaging when making its decision. The noise averaging
property of the comparator is discussed in detail in Chapters 3 and 4. It is also
desirable to minimize the final overshoot to minimize the sensitivity to nonlinearity
in the ramp rate.
To address these requirements, the charge transfer phase for the prototype was
divided into three sub-phases: preset phase (P), coarse charge transfer phase (Ei),
and fine charge transfer phase (E 2 ). The time available for each sub-phase is as
illustrated 'in Figure 2-4. The time spent on coarse and fine charge transfer are signal
dependent because of the self-timed nature of the comparator-based circuit.
02fli
E,
E2
S
VOM
\I
VCM
(a) (b)
Figure 2-5: Preset phase (P). (a) Switch P closes. (b) vo grounded and vx set below
VCM
2.3.1 Preset Phase
To ensure the voltage vx starts out below the virtual ground condition VCM, a brief
preset phase is used. Assuming the input has just been sampled onto Ci and C 2 , the
summing node voltage vx starts at VCM. If at the same time C2 is connected to VCM,
the output node is also switched to the lowest voltage in the system (ground), then a
negative step results at the summing node vx through the capacitive divider C, and
C2. This negative step can be used to ensure the preset voltage for vx is less than
the common-mode voltage over a range of input voltages.
To derive the valid input range for the given preset method, the preset value of the
summing node voltage vxo is found from its initial voltage VCM and the superposition
of the voltage steps at vx from closing the switches at C2 and C, to VCM and ground
1
respectively
C1 + C2 C1 + C2
Therefore, the preset value for the summing node is
x= (2 - c )VcM - VIN. (2.3)

C1 + C2
Using the constraints that the summing node voltage vxo must be greater than zero
and less than VCM results in the following valid input range for a gain of two stage
2VcM 5 VIlN- 3 VcM. (2.4)
Assuming that VCM is halfway between the supply rails, this is exactly the same input
range required to keep the output within the supply rails.
During the preset phase, the output sampling switch S is also closed after the
preset switch to ground has been closed. Therefore, the preset state also resets the
load capacitance before charge transfer begins.
2.3.2 Coarse Charge Transfer Phase
To obtain a quick, rough estimate of the output and virtual ground condition, a
relatively fast ramp-rate is used in the coarse charge transfer phase. The coarse
phase ramp is generated with current source I1 in Figure 2-6. Because of finite delay
of the comparator, the output of the gain stage overshoots the correct value
Vo1= tdl (2.5)

CE
1
The same result can be derived using charge conservation at the summing node before and after
the switches are closed.
02 ~ili~
E2 I~
S ----- ~
II (
VCM
VCM
Figure 2-6: Coarse charge transfer phase (El). (a) Current source I1 charges output.
(b) vo and vx ramp and overshoot their ideal values.
where I, is the coarse charging current, tdl is the comparator delay for the coarse
charge transfer phase
CE = CL + Cx (2.6)
and Cx = C1C2 /(C 1 + C2) is the series combination of C1 and C2. The overshoot of
the virtual ground condition is
VOx I = fo-Vo1 (2.7)
where
fo =
C1
(2.8)
C1 + C 2
is the feedback factor.

02 4 I I
P I
EF
E2
IVII I
-VcM t
VCM
VXI
Vx° LIA
VCM . . t
(a) (b)
Figure 2-7: Fine charge transfer phase (E 2). (a) Current source 12 discharges output.
(b) vo and vx ramp to their final values.
2.3.3 Fine Charge Transfer Phase
To obtain a more accurate virtual ground condition, a fine charge transfer phase with
a significantly more gradual ramp rate is used. The fine charge transfer ramp is
generated with current source I2 in Figure 2-7. The use of the fine charge transfer
phase also erases any noise and nonlinearity from the first comparator decision and
overshoot. It is the final overshoot that determines the offset and nonlinearity of the
stage. If the ramp rate is perfectly constant over the full-scale output range of the
stage, then the final overshoot would only be an offset, and in many systems, it could
be easily be corrected. Unfortunately, the overshoot is not constant in a real system.
Therefore, the second overshoot must be kept small enough to meet the linearity
requirements of the stage.
2.3.4 Overshoot Correction
To maximize the time available for the comparator decision in fine charge transfer
phase without placing excessive speed requirements on the comparator during the
coarse charge transfer phase, it becomes necessary to implement some sort of over-
shoot correction in the coarse charge transfer phase.
Consider the coarse phase decision shown in Figure 2-8(b). If the comparator
has a total delay time of tdl for the coarse charge transfer phase, and the reference
voltage on the comparator is the common-mode voltage VCM, then the overshoot
vov1 of the true virtual condition is relatively large. The fine phase charge current
must discharge the summing node voltage back to VcM before the comparator can
make its second decision in the fine charge transfer phase. Therefore, the overshoot of
VCM limits how much the ramp rate can be reduced for the fine charge transfer phase
while maintaining the same speed of operation. However, if the coarse phase ramp
rate is constant, then the overshoot vov1 is the same every time, and it is possible
to use a comparator reference voltage Voc that is slightly below VCM to anticipate
the threshold crossing as shown in Figure 2-8(c). The circuit implementation for
the overshoot correction used in the prototype is shown in Figure 2-8(a), where two
different references are switched to the comparator for the coarse and fine charge
transfer phases.
For a perfectly constant ramp rate, the coarse phase overshoot could be completely
canceled, but ramp rate variation and noise in the coarse phase comparator decision
place a limit on the amount of overshoot correction. The supply voltages also place
a constraint on the possible amount of overshoot correction.
VCM
VOM
SlA
C-IVl VcM
)V2
Voc Voc
0-w I
tdl td2
Figure 2-8: Overshoot cancellation. (a) CBSC stage with overshoot cancellation.
(b) vx node voltage during the charge transfer phase without overshoot correction.
The large overshoot during the coarse phase prevents the charge transfer operation
from finishing in allowed time. (c) CBSC stage with overshoot cancellation.
2.4 Noise Analysis
If the comparator is thought of as a finite time integrator,2 then the input referred
noise voltage of the comparator is inversely proportional to the square-root of com-
parator integration time
1
VnRMS oC 1 (2.9)
This is because the output noise voltage of the integrator preamplifier grows with the
square-root of integration time (random-walk)
VoRMS OC i, (2.10)
but the signal grows proportional to the integration time
vo(t) Oc ti. (2.11)
Noise analysis techniques are covered in Chapter 3. Comparator noise analysis is

covered in more detail in Chapter 4 in the context of threshold detection comparator
design. Chapter 6 presents the detailed noise analysis of a CBSC gain stage.
2.5 Ramp Linearity
Ramp linearity has an effect similar to finite gain in op-amp based systems. Therefore,
careful design of constant ramp generators is key to designing CBSC systems with a
high degree of linearity.
2It is shown in Chapter 4 that an integrating preamplifier for the comparator results in the lowest
power consumption for a given speed and noise requirement.
In op-amp based designs, the output of a gain stage is
vo = 1(+ 1 )(v"- V.o) (2.12)
1(1)
Sfo1 - (VN Vos) (2.13)
0 is the input referred offset for the

where fo =: C1/(C1 + C2) is the feedback factor, Vo
op-amp, and Ao is the op-amp DC gain.
For the CBSC case, assuming the fine charge transfer phase current source I2 has
a constant finite output resistance Ro over the full-scale output range of the stage, I2
can be expressed as
12 = I2o + 1O (2.14)
Ro
= I2o 1 + ) (2.15)
The output ramp rate for the fine charge transfer phase is
dvo
S= 12 (2.16)
dt CE
20( 1+ ) (2.17)
where CE as defined above (2.6) is the net capacitance the current source is charging
and is assumed to be constant here. For a comparator delay of td seconds, the final
output value is
Vo _ drv° td (2.18)
Vfo - )
vo N
=fo
1( 1 td
CE ) (l--Vos)
vo V (2.19)
where
Vos = foI td (2.20)

CE
is the part of the overshoot that is signal independent and looks like an input referred
offset voltage. This offset is in addition to the offset of the comparator. Completing
the analogy to the op-amp case (2.13), the effective open-loop gain is
CERo
Ao t 0 (2.21)
fotd
The finite output resistance of the fine charge transfer phase current source behaves
similar to finite gain in the op-amp case. Note that the gain can be increased in a
couple of ways. Shorter comparator delay results in a higher effective gain, but it
will trade off with noise performance. Increasing the current source output resistance
directly increases the effective gain, and increasing the signal capacitances also helps.
Finally, note that unlike the op-amp case, the finite gain term
CERo
C o (2.22)
Aof o td
does not depend of the feedback factor used.
2.6 Summary
The basic principle of a comparator-based charge transfer phase has been explained.
Its operation parallels that of an op-amp based system, but it takes advantage of the
fact that an accurate virtual ground is only needed at the sampling instant. A brief
overview of accuracy limitations was given.
2.6.1 Limitations
Because CBSC systems lack an output amplifier, they can only drive switched-
capacitor loads. This is expected since it was one of the drawbacks stated above
for op-amp systems that continuously force the virtual ground and output voltages.
Only being able to drive switched-capacitor loads does not severely limit the applica-
bility of the CBSC approach. If a continuous load needs to be driven, then an output
buffer could be used.
A related limitation is that CBSC designs cannot drive both sides of the sampling
capacitor simultaneously. This makes the technique incompatible with conventional
closed-loop offset cancellation where the input sampling capacitors sample with refer-
ence to a driven virtual ground node. The comparator is still free during the sampling
phase, and other techniques should be possible to perform offset cancellation if nec-
essary.
As discussed above, finite output resistance of the ramp current sources have an
effect similar to finite op-amp gain. However, designing a constant current source in
scaled technologies should be easier than designing a high-gain op-amp because the
current source is not directly in the signal path, and therefore it has fewer design
constraints.
To be sure, the above list of limitations is incomplete. Because this is a new
design method, further investigation is required to determine a more complete list of
limitations.
2.6.2 Advantages
Comparator-based systems have the potential for significant power reduction com-
pared to op-amp based designs because of the differences in the noise-bandwidth and
speed requirements of op-amp and comparator-based designs. See Chapter 4 and [15]
for details.
In addition, comparator-based systems are more amenable to design in scaled
technologies than op-amp based systems because of differences in the requirements
for the comparator and current sources compared to the op-amp. The big difference
is that feedback and stability concerns have been removed for comparator-based sys-
tems, and the high output resistance current sources are not directly in the signal
path.
Finally, the CBSC design method should be applicable to a wide range off switched-
capacitor circuits and compatible with most known architectures. In sampled data
systems, circuit designs that traditionally use feedback to force a virtual ground
should be compatible with the proposed virtual ground detection scheme. Switched-
capacitor filter, integrators, DACs and ADCs should all be compatible with the CBSC
technique. Because the CBSC approach utilizes architectures similar to traditional
op-amp based designs, with some notable exceptions made above, the wealth of the
design techniques and architectures from op-amp designs should transfer to CBSC
designs.
Chapter 3
Noise Analysis
Because of the transient nature of comparator circuits, the usual steady-state anal-
ysis that is performed on amplifiers is not appropriate. To determine the transient
response of a circuit, differential equations or Laplace transform methods must be
employed. These methods are well documented and widely used in electrical engi-
neering. Methods for handling transient responses of noise inputs, which are random
processes, exist [16] [17], but are not widely known or applied in the electrical engi-
neering circuit design community. Two exceptions are the areas of charge transfer
devices [18] [19] [20] and relaxation oscillators [21]. The work on charge transfer de-
vices actually addresses the more complicated case where device parameters are also
allowed to vary with time. This approach is also appropriate for the dynamic circuits
discussed here because of their large signal behavior. The linear analysis approach
presented in this thesis is only approximate, but it is significantly less complicated
than the analysis with time-varying coefficients. The differential equation analysis
presented for the relaxation oscillator jitter calculation in [21] is identical in princi-
ple to that presented in this chapter. The benefit of the approach presented here
is that it generalizes to arbitrary linear, time-invariant (LTI) systems. The time-
domain method presented parallels the usual frequency-domain approach. Finally, a
set of simple results for the special case of a white noise step input is given with both
time-domain and frequency-domain interpretations.
Recently, interest in charge-based sampling circuits [22] that periodically integrate
the input signal for a fixed amount of time has resulted in a series of papers applying
this technique for sub-sampling [23] [20] [24] [25] [26]. The sampling model and
resulting mathematics also apply to the analysis of comparator-based systems if the
periodic integration is extended to periodic filtering. While the non-stationary noise
analysis examines the details of noise behavior over a single period of operation, a
periodic filtering analysis is presented that examines a series of sampled outputs. The
sampled values form a wide-sense stationary (WSS) sequence with PSD properties
that can be calculated using the traditional frequency domain aliasing model for both
thermal and flicker noise sources. Flicker noise is not strictly WSS because the integral
of the noise PSD is not bounded on the low frequency limit. However, a finite duration
measurement of a flicker noise process is WSS and non-overlapping measurements are
independent [27] [28]. This chapter concludes with a brief summary of the key results
from noise aliasing theory for both white and flicker noise sources.
3.1 Noise Analysis Overview
Like all signal processing problems, noise analysis can be viewed in the time-domain
and the frequency-domain. Both viewpoints tend to offer unique insights to the signal
or the system. Figure 3-1 shows a generic system H(f) or h(t) and the input and
output quantities associated with frequency-domain and time-domain noise analysis.
The quantities shown in the Figure 3-1 and the relationships between them are ex-
plained in the following sections. A simple transconductance amplifier example is
used to illustrate each analysis method. To keep complexity to a minimum, the series
of examples only solve for the output noise voltage. The issues of gain and input
referred noise are addressed later in the chapter.
Frequency Domain Analysis
X(f) Y(f)
Sxx(f) Sy,(f)
2 2
ax Gy
Time Domain Analysis
x(t) y(t)
Rxx(t ,t2) Ryy(t ,t2)

2
o2x(t) Gy(M)
Figure 3-1: Overview of time-domain and frequency-domain analysis.
3.2 W ide-Sense-Stationary Noise Analysis

Much like sinusoidal-steady-state signal analysis, steady-state noise analysis methods
assume an input x(t) of infinite duration, which is a Wide-Sense Stationary (WSS)
random process'. A WSS random process has a mean
P:=E[x(t)] (3.1)
and variance
oa = E [(x(t) - Px)2] (3.2)

that are independent of time. Therefore, the input noise waveform has an ill-defined
amplitude, but it has a constant root-mean-square (RMS) value. In other words, it
has a constant noise power. The RMS value of the noise is commonly measured as a
time average. In circuit analysis, a noise signal is always defined to have zero mean
1Bold variables are used to denote random processes.

(,x = 0) to separate the deterministic or average response from the noise.
3.2.1 WSS Frequency-domain Analysis
The output y(t) of a linear time-invariant (LTI) system with transfer function H(f)
to a noise input can be calculated using the Power Spectral Density (PSD) of the
input signal Sxx(f). The output PSD Sy,(f) for the system H(f) can be calculated
as
S,,(f) = IH(f)l2 SXX(f) (3.3)
and the average noise power of the output signal is
2
y
S,, (f)df (3.4)
f--c00
Notice that a two-sided PSD has been assumed in this definition. Because the two-
sided PSD Syy(f) is symmetric around zero frequency, a one-sided PSD is customarily
used
Sx(f) = 2 S3x(f) (3.5)
S,(f) = 2S,,(f) (3.6)
S,(f) = IH(f)12 SX(f) (3.7)
and the integral limits are taken from 0 to +oo
ca2= S(f) df . (3.8)
As a final point, the output noise signal also has zero mean and a constant RMS value
which means that the output noise is also WSS.
Example 3.1 Transconductance Amplifier: WSS Frequency-domain Anla-

ysis
0-
+ I I I +
Vx GmV , i R C V
Figure 3-2: Transconductance Amplifier.
For comparison to the other analysis methods, the WSS frequency-domain noise
analysis of the simple transconductance amplifier in Figure 3-2 is presented. The input
noise signal i, is the white noise current source associated with the transconductance
device and has a one-sided PSD
Si,(f) = Si,(0) = 4kTGn (3.9)
where Gn, is the noise conductance for the current noise source in. The transfer
function from the noise current to the output voltage is simply the impedance that
the current source drives
Ro
H(f)= 1 + j(3.10)
1+j27f TO
where To = R,,C. The output voltage PSD for the amplifier is
So(f) = H(f)|2 S ,(f)
= 4kTGn, (f)2 (3.11)
The usual method to determine the integral for the output noise voltage (3.8) for
a white noise input is to define an effective noise bandwidth NBW for the transfer
function H(f)
NBW = )i2 IH(f)12df
|iH (3.12)
47
'
10" 10d 10Y 1010 1011
frequency (Hz)
Figure 3-3: Noise Bandwidth (NBW) for a one-pole system.
which has the well known result for a single pole transfer function
.
NBW = f3dB = (3.13)
2 4To
The NBW is shown graphically in Figure 3-3, and it can be thought of as the equiv-
alent brick-wall filter bandwidth. The output noise voltage is then
Vo= S,, (O) JH(0)12 NBW (3.14)
2 1
= 4kTGR
° 4RoC
v2 - ) (GmRo) (3.15)
0Gm C
3.2.2 WSS Time-domain Analysis
The problem can also be solved in the time-domain using the autocorrelation 2 of the
noise instead of the PSD. Autocorrelation is defined as the correlation between the
value of a random process at two different time instants
Rxx(t, t 2 ) = E[X(tl)x(t 2 )]. (3.16)
For a WSS random process, the autocorrelation is only a function of the time differ-
ence 7 = t2 - tll
Rx,(Tr) = E [x(t + T)x(t)]. (3.17)
This property is the result of the mean and variance of x(t) being independent of
time. The Einstein-Wiener-Khinchin Theorem [29] states that the two-sided PSD
and the autocorrelation are related through the Fourier transform j{} with respect
to 7
Rxx (T) Sxx(f). (3.18)
To calculate the response of an LTI system h(t) to x(t), the multiplication in the
frequency domain by the transfer function is replaced by convolution with the impulse
response
R,(T) = Rxx(T)*[h(r)*h(-7)] (3.19)
and the output noise variance is
= RyY(0).
Ya2 (3.20)
2n1 general. autocovariance (Cxx(tl, t 2 )) should be used for random

processes with nonzero mean,
but since all noise random processes are defined to be zero mean, the autocovariance and the auto-
correlation are equal.
Cxz(tl1, t2) = Rx (t, t2) - 2
The autocorrelation of a WSS white noise process is the inverse Fourier Transform
of its PSD, which is constant over all frequencies. Therefore, the WSS white noise
autocorrelation is
R.0(T) = SX,(O) 6 (T). (3.21)
For a WSS white noise input the two convolutions simplify to a single integral
0 = S2x(O) jh(a)12 doa. (3.22)
Because the time-domain analysis requires two convolutions in general and the fre-
quency domain analysis only requires multiplication and one integration, the time-
domain method is very rarely used.
Example 3.2 Transconductance Amplifier: WSS Time-domain Anlaysis
For the same transconductance amplifier in the previous example (Figure 3-2),
the impulse response from the noise source to the output voltage is
h(t) = e-t/r • u(t). (3.23)

C
The autocorrelation for the current noise is
= 1Si,,(0)6(T)
Rilnin (7) (3.24)
where Sj(0) is the same as defined in Example 3.1. Substituting these values into
(3.22), the output noise voltage variance can then be calculated as
2= 2kTGn C2 e-2a/T doe
vwi= idnn (GmRo) (3.25)
which is identical to the result found in the previous example (3.15) using frequency-
+
V,
) in Ro C Vo
(v x-V T)G m -
ti I
Figure 3-4: Transconductance amplifier operating as an integrator (VH > VT).
/V
- I
-A
s in
(0)
2kTGn
I
VT Vx
Figure 3-5: Large signal response of transconductance device with noise.
domain analysis.
3.3 Non-stationary Noise Analysis
As motivation for non-stationary noise analysis, consider the case of the example
transconductance amplifier operating as an integrator (Ro - o00). If the transcon-
ductance device has the device characteristics shown in Figure 3-5 and is driven with
the v,(t) waveform shown in Figure 3-4, the noise in is applied at time zero and re-
Figure 3-6: Step noise signal x(t). Underlying WSS noise process v(t) applied at
t = 0. For tl or t 2 less than zero, the autocorrelation for x(t) is zero, and for tl
and t 2 greater than zero, the underlying WSS autocorrelation R,,(tl, t 2 ) defines the
autocorrelation of x(t).
moved at time ti. Assuming that the time the noise is applied tj is much less than the
time constant at the output To, the output voltage does not reach steady-state and
WSS noise analysis does not apply. This section presents the techniques for analyz-
ing non-stationary noise problems given in [16] [17] in the context of circuit analysis
problems.
3.3.1 Non-stationary Time-domain Analysis
In order to determine the response of an LTI system to a step noise input, the problem
is more conveniently solved in the time-domain. Assume the input is constructed from
an underlying WSS process v(t) applied at time zero
x(t) = v(t)u(t) (3.26)
where u(t) is the unit step function. An example step noise waveform is given in
Figure 3-6. This is a non-stationary random process; the mean and variance of x(t)
are functions of time. The autocorrelation is then
Rx(tl, t 2 ) = E[x(tl)x(t 2 )] (3.27)
= E [v(t 1)v(t 2)u(tl)u(t 2 )]
= E [v(tl)v(t 2 )] E [u(tl)u(t 2)]
= R,,(t 1 , t 2) u(tl)u(t 2 ) (3.28)
which is the autocorrelation of the underlying random process when both time points
are after the noise input was applied. In order to simplify the non-stationary auto-
correlation expressions, it is always assumed that (0 _ tl < t 2 ). For a white noise
step input
R,,(tl, t 2 ) = Sxz(O) 6(t 2 - t 1 ) (3.29)
where Sx(I)0) is again the two-sided white noise PSD. The transient response of an
LTI system with impulse response h(t) to a step noise input can be calculated by
convolving the input autocorrelation function with the impulse response once for
each time index to obtain the output autocorrelation 3
Rxy(tl, t2 )= Rxx(t, t2) * h(t2)
=1 Rxx(t, -r)h(t2 - T)dT (3.30)
1)
Ryy(tl, t 2 ) = Rxy(tl, t 2 ) * h(t
=1 Ry (T,t 2 )h(ti - T)dT. (3.31)
The procedure is similar to the WSS time-domain analysis except that the absolute
value of each time index is important for a non-stationary signal, and only the time
difference was important for WSS signals. Setting the two time indexes equal to each
3
The intermediate result Ry (t1 , t 2) is known as the cross-correlation.
other gives the variance of the output as a function of time
a7(t) = Ryy,(tl, t2) 112 (3.32)
where tl = t 2 is the same as - = 0 in the WSS case. For a white noise step input,
the two convolutions again simplify to a single integral
o2(t) = Sex(0) Ih(T) 2 dT. (3.33)
The output variance changes over time and has a transient and steady-state solution
that depend on the system to which the noise was applied. Notice the similarities
between (3.33) and (3.22). The only difference is in the upper limit of integration,
infinity in (3.22) and time in (3.33). Because stable systems have impulse responses
that decay to zero as time goes to infinity, the output noise variance approaches the
WSS result as time approaches infinity.
Example 3.3 Transconductance Amplifier: Non-stationary Time-domain

Analysis
Again, the impulse response from the noise current to the output voltage for the
circuit in Figure 3-4 is
h(t) = e-t/lr u(t). (3.34)
C
The autocorrelation for the step current noise is
R,,(tl, t 2 ) = IS-n,(0)6(t 2 - t 1) (3.35)
R,,(t1 , t 2 ) = 2kTG,6(t 2 - t1 ) u(ti) u(t 2 ). (3.36)

The output noise voltage variance from (3.33) is
t 1 2
v2 (t) = 2kTG e-02a/ro
v2 (t,) =
Gm
k1(GmRo)
kT
C
- -2ti/] u(t) (3.37)
which is valid for all values of the amplifier response time ti. Two limiting cases are
of interest: ti < ro and ti > -T.
For times much shorter than the time-constant at the output of the amplifier
(ti << To), the transconductance amplifier operates as an integrator. Using the first
two terms of a Taylor approximation for the exponential
e- 2t
i ro
/ - _ 2ti for ti < T/2 (3.38)
To
and (3.37) is approximately,
vz2(t) =
2kTGn t0u(t) for tj < 7</2. (3.39)
In this case, the output noise voltage is a Weiner process, also commonly referred to
as a random walk or Brownian motion. Think of the current noise source as either
adding or removing a packet of noise charge to the capacitor at each instant of time,
and the probability of doing so at each time instant is independent of what happened
at all previous times. The average charge added to the capacitor is zero, but the
variance grows with time. It should be noted that this result is not obtainable using
traditional WSS frequency-domain analysis.
The other case of interest is what happens for times much longer than the system
time constant (ti > To), in other words the steady-state solution. For this case, the
exponential term in (3.37) goes to zero, and the output noise voltage variance is
-- = (Gn) kT
vo(t) = (GmRo) (3.40)
55
. . IJ.-\
VC RMS~) I
R =0
=0 VCoRMS1
1 2 3 4 5 6 7
I I~
(b)
Figure 3-7: Noise initial condition example: capacitor reset noise. (a) RC circuit
with capacitor reset noise (R > Rswitch). (b) Capacitor RMS noise voltage from
initial condition for t > 0.
but (3.40) is recognized to be the same as (3.15) and (3.25), the WSS solution.
3.3.2 Noise Initial Conditions
Another issue with time domain noise analysis is the handling of initial conditions
on capacitors and inductors. The above method determines the noise response for
zero initial conditions, also known as the zero state response. Assuming the initial
condition is statistically independent of the noise input, the system can be analyzed
for zero state and initial condition responses separately. Consider the parallel RC
circuit in Figure 3-7 with a reset noise initial condition on the capacitor. For the
initial condition response, assume a zero average initial condition with some variance
(kT/C noise)
vc( (0)= = 0 Initial condition mean (3.41a)
Sv(0) = v• Initial condition variance (3.41b)

and assume that the initial condition is independent of other noise. For each trial in
the ensemble, the system response to an initial condition is
vc(t) = vc(O) e- t /lt u(t) (3.42)
where T0 = RC. Then, the ensemble average is
v--(t) = E[vc(O)] e- t/ro u(t) = 0 (3.43)
and the ensemble variance is
vC(t) = E [v(0) e - 2 t/o] u(t) (3.44)
= vIo e- 2t/ro u(t). (3.45)
The standard deviation of the noise voltage decays at the same exponential rate
as an average initial condition. Because the initial condition response is assumed
independent of the zero state response, the variances simply add.
3.3.3 Non-stationary Noise Interpretation
To understand the meaning of a time-varying variance (or standard deviation), it is

necessary to discuss more precisely the averages used to define the statistics of ran-
dom processes. When dealing with non-stationary random processes, it is important
to realize that ensemble averages and not time averages are being used. The ran-
dom process x((, t) represents a collection of many x(t) realizations, and each one is
associated with a specific value ( = (j, where ( is a random variable. An ensemble
average is taken over all realizations ( at a fixed time ti. In contrast, time averages
are an average over time for a fixed realization (i. The two are equivalent in the case
of a stationary random process because the mean and variance are independent of
time. While it is convenient to think of random process statistics as time averages
for the WSS case, the results of a non-stationary analysis require the interpretation
of the statistics as ensemble averages. For example, consider a noisy current source
charging a capacitor, the capacitor voltage is shown in Figure 3-8. Because the system
is linear and superposition applies, the composite waveform can be separated into the
average ramp that the DC current causes and a noise voltage that the noise current
integrating on the capacitor causes. At any point in time, the possible values of the
noise waveform are given by a statistical distribution. A time varying noise variance
implies that the standard deviation of the voltage distribution is changing with time.
Therefore, the noise voltages and currents calculated represent the standard deviation
of the signal taken over many experiments.
3.3.4 Non-stationary Frequency-domain Analysis
Because the definition of the PSD assumes that the variance of the noise process is
independent of time, the PSD of a non-stationary process is not very meaningful.
However, a slight reformulation of the problem allows for a frequency domain inter-
pretation to the non-stationary noise problem for a white noise input. First, rewriting
(3.33) as
o (ti) = S00()O Ihw(a)I2 do (3.46)
where
h,(t) = h(t)w(t) (3.47)
and w(t) is a rectangular window from 0 to ti. An example of a windowed impulse

response is shown in Figure 3-9. Next, Parseval's Theorem can be used to rewrite
(3.46) in the frequency domain
2(ti) = Sx.x(0) j IH(f)12 df
= S(0) j HW(f)12 df (3.48)

' I(t
VX\LJ
t
(a)
VX LJ
t
(b)
• /÷
vnx L,x
(c)
Figure 3-8: In transient noise analysis, it is ensemble averages and not time averages
that are most important. (a) Ramp voltage plus random walk noise. (b) Average
ramp voltage. (c) Random walk noise voltage showing 3a bounds.
·_
h(t) w(t)
h, 1
t
I k •
Figure 3-9: Windowed impulse response.
where again S,(0) = 2Sz(0). Because multiplication in the time-domain is con-

volution in the frequency-domain, the time-dependent transfer function H,(f) is
calculated as
W(f) = ti sin (7irft) ej2rft/2 tj sinc (fti) ej2i fti/ 2

(3.49)
H,(f) = H(f) * W(f) = Tf{h(t)}. (3.50)
Upon examination of (3.48) and review of the WSS frequency-domain analysis, it is

possible to define a generalized effective noise bandwidth that is a function of time
NBW(ti) = Ho)2 IHw(f ) 2df (3.51)
= 1 t h(t) 12dt (3.52)

| fo h(t) dtl 2 0
Figure 3-10 shows what happens to H,,(f) as ti increases for a one-pole system. For
small ti, NBW is larger, but the amplitude is lower. Because the input PSD is being
amplified by a gain proportional to t , and the NBW is inversely proportional to ti,
the output noise voltage variance is proportional to ti. As ti gets to be much larger
than T• of the system, the transfer function approaches IH(f) . Therefore, the NBW
also approaches the steady-state NBW for large ti.
_ ·__ I_~·
loglo IH,(f
IHo
4
I 'V 10'
2Figure
3-
Frequency
Domain: Transfer function for different window widths (ti)
Figure 3-10: Frequency Domain: Transfer function for different window widths (ti)
Example 3.4 Ideal Integrator: Frequency-domain Analysis

Consider the ideal integrator from the previous example that integrates the input
white noise current i, onto the output capacitor C. The impulse response is a step
function
h(t) = Iu(t). (3.53)
To determine the windowed response transfer function, it is easier to perform the
multiplication in the time-domain first and then take the Fourier transform
ti - 7ri 2
H,(f) = sinc (fti) e j2 ft / . (3.54)
C
Recalling the definition of NBW (3.12), it is possible to define the NBW for the
transfer function H,(f) where
IH(O)I = (3.55)
C
Hi(f sin (rft)) i (3.56)

C 7rft "
Substituting into (3.51)
NBW(ti) 0"sin2 (7rfti)

1J' 7 22
sin ()trf i
NBW(ti) = • (3.57)
2ti
Using the frequency-domain method to determine the output noise voltage (3.14)
v0(ti) = Si, (0)IH(0) 2NBW(ti) (3.58)

=4kTG, (i (3.59)
2kTG,
V(t~ = C2 t (3.60)
which is the same result obtained for the integrator using the non-stationary time-
domain method (3.39).
3.4 Input Referred Noise

All the examples in the previous sections calculated the output noise voltage for
transconductance amplifier, but the input referred noise is more useful for evaluating
amplifier performance. The reason is that input referred noise allows a direct com-
parison of the input signal to the noise the amplifier adds. If only the noise at the
AAA
0
VCN I[Ll
(a)
VX
Q
2
Vn
v
n
IL
VCM
(b)
Figure 3-11: Input referred noise comparator model (a) Noisy comparator results in
timing jitter cri. (b) Noiseless comparator with input referred noise v2 resulting in
the same timing jitter.
output was examined, it would appear that a better amplifier can be made by lowering
the transconductance and hence the output noise, but lowering the transconductance
lowers the signal gain faster than it lowers the amplifier output noise. Therefore,
it turns out to be better to increase the transconductance because the signal gain
increases faster than the amplifier output noise increases. In this section, the noise
gain for a comparator is defined and then used to find the input referred noise of the
comparator.
3.4.1 Noise Gain
The output noise voltage of the amplifier results in jitter of the output threshold
crossing through the rate of change of the amplifier output voltage as shown in Fig-
ure 3-11(a). To refer the output voltage noise to the input of the amplifier, it is desired
to have an input noise voltage that results in the same comparator jitter when the
input voltage ramp crosses the input threshold voltage as shown in Figure 3-11(b).
Determining the noise gain requires a discussion of noise voltage to timing jitter
conversion and timing jitter to noise voltage conversion. The result is that the ap-
propriate noise gain is defined as a ratio of the output to input time derivatives at
the output and input threshold crossings respectively.
Noise Voltage to Timing Jitter Conversion
The conversion of noise voltages to timing jitter happens when a noisy signal is sensed
by a threshold detection device [30]. To see how this occurs, consider Figure 3-12.
The signal crosses the threshold VM at some average rate dvx/dt and has a noise
voltage distribution at the average crossing time ti as shown on the right. Assuming
the noise voltage variations are small over the range of possible crossing times, the
standard deviation of the noise voltage projects back to the threshold with the average
slope,
-2
or2i = -2n dt (3.61)
defining the standard deviation of a distribution of times the threshold is crossed.

The variation in time is the jitter in the threshold crossing.
In some sense, the above description is an oversimplification of what actually oc-

curs. If the noise was a high frequency signal superimposed on the average signal, the
noise would consistently cause early threshold crossings. However, in the transconduc-
tance amplifier, the output noise voltage is the integration of the white noise current
which is random walk noise. Amplitude variations in random walk noise are much
slower than for white noise. For example, consider the signal plus noise waveform
shown in Figure 3-8(a). Superimposing a threshold voltage on this waveform shows
that the noise does result in a distribution of times about the average crossing time
as described in the model above.
vx(t)
VM ---
-I
I
III t
Figure 3-12: Transformation of voltage noise to timing jitter in the comparator deci-
sion.
Timing Jitter to Noise Voltage Conversion
The conversion of jitter back to a noise voltage is commonly invoked in the clock
jitter analysis of sampling circuits [31] [32]. The idea is that for some input signal
rate of change, random variation in the sampling instant results in a random error in
the sampled value
v• = 2vx2
X_2 (3.62)
where ati is the RMS timing jitter of the sampling clock. Referring again to Fig-
ure 3-12, the transformation of timing jitter into a sampled noise voltage is just the
reverse of the noise voltage to timing jitter conversion.
Input Refierred Noise and Noise Gain
Using the above results, the amplifier introduces a jitter at the output
-2
02=2 dvo
ati = fl dt (3.63)
where VIMo is the threshold voltage at the output (input threshold of next stage). For
an input referred noise voltage vn, the jitter calculated at the input is
-2
2 dvx =V (3.64)
i v I dt
VX = 1VCM
where VCM is the threshold at the amplifier input in Figure 3-11. Setting the jitter
from the output noise equal to the jitter from the input referred noise, the input
referred noise is
2 V2
on (3.65)
S AN 2
where the noise gain is
AN
( dvo
=V(3.66) dt
dvx
which is the ratio of the rate the output threshold is crossed to the rate the input
threshold is crossed.
Example 3.5 Transconductance Amplifier: Input Referred Noise

Consider the amplifier shown in Figure 3-4 with a step ramp input
vx(t) = Mt u(t) (3.67)
shown in Figure 3-13 where M is the slope of the ramp. For simplicity, assume the
threshold voltage for the transconductance device is zero (V1 , = 0). The response of
the amplifier to a ramp input is
vo(t) = AoM[t - To(1- e-t/)] u(t) (3.68)
where Ao = GmRo is the DC gain of the amplifier. Using (3.66), the input slope is a
1 c' 'i
2kTGn rt
Figure 3-13: Step ramp input and corresponding step noise input.
VM
'II
Figure 3-14: Response time ti for amplifier to reach output threshold Voi,.
constant M, and the output slope is
dvo
= MAo [1 - e-tI/ro] u(ti) (3.69)
dt vo=VMo
where ti is the response time for the output to cross its threshold VMo as shown in
Figure 3-14. The noise gain is
JAN(ti)I = Ao [1 - e -t i/ Tr] u(ti). (3.70)
Using the expression for the output voltage noise (3.37) derived in Example 3.3,
the input referred noise is
2 (t,) - v-
Vnz IAN(ti)1 2
kT)
(G
G C (1) 1+i']ei - t / u(t)
)=-G=(kT))(I) coth )u(ti). (3.71)

1011
N
" 1 10
9
10
10-11 10-10 10-9 10-8

ti (s)
Figure 3-15: Noise Bandwidth versus response time ti. T, = 250 ps
The noise bandwidth can be factored out of (3.71)
v2 (t,) = 4kTRn NBW (3.72)
NBW(ti) = coth u(ti) (373)
where R, =: GI/Gm is the usual input referred noise resistance of a transconductance

amplifier. Figure 3-15 shows a plot of NBW versus response time ti. The limiting
behavior of these expression are now presented for ti < To and t.i
> To.
For times much shorter than the time-constant at the output of the amplifier
(ti <« To), the transconductance amplifier operates as an integrator. Using the first
two terms of a Taylor approximation for the exponential (3.38), the output voltage
grows quadratically with time
vo(t) = m)Mt2 u(t) (3.74)

and the noise gain grows with time
IANI= Gm i.
GA
(3.75)
The output random walk voltage noise expressed in terms of the noise bandwidth is
v= 4kT i
NBW (3.76)
0 ( )2
and the input referred noise is
v = 4kTR, NBW (3.77)
where the noise bandwidth is

1
NBW = . (3.78)
2t,
The noise bandwidth is inversely proportional to the response time ti as shown in

Figure 3-15.
The other limiting case of interest is the steady-state solution (t > To). For this
case, the exponential terms in (3.71) go to zero. The output voltage is a delayed
version of the input with the slope scaled by the DC gain
vo(t) = AoM [t - To] u(t). (3.79)
The noise gain is then just the DC amplifier gain
IANI = Ao (3.80)
and the output noise voltage is
kT
=( Gn-C- (GmRo).
- 1
v = 4kTG- (3.81)
4To
The input referred noise voltage is the expected kT/C noise
v2- G= (3.82)
" Gm C Ao
and the noise bandwidth in this case is
1x
NBW= - f3dB (3.83)
4To 2
which is the familiar fraction of the 3dB bandwidth.

The shape of the NBW versus response time plot in Figure 3-15 is determined by
the hyperbolic cotangent function. Because the input referred noise is the input re-
ferred white noise PSD times the NBW, the input referred noise voltage has the same
shape as the plot in the figure. In addition, Figure 3-15 shows that the intersection
of the steady-state and band-limiting asymptotes is ti = 2To.
3.5 Periodic Filtering Frequency Domain Model

While the non-stationary analysis of noise sources describes the circuit response to
the step noise input in detail, in most cases the final value is sampled and the system
operates on. a series of discrete-time samples. Therefore, it is the statistics of the series
of samples that are of interest. Even though the details of the processing during each
period results in non-stationary noise voltages and currents, the same operation is
performed each clock cycle, and the signals have the same statistics each clock cycle.
This means that the process is wide-sense cyclo-stationary (WSCS). The periodically
sampled values then all have the same statistics and form a WSS discrete-time series.
First, the periodic filtering sampler model is described, and the filter transfer function
is defined. Then, well known noise aliasing techniques can be applied to obtain a noise
PSD estimate for the series of samples.
The derivation for the model of a periodic filtering sampler follows that presented
8T (t-ti)
x(t) - h,(t) y(t) y(nTs+ti)
Figure 3-16: Periodic filtering sampler model: the output samples can be modeled as
the impulse train sampling of the input filtered by Fourier transform of the windowed
impulse response.
in [20] for a periodic integrating sampler. The value of the nth-sample of the output
y(t) for a system that integrates the input x(t) from time nT, to nT, + ti is
nTs+tj
y(nT, + ti) = z() dT (3.84)
JnTs
So0x(TF)w(,+ti - -F)dT (3.85)
where w(t) is the rectangular window function of unit height and duration ti. Realiz-
ing that the second integral is just the convolution of the input x(t) to a time-shifted
impulse response of a finite duration integrator w(t), the procedure is easily extended
to finite duration filtering of an arbitrary impulse response
0+oo
where h,(t) = h(t)w(t) is the windowed impulse response. It should be noted that
it is the zero-state response that is found from the convolution of the input with
an impulse response. Therefore, this procedure assumes the output is reset between
operations. Continuing with the model derivation, the series of periodically filtered
samples can be expressed as the infinite sum of samples
+00 +00
Z
n=-oo00
y(nT , + ti) 6(t - nT, - ti) = y(t) E
n=-oo00
6(t - nT, - ti) (3.87)
which is an impulse train sampling of the output. Using the usual short-hand for the
sampling impulse train
+oo
6T(t)= (t - nT) (3.88)
the output samples of the periodic filtering system can be modeled as shown in Fig-
ure 3-16 according to
y(t) 6 T (t - ti) = [x (t) * h(t)] 6 T (t - ti) (3.89)
where the filter function H,(f) is the Fourier transform the the windowed impulse
response.
H(fi) = h(t)e - j (2' f)t dt. (3.90)
The model in Figure 3-16 reduces to that originally suggest in [22] and used in [24] [25]
for a period integrating system. The periodic filtering model also works to describe
the classic RC sampling circuit. Because the switch and capacitor are assumed to
reach steady-state, the filter function is just the RC low-pass filter of the switch and
capacitor.
The advantage of generalizing the periodic integration model to handle periodic

filtering is that the variation in output samples from periodic filtering of noise sources
can be analyzed using well established noise aliasing theory where the transfer func-
tion for the noise sources is the H,(f) from the noise source to the output. The
procedure for determining the filter transfer function is to find the Laplace s-domain
transfer function from the noise source to the output. The inverse Laplace transform
yields the system impulse response, which is then windowed by w(t) from 0 to ti.
The Fourier transform of the windowed impulse response produces the desired filter
function. Summarizing mathematically,
H(s) = h(t) (3.91)
h,(t) = h(t)w(t) (3.92)
h,(t) = H,(f). (3.93)
The noise PSD of the sampled output can then be found from the sum of the filtered
and shifted input noise PSD [33] [34] [35] [36] [16]
+00
Sy,(f) = wg (f - nfs) 2
Sz'(f - nfs) (3.94)
n=-00
which is valid over the two-sided Nyquist range (-.fs/2 < f < f,/2). Alternatively,
the one-sided aliased noise PSD S,(f) valid from 0 < f < f,/2 can be calculated as
+00
Sy(f) = HE - nfs) 2 2S,,(f - nf8 )

Iw(f (3.95)
n=f-0o
where 2S.z$(f) is the same as assuming a two-sided input noise PSD with the one-
sided PSD magnitude. The limits of summation can be truncated to a finite value
from knowledge of the effective noise bandwidth of H,,(f) [34]. A more extensive
review of key noise aliasing proprieties are given in Section 3.6.
Example 3.6 Periodic Filtering Sampler: Periodic Integration
Consider the simple case of periodic integration of a noise current ix(t) onto a
capacitor Cs for ti seconds every T, seconds. The s-domain transfer function from iZ
to vo is
1
H(s) = . (3.96)
sC,
loa IH.. (f)l
ti
Cs
I log f
2t i
Figure 3-17: Periodic integration filter H,(f). DC gain IH,(0)I = t/ C, and one-sided
noise bandwidth NBW = 1/(2ti).
Taking the inverse Laplace transform results in
1
h(t) =
Csu(t) (3.97)
for an infinite duration integrator. Truncating the impulse response at ti gives the
windowed impulse response
1
hw(t)= w(t), (3.98)
Cand
finally,
the
periodic
integration
filter
is
and finally, the periodic integration filter is
Hw(f) (C 1 - e
j(27rf)ti
- j 7
(2 f)ti
(3.99)
Simplifying and calculating the magnitude squared of the filter function
Si i 2 sinc2(fti)
(3.100)
which is a simple sine filter with a one-sided noise bandwidth of 1/(2ti). A plot of
H,(f) is given in Figure 3-17. The aliased output spectrum then is
+oo00
Svovo(f) = S
nf-o00
Hw,(f - nfs,) 2 SX(f - nfs) (3.101)
which if the current source noise ix has a white noise PSD Sx(0), the one-sided
output voltage PSD simplifies to
s
Svo (f) =- Sx(O0)() (3.102)
The output PSD is the expected random walk noise with a white PSD over the Nyquist
range. Because the integration time must be less than sampling period ti < Ts,
f NBW (3.103)
2 -
which means that the noise aliases for all integration times and has an essentially
white noise PSD.
3.6 Noise Aliasing

Aliasing theory of noise is reviewed highlighting key results that are used in the noise
analysis of the prototype CBSC pipeline ADC. The aliasing of white noise and flicker
noise are addressed along with useful approximations. Finally, a discussion on the
number of terms that must be included in the aliasing summation to include some
percentage of the total noise power given the system noise bandwidth.
3.6.1 White Noise Aliasing
The simplest way of thinking about white noise aliasing is in terms of the conservation
of noise power. For a stationary signal, the RMS value of a sampled signal must be the
same as the RMS value of the original signal. More generally, the ensemble variance of
-4fs -3fs -2fs -fs 0 fs 2fs 3fs 4fs
-NBW +NBW
Figure 3-18: White noise aliasing NBW = 3fs [34].
the original signal at the sampling instant must be the same as the ensemble variance
of the sampled value
02 =H(O) 2 So,NBW = 2 (3.104)
where Sx(f) = Sxo is the white noise input PSD. The noise in the original bandwidth
has been aliased to the baseband frequency range from 0 to fs/2 such that [34] [35]
[33] [37] [38]

) H(0)/2 (3.105)
which means that the aliased spectrum is approximately the original white noise with
a multiplier of NBW/(f,/2). The multiplier is approximately the number of aliased
spectra that fall into the baseband frequency range of -f,/2 < f < f,/2 as shown in
Figure 3-18 [34].
In contrast to sampled signals where the signal bandwidth is always contained

within a single Nyquist band, the noise bandwidth of a sampling system is always
greater than or equal to f,/2. Therefore, noise aliasing is the norm in sampled
systems.
3.6.2 Flicker Noise Aliasing
Flicker noise aliasing can also be examined under the assumption of the conservation
of noise power; however, it is more often instructive to decompose the aliased spectra
into its direct feed-through and folded components. The results can then be examined
in terms of noise power or as a PSD. Both approaches yield different insights to the
aliasing of flicker noise and both are considered below. Only the case of unity flicker
exponent 1/f is considered for mathematical simplicity.
The pre-sampled one-sided noise PSD for flicker noise is
S3 (1)
S (f) =- (3.106)
f
where an example PSD is shown in Figure 3-19(a). The total noise power is found
by integrating the noise PSD
to0tal =
CT2 ff- H() 2 S (1)
JH(a)124 df
df (3-107
(3.107)
- H(0) 2S(1) In( fH(3.108)

where Sx(1) is the flicker noise at 1Hz, fH is the upper frequency limit (NBW),
fL = 1/(2To) is the lower frequency limit, and To is the duration of the measurement.
The interpretation for the lower frequency limit is that for a given measurement
duration very low frequency variations appear as a DC offset. Decomposing the total
noise power into its direct and folded components results in
tota I = ' 7 direct + (Tf old (3.109)
where
S= H(O)
Udirect = JH( 2S(1)ln
kJ In fA (3.110)
(3.110)
Sxx(f)
-NBW +NBW
(a)
S,,(f)
-NBW +NBW
(b)
Figure 3-19: Flicker noise aliasing (a) Original pre-sampled PSD with flicker and
thermal noise. (b) Folded flicker noise.
10
10
10
10
1n
10- 3 10-2 10-1
f/fs
Figure 3-20: Total sampled flicker noise PSD showing direct feed-through contribution
and apparent white folded flicker noise.
and
old = H(0) 2 Sx(1)ln (f2 f (3.111)
It is interesting to note that the folded flicker noise power is independent of the
measurement duration To, but for a fixed sampling frequency, the direct feed-through
flicker noise contribution depends on the measurement duration.
Figure 3-19(b) shows how the folded aliased combine to make up the folded flicker
noise PSD. It is evident from Figure 3-19(b) that the folded flicker noise PSD is
approximately constant over the Nyquist band -f,/2 < f 5 fs/2. The white noise
approximation is discussed below. Assuming the folded flicker noise is essentially
white,
Syfold(O) H(0)12 ln ( f/ 2 (3.112)
and neglecting the logarithmic term, the amount of folded noise is inversely propor-
tional to the sampling frequency. In addition, the PSD originally contained in the
Nyquist band feeds directly through to the output
2Ssx(1)
Sy,direct(f) IH(0) I2 S ( 1 ) (3.113)
Therefore, the total aliased flicker noise PSD is approximately the sum of direct feed-
though component and an essentially white folded component
Sytota(f) H(0)J2 1 + In f )] (3.114)
where an example aliased flicker noise PSD showing the direct and folded contribu-
tions is given in Figure 3-20 The significance of the folded flicker noise is discussed
more below.
A PSD approach to the aliasing problem is now presented that justifies the ap-
parent white noise approximation for the folded flicker noise and gives a useful closed
form approximation for its value.
The spectral aliasing summation (3.94) can also be decomposed into its direct and
folded components. The direct feed-through component is the case where n = 0 in
the summation
Sy,o(f) = IH(f)12 Sx(f). (3.115)
For the noise originally contained in the Nyquist range, the sampler filters the noise
PSD. but otherwise leaves it unchanged.
The folded flicker noise is all the other terms in the summation
+00
Syy,fold(f) = E IH(f - nf) )l2 Sx(f - nfs). (3.116)

n=-o0
n$O
Simplifying the summation to handle one-sided PSDs
Sy,fold(f) = EIH(nfs - f)1 2 Sx(nfs - f) + IH(nfs + f)12 Sx(nf, + f) (3.117)

n=1
which is valid from 0 < f < f,/2.
Useful closed form results for the folded flicker noise can be obtained assuming a
simple one-pole filter with unity gain
2
.. ,9
H() 1 + (f /fc) 2 (3.118)
where fe is the 3 dB frequency of the filter. The filter serves to bound the flicker noise
at high frequencies. Then, the folded noise summation can be approximated by its
first term and the contribution from the rest of the terms bound using the Integral
Test from calculus [39]. For example, if the first term of (3.117) is written as the sum
of the n = 1 term and the remaining terms
1 1 1, 1 1
S=1 nf, - f 1 + (ff 2 f f+ 2nf- f (f 2 (3.119)
then a upper and lower bounds can be place on the remaining summation
00 1 •I
(3.120)
n= S+0nfs- f 1+ (fIf,)2 d
where a is 1 for the upper bound and 2 for the lower bound. Enz [35] approximated
the summation using an intermediate lower bound of 3/2
2nf - [1+ (ff)2 f (f/f•f )2

(3.121)
Carrying out the approximation for both terms in (3.117) and adding the results gives
S, 82z(1)f 2- n f2 (3.122)
faf 2/2_ 2 )2_ 2
which is (8) in [35]
fcs/f
Figure 3-21: Maximum to minimum PSD ratio for folded flicker noise
Syjold(f,/2) /Syfogd(0).
Figure 3-21 plots the maximum to minimum ratio of (3.122) for different ratios
of filter bandwidth to sampling frequency. Figure 3-21 shows that he apparent white
noise approximation is reasonable for filter bandwidths greater than twice the sam-
pling frequency. Assuming the folded flicker noise has a roughly constant value of
Sy,fold(f./2) from 0 to f,/2, the final approximation in [35] is
Sy,f o ld(f) S() 1 + In . (3.123)

fs1/2 fcfs/
Expressing the flicker noise at 1 Hz S (1) in terms of the white noise S,, and the
corner frequency fk
Sx(1) = Sxofk (3.124)
the folded flicker noise is proportional to the unsampled white noise PSD
Sy,fold(f) = S 0o f(1 + In ( .) (3.125)
Comparing (3.125) and (3.105), the folded flicker noise contribution is equal to the
aliased white noise when
NBW fk 1+ln (3.126)
or for reasonable (fl/f 8 ) ratios, NBW • 3fk.
3.6.3 Finite Summation Approximation of Aliased Noise
For more complicated filter functions and non-unity flicker noise exponent, the eval-
uation of the integral for the closed-form approximation of the aliasing sum becomes
difficult to solve. Therefore, it is often more convenient to find the aliased spectra
from numerical evaluation of the aliasing summation (3.94). The difficulty in this
approach is determining the number of terms in the summation to use to achieve a
desired accuracy. A method analogous to the cumulative distribution function (CDF)
from statistics is used to determine the number of terms required to achieve a certain
percentage of the total.
Intuitively, it should be possible to approximate the infinite sum (3.117) using a

finite number of terms if the filter has a finite noise bandwidth
Sy,fold(f) -= E H(nfs - f)12 Sx(nff - f)+ IH(nfs + f)12 Sx(nf 8 +

ff). (3.127)
n=O
The question is how large does N need to be to account for some percentage of
the total folded noise power. The required number of terms is related to the noise
bandwidth NBW of H(f)
N = krl (3.128)
where rq is the noise bandwidth normalized to half the sampling frequency
SNBW (3.129)
and k7r terms are required to get the desired accuracy.
Consider the white noise aliased from a one-pole transfer function. A one-pole
transfer function should be a conservative case since most other filters have lower
noise bandwidths. A CDF like plot can be made of the fraction of the total noise
power versus k referred to here as the cumulative aliasing function (CAF). Figure 3-22
shows the plot of the CAF. Note that using k = 1 is equivalent to assuming that 100%
of the noise power is contained within the noise bandwidth. However, Figure 3-22 and
Table 3.1 show that only 80.6% of the noise is accounted for with this approximation.
Table 3.1 shows the required number of rl for higher accuracy. Note that the CAF
noise power fraction approaches one slowly, but for k = 4 the sum would contain 95%
of the total noise power.
3.7 Summary
A comprehensive series of noise analysis methods have been presented for linear circuit
analysis. Their basic application has been illustrated through a series of examples.
In addition, a definition of noise gain for large signal systems has been presented
assuming an amplifier with noise and a noiseless amplifier with input referred noise
produce the same jitter. Next, a periodic filtering analysis method has been presented
that allows for the analysis of periodic samples in terms of well-known aliasing theory.
A brief review of aliasing theory is presented focusing on the lesser known effect
of aliased flicker noise. The techniques and concepts presented in this chapter are
used in later chapters to analyze comparators and their preamplifiers. The results
LL
10-' 10-' 10-' 10 10' 10'

k
Figure 3-22: Cumulative aliasing function (CAF): fraction c)f total noise power as a
function of the number k of normalized noise bandwidths 7r.
k % of Total Noise Power

1 80.6%
4 95%
20 99%
200 99.9%
Table 3.1: Fraction of total noise power as a function of the number k of the normal-
ized noise bandwidths q = [NBW/(fs/2)].
summarized in Example 3.5 for a ramp input will be used extensively.
Chapter 4
Threshold Detection Comparator

Design
4.1 Overview
Threshold comparator design for comparator-based switched capacitor circuits is pre-

sented. First, threshold comparator specifications are reviewed and contrasted with
latched based comparators that are ubiquitous in mixed-signal design. Because the
threshold comparator in the CBSC charge transfer phase determines to a large ex-
tent the noise accuracy, considerations for low noise threshold comparator design are
addressed. A band-limiting preamplifier placed in front of a traditional threshold
detection comparator is recommended, and a noise analysis of the resulting com-
parator plus preamplifier is presented drawing on the non-stationary noise analysis
from Chapter 3. A design procedure for the band-limiting preamplifier is proposed.
Finally, the design of the threshold detection comparator is discussed.
VIN
VOS a
I
VIN
Q
V rC I
'I
V w
VL
tI
td
Figure 4-1: General definition of threshold detection comparator performance.
4.2 Threshold Detection Comparators
4.2.1 Specifications
Unlike traditional latch-based clocked comparators that determine whether its in-
put voltage is positive or negative at a specific instant in time, threshold detection
comparators must determine the time at which the input crosses zero. A generic
schematic of a threshold detection comparator with its key parameters is shown in
Figure 4-1. In simplistic terms, if the input voltage is positive, the output must be
a logic high, and if the input voltage is negative, the output must be a logic low. A
comparator offset (Vo) causes a systematic error in the threshold, which for a ramp
input can also be viewed as a timing skew (t1 ) in the threshold detection. The com-
parator has a finite delay (td) from the point of crossing the offset adjusted threshold
to the logic transition. This delay varies due to thermal and flicker noise sources in
the devices used in the comparator and appears as jitter in the comparator decision.
The jitter can also be input referred and expressed as a noise voltage superimposed
on the reference voltage. The transformation of jitter to voltage noise and voltage
noise to jitter was discussed in Chapter 3.
As mentioned in Chapter 2, the role of the virtual ground threshold detection

comparator is of critical importance to the accuracy of the CBSC charge transfer
accuracy. Offset and delay errors in the decision can be tolerated in most systems,
but jitter in the threshold detection results in a noise voltage sampled onto the load
capacitance. When referred to the input, this voltage noise can be equivalently mod-
eled as an input referred voltage noise at the input of the virtual ground threshold
detection comparator. Methods for analyzing non-stationary threshold detection sys-
tems to determine their input referred noise voltage for white noise were presented
in Chapter 3. The previously obtained results for a transconductance amplifier with
finite output resistance are briefly reviewed and are used to discuss the design of
low noise threshold detection comparators. Only thermal noise is considered here to
simplify the discussion. The impact of flicker noise is addressed in Chapter 6 when
Threshold
Preamplifier Comparator
I I I I
VX Q
Vcr Q
Figure 4-2: Ideal threshold detection comparator with band-limiting preamplifier.
the analysis of the entire CBSC gain stage is performed.
4.2.2 Low Noise Comparator Design
A threshold detection comparator is usually thought of as a wide-bandwidth high-

gain amplifier possibly implemented as a cascade of low-gain amplifiers [40] [41]. The
first stage of the cascaded amplifier typically dominates its input referred noise PSD
and approximately sets the comparator noise bandwidth. Because the capacitance at
the output of the first stage is kept as small as possible to maximize the speed at a
given power consumption, the input referred noise of such an amplifier can be rather
large.
One possible solution to lower the input referred noise of the comparator is to add
a preamplifier in front of the threshold detection comparator as shown in Figure 4-2.
The sensitivity of the comparator is improved if the preamplifier has lower input
referred noise than the threshold comparator alone and if the preamplifier has enough
gain to dominate the input referred noise performance of the comparator.
In small-signal amplifiers, the frequency of the transfer function poles of the am-
plifier determine speed, but in threshold detection systems, the time it takes the
output to reach a threshold voltage determines speed. This difference in speed defi-
VvA -Vc•A
VOD
+VD
I- td
-VD. 0000/ti /71
VDD
I - --I
'td
Figure 4-3: Ideal timing for comparator with preamplifier. The preamplifier output
voltage is clamped at ±VD. (a) Preamplifier input voltage where the summing node
voltage vx has crossed the virtual ground condition at time zero. (b) Preamplifier
output voltage showing the response time ti it takes for the preamplifier output to
reach the comparator threshold. (c) Output logic signal changes stage after total
comparator delay td.
nitions is a consequence of comparators not necessarily operating under small-signal
steady-state conditions. If the band-limiting preamplifier output always starts with
the same initial condition, for the same load capacitance CL and transconductance
Gm, the fastest way to the output logic threshold is the amplifier with the highest
small-signal gain [42].
The general ramp response of a transconductance amplifier was derived in Chap-

ter 3 (3.68), and is repeated here for convenience
vo(t) = AoM[t - To(1 - e-tro)] u(t) (4.1)
where the small-signal steady-state gain is Ao = GmRo, the preamplifier time constant
is T0 = RoCi, and M = dvx/dt is the input ramp rate. Figure 4-3 shows the response
of the preamplifier and threshold comparator assuming the output of the preamplifier
is clamped to IVDI between decisions. The time it takes the output of the preamplifier
to reach the threshold VjA is defined as the preamplifier response time ti. Holding
the transconductance Gm and the load capacitance Ci constant, Figure 4-4(a) shows
a plot of the ramp response for increasing values of output resistance demonstrating
that the preamplifier with the highest output resistance has the fastest ramp response.
Figure 4-5(a) is a graph of preamplifier response time (ti) versus preamplifier

output resistance Ro for constant Gm and C2 . Since it is not possible to solve (4.1)
explicitly for the response time ti in the general case, consider the limiting behavior
vo(ti) = f• Mti Ideal integrator (ti < ro) (4.2a)
GmRoMt, Steady-state (ti > To). (4.2b)
To find the response time for the limiting cases, set the output voltage equal to the
threshold voltage VM!and solve for the response time ti. For the steady-state case
when Ro is small (4.2b), the response time is inversely proportional to Ro
tss= MGm Ro (43)
\ V11m) Io
As the output resistance approaches infinity Ro -- oo, the preamplifier becomes an
ideal integrator, and the time to reach the threshold approaches its minimum value
and becomes independent of Ro
tiint 2V 2 (4.4)
Using the above relationships, it can be shown that the point at which these two
asymptotes intersect is where To = ti,int/2. This point represents a point of diminish-
ing returns for increasing output resistance and is noted as Ro,dim in Figure 4-5(a).
Intuitively, a band-limiting stage should be lower noise than a broadband stage,

but as was shown in Chapter 3, care must be taken in applying knowledge of small-
signal amplifier noise behavior to systems that do not necessarily reach steady-state.
From Example 3.5, the input referred noise of a transconductance amplifier was shown
to be proportional to the noise bandwidth (3.73), which is a function of the pream-
plifier response time ti. The key results from that discussion are the input referred
noise voltage
v-(ti) = 4kTR, NBW (4.5)
and the noise bandwidth
1 t-
NBW(t,) = I coth t () (4.6)
4-r 2-ro)
2(
2
where the noise resistance of the preamplifier Rn = Gn/G . As shown in Fig-
ure 4-4(b). for a constant Gm and C1 , the preamplifier noise bandwidth decreases
as the output resistance is increased as expected. However, at some point the pream-
plifier begins to behave like an integrator, and the noise bandwidth does not decrease
below that defined by the random walk noise
1
NBW > < To.
«ti (4.7)
- 2ti,int
v (t)
VM
-ing Ro
t i,int t i2 t
t i1
Sn(f) Increasing Ro
4kTR n M
NB'Ni nt
NBW2
4
NBWj
NBW
h.._
1 1 1
2t i,int 4 2
4,r1
(b)
Figure 4-4: Holding Gm and CL constant, Ro is swept, the ramp response to a given
threshold VnA is faster for high Ro and the total mean-square noise is lower for high
Ro (a) Ramp response. (b) Noise bandwidth.
1
1og tiI A L
ti,int -
F
Ro,dim log Ro
• + LIIP•II
log NBW L
1
2 ti,int
Ro,dim log Ro
(b)
Figure 4-5: Holding Gm and Ci constant, Ro is swept. (a) Ramp response: time to
a given threshold VM is faster for larger Ro. (b) Noise bandwidth: reduces for larger
Ro
The graph in Figure 4-5(b) also shows that the noise bandwidth decreases inversely
proportional to the preamplifier output resistance
1
NBW = 4t > To. (4.8)
4RoCi
As the preamplifier output resistance approaches infinity, the noise bandwidth be-
comes independent of the output resistance
NBW = (4.9)
2ti,int
and the point at which these two asymptotes intersect is when To = ti,int/2. There-
fore, the noise also has a point of diminishing return that is the same as for speed
considerations.
Noise from the clamped state of the circuit does results in a kT/Ci reset noise
initial condition on the preamplifier load capacitor Ci, but the clamp noise is at the
output of the preamplifier. Therefore, its contribution to the input referred noise is
small if the preamplifier has a relatively large noise gain or has time for the initial
condition to decay to zero. The noise contribution from the clamp stage of the
preamplifier is addressed in the CBSC gain stage noise analysis in Chapter 6.
4.2.3 Preamplifier Design
The goal in this section is to derive a set of approximate design equations for the
preamplifier. Given a noise requirement vR, a speed requirement f, = 1/Ts, and some
information about the linearity requirements of the system, determine the required
power consumption Gm = f(ID), the required capacitance Ci and the required out-
put resistance Ro. Again, only thermal noise is addressed. First, a general set of
design equations are presented. Then, three special cases are addressed. The two
limiting cases of a wide bandwidth preamplifier and an ideal integrator preamplifier
are considered, and the point of diminishing return is discussed.
Analysis Equations
Before deriving the design relationships, the relevant analysis equations for the pream-
plifier are summarized. In the following discussion, the preamplifier response time tj
is assumed, to dominate the total comparator delay. The speed of the system places
some constraint on amount of time that the preamplifier can spend integrating, which
is captured in the following relation
mti = T (4.10)
2
where m is the number of ti's that can fit into T,/2. The linearity constraint deter-
mines the amount of time allowed for the final preamplifier response time [43]. The
number of response times m is analogous to the number of time constants required
for settling in an op-amp based system (nTo = T,/2). The equation that determines
the response time is
V = MAoti - T(1- ei/-ro)]. (4.11)
As discussed in Chapter 2, ramp rate variation results in an overshoot that is a func-
tion of the input voltage. This signal dependent overshoot introduces non-linearity in
the sampled output voltage of the CBSC stage. For a given ramp rate variation over
the full-scale output range, the linearity requirement for the stage places a constraint
on the allowable overshoot at the output V,,, which when referred to the input of the
comparator is
Vo= Vo•, = Mt . (4.12)
The input referred noise of the comparator can then be written as
v2 = coth (4.13)
" Gm Cz Ao 2T,
where terms from the noise bandwidth and noise resistance have been rearranged to
obtain a result that is proportional to kT/Ci. Solving (4.11) for Ao, the input referred
noise can be expressed as
v7 = G, T VM 1-- 1--e - t / ro coth t (4.14)

SGm Ci VIVI
) tj 2-)
Equations (4.10), (4.11), (4.12) and (4.14) complete the set of analysis equations for
the preamplifier.
Design Equations
Given the linearity constraints (m, Vo,,), the threshold voltage VM of the threshold
comparator following the preamplifier, and the topology dependent Gn/Gm ratio, the
input referred noise of the comparator is only a function of the preamplifier load
capacitance Ci and the preamplifier response time ti relative to the preamplifier time
constant x = ti/To. Solving (4.14) for Ci
Ci = 1(n) - e-x) coth ) (4.15)
sets the required preamplifier load capacitance. The speed of the preamplifier can
then be related to Gm/Ci
= (2mrs) 1-e1 x )
(4.16)
where (4.11), (4.10) and the output resistance for ti = x-ro
ti 1
Ro =t - 1 (4.17)
xCi x(2mfs)Ci
have been combined. The speed requirement combined with the value of Ci calculated
above for noise determines the required transconductance
Gm = (2mf,) G 2 x coth 2] (4.18)
100
Ci
max(Ci)
1 -
0.8
0.6
0.4
0.2
0
I I 'I
IU lU IU IU IU "'VY
Figure 4-6: Relative preamplifier band-limiting capacitance Ci versus response time

relative to preamplifier time constant x = ti/To for a given noise and speed require-
ment. Because Ci is relatively constant, the relative amount of response time is
approximately only a function of output resistance Ro (x N 1/Ro).
The preamplifier power can be found from the Gm/ID relationship for the input
devices of the preamplifier.
The general design equations above depend on the amount of time it takes the
preamplifier to reach the threshold VM relative to the preamplifier time constant.
This relative amount of response time defined above as
ti 1
x = -- 1 (4.19)
To (2mf,)RoCi
where the constant speed requirement (4.10) and To = RoCi have been substituted.
The relative response time is a function of both Ro and Ci. Figure 4-6 shows a plot
of the relative magnitude of Ci versus x for a constant noise, speed, and linearity
requirements. The required capacitance is essentially independent of whether the
preamplifier has a wide bandwidth or is an ideal integrator. The reason for the
101
Il
i10
Gm/Ci
10- (Gm/Ci)
int
1-
D I#e
no,dim Vuyn o
Figure 4-7: Relative preamplifier speed Gm/Ci and transconductance Gm versus out-
put resistance Ro. Transconductance approaches the ideal integrator result versus Ro
more quickly than speed.
minimum in the required capacitance near ti = 2-T can be understood as follows: for
a constant Gm and Ci, Figure 4-5 shows that the noise bandwidth improves more
quickly than the speed (ti). For the design equations, the noise and speed are held
constant. Therefore, the improvement in noise can be traded for lower capacitance
Ci and lower Gm to keep the noise and speed the same. The implications of the faster
improvement in noise versus Ro for the design equations can be seen in Figure 4-7
where the required relative transconductance Gm approaches its minimum value more
quickly than the relative speed Gm/Ci.
The limiting behavior versus output resistance of the design equations (4.15),
(4.16), and (4.18) is now explored.
The limiting behavior of the required capacitance for large and small output re-
102
log Gm
D .. Irr D
''o,dim mUy no
Figure 4-8: Required preamplifier transconductance versus output resistance for con-
stant noise, speed and linearity requirements. Minimum transconductance (Gm,int)
design is an ideal integrator (Ro >> Ro,dim).
sistance equivalently large and small x is
ti
Gn < To (4.20a)
Ci =
(•m ( v2- VM ti > To (4.20b)
which turn out to be identical as expected from Figure 4-6. Taking the derivative of
(4.15) with respect to x and setting equal to zero, the minimum required capacitance
versus x can be solve for numerically and is
i 0.7443 (4.21)
max (Ci)
at x e 2.209. Therefore, the minimum capacitance point is near ti = 2T , the

•
significance of which is explained below.
103
Assuming the preamplifier is an ideal integrator, the speed of the preamplifier is
Gm = 2(2mVfs) V ti o (4.22a)
Ci Vovx
which is independent of the output resistance (Figure 4-7). For the case of a wide-
bandwidth preamplifier, the required speed is
C -
Gm _
0o
1 (VM ) ti T-o 4.22b)
(4.22b)
which is inversely proportional to Ro. The point at which these two limiting cases
intersect is ti = 2To. The output resistance at this point is
1
Ro,dim =4m (4.23)
4mfsCi,int
where Ci,int is the capacitance required for an integrator (4.20a). The point where ti =
2To represents a point of diminishing return. For output resistances below Ro,dim, an
increase in Ro yields a proportional improvement in speed, but the speed approaches

a minimum for output resistance greater than Ro,dim.
The point of diminishing return also carries over into the required transconduc-
tance for a given noise and speed requirement. The limiting behavior for the transcon-
ductance (4.18) is
2 (2mfs•)( ) (• ti <To (4.24a)
R= (VM
V ti > 7o (4.24b)
where the transconductance approaches its minimum value
s) nn
Gm,int = 2 (2mefs) (b ( (4.25)
when the preamplifier becomes an ideal integrator and is inversely proportional to Ro
104
for a wide bandwidth preamplifier (Figure 4-8). The intersection of these two limiting
equations is the same Ro,dim as above which occurs when ti = 2T,.
Because t, = 27, represents the point of diminishing return for increasing Ro, it
is useful to quantify how much additional transconductance savings can be obtained
in the limit of infinite output resistance. Assuming ti = 2-ro and Ro = Ro,dim, the
required transconductance from (4.18) with x = 2 is
Gm,dim = Gm,int coth (1) . 1.313 Gm,int (4.26)
where Gm,i'nt is defined in (4.25). Therefore, the additional transconductance savings

from increasing Ro beyond Ro,dim is less than 25 %.
The final conclusion from this discussion is that it is not efficient to force the use
of a wide-bandwidth preamplifier that has time to settle to many time constants. It
should be noted that the preamplifier design procedure presented does not consider
the impact of other noise sources in the CBSC charge transfer. The role of the
preamplifier noise in the CBSC gain stage is addressed in Chapter 6.
4.2.4 Threshold Detection
The actual threshold detection is also an important part of the overall threshold
comparator design. Ultimately, small differential inputs must generate rail-to-rail or
near rail-to-rail outputs in a short amount of time. If care is not used in the design,
the threshold detection circuit can consume more power than the preamplifier. In
theory, the only required power consumption for threshold detection is the CV 2 f
power to charge and discharge the node capacitances. Comments are made on possible
threshold comparator implementations. The actual threshold comparator used in the
prototype is described in Chapter 5. Finally, differences in the requirements of a
threshold comparator for CBSC are enumerated pointing output potential ideas to
explore in future CBSC comparator designs.
105
V0
Figure 4-9: Cascade of three amplifier stages.
Cascaded Amplifiers
The simplest implementation of a threshold comparator is to use an open-loop ampli-

fier with high gain and a wide bandwidth [40] [44] [41]. This was the model assumed
when the argument was made to use a band-limiting preamplifier in front of the
threshold comparator. Again, assuming that the threshold comparator is reset be-
tween decisions, what is actually important for a fast response is not the actual band-
width, but the unity gain frequency Gm/CL [42]. The argument for a band-limiting
preamplifier also holds for threshold comparator stages.
An optimum design strategy has been considered for preamplifiers in clocked com-
parators [45] that minimizes the delay of a cascade of N identical, ideal band-limiting
amplifiers for a step input. It is assumed that the transconductance amplifiers all
start from a state such that they immediately respond to changes in their inputs, and
the transconductance amplifiers have no slew-rate limitations. Given the Gm/CL of
the amplifiers, the design specifies the optimum number of stages to minimize the
delay for a required gain, where the gain is the ratio of the required output voltage
to the step input size. It is possible to duplicate this analysis for step ramp inputs.
The output voltage response for a step ramp input VID(t) = Mtu (t) is
vo(t) = (N +1)! (MTn) -(t (4.27)
where M is the input ramp rate, -71 = CL/Gm is the unity gain time constant for the
amplifier, and N is the number of stages. The response time ti it takes the cascade
106
Z
D4
1Z - --- ·----
, - --- ·---
, - ------- , - ------~
10
I . . ...... I . . ...... I . . ...... I . .......

10" 101 102 10 104
A (V/V)
(b)
Figure 4-10: Optimum cascade of amplifiers. (a) Optimum number of stages Nop
versus the required gain A for minimum response time ti. Approximation that the
gain is a linear function of the natural logarithm of the required gain [45]. (b) Relative
delay (ti/T1) versus required gain A assuming the optimum number of stages Nop is
used.
107
I-
1:
Figure 4-11: Relative delay versus number of stages for a given gain requirement A.
of amplifiers to reach the output threshold VM is
N+1
ti = 71 A(N + 1)!] (4.28)
where A = Vn/(MTl) is required gain. The optimum number of stages versus required
gain is plotted in Figure 4-10(a) along with a rough approximation for the optimum
number of stages [45]
Nop 1.1 In (A) - 0.21. (4.29)
Figure 4-10(b) shows a plot of the relative response time ti/T1 versus the required
gain A assuming the optimum number of stages Nop is used.
However, the suggested optimum number of stages is rather large and has a broad
minimum as shown in Figure 4-11. Only a small penalty in terms of delay is payed for
significantly reducing the number of stages used and the amount the power consump-
108
)
CL
M.
Figure 4-12: Current mirror op-amp as a comparator.
tion. For example, in Figure 4-11, the optimum number of stages is approximately 8,
and the relative delay is 10. If the number of stages is halved to 4, the relative delay
is only increased to roughly 13, but the power consumption is halved.
While a cascade of differential amplifiers can be used to generate output decisions

with several hundred millivolts of voltage swing, it is not amenable to the generation
of rail-to-rail signals needed to control CMOS logic and sampling switches.
Current Mirror Op-amp
A simple single stage implementation of a threshold comparator is the current mirror

op-amp [4011 [41] shown in Figure 4-12. The cross-coupled transistors M3b and M4b
serve two important purposes. First, they speed up the completion of the decision at
the output of the differential amplifier. If they are not present, the transient operation
is slow because transistors M3a or M4a enter weak inversion and do not shut off M5
or AM/6 quickly. The second purpose is that the cross coupled devices can be used to
add a small amount of hysteresis to the comparator.
Two important design issues exist for this comparator topology. The first is the
trade-off between output slew rate and static power dissipation and the second is the
109
VIN VlN
VREF
Figure 4-13: Bazes comparator based on a self-biased differential amplifier.
asymmetry in the design.
Because the current mirror op-amp essentially just steers the tail current Iss to
charge or discharge the load capacitance, its output slew rate trades off linearly with
the amount of static power dissipation. For example, the current required to charge
5 fF from 0 to 1.8 V with a 100 ps rise time is 90 1tA. The situation is problematic
since the jitter in the output decision is a function of the output slew rate.
The other problem is the asymmetry of the amplifier and the slow transient in
shutting off transistor M7 . Because the pull-up and pull-down paths are different, the
response of the amplifier is different depending on the direction of the decision. Pull-
down transitions are fast because the cross-coupled device turns off M 6 quickly and
allows transistor Ms to discharge CL unopposed. However, for the pull-up transition,
the transistor M6 turns on quickly, but it has to supply the current being sunk by
M s during the slow turn off of transistor M7 .
110
VIN
C
CL
Figure 4-14: Inverter with split NMOS and PMOS drive. A source follower is used
as a DC level shifter to drive the NMOS device.
Bazes Comparator
An interesting idea that can break the link between the static power consumed to
the output slew rate is the self-biased CMOS differential amplifier [46] shown in
Figure 4-13. This differential amplifier has a bias current that behaves similar to an
inverter. For large differential inputs, the amplifier draws little or no static current,
and draws large amounts of current when the differential input is near zero. This
situation is the exact opposite of a Class AB differential amplifier that has a larger
bias current for large differential inputs to address slew rate limitations in op-amp
settling.
The comparator shown is not fully differential because it has a singled-ended out-
put. A fully-differential implementation has been proposed [47]. These comparators
require a common-mode input voltage near VDD/ 2 , but they are not suited to be a
single stage comparator for CBSC because of the large current draw for a zero differ-
ential input. This comparator design could work well for later stages to turn a low
swing differential signal into a rail-to-rail signal, but the output of the differential
preamplifiers would require a common-mode level shift.
111
Inverter-Based Level Converter
From the discussion of the previous comparator designs, it is clear that a circuit with a
high slew rate but low static power consumption is required. An inverter meets these
requirements, but requires a near rail-to-rail input that is centered around VDD/2.
Assuming at least one stage of differential amplification with an output voltage that
swings from the positive rail down to about mid-rail, the single-ended circuit shown
in Figure 4-14 can convert the signal into to a rail-to-rail signal. Because the circuit is
based on an inverter, it has a large dynamic current available for generating fast edge
rates, but it only draws static power in the source follower. The input capacitance
of the source follower is relatively small, approximately Cgd of M1. The static bias
current of the follower can be relatively small because it only drives a minimum sized
NMOS device and its internal parasitics.
Although this design has a fairly good dynamic to static power consumption ratio,
it still consumes static power. In addition, the minimum size inverter driven with a
half VDD drive limits the output slew rate to some extent. Finally, the minimum sized
inverter can not drive very large capacitive loads, and buffering the logic output with
a series of inverters adds to the total comparator delay.
Adaptively Biased Differential Amplifier
The final threshold comparator circuit idea to be discussed is to apply the idea of a
larger current for zero differential input to an adaptively biased differential amplifier.
A simplified schematic is shown in Figure 4-15. The tail current is the product
of the current in each leg of the differential amplifier plus a small static current
(Iss = II * 12+ 1o). This circuit is a simple extension of the more common Class AB
like adaptive bias where Iss = I1 - 12+ Io [48]. One possible method of obtaining the
product of the currents I, and 12 is to use translinear circuits techniques [49]. The
challenges are getting a large ratio between 1112 and 1o, and implementing a fast and
efficient multiplier for 112.
112
12*
12+ 10
Vin = V
I I IVl
,ISS
0So
VID
Figure 4-15: Adaptively biased differential amplifier. (a) Simplified schematic.

(b) Required bias current variation. When vID = 0, I1 = 12.
113
Threshold Detection for CBSC
In comparator-based switched-capacitor circuits, the threshold detection comparator

does not need to meet all the requirements of a traditional threshold detection com-
parator. Removal of these constraints should allow for more design flexibility and
improved efficiency. Three key differences in CBSC systems are that the direction of
each decision is known, each decision has different speed and accuracy requirements,
and the comparator can be reset or reconfigured between decisions.
First, because the direction of each decision is known, the design can be optimized
for one direction, and an asymmetric circuit could be used. For example, a circuit with
asymmetric positive feedback that has a weak pull-up device that must be overcome
but enables a strong pull-down device that never has to be overcome by the weak
pull-up is possible.
Second, because each decision has different speed and accuracy requirements, it
is possible to either reconfigure the comparator between stages to vary speed and
accuracy or use different comparators for each decision. For example, one simple
modification would be to change the preamplifier load capacitance C, between the
coarse and fine charge transfer phase decision. A small Ci during the coarse phase
allows for a fast but noisy decision, and a large C, during the fine phase allows for a
slower but lower noise decision.
Finally, a general purpose comparator must be able to make decisions in either

direction and be able to recover quickly after making a decision, but because the
comparator can be reset or reconfigured between decisions in CBSC, the comparator
does not need to be designed for fast recovery. The state of the comparator can either
be reset with switches between decisions or a different comparator can be used.
The proof of concept pipeline ADC did not take advantage of the unique require-
ments of a CBSC virtual ground threshold detection comparator. Future work should
explore the possibility of exploiting these differences.
114
4.3 Summary
The specifications of threshold detection comparators have been described, and their
operation contrasted with that of the more common clocked comparator. The non-
stationary noise analysis techniques from Chapter 3 were used as the basis for a
discussion on low noise threshold comparator design. It was found that it is advanta-
geous to band-limit the preamplifier to improve both its speed and noise performance
at a given power consumption. A set of simplified design equations for the preampli-
fier were derived. The capacitance required for a given noise performance requirement
was found to be relatively independent of whether the preamplifier was severely band-
limited or not. The difference is that the band-limited design can be made to consume
less power while operating at the same speed. Finally, the issues related to the design
of the actual threshold comparator were briefly discussion concluding with a summary
of the potential design flexibility for virtual ground threshold detection comparators
in comparator-based switched-capacitor circuits.
115
116
Chapter 5
CBSC Prototype Pipeline ADC
5.1 Overview
Although the CBSC technique is a general approach that can be applied to most
switched-capacitor circuits, for the demonstration of the concept, a prototype pipeline
ADC was constructed [50] [15]. A brief description of the overall pipeline ADC
is given. The details of the bit-decision comparator and the threshold comparator
used in the prototype are emphasized. The experimental results from the prototype
converter are presented along with comments on testing procedures and equipment.
5.2 1.5-bit/stage CBSC Pipelined ADC

A schematic of the first two stages of the prototype pipeline ADC is shown in Fig-
ure 5-1. To simplify the design of the prototype, a single-ended circuit design was
used as shown. A fully-differential design should be possible, but it would require
the design of a common-mode feedback circuit to equalize the differential pull-up and
pull-down currents. The pipeline was implemented as a cascade of identical stages
with sampling capacitors C, = Ca1 + Clb = 500 fF. No threshold comparator sharing
between adjacent stages or comparator duty-cycling for lower power consumption was
performed. The system clock directly controls the sampling and bit decision timing of
117
Stage 0 Stage 1
Figure 5-1: First two stages of Pipeline ADC. Note that the first stage sampling and
bit-decision clocking are controlled by the system clock, but for the second and subse-
quent stages, the sampling and bit-decision clocking are controlled by the comparator
of the previous stage.
118
M6
*12
VB1 02 V5
VE
(b)
Figure 5-2: Coarse and fine phase current sources. Bias voltage generation not shown.
(a) Coarse phase current source I1 = 70 ýtA. (b) Fine phase current source 12 = 3 iiA.
the first stage of the pipeline, but the previous stage comparator decision controls the
sampling and bit decision timing for the second and subsequent stages. However, the
overall pipeline process is not self-timed. The operation of each stage of the pipeline
operates under the control of the system clock. The circuits used to implement the
coarse and fine charging current sources, the bit-decision comparators, and the virtual
ground threshold detection comparator are described below.
5.2.1 Charging Current Sources
To allow for the majority of the coarse phase overshoot to be canceled as discussed in
Chapter 2, a constant ramp rate for the coarse charge transfer phase is required across
the full-scale output range. One straightforward method of reducing the ramp rate
variation is to use a cascoded current source. Therefore, the coarse phase charging
current source I1 was implemented as a cascoded PMOS current source (M 1 , NI2 )
as shown in Figure 5-2(a), where the bias voltage on the cascode device is used to
turned on (AM
3 ) and off (M 4 ) the current source. For lower supply voltage operation,
alternative methods of keeping the ramp rate constant are required.
Because the fine phase current is more than an order of magnitude lower than the
119
coarse phase charging current (70 ýxA/3 LA), the output resistance of a single device
of the same length should also be an order of magnitude larger. According to the
simulation models used at design time, the output resistance of a single device would
be adequate to keep the fine phase overshoot variation small enough for 10 b linearity.
Therefore, the fine phase current source 12 was implemented as a single transistor
current source (M 5 ) as shown in Figure 5-2(b), where a series NMOS switched (M 6 )
was used to turned on and off the current source. It was later realized that the series
switch (M 6 ) behaves like a cascode device at the high end of the full-scale range. The
large increase in output resistance at the high end of the output range results in a
signal dependent overshoot and ultimately INL in the ADC transfer characteristic.
5.2.2 Bit Decision Comparators
The two bit-decision comparators shown in Figure 5-1 are traditional latch-based
clocked comparators. At the falling edge of 01 or S, these comparators determine
if their inputs are greater than or less than the two reference voltages VRp and VRN
according to the 1.5 b/stage algorithm [51] [52]. The core of the bit-decision com-
parator is the latch circuit shown in Figure 5-3(b). The latch used in Figure 5-3(b)
is a slight modification of the well-known cross-coupled inverter latch [53] shown in
Figure 5-3(a). The reason for splitting the transistor MR into two separate devices
with their drains not connected is to minimize signal dependent current required at
the input of the latch during the charge transfer phase.
Consider the traditional latch in Figure 5-3(a), the reference voltage VREF is some-
where near the middle of the supply range, and the input yIN is always pulled to
Vss = 0 during preset. At the beginning of the charge transfer phase, the transis-
tors M 2 and M3 are off and transistors MA4 and M 1 are on. Therefore, the drain
of MN starts at Vss and the drain of Mp (node X) starts at VREF. As the input
voltage ramps up during the charge transfer phase, transistor M1 turns off when
VIN Ž VREF - VTN, and transistor M 4 turns off when vIN > VREF - VTP. However,
when vIN > VREF + VTP, transistor M 3 turns on with node A acting as the source
120
V
(a) (b)
01
OL2
02S ....
A Latch Data Ready
Q e Bit Decision Valid
(c)
Figure 5-3: Bit decision comparators. (a) Typical cross-coupled inverter based clocked
latch. (b) Cross-coupled inverter based clock latch used in prototype. Addresses the
problem of having to charge node X at the drain of MR. (c) Latch timing diagram.
121
A Q
02S
A
0
Figure 5-4: Bit decision comparator data valid and storage registers.
terminal because the gate of M3 is at VREF and the input voltage pulls node A a
threshold voltage above VREF. When M 3 turns on, more current is needed from the
input to charge the capacitance at node X from VREF to VREF + VTP . This large
change in the input current causes ramp variation at the output of the CBSC gain
stage, which can cause non-linearity in the overshoot.
The modified latch in Figure 5-3(b) eliminates this problem because the drain of
transistor MPA is discharged to VREF + VTp during preset, which is exactly the voltage
at where transistor M 3 turns on. However, the extra drain and source capacitance of
transistors MPA and M 3 still become visible to the input when vIN Ž> VREF + VTP-
If less ramp variation is needed, alternative comparator designs could be used.

An additional consideration for the design of the latch is the trade-off between
input referred offset and speed. The matching between the two inverters determines
the input referred offset of the latch. The offset requirement for a pipeline converter
using the 1.5 b/stage algorithm is greatly reduced [51] [52], but longer devices can be
used to improve the input referred offset if required. However, the speed of the latch
is reduced and the input capacitance is increased.
The additional supporting circuitry for the bit-decision comparators is shown in
Figure 5-4. A fixed set of inverter delays are used to self-time the enable signal 02S
on the output decision circuit. The rest of the logic detects when the comparator
has made a valid decision (Y) and stores the bit decisions in static D-type flip-flops
(DFF) [54].
122
5.2.3 Virtual Ground Threshold Detection Comparator
In contrast to the bit-decision comparators that make a magnitude decision at a

specific instant in time, the virtual ground threshold detection comparator must de-
termine the time at which the node vx equals VCM. The schematic of the threshold
detection comparator used in the prototype is shown in Figure 5-5. Following the dis-
cussion in Chapter 4, the threshold comparator can be thought of as a band-limiting
preamplifier stage followed by a broad-band amplifier cascade plus level shifter.
The band-limiting preamplifier was implemented as a differential amplifier with
active loads. The output is clamped with back-to-back diode connected NMOS tran-
sistors. The clamp devices provide an effective reset state for the output between
decisions and keeps all devices in their active regions to minimize recovery time. The
details of the preamplifier with a continuous-time common-mode feedback circuit is
shown in Figure 5-6 [55]. The tail current for the preamplifier is nominally 16 kA.
To maximize the unity gain frequency of the preamplifier, the input devices use short
gate lengths WV
1/L 1 = 3.2 Rm/0.26 inm. From simulations including parasitic extrac-
tion, the preamplifier has a transconductance (Gm) of 166 RS, an output resistance
of 130 kQ, and an equivalent load capacitance (Ci) of 25 fF.
The two low-swing gain stages are differential amplifiers with resistive loads where
the resistors were implemented using triode PMOS devices with their gates tied to
Vss. The nonlinearity introduced from using triode devices as loads is unimportant
for comparator amplifier stages. The single-ended output swing of the low-swing gain
stages is roughly 400 mV, and it is DC level shifted down with a diode connected
PMOS device. The DC level shift allows the final gain stage, which also has triode
PMOS loads, to have a larger swing while still keeping its differential input devices
in saturation. Each half of the final gain stage swings about half the supply voltage
(900 mV) and is converted to a rail-to-rail signal with the inverter based level converter
shown in Figure 5-5. One advantage of the level converter shown is that because it is
based on an inverter, it has a peak transition current that is significantly larger than
the static current IB4 = 5 pA in the source follower as discussed in Chapter 4. This
123
Band-limiting Amplifier Low Swing Gain Stages
I I
VI
VM2
Vp2
Gain Stage Level Conv erter Buffer

I I
-I-I-
Q
VM2
I , K _ (
Vp2
V,3-1 IB3 V ,B4B4 VB4 IB4
Figure 5-5: Schematic of prototype threshold-detection comparator with band-

limiting preamplifier. The total parasitic capacitance at the output of the band-
limiting amplifier determines the bandwidth. Resistors shown in the schematic are
implemented as PMOS devices with grounded gates operating in the triode region.
Each comparator has a power consumption of roughly 200 ýiW.
CMFB Amplifier Preamplifier Threshold Comparator

I I I I I " "
Figure 5-6: More detailed schematic of comparator preamplifier for prototype showing
the common-mode feedback circuit.
124
Bias Current Value
IM14 + IM15 16 LA
IM7 + IM8 16 pLA
IB2 13 LA
IB3 24 LA
IB4 5 LA
Total Static Bias 92 RA
Table 5.1: Threshold-detection comparator static bias currents.
State
1- Logic
2-
V
To Sampling
Switch
Figure 5-7: Current source and sampling logic and CBSC state machine.
behavior allows for fast rise/fall times resulting in lower jitter sensitivity in the later
stages of the comparator. Table 5.1 gives the bias currents for the different stages.
5.2.4 CBSC State Machine
A finite state machine is used to control the coarse and fine charge transfer phase
operation as shown in Figure 5-7. The state machine consists of two fully static
DFFs [54] and some combinational state logic to generate the control signals El and
E 2 from the current state and the system clock.
During the sampling and preset phases, the clock inputs to the DFFs are discon-
nected from the comparator output and held low. During the preset phase, the DFFs
are reset, which sets their Q outputs high. Therefore, the signal S 2 is high and the
125
10.4mm
2.9mm
2
Figure 5-8: Die photograph. 0.18 ýtm CMOS process. Pipeline Area: 1.2 mm
sampling switch is closed during preset.

During the charge transfer phases El and E2, the output of the comparator is
connected to the clock input of the DFFs. When the comparator input makes its first
decision for the coarse charge transfer phase, the signal Si falls low. The state logic
then shuts off the coarse phase charging current II and turns on the fine phase current
'2. Upon the fine phase threshold crossing decision, the signal S2 falls low and opens
the sampling switch. The signal E 2 falls low after the state logic propagation delay.
5.2.5 Prototype Test Chip
A die micrograph of the prototype pipeline ADC is shown in Figure 5-8. The pro-
totype was fabricated in a 0.18 ýtm CMOS process. All the bit decision for the 12
pipeline stages are sent off chip for post-processing. For the ADC performance data in
this chapter, the output was truncated to 10 bits, but 12 bits of output were used for
the noise characterization of the pipeline in order to reduce the effect of quantization
126
HSC-ADC
8656B
AP1
Figure 5-9: Simplified diagram of the prototype test setup.
noise. The prototype had an on-chip non-overlapping clock generator to generate all
the required timing edges from a single input reference clock. The relative timing
of the clock edges was controllable through a 32 b serial configuration register. All
comparator bias currents and the coarse and fine phase currents were applied exter-
nally for maximum testing flexibility. The reference voltages for the ADC were also
generated off chip [43].
5.3 Experimental Results
Measured results of the prototype pipeline ADC are presented. Testing results are
reported in accordance with the IEEE standards on ADC test methods [56].
127
A simplified diagram of the test setup is shown in Figure 5-9. The Agilent 8644B
signal generator was used to supply the reference clock for the prototype. The out-
put data from the prototype converter could be acquired using either the HSC-ADC-
EVALA-DC data acquisition board from ADI with 256 kS deep FIFOs (IDT-72V2113)
or the TLA715 logic analyzer. The data acquisition board has a USB interface and
comes with a driver and software to control the board. Labview was used to control
a National Instruments PCI-DIO-32HS data acquisition board for programming the
configuration register in the prototype to set timing options for the clock edges gen-
erated on chip. The DIO-32HS connects to the test board with a 68-pin cable and
connector on the PCB.
The INL and DNL performance of the prototype converter operating at approxi-
mately a 7.9 MHz sampling rate are shown in Figure 5-10. The INL and DNL measure-
ments were made using the sine wave histogram test [57] where the Audio Precision
API was used to generate the low frequency sine wave input. It is important to select
the input and sampling frequencies such that exactly an integer number of periods are
recorded and samples do not repeat periodically during the data record. This special
selection of frequencies is often referred to as coherent sampling. A useful adaptation
of this concept to testing with finite precision signal sources has been suggested in
Maxim Application Note 3190 [58].
The FFT testing results for a single tone input are given in Figure 5-11 for an input
frequency near fs/2 and an input amplitude of -1 dBFS. The output of a HP8656B
signal generator was low-pass filtered to provide a spectrally pure input sine wave
for FFT testing. The filters used for testing were a series of low-pass filters from
Mini-Circuits and TTE. All harmonic distortion components of the input sine wave
should be at least 20dB below the magnitude of the distortion components under
investigation [56]. Again, the the input frequency and the sampling frequency should
be selected according to coherent sampling requirements. For FFT testing, coherent
sampling results in all signal and harmonic tones falling in their own FFT bins. The
128
.1
0.5
-r -- --
U)
-j
..
...
..... Jbl...
... h .....
........
ijLI
0 --------------------------
i
i
.---
, ir
------------
,..........................
-----------
---IIA
Aj..A.A
..........................
. i
-----
I
---------
i-
I ..........................
i ..........................
iF i i
z -0.5
0
1
- ') 200 400 600 800 1000
CODE
(a)
t•
0co 1
. .........
... . . . ... .. ..... ..........
..... . . ... ....... ......... ........
............ ---------------------
-----------
.J
-J
.z
2
0 --
-1 ...
...
...
..
...
...
..
...
....
--v
...
..
...
....
...
----
-------------
------------
...
..
----
-
...
---
...
..
--
---
---
---
---
---
--
...............
.....
.....
........
...
..............
_-3
--C) 200 400 600 800 1000
CODE
Figure 5-10: ADC 10b INL and DNL for a 7.9 MHz sampling frequency. (a) DNL.
(b)INL.
129
FFT Test: f = 7.9MHz, fin = 3.8MHz, Ain= -1.0dBFS
UJL
IP
00
(MHz)
Figure 5-11: Output FFT for fs = 7.9MHz sampling rate and a -1dBFS input at
fin = 3.8 MHz.
spectral plot shown is the average square magnitude of 60 FFTs of 214 samples'. The
spectral averaging makes the higher-order low level distortion products visible in the
FFT spectrum shown in Figure 5-11.
Figure 5-12 shows the signal-to-noise and distortion ratio (SNDR) and spurious
free dynamic range (SFDR) versus input frequency fin for the prototype. The SNDR
performance is essentially constant up to the Nyquist rate (fs/2). This result demon-
strates that input sampling circuit was not limiting the linearity performance of the
1
Note: Equation (87) in [56] is incorrect. It should be [59]
K
Xav•nm[fm] = Kj X[f,] 2.• (5.1)
k=1
FFT averaging and spectral estimation are discussed in more detail in Chapter 7.
130
1.5 2 2.5 3 3.5 4
fin (MHz)
Figure 5-12: SNDR and SFDR versus input frequency.
prototype.
Recall that the SFDR is defined as the ratio between the largest harmonic com-
ponent and the input tone. From Figure 5-12, the SFDR appears to improve with
input frequency. However, variation in the SFDR performance versus input frequency
is reasonable because the amplitude of the dominant harmonic component can vary
versus input frequency due to the cancellation of competing effects for a single har-
monic component.
Table 5.2 gives a summary of the performance of the prototype pipeline ADC.
Operating at a 7.9 MHz sampling frequency, the converter achieves 8.6 effective bits
of accuracy. and consumes 2.5 mW of power resulting in a 0.8 pJ/b figure of merit [60].
The 2.5 mW power consumption does not include the power consumption from the
clock generation circuits or the pad drivers for the output bits. In addition, the time-
131
fs 7.9 MHz
VFS 1 V (single-ended)
DNL +0.33/-0.28 LSBlo
INL +1.59/-1.13 LSB 10
SFDR 62 dB
SNDR 52 dB
SNR 53 dB
ENOB 8.6 b
Power 2.5 mW
P
EN
FOM 2O B 0.8 pJ/step
2fin 2 ENOB
Table 5.2: ADC Performance Summary
alignment and 1.5 b/stage correction algorithm were also not implemented on-chip.
5.4 Summary
The circuits used in the implementation of the CBSC prototype pipeline ADC were
described. Details of the bit decision and threshold detection comparators were em-
phasized. The bit decision comparator used was a slight modification of the standard
cross-coupled inverter based latch to address the signal dependent load problem of
the original design. The threshold detection comparator used in the prototype was
described focusing on the preamplifier implementation. The basic test setup for the
prototype was described, and measured results from the prototype were presented.
The key results were summarized in Table 5.2.
132
Chapter 6
CBSC Noise Analysis
6.1 Overview
The noise analysis of a CBSC pipeline ADC stage is presented. The analysis is based
on the prototype implementation described in Chapter 5. Noise from the virtual
ground threshold detection comparator, the charging current, and the switches are
analyzed separately. The results can then be combined with the noise from the input
sampler to form a total input referred noise PSD estimate for the prototype. The
theoretical estimate is compared with measured results in Chapter 7.
6.2 Total Input Referred Noise of Pipeline ADC

For the purposes of analyzing the input referred noise of the ADC, a single pipeline
stage can be represented as a gain-of-two amplification shown in Figure 6-1 that
resolves 1.5 effective bits [51]. The input referred noise of the i-th stage of residue
calculation is Vn(i), and the noise in the residue calculation for the i-th stage does
not affect the i-th stage bit decision.
The input referred noise PSD of the ADC can be measured by examining the
output codes for a zero input signal, but the measured value also contains quantization
noise from the ADC. Because the prototype pipeline was implemented as a cascade
133
D(i)
VIN(i) v0(i)
Figure 6-1: Single 1.5b/stage model for noise analysis.
VIN . . .
Figure 6-2: Pipeline ADC model noise model.
134
of identical stages, the total input referred noise from the residue amplifiers has a
particularly simple form. Referring to Figure 6-2, the input referred noise PSD of an
N-bit ADC due to noise in the residue calculations is
Sno(f) Sn1(f Sn(N-2)(f

Sn,ADC(f) 1 + 22 2(N-2)
2
N-2
= Sno(f) -
i=O
Sn,ADC(f) = ~ - SnO(f) (6.1)
4
(6.2)
Sn,ADC (f)M
3SnO(f)
where Sno(f) is the input referred noise PSD of a single stage and the final approx-
imation in (6.2) is true for a large number of bits (N > 1) and converges to 4/3
quickly. The kT/C noise of the input sampler and the ADC quantization noise add
to the input referred noise PSD to give the total input noise PSD. In total,
Sn,tota,(f) = Ssample(f) + Sn,ADC(f ) + Sq(f) (6.3)
where Samplie(f) = kT/C,/(f,/2) is the noise PSD from the input sampler over the
Nyquist range and Sq(f) = VSB/12/(fS/2) is the ADC quantization noise PSD.
6.3 Single Pipeline Stage Input Referred Noise
The goal of this section is to derive the input referred noise PSD for a single pipeline
stage S,o(f). The interpretation of the periodic filtering model with aliasing is used to
calculate the input referred noise PSD for each of the noise sources in the gain stage.
The total input referred noise from a pipeline stage consists of contributions from
the virtual ground threshold detection comparator, the fine phase charging current
source, and the switches in the gain stage.
135
6.3.1 Periodic Filtering Model
Most of the noise sources in the CBSC charge transfer phase result in a non-stationary
noise response. For example, the fine phase charging current integrates noise onto the
capacitance network and clearly does not reach steady-state. As another example,
the response of the preamplifier for the threshold detection comparator may not
reach steady-state before reaching the output threshold voltage. The non-stationary
noise analysis presented in Chapter 3 can be used to analyze both of these cases
for a single charge transfer phase. While analyzing a single charge transfer phase
does yield insight into the noise voltage behavior versus time over the duration of
the charge transfer, ultimately, the output value is sampled and the statistics on
the series of samples are of more interest. The periodic filtering noise model from
Chapter 3 addresses the spectral analysis of the series of periodic samples allowing
for the inclusion of both thermal and flicker noise sources. The focus of the analysis
then becomes the Fourier transform of the windowed transfer function from the noise
source to the output of the gain stage which is referred to the input by the stage
gain. Because both approaches yield different insights into the performance of the
system, they are both presented. However, only results for the white noise sources
using the non-stationary noise analysis are presented under the assumption that the
preamplifier is an ideal integrator. These results are simpler and allow for an easier
comparison of the different noise contributions.
6.3.2 Threshold Detection Comparator Noise
The schematic of the ideal threshold detection comparator with a band-limiting

preamplifier is shown in Figure 6-3. As discussed in Chapter 4, the output of the
preamplifier is assumed to be clamped after each decision so that !Ci has either +VD
across it. When the voltage on the output capacitance is clamped, it does not begin
to discharge until the differential input voltage to the transconductance preamplifier
is greater than the input referred clamp voltage (IVIDI > IVDII/A). An approximate
136
Threshold
Preamplifier Comparator
I I I I
VX Q
VCK1
Figure 6-3: Ideal threshold detection comparator with band-limiting preamplifier.
linear half-circuit model for the ideal preamplifier that neglects slew rate limitations
is shown in Figure 6-4(a) where its differential input voltage is modeled as a step ramp
waveform and the noise from the transconductance device starts integrating onto the
output capacitance at time zero (Figure 6-4(b)). The noise from the preamplifier
consists of noise on the band-limiting capacitance Ci from the clamped output after
the coarse charge transfer phase and noise current integrated onto the band-limiting
capacitance during the fine phase response time ti. The noise contribution from the
threshold comparator following the preamplifier is assumed to be small when referred
to the input, which is equivalent to assuming the preamplifier has a reasonably large
noise gain.
Clamp State Noise
The noise from the clamped state is a noise initial condition on the band-limiting
capacitance (½Ci). Assuming the NMOS diode has a relatively low on-resistance
compared to the output resistances of the current source loads and input pair devices
(M-MA
4 ) in Figure 6-5, only noise from the clamp device and the current passing
through the clamp (M3 or M 4 ) feed noise to the band-limiting capacitor. The transfer
function from these two noise sources to the output is the low-pass filter at the output
of the preamplifier in the clamp state. Assuming the preamplifier reaches steady-state
137
VID +GmVID in(t) Cj ý
1 vo
Q• NI
21
Figure 6-4: Half-circuit model for band-limiting preamplifier. (a) Linear half-circuit
model. (b) Waveforms for linear half-circuit model.
CMFB Amplifier Preamplifier Threshold Comparator

I I I I Ir -
18
Figure 6-5: Comparator preamplifier for prototype.
138
during its time in the clamped state, the transfer function is
Hw,G2m
2 1
(2 G-2IR 2
1+(2fD) 0 2
e-ti/To
e-ti/(o (6.4)
2
S(I+
( (2-f) ( )2 )
where GD is the diode clamp conductance, the noise has been referred to the input of
the preamplifier using (3.70), and the exponential decay occurs during the preamplifier
response time. If the response time ti is much longer than the high impedance time
constant To, = RoCi during the response time, the clamp noise decays to zero and does
not contribute to the input referred noise. The one-sided input referred aliased noise
contribution from the clamp state can be found using the transfer function (6.4) in
aliasing summation (3.94)
Sn,clamp(f) = •IHw,ctamp(f - nfs) 2Sin,camp(f - nfs) (6.5)

n
where Sin,camp(f) is the twice the two-sided noise current PSD applied to Ci during
the clamp state.
However, because the preamplifier is assumed to reach steady-state during the

clamp state, the non-stationary noise analysis is not necessary to calculate the output
noise voltage from the clamp and current source load thermal noise sources. The noise
at the output is simply the kT/C noise at the output
v2n,clamp = 2 GD
. (6.6)
i
If the response for an ideal integrator is being calculated, the noise initial condition
from the clamp state does not decay, and the input referred noise is
=2 (GD (kT 1 (6.7)
nclamp GD Ci JAN(ti)l 2
where IAN(ti) I= Gmti/Ci (3.75) is the noise gain of an ideal integrator operating for
tiseconds before reaching the threshold at the output of the preamplifier.
139
Preamplifier Response Time Noise
During the preamplifier response time, the noise current from the transconductance
amplifier adds noise to the output voltage of the preamplifier. The general transfer
function from the output noise current of the transconductance amplifier referred to
the input is
H,
2 1 /G2m 1 - 2e-ti/_o cos (2?rfti) + e- 2ti/ ro
+(2fro)2)
+Hwresp(f) ( 1 - 2e-4t/ro + e-2ti/o (6.8)
where the noise has been referred to the preamplifier input with (3.70), and the
preamplifier response time ti is that defined in Figure 4-3. The preamplifier response
time noise simplifies into two interesting special cases for a broad-band preamplifier
and an ideal integrator preamplifier
1/G2
m ti >» 0 (6.9a)
2 = 2
jHw,resp(f) 1 (27rfo)
- sinc 2 (fti) t<i < o. (6.9b)
m
For the broad-band case, the transfer function simplifies to the expected steady-
state result which is independent of the response time ti and has a constant noise
bandwidth. For the case of an ideal integrator preamplifier, the transfer function
simplifies to a sinc function with a noise bandwidth that is inversely proportional
to the response time. These two results are identical to the cases (3.83) and (3.78)
2
described in Example 3.5. Figure 6-6 show a plot of IHw,resp(f) for three cases
where the output resistance of the preamplifier was varied. The one-sided input
referred aliased noise contribution from the preamplifier during its response time is
Sn,resp(f) = EIHw,resp(f - nfs)•2Sin,res.(f - n f) (6.10)

n
where Sin,resp(f) is twice the two-sided noise PSD applied to Ci during the preamplifier
response time.
140
2
In2)f(H(goI
1
Gm
I--.
lug I
Figure 6-6: Preamplifier response time filter IHw,resp(f) 2 for different output resis-
tances causing variation in ti relative to ,o.
The input referred noise of a transconductance amplifier with infinite output re-
sistance was derived in Example 3.5 as a special case when ti < To. From (3.77) and
(3.78)
v2n,resp = 4kTR, 1 (6.11)
2ti
where Rn =:- Gn/G2 is the usual input referred noise resistance for the preamplifier.
For easier comparison with the clamp state noise, the input referred noise can be
reformulated into a kT/C noise expression
, Gr (kT 1
n'resp Gm Ci JAN I
(6.12)
where again, the definition of the integrator noise gain (3.75) has been used.
141
Total Preamplifier Noise
The total aliased noise contribution from the preamplifier is the sum of the clamp
state and response time noise
Sn,preamp(f) = Sn,clamp(f) + Sn,resp(f ). (6.13)
To gain some insight into the relative contribution of the magnitude of these two
noise sources, consider the sum of the input referred noise voltages (6.7) and (6.12)
Vn,preamp = 2( 1 1+(Grn) (Gn

( A-~1[2
Gný) ýkTC I 1 (6.14)
Assuming the preamplifier has a relatively large noise gain
AN> G G ) (6.15)
the second term in (6.14) from the clamp noise contribution is small, and the response
time noise dominates the input referred noise of the preamplifier
2-y ,.•(Gn)(kT) 1
vpreamp 2 (6.16)
1
= 4kTR, - (6.17)
2ti
6.3.3 Charging Current Noise
The second source of noise to be considered during the charge transfer phase is the
contribution from the fine phase charging current source 12 shown in Fig. 6-7. The
noise from the charging current 12 only adds noise to the final sampled output value
after the preamplifier input threshold crossing. The noise added to the capacitor
network before this time does not effect the final value, and only changes the time
it takes to reach the preamplifier input threshold. The noise contribution from the
142
D()VRE
D(i)VREF
UL VCM
Figure 6-7: Noise contribution from fine phase charging current '2.
charging current consists of the random walk noise on the external capacitor network
during two independent time intervals. The first interval is the preamplifier response
time ti from Fig. 4-3, and the second interval is the delay time from the threshold
detection to the sampling switch opening td - ti in Fig. 4-3.
Preamplifier Filtered Noise
The random walk at the preamplifier input during the preamplifier response time
generates a jitter that is negatively correlated with the noise voltage at preamplifier
input and partially cancels the noise during this time. Referring to Figure 6-7, con-
sider a larger than average random walk deviation at the preamplifier input. This
larger than average deviation results in a larger than average preamplifier output, and
a shorter t[han average time to reach the comparator threshold voltage. Therefore,
the shorter than average comparator delay cancels the larger than average random
walk deviation.
To derive a transfer function for the noise that takes into account the correlation
between the comparator jitter and the output random walk, consider the following
procedure: analyze the circuit as two open-loop voltages referred to the input of the
gain stage. The first is the open-loop random walk voltage at the output of the gain
stage referred to the input y(t), and the second is the voltage error at the output
referred to the input z(t) that results from the jitter in the comparator decision from
143
the preamplifier filtered random walk voltage. The true input referred noise voltage
is then the difference of these two voltages
v1 2 (t = y(t) - z(t). (6.18)
The two-sided noise PSD is then a function of the PSDs of y(t) and z(t) as well as
their cross-power spectral densities
Snn,I2(f = Siy(f) - Syz(f) - Sz (f) + Szz(f) (6.19)
= IH(f) - Hz(f)12Sx(f) (6.20)
where H,(f) is the open-loop transfer function from the current source noise to the
output, Hz(f) is the open-loop transfer function from the current source to output
error due the the jitter in the comparator decision from the preamplifier filtered noise,
and Sx(f) is the two-sided noise PSD of the current source 12. The open-loop transfer
function for the random walk referred the input of the gain stage during ti is
Hy(f)= (Et C+
CE) (C + C2)
sinc(ft )e-j(27f)ti/ 2 . (6.21)
The open-loop transfer function due to the jitter in the comparator decision is more
complicated. The s-domain transfer function from the charging current I2 to the
preamplifier output referred to the input of the gain stage is
1 1 C \) A
Hz (s)= I( I)( C Ao0 (6.22)
A = (ti)I sCE C1 + 2 1+ ST,
The infinite duration impulse response is the inverse Laplace transform
hz(t) = (Aoi) ( ) () C e- t/ro) u(t)

) (1 - (6.23)
andthe
transform
Fourier of th windowed
CE +
impulse response is the desired noise1
and the Fourier transform of the windowed impulse response isthe desired noise
144
transfer function
Hz(f) = { hz(t)w(t) . (6.24)
The transfer function for the charge current noise accounting for the correlated jitter
is
IHw,i(f)12 = IHy(f) - Hz(f)1 2. (6.25)

The one-sided input referred aliased noise contribution from the charging current
during the preamplifier response time is
Sn,I2,(f) = IlHw,I2 (f - nf,)1 2 2S,,(f - nf,) (6.26)

n
To understand the properties of this transfer function, two special cases are con-
sidered, a wide-bandwidth preamplifier and an ideal integrator preamplifier. Plots
of the transfer function H,,I2 (f) are shown for three values of preamplifier output
resistance Ro in Fig. 6-8. For a wide-bandwidth preamplifier Ro = 10 kQ, the noise
at the output of the preamplifier is proportional to the noise at the input of the
preamplifier at low frequencies. For an infinite bandwidth preamplifier, they would
be proportional at all frequencies and the jitter would completely cancel the open-loop
random walk deviation and would have a correlation coefficient of cyz = -1. For a fi-
nite bandwidth, higher frequencies have a phase delay resulting in less than complete
cancellation. In the other extreme, an ideal integrating preamplifier Ro = 100 MQ
still has a correlated jitter, but it is the minimum. Using the open-loop transfer
functions, i.t can be shown that the correlation coefficient for an ideal integrator is
cy, = - y /,2. -0.866.
Using a procedure that parallels the frequency domain approach above, the white
noise voltage response including correlation can be expressed in a form similar to
(3.33)
-
v2i = S(0) ]hy(-) - h,(r) 12d (6.27)
145
^,6
1
10
f (Hz)
Figure 6-8: Charging current transfer function during preamplifier response time.
Preamplifier output swept for a constant Gm and Ci. A broad-band preamplifier,
lower output resistance, results in more noise cancellation and therefore, lower transfer
function gain.
146
where
hy(t) = u(t) (6.28)
C•()=
E C1 + C2 t
is the impulse response from the charging current noise to the output voltage referred
to the input of the gain stage and the general form of hz(t) is define in (6.23). The
expression for hz(t) simplifies to
hz(t) =( CE C1 + C2 (-ti u(t) (6.29)

for the case where the preamplifier is an ideal integrator. Substituting (6.28) and
(6.29) into (6.27) to calculate the input referred noise from the charging current
including the effects of the negatively correlated comparator jitter results in
Vn2(')i = t C2 (6.30)
The input referred noise is 1/3 of the open-loop random walk voltage at the output
referred to the input. The factor of 1/3 is a result of the partial cancellation of noise
for an ideal integrator preamplifier. For a wide bandwidth preamplifier, this factor
approaches zero.
Noise During Threshold Comparator Delay
During the second interval, the threshold comparator delay, the random walk noise
also accumulates on the external capacitor network until the output sampling switch
is opened. The noise transfer function is
,,,2 S E) Cc 1
+ 2sinc2(f c) (6.31)
where ti = td - ti is the threshold comparator delay. The one-sided input referred

aliased noise contribution from the charging current during the threshold comparator
147
delay is
Hlw,I 2 c(f - nf,) 2 2S..(f - nf,). (6.32)

Sn,,, (f) =
n
Because the preamplifier does not filter the noise added to the output during the
threshold comparator delay, the noise added during this time is not correlated with
the comparator jitter. The noise contribution referred to the input during this time
is
v2 - Cc .2 (6.33)
which is simply a random walk noise voltage.
Total Charging Current Noise
The total one-sided input referred noise PSD from the charging current noise is
Sn,!2 (f) = Sn,1 (f) + Sn,12c(f). (6.34)
The total input referred noise from the charging current is the sum of the preamplifier
filtered (6.30) and threshold comparator delay (6.33) contributions
, =2 S0)2 t [1 + 3t,. (6.35)

,12 3 C2 ti
For the case of an ideal integrator preamplifier, the noise accumulated during the
preamplifier response time dominates this input referred noise contribution if
t. > 3tc. (6.36)
However, for a general preamplifier bandwidth, it is difficult to say a priori which of

the two terms is more important.
Assuming that the preamplifier response time is much larger than the thresh-
old comparator delay (ti > t,) and the charging current source has shot noise
S,,(O) = qI2, the expression for the noise contribution from the charging current
148
D(i Rs
VCM VcM
Figure 6-9: Noise contribution from sampling and configuration switches.
can be rewritten as
v-2 = (6.37)
n12 3 CE
where V,, is the input referred overshoot of the fine charge transfer phase. Therefore,
for a constant overshoot requirement for linearity, the only way to lower the noise
contribution from the charging current noise is to increase the total capacitance used
in the sampling and feedback networks.
6.3.4 Switch Noise
During the charge transfer phase, two switches are connected in series with the load
capacitance and one in series with capacitor C 2 to the appropriate reference voltage
as shown in Fig. 6-9. The noise from these switches is white and results in two sources
of noise for the CBSC charge transfer phase. The first source is the noise present at
node vx that the preamplifier filters during its response time. The second source is
the noise present on the load capacitance at the output sampling instant. These two
voltages result from the same resistor noise, but they are uncorrelated because they
occur at different times due to the finite threshold comparator delay.
149
Preamplifier Filtered Noise
The noise present at node vx at the threshold detection point is a white noise PSD
determined by the resistance and capacitor network
SRneq (O) = 4kTRneq (one-sided) (6.38)
where
Rneq =RCM + (R +RS) (CC 2 + R 22 C (6.39)
and C1L is the series combination of C1 and CL. This formulation assumes that
the RC time-constant of the switch and capacitor network is much smaller than the
preamplifier time constant. The preamplifier filters the switch noise resulting in jitter
in the comparator decision. The transfer function to refer this noise source to the
input of the stage is similar to the preamplifier response noise
2H \ 1 1(- 2e-ti/o cos (27rfti) + e-2ti/ro\

= 1wfil
+)I (27rf To)2) 1 - 2e-ti/o + e-2ti/Tao . (6.40)
The one-sided input referred aliased noise contribution from the switch noise during
the preamplifier response time is
2 (6.41)
Sn,filter(f)= Hw,fiter(f - nffs) SRneq(f - nf,).
n
where SRneq (f - nf8 ) is twice the two-sided noise PSD from the equivalent switch
noise resistance Rneq.
Because the the noise bandwidth of the preamplifier filters the switch noise at vx
in a manner similar to the input referred noise of the preamplifier
1
VRfiter = 4kTRneq 1 (6.42)
for
an
ideal
integrator
preamplifilter.
Therefore, this noise contributi
for an ideal integrator preamplifier. Therefore, this noise contribution from the
150
switches can be minimized through appropriate design of the switch resistances so
that Rneq is much less than the input referred noise resistance Rn of the preamplifier.
Sampling Noise
The noise sampled onto the load capacitance from the switch and capacitor network
assuming that the threshold detection comparator was not present is just the kT/C
noise of the equivalent total capacitance
Cx 0CL
Ce L (6.43)
Ce= C+ CL
where Cx is the series combination of the feedback capacitances C1 and C2. The noise
voltage on CL is the kT/C noise of 0C q through the voltage divider from veq to the
load capacitance
oR,sample =C C L
= ( x (6.44)
CL CX + CLC (6.44)
Therefore, the input referred noise is
C C_
v2 = _kT 2
(6.45)
R,sample CL Cx + CL C1 + C2
where (C1 +-C2)/C 1 is the stage gain. Because this is a white noise source, its one-sided
noise PSD is constant over the Nyquist range is
V2
Sn,sample(f) _R= (6.46)
f,/2
Note, this result could also have been obtained using the steady-state transfer function
for the switch and capacitor network and the aliasing summation.
151
Total Switch Noise
The total one-sided input referred noise from the switches during the charge transfer
phase is sum of the noise voltage variances of the kT/C noise of the load and the
switch noise error in the threshold detection
Sn,R(f) = Sn,ilter(f) + Sn,sample(f). (6.47)
The total noise contribution from the switches for an ideal integrator preamplifier
is the sum of the noise voltage variances for the two independent noise contributions
(6.42) and (6.45). The filtered switch noise can be managed through appropriate
sizing of switch resistances, but the sampling kT/C noise represents a fundamental
noise limitation that depends on the size of the capacitances used. Unlike the usual
kT/C limitation, the noise here is not solely defined in terms of CL. For example,
consider a gain of two stage C1 = C2 = C,/2 where the load capacitance is scaled by
a factor of two CL = C,/2. Then, the input referred noise contribution from sampling
at the output is
R,sample
2
61 kT
C, (6.48)
It should also be pointed out that the traditional op-amp based charge transfer
implementations have similar contributions from the switch noise (Figure 6-10). In
an op-amp based system, the switch and capacitor network has a wider bandwidth
than the op-amp feedback loop. Therefore, the feedback loop filters a portion of the
switch noise, but some also reaches the output through a feed-forward path. These
two contributions are similar to those in the comparator-based charge transfer, but
the two contributions in the op-amp based system are not independent.
6.4 Putting It All Together

This section discusses how to combine the filter results above to determine the total
input referred noise PSD of the CBSC gain stage and prototype ADC. The thermal
152
r0-
D%i
k ) v REF Rs
RcM e2
VCM VCM
Sn (f)
Feedback path
1 kT
SCs
g01o f
Figure 6-10: Op-amp based charge transfer switch noise contribution for a gain of
two stage. Op-amp noise bandwidth is 1/(4•o) = f3dB, C1 = = C0, and the load
capacitance has been scaled by a factor of two CL = C,/2. (a) Schematic of op-amp
based gain of two stage with switch resistances shown. (b) Input referred noise PSD
highlighting feedback V,,FB and feed-forward v2FF noise paths.
153
noise contributions for CBSC designs with ideal integrator preamplifiers are compared
to similar contributions in op-amp based designs and to each other.
6.4.1 Complete Noise PSD Estimate
The noise transfer functions for the periodic filter model derived in the previous
section can be combined to determine the input referred noise PSD estimate for the
switched-capacitor gain stage. Numerical techniques for calculating the noise PSD
from the transfer function, the input noise PSD, and the aliasing summation were
presented in Chapter 3. For the prototype, a cascade of identical stages was used for
the pipeline ADC, and the total input referred noise of the ADC can be calculated
using (6.2) and (6.3). In Chapter 7, the results of the theoretical model presented
here are compared to noise measurements from the prototype CBSC pipeline ADC.
6.4.2 Comparison of White Noise Voltage Contributions
Based on the mean-squared noise voltage results presented above, relative compar-
isons about the importance of the different thermal noise source are made. Emphasis
is placed on the noise sources that are unique to CBSC designs compared to op-amp
based designs. The importance of folded flicker noise is also addressed.
Thermal Noise
Assuming that both the op-amp and CBSC designs use the open-loop input sampler,
they both suffer equally from the kT/Cs noise of the sampling capacitors. As discussed
in Section 6.3.4 and shown in Figure 6-10, the switch noise contributions for a CBSC
gain stage have similar contributions in op-amp based designs. However, the sampling
noise and filtered noise in a CBSC system are independent because of the finite delay
of the threshold detection comparator and logic that follow the preamplifier. In the
op-amp based gain stage, the feedback loop filters the switch noise within the loop
bandwidth, but at frequencies beyond the loop bandwidth, the switch noise feeds
154
vo0
Vo[k] - Ilrrll
-
IVv
T
mt= s
Lr-
2 M·
II
! _
Top nTop
E1 E2
Ts
2
Figure 6-11: CBSC versus op-amp based charge transfer timing. Because ti can po-
tentially be made a larger fraction of T,/2 than the op-amp closed-loop time constant
Top can be, for the same power consumption and speed, the comparator-based design
has lower noise bandwidth.
directly to the output capacitance.
The most significant difference in the noise performance of comparator-based and

op-amp based switched capacitor systems is the noise contribution of the op-amp ver-
sus the virtual ground threshold detection comparator and charging current source.
First, the charging current noise is assumed to be significantly smaller than the pream-
plifier noise. The preamplifier noise is then compared to the op-amp noise. Finally,
the conditions for when the charging current noise is significantly smaller than the
preamplifier noise are determined.
From (6.11), the input referred noise for the preamplifier is the expected noise PSD
and the noise bandwidth is inversely proportional to the response time ti. For an op-
amp based system, the input referred noise PSD may be larger than the threshold
comparator and preamplifier due to architectural differences in the op-amp that are
155
necessary to acheive high gain and make the op-amp stable in feedback. In an op-
amp based system, the closed-loop bandwidth of the system determines the noise
bandwidth
Nr 1
NBWo = -2 f3dB = (6.49)
4rop
where the op-amp based system is modeled with a single pole. The number of closed-
loop time constants in a half clock-cycle for an op-amp based system is relatively
large and the desired accuracy determines the required number of time constants. In
a CBSC system, potentially, the preamplifier response time of the fine charge transfer
phase can be made a larger fraction of T,/2 than Top. This situation is illustrated in
Figure 6-11. It should be possible to trade the noise advantage of comparator based
designs for lower power consumption at the same speed of operation. Therefore,
CBSC designs have the potential to achieve the same noise accuracy and speed of
operation at a lower power consumption than their op-amp based counterparts.
The preceding argument assumed that the noise contribution from the charging
current is negligible, but in reality, the charging current noise also places a limit on
the minimum value of capacitances that can be used to achieve a given accuracy for a
specified overshoot requirement. In order for the charging current noise to be smaller
than the preamplifier noise
CE > 3 -IGn. C (6.50)

kT/q
where VM is the change in preamplifier output voltage to reach the threshold com-
parator trip point and G,/Gm is total input referred noise conductance relative the
transconductance of the preamplifier input pair. Given a noise requirement, the
preamplifier integration capacitance can be determined as discussed in Chapter 4.
Folded Flicker Noise
As discussed in Chapter 3, folded flicker noise appears white in the aliased spectrum.
Using the conservation of noise power expressions for flicker noise aliasing (3.111),
156
the folded flicker mean squared noise can be estimated as
afo = (H(0)2 Sx(1)ln (fs2 (6.51)
where an ideal brick-wall filter with gain IH(O)I and noise bandwidth NBW have been
assumed. The folded flicker noise contribution is significant compared to the aliased
thermal noise unless
exp (NW
BW (6.52)
f92 < exp (6-52)
f 8 /2 fic
which implies that the noise bandwidth of the system is greater than the flicker noise
corner frequency. Unfortunately, this folded flicker noise contribution is present even
when correlated double sampling is used [35].
If the preamplifier response time noise dominates, the folded flicker noise contri-
bution using (6.51) is
2n,pramp
n,preamp 2Sin,resp(1))
G2 n ( .j (6.53)
where Sin,resp(1) is the two-sided flicker noise current PSD at 1 Hz from the pream-
plifier. The noise is only a function of input referred flicker noise of the preamplifier
and depends logarithmically on the ratio of Ts and ti, which is greater than or equal
to 2 for the limiting case of ti = T,/2. Assuming that the relationship between
tj and the sampling period is fixed, the main factor determining the magnitude of
the folded flicker noise contribution is the input referred flicker noise density at 1 Hz
(2 Sin,r.esp(1)). Lowering the contribution of the folded flicker noise in a given technol-
ogy, requires increasing the area of the devices used in the preamplifier, especially the
input differential pair. However, increasing the transistor sizes increases the parasitic
capacitances and possibly the required power consumption.
An approximate expression for the folder flicker noise contribution from the charg-
ing current source 12 can also be found. Assuming the noise during preamplifier
157
response time dominates the charging current noise
, 12
41V2
S,2 (
OVx
S, (1)I
2 43 T(6.54)
tJ
where Vo,, is the overshoot at the output of the gain stage referred to the input, and
Sx (1) is the one-sided flicker noise current PSD at 1 Hz from the charging current
source 12.
The folded flicker noise contribution is not unique to comparator-based designs.

Op-amp designs would also suffer from the effects of folded flicker noise in a similar
manner. However, the larger noise bandwidths of op-amp based systems means that
flicker noise corner frequencies need to be that much higher for folded flicker noise to
be significant compared to the aliased thermal noise.
6.5 Summary
The periodic filtering analysis for a series of samples from a possibly non-stationary
underlying random process presented in Chapter 3 was applied to the CBSC charge
transfer phase to derive a set of noise transfer functions than can be used to obtain a
noise PSD estimate for a given CBSC design. In addition, noise voltage expressions
were derived for the simplified case of an ideal integrator preamplifier. These simpli-
fied expressions were used to comment on the relative importance of each noise source
and compare it to the similar noise source in an op-amp based implementation. As a
final note, parasitic capacitances at the virtual ground summing node and the output
node have been ignored in the equations given in this chapter to avoid unnecessarily
complicating the discussion. However, the effect of these capacitances can be signif-
icant. It is relatively straight forward to extend the expressions presented here to
include their effect, and the theoretical estimate given in Chapter 7 does include the
effects of these parasitics.
158
Chapter 7
Measured Results of Noise in

CBSC
7.1 Overview
Measured results of the noise performance of the prototype CBSC pipeline ADC
are presented. The theoretical PSD estimates from Chapter 6 are compared with
measured results for a variety of sampling frequencies. It is found that the two
dominant sources of noise for the prototype are the flicker and thermal noise from the
preamplifier of the comparator.
7.2 Mleasurement Method
A measurement of the input referred noise PSD of the prototype ADC can be made
from the measurement of ADC output codes for a zero DC input. These output codes
can then be mapped into the equivalent input noise voltage that would be used to
generate them for a noiseless ADC
VDo(nT8 ) = Do(nT,) VLSB12 (7.1)
159
where Do(nTs) is the measured output code of sample n and VLSB12 least significant
bit voltage for the prototype converter using all 12 b of output. A periodogram
estimate [59] of the noise PSD can then be made from the series of samples
ST.(f) = 2 F{Ts VDo,(nTs)} df (7.2)
where T, = 1/f, is the sampling period, df = 1/To is the FFT bin width, To = NT,
is the duration of the data record and N is the number of samples in the data record
and the length of the FFT. The factor of 2 in (7.2) is because the one-sided PSD
estimate is calculated.
Because a single periodogram measurement has a large variance, spectral averag-

ing techniques are required to make an unbiased, low variance spectral estimate [59].
A simple method for achieving the spectral averaging is to average a large number K
of independent periodogram measurements
K
ST (f) = STo,k (f). (7.3)
k=1
The expected value of the average periodogram estimate is the same as that of the
original periodogram [59]
E{-ST(f)} = 2S(f) Tosinc (f To) df (7.4)
which is the actual PSD S(f) convolved with the magnitude squared of the Fourier
transform of a rectangular window of duration To. From the discussion of noise
bandwidth in Chapter 3, the two-sided noise bandwidth of the sinc filter is 1/To = df.
Therefore, if the actual noise PSD is constant over the noise bandwidth of the sinc
filter, the periodogram estimate is approximately unbiased. In the limit of To --, co,
the noise bandwidth goes to zero, and the periodogram is an unbiased estimate of
S(f) [59].
160
The standard deviation of the average periodogram estimate is [59]
1
Std{STo(f)} [2S(f)] f # 0. (7.5)
For example, for an average of 100 periodogram measurements, the standard deviation
is roughly 10 % of the mean. The data presented here uses K = 30, which results in
a standard deviation of approximately 18 % of the mean.
The advantage of the average periodogram spectral estimation technique is that
it achieves smoothing of the periodogram PSD estimate without loss of frequency
resolution. The disadvantage is that large amounts of data are required to obtain a
low variance PSD estimate.
Because investigation of the low frequency flicker noise is desired, the minimum
frequency of the periodogram is of interest. The lowest frequency bin in the FFT
depends on the length of the data record
1 f
df = N (7.6)
To N
Therefore, the only way to measure very low frequency noise is to increase the duration
of the data record either through the collection of more continuous samples (increase
N) or increasing the time between samples (decrease fs). The minimum frequency
FFT bin has a width of df centered around df Hz, which extends from ½df < f < ldf.
All noise from frequencies less than ½df is lumped into the DC FFT frequency bin
and appears as an time-varying offset between the datasets.
7.3 Results
The measured PSD estimates using the average periodogram method are compared
with theoretical estimates made using the analysis from Chapter 6. Device parameters
for prototype design are determined from simulations and parasitic extraction of the
layout.
161
~.--10
N
N
I
cu%
-0
3 A-, A
_C 0
10 10 10 10
(MHz)
Figure 7-1: Theoretical and measured noise PSD f, = 2.4576 MHz, K = 30
7.3.1 ADC Input Referred Noise PSD
For a sampling frequency of 2.4576 MHz, both the measured and theoretical noise
PSD estimates are shown in Figure 7-1 in a log-log graph. The theoretical estimate
and measured PSD match to within knowledge of the device flicker noise parameters
and output resistance of preamplifier devices. Sensitivity of the theoretical prediction
to these parameters is investigated in Section 7.3.2.
The theoretical breakdown of the noise contributions for the 2.4576 MHz sampling
frequency data is given in Figure 7-2(a). This plot shows the contributions of the
direct baseband flicker noise, the folded flicker noise, the total aliased thermal noise,
and their contribution to the total noise PSD. The apparent white noise is the sum
of the aliased thermal noise and the folded flicker noise PSDs. It is clear from this
graph that the folded flicker noise contributes significantly to the apparent white
noise of the ADC. Figure 7-2(b) plots the top four contributors to the apparent white
noise of the ADC and shows that the folded flicker noise of the preamplifier dominates.
162
-10
IU
N
S10 -1
ý- 1
1
- 0 1
Iv
10-3 10-2 10- 1 100
(MHz)
- 13
I.5i
., 10 I I I 1 1 I
-- Total Apparent White
•Preamp Folded Flicker
- Preamp Thermal
+ Input Sampling
-+-Quantization
A C-
A. r•
AA
• Am
A.
0.2 0.4 0.6 0.8 1 1.2

(MHz)
Figure 7-2: Theoretical breakdown of PSD noise for f, = 2.4576 MHz (a) Theoretical
breakdown of aliased components. (b) Theoretical breakdown of apparent white noise
sources.
163
Rank PSD (V2/Hz) % of Total Source
1 2.62 x 10- 14 42.8% Preamp Folded Flicker
2 1.75 x 10-14 28.6% Preamp Thermal
3 7.79 x 10-15 12.7% Input Sampler
4 4.04 x 10-15 6.60% Quantization Noise
5 3.36 x 10- 15 5.49% Switch Noise Preamp Response
6 1.12 x 10- 15 1.84% Output Sample
7 7.36 x 10-16 1.20% Charging Current Thermal: tc
8 2.26 x 10-16 0.37% Charging Current Thermal: t,
9 1.83 x 10- 16 0.30% Charging Current Folded Flicker: t,
10 5.77 x 10-17 0.09% Charging Current Folded Flicker: t,
11 8.46 x 10-19 0.00% Preamp Clamp Thermal
12 5.75 x 10-19 0.00% Preamp Clamp Folded Flicker
Table 7.1: Ranking of apparent white noise sources in ADC PSD estimate for sampling
frequency f, = 2.4576 MHz.
Specifically, it is the flicker noise of the input pair devices that represents the dominant
contribution to the folded flicker noise. Table 7.1 shows a complete breakdown of
all possible apparent white noise sources from their theoretical estimates and their
relative contribution to the total apparent white noise.
Figure 7-3 and Figure 7-4 compare the theory and measurements for two addi-
tional sampling frequencies of 983.04 kHz and 327.68 kHz. Over the three sampling
frequencies shown, the apparent white noise level varies over almost an order of mag-
nitude and still matches the theoretical prediction reasonably well.
7.3.2 Sensitivity of Theoretical Prediction
The sensitivity of the theoretical prediction to key parameters is investigated. Because

the flicker noise of the preamplifier input devices dominate the noise performance of
the prototype ADC, the theoretical results are particularly sensitive to the pream-
plifier flicker noise parameters Si, (1) and a. In addition, the output resistance Ro
determines the steady-state bandwidth of the preamplifier. Therefore, the accuracy
of the output resistance can have a noticeable effect on the thermal noise contribution
164
,-10
1U
• A
10
N
NIU
c I 10
• A
10
-
I 0
10 - 1 10 101 102
(kHz)
Figure 7-3: Theoretical and measured noise PSD fs = 983.04 kHz, K = 30.
-10
IL)
o Measurement
. Theory
000 00
-'Paol
10C -i,- VV~
N
I -12
=101
C14
1 111111 1 I I I I III( · I I I I IIIi I · 1 111111

10 - 1 100 101 102
(kHz)
Figure 7-4: Theoretical and measured noise PSD f, = 327.68 kHz, K = 30.
165
^-10
1
N
I
cu4
10- 3 10- 2 10- 1 100

(MHz)
Figure 7-5: Fit of ADC input referred noise PSD to determine preamplifier flicker
noise parameters. The flicker noise exponent a = 0.86 and the flicker noise PSD for
a single preamplifier at 1 Hz Sin(1) = 1.3 x 10-17 A2 .
of the preamplifier. Holding everything else in the theoretical calculations constant,

the effect of variations in each of these parameters are investigated.
Because the preamplifier input devices dominate the input referred flicker noise of
the prototype ADC, the baseband flicker noise can be interpreted as a measurement
of the flicker noise of the sum for all the of the preamplifiers in the pipeline. A
linear regression on the logarithm of the PSD measurements versus the logarithm
of frequency at frequencies significantly below the corner frequency of the aliased
spectrum can be used to make a measurement of the flicker noise parameters sin (1)
and a in the general flicker noise equation
s(f) = 1) (7.7)
The fit used is shown in Figure 7-5, where the flicker noise exponent a = 0.86 and
the flicker noise at 1 Hz Si, (1) = 1.3 x 10-17 A2 . These flicker noise parameters imply
166
-10
IU
f=df
.... f=f /2
-
10 11
N -
10 12
10
10- 1
........
1n-14 -
Iv10 10- 1 6
1017 S. (1) (A2) 10
n
Figure 7-6: ADC input referred noise PSD at f = f,/2 and f = df versus flicker noise
of preamplifier at 1 Hz Sin (1).
a flicker noise corner frequency for the preamplifier before sampling of fk = 41 MHz.
The extracted flicker noise parameters are consistent with simulation and measured
data, for the process.
Since the predicted theoretical value for the noise PSD depends directly on the
accuracy of the extracted flicker noise coefficients, the sensitivity of the theoretical
noise PSD prediction to the flicker noise coefficients is examined. Figure 7-6 shows a
plot of the ADC input referred PSD versus Si,,(1) at fs/2 and df. The PSD at f,/2
is a, measure of the apparent white noise, and the PSD at the first FFT bin df is a
measure of the baseband flicker noise. Figure 7-6 shows that variation in Si (1) has a
strong effect on both the baseband and folded flicker noise contributions as expected.
The flicker noise exponent a is the log-log slope of the flicker noise and is defined
above (7.7) where a is typically between 0.8 and 1.2 and ideally has a value of 1.
Figure 7-7 ,shows a plot of the ADC input referred noise PSD versus the flicker noise
exponent of the input devices of the preamplifier at f,/2 and df. The flicker noise
167
4,'\ -10
IV
f = df
..... f=f/2
10-11
N
Z 12
10
10-13,
- 14
1
0.8 0.9 1 1.1 1.2
a (-)
Figure 7-7: ADC input referred noise PSD at f = f.,/2 and f = df versus flicker noise
exponent a.
168
1
N
-1
Iv
104 1 106
Figure 7-8: ADC input referred noise PSD at f = fs/2 and f = df versus output
resistance Ro, of preamplifier.
exponent does have a noticeable effect on the magnitude of the folded flicker noise
contribution, but an exponent in the range of 0.8 to 0.9 is consistent with simulation
models and measured data for the process. For f, = 2.4576 MHz, the frequency of
the lowest FFT bin df is 150 Hz for 214 samples, so the baseband flicker noise does
change some as a is varied.
The theoretical noise estimate is also sensitive to the noise bandwidth of the
preamplifier. The preamplifier response time in the prototype was several time con-
stants, and. the output resistance defines the noise bandwidth of the preamplifier.
Figure 7-8 shows the plot of ADC input referred noise PSD versus the preampli-
fier output resistance Ro over a range of values. The output resistance value used
from simulation was 130 kQ. The BSIM3v3 simulation models used to determine
the output resistance do not take into account the effects of the pocket halo doping
on output resistance, which would tend to result in a lower than predicted output
resistance [9] [10] and wider noise bandwidth.
169
7.4 Discussion
Because the folded flicker noise, preamplifier thermal noise and input sampling noise
components dominated the noise over all possible sampling frequencies for the proto-
type, detailed measurements of the other noise sources in the CBSC gain stage were
not possible. The contributions of the other noise sources have been verified with be-
havioral simulations, but further investigation is needed to verify each of these noise
contributions independently with measured results.
It should be pointed out that the preamplifier in the prototype design had too
low of an output resistance to behave as an integrator for the fine charge transfer
phase. The required output resistance was underestimated when the prototype was
designed. One reason for the underestimation was the original assumption that the
preamplifier response time was equivalent to the zero-cross delay of the preamplifier.
As discussed in Chapter 4, the correct definition is the time which the preamplifier
noise is integrated onto its load capacitance. This time can be significantly longer
than the zero-crossing delay for a finite gain preamplifier with a slow input ramp.
In addition, the comparator was designed to be fast enough to control the coarse
phase overshoot without consuming excessive amounts of power. Because the noise
analysis was not completely understood at design time, no serious prediction of the
noise performance was possible. The goal was a functioning prototype.
The input devices of preamplifier are relatively short and small in area
W _ 3.2m (7.8)
L 0.26 tim
Flicker noise could have been lowered and output resistance increased if longer and
wider devices were used. However, if device parasitic capacitances are a significant
contributor to the preamplifier integration capacitance, additional power would be
required to maintain the same speed of operation.
A flicker noise exponent of less than one (a < 1) is clearly evident from the
measured input referred noise of the ADC. Flicker noise measurement in scaled tech-
170
SNR ENOB Description
65 dB 10.5 b Thermal noise: Theory
63 dB 10.1 b Apparent white noise: Theory
62 dB 110.0b Apparent white noise with 12 b quantization noise: Theory
59 dB 9.6 b Apparent white noise with 12 b quantization noise: Measured
58 dB 9.3 b Apparent white noise with 10 b quantization noise: Measured
53dB 8.7b SNR from FFT test with 10b quantization noise
52 dB 8.6 b SNDR from FFT test with 10b quantization noise
Table 7.2: SNR and ENOB for prototype converter for different combinations of noise
sources and harmonic distortion.
nologies have also shown NMOS devices to have flicker noise exponent consistently
less than one. Either a non-uniform trap density in the oxide or correlated mobility
fluctuations can explain this behavior [61] [62].
Table 7.2 presents the performance of the prototype ADC in terms of SNR and
ENOB assuming different combinations of noise sources and harmonic distortion. The
first row of Table 7.2 gives the SNR and ENOB of the prototype converter for thermal
noise sources only without quantization noise. The SNR and ENOB given in the
second row is for the apparent white noise (thermal noise + folded flicker noise), which
shows a degradation of 0.4 b in ENOB and 2 dB in SNR. Adding 12 b quantization
noise results in a 0.1 b degradation of ENOB. The fourth row in Table 7.2 is from
the measured apparent white noise of the converter including 12 b quantization noise.
The 3 dB difference in SNR from the theoretically predicted value occurs for the same
reasons as discussed above for the difference in measured and predicted noise PSD.
The fifth row in Table 7.2 is the measured apparent white noise for 10 b quantization
noise which. results in a 0.3 b lower ENOB. The last two rows in Table 7.2 are from the
FFT test results in Chapter 5. The SNR from the FFT test includes all higher order
harmonic distortion (first 9 harmonics removed) and shows a 5 dB reduction in SNR
compared to the measured apparent white noise with 10 b quantization noise. The
5 dB reduction in SNR is equivalent to a 0.6 b reduction in ENOB. As can be seen
in Figure 5-11, significant harmonic distortion exists across the frequency spectrum.
171
For the SNDR, the first 9 harmonic components are included, which results in an
additional 0.1 b degradation in ENOB.
7.5 Summary
The measurement technique used to extract the comparator noise from the CBSC
prototype pipeline ADC was presented. Measured results of the noise performance of
the prototype were compared with the theoretical model presented in Chapter 6. It
was found that folded flicker noise from the preamplifier was the dominant noise source
in the converter. Because of the inaccuracies of modeling parameters, the sensitivity
of the theoretical results to key parameters was explored. The results were found
to be most sensitive to the flicker noise at 1 Hz for the preamplifier input devices.
The flicker noise exponent can also cause signification differences in the amount of
folded flicker noise, but the measured noise of the ADC confirm the low flicker noise
exponent. The short comings of the prototype design were discussed, and the need
for further investigation to verify the theoretical models given in Chapter 6 with
measured data was highlighted. Finally, the impact of the different noise sources and
distortion components had on the performance of the prototype ADC was discussed.
172
Chapter 8
Conclusion
8.1 Thesis Contributions
The comparator-based switched-capacitor circuit technique proposed in [50] [15] was

reviewed, including the description and results of the the prototype 1.5 b/stage pipeline
ADC. The proposed technique eliminates the need for high gain op-amps in the signal
path, and should be applicable to a wide range of switched-capacitor circuits.
In order to analyze the noise behavior of comparator-based switched capacitors
circuits, a set of non-stationary noise analysis techniques were applied to circuit anal-
ysis problems in a framework similar to well-known stationary noise analysis methods.
A periodic filtering analysis method was used to analyze the noise power spectral den-
sity of a series of periodic samples in CBSC systems. The key result is the definition
of the appropriate filter for the non-stationary noise source that is periodically sam-
pled. Impulse sampling of the filtered noise can then be analyzed using preexisting
noise aliasing methods.
The design of efficient low noise preamplifiers for threshold detection comparators
was discussed, and a design methodology was presented. This discussion showed
that an ideal integrator represents the lowest power preamplifier implementation for
a given speed and noise requirement. In addition, the requirements of threshold
detection comparators used in CBSC designs were discussed.
173
The noise analysis techniques were applied to the analysis of a CBSC gain stage
for the prototype. The relative contribution of the noise sources from the switches,
the charging current and the comparator were detailed and comparisons were made.
Finally, the periodic filtering analysis of a series of WSS samples of a system
was used to generate a theoretical noise estimate for prototype pipeline ADC. It was
found that the noise from the preamplifier for the comparator dominated the input
referred noise performance of the prototype pipeline ADC. In addition, the folded
flicker noise contribution was significant because the flicker noise corner frequency of
the preamplifier was greater than half the sampling frequency.
8.2 Future Work
Some suggestions for future work:
* A fully-differential design implementation for CBSC charge transfer. A differ-

ential design would require a common-mode feedback circuit to equalize the
pull-up and pull-down currents to maintain a constant output common-mode
for the stage.
* An offset correction or correlated double sampling method that allows for the
removal of constant offsets and low frequency flicker noise.
* Develop methods for constant ramp generation at lower supply voltages where
cascoding of current sources is not possible.
* Additional optimization of threshold comparator designs based on the unique

threshold comparator requirements outlined in Chapter 4.
* Determine practical limits of potential power reduction for CBSC designs. Ex-
plore the possibilities of making the preamplifier integration time ti much longer
than an op-amp settling time constant To for the same linearity requirement.
174
* Test the CBSC approach in other ADC design spaces (eg. high speed or high
accuracy) and switched capacitor applications.
175
176
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Comparator Design and Analysis for

Comparator-Based Switched-Capacitor Circuits

Signature of A uthor ................ .... ...........................

Submitted to the Department of Electrical Engineering and Computer Science

Thesis Supervisor: Hae-Seung Lee

Thesis Supervisor: Charles G. Sodini

2 Comparator-Based Switched-Capacitor Circuits 27

2.2 CBSC Basic Principle of Operation . .................. 27

4 Threshold Detection Comparator Design 89

5 CBSC Prototype Pipeline ADC 117

6 CBSC Noise Analysis 133

6.1 Overview ....... ............ .............. 133

6.2 Total Input Referred Noise of Pipeline ADC . ............. 133

7 Measured Results of Noise in CBSC 159

7.1 Overview. ................... .. 159

2-2 Op-amp based switched-capacitor gain stage charge transfer phase.

(a.) Switched-capacitor circuit (b) The output voltage exponentially

2-3 Comparator-based switched-capacitor gain stage charge transfer phase.

2-4 CBSC charge transfer phase timing ............ ....... 31

3-1 Overview of time-domain and frequency-domain analysis. ....... . 45

3-2 Transconductance Amplifier. ................... .... 47

3-5 Large signal response of transconductance device with noise. ...... 51

3-9 Windowed impulse response.... ................... . 60

3-12 Transformation of voltage noise to timing jitter in the comparator de-

4-1 General definition of threshold detection comparator performance. .. 90

4-7 Relative preamplifier speed Gm/Ci and transconductance Gm versus

4-8 Required preamplifier transconductance versus output resistance for

4-9 Cascade of three amplifier stages. ................... . 106

4-10 Optimum cascade of amplifiers. (a) Optimum number of stages Nop

4-12 Current mirror op-amp as a comparator. . ................ 109

4-13 Bazes comparator based on a self-biased differential amplifier. ..... 110

6-8 Charging current transfer function during preamplifier response time.

3.1 Fraction of total noise power as a function of the number k of the

5.1 Threshold-detection comparator static bias currents. ........... 125

The design of switched-capacitor circuits in scaled CMOS technologies is becoming

Charge storage in scaled CMOS technologies is a looming problem. In the past,

1.2 Thesis Organization

The basic operation of comparator-based switched-capacitor circuits (CBSC) is in-

2.2 CBSC Basic Principle of Operation

Although the CBSC technique is applicable to a wide range of switched-capacitor

2.2.1 Sampling Circuit

2.2.2 Op-amp Based Charge Transfer Phase

vo [n] =( +C2) V[n - 1] (2.1)

Figure 2-3: Comparator-based switched-capacitor gain stage charge transfer phase.

energy efficient than forcing it.

2.2.3 Comparator-Based Charge Transfer Phase

2.3 Practical CBSC Gain Stage Charge Transfer

2.3.1 Preset Phase

Therefore, the preset value for the summing node is

x= (2 - c )VcM - VIN. (2.3)

2VcM 5 VIlN- 3 VcM. (2.4)

2.3.2 Coarse Charge Transfer Phase

Vo1= tdl (2.5)

VOx I = fo-Vo1 (2.7)

is the feedback factor.

2.3.3 Fine Charge Transfer Phase

but the signal grows proportional to the integration time

vo(t) Oc ti. (2.11)