TegraK1 TRM DP06905001 Public v03p

TECHNICAL REFERENCE MANUAL
NVIDIA Tegra K1 Mobile Processor
Abstract
The Technical Reference Manual focuses on the logical organization and control of Tegra K1 mobile processors. It
provides information for those modules that interface to external devices, or those that control fundamental chip
operations. The modules detailed in this document provide an overview, any necessary programming guidelines, and
a register listing for that module. Internal functional units such as video and graphics hardware acceleration are
controlled by NVIDIA provided software and not documented here.
Revision History
Version Date Description
v01p MAR 20, 2014 Public release to support Open Source Development. This document is a work in progress. There will be follow-up
releases as new information is made available.
v02p JUL 15, 2014 • Revised DSI and eDP maximum resolution to 3200x2000.
• I2C Controller: Revised encoding for BC_TERMINATE field.
• USB Complex: Revised maximum packet size supported on any endpoint to 1024 bytes. Clarified encoding
of MEM_ALIGNMENT_MUX_EN fields.
v03p OCT 15, 2014 • Activity Monitor/HDMI: New sections.

• APB: Added “APB_MISC_GP_MIPI_PAD_CTRL_0”. Moved SATA_AUX registers to the SATA section.
• AVP Cache Controller: Added “Initializing the AVP Cache Controller”. Added registers from offsets 0x18
through 0x84.
• Clock and Reset Controller: Added “CLK_RST_CONTROLLER_PLLE_SS_CNTL_0” and
“CLK_RST_CONTROLLER_PLLD2_SS_CFG_0”. Updated reset and default values of
CLK_RST_CONTROLLER_PLLC3_MISC_0_0.
• I2C Controller: Corrected encoding of I2C_I2C_BUS_CLEAR_CONFIG_0 register.
• Interrupt Controller: Added “EVP Registers”.
• MIPI-CSI (Camera Serial Interface): Updated the Pin Muxing for DSI and CSI Controllers figure.
• Power Management Controller: Updated the description of the APBDEV_PMC_NO_IOPOWER_0 register.
Added “Secure Boot Registers”.
• SATA Controller: Added steps for System Power Management driver using software override to “ELPG
Entry” and “ELPG Exit”.
• SPI Controller: Added “Known Limitations” and “Special Guidelines for Slave Mode”. Clarified packet size in
Unpacked Mode for Master and Slave modes.
• Thermal Sensor: Added “Temperature Sensor Calibration Registers”.
TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com

Tegra K1 Technical Reference Manual
Table of Contents
Table of Contents
1.0 Introduction ....................................................................................................................................................... 11
1.1 The Role of the Technical Reference Manual .............................................................................................. 11
1.2 Block Diagram .............................................................................................................................................. 12
1.3 Memory Controller and Internal Bus Architecture ........................................................................................ 13
1.4 Reading Register Tables .............................................................................................................................. 14
1.5 Glossary........................................................................................................................................................ 15
2.0 Address Map..................................................................................................................................................... 19
2.1 System Address Map ................................................................................................................................... 19
2.2 Available DRAM Address Ranges ................................................................................................................ 25
3.0 Interrupt Controller ............................................................................................................................................ 29
3.1 References ................................................................................................................................................... 29
3.2 Interrupt Mapping.......................................................................................................................................... 29
3.3 Hierarchical Groups ...................................................................................................................................... 34
3.4 Functional Description .................................................................................................................................. 34
3.5 Interrupt Registers ........................................................................................................................................ 43
4.0 Semaphores ..................................................................................................................................................... 51
4.1 Arbitration Semaphores ................................................................................................................................ 51
4.2 Semaphore Registers ................................................................................................................................... 52
5.0 Clock and Reset Controller ............................................................................................................................... 55
5.1 Hardware Features ....................................................................................................................................... 55
5.2 Clocking Architecture .................................................................................................................................... 56
5.3 PLLs .............................................................................................................................................................. 72
5.4 Reset Architecture ........................................................................................................................................ 75
5.5 Power Gating and Ungating ......................................................................................................................... 75
5.6 Software Features and Programming Model ................................................................................................ 77
5.7 Clock and Reset Controller Registers .......................................................................................................... 92
6.0 CL-DVFS ........................................................................................................................................................ 247
6.1 CL-DVFS Registers .................................................................................................................................... 247
7.0 Timers ............................................................................................................................................................. 253
7.1 ARM CPU Generic Timers (GITs) .............................................................................................................. 253
7.2 Generic Timer System Counter (TSC) ....................................................................................................... 253
7.3 NVIDIA Timers (TMR) ................................................................................................................................ 254
7.4 Watchdog Timers (WDTs) .......................................................................................................................... 255
7.5 Secure TMRs and Secure WDTs ............................................................................................................... 255
7.6 Legacy Watchdog Timer ............................................................................................................................. 256
7.7 Watchdog Timer Programming Guide ........................................................................................................ 257
TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 2

Table of Contents
7.8 Timers Registers......................................................................................................................................... 258

7.9 Fixed Time Base Registers ........................................................................................................................ 259
7.10 Watchdog Timers...................................................................................................................................... 260
7.11 Timer Shared Interrupt Status .................................................................................................................. 263
8.0 Multi-Purpose I/O Pins and Pin Multiplexing (Pinmuxing) .............................................................................. 265
8.1 Overview ..................................................................................................................................................... 265
8.2 Terms and Acronyms ................................................................................................................................. 265
8.3 MPIO Pad Description ................................................................................................................................ 265
8.4 Pad Controls ............................................................................................................................................... 267
8.5 Pinmuxing ................................................................................................................................................... 269
8.6 Cold Boot Reset.......................................................................................................................................... 272
8.7 Secondary Boot .......................................................................................................................................... 272
8.8 Deep Sleep Behaviors ................................................................................................................................ 273
8.9 GPIO Controller .......................................................................................................................................... 276
8.10 Programming Considerations ................................................................................................................... 276
8.11 GPIO Registers......................................................................................................................................... 278
8.12 Pinmux Registers...................................................................................................................................... 293
9.0 Power Management Controller ....................................................................................................................... 377
9.1 Register Definitions for the PMC ................................................................................................................ 377
9.2 PMC Registers............................................................................................................................................ 378
9.3 PMC Counter 0 Registers ........................................................................................................................... 484
9.4 PMC Counter 1 Registers ........................................................................................................................... 487
9.5 Secure Boot Registers ................................................................................................................................ 489
10.0 Activity Monitor ............................................................................................................................................. 495
10.1 Functional Description .............................................................................................................................. 495
10.2 ACTMON Registers .................................................................................................................................. 496
11.0 Real-Time Clock ........................................................................................................................................... 521
11.1 Functional Description .............................................................................................................................. 521
11.2 RTC Registers .......................................................................................................................................... 522
12.0 Host Subsystem............................................................................................................................................ 527
12.1 Glossary.................................................................................................................................................... 527
12.2 Features .................................................................................................................................................... 529
12.3 Hardware Features ................................................................................................................................... 530
12.4 Unit Description ........................................................................................................................................ 539
12.5 Performance ............................................................................................................................................. 546
12.6 Host1x Programming Model ..................................................................................................................... 546
12.7 Host Channel Opcodes ............................................................................................................................ 551
12.8 Host Channel Registers ............................................................................................................................ 552
Table of Contents
12.9 Host SYNC Registers ............................................................................................................................... 558

12.10 Host Class Methods ............................................................................................................................... 582
12.11 Host Proto Channel Registers ................................................................................................................ 589
13.0 Video Image Compositor (VIC) ..................................................................................................................... 595
13.1 Features .................................................................................................................................................... 595
13.2 Block Diagram Description ....................................................................................................................... 595
13.3 Functionality.............................................................................................................................................. 597
13.4 Programming Guidelines .......................................................................................................................... 615
13.5 VIC THI Registers ..................................................................................................................................... 642
13.6 HOSTIF Miscellaneous Registers ............................................................................................................ 644
13.7 Falcon UCTL Registers ............................................................................................................................ 645
13.8 Falcon DMA Registers .............................................................................................................................. 646
14.0 CPU .............................................................................................................................................................. 649
14.1 Cortex-A15 CPU ....................................................................................................................................... 649
14.2 4-Plus-1 Configuration and Control .......................................................................................................... 650
14.3 Exclusive Operations ................................................................................................................................ 650
14.4 CPU Voltage Sensing Control .................................................................................................................. 650
15.0 Flow Controller.............................................................................................................................................. 653
15.1 Features and Functionality ....................................................................................................................... 653
15.2 Flow Controller Registers ......................................................................................................................... 662
16.0 Memory Controller ........................................................................................................................................ 679
16.1 Memory Controller Architecture ................................................................................................................ 679
16.2 Hardware Features ................................................................................................................................... 680
16.3 Software Features .................................................................................................................................... 682
16.4 Software Interfaces ................................................................................................................................... 686
16.5 Functionality.............................................................................................................................................. 700
16.6 Memory Tiling ........................................................................................................................................... 711
16.7 Memory Controller Registers .................................................................................................................... 714
17.0 AHB .............................................................................................................................................................. 873
17.1 AHB Bus ................................................................................................................................................... 873
17.2 AHB Bus Arbiter........................................................................................................................................ 873
17.3 AHB “Gizmo”............................................................................................................................................. 876
17.4 AHB Memory Controller Slave.................................................................................................................. 893
18.0 APB ............................................................................................................................................................... 909
18.1 APB Miscellaneous Registers .................................................................................................................. 909
18.2 APB DMA Controller ................................................................................................................................. 933
19.0 USB Complex ............................................................................................................................................... 973
19.1 USB Overview .......................................................................................................................................... 973
Table of Contents
19.2 USB 2.0 Controllers and Interfaces .......................................................................................................... 974

19.3 USB 2.0 Programming Interfaces ............................................................................................................. 976
19.4 USB 3.0 Controller .................................................................................................................................... 977
19.5 USB 3.0 Programming Interface............................................................................................................... 978
19.6 USB PADCTL ........................................................................................................................................... 979
19.7 Programming Guidelines .......................................................................................................................... 981
19.8 Recommended PHY Settings ................................................................................................................. 1028
19.9 BIAS PAD Configuration ......................................................................................................................... 1028
19.10 BOOT ROM Initialization Sequence for USB Recovery ....................................................................... 1029
19.11 Performance Settings for USB Controllers ........................................................................................... 1030
19.12 USB Controller Handling of USB Resume Sequence .......................................................................... 1031
19.13 USB Registers ...................................................................................................................................... 1031
20.0 Audio Hub (AHUB) ..................................................................................................................................... 1311
20.1 Crossbar ................................................................................................................................................. 1312
20.2 Audio Client Interface (ACIF) .................................................................................................................. 1312
20.3 APBIF ..................................................................................................................................................... 1314
2
20.4 I S Controller .......................................................................................................................................... 1315
20.5 Serial Peripheral Device Interface (S/PDIF) ........................................................................................... 1321
20.6 Digital Audio Mixers ................................................................................................................................ 1324
20.7 Audio Multiplexer Block (AMX) ............................................................................................................... 1325
20.8 Demultiplexer Block (ADX) ..................................................................................................................... 1326
20.9 Audio Flow Controller (AFC) ................................................................................................................... 1327
20.10 Audio Hub Registers ............................................................................................................................. 1327
21.0 Display Controller ....................................................................................................................................... 1447
21.1 Features .................................................................................................................................................. 1447
21.2 Block Diagrams....................................................................................................................................... 1452
21.3 Display Controller Description ................................................................................................................ 1453
21.4 Programming Model ............................................................................................................................... 1486
21.5 Display Controller Registers ................................................................................................................... 1487
21.6 Display CMD Registers .......................................................................................................................... 1497
21.7 Display COM Registers .......................................................................................................................... 1521
21.8 Display DISP Registers .......................................................................................................................... 1527
21.9 Window A (WINC_A) Registers .............................................................................................................. 1562
21.10 WINBUF_A Registers ........................................................................................................................... 1589
21.11 Window B (WINC_B) Registers ............................................................................................................ 1603
21.12 WINBUF_B Registers ........................................................................................................................... 1630
21.13 Window C (WIN_C) Registers .............................................................................................................. 1644
21.14 WINBUF_C Registers ........................................................................................................................... 1670
Table of Contents
21.15 Window D (WIN_D) Registers .............................................................................................................. 1683

21.16 WINBUF_D Registers ........................................................................................................................... 1687
21.17 Window T (WIN_T) Registers ............................................................................................................... 1694
21.18 WINBUF_T Registers ........................................................................................................................... 1699
22.0 MIPI-DSI (Display Serial Interface)............................................................................................................. 1707
22.1 Features .................................................................................................................................................. 1707
22.2 Functionality............................................................................................................................................ 1707
22.3 Modes of Operation ................................................................................................................................ 1711
22.4 FIFO Buffers ........................................................................................................................................... 1712
22.5 Programming Guidelines ........................................................................................................................ 1713
22.6 MIPI-DSI Registers ................................................................................................................................. 1740
22.7 Initialization Sequence Registers ........................................................................................................... 1747
22.8 Packet Sequence Registers ................................................................................................................... 1748
22.9 DCS Command and Packet Length Registers ....................................................................................... 1755
22.10 Physical Interface Timing Registers ..................................................................................................... 1756
22.11 Contention Recovery Timers ................................................................................................................ 1758
22.12 Physical Pad Control Registers ............................................................................................................ 1759
23.0 High-Definition Multimedia Interface........................................................................................................... 1765
23.1 Features .................................................................................................................................................. 1765
23.3 Audio / Display Driver Communication ................................................................................................... 1772
23.4 Clock Use Cases .................................................................................................................................... 1773
23.5 CTS/N/AVAL Algorithm .......................................................................................................................... 1773
23.6 HDMI Registers ...................................................................................................................................... 1774
23.7 Serial Output Resource Registers .......................................................................................................... 1815
23.8 Test and Debug Registers ...................................................................................................................... 1847
23.9 Audio Registers ...................................................................................................................................... 1851
24.0 LVDS/eDP Display Output .......................................................................................................................... 1861
24.1 Overview ................................................................................................................................................. 1861
24.2 Features .................................................................................................................................................. 1861
24.3 Functional Description ............................................................................................................................ 1862
24.4 DisplayPort Overview ............................................................................................................................. 1862
24.5 SOR Security .......................................................................................................................................... 1863
24.6 LVDS/eDP Registers .............................................................................................................................. 1863
24.7 DPAUX Registers ................................................................................................................................... 1938
25.0 HDMI CEC .................................................................................................................................................. 1951
Table of Contents
25.3 CEC Registers ........................................................................................................................................ 1954

26.0 MIPI-CSI (Camera Serial Interface)............................................................................................................ 1967
26.2 Use Cases .............................................................................................................................................. 1969
26.3 Performance ........................................................................................................................................... 1970
26.4 Supported CSI to VI Data Formats ......................................................................................................... 1971
26.5 CSI Packet Structure .............................................................................................................................. 1972
26.6 CSI Implementation ................................................................................................................................ 1973
26.7 Performance Limitations ......................................................................................................................... 1973
26.8 Frame Size Mismatch Scenarios ............................................................................................................ 1974
26.9 Error Handling......................................................................................................................................... 1976
26.10 Other Architectural Constraints ............................................................................................................ 1977
26.11 CSI Datapath Module ........................................................................................................................... 1977
26.12 Test Pattern Generator (TPG) .............................................................................................................. 1979
26.13 Differential Pulse Code Modulation Support ........................................................................................ 1981
26.14 Software Requirements ........................................................................................................................ 1982
26.15 DPHY Modes of Operation ................................................................................................................... 1983
26.16 MIPI-CSI Registers ............................................................................................................................... 1984
27.0 MIPI D-PHY Calibration for CSI and DSI ................................................................................................... 2021
27.1 MIPI-CAL Registers ................................................................................................................................ 2021
28.0 Video Input (VI) ........................................................................................................................................... 2029
28.1 Functionality............................................................................................................................................ 2029
28.2 Data Formatting ...................................................................................................................................... 2048
28.3 VGP (GPIO) Interface ............................................................................................................................. 2061
28.4 Error Handling......................................................................................................................................... 2062
28.5 VI Registers ............................................................................................................................................ 2063
28.6 VI Input CSI Interface Registers ............................................................................................................. 2072
28.7 MIPI-CSI Registers ................................................................................................................................. 2085
29.0 SD/MMC Controller .................................................................................................................................... 2087
29.1 Supported Specifications and Standards ............................................................................................... 2087
29.2 Supported Speeds .................................................................................................................................. 2087
29.3 Operation ................................................................................................................................................ 2089
29.4 Caveats and Assumptions ...................................................................................................................... 2089
29.5 SD/MMC Interfaces ................................................................................................................................ 2090
29.6 Pinmux Options ...................................................................................................................................... 2091
29.8 SD/MMC Registers ................................................................................................................................. 2104

Table of Contents
30.0 SNOR (GMI) Controller .............................................................................................................................. 2115

30.3 GMI/SNOR Registers ............................................................................................................................. 2122
31.0 SATA Controller .......................................................................................................................................... 2127
31.1 Overview ................................................................................................................................................. 2127
31.2 Device ID ................................................................................................................................................ 2127
31.3 Device Sleep........................................................................................................................................... 2127
31.4 Power Gating Sequence......................................................................................................................... 2129
31.5 Address Translation ................................................................................................................................ 2134
31.7 Registers ................................................................................................................................................. 2140
32.0 PCI Express (PCIe) Controller.................................................................................................................... 2261
32.1 Supported Configurations ....................................................................................................................... 2261
32.3 PCIe Registers........................................................................................................................................ 2267
32.4 AFI Registers .......................................................................................................................................... 2353
33.0 I2C Controller.............................................................................................................................................. 2369
33.1 Functionality............................................................................................................................................ 2369
33.2 Software Interfaces ................................................................................................................................. 2371
33.4 Programming Guidelines for Packet-Based Interface ............................................................................ 2380
33.5 I2C Registers .......................................................................................................................................... 2381
34.0 UART and VFIR Controller ......................................................................................................................... 2401
34.2 UART Programming Guidelines ............................................................................................................. 2405
34.3 VFIR Programming Guidelines ............................................................................................................... 2410
34.4 UART Registers ...................................................................................................................................... 2421
34.5 VFIR Registers ....................................................................................................................................... 2429
35.0 Serial Peripheral Interface (SPI) Controller ................................................................................................ 2435
35.1 Functionality............................................................................................................................................ 2435
35.2 SPI Programming Guidelines ................................................................................................................. 2441
35.3 SPI Controller Registers ......................................................................................................................... 2447
36.0 PWM Controller .......................................................................................................................................... 2455
36.1 Functionality............................................................................................................................................ 2455
36.2 PWM Registers ....................................................................................................................................... 2456
37.0 Thermal Sensor and Thermal Throttling Controller .................................................................................... 2459
37.1 Thermal Throttling Controller (SOC_THERM) ........................................................................................ 2459
Table of Contents
37.2 Thermal Sensor ...................................................................................................................................... 2459

37.4 TSensor Registers .................................................................................................................................. 2463
37.5 Temperature Sensor Calibration Registers ............................................................................................ 2508
38.0 Audio-Video Processor (AVP) .................................................................................................................... 2511
38.1 Overview ................................................................................................................................................. 2511
38.2 Address Map........................................................................................................................................... 2511
38.3 Cache Controller ..................................................................................................................................... 2511
38.4 Interrupts ................................................................................................................................................. 2511
38.5 IRAM and Crossbar Bus ......................................................................................................................... 2511
38.6 AVP Registers ........................................................................................................................................ 2511
39.0 AVP Cache Controller ................................................................................................................................ 2519
39.1 Overview ................................................................................................................................................. 2519
39.2 Features .................................................................................................................................................. 2519
39.3 Address Space ....................................................................................................................................... 2520
39.4 Reference Block Decomposition ............................................................................................................ 2520
39.5 Memory Management Unit ..................................................................................................................... 2522
39.6 Access to Memory .................................................................................................................................. 2523
39.7 Cache Maintenance ................................................................................................................................ 2524
39.8 Initializing the AVP Cache Controller ..................................................................................................... 2524
39.9 AVP Cache Controller Registers ............................................................................................................ 2525

Table of Contents
[THIS PAGE INTENTIONALLY LEFT BLANK]

1.0 INTRODUCTION
® ®
The NVIDIA Tegra K1 mobile processor is a complete applications and digital media system built around several powerful
hardware elements:
® ®
 Graphics: NVIDIA GeForce Kepler Graphics Processing Unit (GPU). The GPU fully supports DX11, Shader Model
4, and OpenGL4.3 as well as OpenGL ES 3.0. It supports Unified shaders and is GPU compute capable with 192
CUDA cores. The GPU supports all the same features as discrete NVIDIA GPUs, including PhysX, CUDA, OpenCL,
and DX compute. It is highly power optimized for best performance in mobile use cases.
® ®
 CPU Complex: Quad Cortex -A15 Symmetric Multi-Processing ARM Cores in a 4-PLUS-1™ configuration with a
quad-core fast CPU complex and a fifth Battery Saver Core. The Cortex-A15 core features triple instruction issue and
both out-of-order and speculative execution. It has full cache coherency support for the quad symmetric processors.
All processors have 32 KB Instruction and 32 KB Data Level 1 caches; and there is a 2 MB shared Level 2 cache for
the quad-core complex and a 512 KB Level 2 cache for the fifth core. The NVIDIA 4-PLUS-1 architecture uses the
fifth Battery Saver Core, which operates exclusively with the main CPU complex, for very low-power, low-leakage
operation at the light CPU loads common to multimedia and lightly loaded use situations.
 Memory Controller: 64-bit DRAM interface providing high bandwidth. LP-DDR3 and DDR3L DRAM types are
supported.
 Audio/Video Decoder: the Audio-Video Processor (AVP) subsystem includes dedicated audio and video decode
hardware acceleration, an ARM7 processor, and embedded RAM. This subsystem provides full motion playback of
up to 1440P high-definition video and supports H.264 BP/MP/HP/MVC, VC-1, VP8, MPEG-2 and MPEG-4 video
standards and multiple audio standards with dedicated hardware.
 Video Encoder: A high performance H.264 capable hardware video encoder. This processor supports H.264
BP/MP/HP/MVC and VP8 encoding.
 Imaging: A high-quality hardware accelerated still-image and video capture path, with dual next-generation ISP3s.
 Display: Dual display controllers with MIPI-DSI output, along with LVDS or eDP support for LCD panels and HDMI
output for external display devices. Multiple line pixel storage allows more memory-efficient scaling operations and
pixel fetching. Hardware display surface rotation is also provided for bandwidth reduction.
In addition to these major elements, Tegra K1 mobile processors have a broad range of peripheral interfaces to enable
communication with wireless baseband, other communications peripherals, audio codecs, power management, and mass
storage. When combined with baseband and PMIC chips, the Tegra K1 mobile processor provides the functionality needed to
build a range of low-power devices. Dedicated high-performance mass storage controllers, with their own DMA engines, free
the CPU Complex from routine data management tasks.
1.1 The Role of the Technical Reference Manual

This document is intended to provide guidance to programmers writing code for Tegra K1 devices. It describes the register
interfaces and hardware functionality, with the goal to aid anyone in understanding and potentially modifying the NVIDIA
provided code.
It may also describe hardware functions not currently supported by NVIDIA drivers; thus the description of a capability in this
document does not necessarily imply software support for that function.

Introduction
1.2 Block Diagram

This diagram provides an overview of a Tegra K1 mobile processor.
Figure 1: Tegra K1 Processor Block Diagram

CCPLEX
Atomic Ops PMC AO
vGIC (Interrupt Controller) vGIC obs 32-bit
IRAM-A Semaphores Always-On
64 KB Mailboxes, EVs RTC Power Block
CPU 0 CPU 1 CPU 2 CPU 3 CPU LP
NEON
NEON
NEON
NEON
NEON
Cortex-A15 Cortex-A15 Cortex-A15 Cortex-A15 Cortex-A15 DFD Interrupt
D$ I$ D$ I$ D$ I$ D$ I$ D$ I$ (CS,OBS, 32-bit Controller
controller
32K 32K 32K 32K 32K 32K 32K 32K iLA,DDS) IRAM-B
32K 32K I2S
64 KB Timer,
PPSB Low Latency Register Bus (32-bit)

L2 (2MB) L2 (512KB) ActMons, AHUB
ARM7 Crossbar Processor Data Bus

AXI Demux AXI Demux 32-bit SysStatMons X5
128-bit AXI IRAM-C
Msel. AXI 64 KB SPDIF
AXI Msel.
CIF CPUIF CIF CPUIF Clock And Reset SRC/MIX
PCI-E
PCIe 32-bit
Dual IRAM-D Flow Controller
APB Peripheral Bus (32-bit)

Root 64 KB (HALT/WAIT/
Port SYNC) UART
128-bit AXI
X4,x1
Lane 32-bit
32-bit iROM iPatch
32-bit AXI AXI>ARM7 Boot
64-bit AXI Misc Registers
AFI MSelect (APC) Code UART / VFIR
32-bit SYS-CFG
64-bit AXI
VCP2 32-bit I2C Master/Slave

SYS
SysREGISTERS
Registers
COP GPIO
X4
Kepler AXI>C11(ACB) ARM7TDMI-S 32-bit Controller PWFM

GPU 32K
(GK20A) 32-bit SPI Master/Slave
HOST cache
APB Bridge SPI peripherals
256-bit
X6
UCQ
FE, PD, PE, RAST, SM, ROP 32-bit DTV Serial TS
BSEA SE
VDE
Video AHB (Security AHB APB Fuses
HUB, L2, LTCX
Decoder Data Engine) DMA DMA
Bridge Thermal sensor
64KB Secure
Memory
DVC
Configuration
Registers Control registers of
PPCS mccif AHB
AHB
Multi-Master
Multi-master
BusBus
(32-bit)
(32-bit)
(incl(includes
udes Mux, Decode
Mux, r, Arbi
Decoder, terand
Arbiter andAHB
A HBSLV MEM)
SLV MEM) multiple blocks here
USB2 OTG USB2 Host/
PHY device
Graphics HOST (HOST1X) USB2

USB2 OTG Host
PHY
HSIC
USB2
USB2 OTG Host
PHY
ULPI
MSENC 2.0 (S)NOR Flash HSIC
MEMORY Controller TSEC Controller
(MC2) VI Video VIC ISP3 Display Display
ISP3 (SECOP)
Encoder AD muxed
sync NOR,
128-bit 256-bit 128-bit 256-bit 128-bit 256-bit 256-bit MIO
128-bit
Memory Interface
256-bit
EMC2
256-bit crossbar
MIPI CSI SD/MMC
USB3 HD Controller
1x32/ SATA MIPI MIPI eDP/
2 ports Audio HDMI
1x64 x4 x4 x1 To USB2 DSI DSI LVDS
DDR3 / PHYs X4
Serial
LP-DDR2
camera sensor Serial Serial HDMI
Port Mux x5 Display Display 1-4 lane eDP 1.4 or SD/SDIO/
x4 x4 1 x single LVDS MMC bus

Introduction
1.3 Memory Controller and Internal Bus Architecture

The Tegra K1 mobile processor has a highly optimized 64-bit memory controller, supporting low latency access for the CPU,
optimized high bandwidth access for the graphics and video devices, and controlled latency for real time devices such as
display.
There is a three-level hierarchy of memory clients:
1. Memory controller clients: The memory controller directly arbitrates between these using a complex algorithm
optimizing DRAM efficiency. The highest bandwidth clients all fall into this class, and they communicate directly with
the memory controller using a proprietary high-speed bus.
2. AHB devices: These generally have a built-in DMA engine, and share a single memory client using the AHB bus
protocol.
3. APB devices: All APB devices are slaves, and are serviced by a shared multi-channel APB DMA controller which is
also an APB device.
Special provisions are made for the CPU to bypass parts of the memory controller arbitration to help achieve a lower latency.

Introduction
1.4 Reading Register Tables

Every register table has an address line followed by a table containing the bit descriptions for that register. The address line
contains:
 Offset: the address of the register within the specific module. Refer to the system memory map for the start address
of the module, and apply the offset at the top of the table to get the register address.
 Read/Write: the register access type. When a register table contains the R/W column, individual bits within the
register will have different R/W properties. When there is no R/W column, all bits in that register have the same R/W
property.
 Reset: gives the power-on reset value in 32-bit binary. A value of x implies that the register bit has an undefined
value at reset. A hexadecimal value is listed for convenience, where appropriate.
 Default: only displayed if the default setting is different from the Reset value.
Unspecified bits may not appear in tables (see example below). Unspecified bits should be written with their Reset values,
while reads return an unknown value.
32-bit Power-on reset Default provided if different

Register access type value from Reset
Address within the
module
Offset: 0x010 | Read/Write: R/W | Reset: 0x00040002(0b00xxxx00xxxx0100xxxxxx00xxxx0010) | Default: 0x00000000
Bit R/W Reset Description
25:24 RW N1 EMEM_NUMDEV
Unspecified bits in this example 0 = N1
register: 31:26, 23:20, 15:10, 7:4 1 = N2
19:16 RO D64MB EMEM_DEVSIZE

0 = D4 MB
1 = D8 MB
In the Reset field above the table, 2 = D16 MB
most unspecified bits are shown as 3 = D32 MB
‘x’ in binary format. In hex format, 4 = D64 MB
unspecified bits within nibbles are 5 = D128 MB
shown as 0 in the Reset field above 6 = D256 MB
the table. 7 = D512 MB
At power-on reset, write only the 9:8 RW W2 EMEM_BANKWIDTH

provided reset value to unspecified 1 = W1
bits for proper operation. For 2 = W2
3 = W3
example, in the Reset field above
the table, bits [31:30], which are not 3:0 RO W9 EMEM_COLWIDTH
specified in the table, must be 0 = W7
written as 0s. 1 = W8
2 = W9
3 = W10
4 = W11

Introduction
1.5 Glossary
This glossary is intended to cover the Tegra specific acronyms used in this document; along with some others related to the
ARM SOC world. Many acronyms in this document are in broad engineering use and are not documented here; we assume
you already know what USB and CPU are, for example.
Term Definition
ADX Audio Demultiplexer Block, part of the Audio Hub used to demultiplex multiple
audio streams.
AHB AMBA High-Speed Bus, a multi-master high-speed (relative to APB) bus
supporting arbitration and split transactions, defined as part of AMBA 2.
AHBSLVMEM The AHB slave used for the main memory interface. Acts as an AHB slave and
provides a path from there to main memory. Refer to the AHB section.
AMBA Advanced Microcontroller Bus Architecture, a set of standard buses defined by
ARM.
AMX Audio Multiplexer Block, part of the Audio Hub used to multiplex multiple audio
streams together.
APB AMBA Peripheral Bus, a simple 32-bit single master bus for peripheral devices.
APBDMA A multi-channel DMA controller for devices on the APB bus, performing DMA
between APB and AHB.
ARM Advanced RISC Machines, a company that licenses CPU IP to Tegra. Also:
Architecture Reference Manual, so the ARM defines the CPU architecture.
AVP Audio-Video Processor, the term used both to describe the ARM7 processor in
Tegra devices, and to describe the broader audio and video decode acceleration
hardware and RAM associated with the ARM7. Note that the AVP is sometimes
known as COP in legacy documentation and registers.
AXI AMBA Advanced eXtensible Interface, a more advanced bus than AHB defined as
part of AMBA 3.
BSEA Bit Stream Engine for Audio applications
CAR Clock and Reset module allows controlling clocks and resets to all the modules
and subsystems in the Tegra processor.
CEC Consumer Electronics Control, a part of the HDMI interface specification used for
sending device control commands, often from a remote control.
COP CO-Processor, an obsolete name for the AVP still present in legacy
documentation and registers.
CSI MIPI Camera Serial Interface, a standard high-speed serial interface for
connecting cameras to the Tegra processor.
DAM Digital Audio sample-rate conversion and Mixing block, a block within the Audio
Hub that performs audio mixing and sample rate conversion
DSI MIPI Display Serial Interface, a standard high-speed serial interface for
connecting displays to the Tegra processor.
DTV Digital TV input block, used to stream a serial TV transport stream of compressed
data into Tegra, using an SPI like protocol.
DVC Dynamic Voltage Controller module
eDP Embedded Display Port
EMC External Memory Controller, a module that interfaces with external DDR/LPDDR
devices.
GART Graphic Address Relocation Table, a now obsolete mechanism for mapping from
virtual to physical addresses for devices. Remains in Tegra only as an aperture to
memory that may be mapped though the SMMU, the replacement for the GART.
GPIO General Purpose Input/Output, an I/O signal uncommitted to a specific role and
controlled by software.
HDMI High-Definition Multimedia Interface, a digital connection carrying uncompressed
video and audio at high speed over a single connector.
HSI MIPI High-Speed Synchronous Interface, a standard high-speed serial interface
for bi-directional communications with baseband processors and other devices.

Introduction
Term Definition
IDE Integrated Drive Electronics (or Integrated Device Electronics)
ISP Image Signal Processor, a hardware engine that is part of the camera processing
pipeline.
KBC Keyboard Controller module allows the Tegra processor to be connected to
keyboard matrices of sizes up to 11x8.
LVDS Low Voltage Differential Signaling
MC Memory Controller module handles requests from internal clients and arbitrates
among them to allocate memory bandwidth.
MCCIF or Memory Controller Client InterFace, the standard interface block between the
MC-CIF memory controller sub-system fabric and the client device. Note that some
modules may have multiple client interfaces.
MIPI The Mobile Industry Processor Interface and industry alliance promoting a number
of standard interfaces for mobile devices.
MPCORE Multi-processor CPU core, a generic term for a CPU capable of operating as part
of an SMP group.
MPE An older name for the Video Encoder in the Tegra processor capable of encoding
raw video stream into MPEG. Now referred to as MSENC.
MSENC Multi-Standard video Encoder engine.
NAND A type of flash memory supporting high densities, and commonly used for non-
volatile mass storage in portable devices. Accessed in sequential blocks to be
generally treated as a file system.
NOR A type of flash memory, with a direct bus interface that allows random access so
code can be executed in place. Generally more costly and less dense than NAND
flash memory.
OGL Open Graphics Library, also known as OpenGL. An API supported on Tegra
devices and accelerated in hardware by dedicated 3D and 2D engines.
PCIe Peripheral Component Interconnect Express, a high-speed interface for external
devices connected to the Tegra SOC.
PMC Power Management Controller module controls the various power management
features in the system.
PPSB PortalPlayer System Bus, a proprietary register bus used for some blocks. Similar
to APB. PortalPlayer is a company that was acquired by NVIDIA, and from where
parts of Tegra are derived including this bus.
PWFM Pulse Width Frequency Modulation module generates programmed pulse widths
typically used to control backlight in display panels.
PVT Process, Voltage, & Temperature
RISC Reduced Instruction Set Computer, the CPU architecture used by ARM CPUs.
SATA Serial Advanced Technology Attachment (ATA)
SDMMC SD and MMC controller. An I/O controller supporting
SLINK Serial Link, a legacy and now obsolete name for the SPI controller
SMMU System Memory Management Unit, a block within the memory controller used to
map from a virtual address space to physical addresses for device DMA.
SMP Symmetric Multi-Processing
SOC System On a Chip, an integrated circuit containing a CPU, memory controller and
the peripheral devices needed for a computing system.
SOR Serial Output Resource. SOR is GPU IP for driving HDMI/DP/LVDS. It converts
the output of the display to a more modern high-speed serial protocol. DSI is not
included since it’s not GPU IP based
S/PDIF Sony/Philips Digital Interconnect Format
SPI Serial Peripheral Interface Bus, a synchronous serial data link, that operates in full
duplex mode.
TSEC Tegra Security co-processor, an embedded security processor used mainly to
manage the HDCP encryption and keys on the HDMI link.
TZ Trust Zone, a secure operating environment of the ARM CPU and the related
secure parts of the SOC backbone and devices

Introduction
Term Definition
TZRAM Trust Zone secured RAM on the SOC.
UCQ Unified Command Queue – a sub module within Video Decoder Engine
VCP2 Vector Co-Processor version 2, a hardware acceleration block for the signal
processing parts of audio decode and filtering. Use to offload the ARM7 AVP
during audio playback.
VDE Video Decode Engine, a Tegra hardware acceleration block dedicated to
decoding compressed video in various formats.
VI2 Video Input 2 block, the acronym used to describe the Tegra K1 block used for
camera and related input functions.
VIC Video Image Compositer, a Tegra K1 block that implements video post-
processing functions needed by a video playback application to produce the final
image for the player window.

Introduction

2.0 ADDRESS MAP
2.1 System Address Map
Table 1: System Address Map

Description Address Start Address End Offset Start Offset End Default Length
Remap 0100:0000 3fff:ffff 1008 MB
PCIE 0100:0000 3fff:ffff 0000:0000 3eff:ffff 1008 MB
PCIE_A1 0100:0000 01ff:ffff 16 MB
PCIE_A2 0200:0000 0fff:ffff 224 MB
PCIE_A3 1000:0000 3fff:ffff 768 MB
Data Memory 4000:0000 40ff:ffff 16 MB
iRAM-A 4000:0000 4000:ffff 64 KB
iRAM-B 4001:0000 4001:ffff 64 KB
iRAM-C 4002:0000 4002:ffff 64 KB
iRAM-D 4003:0000 4003:ffff 64 KB
NOR Flash 4800:0000 4fff:ffff 0000:0000 07ff:ffff 128 MB
NOR Flash_A1 4800:0000 48ff:ffff 16 MB
NOR Flash_A2 4900:0000 4aff:ffff 32 MB
NOR Flash_A3 4b00:0000 4fff:ffff 80 MB
Graphics Host Registers 5000:0000 5003:3fff 208 KB
Host1x 5000:0000 5003:3fff 0000:0000 0003:3fff 208 KB
ARM registers (@ PERIPHBASE) 5004:0000 5005:ffff 128 KB
ARM PERIPHBASE 5004:0000 5005:ffff 0000:0000 0001:ffff 128 KB
ARM Interrupt Distributor 5004:1000 5004:1fff 0000:1000 0000:1fff 4 KB
AVP CACHE 5004:0000 5004:1fff 0000:0000 0000:1fff 8 KB
Interrupt Controller Physical CPU interface 5004:2000 5004:3fff 0000:2000 0000:3fff 8 KB
Interrupt Controller Virtual CPU interface
(Hypervisor view for requesting CPU) 5004:4000 5004:4fff 0000:4000 0000:4fff 4 KB
(Hypervisor view for all CPUs) 5004:5000 5004:5fff 0000:5000 0000:5fff 4 KB
(Virtual Machine view) 5004:6000 5004:7fff 0000:6000 0000:7fff 8 KB
MSelect 5006:0000 5006:0fff 4 KB
MSelect Register Space 5006:0000 5006:0fff 4 KB
Graphics Host 5400:0000 54ff:ffff 16 MB
VI 5408:0000 540b:ffff 0008:0000 000b:ffff 256 KB
CSI 5408:0000 540b:ffff 0008:0000 000b:ffff 256 KB
ISP 5460:0000 5463:ffff 0060:0000 0063:ffff 256 KB
ISPB 5468:0000 546b:ffff 0068:0000 006b:ffff 256 KB
Display A 5420:0000 5423:ffff 0020:0000 0023:ffff 256 KB
Display B 5424:0000 5427:ffff 0024:0000 0027:ffff 256 KB
HDMI 5428:0000 542b:ffff 0028:0000 002b:ffff 256 KB
DSI 5430:0000 5433:ffff 0030:0000 0033:ffff 256 KB
VIC 5434:0000 5437:ffff 0034:0000 0037:ffff 256 KB

Address Map
DSIB 5440:0000 5443:ffff 0040:0000 0043:ffff 256 KB
MSENC 544c:0000 544f:ffff 004c:0000 004f:ffff 256 KB
TSEC 5450:0000 5453:ffff 0050:0000 0053:ffff 256 KB
SOR 5454:0000 5457:ffff 0054:0000 0057:ffff 256 KB
DPAUX 545c:0000 545f:ffff 005c:0000 005f:ffff 256 KB
GPU 5700:0000 5fff:ffff 0000:0000 08ff:ffff 144 MB
GPU_GART 5700:0000 5fff:ffff 144 MB
PPSB 6000:0000 60ff:ffff 16 MB
uP-TAG 6000:0000 6000:0fff 4 KB
Resource Semaphore 6000:1000 6000:1fff 0000:0000 0000:0fff 4 KB
Arbitration Semaphore 6000:2000 6000:2fff 0000:1000 0000:1fff 4 KB
ARB-PRI 6000:3000 6000:3fff 0000:3000 0000:3fff 4 KB
Primary ICTLR 6000:4000 6000:403f 0000:4000 0000:403f 64 B
Primary ICTLR ARB-GNT 6000:4040 6000:40ff 0000:4040 0000:40ff 192 B
Secondary ICTLR 6000:4100 6000:41ff 0000:4100 0000:41ff 256 B
Tertiary ICTLR 6000:4200 6000:42ff 0000:4200 0000:42ff 256 B
Quad ICTLR 6000:4300 6000:43ff 0000:4300 0000:43ff 256 B
Penta ICTLR 6000:4400 6000:44ff 0000:4400 0000:44ff 256 B
HIER GROUP1 ICTLR 6000:4800 6000:48ff 0000:4800 0000:48ff 256 B
TMR 6000:5000 6000:53ff 0000:5000 0000:53ff 1 KB
TMR1 0000:0000 0000:0007 8B
TMR2 0000:0008 0000:000f 8B
TMRUS 0000:0010 0000:004f 64 B
TMR3 0000:0050 0000:0057 8B
TMR4 0000:0058 0000:005f 8B
TMR5 0000:0060 0000:0067 8B
TMR6 0000:0068 0000:006f 8B
TMR7 0000:0070 0000:0077 8B
TMR8 0000:0078 0000:007f 8B
TMR9 0000:0080 0000:0087 8B
TMR0 0000:0088 0000:008f 8B
WDT0 0000:0100 0000:011f 32 B
WDT1 0000:0120 0000:013f 32 B
WDT2 0000:0140 0000:015f 32 B
WDT3 0000:0160 0000:017f 32 B
WDT4 0000:0180 0000:019f 32 B
TMR_SHARED 0000:01a0 0000:01bf 32 B
Clock and Reset 6000:6000 6000:6fff 0000:6000 0000:6fff 4 KB
Flow Controller 6000:7000 6000:7fff 0000:7000 0000:7fff 4 KB
AHB-DMA 6000:8000 6000:9fff 0000:8000 0000:9fff 8 KB
AHB-DMA CH0 6000:9000 6000:901f 0000:9000 0000:901f 32 B
AHB-DMA CH1 6000:9020 6000:903f 0000:9020 0000:903f 32 B
AHB-DMA CH2 6000:9040 6000:905f 0000:9040 0000:905f 32 B
AHB-DMA CH3 6000:9060 6000:907f 0000:9060 0000:907f 32 B
APB-DMA 6002:0000 6002:3fff 0002:0000 0002:3fff 16 KB
APB-DMA CH0 6002:1000 6002:103f 0002:1000 0002:103f 64 B

Address Map
APB-DMA CH1 6002:1040 6002:107f 0002:1040 0002:107f 64 B
APB-DMA CH2 6002:1080 6002:10bf 0002:1080 0002:10bf 64 B
APB-DMA CH3 6002:10c0 6002:10ff 0002:10c0 0002:10ff 64 B
APB-DMA CH4 6002:1100 6002:113f 0002:1100 0002:113f 64 B
APB-DMA CH5 6002:1140 6002:117f 0002:1140 0002:117f 64 B
APB-DMA CH6 6002:1180 6002:11bf 0002:1180 0002:11bf 64 B
APB-DMA CH8 6002:1200 6002:123f 0002:1200 0002:123f 64 B
APB-DMA CH9 6002:1240 6002:127f 0002:1240 0002:127f 64 B
APB-DMA CH10 6002:1280 6002:12bf 0002:1280 0002:12bf 64 B
APB-DMA CH12 6002:1300 6002:133f 0002:1300 0002:133f 64 B
APB-DMA CH13 6002:1340 6002:137f 0002:1340 0002:137f 64 B
APB-DMA CH14 6002:1380 6002:13bf 0002:1380 0002:13bf 64 B
APB-DMA CH16 6002:1400 6002:143f 0002:1400 0002:143f 64 B
APB-DMA CH17 6002:1440 6002:147f 0002:1440 0002:147f 64 B
APB-DMA CH18 6002:1480 6002:14bf 0002:1480 0002:14bf 64 B
APB-DMA CH20 6002:1500 6002:153f 0002:1500 0002:153f 64 B
APB-DMA CH21 6002:1540 6002:157f 0002:1540 0002:157f 64 B
APB-DMA CH22 6002:1580 6002:15bf 0002:1580 0002:15bf 64 B
APB-DMA CH24 6002:1600 6002:163f 0002:1600 0002:163f 64 B
APB-DMA CH25 6002:1640 6002:167f 0002:1640 0002:167f 64 B
APB-DMA CH26 6002:1680 6002:16bf 0002:1680 0002:16bf 64 B
APB-DMA CH28 6002:1700 6002:173f 0002:1700 0002:173f 64 B
APB-DMA CH29 6002:1740 6002:177f 0002:1740 0002:177f 64 B
APB-DMA CH30 6002:1780 6002:17bf 0002:1780 0002:17bf 64 B
System Registers 6000:c000 6000:c2ff 0000:c000 0000:c2ff 768 B
AHB Arbitration + Gizmo Controller 0000:0000 0000:014f 336 B
AHB/APB Debug Bus 0000:0150 0000:01ff 176 B
Secure Boot 0000:0200 0000:02ff 256 B
STAT-MON 6000:c400 6000:c7ff 0000:c400 0000:c7ff 1 KB
Activity Monitor 6000:c800 6000:cbff 0000:c800 0000:cbff 1 KB
GPIO-1 6000:d000 6000:d0ff 0000:d000 0000:d0ff 256 B
GPIO-2 6000:d100 6000:d1ff 0000:d100 0000:d1ff 256 B
GPIO-3 6000:d200 6000:d2ff 0000:d200 0000:d2ff 256 B
GPIO-4 6000:d300 6000:d3ff 0000:d300 0000:d3ff 256 B
GPIO-5 6000:d400 6000:d4ff 0000:d400 0000:d4ff 256 B
GPIO-6 6000:d500 6000:d5ff 0000:d500 0000:d5ff 256 B
GPIO-7 6000:d600 6000:d6ff 0000:d600 0000:d6ff 256 B
GPIO-8 6000:d700 6000:d7ff 0000:d700 0000:d7ff 256 B
VCP 6000:e000 6000:efff 0000:e000 0000:efff 4 KB

Address Map
Exception vectors 6000:f000 6000:ffff 0000:f000 0000:ffff 4 KB
AVPUCQ 6001:0000 6001:00ff 0001:0000 0001:00ff 256 B
BSEA 6001:1000 6001:1fff 0001:1000 0001:1fff 4 KB
IPATCH 6001:dc00 6001:dfff 0001:dc00 0001:dfff 1 KB
VDE 6003:0000 6003:3fff 0003:0000 0003:3fff 16 KB
SXE 6003:0000 6003:0fff 0003:0000 0003:0fff 4 KB
BSEV 6003:1000 6003:1fff 0003:1000 0003:1fff 4 KB
MBE 6003:2000 6003:20ff 0003:2000 0003:20ff 256 B
PPE 6003:2200 6003:22ff 0003:2200 0003:22ff 256 B
MCE 6003:2400 6003:24ff 0003:2400 0003:24ff 256 B
TFE 6003:2600 6003:26ff 0003:2600 0003:26ff 256 B
PPB 6003:2800 6003:28ff 0003:2800 0003:28ff 256 B
VDMA 6003:2a00 6003:2aff 0003:2a00 0003:2aff 256 B
UCQ 6003:2c00 6003:2cff 0003:2c00 0003:2cff 256 B
FRAMEID 6003:3800 6003:3bff 0003:3800 0003:3bff 1 KB
APB 7000:0000 70ff:ffff 16 MB
MISC 7000:0000 7000:3fff 0000:0000 0000:3fff 16 KB
PP 0000:0000 0000:03ff 1 KB
SC1X_PADS 0000:0400 0000:07ff 1 KB
GP 0000:0800 0000:0bff 1 KB
SECURE_REGS 0000:0c00 0000:0cff 256 B
OBS 0000:0d00 0000:0dff 256 B
USB_AUX 0000:1000 0000:10ff 256 B
SATA_AUX 0000:1100 0000:11ff 256 B
PINMUX_AUX 0000:3000 0000:3fff 4 KB
UART-A 7000:6000 7000:603f 0000:6000 0000:603f 64 B
UART-B 7000:6040 7000:607f 0000:6040 0000:607f 64 B
VFIR 7000:6100 7000:61ff 0000:6100 0000:61ff 256 B
UART-C 7000:6200 7000:62ff 0000:6200 0000:62ff 256 B
UART-D 7000:6300 7000:63ff 0000:6300 0000:63ff 256 B
HDMI_IOBIST 7000:6500 7000:65ff 0000:6500 0000:65ff 256 B
MIPI_IOBIST 7000:6600 7000:66ff 0000:6600 0000:66ff 256 B
LPDDR2_IOBIST 7000:6700 7000:67ff 0000:6700 0000:67ff 256 B
PCIE_X2_0_IOBIST 7000:6800 7000:68ff 0000:6800 0000:68ff 256 B
PCIE_X2_1_IOBIST 7000:6900 7000:69ff 0000:6900 0000:69ff 256 B
PCIE_X4_IOBIST 7000:6a00 7000:6aff 0000:6a00 0000:6aff 256 B
SATA_IOBIST 7000:6c00 7000:6dff 0000:6c00 0000:6dff 512 B
XIO Interface 7000:8a00 7000:8bff 0000:8a00 0000:8bff 512 B
Sync NOR 7000:9000 7000:9fff 0000:9000 0000:9fff 4 KB
PWM Controller 7000:a000 7000:a0ff 0000:a000 0000:a0ff 256 B
MIPIHSI Baseband 7000:b000 7000:bfff 0000:b000 0000:bfff 4 KB
I2C 7000:c000 7000:c0ff 0000:c000 0000:c0ff 256 B
TWC 7000:c100 7000:c1ff 0000:c100 0000:c1ff 256 B
DTV 7000:c300 7000:c3ff 0000:c300 0000:c3ff 256 B
I2C2 7000:c400 7000:c4ff 0000:c400 0000:c4ff 256 B
I2C3 7000:c500 7000:c5ff 0000:c500 0000:c5ff 256 B

Address Map
OWR 7000:c600 7000:c6ff 0000:c600 0000:c6ff 256 B
I2C4 7000:c700 7000:c7ff 0000:c700 0000:c7ff 256 B
I2C5 7000:d000 7000:d0ff 0000:d000 0000:d0ff 256 B
I2C6 7000:d100 7000:d1ff 0000:d100 0000:d1ff 256 B
SPI 2B-1 7000:d400 7000:d5ff 0000:d400 0000:d5ff 512 B
SPI 2B-2 7000:d600 7000:d7ff 0000:d600 0000:d7ff 512 B
SPI 2B-3 7000:d800 7000:d9ff 0000:d800 0000:d9ff 512 B
SPI 2B-4 7000:da00 7000:dbff 0000:da00 0000:dbff 512 B
SPI 2B-5 7000:dc00 7000:ddff 0000:dc00 0000:ddff 512 B
SPI 2B-6 7000:de00 7000:dfff 0000:de00 0000:dfff 512 B
RTC 7000:e000 7000:e0ff 0000:e000 0000:e0ff 256 B
KBC 7000:e200 7000:e2ff 0000:e200 0000:e2ff 256 B
PMC 7000:e400 7000:ebff 0000:e400 0000:ebff 2 KB
FUSE 7000:f800 7000:fbff 0000:f800 0000:fbff 1 KB
KFUSE 7000:fc00 7000:ffff 0000:fc00 0000:ffff 1 KB
LA 7001:0000 7001:1fff 0001:0000 0001:1fff 8 KB
SE 7001:2000 7001:3fff 0001:2000 0001:3fff 8 KB
TSENSOR 7001:4000 7001:4fff 0001:4000 0001:4fff 4 KB
CEC 7001:5000 7001:5fff 0001:5000 0001:5fff 4 KB
ATOMICS 7001:6000 7001:7fff 0001:6000 0001:7fff 8 KB
MC 7001:9000 7001:9fff 0001:9000 0001:9fff 4 KB
EMC 7001:b000 7001:bfff 0001:b000 0001:bfff 4 KB
SATA 7002:0000 7002:ffff 0002:0000 0002:ffff 64 KB
HDA 7003:0000 7003:ffff 0003:0000 0003:ffff 64 KB
MIOBFM 7020:0000 7020:ffff 0020:0000 0020:ffff 64 KB
AUDIO_CLUSTER 7030:0000 7030:ffff 0030:0000 0030:ffff 64 KB
APBIF 0000:0000 0000:01ff 512 B
APBIF2 0000:0200 0000:07ff 1536 B
AUDIO 0000:0800 0000:0fff 2 KB
I2S0 0000:1000 0000:10ff 256 B
I2S1 0000:1100 0000:11ff 256 B
I2S2 0000:1200 0000:12ff 256 B
I2S3 0000:1300 0000:13ff 256 B
I2S4 0000:1400 0000:14ff 256 B
DAM0 0000:2000 0000:21ff 512 B
DAM1 0000:2200 0000:23ff 512 B
DAM2 0000:2400 0000:25ff 512 B
AMX0 0000:3000 0000:30ff 256 B
AMX1 0000:3100 0000:31ff 256 B
ADX0 0000:3800 0000:38ff 256 B
ADX1 0000:3900 0000:39ff 256 B
SPDIF 0000:6000 0000:60ff 256 B
AFC0 0000:7000 0000:70ff 256 B
AFC1 0000:7100 0000:71ff 256 B
AFC2 0000:7200 0000:72ff 256 B
AFC3 0000:7300 0000:73ff 256 B

Address Map
AFC4 0000:7400 0000:74ff 256 B
AFC5 0000:7500 0000:75ff 256 B
XUSB_PADCTL 7009:f000 7009:ffff 0009:f000 0009:ffff 4 KB
XUSB_HOST 7009:0000 7009:9fff 0009:0000 0009:9fff 40 KB
XUSB_DEV 700d:0000 700d:9fff 000d:0000 000d:9fff 40 KB
DDS 700a:0000 700a:11ff 000a:0000 000a:11ff 4608 B
SDMMC-1 700b:0000 700b:01ff 000b:0000 000b:01ff 512 B
SDMMC-1B 700b:1000 700b:11ff 000b:1000 000b:11ff 512 B
SDMMC-2 700b:0200 700b:03ff 000b:0200 000b:03ff 512 B
SDMMC-3 700b:0400 700b:05ff 000b:0400 000b:05ff 512 B
SDMMC-4 700b:0600 700b:07ff 000b:0600 000b:07ff 512 B
SPEEDO 700c:0000 700c:7fff 000c:0000 000c:7fff 32 KB
SPEEDO_0 0000:0000 0000:00ff 256 B
SPEEDO_1 0000:0100 0000:01ff 256 B
SPEEDO_PMON 700c:8000 700c:ffff 000c:8000 000c:ffff 32 KB
SPEEDO_PMON_0 0000:0000 0000:01ff 512 B
SPEEDO_PMON_1 0000:0200 0000:03ff 512 B
SYSCTR0 700f:0000 700f:ffff 000f:0000 000f:ffff 64 KB
SYSCTR1 7010:0000 7010:ffff 0010:0000 0010:ffff 64 KB
DP2 700e:0000 700e:00ff 000e:0000 000e:00ff 256 B
APB2JTAG 700e:1000 700e:11ff 000e:1000 000e:11ff 512 B
SOC_THERM 700e:2000 700e:2fff 000e:2000 000e:2fff 4 KB
MIPI_CAL 700e:3000 700e:30ff 000e:3000 000e:30ff 256 B
DVFS 7011:0000 7011:03ff 0011:0000 0011:03ff 1 KB
CLUSTER_CLOCK 7004:0000 7007:ffff 0004:0000 0007:ffff 256 KB
CSITE 7080:0000 709f:ffff 0080:0000 009f:ffff 2 MB
AHB_A2 7c00:0000 7dff:ffff 32 MB
PPCS (AHB to MC flush) 7c00:0000 7c00:ffff 0000:0000 0000:ffff 64 KB
TZRAM 7c01:0000 7c01:ffff 0001:0000 0001:ffff 64 KB
USB 7d00:0000 7d00:17ff 0100:0000 0100:17ff 6 KB
USB2 7d00:4000 7d00:57ff 0100:4000 0100:57ff 6 KB
USB3 7d00:8000 7d00:97ff 0100:8000 0100:97ff 6 KB
External Memory 8000:0000 27fff:ffff 8 GB
EMEM 8000:0000 27fff:ffff 0000:0000 1ffff:ffff 8 GB
IROM (boot code) 0010:0000 0010:ffff 64 KB
IROML 0010:0000 0010:ffff 64 KB
Lo-VEC 0000:0000 0000:ffff 64 KB
IROM_LOVEC 0000:0000 00ff:ffff 16 MB

Address Map
2.2 Available DRAM Address Ranges

®
Table 2 describes the various address regions that are available as DRAM in Tegra K1 devices.
The address map available varies by master, because MMIO is not available to any direct MC client except the processors.
These other direct MC clients are therefore able to access all DRAMs on 4GB systems, with the spaces reserved for MMIO on
the processors available to them as DRAM. This may be used as a carve-out or for similar purposes.
Note: MMIO in Table 2 below refers to the MMIO target, register, or non-DRAM region. Not all of
the MMIO regions actually have an MMIO target.
Physical/Virtual Address Range is available for Host1X clients for all apertures.
Table 2: DRAM Address Ranges

IOVA Range
Physical DRAM Range Available for:
Size H/W Config COP/ AHB
Aperture Range (MB) Option 2 GB 3GB 4 GB >4 GB AVP? Clients?
DRAM 8000_0000 - FFFF_FFFF 2048 Always DRAM DRAM DRAM DRAM DRAM Yes Yes
DRAM2 1_0000_0000 - 2_7FFF_FFFF 6144 Always DRAM N/A N/A N/A DRAM No No
+ + +
AHB_A2_rsvd 7E00_0000 - 7FFF_FFFF 32 Selectable DRAM DRAM DRAM DRAM Yes Yes
AHB_A2 7C00_0000 - 7DFF_FFFF 32 Always MMIO MMIO MMIO MMIO MMIO No No

+ + +
AHB_A1_rsvd 7900_0000 - 7BFF_FFFF 48 Selectable DRAM DRAM DRAM DRAM Yes Yes
AHB_A1 7800_0000 - 78FF_FFFF 16 Selectable MMIO MMIO MMIO MMIO No No

+ + +
APB_rsvd 7100_0000 - 77FF_FFFF 112 Selectable DRAM DRAM DRAM DRAM Yes Yes
APB 7000_0000 - 70FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No

+ + +
ExtIO_rsvd 6900_0000 - 6FFF_FFFF 112 Selectable DRAM DRAM DRAM DRAM Yes Yes
ExtIO 6800_0000 - 68FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No

+ + +
PPSB_rsvd 6100_0000 - 67FF_FFFF 112 Selectable DRAM DRAM DRAM DRAM Yes Yes
PPSB 6000_0000 - 60FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No
GART/GPU_GART 5700_0000 - 5FFF_FFFF 144 Always MMIO MMIO MMIO MMIO MMIO Yes Yes
Graphics Host rsvd + + +

5500_0000 - 56FF_FFFF 32 Selectable DRAM DRAM DRAM DRAM Yes Yes
(HOST1X_DR_RSVD)
Graphics Host
5400_0000 - 54FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No
(HOST1X_DR)
Verif Aper + Rsvd 5100_0000 - 53FF_FFFF 48 Selectable DRAM+ DRAM+ DRAM DRAM+ Yes Yes
1
Host1x+PERIPH 5000_0000 - 50FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO
Host1x 5000_0000 – 5002_7FFF 160KB Always MMIO MMIO MMIO MMIO MMIO No No
Host1X+ PERIPHBASE 5004_0000 - 5005_FFFF 128KB Always MMIO MMIO MMIO MMIO MMIO No Yes
PERIPH
MSELECT 5006_0000 - 5006_0FFF 4KB Always MMIO MMIO MMIO MMIO MMIO No Yes
DRAM/ DRAM/ DRAM/ DRAM/ Yes if no Yes if no

NOR_A3 4B00_0000 - 4FFF_FFFF 80 Selectable
MMIO MMIO MMIO MMIO NOR. NOR.
NOR_A2 4900_0000 - 4AFF_FFFF 32 Selectable
NOR_A1 4800_0000 - 48FF_FFFF 16 Selectable
IRAM_rsvd 4100_0000 - 47FF_FFFF 112 Selectable DRAM+ DRAM+ DRAM DRAM+ Yes Yes
1
The Host1X+PERIPH is split into multiple apertures.
Address Map
IOVA Range
Physical DRAM Range Available for:
Size H/W Config COP/ AHB
Aperture Range (MB) Option 2 GB 3GB 4 GB >4 GB AVP? Clients?
IRAM 4000_0000 - 40FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No
DRAM/ DRAM/ DRAM/ DRAM/

PCIE_A3 1000_0000 - 3FFF_FFFF 768 Selectable Yes Yes
MMIO MMIO MMIO MMIO
PCIE_A2 0200_0000 - 0FFF_FFFF 224 Selectable Yes Yes
MMIO MMIO MMIO MMIO
PCIE_A1 0100_0000 - 01FF_FFFF 16 Selectable Yes Yes
MMIO MMIO MMIO MMIO
IROM_LOVEC 0000_0000 - 00FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No
Notes:
 The IOVA Range column is available for AVP or AHB clients that have SMMU translation enabled or PA address for
AHB clients that have SMMU translation disabled.
 “DRAM” really means “Memory Controller”. In particular:
 The GART range (5700_0000 – 5FFF_FFFF) has been used as an SMMU bounce range, which through the
SMMU points to DRAM.
 If the system configuration includes a PCIe device, then the PCIE_A* regions need to be configured as MMIO
(appropriately as required by address space requirement). If the system does not include any PCIe devices, then
these regions should be configured as DRAM.
 All configurable regions that do not have a real MMIO target (labeled as DRAM+) in the above table should be
configured as DRAM to provide the largest and uniform IOVA view (in 2GB or 4GB system) for the AVP and
other clients that generate virtual addresses to access DRAM.
 Requests from all clients (except the main CPU) are allowed to use SMMU translation. Any request address range
that can reach the MC can be translated by the SMMU.
 SMMU is a sub-unit in the memory controller. Address ranges marked as "No" in the table will not reach the memory
controller.
 All Host1x clients can see the full 4GB physical or IOVA range.

Address Map
Clients/Controllers are logically (static) grouped in different SWNAME/SWID. SMMU translation can be enabled/disabled for
individual SWNAME. The following table gives the Client to SW Name mapping details.
Table 3: Client to SW Name Mapping
SW Group Client Description

AFI AFI PCIe reads
AVPC AVP Cache ARM7 Audio-Video Processor (AVP)
DC Display Display reads, window A, window C, window D, window T, cursor
DCB Displayb Display reads, window B, window C, cursor
GPU GPU Kepler GPU, 3D engine
HC Host1x Host interface
HDA HDA High-definition Audio engine
ISP2 ISP2 Image Signal Processor, instance a
ISP2B ISP2B Image Signal Processor, instance b
MPCORE AXICIF Cortex-A15 CPU cores, writes
MPCORELP AXICIF_LP Cortex-A15 Shadow CPU core, writes
MSENC MSENC Multi Standard Video Encoder
PPCS AHBDMA, AHBSLV Clients in the AHB cluster (ppcs2mc_swid=1'b0)
PPCS1 AHBDMA, AHBSLV Same as PPCS, ppcs2mc_swid=1'b0)
PPCS2 AHBDMA, AHBSLV Same as PPCS, ppcs2mc_swid=1'b0)
PTC MC (SMMU) Misses from SMMU PTC
SATA SATA Serial ATA
SDMMC1a SDMMCA SDMMC1
SDMMC2a SDMMCAA SDMMC2
SDMMC3a SDMMC SDMMC3
SDMMC4a SDMMCAB SDMMC4
TSEC TSEC Tegra Security coprocessor
VDE VDE Video Decode Engine
VI VI2 Video Input engine for CSI
VIC VIC Video Image Compositer
XUSB_HOST USB3 Host
Although the same driver is expected to control both units, each has its own SWNAME
XUSB_DEV USB3 Device
Note: Requests from all clients (except main CPU) are allowed to use SMMU translation. Any
request address range that can reach the MC can be translated by the SMMU.

Address Map
The clients behind AHBSLV in the above table are:
 VCP
 CSITE
 ARC
 AHBDMA
 USB
 APBDMA
 SNOR
 BSEV
 SE
 DDS
 BSEA
 USB2
 MIPIHSI
Each client in the above list has a SWID register field which controls whether the client maps to PPCS or PPCS1 SWNAME.

3.0 INTERRUPT CONTROLLER

®
This section provides the mapping and hierarchical groups of the Tegra K1 family processor interrupts. It also describes the
architecture for routing and handling of these interrupts. It describes semaphores, which provide a mechanism for the
processors to arbitrate for the use of various resources.
From the perspective of interrupts: devices (GPU, Memory Controller, Video encode/decode engines, and various I/O devices)
are the sources of interrupts; and processors are the target of interrupts. From sources, interrupts go to interrupt controllers
which, based on configuration, prioritize and route them to the appropriate target processor. There are two different types of
®
interrupt controllers used in Tegra K1 devices: The ARM vGIC and the Legacy Interrupt Controller (LIC).
Glossary and Acronyms

Acronym Description
COP Refers to ARM7™ AVP
CPU Unless specified otherwise, refers to CPU complex
FIQ Fast Interrupt Request
GIC Also known as vGIC, see below
IPI Inter Processor Interrupt
IRQ Interrupt Request
LIC Legacy Interrupt Controller (used for the ARM7 AVP)
MSI Message Signaled Interrupt
PPI Private Peripheral Interrupts
SGI Software Generated Interrupt
SMP Symmetric MultiProcessors
SPI Shared Peripheral Interrupts
vGIC Virtual GIC (also known as GICv2, part of the CPU complex)
WFE Wait For Event (an ARM instruction)
WFI Wait For Interrupt (an ARM instruction)
3.1 References
Some ARM documentation is required to fully understand the Tegra interrupt architecture. Refer to ARM’s website for further
details and to access these.
Document Description
vGIC Architecture ARM Virtual Generic Interrupt Controller (also known as GIC v2) Architectural Specification
Timers Architecture ARM Generic Timer Architectural Specification
Cortex-A15 TRM Cortex-A15 Technical Reference Manual for Cortex-A15 implementation specific information
(Tegra K1 32-bit).
ARM Technical Reference For implementation specific information (Tegra K1 64-bit)
Manual v8
3.2 Interrupt Mapping

The following five tables show the mapping of the interrupts from system devices to the bit fields in the Tegra K1 interrupt
controllers.
Interrupts to the CPU’s embedded interrupt controller (vGIC) are in this same order, but start at offset 32 because the first 32
are reserved for the CPU’s internal interrupts.

Interrupt Controller
Table 4: Primary Interrupt Controller (PRI_ICTRL) Mapping

Global LIC
Interrupt Interrupt Interrupt Source Interrupt
Number Target Number Interrupt Name Block Interrupt Description Order
31 31 SDMMC4 SDMMC SDMMC4 Controller 0
30 30 OWR OWR OWR Interrupt 0
29 CPU 29 ARB_SEM_GNT_CPU Semaphore GNT.0 Arbitration Grant Status of CPU 0
28 COP 28 ARB_SEM_GNT_COP Semaphore GNT.1 Arbitration Grant Status of COP 0
27 CPU 27 AHB_DMA_CPU AHB_DMA AHB DMA Controller (CPU) 0
26 CPU 26 APB_DMA_CPU APB_DMA APB Bridge DMA Controller (CPU) 0
25 25 VCP VCP VCP 0
24 24 Unmapped Unassigned 0
23 23 SATA_CTL SATA SATA Controller Interrupt 0
21 21 USB2 USB USB Device 0
20 20 USB USB USB Device 0
18 18 AVP_UCQ AVP_UCQ AVP UCQ Interrupt 0
17 17 VDE VDE VDE Interrupt 0
13 13 SATA_RX_STAT SATA SATA RX Wake Up Interrupt 1
12 12 VDE_SXE VDE VDE SXE Interrupt 3
11 11 VDE_BSEA VDE AVP BSEA Interrupt 0
10 10 VDE_BSEV VDE VDE BSE-V Interrupt 1
9 9 VDE_SYNC_TOKEN VDE VDE Sync Token Interrupt 0
8 8 VDE_UCQ VDE VDE UCQ Error Interrupt 4
SHR_SEM_OUTBOX_
7 CPU 7 EMPTY Semaphore CPU Outbox Empty Interrupt 3
6 COP 6 SHR_SEM_OUTBOX_FULL Semaphore COP Outbox Full Interrupt 2
5 COP 5 SHR_SEM_INBOX_EMPTY Semaphore COP Inbox Empty Interrupt 1
4 CPU 4 SHR_SEM_INBOX_FULL Semaphore CPU Inbox Full Interrupt 0
3 3 CEC CEC CEC General Interrupt 0
2 2 RTC RTC RTC Interrupt 0
1 1 TMR2 Timer TMR2 Interrupt 0
Table 5: Secondary Interrupt Controller (SEC_ICTLR) Mapping

Global LIC
Interrupt Interrupt Interrupt Interrupt
Number Target Number Interrupt Name Source Block Interrupt Description Order
63 31 I2C6 I2C I2C6 Interrupt 0
62 30 CLDVFS CL-DVFS Close Loop DVFS control logic 0
61 COP 29 AHB_DMA_COP AHB_DMA AHB-DMA Interrupt (COP) 1
60 COP 28 APB_DMA_COP APB_DMA APB-DMA Interrupt (COP) 1
59 27 SPI1 SPI SPI Controller (SBC1) 0
58 26 SE SE SE and TZRAM General Interrupt 0
57 25 USB3_DEV_PME USB3 USB3_DEV_PME 0

Global LIC
56 24 USB3_DEV_SMI USB3 USB3_DEV_SMI 0
55 23 GPIO5 GPIO (external) GPIO4 Interrupt 0
54 22 STAT_MON sts_stat_mon SYS_STATS_MON 0
52 20 VFIR VFIR VFIR Controller 0

EDP (Electrical Design Power)
51 19 EDP SOC_THERM interrupt 0
50 18 TSEC TSEC Tegra HDCP Security Controller 0
49 17 XUSB_PADCTL XUSB_PADCTL Unassigned 0
48 16 THERMAL SOC_THERM SOC Thermal interrupt 0
47 15 HSI HSI MIPI HSI Baseband Controller 0
46 14 UARTC UART UART-C 0
45 13 ACTMON ActMon ACTMON 0
44 12 USB3_DEV_HOST USB3 USB3_DEV_HOST 1
43 11 USB3_HOST_PME USB3 USB3_HOST_PME 0
40 8 USB3_HOST_SMI USB3 USB3_HOST_SMI 0
39 7 USB3_HOST_INT USB3 USB3_HOST_INT 0
38 6 I2C I2C I2C Interrupt 0
37 5 UARTB UART UART-B 0
36 4 UARTA UART UART-A 0
Table 6: Tertiary Interrupt Controller (TRI_ICTLR) Mapping

Global LIC
95 31 SW_INTR N/A (Software) SW Controlled Interrupt 0
90 26 UARTD UART UART-D 0

External Power Management Chip
86 22 PMU_EXT PMIC Interrupt 0

Global LIC
81 17 HDA HDA HDA Interrupt 0
79 15 SPI6 SPI SPI Controller 0
78 14 EMC EMC EMC General Interrupt 0
77 13 MC MC MC General Interrupt 0
76 12 SOR SOR (Display) SOR (eDP/LVDS) General Interrupt 0
75 11 HDMI HDMI HDMI INT from pins 0
74 10 DISPLAYB DISPLAYB Display B General Interrupt 0
73 9 DISPLAY DISPLAY Display A General Interrupt 0

Video Image Compositer General
72 8 VIC VIC Interrupt 0
71 7 ISP ISP ISP General Interrupt 0
70 6 ISPB ISPB ISPB General Interrupt 0
69 5 VI VI VI General Interrupt 0
68 4 MSENC MSENC MSENC General Interrupt 0
67 CPU 3 HOST1X_GEN_CPU HOST1X CPU General Interrupt 3
66 COP1 2 HOST1X_GEN_COP HOST1X COP General Interrupt 2

HOST1X_SYNCPT_
65 CPU 1 CPU HOST1X CPU SyncPt Interrupt 1
HOST1X_SYNCPT_
64 COP1 0 COP HOST1X COP SyncPt Interrupt 0
Table 7: Quaternary Interrupt Controller (QUAD_CTLR) Mapping

Global LIC
Number Target Number Interrupt Name Source Block Description Order
HIER_GROUP1_ CPU interrupt from hierarchical
127 31 CPU HIER_GROUP1 group1. 0
126 30 CAR CAR CAR Interrupt 0
124 28 WDT_AVP Timer Watchdog AVP Interrupt 2
123 27 WDT_CPU Timer Watchdog CPU Interrupt 1

HIER_GROUP1_ COP interrupt from hierarchical
HIER_GROUP1
122 26 COP group1. 0
119 23 APB_DMA_CH15 APB_DMA APB-DMA Channel 15 0

Global LIC
Number Target Number Interrupt Name Source Block Description Order

AUDIO_
103 7 AUDIO_CLUSTER CLUSTER Audio Cluster Interrupt 0
101 5 AVP_CACHE ARM7 Cache ARM7 Cache Interrupt 0
100 4 PCIE_WAKE PCIe PCIe wake-up signal 0
99 3 PCIE_MSI PCIe PCIe message signaled interrupt 0
98 2 PCIE_INT PCIe PCIe catch-all error/legacy interrupts 0
97 1 USB3 USB USB Device 0
96 0 SNOR SNOR Sync NOR Controller 0
Table 8: Fifth Interrupt Controller (PENTA_ICTLR) Mapping

Global LIC
159 31 ARDPAUX DPAUX ARDPAUX General Interrupt 0

GPU_NONSTALL_
158 30 INT GPU GPU Interrupt 0
157 29 GPU_INT GPU GPU Interrupt 0

SDMMC4 interrupt for standard driver
151 23 SDMMC4_SYS SDMMC (e.g., WOA) 0
CPU3 Performance Management Unit
147 19 CPU3_PMU_INTR A15 CPU3 (PMU) Interrupt 0
146 18 CPU2_PMU_INTR A15 CPU2 CPU2 PMU Interrupt 0

Global LIC
3.3 Hierarchical Groups

The following table is a hierarchical interrupt grouping which generates interrupts for the first level of interrupt controllers.
Table 9: Hierarchical Interrupt Grouping
Hierarchical Interrupt Interrupt

Controller Name Number Interrupt Name Source Block Interrupt Description
HIER_GROUP1 31 - 16 Currently Unmapped Currently Unassigned
HIER_GROUP1 15 MselectError Unassigned
HIER_GROUP1 14 MPCORE_CTIIRQ3 CPU3 CTI interrupt
HIER_GROUP1 10 TMR_SHARED Timer TMR_SHARED interrupt
HIER_GROUP1 9 FLOW_RSM_COP FlowCtlr FLOW - RSM1 Resume for COP or COP1
HIER_GROUP1 8 FLOW_RSM_CPU FlowCtlr FLOW - RSM0 Resume for CPU
HIER_GROUP1 7 Currently Unmapped Currently Unassigned
HIER_GROUP1 6 Currently Unmapped Currently Unassigned
HIER_GROUP1 5 EVENT_GPIO_D GPIO (External) Event Detector GPIO Port D
HIER_GROUP1 4 EVENT_GPIO_C GPIO (External) Event Detector GPIO Port C
HIER_GROUP1 3 EVENT_GPIO_B GPIO (External) Event Detector GPIO Port B
HIER_GROUP1 2 EVENT_GPIO_A GPIO (External) Event Detector GPIO Port A
HIER_GROUP1 1 MPCORE_INTERRIRQ CCPLEX CPU INTERRIRQ
HIER_GROUP1 0 MPCORE_AXIERRIRQ CCPLEX CPU AXIERRIRQ
3.4 Functional Description
3.4.1 Interrupt Handling Mechanism

The two different types of interrupt controllers (vGIC, and LIC) receive interrupts from devices (i.e., hardware interrupts also
known as SPIs) or processors (i.e., software interrupts including IPI), arbitrate them, and send them to the appropriate target
processor(s). From an interrupt perspective, there are two different types of processors: CPUs (Cortex-A15) and COP (ARM7
AVP). The vGIC is the interrupt controller for the CPUs, and the LIC is the interrupt controller for the ARM7 AVP. Any
processor can initiate a software interrupt, targeted to any one or more processors (including itself). However, IPIs can only be
initiated by a Cortex-A15 CPU to any one or more Cortex-A15 CPUs (including itself).
There are 160 hardware interrupts in Tegra K1 devices. Interrupt sources are allocated one or more interrupts as required.
The 160 interrupts are grouped into slices of 32, where each slice can be configured independently.
3.4.1.1 ARM Processors’ IRQ and FIQ

ARM processors (Cortex-A15, and ARM7) each have two input pins to receive two different types of interrupts. These
interrupts are called IRQ (Interrupt Request) and FIQ (Fast Interrupt Request). The interrupts are implemented as active-low
pins on the ARM processor input; thus the processor pins are named nIRQ and nFIQ.
The ARM processor goes into the IRQ mode or the FIQ mode depending up on which interrupt is activated. Generally,
interrupts that require low latency or are time critical are configured as FIQ. All other interrupts are configured as IRQ. Non-
secure interrupts can only be IRQ.
3.4.1.2 Interrupt Controllers

The interrupt controller receives interrupts from a large number of sources. The interrupt sources can be assigned a target
processor, a type (IRQ versus FIQ), priority levels, etc., by configuring interrupt-controller registers. The interrupt controller
arbitrates among different incoming interrupts and sends the interrupt to the nIRQ or nFIQ pin of the targeted processor.
In general, any incoming hardware interrupt can be routed to either nIRQ or nFIQ pin of any of the processors.
The Legacy Interrupt Controller (LIC) is primarily used for COP (ARM7). But it is also used for generating interrupts as wake
events for CPUs. All of the device hardware interrupt signals are sent to the LIC first, which routes them to the ARM7 AVP as
well as forwards them to other interrupt controller. The LIC also provides a software set/clear mechanism for all of the
interrupts.
The interrupt controller used for CPUs (Cortex-A15 CPUs) is called vGIC (virtual generic interrupt controller). The vGIC is an
SMP interrupt controller. It receives interrupts targeted to any one or more of the CPUs in the SMP complex. There is one
vGIC per CPU cluster.
3.4.1.3 vGIC Interrupt Sources

The vGIC supports 256 interrupts. All interrupts are identified by a unique ID. There are three types of interrupt sources for the
vGIC: SGIs, PPIs, and SPIs.
Software Generated Interrupts (SGIs)

SGIs are software interrupts which are generated by writing to a vGIC register. Software can generate a maximum of 16 SGIs,
with ID0-15. The SGIs are also referred to as IPIs (Inter Processor Interrupts).
Private Peripheral Interrupts (PPIs)

PPIs are interrupts generated by a peripheral that is specific to a single processor.
There are seven PPIs for each CPU: virtual maintenance interrupt (ID25), hypervisor timer interrupt (ID26), virtual timer
interrupt (ID27), legacy nFIQ (ID28), secure physical timer interrupt (ID29), non-secure physical timer interrupt (ID30), and
legacy nIRQ (ID31).
Tegra K1 devices use all PPIs except for the legacy nFIQ and legacy nIRQ.

Shared Peripheral Interrupts (SPIs)

SPIs are external hardware interrupts which are generated by asserting signals on vGIC input pins (called IRQs). From a
Tegra hardware perspective, these are the interrupts which are generated by various units to be sent to interrupt controllers.
Tegra K1 devices use 160 of the possible 224 SPIs generated through the IRQS[223:0] pins. SPIs start at ID32. Tegra K1
devices use level-sensitive SPIs only.
3.4.1.4 Interrupt Routing

Tegra hardware interrupts (also known as shared peripheral interrupts) can be generated either by internal SoC units, external
®
events (through GPIO, USB, etc.), or PCIe unit (MSI, legacy INTx, or Wake interrupts). All of these hardware interrupts are
routed through sideband active-high level-sensitive signals to the LIC. The MSI and INTx (from external PCIe devices) are
intercepted by the PCIe unit and converted to a sideband interrupt signal. The PCIe unit ensures MSI ordering; that is, it
ensures that upstream writes ahead of MSI have been completed/acknowledged before asserting an interrupt signal to the
LIC. Also, the PCIe unit captures MSI information into a register that software can read to identify MSI vectors, etc.
Figure 2: Interrupt Routing (Top-Level View) for Tegra K1 32-Bit
ARM-IP
Cluster0 Cluster1
CPU4
CPU0 CPU1 CPU2 CPU3
(shadow)
To
FlowCtlr
nvirq0/nvfiq0 nvirq1/nvfiq1 nvirq2/nvfiq2 nvirq3/nvfiq3 RegBus nvirq0/nvfiq0

RegBus
vGIC vGIC
PCPU0 I/F PCPU1 I/F PCPU2 I/F PCPU3 I/F CPU0 I/F
VCPU0 I/F VCPU1 I/F VCPU2 I/F VCPU3 I/F VCPU0 I/F
Distributor Distributor
irqs[159:0]
4 Timer PPIs per CPU (P-Secure, P-non- irqs[159:0] Timers
Secure, V-non-Secure, P-Hyper)
irqs[31:0] irqs[63:32] irqs[95:64] irqs[127:96] irqs[159:128]
Legacy
Interrupt
Ctlr cop_nirq,
cop_nfiq ARM7
PRI_IC SEC_IC TRI_IC QUAD_IC PENTA_IC Combiner
cpu_irq[3:0],
cpu_irq[3:0]
int[31:0] int[63:32] int[95:64] int[127:96] int[159:128]

To
FlowCtlr
int[159:0]*
External Interrupts MSI + INTx 10 Timers

Internal Interrupts 8 ints (5 TMR, 1
* All source to interrupt-controller interrupt-
(GPIO, PMU, Interrupts
(Units) TMR_shared, 2 WDT) signals are level-sensitive (active high).
WakeEvents) (PCIE RP)
As shown in the figure above, hardware interrupts are routed to the interrupt controllers (called IC32) within the LIC, where
each IC32 handles 32 interrupts. The interrupt signals are synchronized within the LIC to the system clock. The synchronized
signals are combined with software set/clear bits per interrupt. This allows software to set or clear individual interrupts,

provided the corresponding interrupt is not asserted by hardware. The resulting interrupt signals are broadcast to the LIC (for
further processing) and the vGIC. Within the LIC and vGIC, per interrupt and per CPU enable-masks are configured to qualify
the interrupt targeted for the corresponding processor. This mechanism allows any interrupt to be targeted to any one or more
processors in Tegra K1 devices.
For details on interrupt handling within the LIC and vGIC, refer to the following sections.
3.4.1.5 Interrupt Handling with Targeted CPU and vGIC Powered Off
When a CPU and associated vGIC are powered off (e.g., the CPU rail is powered off for cluster0), then the legacy interrupt
controller is configured to act as a “proxy” interrupt controller to generate IRQ/FIQ for that CPU. Also, Tegra K1 timers (instead
of vGIC timers) have to be set up if a timer interrupt is required. The flow controller uses legacy interrupt controller IRQ/FIQ to
power-up the targeted CPU (and vGIC).
The following sequence describes the steps to follow to handle interrupts when the targeted CPU and vGIC are powered off:
 [SW-CPU] Prepare the CPU (including vGIC) for power off

- Flush caches and save context
- Set up the Tegra timer (if required)
- Configure the corresponding legacy interrupt controller
- Configure the flow controller for an interrupt (from the flow controller) wake-up event
- Trigger power-off by WFI/WFE instruction
 [HW-Flow] Power off the CPU with the help of the PMC
 [HW-Flow] Wait for a wake-up interrupt (from the legacy interrupt controller)
 [HW-Flow] At interrupt assertion, power up the CPU with the help of the PMC
 [SW-CPU] Restore the context (including vGIC context)
 [SW-CPU] The CPU receives the interrupt and jumps to the interrupt handler
Because Tegra interrupts are level-triggered, the interrupt that triggered the wake-up is still asserted and is now visible to the
vGIC. The vGIC will process the interrupt and send it to the CPU.
3.4.1.6 Interrupt Handling with Targeted CPU Powered Off

Each CPU can be individually powered off while the corresponding vGIC is powered on. In this case, the flow controller uses
vGIC interrupts to wake up the CPU. This allows vGIC timers and IPI interrupts to be used as wake events.
The following sequence describes the steps to follow to handle interrupts when the targeted CPU is powered off:
 [SW-CPU] Prepare the CPU for power off

- Flush caches and save context
- Configure the flow controller for an interrupt (from the vGIC) wake-up event
- Trigger power-off by WFI/WFE instruction
 [HW-Flow] Power off the CPU with the help of the PMC
 [HW-Flow] Wait for a wake-up interrupt (from the vGIC)
 [HW-Flow] At interrupt assertion, power up the CPU with the help of the PMC
 [SW-CPU] Restore the context
 [SW-CPU] The CPU receives the interrupt and jumps to the interrupt handler
Because the vGIC IRQ and FIQ are level-triggered, the interrupt that triggered the wake-up is still asserted.

3.4.2 Virtual Generic Interrupt Controller (Tegra K1 32-Bit)

This section describes the Cortex-A15 vGIC (also known as GICv2). Refer to the ARM Cortex-A15 TRM for the vGIC
implementation specific specification and/or the ARM vGIC architectural specification.
The vGIC consists of the physical CPU interface and the physical distributor. In addition, to support CPU virtualization it
consists of the virtual CPU Interface which is configured by the Hypervisor and used by the virtual machine (VM).
3.4.2.1 Functional Description
Split EOI Functionality

Every interrupt has a priority, and any interrupt being active will prevent another interrupt of equal (or lower) priority from being
asserted to the CPU. This causes problems for virtualization where there is not necessarily any well-defined priority for
interrupts between the various VMs. To address this problem the functionality associated with EOI is divided into two distinct
functions:
 Priority Drop to be used after the interrupt is acknowledged to drop the running priority of the CPU back down but
leave the interrupt in the ACTIVE state
 Deactivate Interrupt to be used when the interrupt handling is truly completed by the VM, causing the interrupt to
transition from ACTIVE to INACTIVE in the physical distributor.
To avoid Hypervisor intervention being necessary when a Guest OS completes interrupt processing, the virtual CPU Interface
is able to directly trigger a Deactivate Interrupt event on the interrupt distributor.
Virtual CPU Interface

The Virtual CPU Interface supports CPU virtualization.
The Virtual CPU Interface provides two sets of registers for each CPU in the system. The “front-end” registers are intended to
be mapped into the VM’s IPA space where the Guest OS’ CPU Interface registers are expected to reside. The “back-end”
registers are intended to be accessed by the Hypervisor only. The front-end and back-end registers are mapped into separate
4KB address spaces. The back-end registers primarily comprise a list of active and pending interrupts for the current Virtual
CPU. These registers are updated by the Hypervisor when new interrupts occur, and by the VCPUIF itself in response to
accesses to the front end from the VM.
Security and Virtual FIQ

In ARM virtualization, Hypervisor and all VMs run in the TrustZone™ Non-Secure domain. Therefore, all vGIC features are
available to Non-Secure accesses. Protection of the Hypervisor view of the Virtual CPU Interface is achieved using MMU
protection. However, some operating systems running as Guests might require the security features of the GIC architecture to
allow interrupts to be divided into IRQ and FIQ. To support this, the Hypervisor and Virtual CPU Interface provide a view
compatible with the Secure view of the physical GIC, even though the software is running in the Non-Secure domain. This
means that the GIC interface includes various security-related bits that have no relationship to TrustZone but exist purely to
support this model.
Interrupt Processing in the vGIC

 Physical Interrupt Asserted
The physical interrupt is routed to the vGIC, which generates an interrupt that is taken by the Hypervisor. The
Hypervisor reads INTACK on the physical vGIC to determine the interrupt number. Determining that the interrupt is
destined for a virtual machine, the EOI register is written to prevent further interrupts being masked by the vGIC.
Hypervisor locates an empty list register (in the target VM’s virtual CPU interface) and writes a new value indicating
that this is a Valid interrupt in PENDING state, with the physical and virtual interrupt numbers and its priority as
assigned by the VM.
 Virtual Interrupt Asserted

Upon the write to the list register, the VCPU interface will re-evaluate whether to assert the Virtual IRQ signal, based
on the priority of the interrupt, any currently active interrupts, and the current setting of the Priority Mask register.
Assuming these conditions are met, the Virtual Interrupt signal will be asserted. When the CPU returns to the virtual
machine (with the CPSR.I bit clear), the Virtual Interrupt will be taken triggering a jump to the normal IRQ vector.
 Virtual Interrupt Acknowledged
The Guest OS’s interrupt handler will access the VCPU Interface’s INTACK register. In response to this, the VCPU
interface determines the highest priority PENDING interrupt stored in the list. Its priority is checked against the Active
Priorities register and the Priority Mask register. Assuming that the pending interrupt’s priority is higher, its virtual
interrupt number is returned, its status in the list register changed to ACTIVE, and the corresponding bit in the Active
Priorities register is set. Otherwise, the spurious interrupt value is returned. Once the Guest OS has received the
virtual interrupt number it is able to execute interrupt processing exactly as it would if it were running on bare
hardware with a real GIC.
 Virtual Interrupt EOI
Once interrupt processing is complete, the Guest OS writes to the EOI register on the VCPU interface to indicate
completion. In response, the VCPU interface determines the highest priority ACTIVE interrupt from the list registers,
and the highest priority set bit in the Active Priorities register. This highest priority set bit is cleared. Assuming a
highest priority ACTIVE interrupt was found, a Deactivate Interrupt signal is sent to the Interrupt Distributor specifying
the physical interrupt number from the list register. The list register is updated to indicate that the entry is now empty
(INVALID).
Timers
The Cortex-A15 processor provides a set of four timers for each processor in the cluster:
 A Secure Physical Timer and a Non-Secure Physical Timer for use in Secure and Non-secure PL1 modes,
respectively. These are generated as two separate interrupts to the core: ID29 (secure) and ID30 (non-secure).
 Virtual Timer for use in Non-secure PL1 modes.
 Physical Timer for use in Hypervisor mode.
The counter value is distributed to the processor with a synchronous binary encoded 64-bit bus, CNTVALUEB[63:0]. Within
each processor, a set of Timer registers are allocated to the CP15 coprocessor space.
For more information, see the Timers section in this TRM and the ARM Architecture Reference Manual v7 for generic timer
specifications.
3.4.2.2 vGIC Clock Frequency

The vGIC can operate at any integer multiple that is slower than the main Cortex-A15 CPU clock (CLK) using the
PERIPHCLKEN signal. For example, the CLK to internal vGIC clock frequency ratio can be 2:1 or 3:1. PERIPHCLKEN is
asserted one CLK cycle prior to the rising edge of the internal IC clock. The CLK to internal vGIC clock frequency ratio can be
changed dynamically using PERIPHCLKEN.
Both CPU clusters (cluster0 and cluster1) incorporate their own vGIC. The vGIC runs at half the CPU CLK frequency of the
cluster it is in.
3.4.2.3 vGIC Context Save/Restore

The vGIC and timers are part of the Cortex-A15 non-CPU (also known as L2) logic. The cluster0 vGIC is powered by the CPU
rail, and cluster1 is powered by the SoC rail. Also, if non-CPU is power gated then vGIC is power gated as part of non-CPU
partition.
In general, the vGIC context needs to be saved/restored in following cases.

 When CPU(s) is individually power gated (i.e., LP2 power state), the vGIC is still powered, so the vGIC context does
not have to be saved/restored. Therefore, CPUs can be individually powered-off (that is, put into the LP2 state) and
powered on without saving/restoring their vGIC context.
 When the non-CPU partition is power-gated or the CPU rail is powered off, the context of the corresponding vGIC
needs to be saved.
 When one cluster is migrated to the other cluster, the VGIC context needs to be migrated from the source cluster to
the destination cluster.
 When the SoC rail is powered off (that is, LP0 power state), the vGIC is powered off. Thus the vGIC has to be
configured/restored at LP0 exit (warm boot)
 When using the virtualization extension of the vGIC, for switching from one VM to another, Hypervisor will save the
contents of all the back-end registers (i.e., VM view of VCPU Interface registers) from the outgoing VM and load them
into the registers for the incoming VM. This restores the VCPU interface to the correct state for the incoming VM.
When a VCPU is migrated (context switched) to another physical CPU, the software has to save the contents of all
the back-end registers (that is, the VM view of the VCPU Interface registers) associated with the outgoing CPU, and
load them into the corresponding registers of the incoming CPU.
3.4.3 Legacy Interrupt Controller (LIC)

Interrupts from various Tegra K1 units are routed to the LIC. The LIC consists of five interrupt controllers (called IC32); each
IC32 handles 32 interrupts (for a total of 160 interrupts). Each IC32 generates five sets of IRQ/FIQ interrupts: one for COP
(ARM7) and the other ones for CPU<3:0>. The interrupts for CPU<3:0> are used by the flow controller only for wake events.

Figure 3: Legacy Interrupt Controller Block Diagram

To vGIC
Legacy Interrupt Controller

(IC32 --- PRI_IC)
SEC_IC
TRI_IC
QUAD_IC
(PRI_ICTLR_COP_IEP_CLASS)
Per Interrupt Enable (PRI_ICTLR_COP_IER)
OR of all interrupts
(PRI_ICTLR_CPU_IEP_CLASS)
Per Interrupt Enable (PRI_ICTLR_CPU_IER)
PENTA_IC
OR of all interupt
& ~FIQ
& FIQ
COPnIRQ
<3:0>
(LIC CPU interrupts are not used)
32b
Combiner
Combiner
cpu_nirq[3:0] cop_nirq
Flow ARM7
(PRI_ICTLR_COP_IEP_CLASS)
cpu_nfiq[3:0] cop_nfiq
Controller (PRI_ICTLR_CPU_IEP_CLASS)
& FIQ
& ~FIQ
COPnFIQ
<3:0>
Software set/clear (PRI_ICTLR_FIR*)
Interrupt status (PRI_ICTLR_ISR register)
Signal Synchronization (sync2d)
Interrupt Sources (Units)
The following text discusses interrupts as they relate to the COP IRQ/FIQ interrupts. Unless specified otherwise, this also
applies to the CPU<3:0> IRQ/FIQ interrupts.
3.4.3.1 LIC Functional Description

Each IC32 in the LIC handles 32 interrupts. As shown in above figure, the IC32 synchronizes the incoming hardware interrupt
requests and combines (bitwise OR) them with software interrupts (FIR). The software interrupt can set be set or cleared by
the FIR register. The combined software/hardware interrupt signals are broadcast to the vGIC, and are used by the IC32 for
targeting interrupts to the COP. This allows any interrupt to be routed to any one or more processors (Cortex-A15/ ARM7) in a
Tegra system. Note that routing can be changed dynamically. In addition, any of these interrupts can be mapped to either IRQ
or FIQ.
The interrupt routing (to the COP) is achieved by configuring the Interrupt Enable Register (IER) and the Interrupt Class
Registers (IEP_CLASS). Each IC32 has a set of IER and IEP Class registers. The COP registers are called COP_IER and
COP_IEP_CLASS. Similarly, the CPU IER/IEP Class Registers are called CPU_IER/CPU<1,2,3>_IER and
CPU_IEP_CLASS/CPU_IEP_CLASS.
When a 1 is set in the proper bit position in the COP_IER register, that particular source is capable of interrupting the COP.
Also, the class is set in the proper bit position of COP_IEP_CLASS for the corresponding interrupt to be routed as IRQ or FIQ.
The interrupt status register (ISR) allows the processor to view the state of the pending hardware interrupt requests regardless
of the bit enables programmed in COP_IER. The forced interrupt status register (FIR) allows the software to selectively force
set or clear specific interrupts. The read-only VIRQ/VFIQ allows the COP to determine the source of the interrupt request(s)
causing the processor to enter the interrupt service routine.

The nIRQ signals generated by five IC32 controllers are logically ANDed in the combiner to generate the final nIRQ (called
nirq1 in the above diagram) which is routed to the COP. Similarly, nFIQ signals are logically ANDed in the combiner to
generate nFIQ which is routed to the COP.
3.4.3.2 LIC Registers Description

The LIC consists of five interrupt controllers (called IC32); each IC32 handles 32 interrupts (for a total of 160 interrupts). Each
IC32 defines two sets of registers: one set for the COP (ARM7) and other set for the Cortex-A15 CPU.
Each IC32 has sixteen 32-bit registers. The COP and CPU<n> interrupt enable registers (COP_IER/CPU_IER) indicate the
interrupts enabled for the COP and CPU<3:0>, respectively. These registers have their respective SET and CLR registers that
allow setting or clearing individual bits of these registers without the need of a Read-Modify-Write cycle.
The COP/CPU Interrupt Class Register (COP_IEP_CLASS/CPU_IEP_CLASS) controls whether the interrupt will be routed to
the IRQ or the FIQ interrupt of the respective processor.
The Forced Interrupt Status Register (FIR) allows the software to force the set and clear of individual interrupts. This could be
used for debugging/testing purposes or could be used in the working system. Note that software cannot force set/clear an
interrupt which is already asserted by a hardware source. The FIR has its corresponding SET and CLR registers.
The Valid Interrupt Status Register (VIRQ_COP/VIRQ_CPU) and Valid FIQ Interrupt Status Register (VFIQ_COP/VFIQ_CPU)
indicate the currently active interrupts that are valid on the respective pins (nIRQ or nFIQ).
The differences between ISR and VFIQ/VIRQ registers are:
 The VFIQ/VIRQ registers indicate the interrupt which is sent to the processor (i.e., these registers indicate interrupts
outgoing from the interrupt controller). On the other hand, ISR indicates hardware interrupt incoming into the interrupt
controller.
- The VFIQ/VIRQ registers indicate the interrupts set by hardware or by software. The ISR register indicates
registers set by only hardware.
- The VFIQ/VIRQ registers only show the enabled interrupts. ISR shows the interrupt status irrespective of
whether the interrupt is enabled or not.
- The ISR shows the interrupt to be active whether it is routed to the FIQ pin or to the IRQ pin. The VFIQ/VIRQ
registers contain only the routed interrupts.
The VIRQ_COP and VIRQ_CPU registers are calculated as follows.
VIRQ_COP = (ISR | FIR) & IER_COP & (~COP_IEP_CLASS)

VIRQ_CPU<n> = (ISR | FIR) & IER_CPU<n> & (~CPU_IEP_CLASS)
Similarly, the VFIQ_COP and VFIQ_CPU<n> registers are generated as follows.
VIRQ_COP = (ISR | FIR) & IER_COP & COP_IEP_CLASS

VIRQ_CPU<n> = (ISR | FIR) & IER_CPU<n> & CPU<n>_IEP_CLASS
3.4.3.3 Hierarchical Interrupts Grouping

To reduce the number of interrupts (as seen by interrupt controllers also known as IRQs), interrupt sources that are non-critical
or unlikely to be used are grouped together. The hierarchical interrupt group (HIER_GROUPx) assembles 32 interrupts into
two interrupts: one for the CPU (called HIER_GROUPx_CPU) and the other one for the COP (called HIER_GROUPx_COP).
There is a software configurable enable register (HIER_GROUPx_{CPU,COP}_ENABLE) for each of the two interrupts which
can be independently programmed to select interrupts for that destination. Also, there is a status register
(HIER_GROUPx_{CPU,COP}_STATUS) for each of the two interrupts which provides the status of interrupts that are qualified
by an enable register. Note that incoming interrupt signals are active-high level signals, so interrupts have to be cleared (by
software) at the source unit. The interrupts are grouped as follows.

HIER_GROUP1_CPU_STATUS[31:0] = HIER_GROUP1_CPU_ENABLE[31:0] & source_INT[31:0]

HIER_GROUP1_CPU = | HIER_GROUP1_CPU_STATUS[31:0] //OR-ing of all bits
HIER_GROUP1_COP_STATUS[31:0] = HIER_GROUP1_COP_ENABLE[31:0] & source_INT[31:0]

HIER_GROUP1_COP = | HIER_GROUP1_COP_STATUS[31:0] //OR-ing of all bits
The HIER_GROUPx_{CPU,COP}_ENABLE registers act as mask registers for the hierarchical interrupts. Each bit in the
ENABLE register can mask the interrupt for the corresponding hierarchical group. Refer to Table 9 for the hierarchical interrupt
grouping per bit.
The Address Interrupt section of this document lists the interrupt sources which are in the hierarchical interrupts group(s).
3.4.4 Arbitration Semaphores

Arbitration semaphores provide a mechanism by which the CPU and COP can arbitrate for the use of various resources.
These semaphores provide a hardware locking mechanism, so that when a processor is already using a resource, the second
processor is not granted that resource. There are 32 bits of Arbitration semaphores provided in the system. The hardware
does not enforce any resource association to these bits. It is left to the software to assign and use these bits. Any processor
that needs to access a particular resource will request for the corresponding bit in the Arbitration semaphores by writing a one
to that bit in the Arbitration Semaphore Request register (SMP_GET register). Software will then check the corresponding bit
in the Semaphore Granted Status register (SMP_GNT_ST register)
If the requesting processor has been granted the resource, then the status returned will be a one. Alternately, the processor
can configure the interrupt controller to generate an interrupt when the resource becomes available.
When the processor has finished using the resource, it releases the resource by writing a one to the corresponding bit in the
Arbitration Semaphore Put Request register (SMP_PUT register). Additionally, pending request status is provided through the
Arbitration Request Pending Status register (SMP_REQ_ST register).
The Primary Interrupt Controller (PRI_ICTLR) supports Arbitration Grant Interrupts. When a processor is granted access to a
resource, the Arbitration semaphore module can be programmed to send a Grant signal to the interrupt controller. The
interrupt controller can then interrupt the processor to indicate that it has been granted exclusive access to a particular
resource. The individual ARB_GNT bits are OR’ed together and presented to the Primary Interrupt controller as Interrupt
Number 29.
The Arbitration/Grant interrupts mechanism registers are described in the Arbitration Semaphores section of this document.
3.4.5 Interrupts Used for Processor Power-Ups

The interrupt signals (nIRQ and nFIQ per processor) are routed to each processor as well as the Flow Controller unit. Based
on configuration, the flow controller uses them to power up the corresponding CPU. Refer to the Flow Controller section in this
TRM for the details of processor wake-up.
3.5 Interrupt Registers
3.5.1 Interrupt Controller Registers

NOTE: The interrupt controller (IC32) register descriptions do not follow the standard register table protocol
described in “Reading Register Tables” in the Introduction section. Each register’s relative offset, access
type, and power-on reset value are located in Table 11. The bit descriptions for each register are defined in
Table 12 according to interrupt controller (IC32).
Each IC32 has a set of 34 registers with names using the form <ID>_<FUNCTION>_0:
 ID identifies the specific IC32: PRI_ICTLR, SEC_ICTLR, TRI_ICTLR, QUAD_ICTLR, PENTA_ICTLR. Based on the
IC32, ID defines a base address and mapping (see below).

 FUNCTION identifies the use for this register. Refer to the LIC Registers Description subsection for more details.
FUNCTION is defined as one of the following:
- VIRQ_<DEST> and VFIQ_<DEST>: indicates the Valid status, as an IRQ or FIQ, respectively, for this
destination. DEST is COP, CPU, CPU1, CPU2, or CPU3.
- ISR: indicates the latched Interrupt Status
- FIR: indicates Force Interrupt
- FIR_SET and FIR_CLR: to control FIR, bits set to 1 are set or cleared, respectively, in FIR.
- <DEST>_IER: indicates that the corresponding event is enabled as an interrupt
- <DEST>_IER_SET and <DEST>_IER_CLR: to control IER, bits equal to 1 are set or cleared, respectively, in
IER.
- <DEST>_IEP_CLASS: Interrupt Enable Priority Class, a bit set to 0 indicates IRQ, and set to 1 indicates FIQ.
Table 10 associates the following with each IC32: the ID (used in the register names), the base offset (address map of the five
IC32s), and interrupt mapping reference.
Table 10: IC32 Characteristics
ID Base Offset Mapping
PRI_ICTLR 0x000 See Table 4: Primary Interrupt Controller (PRI_ICTLR) Mapping

SEC_ICTLR 0x100 See Table 5: Secondary Interrupt Controller (SEC_ICTLR) Mapping
TRI_ICTLR 0x200 See Table 6: Tertiary Interrupt Controller (TRI_ICTLR) Mapping
QUAD_ICTLR 0x300 See Table 7: Quaternary Interrupt Controller (QUAD_CTLR) Mapping
PENTA_ICTLR 0x400 See Table 8: Fifth Interrupt Controller (PENTA_ICTLR) Mapping
HIER2_ICTLR1 0x800
The table below summarizes all 34 registers for each IC32 (where <ID> is the controller name), their relative offsets, register
access types (RO, WO, or RW), and their 32-bit power-on reset values. The actual offset for each register is the base offset
(from the table above) plus the relative offset. The PRI_ICTLR, SEC_ICTLR, TRI_ICTLR, QUAD_ICTLR, and PENTA_ICTLR
have same set of registers at the same address offset with the exception of the ARBGNT registers which are only in
PRI_ICTLR. The ARBGNT registers are defined in the “Arb_gnt Specific Interrupt Controller Registers” subsection.
Table 11: Interrupt Controller IC32 Register Set
Relative Read/
Name Offset Write Reset Remark
<ID>_VIRQ_CPU_0 0x00 RO x Valid Interrupt Request Status for CPU0 Register
<ID>_VIRQ_COP_0 0x04 RO x Valid Interrupt Request Status for COP Register
<ID>_VFIQ_CPU_0 0x08 RO x FIQ Valid Interrupt Status for CPU0 Register
<ID>_VFIQ_COP_0 0x0C RO x FIQ Valid Interrupt Status for COP Register
<ID>_ISR_0 0x10 RO x Latched Interrupt Status Register
<ID>_FIR_0 0x14 RO x Forced Interrupt Status Register
<ID>_FIR_SET_0 0x18 WO 0 Force Interrupt Register Set Register
<ID>_FIR_CLR_0 0x1C WO 0 Force Interrupt Register Clear Register
<ID>_CPU_IER_0 0x20 RO x Enabled Interrupt Source for CPU0 Register (0=disabled)
<ID>_CPU_IER_SET_0 0x24 WO 0 Set Interrupt Enable for CPU0 Register
<ID>_CPU_IER_CLR_0 0x28 WO 0 Clear Interrupt Enable for CPU Register
<ID>_CPU_IEP_CLASS_0 0x2C RW 0 CPU0 Interrupt Enable Priority Class Register (1=FIQ/0=IRQ)

Relative Read/
Name Offset Write Reset Remark
<ID>_COP_IER_0 0x30 RO x Enabled Interrupt Source for COP Register (0=disabled
<ID>_COP_IER_SET_0 0x34 WO 0 Set Interrupt Enable for COP Register
<ID>_COP_IER_CLR_0 0x38 WO 0 Clear Interrupt Enable for COP Register
<ID>_COP_IEP_CLASS_0 0x3C RW 0 COP Interrupt Enable Priority Class Register (1=FIQ/0=IRQ)
<ID>_VIRQ_CPU1_0 0x60 RO x Valid Interrupt Request Status for CPU1 Register
<ID>_VFIQ_CPU1_0 0x64 RO x FIQ Valid Interrupt Status for CPU Register
<ID>_CPU1_IER_0 0x68 RO x Enabled Interrupt Source for CPU1 Register (0=disabled)
<ID>_CPU1_IER_SET_0 0x6C WO 0 Set Interrupt Enable for CPU1 Register
<ID>_CPU1_IER_CLR_0 0x70 WO 0 Clear Interrupt Enable for CPU1 Register
<ID>_CPU1_IEP_CLASS_0 0x74 RW 0 CPU1 Interrupt Enable Priority Class Register (1=FIQ/0=IRQ)
<ID>_VIRQ_CPU2_0 0x78 RO x Valid Interrupt Request Status for CPU2 Register
<ID>_VFIQ_CPU2_0 0x7C RO x FIQ Valid Interrupt Status for CPU2 Register
<ID>_CPU2_IER_SET_0 0x84 WO 0 Set Interrupt Enable for CPU2 Register
<ID>_CPU2_IER_CLR_0 0x88 WO 0 Clear Interrupt Enable for CPU2 Register
<ID>_CPU2_IEP_CLASS_0 0x8c RW 0 CPU2 Interrupt Enable Priority Class Register (1=FIQ/0=IRQ)
<ID>_VIRQ_ CPU3_0 0x90 RO x Valid Interrupt Request Status for CPU3 Register
<ID>_VFIQ_ CPU3_0 0x94 RO x FIQ Valid Interrupt Status for CPU3 Register
<ID>_CPU3_IER_SET_0 0x9C WO 0 Set Interrupt Enable for CPU3 Register
<ID>_CPU3_IER_CLR_0 0xA0 WO 0 Clear Interrupt Enable for CPU3 Register
<ID>_CPU3_IEP_CLASS_0 0xA4 RW 0 CPU3 Interrupt Enable Priority Class Register (1=FIQ/0=IRQ)
The following table defines the bits within each of the five IC32 interrupt controller’s registers. To calculate the global interrupt
number of each bit, add the bit location (0 to 31) to the base interrupt value for the specific interrupt controller.
Table 12: IC32 Register Bit Descriptions
Fourth IC32
First IC32 (PRI_ICTLR) Bits Second IC32 (SEC_ICTLR) Bits Third IC32 (TRI_ICTLR) Bits Fifth IC32 (PENTA_ICTRL) Bits
Bit (QUAD_ICTRL) Bits
(Base Interrupt = 0) (Base Interrupt = 32) (Base Interrupt = 64) (Base Interrupt = 128)
(Base Interrupt = 96)
31 SDMMC4 I2C6 SW_INTR HIER_GROUP1_CPU DPAUX
30 OWR CLDVFS SPI5 CAR GPU_NONSTALL
29 ARB_SEM_GNT_CPU AHB_DMA_COP SPI4 GPIO8 GPU_STALL
28 ARB_SEM_GNT_COP APB_DMA_COP I2C3 WDT_AVP TMR0
27 AHB_DMA_CPU SPI1 - WDT_CPU TMR9
26 APB_DMA_CPU SE UARTD HIER_GROUP1_COP TMR8
25 VCP USB3_DEV_PME GPIO7 TMR5 TMR7
24 - USB3_DEV_SMI - I2C4 TMR6
23 SATA_CTL GPIO5 GPIO6 APB_DMA_CH15 SDMMC4_SYS
22 - STAT_MON PMU_EXT APB_DMA_CH14 SDMMC3_SYS
21 USB2 I2C5 - APB_DMA_CH13 SDMMC2_SYS
20 USB VFIR I2C2 APB_DMA_CH12 SDMMC1_SYS
19 SDMMC3 EDP SPI3 APB_DMA_CH11 CPU3_PMU_INTR
18 AVP_UCQ TSEC SPI2 APB_DMA_CH10 CPU2_PMU_INTR

Fourth IC32
First IC32 (PRI_ICTLR) Bits Second IC32 (SEC_ICTLR) Bits Third IC32 (TRI_ICTLR) Bits Fifth IC32 (PENTA_ICTRL) Bits
Bit (QUAD_ICTRL) Bits
(Base Interrupt = 0) (Base Interrupt = 32) (Base Interrupt = 64) (Base Interrupt = 128)
(Base Interrupt = 96)
17 VDE XUSB_PADCTL HDA APB_DMA_CH9 CPU1_PMU_INTR
16 - THERMAL - APB_DMA_CH8 CPU0_PMU_INTR
15 SDMMC2 HSI SPI6 APB_DMA_CH7 APB_DMA_CH31
14 SDMMC1 UARTC EMC APB_DMA_CH6 APB_DMA_CH30
13 SATA_RX_STAT ACTMON MC APB_DMA_CH5 APB_DMA_CH29
12 VDE_SXE USB3_DEV_HOST SOR APB_DMA_CH4 APB_DMA_CH28
11 VDE_BSEA USB3_HOST_PME HDMI APB_DMA_CH3 APB_DMA_CH27
10 VDE_BSEV TMR4 DISPLAYB APB_DMA_CH2 APB_DMA_CH26
9 VDE_SYNC_TOKEN TMR3 DISPLAY APB_DMA_CH1 APB_DMA_CH25
8 VDE_UCQ USB3_HOST_SMI VIC APB_DMA_CH0 APB_DMA_CH24
7 SHR_SEM_OUTBOX_EMPTY USB3_HOST_INT ISP AUDIO_CLUSTER APB_DMA_CH23
6 SHR_SEM_OUTBOX_FULL I2C ISPB - APB_DMA_CH22
5 SHR_SEM_INBOX_EMPTY UARTB VI AVP_CACHE APB_DMA_CH21
4 SHR_SEM_INBOX_FULL UARTA MSENC PCIE_WAKE APB_DMA_CH20
3 CEC GPIO4 HOST1X_GEN_CPU PCIE_MSI APB_DMA_CH19
2 RTC GPIO3 HOST1X_GEN_COP PCIE_INT APB_DMA_CH18
1 TMR2 GPIO2 HOST1X_SYNCPT_CPU USB3 APB_DMA_CH17
0 TMR1 GPIO1 HOST1X_SYNCPT_COP SNOR APB_DMA_CH16
3.5.2 Arb_gnt Specific Interrupt Controller Registers

Refer to “Reading Register Tables” in the Introduction section for the register table protocol as well as recommendations for
accessing registers.
Arbitration semaphores provide a mechanism by which the two processors can arbitrate for the use of various resources.
These semaphores provide a hardware locking mechanism, so that when a processor is already using a resource, the second
processor is not granted that resource. There are 32 bits of Arbitration semaphores provided in the system.
The hardware does not enforce any resource association to these bits. It is left to the firmware to assign and use these bits.
The Arbitration Semaphores can also generate an interrupt when a hardware resource becomes available. The registers in
this module configure these interrupts. When a 1 is set in the corresponding bit position of the Arbitration Semaphore Interrupt
Source Register (CPU_enable or COP_enable), an interrupt will be generated when the processor achieves Grant Status for
that resource.
The current Grant status can be viewed in the CPU_STATUS or COP_STATUS registers.
3.5.2.1 PRI_ICTLR_ARBGNT_CPU_STATUS_0
CPU Arbitration Semaphore Interrupt Status Register

Offset: 0x40 | Read/Write: RO | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Bit Reset Description
GNT31_GNG0: Each bit is set by hardware when the corresponding arbitration semaphore
31:0 X ownership is granted to the CPU. Interrupt is cleared when the CPU writes the ARB_SMP.PUT
register with the corresponding bit set.

3.5.2.2 PRI_ICTLR_ARBGNT_CPU_ENABLE_0
CPU Arbitration Semaphore Interrupt Enable Register

Offset: 0x44 | Read/Write: R/W | Reset: 0x00000000 (0b00000000000000000000000000000000)
GER31_GER0: Writing a 1 in any bit position will enable the corresponding arbitration
31:0 0x0
semaphore interrupt.
3.5.2.3 PRI_ICTLR_ARBGNT_COP_STATUS_0
COP Arbitration Semaphore Interrupt Status Register

GNT31_GNG0: Each bit is set by hardware when the corresponding arbitration semaphore
31:0 X ownership is granted to the COP. The interrupt is cleared when the COP writes the
ARB_SMP.PUT register with the corresponding bit set.
3.5.2.4 PRI_ICTLR_ARBGNT_COP_ENABLE_0
COP Arbitration Semaphore Interrupt Enable Register

Offset: 0x4c | Read/Write: R/W | Reset: 0x00000000 (0b00000000000000000000000000000000)
GER31_GER0: Writing a 1 in any bit position will enable the corresponding arbitration
31:0 0x0
semaphore interrupt.
3.5.3 Hier Group Interrupt Registers

This subsection describes the registers for Hier group interrupts for the CPU and the COP.
3.5.3.1 HIER_GROUP_CPU_ENABLE_0
Hier Group Enable for CPU

CPU_ENABLE: Enable for the hier group interrupt for the CPU. Writing a 1 in any bit position will enable
31:0 0x0
the corresponding interrupt.

3.5.3.2 HIER_GROUP_CPU_STATUS_0
Hier Group Status (ISR) Register for CPU

31:0 X CPU_STATUS: Status for the hier group interrupt for the CPU.
3.5.3.3 HIER_GROUP_COP_ENABLE_0
Hier Group Enable for COP

COP_ENABLE: Enable for the hier group interrupt for the COP. Writing a 1 in any bit position will enable
31:0 0x0
the corresponding interrupt.
3.5.3.4 HIER_GROUP_COP_STATUS_0
Hier Group Status (ISR) for COP

Offset: 0x80c | Read/Write: RO | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X COP_STATUS: Status for the hier group interrupt for the COP.
3.5.3.5 HIER_GROUP_FIR_STATUS_0
Status Register for FIR Register in Hier Group

31:0 X FIR_STATUS: Software interrupts for the hier group.
3.5.3.6 HIER_GROUP_FIR_SET_0
FIR Set for Hier Group

Offset: 0x814 | Read/Write: WO | Reset: 0x00000000 (0b00000000000000000000000000000000)
31:0 0x0 FIR_SET: FIR set for the hier group.

3.5.3.7 HIER_GROUP_FIR_CLEAR_0
FIR Clear for Hier Group

31:0 0x0 FIR_CLEAR: FIR clear for the hier group.
3.5.4 EVP Registers

Each processor sees its own set of EVP reset vector registers.
3.5.4.1 EVP_RESET_VECTOR_0
31:0 X RESET_VECTOR: RESET Exception Vector Pointer


4.0 SEMAPHORES
4.1 Arbitration Semaphores

Arbitration semaphores provide a mechanism by which the two processors can arbitrate for the use of various resources.
These semaphores provide a hardware locking mechanism to ensure that when a processor is already using a resource, the
second processor is not granted that resource. There are 32 bits of arbitration semaphores provided in the system. The
hardware does not enforce any resource association to these bits and it is left to the user to assign and use these bits.
Any processor that needs to access a particular resource will request for the corresponding bit in the arbitration semaphores
by writing a one to that bit in the Arbitration Semaphore Request register (SMP_GET register). Firmware will then check the
corresponding bit in the Semaphore Granted Status register (SMP_GNT_ST register). If the requesting processor has been
granted the resource, then the status returned will be a one.
Alternately, the processor can configure the interrupt controller to generate an interrupt when the resource becomes available.
When the processor has finished using the resource, it releases the resource by writing a one to the corresponding bit in the
Arbitration Semaphore Put Request register (SMP_PUT register). Additionally, pending request status is provided through the
Arbitration Request Pending Status register (SMP_REQ_ST register).
(Note that an alternative mechanism to this exists in the Atomics block. Please refer to the corresponding section of this
document for further details. At the time of this writing, NVIDIA software does not make use of the Atomics block.)

SD/MMC Controller
4.2 Semaphore Registers

4.2.1 Arbitration Semaphore Registers
4.2.1.1 ARB_SEMA_SMP_GNT_ST_0
Semaphore Granted Status Register

Offset: 0x0 | Read/Write: RO | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X ARB_31_ARB_0: A one in any bit indicates that the processor reading this register as
granted status for that bit. A zero indicates semaphore not granted.
4.2.1.2 ARB_SEMA_SMP_GET_0
Request Arbitration Semaphore Register

31:0 0x0 GET_31_GET_0: Writing a one in any bit is a request for that semaphore bit by the
processor performing the register write.
4.2.1.3 ARB_SEMA_SMP_PUT_0
Arbitration Semaphore Put Request Register

31:0 0x0 PUT_31_PUT_0: Writing a one in any bit will clear the corresponding semaphore bit by
the processor performing the register write.
4.2.1.4 ARB_SEMA_SMP_REQ_ST_0
Arbitration Request Pending Status (1=PENDING) Register

Offset: 0xc | Read/Write: RO | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X REQ_31_REQ_0: A one in any bit indicates a request pending status. The corresponding
bits are set when the request for the individual resource is pending. The read by the CPU
of this register shows the pending status for the CPU and a read of this register by AVP
(COP) shows the pending status for AVP.

SD/MMC Controller
4.2.2 Shared Resource Semaphore Registers
4.2.2.1 RES_SEMA_SHRD_SMP_STA_0
Shared Resource Semaphore Status

31:0 X SMP_31_SMP_0: SMP.27:SMP.24: Available in APB_DMA.REQUESTORS register
4.2.2.2 RES_SEMA_SHRD_SMP_SET_0
Shared Resource Semaphore Set-Bit Request

SET_31_SET_0: Semaphore set register. Writing a one to any bit will set the corresponding semaphore
31:0 0x0
bit. Shared resource set-bit requests.
4.2.2.3 RES_SEMA_SHRD_SMP_CLR_0
Shared Resource Semaphore Clr-bit Request Register

31:0 0x0 CLR_31_CLR_0: Corresponding semaphore bit.
4.2.2.4 RES_SEMA_SHRD_INBOX_0
Shared Resource Inbox (Messages from COP (ARM7) to CPU)

Offset: 0x10 | Read/Write: R/W | Reset: 0x00000000 (0b000x0000000000000000000000000000)
IE_IBF: Interrupt CPU on INBOX Full (TAG=1)

31 0x0 0 = EMPTY
1 = FULL
IE_IBE: Interrupt COP on INBOX Empty (TAG=0)

30 0x0 0 = EMPTY
1 = FULL
TAG: Set when the COP writes this register and cleared when CPU writes this register with this bit set
to 1 (write one clear).
29 0x0
0 = INVALID
1 = VALID
IN_BOX_STAT: General-purpose data bits, suggested usage is for INBOX status (software can change
27:24 0x0
the definition)
IN_BOX_CMD: General-purpose data bits, suggested usage is for INBOX command (software can
23:17 0x0
change the definition)
IN_BOX_DATA: General-purpose Inbox data bits, suggested usage is for INBOX data (software can
16:0 0x0
change the definition)

SD/MMC Controller
4.2.2.5 RES_SEMA_SHRD_OUTBOX_0
Shared Resource Outbox (Messages from CPU to COP (ARM7))

IE_OBF: Interrupt COP on OUTBOX Full (TAG=1)

31 0x0 0 = EMPTY
1 = FULL
IE_OBE: Interrupt CPU on OUTBOX Empty (TAG=0)

30 0x0 0 = EMPTY
1 = FULL
TAG: Set when the CPU writes this register and cleared when the COP writes this register with this bit
set to 1 (write one clear).
29 0x0
0 = INVALID
1 = VALID
OUT_BOX_STAT: General-purpose data bits, suggested usage is for Outbox OUTBOX status (software
27:24 0x0
can change the definition)
OUT_BOX_CMD: General-purpose data bits, suggested usage is for Outbox OUTBOX command
23:17 0x0
(software can change the definition)
OUT_BOX_DATA: General-purpose Outbox data bits, suggested usage is for OUTBOX data (software
16:0 0x0
can change the definition)

5.0 CLOCK AND RESET CONTROLLER

®
The Clock and Reset (CAR) block contains all the logic needed to control most of the clocks and resets to the Tegra K1
device. The CAR block provides the registers to program the PLLs and controls most of the clock source programming, and
most of the clock dividers.
Power on reset (SYS_RESET_N_) is the primary reset for the Tegra K1 chip and is provided by the external PMC.
5.1 Hardware Features
5.1.1 External Clock Sources

The CAR block takes two external clock sources as input:
 A single external 32.768 kHz clock, normally provided by the Power Manager Integrated Circuit (PMIC)
 An oscillator clock (OSC) at 12, 13, 16.8, 19.2, 26, 38.4, or 48 MHz, provided by an external crystal. Not all these
frequencies may be supported by software.
5.1.2 Clock Sources and PLLs

Clock sources are provided by 16 PLLs in the Tegra K1 clock system:
 PLLM: Clock source for EMC 2x clock

 PLLX: Clock source for the fast CPU cluster and the shadow CPU
 PLLC: Clock source for general use
 PLLC2 and PLLC3: Clock source for engine scaling
 PLLC4: Clock source for ISP/VI units
 PLLP: Clock source for most peripherals
 PLLA: Audio clock sources:
 11.2896 MHz
 12.288 MHz
 24.576 MHz
 PLLU: Clock source for USB PHY, provides 12/60/480 MHz
 PLLD and PLLD2: Clock sources for the DSI and display subsystem
 refPLLe and PLLE generate the 100 MHz reference clock for USB 3.0 and can generate a spread-spectrum clock
 PLLDP: Clock source for eDP/LVDS (spread spectrum)
 DFLLCPU: DFLL clock source for the fast CPU cluster
 GPCPLL: Clock source for the GPU
5.1.3 Clock Dividers / Skippers / Multiplier

There are a number of clock skippers and clock dividers as well as one clock multiplier in use in the Tegra K1 devices.
 Clock skippers:
 An M/N clock-skipping divider that is used to generate the CPU clock and also the Tegra K1 "system clock"
(sclk).
 Clock skippers that are used to generate the "AHB clock" (hclk) and "APB clock" (pclk). One that divides down
by a 2-bit unsigned value (U2).

Clock and Reset Controller
 Clock dividers:
 An unsigned 16-bit divider (U16) that is the divider for the I2C and UART devices.
 An unsigned 8-bit divider that provides 7 bits of mantissa and 1 bit of fraction (U7.1). Tegra K1 devices have
reduced the number of divider types and in particular this U7.1 divider is the default divider for most all blocks in
Tegra K1 devices.
Note: The clock-skipping divider and the U7.1 divider when programmed with the 1b fraction do
not create 50/50 duty-cycle clock waveforms and may not be suitable for all modules
under all circumstances.
 Clock multiplier:
 A times-two multiplier used to double the external reference frequency by delaying and XORing the input clock
with a 4-bit programmable delayed reference clock. Care must be exercised when using this dual-frequency and
widely varying duty-cycle clock.
5.2 Clocking Architecture

Tegra K1 clocks are classified into two categories: core clocks and I/O clocks. Core clocks drive the non-I/O modules on the
Tegra K1 chip. I/O clocks are custom designed for each I/O module. Only core clocks are described here.
5.2.1 Core Clocks

The core clock structure consists of:
 Sources
 Switches
 Distribution and skew balancing
 Second-level non-functional clock gates
Core clocks originate from external clock sources which are used by on-chip PLLs to generate a set of primary clock sources.
Secondary clock sources are created by dividing down various PLL outputs. This group of external, PLL, and divided PLL
clocks constitutes the clock sources.
These sources feed the clock switches. Each module has its own switch. A clock switch consists of one or more clock sources
selected through a Clock Source Selection Mux and driving a clock divider. Multiple clock source options are available to the
module divider to allow software to choose a clock frequency based on the unit’s performance requirements and overall SOC
power. Switching a clock source away from a PLL when it is locking after being reprogrammed to a new frequency may also
be required. There are three types of dividers: fixed divide value, fractional divider, or clock skipping (pulse eating) divider.
5.2.2 Main Clock Sources

There are three types of clock sources:
 External clock sources

 PLLs
 Derived clock sources
Table 13: External Clocks to Tegra K1 Devices

Clock Name Description
dbg_oscout: This clock runs at 12MHz, 13 MHz, 19.2 MHz, 26 MHz, 16.8 MHz, 38.4 MHz, or
48 MHz. Only 12 MHz is currently supported.
ck32khz_IB: This clock runs at 32.768 kHz.

Table 14: Primary Clock Sources in Tegra K1 Devices

osc_div_clk: This clock runs at 12 MHz, 13 MHz, 16.8 MHz, 19.2 MHz, or 26 MHz. Only 12
MHz is currently supported.
car_sclk: This is the system clock whose maximum frequency is 200 MHz
clk_m: This clock (with DFT control) runs at 12 MHz, 13 MHz, 16.8 MHz, 19.2 MHz,
26 MHz, 38.4 MHz, or 48 MHz. Only 12 MHz is currently supported.
car_clk_m: This clock (with DFT control) runs at 12 MHz, 13 MHz, 16.8 MHz, 19.2 MHz, 26
MHz, 38.4 MHz, or 48 MHz. Only 12 MHz is currently supported.
dfllCPU_out: This is the dfllCPU’s output clock.
pllC_out: This is the PLLC’s output clock.
pllC2_out: This is the PLLC2’s output clock.
pllC3_out: This is the PLLC3’s output clock.
pllC4_out: This is the PLLC4’s output clock, which is used for the VI and ISP blocks.
pllM_out: This is the PLLM’s output clock.
int_pllA_out This is the PLLA’s output clock.
pllD_out: This is the PLLD’s output clock.
pllD2_out: This is the PLLD2’s output clock.
pllDP_out This is the PLLDP’s output clock.
pllU: This is the PLLU’s output clock. USB2 I/O.
refPLLE_out: This is the refPLLE’s output clock. Low jitter reference clock for PLLE, USB.
pllE_out0: This is the PLLE’s output clock. USB3 I/O.
pllP_out: This is the PLLP’s output clock which is set to 408 MHz.
pllX This is the output clock for the fast CPU cluster and the shadow CPU
GPCPLL This is the output clock for the GPU
clk_s: This clock (with DFT control) runs at 32.768 kHz.
car_clk_s: CAR’s clock tree balanced version of clk_s.
Table 15: Derived Clock Sources in Tegra K1 Devices

pllC_out1: This is the U7.1 divider output clocked by “pllC_out”.
pllM_out1: This is the U7.1divider output clocked by “pllM_out”.
pllP_out1: This is the U7.1 divider output clocked by “pllP_out” (28.8 MHz boot, changed to
9.6 MHz).
pllP_out2: This is the U7.1 divider output clocked by “pllP_out” (48 MHz boot, changed to
48 MHz).
pllP_out3: This is the U7.1 divider output clocked by “pllP_out”. (72 MHz boot, changed to
102 MHz).
variable)
variable).
pllA_out0: This is the U7.1 divider output clocked by “int_pllA_out”.
The table below lists which clock source they are derived from and their divider size.

Table 16: Clock Sources for the Derived Clocks
Have super clock divider ?
Have U7.1 divider?

pllM_2x_out
int_pllA_out
dbg_oscout
ck32khz_IB
(# of bits)
(# of bits)
pllM_out
pllC_out
pllP_out
pllC_out1 x 8
pllM_out1 x 8
pllP_out1 x 8
pllP_out2 x 8
pllP_out3 x 8
pllP_out4 x 8
pllP_out5 x 8
pllA_out0 x 8
These clock sources are shown in the following figure.

Figure 4: Clocking Sources

clk_m
car_clk_m
Trim
dfllCPU_out
DFLL
oscfi
glitchless
dbg_oscout
/2 osc_div_clk
pllX
pllX_out_g
/4 /1 or /2
pllxlp
pllC_out
NV pllC_out1
pllC divider
pllC2_out
pllC2
pllC3_out
pllC3
pllM_out
NV pllM_out1
pllM divider
pllD_out
pllD_out0
pllD /2
pllU_12
pllU_48
pllU pllU_60
pllU_480
PLLD2 pllD2_out0
PLLDP pllDP_out0
PLLC4 pllC4_out0
pllREFE_out
differential clock to USB3

refpllE
pllE pllE_out0
pllP_out
pllP
pllP_out1
NV NV pllA_out0
divider
pllA divider
NV pllP_out2
divider
NV pllP_out3
divider
NV pllP_out4
divider
NV pllP_out5
divider
ck32khz
clk32khz_IB
clk_s
car_clk_s
Trim
The two tables below give a quick overview of the root clock generators. They include the clock sources and the divider type
and size. For example, the ACTMON root clock has 6 clock sources (000=pllP_out, 001=pllC2_out, 010=pllC_out,
011=pllC3_out, 100=ck32khz_IB, 110=dbg_oscout) and has an 8-bit wide U7.1 fractional divider. The default reset value is
shown as an underlined value such as 6.

Notes:
 Clock source pllX_out is an output of a mux that can select between the pllX_out clock and a predivide-by-2 pllX_out
clock. Clock source dfllCPU_out is an output of a mux that can select between the dfllCPU_out clock and a
predivide-by-2 dfllCPU_out.
 When EMC clock source = 4, the U7.1 divider is bypassed/ignored. This setting will give a very short low jitter clock
path from pllM_out to EMC clock.
 When clock source = 14 or 15, in addition to being selected into the glitch-less switching logic in CAR, the selected
clock will also bypass the U7.1 divider creating a short low jitter clock path to the output clock.
 The Clock Skipper is controlled by SOC Therm hardware.
Table 17: Root Clock Sources (1 of 2)
spdif_audio_2x_sync_clk
pllM_out_for_emc
pllE_clockout
dfllCPU_out
ck32khz_IB
pllP_out4_t
pllP_out3_t
pllD2_out0
pllM_out1
pllC2_out
pllC3_out
pllC_out1
pllA_out0
pllD_out0
pllP_out2
pllM_out
pllC_out
pllP_out
pllX_out
oscout
actmon_clk_t 6 2 1 3 4 0
adx0_r_clk 6 2 1 3 4 0
adx1_r_clk 6 2 1 3 4 0
amx0_r_clk 6 2 1 3 4 0
amx1_r_clk 6 2 1 3 4 0
audio_r_clk 6 2 1 3 4 0
cilab_clk_t 6 2 0
cilcd_clk_t 6 2 0
cile_clk_t 6 2 0
clk72mhz_clk 3 1 2 0
csite_clk_t 6 2 1 3 4 0
dam0_r_clk 6 2 1 3 4 0
dam1_r_clk 6 2 1 3 4 0
dam2_r_clk 6 2 1 3 4 0
display_clk_t 6 4 1 0 3 2 5
displayb_clk_t 6 4 1 0 3 2 5
dsia_lp_clk_t 6 2 0
dsib_lp_clk_t 6 2 0
dvfs_ref_r_clk 6 2 1 3 4 0

pllM_out_for_emc
pllE_clockout
dfllCPU_out
ck32khz_IB
pllP_out4_t
pllP_out3_t
pllD2_out0
pllM_out1
pllC2_out
pllC3_out
pllC_out1
pllA_out0
pllD_out0
pllP_out2
pllM_out
pllC_out
pllP_out
pllX_out
oscout
dvfs_soc_r_clk 6 2 1 3 4 0
emc_dll_clk_t 3 1 5 6 4 2
emc_latency_clk_t 3 1 5 6 4 2
entropy_r_clk 1 2 3
extperiph1_clk 3 1 2 0 4
hda_r_clk 6 2 1 3 4 0
hdmi_audio_clk_t 3 1 2
hdmi_clk_t 6 4 1 0 3 2 5
host1x_clk_t 2 1 3 0 4 6
hsi_clk_t 6 2 1 3 4 0
i2c1_r_clk 6 2 1 3 4 0
i2c2_r_clk 6 2 1 3 4 0
i2c3_r_clk 6 2 1 3 4 0
i2c4_r_clk 6 2 1 3 4 0
i2c5_r_clk 6 2 1 3 4 0
i2c6_r_clk 6 2 1 3 4 0
i2c_slow_clk 6 2 1 3 4 0
i2s0_r_clk 6 4 0
i2s1_r_clk 6 4 0
i2s2_r_clk 6 4 0
i2s3_r_clk 6 4 0
i2s4_r_clk 6 4 0
int_emc_clk 3 1 5 6 0 4 2
int_hda2codec_2x_clk 6 2 1 3 4 0
isp_r_clk_t 6 1 4 5 0 2 3
la_clk_t 6 2 1 3 4 0
lvds0_pad_clockin_t 6 4 1 0 3 2 5

pllM_out_for_emc
pllE_clockout
dfllCPU_out
ck32khz_IB
pllP_out4_t
pllP_out3_t
pllD2_out0
pllM_out1
pllC2_out
pllC3_out
pllC_out1
pllA_out0
pllD_out0
pllP_out2
pllM_out
pllC_out
pllP_out
pllX_out
oscout
mselect_clk_t 6 2 1 3 5 4 0
msenc_clk_t 2 1 3 0 4 6
nor_r_clk 6 2 1 3 4 0
owr_r_clk 6 2 1 3 4 0
pex_txclkref
pex_txclkref_grp0
pex_txclkref_grp1
pex_txclkref_grp2
pex_txclkref_tms
pwm_r_clk 6 2 1 3 4 0
sata_oob_clk_t 6 2 4 0
sclk_sel 0 5 6 2 1 4 7
sdmmc1_r_clk_t 6 2 1 3 4 0 5
sdmmc2_r_clk_t 6 2 1 3 4 0 5
sdmmc3_r_clk_t 6 2 1 3 4 0 5
sdmmc4_r_clk_t 6 2 1 3 4 0 5
se_clk_t 6 2 1 3 4 0 5
soc_therm_t 1 4 5 0 2 3
spdif_in_r_clk 2 1 3 4 0
spdif_out_r_clk 6 4 0 2
spi1_clk_t 6 2 1 3 4 0
spi2_clk_t 6 2 1 3 4 0
spi3_clk_t 6 2 1 3 4 0
spi4_clk_t 6 2 1 3 4 0
spi5_clk_t 6 2 1 3 4 0
spi6_clk_t 6 2 1 3 4 0
sys2hsio_sata_r_clk 6 2 4 0
traceclkin_clk_t 6 2 1 3 4 0
tsec_clk_t 6 2 1 3 4 0 5

vi_clk_t
vic_clk_t
vfir_clk_t
vde_clk_t
adx1_r_clk
adx0_r_clk
uartc_r_clk
uartd_r_clk
uartb_r_clk
uarta_r_clk
amx0_r_clk
xusb_fs_clk
actmon_clk_t
tsensor_r_clk
vi_sensor_clk
xusb_core_clk
vi_sensor2_clk
xusb_120m_clk
xusb_falcon_clk
xusb_core_dev_clk
7
6
6
6
6
6
6
6
4
pllREFE_clockout oscout
3
3
3
4
1
2
2
2
2
2
2
2
2
2
2
uhsic_clk480pll pllC_out
Table 18: Root Clock Sources (2 of 2)

2
2
2
5
4
1
1
1
1
1
1
1
1
1
1
fo_60m_out pllC2_out
4
4
4
6
5
3
3
3
3
3
3
3
3
3
fo_48m_out 3 pllC3_out
2
6
audio_clk_src1111 ck32khz_IB
0
0
0
0
4
4
4
4
4
4
dam0_clk_src1111 pllM_out
dam1_clk_src1111 pllM_out_for_emc
4
1
1
1
2
4
4
4
0
0
0
0
0
0
0
dam2_clk_src1111 pllP_out
i2s0_audio_sync_clk pllP_out4_t
i2s1_audio_sync_clk pllP_out3_t
TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com

i2s2_audio_sync_clk pllX_out
i2s3_audio_sync_clk dfllCPU_out
i2s4_audio_sync_clk pllC_out1
pex_pad_txclkref pllP_out2
pex_pad_txclkref_div1 pllM_out1
3
6
6
6
pex_pad_txclkref_div2 pllA_out0
pllC4_clockout spdif_audio_2x_sync_clk
pllP_out0 pllD_out0
sys2hsio_clk_m_sys_clk pllD2_out0
8
8
8
8
Divide pllE_clockout
63
sys2hsio_clk_m_sys_clk
pex_pad_txclkref_div1
i2s0_audio_sync_clk
i2s1_audio_sync_clk
i2s2_audio_sync_clk
i2s3_audio_sync_clk
i2s4_audio_sync_clk
dam1_clk_src1111
dam2_clk_src1111
audio_clk_src1111
dam0_clk_src1111
pllREFE_clockout
pex_pad_txclkref
uhsic_clk480pll
pllC4_clockout
fo_60m_out
fo_48m_out
pllP_out0
Divide
amx1_r_clk 8
audio_r_clk 7 8
cilab_clk_t 8
cilcd_clk_t 8
cile_clk_t 8
clk72mhz_clk 8
csite_clk_t 8
dam0_r_clk 7 8
dam1_r_clk 7 8
dam2_r_clk 7 8
display_clk_t 0
displayb_clk_t 0
dsia_lp_clk_t 8
dsib_lp_clk_t 8
dvfs_ref_r_clk 8
dvfs_soc_r_clk 8
emc_dll_clk_t 8
emc_latency_clk_t 8
entropy_r_clk 0 8
extperiph1_clk 8
extperiph2_clk 8
extperiph3_clk 8
hda_r_clk 8
hdmi_audio_clk_t 0 8
hdmi_clk_t 8
host1x_clk_t 8
hsi_clk_t 8
i2c1_r_clk 16
i2c2_r_clk 16

i2s0_audio_sync_clk
i2s1_audio_sync_clk
i2s2_audio_sync_clk
i2s3_audio_sync_clk
i2s4_audio_sync_clk
dam1_clk_src1111
dam2_clk_src1111
audio_clk_src1111
dam0_clk_src1111
pllREFE_clockout
pex_pad_txclkref
uhsic_clk480pll
pllC4_clockout
fo_60m_out
fo_48m_out
pllP_out0
Divide
i2c3_r_clk 16
i2c4_r_clk 16
i2c5_r_clk 16
i2c6_r_clk 16
i2c_slow_clk 8
i2s0_r_clk 2 8
i2s1_r_clk 2 8
i2s2_r_clk 2 8
i2s3_r_clk 2 8
i2s4_r_clk 2 8
int_emc_clk 0
int_hda2codec_2x_clk 8
isp_r_clk_t 7 8
la_clk_t 8
lvds0_pad_clockin_t 8
mselect_clk_t 8
msenc_clk_t 8
nor_r_clk 8
owr_r_clk 8
pex_txclkref 0 8
pex_txclkref_grp0 1 0 8
pex_txclkref_tms 1 0 8
pwm_r_clk 8
sata_oob_clk_t 8
sclk_sel 3 8
sdmmc1_r_clk_t 8
sdmmc2_r_clk_t 8

i2s0_audio_sync_clk
i2s1_audio_sync_clk
i2s2_audio_sync_clk
i2s3_audio_sync_clk
i2s4_audio_sync_clk
dam1_clk_src1111
dam2_clk_src1111
audio_clk_src1111
dam0_clk_src1111
pllREFE_clockout
pex_pad_txclkref
uhsic_clk480pll
pllC4_clockout
fo_60m_out
fo_48m_out
pllP_out0
Divide
sdmmc3_r_clk_t 8
sdmmc4_r_clk_t 8
se_clk_t 8
soc_therm_t 8
spdif_in_r_clk 8
spdif_out_r_clk 8
spi1_clk_t 8
spi2_clk_t 8
spi3_clk_t 8
spi4_clk_t 8
spi5_clk_t 8
spi6_clk_t 8
sys2hsio_sata_r_clk 8
traceclkin_clk_t 8
tsec_clk_t 8
tsensor_r_clk 8
uarta_r_clk 17
uartb_r_clk 17
uartc_r_clk 17
uartd_r_clk 17
vde_clk_t 8
vfir_clk_t 8
vi_clk_t 7 8
vi_sensor2_clk 8
vi_sensor_clk 8
vic_clk_t 8
xusb_120m_clk 1 3 0 8
xusb_core_clk 5 0 8
xusb_core_dev_clk 5 0 8

i2s0_audio_sync_clk
i2s1_audio_sync_clk
i2s2_audio_sync_clk
i2s3_audio_sync_clk
i2s4_audio_sync_clk
dam1_clk_src1111
dam2_clk_src1111
audio_clk_src1111
dam0_clk_src1111
pllREFE_clockout
pex_pad_txclkref
uhsic_clk480pll
pllC4_clockout
fo_60m_out
fo_48m_out
pllP_out0
Divide
xusb_falcon_clk 5 0 8
xusb_fs_clk 6 2 0 8
5.2.3 Generic Clock Core Structure

Root clock generation is typically a clock source selection mux followed by a U7.1 fractional divider. The clock source
selection mux is made glitch-less by the addition of a state machine that gates off the clocks that might be impacted by the
glitch, switching the clock source, and then ungating the clock.
Changing the fractional divider ratio is also glitch-less and will use one of two mechanisms. When used in a switch with a
clock source selection mux, the switching state-machine described above is used. When used without a clock source
selection mux such as in the pllP_out1,2,3,4,5 dividers, the divider is not stopped and seamlessly switches to the new
frequency at the end of a clock period. In this latter scheme, no dead cycles exist– between the original frequency and then
the newly requested frequency.
In all structures above, when the clock is gated off, it occurs at the end of the clock period so that 1) there are no runt pulses,
and 2) the output clock will be stopped low.
5.2.4 Custom Core Clocks
5.2.4.1 FCPU Clock

The following figure shows a block diagram of the components of the Fast CPU (FCPU) clocking.

Figure 5: FCPU Clock Generation
CAR
Software SOC_Therm
Registers HW Controls
Ramp
Controller
SOC_Therm
HW Controls
Ctrls DynFreq
SOC_Therm
Oscillator
PLLX Div2
Clock
Skipper
/2
div CG cpu_clk
ftm
Clock Switch
Oscillator DFLL
/N fcpu_atclks_clken
/2 fcpu_periphclk_clken
PLLX
PLLX is one of two possible primary clock sources for the FCPU. It contains two dynamic frequency mechanisms: a fast one
that could overshoot and a slower one with no overshoot.
DFLL
The alternate primary clock source for the FCPU is the DFLL. The DFLL is based around a ring oscillator with supporting
structures for di/dt management and frequency control.
Clock Skipper
An M/N clock skipper that is managed by the SOC Thermal module.
SOC Therm Div 2

This logic will slow the CPU clock to manage thermal runaway.
Clock Switch
The clock switch consists of a clock source selection mux that can switch glitchlessly between a number of clock sources
including the PLLX and DFLL. This is followed by a programmable U7.1 divider. For low jitter when the divider is not required,
a direct bypass path from PLLX or DFLL inputs to the output is also provided.
The following figure shows the details of the clock switch, clock skipper, SOC Therm Div 2, and root clock generation. The
clock sources to the clock source selection mux are described in the table entitled “Root Clock Clock Sources” in the “Main
Clock Sources” section.

Figure 6: FCPU Clock Details
Clock
skip 1
super clk div2

cpu_clk_switch
divider 0
UI_cpu_car_clk (clk skip)
CG
cclk_sel
int_car_cclk
dfllCPU_out
pllX_out soc_therm_fcpu_div2_sync UI_cpu_clk
UI_clk_mux
0 CG
cpu_clk_ss
muxed_clk out_clk
0
UI_test_mux
int_out_clk
CG 0 1
muxed_ftm_clk
1
enb_out_clk
FTM 1
test_t1clk
OR
test_t1clk
T tmc2clk_fast_test_mode_cpu
low_jitter_clk_sel
tmc2clk_bypass_t1clk
low_jitter_clk_sel2
tmc2clk_disable_clock_gating
sync
nor
cpu_part_clk_drv_ftop
clock
func_dis_clk
car_clk_m switch mpcore_clk
FSM
scan scan_dis_clk
debug disable_clock_gating
clk2tmc_polling
FSM
/N fcpu_atclks_clken
disable_clock_gating
/2 fcpu_periphclk_clken
5.2.4.2 SCPU Clock

The following figure shows the details of the Clock Switch, Clock Skipper, and root clock generation for the Slow CPU (SCPU).
The clock sources to the clock source selection mux are described in the table entitled “Root Clock Clock Sources” in the
“Main Clock Sources” section.

Figure 7: SCPU Clock Details
cpulp_clk_switch super clk

divider
(clk skip)
CG
cclk_sel
int_car_cclk
pllX_out
UI_clk_mux
UI_cpulp_clk
muxed_clk UI_test_mux
0 CG
int_out_clk out_clk
CG 0
muxed_ftm_clk 1
enb_out_clk
FTM 1
test_t6clk
OR
test_t6clk T low_jitter_clk_sel
tmc2clk_fast_test_mode_cpu
tmc2clk_disable_clock_gating
sync
nor
clock cpu_part_clk_drv_stop
func_dis_clk
car_clk_m switch
FSM
mpcorelp_clk
scan scan_dis_clk
debug
clk2tmc_polling
FSM disable_clock_gating
/N scpu_atclks_clken
disable_clock_gating
/2 scpu_periphclk_clken
5.2.4.3 EMC/MC Clock

The PLLM’s primary purpose is to clock the MC and EMC. The EMC/MC clocking structure is complicated due to the need to
support high speed DRAMs, avoid clock switching when DRAMs are being accessed, and conserve power.
When changing the EMC frequency, internal logic sequencing handles the requirement that the DRAMs must be placed into
self-refresh before the clock frequency is changed. Certain register fields when written do not get immediately applied but
rather are applied at the correct time during the sequencing. These registers are referred to as "shadowed". Other register
fields initiate the sequencing state-machine and therefore should be written last. At the end of the sequencing, the DRAMs are
restored to being operational.
The reprogramming sequence is:
1. Program the MC/EMC shadow registers corresponding to the new frequency. These registers are “shadowed”, as
noted in their descriptions, and will not impact the hardware until later during the clock change sequence.
2. Program the EMC clock change FIFO (CCFIFO) with the pre-/post-clock change sequence.
3. Program CAR CLK_SOURCE_EMC register to trigger a clock change. At this point hardware takes the following
actions:
 The CAR block asserts the clock change request to the EMC.
 The EMC stops MC transactions, flushes its internal outstanding requests, executes MRSs/enter self-refresh,
and then updates the timing to copy the EMC shadow
 Register contents (including CDB phase select) to EMC current register.
 The EMC asserts clock change acknowledge to the CAR block.
 The CAR stops the clock to PLLM/CDB, updates to the new clock source, and passes the EMC CDB phase
select control to the CDB.
 The CAR re-enables the clock to PLLM/CDB.
 The CAR de-asserts the clock change request to the EMC (telling it the clock change is done).

 The EMC unblocks MC transactions, de-asserts clock change acknowledge.

 The EMC executes the post clock change sequence (self-refresh exit, MRSs).
 Normal memory access resumes.
4. Software monitors the clock change complete interrupt status from the EMC register to know when the clock change
is done.
5.2.4.4 SYS Clock Generation (SCLK, HCLK, PCLK)

The system clock sclk is used by the AVP sub-system (COP), hclk is the AHB bus clock, and pclk is the APB bus clock.
Figure 8: SCLK Clock Generation
T = clock trimmer CG = clock gate
sys_clk_switch
pllM_out1
ck32khz_IB
pllC_out
UI_clk_mux
pllP_out2
muxed_clk
pllP_out
UI_test_mux
int_clk int_out_clk
pllP_out4
test_clk_trim CG super clk
pllC_out1 out_clk sclk_sel
divider
dbg_oscout (clk skip)
test_clk FTM sync_enb_sclk
sync
test_clk enb_out_clk sclk_sys_clk_tt
T fast_test_mode CG
nor
clock Divider sync_enb_hclk
car_clk_m
switch func_dis_clk (clk skip)
FSM hclk_sys_clk_tt
CG
scan scan_dis_clk
debug clk2tmc_polling
FSM Divider sync_enb_pclk
(clk skip)
pclk_sys_clk_tt
CG
5.2.4.5 Jtag_ref_clk and fuse_clk

The RAMs in the Fast CPU need to support RAM repair. Since the power rail to the FCPU will be shut down in modes such as
LP1, the RAM repair information will be lost. When power is returned, the RAM repair information needs to be reprogrammed.
A faster clock is needed to avoid delays in bringing the FCPU online. Additionally, a synchronous clock relationship is
temporarily needed between the fuse and the re-repair logic running on the JTAG clock.

Figure 9: Jtag_ref_clk and fuse_clk Clock Generation
jtag_fast_mode
jtag_clk_out 0
Glitchless
ClkPlanner
jtag_tck_IB jtag_tck_part_ctr_IB 1
Jtag_port_clk
0
Jtag_reg_clk ClkPlanner To Modules:
Glitchless
Sdbg
Trim jtag_controller
1 (s1_selected->jtag_clk_ready) test_bus_core
Jtag Registers
reshift_clk_req fast_clk_ tbc2clk_req
with_repair_freq (!TRST_ | tbc2clk_req0 | reshift_clk_switch_req)
pllP_out0 (No test mode bypass clk)
(408MHz)
CG ÷
Ratio
(1..128)(divw=8)
jtag_intfc_clk Jtag_intfc_clk_tt ClkPlanner
1
Sdbg CG fuse_clk
Trim
Glitchless
OSCFI To Modules:
dbg_osc_out ClkPlanner
0
(s1_selected->clk2jtag_reshift_clk_switch_ack)
CG fuse2jtag_clk NV_fuse
fuse2jtag Interface
(Xtal_in)
reshift_clk_req CG host2jtag_clk
ClkPlanner
Sdbg CG
Trim
jtag2tbc_intfc_clk
clk_m_sys Sdbg CG
test_mux Trim
car_clk_m
CG mca_clk_m
CG mcb_clk_m
... cpu_clk_m cpulp_clk_m ao_clk_m dis_clk_m disb_clk_m

usx_clk_m usb_phy_clk_m kfuse_clk tmr_clk ahb_clk_m
apb_clk_m xusb_clk_m xusb_vcore_ao_clk_xusba
xusb_vcore_ao_clk_xusbc
5.3 PLLs
5.3.1 DFLLCPU
DFLLCPU is a dedicated clock source for the Fast CPU. The DFLL is based on a ring oscillator and translates voltage
changes into frequency compensation changes needed to prevent the CPU from failing.
5.3.2 PLLX
Tegra K1 devices require an alternative clock source in addition to DFLLCPU. Additionally, for EDP management and to avoid
creating di/dt problems, this PLL needs a dynamic frequency changing mechanism.
Similar to prior Mobile products, PLLX is dedicated for this purpose. This PLL will feed to both the Fast CPU Cluster and
Shadow CPU. This PLL cannot be easily used opportunistically for other units.
5.3.2.1 PLLX Startup Sequence

PLLX has additional logic for support of dynamic ramp. To improve leakage power, additional logic in the PLL is also power-
gated with help of an IDDQ control. The sequence between IDDQ and ENABLE is detailed below.
1. After powering up, the PLL rails (in case of LP0 exit), change IDDQ from 1 to 0.
2. Wait for 2 µs.
3. Program PLL parameters in registers.
4. Change ENABLE from 0->1 while the reference clock is running and stable.
5. ENABLE=1 and IDDQ=1->0 is not allowed for starting PLL.

5.3.3 refPLLE, PLLE, USB3 Brick PLLs

USB 3.0 requires a spread spectrum (SS) clock. It also has stringent jitter requirements to be met. A spread-spectrum PLL
with high VCO frequency (for low jitter) meets these requirements. A dedicated PLL (PLLE) is used for this purpose.
In addition to PLLE, to ensure that oscillator clock jitter gets filtered out prior to feeding it to PLLE, a reference PLL (refPLLE) is
required. There are additional PLL(s) in the pad brick used for physical layer signaling for USB 3.0. For cases where spread
spectrum might not be required and jitter may not be an issue, an option is kept to bypass PLLE to save power. This option
requires that the crystal be 12 MHz or 48 MHz to be able to create the required PLLE output frequency of 100 MHz.
5.3.4 PLLU and UTMI PLL

USB 2.0 mode requires 8 phase data sampling logic per USB 2.0 port to capture data. This requires a dedicated PLL
(UTMI_PLL) with 5 data sampling logic ports. XUSB needs 2 samplers (that is, one for host mode and one for device mode).
Synopsys IP needs 3.
The dedicated PLL (PLLU) is used to generate the low jitter reference clock for UTMI_PLL. There is a provision to bypass
PLLU for cases where a slightly higher jitter is acceptable for UTMI PLL reference clock. USB2 mode requires 8 phase data
sampling logic per USB2 port to capture data. This requires a dedicated PLL (UTMI_PLL) with 5 data sampling logic ports.
5.3.5 PLLM
The DDR interface in Tegra K1 devices is required to operate at 1866 MT/s. This means that the EMC should work at 933
MHz and the MC should work at 466 MHz. The memory subsystem (DDR, EMC, and MC) is required to support a number of
discrete frequencies such as DDR1866, DDR 1600, DDR 1333, DDR 1066, DDR 800 as well as slower frequencies to
conserve power. A dedicated PLL (PLLM) is used for memory clocks.
DDR interface signaling also needs a DLL to support ¼ clock shift to reliably capture/drive DQ. In addition, a CDB (clock
distribution buffer) is required to get a low jitter/skew clock for each byte/command group.
5.3.6 PLLA and PLLP

All audio clocks are a multiple of the sampling frequency which can be 32 KHz, 44.1 KHz or 48 KHz. A frequency of 56.448
MHz or 73.728 MHz can be used to generate any of these sampling rates. It is not possible to generate both of these
frequencies from the osc_freq by just using PLLA so a cascade of 2 PLLs, PLLP to PLLA, is required to generate the audio
clocks.
PLLP is fixed at generating 408 MHz, and PLLA takes in 9.6 MHz (PLLP / 42.5) to generate the two required audio
frequencies.
Because PLLP generates a fixed frequency clock for audio, it can also be divided down and used for other modules which
might need a fixed frequency clock.
Most audio codecs have their own PLL, which turns out to be more power efficient, so it is possible that PLLA does not get
used in a typical system for audio. In such a case PLLA can be used as a general purpose PLL.
5.3.7 Display Clocks and PLLs (PLLD, PLLD2, and PLLDP)

The display requires three PLLs:
 PLLD (MIPI PLL) – Used to feed CSI/DSI pads.

 PLLD2 (SS PLL) – Used for HDMI
 PLLDP – Used for eDP/LVDS
PLLD is a dedicated PLL (with differential clock outputs and some DSI specific functionality) which should be used for DSI0
and DSI1. This PLL can be configured to generate the pixel clock from any oscillator frequency. These PLLs consume high

power (estimated at 4 times a regular general purpose PLL) and should be used only if DSI is required. For HDMI, the pad
brick has PLLs which are used for interface signaling. These PLLs expect a pixel clock as an input.
5.3.7.1 PLLD and PLLD2 Startup Sequence

Additional logic in the PLL is also power-gated with help of an IDDQ control. The sequence between IDDQ and ENABLE is
detailed below.
1. After powering up the PLL rails (in case of LP0 exit), change IDDQ from 1 to 0.
2. Wait for 2 µs.
3. Program PLL parameters in registers
4. Change ENABLE from 0->1 while the reference clock is running and stable.
5. ENABLE=1 and IDDQ=1->0 is not allowed
5.3.8 PLLC, PLLC2, PLLC3, and PLLC4

The AVP (300MHz), MSENC (333 MHz), imaging (VI/ISP – 600 MHz), VDE (366 MHz) and various other high frequency
peripherals have different maximum frequency requirements. PLLC2 and PLLC3, can go up to 700 MHz, are used for these
modules.
PLLC4 is used to provide 600 MHz dedicated output to VI and ISP blocks.
5.3.8.1 PLLC and PLLC4 Startup Sequence

PLLC has additional logic for support of dynamic ramp. Additional logic in the PLL is also power-gated with help of an IDDQ
control. The sequence between IDDQ and ENABLE is detailed below.
1. After powering up the PLL rails (in case of LP0 exit), change IDDQ from 1 to 0.
2. Wait for 2 µs.
3. Program PLL parameters in registers.
4. Change ENABLE from 0->1 while reference clock is running and stable.
5. ENABLE=1 and IDDQ=1->0 is not allowed.
5.3.8.2 Digital PLLs (PLLC2, PLLC3) Startup Sequence

To save more power, additional power gating is implemented in digital PLLs; the additional ENABLE control has a
corresponding register bit added.
1. PLL rails are turned ON (in case they are OFF when coming out from LP0)
2. IDDQ changes from 1 to 0 with ENABLE being 0
3. Program the PLL parameters
4. ENABLE is also asserted with guarantee that the reference clock is running.
5. ENABLE=1 and IDDQ=1->0 is not allowed.
5.3.9 GPU PLL

The GPU uses a dedicated GPCPLL inside the GPU core (PLL20G_DYN_PRB_ESD). This PLL has dynamic frequency
scaling capabilities and generates a 400 MHz gpcclk.

5.4 Reset Architecture

The external PMC provides the primary power-on reset (SYS_RESET_N_). Apart from POR, some other events can also
result in a system reset. These are:
1. Reset due to an indication from a thermal sensor. The thermal sensor module would assert a reset signal
tsensor2pmc_reset, which would in turn generate a reset for the whole chip and in the process de-assert
tsensor2pmc_reset itself.
2. Expiry of watchdog timer. The watchdog timer has a counter which is loaded with an initial value and ticks on periodic
intervals. Once the counter expires, it reloads itself with the initial value, increments an expiry count, and generates
an event for software. If software acknowledges the event, the expiry count is cleared and the counter is loaded back
with initial value. This process continues indefinitely. Depending on the current expiry count, the event generated for
software could be different. There are 2 types of watchdog timers in Tegra K1 systems depending on how they
generate the reset:
 Deadman timer (referred as WDT in reset code): This is the legacy implementation in which:
1st expiry an interrupt is issued
2nd expiry a reset is issued. This reset, however, resets only a subset of units.
 Watchdog timer (referred as WDT2 in reset code):
1st expiry – interrupt is issued
2nd expiry – FIQ is issued
3rd expiry – CPU reset is issued
4th expiry – full system reset – This is the relevant reset for this section
3. Software reset. This reset is controlled by a configuration bit in the PMC address space (main_swrst). Once asserted,
this result in a reset generation for the whole chip and in the process de-asserts itself.
4. LP0 wakeup reset. This is controlled by the logic within the PMC.
The POR (SYS_RESET_N_) is de-asserted by the external PMC after the power sequencing is done and after the RTC clock
(clk_32KHz) and crystal clock is already running. For the other sources, the reset is originated within the Tegra K1 hardware.
5.5 Power Gating and Ungating
5.5.1 Clamp/Reset/Clock/PG-Enable Sequencing
5.5.1.1 Power Gating

For power-gating (powering off) a partition, the clamp, reset, clocks, and PG-enable (also known as sleep-enable) controls
must be sequenced as shown in following diagram. For CCPLEX PG partitions, this sequencing is ensured by hardware (when
power-gating is done via the flow controller). For SoC (non-CCPLEX) PG partitions, this sequencing needs to be ensured by
software.
The following registers are used for the Clamp/PG-Enable control of each PG partition:
 PMC_PWRGATE_TOGGLE
 PMC_REMOVE_CLAMPING_CMD
The following registers are used for the Clock/Reset control of each unit:
 RST_DEVICES_L/H/U/V/W/X
 CLK_OUT_ENB_L/H/U/V/W/X
In general, clamp-enable should be asserted before reset (as shown in the diagram). This works with synchronous or
asynchronous clamping. However, if a unit can guarantee that its output signals will have the same clamp values as their pre-

clamp values (idle values) as well as their reset values, then clamp and reset ordering is not critical. Note it is non-trivial to
verify the above guarantee.
Figure 10: Power-Gating Timing Sequence for Clamp/Reset/Clock/PG-Enable
Clamp
Enable
Reset
Clock
Pwr Gate
Enable
Virtual VDD
5.5.1.2 Power Ungating

For power-ungating (powering on) a partition, we have to ensure that clamp, reset, clocks, and PG-enable (sleep-enable)
controls are sequenced as shown in the following diagram. For CCPLEX PG partitions, this sequencing is ensured by
hardware (when power-gating is done via the flow controller). For SoC (non-CCPLEX) PG partitions, this sequencing needs to
be ensured by software.
In general, the clamp enable should be de-asserted before reset (as shown in the diagram). This works with synchronous or
asynchronous clamping. However, if a unit can guarantee that its output signals will have same clamp values as its post-clamp
values (idle values), then clamp and reset ordering is not critical for power ungating. Note it is non-trivial to verify the above
guarantee.
Figure 11: Power-Ungating Timing Sequence for Clamp/Reset/Clock/PG-Enable
Power
Gate
Enable
Virtual VDD
Clock
Clamp
Enable
Reset
5.5.2 Power-Gating Controller

The PMC provides power-gating controllers as programmable sequencers. When the power gating/ungating in is triggered, the
controller sequences PG-enable signals with a programmable delay (measured in APB clock cycles) between consecutive
“zones” PG-enable controls. There are two types of power-gating controllers: CPU and SOC power-gating controllers. The
following sections describe both types of controllers.
5.5.2.1 SOC Power-Gating Controller

The SOC power-gating controller is used to sequence power gating of SOC (including shadow CPU cluster) power partitions.
It uses 8 zones and shares the same programming register for inter-zone delays. The zones are powered up in one order and
powered down in reverse order, using the same inter-zone timings. So only one set of delays are used for both powering down
and up.
For all non-CPU SOC partitions, power-gating can only be turned on/off by direct register write. For CPU (shadow) SOC
partitions, power-gating can be turned on/off via flow-controller. Refer to “SOC Power Gating Controllers” in the PMC section.
GPU Power Gating

The GPU power gating is controlled by the GPMU unit inside the Kepler GPU. This is independent of the SOC/CPU power-
gating control.
If the GPU has its own rail, then the software mutual exclusion for GPU ELPG and SoC power gating is not needed. But for a
heavily cost reduced system where the GPU and SoC might share a rail, the software must interlock the two mechanisms in
order to avoid di/dt problems (which could result if the two mechanisms were to alter power gating state simultaneously).
5.5.2.2 Fast CPU Power-Gating Controller

The fast CPU power-gating controller is used to sequence power-gating of fast CPU partitions. All CPU partitions (CE0/1/2/3
and C0NC) share the same programming register for inter-zone delays, which are different from inter-zone delays in SoC
partitions. The zones are powered up in one order and powered down in reverse order, using the same inter-zone timings. So
only one set of delays are used for both powering down and up. For fast CPU partitions, power gating can be turned on/off via
the flow controller. Refer to “CPU-G Power Gating Controllers” in the PMC section.
5.6 Software Features and Programming Model
5.6.1 Clock Control

The figure below illustrates the software clock control model.

Figure 12: Clock Control
5.6.2 PLL Programming

PLL output frequencies are programmed by setting their N, M, and P values. The governing equations are:
VCO = (Fi / M) * N,
Fo = VCO / (2 ^ P)
where Fo is the output frequency from the PLL.
Note: Not all PLLs have the simple mapping for the P value listed above. Contact your NVIDIA
representative for assistance.
There are three requirements for each PLL that must be complied with:
 Each PLL has a legal input frequency (Fi) range.

 Each PLL has a legal comparison frequency (CF) range, where CF = Fi / M
 Each PLL has a legal VCO frequency range, where VCO = CF * N.
To change a PLL, do the following:
 Ensure that no enabled module is using the PLL that will change.
 Program the new PLL settings
 Wait for PLL stabilization
 Change the divider values for each clock that will use the PLL to divide-down to the target frequency, and change the
module clock sources for all modules that will use the new PLL settings.
5.6.3 Clock Division Control

The ratio as defined by the 1/divisor for an 8-bit fractional divider, of 7 bits of d and 1 bit of h is:

divisor = (ddddddd + 1) + (h * 0.5)
The divisor for UART 16b integer divider it is:
divisor = (dddddddddddddddd)
The divisor for the I2C 16b integer divider it is:
divisor = (dddddddddddddddd + 1)
5.6.4 Changing Clock Sources and Clock Dividers

Changing a clock source (except the clock sources to the audio_sync_clk) to a running module is "glitch free". The clock
source and divide ratio can be set concurrently without creating spurious frequencies. For the audio_sync_clk, the clock
source select needs to be set up before changing the device clock source to use that audio clock or to enable the device which
uses that audio clock.
The glitch-free clock divider to a running module can also be changed. All modules support changing the clock divider ratio
without disabling the clock; write the new divider to the appropriate register See the section on Power below.
To change the clock source and divider (either after system reset or for any other reason), follow this sequence:
Sequence 1 to change clock source and divider:
1. Assert reset to the module if it is not already asserted

2. Enable clock to the module if the clock is not already enabled
3. Change the clock divider and/or the clock source to the module
4. Wait 2 µs for the clock to flush through the pipe / logic.
5. De-assert reset to the module.

5.6.5 Clock Gating (Override)

Please refer to the register definition section for more information.
5.6.5.1 Power
The following guidelines should be followed in pursuit of the lowest use-case power consumption:
 Target the least number of PLLs running at their lowest allowable frequencies for the given use-case.
 For each module, use the source with the lowest frequency that provides adequate performance for the use case.
 Turn off all clocks not required for the given use-case - employ maximum clock-gating.
 Use hardware dynamic clock bursting whenever possible. Turn on the desired frequency, burst to completion, and
then disable the input frequency (allowing PLLs to be turned off or their output frequencies to be lowered)
 Use the CPU and COP/system super clock divider for lower CPU frequency where possible.
 Disable the oscillator input and/or clock outputs when they are not in use.
5.6.6 Programming Guide for Power Gating and Ungating

This section covers the software procedures for power gating and ungating of SOC power domains. Power gating and
ungating of CPU power domains is not covered here because it is handled through the Flow Controller.
5.6.6.1 Procedure Summary

The general procedure for power gating an SOC power domain is as follows:
1. Write MC register to flush and block MC clients

2. Write CAR register to assert unit resets
3. Write CAR register to disable clocks
4. Write PMC register to gate power domain
The general procedure for power ungating an SOC power domain is as follows:
1. Write PMC register to ungate power domain

2. Write CAR register to enable clocks
3. Write CAR register to de-assert resets
4. Write MC register to enable MC clients
In some cases, partitions require specific deviations from the general procedure. Deviations are covered in the domain-specific
sections below.
This table summarizes the respective clock and reset bits and MC clients in each SOC power domain.
Table 19: MC Clients for Clocks and Resets per Domain
Domain Units MC Clients
VE VI, CSI, ISP VI, ISP
VE2 ISPB ISP2B
VDE VDE VDE
PCX AFI AFI
MPEA MSENC MSENC
SAX SATA SAX

Domain Units MC Clients
DIS DISPLAY DC
DISB DISPLAYB DCB
SOR MIPI_CAL, DPAUX, SOR, HDMI, DSI, DSIB None
XUSBB XUSB_DEV XUSB_DEV
XUSBC XUSB_HOST XUSB_HOST
VIC VIC VIC
5.6.6.2 Procedures for VE Power Domain
VE Power Gating
1. Flush MC clients VI and ISP by setting the following bits:
 MC_CLIENT_HOTRESET_CTRL_0.VI_FLUSH_ENABLE
 MC_CLIENT_HOTRESET_CTRL_0.ISP2_FLUSH_ENABLE
 MC_CLIENT_HOTRESET_CTRL_1_0.ISP2B_FLUSH_ENABLE
Also Poll MC_CLIENT_HOTRESET_STATUS_1_0 until ISP2B_HOTRESET_STATUS is set.
2. Poll MC_CLIENT_HOTRESET_STATUS_0 until the following bits are set:
 VI_HOTRESET_STATUS
 ISP2_HOTRESET_STATUS
3. Set the following bits to assert reset to VI, ISP, ISPB, and CSI:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0.CLK_ENB_VI
 CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0.CLK_ENB_ISP
 CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0.CLK_ENB_ISPB
 CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0.CLK_ENB_CSI
 CLK_RST_CONTROLLER_CLK_OUT_ENB_W_0.CLK_ENB_CILAB
 CLK_RST_CONTROLLER_CLK_OUT_ENB_W_0.CLK_ENB_CILCD
 CLK_RST_CONTROLLER_CLK_OUT_ENB_W_0.CLK_ENB_CILE
4. Clear the following bits to disable clocks to VI, ISP, ISPB, and CSI:
5. Write to these APBDEV_PMC_PWRGATE_TOGGLE_0 fields with the following settings:
 PARTID = VE
 START = ENABLE
6. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the VE bit is set
VE Power Ungating
 PARTID = VE
 START = ENABLE
2. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the VE bit is cleared
3. Set the following bits to enable clocks to VI, ISP, ISPB, and CSI:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0.CLK_ENB_ISPB
4. Remove power-gating clamps by writing a 1 to the following bit:
 APBDEV_PMC_REMOVE_CLAMPING_CMD_0.VE
5. Poll APBDEV_PMC_REMOVE_CLAMPING_CMD_0 until the VE bit is cleared
6. If needed, clear the following bits to de-assert the reset to VI, ISP, ISPB, and CSI:
 CLK_RST_CONTROLLER_RST_DEVICES_L_0.SWR_VI_RST
 CLK_RST_CONTROLLER_RST_DEVICES_L_0.SWR_ISP_RST
 CLK_RST_CONTROLLER_RST_DEVICES_X_0.SWR_ISPB_RST
 CLK_RST_CONTROLLER_RST_DEVICES_H_0.SWR_CSI_RST
7. Enable MC clients VI and ISP by clearing the following bits:
 MC_CLIENT_HOTRESET_CTRL_0.VI_FLUSH_ENABLE
 MC_CLIENT_HOTRESET_CTRL_0.ISP2_FLUSH_ENABLE
 MC_CLIENT_HOTRESET_CTRL_1_0.ISP2B_FLUSH_ENABLE
5.6.6.3 Procedures for VDE Power Domain
VDE Power Gating

1. Flush the VDE MC client by setting the following bit:
 MC_CLIENT_HOTRESET_CTRL_0.VDE_FLUSH_ENABLE
2. Poll MC_CLIENT_HOTRESET_STATUS_0 until the following bit is set:
 VDE_HOTRESET_STATUS
3. Set the following bits to assert the reset to the VDE:
 CLK_RST_CONTROLLER_RST_DEVICES_H_0.SWR_VDE_RST
 CLK_RST_CONTROLLER_RST_DEVICES_H_0.SWR_BSEV_RST
4. Clear the following bits to disable clocks to the VDE:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0.CLK_ENB_VDE
 CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0.CLK_ENB_BSEV
 PARTID = VDE
 START = ENABLE
6. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the VDE bit is set

VDE Power Ungating

 PARTID = VDE
 START = ENABLE
2. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the VDE bit is cleared
3. Set the following bits to enable clocks to the VDE:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0.CLK_ENB_VDE
 CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0.CLK_ENB_BSEV
 APBDEV_PMC_REMOVE_CLAMPING_CMD_0.VDE
5. Poll APBDEV_PMC_REMOVE_CLAMPING_CMD_0 until the VDE bit is cleared
6. Clear the following bits to de-assert the reset to the VDE:
 CLK_RST_CONTROLLER_RST_DEVICES_H_0.SWR_VDE_RST
 CLK_RST_CONTROLLER_RST_DEVICES_H_0.SWR_BSEV_RST
7. Enable the VDE MC client by clearing the following bit:
 MC_CLIENT_HOTRESET_CTRL_0.VDE_FLUSH_ENABLE
5.6.6.4 Procedures for PCX Power Domain
PCX Power Gating

1. Flush the AFI MC client by setting the following bit:
 MC_CLIENT_HOTRESET_CTRL_0.AFI_FLUSH_ENABLE
2. Poll MC_CLIENT_HOTRESET_STATUS_0 until the following bit are set:
 AFI_HOTRESET_STATUS
3. Set the following bits to assert the reset to the PCIE and AFI:
 CLK_RST_CONTROLLER_RST_DEVICES_U_0.SWR_PCIE_RST
 CLK_RST_CONTROLLER_RST_DEVICES_U_0.SWR_AFI_RST
 CLK_RST_CONTROLLER_RST_DEVICES_U_0.SWR_PCIEXCLK_RST
4. Clear the following bits to disable clocks to PCIE and AFI:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0.CLK_ENB_PCIE
 CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0.CLK_ENB_PCIERX0
 CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0.CLK_ENB_AFI
 PARTID = PCX
 START = ENABLE
6. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the PCX bit is set

PCX Power Ungating

 PARTID = PCX
 START = ENABLE
2. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the PCX bit is cleared
3. Set the following bits to enable clocks to PCIE:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0.CLK_ENB_PCIE
 CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0.CLK_ENB_AFI
 APBDEV_PMC_REMOVE_CLAMPING_CMD_0.PCX
5. Poll APBDEV_PMC_REMOVE_CLAMPING_CMD_0 until the PCX bit is cleared
6. Clear the following bits to de-assert the reset to the PCX:
 CLK_RST_CONTROLLER_RST_DEVICES_U_0.SWR_PCIE_RST
 CLK_RST_CONTROLLER_RST_DEVICES_U_0.SWR_AFI_RST
 CLK_RST_CONTROLLER_RST_DEVICES_U_0.SWR_PCIEXCLK_RST
7. Enable the AFI MC client by clearing the following bit:
 MC_CLIENT_HOTRESET_CTRL_0.AFI_FLUSH_ENABLE
5.6.6.5 Procedures for MPE Power Domain
MPE Power Gating

1. Flush the MSENC MC client by setting the following bit:
 MC_CLIENT_HOTRESET_CTRL_0.MSENC_FLUSH_ENABLE
 MSENC_HOTRESET_STATUS
3. Set the following bit to assert the reset to the MSENC:
 CLK_RST_CONTROLLER_RST_DEVICES_U_0.SWR_MSENC_RST
4. Clear the following bit to disable clocks to the MSENC:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0.CLK_ENB_MSENC
 PARTID = MPE
 START = ENABLE
6. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the MPE bit is set
MPE Power Ungating

 PARTID = MPE

 START = ENABLE
2. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the MPE bit is cleared
3. Set the following bits to enable clocks to the MSENC:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0.CLK_ENB_MSENC
 APBDEV_PMC_REMOVE_CLAMPING_CMD_0.MPE
5. Poll APBDEV_PMC_REMOVE_CLAMPING_CMD_0 until the MPE bit is cleared
6. Clear the following bits to de-assert the reset to the MSENC:
 CLK_RST_CONTROLLER_RST_DEVICES_U_0.SWR_MSENC_RST
7. Enable the MSENC MC client by clearing the following bit:
 MC_CLIENT_HOTRESET_CTRL_0.MSENC_FLUSH_ENABLE
5.6.6.6 Procedures for SAX Power Domain
SAX Power Gating

1. Flush the SATA MC clients by setting the following bit:
 MC_CLIENT_HOTRESET_CTRL_0.SATA_FLUSH_ENABLE
 SATA_HOTRESET_STATUS
3. Set the following bits to assert the reset to SATA:
 CLK_RST_CONTROLLER_RST_DEVICES_V_0.SWR_SATA_RST
 CLK_RST_CONTROLLER_RST_DEVICES_W_0.SWR_SATACOLD_RST
4. Clear the following bit to disable clocks to SATA:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_V_0.CLK_ENB_SATA
 PARTID = SAX
 START = ENABLE
6. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the SAX bit is set
SAX Power Ungating

 PARTID = SAX
 START = ENABLE
2. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the SAX bit is cleared
3. Set the following bit to enable clocks to SATA:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_V_0.CLK_ENB_SATA
 APBDEV_PMC_REMOVE_CLAMPING_CMD_0.SAX
5. Poll APBDEV_PMC_REMOVE_CLAMPING_CMD_0 until the SAX bit is cleared
6. Clear the following bits to de-assert the reset to SAX:
 CLK_RST_CONTROLLER_RST_DEVICES_V_0.SWR_SATA_RST
 CLK_RST_CONTROLLER_RST_DEVICES_W_0.SWR_SATACOLD_RST

7. Enable the SATA MC clients by clearing the following bit:

 MC_CLIENT_HOTRESET_CTRL_0.SATA_FLUSH_ENABLE
5.6.6.7 Procedures for DIS Power Domain
DIS Power Gating

The VE power domain has to be gated before the DIS can be gated.
1. Flush the DC MC client by setting the following bit:

 MC_CLIENT_HOTRESET_CTRL_0.DC_FLUSH_ENABLE
 DC_HOTRESET_STATUS
3. Set the following bit to assert the reset to DISP1:
 CLK_RST_CONTROLLER_RST_DEVICES_L_0.SWR_DISP1_RST
4. Clear the following bit to disable clocks to DISP1:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0.CLK_ENB_DISP1
 PARTID = DIS
 START = ENABLE
6. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the DIS bit is set
DIS Power Ungating

DIS power ungating requires the SOR to be ungated as well.
1. Write to APBDEV_PMC_PWRGATE_TOGGLE_0 with the following fields:

 PARTID = DIS
 START = ENABLE
2. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the DIS bit is cleared
3. Set the following bit to enable clocks to DISP1:
 APBDEV_PMC_REMOVE_CLAMPING_CMD_0.DIS
5. Poll APBDEV_PMC_REMOVE_CLAMPING_CMD_0 until the DIS bit is cleared
6. Clear the following bit to de-assert the reset to DISP1:
7. Enable the DC MC client by clearing the following bit:
 MC_CLIENT_HOTRESET_CTRL_0.DC_FLUSH_ENABLE
5.6.6.8 Procedures for DISB Power Domain
DISB Power Gating

1. Flush the DCB MC client by setting the following bit:
 MC_CLIENT_HOTRESET_CTRL_0.DCB_FLUSH_ENABLE

 DCB_HOTRESET_STATUS
3. Set the following bit to assert the reset to DISP2:
4. Clear the following bits to disable clocks to DISP2:
 PARTID = DISB
 START = ENABLE
6. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the DISB bit is set
DISB Power Ungating

DISB power ungating requires the SOR to be ungated as well.

 PARTID = DISB
 START = ENABLE
2. Poll APBDEV_PMC_PWRGATE_STATUS_0 until bit DISB is clear
3. Set the following bits to enable clocks to DISP2:
 APBDEV_PMC_REMOVE_CLAMPING_CMD_0.DISB
5. Poll APBDEV_PMC_REMOVE_CLAMPING_CMD_0 until the DISB bit is cleared
6. Clear the following bits to de-assert reset to DISP2:
7. Enable the DCB MC client by clearing the following bit:
 MC_CLIENT_HOTRESET_CTRL_0.DCB_FLUSH_ENABLE
5.6.6.9 Procedures for SOR Power Domain
SOR Power Gating

SOR can only be power gated when both DIS and DISB are gated.
1. Set the following bits to assert the reset to MIPI_CAL, DPAUX, SOR, HDMI, DP2, DSI and DSIB:
 CLK_RST_CONTROLLER_RST_DEVICES_H_0.SWR_MIPI_CAL_RST
 CLK_RST_CONTROLLER_RST_DEVICES_X_0.SWR_DPAUX_RST
 CLK_RST_CONTROLLER_RST_DEVICES_X_0.SWR_SOR0_RST
 CLK_RST_CONTROLLER_RST_DEVICES_H_0.SWR_HDMI_RST
 CLK_RST_CONTROLLER_RST_DEVICES_H_0.SWR_DSI_RST
 CLK_RST_CONTROLLER_RST_DEVICES_U_0.SWR_DSIB_RST
 CLK_RST_CONTROLLER_RST_DEVICES_W_0.SWR_DP2_RST
 CLK_RST_CONTROLLER_RST_DEVICES_W_0.SWR_ HDA2HDMICODEC_RST
2. Clear the following bits to disable clocks to MIPI_CAL, DPAUX, SOR, HDMI, DP2, DSI and DSIB:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0.CLK_ENB_MIPI_CAL
 CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0.CLK_ENB_DPAUX

 CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0.CLK_ENB_SOR0
 CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0.CLK_ENB_HDMI
 CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0.CLK_ENB_HDMI_AUDIO
 CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0.CLK_ENB_DSI
 CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0.CLK_ENB_DSIB
 CLK_RST_CONTROLLER_CLK_OUT_ENB_W_0.CLK_ENB_DSIA_LP
 CLK_RST_CONTROLLER_CLK_OUT_ENB_W_0.CLK_ENB_DSIB_LP
 CLK_RST_CONTROLLER_CLK_OUT_ENB_W_0.CLK_ENB_DP2
 CLK_RST_CONTROLLER_CLK_OUT_ENB_W_0. CLK_ENB_HDA2HDMICODEC
 PARTID = SOR
 START = ENABLE
4. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the SOR bit is set
SOR Power Ungating

 PARTID = SOR
 START = ENABLE
2. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the SOR bit is cleared
3. Set the following bits to enable clocks to MIPI_CAL, DPAUX, SOR, HDMI, DP2, DSI and DSIB:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0.CLK_ENB_MIPI_CAL
 CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0.CLK_ENB_DPAUX
 CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0.CLK_ENB_SOR0
 CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0.CLK_ENB_HDMI
 CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0.CLK_ENB_HDMI_AUDIO
 CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0.CLK_ENB_DSI
 CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0.CLK_ENB_DSIB
 CLK_RST_CONTROLLER_CLK_OUT_ENB_W_0.CLK_ENB_DSIA_LP
 CLK_RST_CONTROLLER_CLK_OUT_ENB_W_0.CLK_ENB_DSIB_LP
 CLK_RST_CONTROLLER_CLK_OUT_ENB_W_0.CLK_ENB_DP2
 CLK_RST_CONTROLLER_CLK_OUT_ENB_W_0.CLK_ENB_HDA2HDMICODEC
 APBDEV_PMC_REMOVE_CLAMPING_CMD_0.SOR
5. Poll APBDEV_PMC_REMOVE_CLAMPING_CMD_0 until the SOR bit is cleared
6. Clear the following bits to de-assert the reset to MIPI_CAL, DPAUX, SOR, HDMI, DP2, DSI and DSIB:
 CLK_RST_CONTROLLER_RST_DEVICES_H_0.SWR_MIPI_CAL_RST
 CLK_RST_CONTROLLER_RST_DEVICES_X_0.SWR_DPAUX_RST
 CLK_RST_CONTROLLER_RST_DEVICES_X_0.SWR_SOR0_RST
 CLK_RST_CONTROLLER_RST_DEVICES_H_0.SWR_HDMI_RST
 CLK_RST_CONTROLLER_RST_DEVICES_H_0.SWR_DSI_RST
 CLK_RST_CONTROLLER_RST_DEVICES_U_0.SWR_DSIB_RST

 CLK_RST_CONTROLLER_RST_DEVICES_W_0.SWR_DP2_RST
 CLK_RST_CONTROLLER_RST_DEVICES_W_0.SWR_HDA2HDMICODEC_RST
5.6.6.10 Procedures for XUSBA Power Domain
XUSBA Power Gating

1. Set the following bit to assert the reset to XUSB_SS:
 CLK_RST_CONTROLLER_RST_DEVICES_W_0.SWR_XUSB_SS_RST
2. Clear the following bit to disable clocks to XUSB_SS:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_W_0.CLK_ENB_XUSB_SS
 PARTID = XUSBA
 START = ENABLE
4. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the XUSBA bit is set
XUSBA Power Ungating

 PARTID = XUSBA
 START = ENABLE
2. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the XUSBA bit is cleared
3. Set the following bit to enable clocks to XUSB_SS:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_W_0.CLK_ENB_XUSB_SS
 APBDEV_PMC_REMOVE_CLAMPING_CMD_0.XUSBA
5. Poll APBDEV_PMC_REMOVE_CLAMPING_CMD_0 until the XUSBA bit is cleared
6. Clear the following bit to de-assert the reset to XUSB_SS:
 CLK_RST_CONTROLLER_RST_DEVICES_W_0.SWR_XUSB_SS_RST
5.6.6.11 Procedures for XUSBB Power Domain
XUSBB Power Gating

Software should be aware that disabling XUSB_DEV clock will also affect the XUSB_HOST module that is in XUSBC power
domain.
1. Flush XUSB_DEV MC client by setting the following bit:

 MC_CLIENT_HOTRESET_CTRL_0.XUSB_DEV_FLUSH_ENABLE
 XUSB_DEV_HOTRESET_STATUS
3. Set the following bit to assert reset to XUSB_DEV:
 CLK_RST_CONTROLLER_RST_DEVICES_U_0.SWR_XUSB_DEV_RST
4. Clear the following bits to disable clocks to XUSB_DEV:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0.CLK_ENB_XUSB_DEV
 PARTID = XUSBB

 START = ENABLE
6. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the XUSBB bit is set
XUSBB Power Ungating

 PARTID = XUSBB
 START = ENABLE
2. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the XUSBB bit is cleared
3. Set the following bit to enable clocks to XUSB_DEV:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0.CLK_ENB_XUSB_DEV
 APBDEV_PMC_REMOVE_CLAMPING_CMD_0.XUSBB
5. Poll APBDEV_PMC_REMOVE_CLAMPING_CMD_0 until the XUSBB bit is cleared
6. Clear the following bit to de-assert the reset to XUSB_DEV:
 CLK_RST_CONTROLLER_RST_DEVICES_U_0.SWR_XUSB_DEV_RST
7. Enable the XUSB_DEV MC client by clearing the following bit:
 MC_CLIENT_HOTRESET_CTRL_0.XUSB_DEV_FLUSH_ENABLE
5.6.6.12 Procedures for XUSBC Power Domain
XUSBC Power Gating

Software should be aware that disabling XUSB_HOST clock will also affect the XUSB_SS module that is in the XUSBA power
domain.
1. Flush the XUSB_HOST MC client by setting the following bit:

 MC_CLIENT_HOTRESET_CTRL_0.XUSB_HOST_FLUSH_ENABLE
 XUSB_HOST_HOTRESET_STATUS
3. Set the following bits to assert the reset to XUSB_HOST:
 CLK_RST_CONTROLLER_RST_DEVICES_U_0.SWR_XUSB_HOST_RST
4. Clear the following bits to disable clocks to XUSB_HOST:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0.CLK_ENB_XUSB_HOST
 PARTID = XUSBC
 START = ENABLE
6. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the XUSBC bit is set
XUSBC Power Ungating

 PARTID = XUSBC
 START = ENABLE
2. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the XUSBC bit is cleared
3. Set the following bit to enable clocks to XUSB_HOST:

 CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0.CLK_ENB_XUSB_HOST
 APBDEV_PMC_REMOVE_CLAMPING_CMD_0.XUSBC
5. Poll APBDEV_PMC_REMOVE_CLAMPING_CMD_0 until the XUSBC bit is cleared
6. Clear the following bit to de-assert the reset to XUSB_HOST:
 CLK_RST_CONTROLLER_RST_DEVICES_U_0.SWR_XUSB_HOST_RST
7. Enable the XUSB_HOST MC client by clearing the following bit:
 MC_CLIENT_HOTRESET_CTRL_0.XUSB_HOST_FLUSH_ENABLE
5.6.6.13 Procedures for VIC Power Domain
VIC Power Gating

1. Flush the VIC MC client by setting the following bit:
 MC_CLIENT_HOTRESET_CTRL_0.VIC_FLUSH_ENABLE
 VIC_HOTRESET_STATUS
3. Set the following bit to assert the reset to the MSENC:
 CLK_RST_CONTROLLER_RST_DEVICES_X_0.SWR_VIC_RST
4. Clear the following bit to disable clocks to the VIC:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0.CLK_ENB_VIC
 PARTID = VIC
 START = ENABLE
6. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the VIC bit is set
VIC Power Ungating

 PARTID = VIC
 START = ENABLE
2. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the VIC bit is cleared
3. Set the following bit to enable clocks to the VIC:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0.CLK_ENB_VIC
 APBDEV_PMC_REMOVE_CLAMPING_CMD_0.VIC
5. Poll APBDEV_PMC_REMOVE_CLAMPING_CMD_0 until the VIC bit is cleared
6. Clear the following bits to de-assert the reset to the VIC:
 CLK_RST_CONTROLLER_RST_DEVICES_X_0.SWR_VIC_RST
7. Enable the VIC MC client by clearing the following bit:
 MC_CLIENT_HOTRESET_CTRL_0.VIC_FLUSH_ENABLE

5.6.6.14 Procedures for IRAM Power Domain
IRAM Power Gating

1. Set the following bit to enable first level clock gating when IRAMs are not in use:
 CLK_RST_CONTROLLER_ CLK_OUT_ENB_U_0.CLK_ENB_IRAM[A|B|C|D]
 PARTID = IRAM
 START = ENABLE
3. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the IRAM bit is set
IRAM Power Ungating

 PARTID = IRAM
 START = ENABLE
2. Poll APBDEV_PMC_PWRGATE_STATUS_0 until the IRAM bit is cleared
3. Set the following bit to disable first level clock gating:
 CLK_RST_CONTROLLER_CLK_OUT_ENB_ U_0.CLK_ENB_ IRAM[A|B|C|D]
 APBDEV_PMC_REMOVE_CLAMPING_CMD_0.IRAM
5. Poll APBDEV_PMC_REMOVE_CLAMPING_CMD_0 until the IRAM bit is cleared
5.7 Clock and Reset Controller Registers

Because this chip is the system controller, resets are generated in hardware automatically as part of the power-on (POR) or
system (either hardware or software) reset sequence.
In POR, all blocks will be held in reset (with clocks disabled) except the minimal set of modules that are needed for system
boot-up. At POR, the appropriate bits in RST_DEVICES_L/H/U/V/W/X registers are set automatically by hardware. A "1" in
the bit position signifies that block will be held at reset after POR. A "0" in the bit position signifies that block will have its reset
de-asserted after POR.
Similarly for clocks, the appropriate bits in CLK_OUT_ENB_L/H/U/V/W/X registers are set automatically by hardware. A "1" in
the bit position signifies that block will have clock running during and after POR. A "0" in the bit position signifies that block will
not have clock running during or after POR.
The blocks necessary for boot (known as boot blocks) include:
 The ARM7 AVP Processor (COP) and its L1 cache

 All system buses (PPSB, AHB, APB, etc.)
 Timer
 RTC
 NOR Flash controller
 eFUSE
 GPIO
 CoreSight

Each of the boot block devices will have their reset de-asserted at the end of the POR period (as well as their clocks enabled
and use the Oscillator clock for their clock source). Boot blocks clock dividers are all set to divided-by-one.
During POR or system reset, the reset controller will de-assert reset to the boot blocks first and extend the resets to the
CPU/ARM7 for another 511 oscillator clock periods. This will prevent either processor from talking to a boot device while it is
still in the reset state.
Releasing a non-boot block/device from reset to bring into operation will require software to initiate a carefully controlled
sequence with clock and reset control registers. This sequence must be implemented by software precisely to ensure correct
operation of the hardware.
5.7.1 Precautions
 Unless noted elsewhere, all modules support changing the clock divider ratio without disabling the clock.
 Unless noted elsewhere, all modules' clock switching is glitch-free except "audio_sync_clk".
 For "audio_sync_clk", the clock source select needs to be set up before changing the device clock source to use that
audio clock or to enable the device which use that audio clock.
 Before stopping the clock (via CLK_OUT_ENB_L/H/U/V/W/X registers) and/or asserting reset (via
RST_DEVICES_L/H/U/V/W/X registers) to a module, first check the module to make sure it is not active. Stopping
clock/asserting reset while the module is still busy can cause relatively minor problem such as incorrect data
read/written, or catastrophic problem such as system hang. To ensure a module is not active, (a) disable the module
by programming its disable bit if not already done so, and (b) wait until the module is not active by checking for its
busy bit, done bit, count, or similar mechanism.
To set up a non-boot device for operation (only apply if a device has a CLK_SOURCE_<mod> register)
1. Make sure the device's reset is asserted (via RST_DEVICES_L/H/U/V/W/X registers).
2. Enable clock to the device (via CLK_OUT_ENB_L/H/U/V/W/X registers).
3. Change the clock divisor to the device (via CLK_SOURCE_ register).
4. Wait 1 µs to make sure the clock divider has changed.
5. Change the clock source to the device (via the CLK_SOURCE_<mod> register).
6. Wait 2 µs to make sure clock source/device logic is stabilized.
7. De-assert the device's reset (via RST_DEVICES_L/H/U/V/W/X registers).
To change a device's clock divider and/or source after boot-up (only apply if a device has a
CLK_SOURCE_<mod> register):
(A) Method 1 -- (using reset).
1. Make sure the device is disabled (via the device's register).

2. Assert device's reset (via RST_DEVICES_L/H/U/V/W/X registers).
3. Make sure clock to the device is enabled (via CLK_OUT_ENB_L/H/U/V/W/X registers).
4. Change the clock divisor to the device (via CLK_SOURCE_<mod> register).
5. Wait 1 µs to make sure the clock divider has changed.
6. Change the clock source to the device (via the CLK_SOURCE_<mod> register).
7. Wait 2 µs to make sure clock source/device logic is stabilized.
(B) Method 2 -- (not using reset).
1. Make sure the clock to the device is enabled (via CLK_OUT_ENB_L/H/U/V/W/X registers).

2. Depending on the maximum rated frequency of the device and the current and target clock source/divider value,
either change the divider first or the clock source first to avoid a temporary situation where the maximum
frequency for that device is violated. Make sure to wait for 1 µs between changing the divider and clock source
programming.).
3. Wait 2 µs to make sure the device logic is stabilized.
To reset a device (without need to change clock) after boot-up:

1. Make sure the device's reset is asserted (via RST_DEVICES_L/H/U/V/W/X registers).
2. Wait 2 µs to make sure the device logic is stabilized.
Method Used to wait for 1 or 2 µs.

1. To use one of the four timers, refer to the Timers section of this document.
2. Program the TMR_PTV register's TMR_PTV field with the desired microsecond count.
3. Program the TMR_PTV register's EN field to enable the timer.
4. Poll the TMR_PCR register's TMR_PCV field until it reaches 0 to indicate the microsecond count has been
reached.
5. Program the TMR_PTV register's EN field to disable the timer.
Invert Duty-Cycle Distortion Control

Some dividers have a feature to help mitigate clock duty-cycle distortion -- the distortion of the positive edge of a clock can be
swapped with the distortion of the negative edge. This ability may prove useful to counteract some of the inherent distortion
that occurs in clock generation logic and distribution. For example, a divider with a ratio of 1.0 having a 51%/49% duty cycle
could be made to have a 49%/51% duty cycle, if the duty-cycle inversion control is activated.
 Frequency Change Caution:

An INVERT_DCD field can be changed while the clock is running. In circumstances described in item 3 below, this
may temporarily cause a negative impact on the divided clock frequency, causing the module to fail if the frequency
to the module is not temporarily adjusted first.
1. Asserting INVERT_DCD adds 1/2 clock period (divider input clock) to the low pulse of a single divided output
clock period during the change. This causes the divided output clock frequency to be lowered for one clock
period.
2. For ratios other than 1.0, de-asserting INVERT_DCD removes 1/2 clock period (divider input clock) from the low
pulse of a single divided output clock period during the change. Because this effectively speeds up the divided
output clock frequency for one clock period, which can cause a module to fail, the module clock frequency may
need to be changed to a lower frequency before de-asserting INVERT_DCD.
3. De-asserting INVERT_DCD with a ratio of 1.0 is unique in that removing 1/2 clock period (divider input clock)
from the low pulse effectively removes the low pulse altogether. The resulting combination of the high pulses on
either side will effectively look like 1/2 clock period was added to the high pulse instead. Thus there occurs a
lower frequency for one clock period rather than an increased frequency like all other divide ratios.
 Latency:
Once the INVERT_DCD signal gets to the divider logic, there will be a maximum delay of 6 divider input clocks +
1 divider output clock before the change will complete.

Main clock sources used by the system:

(A) Primary clocks.
 "osc" or "clk_m" which can be either 12 MHz, 13 MHz, 19.2 MHz 26 MHz, 16.8 MHz, 38.4 MHz, or 48 MHz (Not
all the frequencies listed under osc or clk_m can be met).
 "clk_s" which is 32 kHz.
(B) PLL clocks.
 "PLLC" is general purpose and its output is called "pllC_out".

 "PLLC2" is general purpose and its output is called "pllC2_out".
 "PLLM" (memory) is primarily used for memory and its output is called "pllM_out".
 "PLLP" (peripheral) has a fixed frequency and its output is called "pllP_out0".
 "PLLA" (audio) is cascaded from PLLP and is used for audio purposes.
 "PLLU" (USB) has fixed outputs at 12 MHz, 48 MHz, 60 MHz, and 480 MHz.
 "PLLD"(DSI) is primarily used for the display and its output (after a /2 fix) is called "pllD_out0".
 "PLLD2"(DSI) is primarily used for the display and its output (after a /2 fix) is called "pllD2_out0".
 "PLLX" has extra high frequency used primarily by the fast CPU and is called "pllX_out0".
 “PLLDP” is used for eDP/LVDS (spread spectrum) and is called “pllDP_out0”.
 "refPLLE" is only used by PLLE.
 "PLLE" is only used by PCIe, SATA, USB3 (if they are present)
(C) PLL divided down clocks (each divider has 7 integer bits and 1 fractional bit).
 "pllC_out1" is divided-down from "pllC_out0".

 "pllM_out1" is divided-down from "pllM_out0".
 "pllP_out1" is divided-down from "pllP_out0".
 "pllA_out0" is divided-down from the "pllA" output.
Note: With the exception of PLLA, the other PLLs all use "osc_div_clk" as the reference clock.
This is the same frequency as "osc" with the exception of the following crystals:
38.4 MHz - Needs to be divided by 2 providing 19.2 MHz to the PLLs.

48.0 MHz - Needs to be divided by 4 providing 12.0 MHz to the PLLs
Note: In this document, CPULP, SCPU, and Slow CPU are synonymous. CPUG, FCPU, and
Fast CPU are also synonymous.

5.7.2 Multi-Address Tagging

A register or bit marked with a [* Multi-Address] tag indicates multiple addresses can access the same register/bit. The two
types of Multi-Address tags are described below.
[CCLK Multi-Address] Tags

These tags apply to legacy, CPUG, and CPULP multiple address registers and bits. For CCLK (CPU_CLK) related registers
values:
 Three sets of addresses are provided to support single cluster legacy, CPUG, and CPULP clusters.
 Two sets of hardware flops are used to store programmed values for G and LP CPU clusters. Legacy single cluster
registers are aliased to one of these based on the active cluster at the time the register is referenced.
 In some cases, only the CPU bit in an otherwise single access register is multi-address accessible, for example,
CLK_ENB_CPU.
[FUSE Multi-Address] Tags

These tags apply to Fuse and CAR multiple address registers:
 A bond_out_* register can be programmed via fuse or CAR CLK_RST_CONTROLLER_BOND_OUT_L_0 register or

fuse FUSE_SKU_BOND_OUT_L_0 register.
 Fuse bond_out writes are updated on fuse2all_fuse_outputs_valid rising edge
 CAR bond_out writes are updated on register writes
5.7.3 CLK_RST_CONTROLLER_RST_SOURCE_0
WatchDog (Deadman) Timer

The watchdog timer is used to recover from hang/lockup condition by resetting the system and/or COP (ARM7) and/or CPU
(MPCore). Either timer1 or timer2 can be used as watchdog timer. Refer to the Timer section of this document for more
information on watchdog timer usage.
Offset: 0x0 | Read/Write: R/W | Reset: 0x000XXX00 (0bxxxxxxxxxxxxxxxxxxxxxxxxxx00x000)
19 RO X WDT_CPU3_RST_STA: CPU3 reset by watchdog timer (RO)
13 RO X SWR_SYS_RST_STA: System reset by software (RO)
12 RO X WDT_SYS_RST_STA: System reset by watchdog timer (RO)
11 RO X SWR_COP_RST_STA: COP reset by software (RO)
10 RO X WDT_COP_RST_STA: COP reset by watchdog timer (RO)
SWR_CPU_RST_STA: CPU reset by software (RO). This bit has been

9 RO X
deprecated. Always returns 1’b0.
8 RO X WDT_CPU_RST_STA: CPU reset by watchdog timer (RO)
WDT_EN: Enable WatchDog Timer (Dead Man Timer)

5 RW DISABLE 0 = DISABLE
1 = ENABLE
4 RW TIMER1 WDT_SEL: WatchDog Timer Select


0 = TIMER1
1 = TIMER2
WDT_SYS_RST_EN: Enable WatchDog Timer reset for system.

1 = ENABLE
WDT_COP_RST_EN: Enable WatchDog Timer reset for COP

1 = ENABLE
WDT_CPU_RST_EN: Enable WatchDog Timer reset for CPU

1 = ENABLE
5.7.4 CLK_RST_CONTROLLER_RST_DEVICES_L_0
Offset: 0x4 │ Read/Write: R/W │ Reset: 0x7cd7dXXX (0b011111xx11x1x11111x1111x11xx100x)
SWR_CACHE2_RST: Reset COP cache controller.

1 = ENABLE
SWR_I2S0_RST: Reset I2S0 Controller

30 RW ENABLE 0 = DISABLE
1 = ENABLE
SWR_VCP_RST: Reset vector coprocessor.

1 = ENABLE
SWR_HOST1X_RST: Reset HOST1X.

1 = ENABLE
SWR_DISP1_RST: Reset DISP1 controller.

1 = ENABLE
SWR_DISP2_RST: Reset DISP2 controller.

1 = ENABLE
SWR_ISP_RST: Reset ISP controller.

1 = ENABLE
SWR_USBD_RST: Reset USB controller.

1 = ENABLE
SWR_VI_RST: Reset VI controller.

1 = ENABLE
SWR_I2S2_RST: Reset I2S 2 Controller

1 = ENABLE
SWR_PWM_RST: Reset Pulse Width Modulator

1 = ENABLE
SWR_SDMMC4_RST: Reset SDMMC4 controller.

1 = ENABLE
14 RW ENABLE SWR_SDMMC1_RST: Reset SDMMC1 controller.


0 = DISABLE
1 = ENABLE
SWR_I2C1_RST: Reset I2C1 Controller

1 = ENABLE
SWR_I2S1_RST: Reset I2S 1 Controller

1 = ENABLE
SWR_SPDIF_RST: Reset SPDIF Controller

1 = ENABLE
SWR_SDMMC2_RST: Reset SDMMC2 Controller

1 = ENABLE
SWR_GPIO_RST: Reset GPIO Controller

8 RO X 0 = DISABLE
1 = ENABLE
SWR_UARTB_RST: Reset UARTB/VFIR Controller

1 = ENABLE
SWR_UARTA_RST: Reset UARTA Controller

1 = ENABLE
SWR_TMR_RST: Reset Timer Controller

5 RO X 0 = DISABLE
1 = ENABLE
3 RW ENABLE SWR_ISPB_RST: Reset ISPB controller
SWR_TRIG_SYS_RST: Write 1 to pulse System Reset Signal. Hardware clears

this bit.
2 RW DISABLE
0 = DISABLE
1 = ENABLE
SWR_COP_RST: Write 1 to force COP Reset Signal. Software needs to clear

this bit when done.
1 RW DISABLE
0 = DISABLE
1 = ENABLE
0 RO X SWR_CPU_RST: Tied to 0.
5.7.5 CLK_RST_CONTROLLER_RST_DEVICES_H_0
Offset: 0x8 │ Read/Write: R/W │ Reset: 0xefddf32X (0b111x111111x111x11111x0110x1xx11x)
SWR_BSEV_RST: Reset BSEV controller.

1 = ENABLE
SWR_BSEA_RST: Reset BSEA controller.

1 = ENABLE
SWR_VDE_RST: Reset VDE and BSEV controller.

1 = ENABLE
SWR_USB3_RST: Reset USB3 controller.

1 = ENABLE

SWR_USB2_RST: Reset USB2 controller.

1 = ENABLE
SWR_EMC_RST: Reset EMC controller.

1 = ENABLE
SWR_MIPI_CAL_RST: Reset MIPI CAL Logic.

1 = ENABLE
SWR_UARTC_RST: Reset UARTC controller

1 = ENABLE
SWR_I2C2_RST: Reset I2C2 controller.

1 = ENABLE
SWR_CSI_RST: Reset CSI controller.

1 = ENABLE
SWR_HDMI_RST: Reset HDMI

1 = ENABLE
SWR_HSI_RST: Reset MIPI base-band HSI controller.

1 = ENABLE
SWR_DSI_RST: Reset DSI controller

1 = ENABLE
SWR_I2C5_RST: Reset I2C5 controller

1 = ENABLE
SWR_SPI3_RST: Reset SPI3 controller.

1 = ENABLE

1 = ENABLE
SWR_SNOR_RST: Reset NOR Flash controller.

1 = ENABLE

1 = ENABLE
SWR_KFUSE_RST: Reset KFuse controller.

1 = ENABLE
SWR_STAT_MON_RST: Reset statistic monitor.

1 = ENABLE
SWR_APBDMA_RST: Reset APB-DMA.

1 = ENABLE
SWR_AHBDMA_RST: Reset AHB-DMA.

1 = ENABLE

SWR_MEM_RST: Reset MC. This bit is disabled for security reasons. You can
0 RO X
write to it but it will always read as 0.
5.7.6 CLK_RST_CONTROLLER_RST_DEVICES_U_0
Offset: 0xc │ Read/Write: R/W │ Reset: 0x8a8ed5fe (0b1xxx1x1x1xxx111x110101011111111x)
SWR_XUSB_DEV_RST: Reset XUSB DEV logic.

31 ENABLE 0 = DISABLE
1 = ENABLE
SWR_MSENC_RST: Reset MSENC logic.

1 = ENABLE
SWR_XUSB_HOST_RST: Reset XUSB HOST logic.

1 = ENABLE
SWR_EMUCIF_RST: Reset EMUCIF logic.

1 = ENABLE
SWR_TSEC_RST: Reset TSEC logic.

1 = ENABLE
SWR_DSIB_RST: Reset DSIB

1 = ENABLE
SWR_I2C_SLOW_RST: Reset I2C_SLOW

1 = ENABLE
SWR_DTV_RST: Reset DTV

1 = ENABLE
SWR_SOC_THERM_RST: Reset SOC_THERM.

1 = ENABLE
SWR_TRACECLKIN_RST: Reset CoreSight™ traceclkin controller.

13 DISABLE 0 = DISABLE
1 = ENABLE
SWR_AVPUCQ_RST: Reset AVPUCQ logic.

1 = ENABLE
SWR_PCIEXCLK_RST: Reset PCIEXCLK logic.

1 = ENABLE
SWR_CSITE_RST: Reset CoreSight controller.

1 = ENABLE
SWR_AFI_RST: Reset AFI controller.

1 = ENABLE

SWR_OWR_RST: Reset OWR controller.

1 = ENABLE
SWR_PCIE_RST: Reset PCIe® controller.

1 = ENABLE
SWR_SDMMC3_RST: Reset SDMMC3 controller.

1 = ENABLE

1 = ENABLE
SWR_I2C3_RST: Reset I2C3 controller.

1 = ENABLE
2 0x1 SWR_UARTE_RST: Reserved.
SWR_UARTD_RST: Reset UARTD controller.

1 = ENABLE
5.7.7 CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0
Offset: 0x10 │ Read/Write: R/W │ Reset: 0x80000130 (0b100000xx00x0x00000x0000100110xx0)
CLK_ENB_CACHE2: Enable clock to COP cache controller.

1 = ENABLE
CLK_ENB_I2S0: Enable clock to I2S0 Controller

1 = ENABLE
CLK_ENB_VCP: Enable clock to vector coprocessor.

1 = ENABLE
CLK_ENB_HOST1X: Enable clock to Host1x.

1 = ENABLE
CLK_ENB_DISP1: Enable clock to DISP1 controller.

1 = ENABLE
CLK_ENB_DISP2: Enable clock to DISP2 controller.

1 = ENABLE
CLK_ENB_ISP: Enable clock to ISP controller.

1 = ENABLE
CLK_ENB_USBD: Enable clock to USB controller

1 = ENABLE

CLK_ENB_VI: Enable clock to VI controller.

1 = ENABLE
CLK_ENB_I2S2: Enable clock to I2S2 controller

1 = ENABLE
CLK_ENB_PWM: Enable clock to PWM (Pulse Width Modulator)

1 = ENABLE
CLK_ENB_SDMMC4: Enable clock to SDMMC4 controller.

1 = ENABLE

1 = ENABLE
CLK_ENB_I2C1: Enable clock to I2C1 Controller

1 = ENABLE
CLK_ENB_I2S1: Enable clock to I2S1 Controller

1 = ENABLE
CLK_ENB_SPDIF: Enable clock to S/PDIF Controller

1 = ENABLE

1 = ENABLE
CLK_ENB_GPIO: Enable clock to GPIO Controller

1 = ENABLE
CLK_ENB_UARTB: Enable clock to UARTB/VFIR Controller

1 = ENABLE
CLK_ENB_UARTA: Enable clock to UARTA Controller

1 = ENABLE
CLK_ENB_TMR: Enable clock to Timer Controller (sticky)

1 = ENABLE
CLK_ENB_RTC: Enable clock to RTC Controller

1 = ENABLE
CLK_ENB_ISPB: Enable clock – ISPB

1 = ENABLE
CLK_ENB_CPU: Enable clock to CPU. [CCLK Multi-Address]

1 = ENABLE

5.7.8 CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0
Offset: 0x14 │ Read/Write: R/W │ Reset: 0x00000480 (0b000x000000x000x00000x1001000x000)
CLK_ENB_BSEV: Enable clock to BSEV Controller.

1 = ENABLE
CLK_ENB_BSEA: Enable clock to BSEA Controller

1 = ENABLE
CLK_ENB_VDE: Enable clock to VDE Controller

1 = ENABLE
CLK_ENB_USB3: Enable clock to USB3 controller.

1 = ENABLE
CLK_ENB_USB2: Enable clock to USB2 controller.

1 = ENABLE
CLK_ENB_EMC: Enable clock to MC/EMC controller.

1 = ENABLE
CLK_ENB_MIPI_CAL: Enable clock to MIPI CAL logic.

1 = ENABLE
CLK_ENB_UARTC: Enable clock to UARTC controller

1 = ENABLE
CLK_ENB_I2C2: Enable clock to I2C2 controller.

1 = ENABLE
CLK_ENB_CSI: Enable clock to CSI controller

1 = ENABLE
CLK_ENB_HDMI: Enable clock to HDMI

1 = ENABLE
CLK_ENB_HSI: Enable clock to MIPI baseband HSI controller.

1 = ENABLE
CLK_ENB_DSI: Enable clock to DSI controller

1 = ENABLE
CLK_ENB_ I2C5: Enable clock to I2C5 controller

1 = ENABLE
CLK_ENB_SPI3: Enable clock to SPI3 controller.

1 = ENABLE

CLK_ENB_SPI2: Enable clock to SPI2 Controller.

1 = ENABLE
CLK_ENB_JTAG2TBC: Enable clock to jtag2tbc Interface.

1 = ENABLE
CLK_ENB_SNOR: Enable clock to NOR Flash Controller.

1 = ENABLE
CLK_ENB_SPI1: Enable clock to SPI1 Controller.

1 = ENABLE
CLK_ENB_KFUSE: Enable clock to KFUSE controller.

1 = ENABLE
CLK_ENB_FUSE: Enable clock to FUSE controller.

1 = ENABLE
CLK_ENB_PMC: Enable clock to PMC controller.

1 = ENABLE
CLK_ENB_STAT_MON: Enable clock to statistic monitor.

1 = ENABLE
CLK_ENB_KBC: Enable clock to keyboard controller.

1 = ENABLE
CLK_ENB_APBDMA: Enable clock to APB-DMA.

1 = ENABLE
CLK_ENB_AHBDMA: Enable clock to AHB-DMA.

1 = ENABLE
CLK_ENB_MEM: Enable clock to MC.

1 = ENABLE

5.7.9 CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0
Offset: 0x18 │ Read/Write: R/W │ Reset: 0x01f02a00 (0b00000x011111000x00101x1000000x0x)
CLK_ENB_XUSB_DEV: Enable clock to XUSB DEV.

1 = ENABLE
CLK_ENB_DEV1_OUT: Enable clock to DEV1 pad.

1 = ENABLE
CLK_ENB_DEV2_OUT: Enable clock to DEV2 pad.

1 = ENABLE
CLK_ENB_SUS_OUT: Enable clock to SUS pad.

1 = ENABLE
CLK_ENB_MSENC: Enable MSENC clk.

1 = ENABLE
26 ENABLE CLK_M_DOUBLER_ENB: Enable CLK_M clock doubler
CLK_ENB_XUSB_HOST: Enable clock to XUSB HOST

1 = ENABLE
CLK_ENB_CRAM2: Enable COP cache RAM clock.

1 = ENABLE
CLK_ENB_IRAMD: Enable IRAMD clock.

1 = ENABLE
CLK_ENB_IRAMC: Enable IRAMC clock.

1 = ENABLE
CLK_ENB_IRAMB: Enable IRAMB clock.

1 = ENABLE
CLK_ENB_IRAMA: Enable IRAMA clock.

1 = ENABLE
CLK_ENB_TSEC: Enable TSEC clock.

1 = ENABLE
CLK_ENB_DSIB: Enable clock to DSIB

1 = ENABLE
CLK_ENB_I2C_SLOW: Enable clock to I2C_SLOW

1 = ENABLE
CLK_ENB_DTV: Enable clock to DTV controller.

1 = ENABLE

CLK_ENB_SOC_THERM: Enable clock to SOC_THERM controller.

1 = ENABLE
CLK_ENB_TRACECLKIN: Enable traceclkin to CoreSight.

1 = ENABLE
CLK_ENB_AVPUCQ: Enable clock to AVPUCQ.

1 = ENABLE
CLK_ENB_CSITE: Enable clock to CoreSight.

1 = ENABLE
CLK_ENB_AFI: Enable clock to AFI.

1 = ENABLE
CLK_ENB_OWR: Enable clock to OWR.

1 = ENABLE
CLK_ENB_PCIE: Enable clock to PCIe.

1 = ENABLE
CLK_ENB_SDMMC3: Enable clock to SDMMC3.

1 = ENABLE
CLK_ENB_SPI4: Enable clock to SPI4.

1 = ENABLE
CLK_ENB_I2C3: Enable clock to I2C3.

1 = ENABLE
CLK_ENB_UARTD: Enable clock to UARTD.

1 = ENABLE
5.7.10 CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0
CPU (CCLK) and COP/System (SCLK) Clock Control

In this section, MPCore is referred to as CPU while ARM7 is referred to as COP. In this context, CPU refers to the active
CPULP or CPUG cluster. Each CCLK and SCLK clock domain can have 5 states: SUSP (suspend) where the clock source is
32 kHz, and normal states (IDLE, RUN, IRQ, FIQ).
Each of the normal states can be selected by software from 8 different clock sources. Furthermore, if any of the CPU/COP
FIQ/IRQ bit is enabled, a hardware auto trigger feature will be enabled such that hardware will jump from any state to IRQ or
to FIQ automatically. Of course, if the source is from a PLL, software needs to guarantee that the PLL clock is running and
stable before changing clock sources.
There are many usage models that can be derived from this mechanism: For example:
 Software can simply keep changing the clock source to one state (i.e., just CWAKEUP_IDLE_SOURCE) without
changing the CPU_STATE field.

 Software can have the concept of multiple states by first setting up CWAKEUP__SOURCE and then changing the
CPU_STATE field.
 Software can enable hardware auto detect of IRQ/FIQ to jump to the IRQ or FIQ state.
Note: Whenever the clock source is switched, the clock is stopped for approximately 400-600 ns.
CCLK and SCLK Super Clock Divider Control

The super clock divider allows a very fine tune of clock frequency going to CPU and COP/system using clock skipping
technique. It is different from a traditional divider (1/n) in that both the numerator and denominator are programmable (m/n).
Both the numerator and denominator are 8 bits each. Thus, "effective" frequency = source frequency * (m/n). Furthermore, if
any of the CPU/COP FIQ/IRQ bits is enabled, hardware will auto disable the super clock divider functionality.
There are many usage models that can be derived from this mechanism. For example:
 There is no clock source switching penalty. Software can just pick a PLL output as a maximum frequency source via
CCLK/SCLK_BURST_POLICY and just keep changing SUPER_CCLK/SCLK_DIVIDER to yield the desired lower
"effective" frequency.
 For applications where the "osc" frequency is more than sufficient to do the job, PLLs can be turned off to save power
and the super clock divider can further divide down the "osc" clock to yield even more power saving.
 If auto IRQ/FIQ feature is enabled, CCLK/SCLK will automatically jump back to full frequency to handle high priority
interrupt routines.
Note: From a dynamic voltage scaling (DVS) standpoint, the full clock frequency source (not the
output frequency of the super clock divider) going into the super clock divider should be
used to determine how low one can lower the voltage.
If m > n, the resulting super clock divider output frequency will be the same as the input
frequency. In other words, there will be no clock skip or divide down.
Offset: 0x20 │ Read/Write: R/W │ Reset: 0x10X00000 (0b00010000xxxxxxx00000000000000000)
CPU_STATE: 0000=32 kHz Clock source; 0001=IDLE Clock Source; 001X=Run clock
source; 01XX=IRQ Clock Source; 1XXX=FIQ Clock Source
0 = STDBY
31:28 RW 0x1 1 = IDLE
2 = RUN
4 = IRQ
8 = FIQ
27 RW 0x0 COP_AUTO_CWAKEUP_FROM_FIQ: 0 = NOP ; 1=Burst on COP FIQ
26 RW 0x0 CPU_AUTO_CWAKEUP_FROM_FIQ: 0 = NOP ; 1=Burst on CPU FIQ
25 RW 0x0 COP_AUTO_CWAKEUP_FROM_IRQ: 0 = NOP ; 1=Burst on COP IRQ
24 RW 0x0 CPU_AUTO_CWAKEUP_FROM_IRQ: 0 = NOP ; 1=Burst on CPU IRQ
23 RO X TSENSOR_SLOWDOWN: 0 = Normal; 1 = cpug_clk/2 triggered by temperature sensor.
16 RW 0x0 CCLK_RESERVED: Reserved. CPULP uses this bit for div2 bypass.

CWAKEUP_FIQ_SOURCE: 0000 = clk_m, 0001 = pllC_out0, 0010 = clk_s, 0011 =

pllM_out0, 0100 = pllP_out0, 0101 = pllP_out4, 0110 = pllC2_out0, 0111 = pllC3_out0, 1000
= PLLX_out0 (low jitter), 1001 = reserved, 1110 = PLLX_out0, (low jitter), 1111 = reserved
0 = CLKM
1 = PLLC_OUT0
2 = CLKS
3 = PLLM_OUT0
15:12 RW 0x0 4 = PLLP_OUT0
5 = PLLP_OUT4
6 = PLLC2_OUT0
7 = PLLC3_OUT0
8 = PLLX_OUT0_LJ
9 = RESERVED9
14 = PLLX_OUT0
15 = RESERVED15
CWAKEUP_IRQ_SOURCE: Same definitions as CWAKEUP_FIQ_SOURCE

0 = CLKM
1 = PLLC_OUT0
2 = CLKS
3 = PLLM_OUT0
4 = PLLP_OUT0
11:8 RW 0x0 5 = PLLP_OUT4
6 = PLLC2_OUT0
7 = PLLC3_OUT0
8 = PLLX_OUT0_LJ
9 = RESERVED9
14 = PLLX_OUT0_LJ
15 = RESERVED15
CWAKEUP_RUN_SOURCE: Same definitions as CWAKEUP_FIQ_SOURCE

0 = CLKM
1 = PLLC_OUT0
2 = CLKS
3 = PLLM_OUT0
4 = PLLP_OUT0
6 = PLLC2_OUT0
7 = PLLC3_OUT0
8 = PLLX_OUT0_LJ
9 = RESERVED9
14 = PLLX_OUT0
15 = RESERVED15
CWAKEUP_IDLE_SOURCE: Same definitions as CWAKEUP_FIQ

0 = CLKM
1 = PLLC_OUT0
2 = CLKS
3 = PLLM_OUT0
4 = PLLP_OUT0
6 = PLLC2_OUT0
7 = PLLC3_OUT0
8 = PLLX_OUT0_LJ
9 = RESERVED9
14 = PLLX_OUT0
15 = RESERVED15

5.7.11 CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0
[CCLK Multi-Address]: See “Multi-Address Tagging” in this section for more details.
Offset: 0x24 │ Read/Write: R/W │ Reset: 0x00000000 (0b00x00000000000000000000000000000)
SUPER_CDIV_ENB: 0 = Disable divider.

1 = ENABLE
SUPER_CDIV_USE_THERM_CONTROLS: 1 = Use therm controls for pulse skipper (cpug

only)
30 DISABLE
0 = DISABLE
1 = ENABLE
CCLK_INVERT_DCD: 1 = Enable inversion of DCD (duty-cycle distortion), 0 = Disable

inversion of DCD
1 = ENABLE
See “Invert Duty-Cycle Distortion Control” in this section for more information.
27 0x0 SUPER_CDIV_DIS_FROM_COP_FIQ: 0 = enable FIQ, disable FIQ.
26 0x0 SUPER_CDIV_DIS_FROM_CPU_FIQ: 0 = enable FIQ, disable FIQ.
25 0x0 SUPER_CDIV_DIS_FROM_COP_IRQ: 0 = enable IRQ, disable IRQ.
24 0x0 SUPER_CDIV_DIS_FROM_CPU_IRQ: 0 = enable IRQ, disable IRQ.
23:16 0x0 CCLK_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
15:8 0x0 SUPER_CDIV_DIVIDEND: Actual value = n + 1.
7:0 0x0 SUPER_CDIV_DIVISOR: Actual value = n + 1.
5.7.12 CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0
Offset: 0x28 │ Read/Write: R/W │ Reset: 0x10000000 (0b00010000xxxxxxxxx000x000x000x000)
SYS_STATE: 0000=32 kHz Clock source; 0001=IDLE Clock Source; 001X=Run clock
0 = STDBY
31:28 0x1 1 = IDLE
2 = RUN
4 = IRQ
8 = FIQ
27 0x0 COP_AUTO_SWAKEUP_FROM_FIQ: 0 = NOP ; 1 = Burst on COP FIQ
26 0x0 CPU_AUTO_SWAKEUP_FROM_FIQ: 0 = NOP ; 1 = Burst on CPU FIQ
25 0x0 COP_AUTO_SWAKEUP_FROM_IRQ: 0 = NOP ; 1 = Burst on COP IRQ
24 0x0 CPU_AUTO_SWAKEUP_FROM_IRQ: 0 = NOP ; 1 = Burst on CPU IRQ

SWAKEUP_FIQ_SOURCE: 000 = clk_m, 001 = pllC_out1, 010 = pllP_out4, 011 =

pllP_out0, 100 = pllP_out2, 101 = pllC_out0, 110 = clk_s, 111 = pllM_out1,
0 = CLKM
1 = PLLC_OUT1
2 = PLLP_OUT4
14:12 0x0
3 = PLLP_OUT0
4 = PLLP_OUT2
5 = PLLC_OUT0
6 = CLKS
7 = PLLM_OUT1
SWAKEUP_IRQ_SOURCE: Same definitions as SWAKEUP_FIQ_SOURCE

0 = CLKM
1 = PLLC_OUT1
2 = PLLP_OUT4
10:8 0x0 3 = PLLP_OUT0
4 = PLLP_OUT2
5 = PLLC_OUT0
6 = CLKS
7 = PLLM_OUT1
SWAKEUP_RUN_SOURCE: Same definitions as SWAKEUP_FIQ_SOURCE

0 = CLKM
1 = PLLC_OUT1
2 = PLLP_OUT4
6:4 0x0 3 = PLLP_OUT0
4 = PLLP_OUT2
5 = PLLC_OUT0
6 = CLKS
7 = PLLM_OUT1
SWAKEUP_IDLE_SOURCE: Same definitions as SWAKEUP_FIQ_SOURCE

0 = CLKM
1 = PLLC_OUT1
2 = PLLP_OUT4
2:0 0x0 3 = PLLP_OUT0
4 = PLLP_OUT2
5 = PLLC_OUT0
6 = CLKS
7 = PLLM_OUT1
5.7.13 CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0
Offset: 0x2c │ Read/Write: R/W │ Reset: 0x00000000 (0b0xxx0000xxxxxxxx0000000000000000)
SUPER_SDIV_ENB: 0 = Disable divider.

1 = ENABLE
27 0x0 SUPER_SDIV_DIS_FROM_COP_FIQ: 0 = enable FIQ, disable FIQ.
26 0x0 SUPER_SDIV_DIS_FROM_CPU_FIQ: 0 = enable FIQ, disable FIQ.
25 0x0 SUPER_SDIV_DIS_FROM_COP_IRQ: 0 = enable IRQ, disable IRQ.
24 0x0 SUPER_SDIV_DIS_FROM_CPU_IRQ: 0 = enable IRQ, disable IRQ.
15:8 0x0 SUPER_SDIV_DIVIDEND: Actual value = n + 1.
7:0 0x0 SUPER_SDIV_DIVISOR: Actual value = n + 1.

5.7.14 CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0
HCLK/PCLK
SCLK is the main system clock which can run up to 275 MHz.
HCLK is the AHB clock which can run at 1, 1/2, 1/3, or 1/4 of SCLK.
PCLK is the APB clock which can run at 1, 1/2, 1/3, or 1/4 of HCLK.
Offset: 0x30 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x000x00)
7 0x0 HCLK_DIS: 0=enable HCLK, 1=disable HCLK.
5:4 0x0 AHB_RATE: 1/(n+1) of SCLK.
3 0x0 PCLK_DIS: 0=enable PCLK, 1=disable PCLK.
1:0 0x0 APB_RATE: 1/(n+1) of HCLK.
5.7.15 CLK_RST_CONTROLLER_CLK_MASK_ARM_0
Offset: 0x44 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxx00xxxxxxxxxxxxxx00)
CLK_MASK_CPU_HALT: WARNING: Deprecated. This bit must not be set in SMP

16 0x0
mode or when the fastsync FIFO feature is enabled.
CLK_MASK_COP:
00 = no clock masking
1:0 0x0 01 = u2_nwait_r
10 = u2_nwait_r
11 = no clock masking.
5.7.16 CLK_RST_CONTROLLER_MISC_CLK_ENB_0
Offset: 0x48 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxx0xxxx0000xxxxxxxxxxxxxxxxxxxx)
DEV1_OSC_DIV_SEL:
00 = osc
23:22 0x0 01 = osc/2
10 = osc/4
11 = osc/8.
DEV2_OSC_DIV_SEL:
00 = osc
21:20 0x0 01 = osc/2
10 = osc/4
11 = osc/8.

5.7.17 CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0
The CPU complex consists of the CPU, L2 cache controller, and a number of bridge devices interfacing CPU/L2 cache to the
rest of the system. Except for the CPU, L2 cache controller, and bridge logic to external memory which always runs at non-
divided-down CPU frequency, other bridge devices can run at various programmable divided-down CPU clock ratios.
Note: However, since the CPU clock can be selected from 1-of-9 clock sources (refer to the CCLK_BURST_POLICY register),
the user is responsible for not selecting a bridge divide-down CPU clock ratio that will exceed 1/4 of the "MAX" CPU frequency
supported. The "MAX" CPU frequency is 1.1 GHz.
Offset: 0x4c │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxx0000xxxxxx00)
11 0x0 CPU3_CLK_STP: 1 = CPU3 clock stop, 0 = CPU3 clock run.
1:0 0x0 CPU_BRIDGE_CLKDIV: Unused but available.
5.7.18 CLK_RST_CONTROLLER_OSC_CTRL_0
Oscillator Control
"osc" can have any of the hardware-supported frequencies (12, 13, 19.2, 26, 16.8, 38.4, 48 MHz) . The OSC_FREQ field
provides a way for software to inform hardware what the incoming clock frequency is. This information is used by hardware to
auto setup the parameters (DIVN, DIVM, DIVP, CPCON, LFCON, VCOCON, DCCON, OUT1_RATIO, OUT2_RATIO,
OUT3_RATIO, OUT4_RATIO, and OUT5_RATIO) to PLLP and its dividers. If a different frequency is used, there is a way to
override the hardware auto-generated PLLP parameters.
Offset: 0x50 │ Read/Write: R/W │ Reset: 0x800003f1 (0b10000000000000x00000xx111111x0x1) | SW Default: 0x00000010
SW
Default
OSC_FREQ: 0000 = 13.0 MHz, 0100 = 19.2 MHz, 1000 = 12.0 MHz, 1100 = 26.00 MHz,
0001 = 16.8 MHz, 0101 = 38.4 MHz*, 1001 = 48.0 MHz*.
*Set PLL_REF_DIV to /2 for 38.4 MHz and /4 for 48 MHz. Unused code map to 13 MHz
setting in hardware.
0 = OSC13
31:28 0x0 NONE 4 = OSC19P2
8 = OSC12
12 = OSC26
1 = OSC16P8
5 = OSC38P4
9 = OSC48
PLL_REF_DIV: PLL reference clock divide.

00 = /1
01 = /2
10 = /4
27:26 0x0 NONE
0 = DIV1
1 = DIV2
2 = DIV4
3 = RESERVED

SW
Default
25:18 0x0 NONE OSCFI_SPARE: Crystal oscillator spare register control.
16:12 0x0 NONE XODS: Crystal oscillator duty cycle control.
9:4 0x3f 0x1 XOFS: Crystal oscillator drive strength control.
2 0x0 NONE CLK_OK: Crystal oscillator clk_ok.
0 0x1 NONE XOE: Crystal oscillator enable (1 = enable).
5.7.19 CLK_RST_CONTROLLER_PLL_LFSR_0
Offset: 0x54 │ Read/Write: RO │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
15:0 X RND: Random number generated from PLL linear feedback shift register.
5.7.20 CLK_RST_CONTROLLER_OSC_FREQ_DET_0
Oscillator Frequency Detect

The “osc” can have any one of the seven supported crystal frequencies (12, 13, 19.2, 26, 16.8, 38.4, 48 MHz). Hardware
provides the following mechanism to detect which frequency of osc is running. To determine the osc frequency, program the
number of 32.768 kHz clock periods to create a fixed time window in which the "osc" clocks will be counted. Once the counting
process is done, the count value can be used to determine the osc frequency.
OSC Frequency Approximate OSC_FREQ_DET_CNT

(MHz) (using two 32 kHz periods as window)
12.00 732 (0x02DC)
13.00 794 (0x031A)
16.80 1025 (0x0401)
19.20 1172 (0x0494)
26.00 1587 (0x0633)
38.40 2344 (0x0928)
48.00 2930 (0x0B72)
Offset: 0x58 │ Read/Write: R/W │ Reset: 0x00000000 (0b0xxxxxxxxxxxxxxxxxxxxxxxxxxx0000)
OSC_FREQ_DET_TRIG: 0 = default, 1 = enable osc frequency detect.

1 = ENABLE
REF_CLK_WIN_CFG: Indicates the number of 32.768 kHz clock periods as window in n+1
3:0 0x0
scheme.
5.7.21 CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0
Offset: 0x5c │ Read/Write: RO │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)

31 X OSC_FREQ_DET_BUSY: 0 = not busy, 1 = busy.
OSC_FREQ_DET_CNT: Indicates the number of osc counts within the 32.768 kHz clock
15:0 X
reference window.
5.7.22 CLK_RST_CONTROLLER_PLLE_SS_CNTL_0
Offset: 0x68 | Read/Write: R/W | Reset: 0x00005c00 (0b0000000000000000010111x000000000) | Default: 0x20010025
SW
Default
31:30 0x0 _NONE_ PLLE_INTEGOFFSET: interpolator bias current.
29:24 0x0 0x20 PLLE_SSCINCINTRV: Triangle generator increment interval control.
23:16 0x0 0x1 PLLE_SSCINC: Triangle generator increment control.
15 0x0 0x0 PLLE_SSCINVERT: 0: gives down spread, 1: gives up-spread.
14 0x1 0x0 PLLE_SSCCENTER: 0: gives control to SSCINVERT, 1: enables center spread.
13 0x0 _NONE_ PLLE_SSCPDMBYP: Bypass from pulse density modulator. Normally set to zero.
12 0x1 0x0 PLLE_SSCBYP: 0: enables spreading, 1: disables spreading.
11 0x1 0x0 PLLE_INTERP_RESET: Interpolator reset. 0: normal operation, 1: resets SS machine.
PLLE_BYPASS_SS: When set feedback clock bypasses interpolator. Default value is

10 0x1 0x0
zero.
8:0 0x0 0x25 PLLE_SSCMAX: Spread limit control.
5.7.23 CLK_RST_CONTROLLER_PLLC_BASE_0
Tegra K1 devices have 14 PLLs controllable by clock control. Consult the PLL specifications for electrical requirements. Below
are the PLL cells used for each PLL referenced in this TRM:
 PLLC is of type PLL14G_DYN_ESD.

 PLLC2 and PLLC3 are of type PLL12G_DIG_E1.
 PLLM is of type PLL10G_4PH_ESD.
 PLLP and PLLA are of type CLKPLL700_LP.
 PLLU is of type CLKPLL960_USB.
 PLLD is of type CLKPLL15G_MIPI.
 PLLD2 is of type PLL12G_SSD_ESD.
 PLLDP and PLLC4 are of type PLL12G_SSD_AESD
 PLLX is of type PLL24G_DYN_PRB_ESD.
 refPLLE is of type PLL600_ESD.
 PLLE is of type PLL24G_SSA_33VCML_ESD.
In general, there are 3 requirements for each PLL with which software needs to comply:
 Input frequency range (REF).

 Comparison frequency range (CF). CF = REF/DIVM, where DIVM is the input divider control.
 VCO frequency range (VCO). VCO = CF * DIVN, where DIVN is the feedback divider control.
Note: The final PLL output frequency (FO) = VCO>>DIVP, where DIVP is the post divide control.

Crystals 38.4 MHz and 48 MHz require pre-divider PLL_REF_DIV settings of 2 and 4, respectively, to meet the input
frequency requirements of all PLLs that use "osc_div_clk" as a reference. All other supported crystals are used by the PLLs
directly, without any pre-divider.
Contact your NVIDIA representative for more details on the PLLs.
PLLP Configuration Information

PLLP is configured as a fixed frequency PLL. The code in the Boot ROM configures PLLP at a fixed 408 MHz. Later on,
software (typically the Boot Loader) may change this to another "fixed" frequency.
For Tegra K1 devices, software changes this frequency from 216 MHz to 408 MHz. Boot ROM configuration values for
408 MHz are listed below.
Table 20: Boot ROM Configuration to 216 MHz

Reference 13.0 MHz 19.2 MHz 12.0 MHz 26.0 MHz 16.8MHz 38.4MHz 48.0MHz Resulting
Frequency Frequency
DIVN 408 (198h) 340 (154h) 408 (198h) 204 (0cch) 340 (154h) 340 (154h) 204 (0cch) -
DIVM 13 (0dh) 16 (10h) 12 (0ch) 13 (0dh) 14 (0eh) 16 (10h) 6 (06h) -
DIVP 1 (0h) 1 (0h) 1 (0h) 1 (0h) 1 (0h) 1 (0h) 1 (0h) -
CPCON 8 (8h) 4 (4h) 8 (8h) 8 (8h) 4 (4h) 4 (4h) 8 (8h) -
LFCON 0 (0h) 0 (0h) 0 (0h) 0 (0h) 0 (0h) 0 (0h) 0 (0h) -
VCOCON 0 (0h) 0 (0h) 0 (0h) 0 (0h) 0 (0h) 0 (0h) 0 (0h) -
DCCON 0 (0b) 0 (0b) 0 (0b) 0 (0b) 0 (0b) 0 (0b) 0 (0b) -
PLL_REF_DIV /1 (0h) /2 (1h) /4 (2h) -
OUT1 div ratio 42.5 (53h) 42.5 (53h) 42.5 (53h) 42.5 (53h) 42.5 (53h) 42.5 (53h) 42.5 (53h) 9.6 MHz
Table 21: PLLU Configuration Information (Reference Clock osc_div_clk and PLLU-FOs fixed at 12 MHz/48 MHz/60 MHz/480 MHz)
Reference 13.0 MHz 19.2 MHz 12.0 MHz 26.0 MHz 16.8 MHz 38.4MHz 48.0MHz
Frequency
DIVN 960 (3c0h) 200 (0c8h) 960 (3c0h) 960 (3c0h) 400 (190h) 200 (0c8h) 960 (3c0h)
DIVM 13 (0dh) 4 (04h) 12 (0ch) 26 (1ah) 7 (07h) 4 (04h) 12 (0ch)
CPCON 12 (ch) 3 (3h) 12 (ch) 12 (ch) 5 (5h) 3 (3h) 12 (ch)
LFCON 2 (2h) 2 (2h) 2 (2h) 2 (2h) 2 (2h) 2 (2h) 2 (2h)
PLL_REF_DIV /1 (0h) /2 (1h) /4 (2h)
Special Consideration when Using PLLX as a Clock Source for the CPU
PLLX is shared between G and LP CPU clusters. To save power, the proper PLLX_FO_LP_DISABLE or
PLLX_FO_G_DISABLE bit should only be de-asserted when the output is being used.
Offset: 0x80 │ Read/Write: R/W │ Reset: 0x0000010c (0bx000xxxx0000xxxx0000000100001100)
PLLC_ENABLE:
1 = ENABLE

PLLC_REF_DIS: 0 = enable reference clock, 1 = disable reference clock.

29 RW REF_ENABLE 0 = REF_ENABLE
1 = REF_DISABLE
28 RW 0x0 PLLC_LOCK_OVERRIDE
27 RO X PLLC_LOCK: 0 = not lock, 1 = lock.
23:20 RW 0x0 PLLC_DIVP: 0 = post divider (2^n).
15:8 RW 0x1 PLLC_DIVN: PLL feedback divider.
7:0 RW 0xc PLLC_DIVM: PLL input divider.
5.7.24 CLK_RST_CONTROLLER_PLLC_OUT_0
Offset: 0x84 │ Read/Write: R/W │ Reset: 0x00000002 (0bxxxxxxxxxxxxxxxx00000000xxxxxx10)
15:8 0x0 PLLC_OUT1_RATIO: PLLC_OUT1 divider from base PLLC (lsb denoted 0.5x).
PLLC_OUT1_CLKEN: PLLC_OUT1 divider clk enable.

1 = ENABLE
PLLC_OUT1_RSTN: PLLC_OUT1 divider reset. 0 = reset, 1 = not reset.

0 RESET_ENABLE 0 = RESET_ENABLE
1 = RESET_DISABLE
5.7.25 CLK_RST_CONTROLLER_PLLC_MISC2_0
Offset: 0x88 │ Read/Write: R/W │ Reset: 0x0000000X (0bxx00000000000000000000000000000x)
29:28 RW 0x0 PLLC_PTS: PTS field for PLLC.

0 = DISABLE
1 = FO
2 = VCO
27 RW 0x0 PLLC_EN_FSTLCK
26 RW 0x0 PLLC_CLAMP_NDIV
25 RW 0x0 PLLC_EN_DYNRAMP
24:17 RW 0x0 PLLC_DYNRAMP_STEPA
16:9 RW 0x0 PLLC_DYNRAMP_STEPB
8:1 RW 0x0 PLLC_NDIV_NEW
0 RO X PLLC_DYNRAMP_DONE
5.7.26 CLK_RST_CONTROLLER_PLLC_MISC_0
Offset: 0x8c │ Read/Write: R/W │ Reset: 0x0X000000 (0bx00001x0000000000000000000000000)
30 RW 0x0 PLLC_OUT1_DIV_BYP: 1 = bypass PLLC_OUT1 divider.
29:28 RW 0x0 PLLC_KCP

27 RW 0x0 PLLC_KVCO
26 RW 0x1 PLLC_IDDQ
25 RO X PLLC_FREQ_LOCK
24 RW 0x0 PLLC_LOCK_ENABLE:
0 = DISABLE
1 = ENABLE
23:0 RW 0x0 PLLC_SETUP: Base PLLC VCO range setup control.
5.7.27 CLK_RST_CONTROLLER_PLLM_BASE_0
Offset: 0x90 │ Read/Write: R/W │ Reset: 0x00000801 (0b000xxxxxxxxxxxx00000100000000001)
PLLM_BYPASSPLL: 0 = no bypass, 1 = bypass.

1 = ENABLE
PLLM_ENABLE: 0 = disable, 1 = enable. (Will invert and connect to IDDQ)

1 = ENABLE
PLLM_REF_DIS: 0 = enable reference clk, 1 = disable reference clk.

1 = REF_DISABLE
27 RO X PLLM_LOCK: 0 = not lock, 1 = lock. Phase and frequency
26 RO X PLLM_FREQ_LOCK: 0 = not lock, 1 = lock. Frequency lock only
20 RW 0x0 PLLM_DIV2: 1= Frequency of CLKOUT*=VCOCLK/2
PLLM_CLAMP_PX: 1 = clamp CLKOUT_P* / CLKOUT_P*B to 0/1 has priority

over IDDQ and ENABLE and PLLAVDD
19 RW 0x0 Note: PLLM_CLAMP_PX will be cleared before using PLLM. Its purpose is to
avoid excessive CDB power consumption while analog PLL power is coming
up and the differential output of PLLM is still stabilizing.
15:8 RW 0x8 PLLM_DIVN: PLL feedback divider.
7:0 RW 0x1 PLLM_DIVM: PLL input divider.
5.7.28 CLK_RST_CONTROLLER_PLLM_OUT_0
See the “PLL post dividers pll*_out*” section.
Offset: 0x94 │ Read/Write: R/W │ Reset: 0x00000002 (0bxxxxxxxxxxxxxxx000000000xxxxxx10)
16 0x0 PLLM_OUT1_DIV_BYP: 1 = bypass PLLM_OUT1 divider
15:8 0x0 PLLM_OUT1_RATIO: PLLM_OUT1 divider from base PLLM (lsb denotes 0.5x).
PLLM_OUT1_CLKEN: PLLM_OUT1 divider clk enable.

1 = ENABLE

PLLM_OUT1_RSTN: PLLM_OUT1 divider reset. 0 = reset, 1 = not reset.

1 = RESET_DISABLE
5.7.29 CLK_RST_CONTROLLER_PLLM_MISC1_0
Offset: 0x98 │ Read/Write: R/W │ Reset: 0x00000000 (0bx0000000000000000000000000000000)
30 0x0 PLLM_PD_LSHIFT_PH135
27 0x0 PLLM_CLAMP_PH135
23:0 0x0 PLLM_SETUP: SETUP fields
5.7.30 CLK_RST_CONTROLLER_PLLM_MISC2_0
Offset: 0x9c │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxx000x0000000)
10 0x0 PLLM_ENABLE_SW_OVERRIDE: Let software override values on clamp/bypass versus hardware

FSM control
9:8 0x0 PLLM_PTS: PTS field for external mux.

0 = DISABLE
1 = FO
6 0x0 PLLM_EN_FSTLCK
5 0x0 PLLM_IDDQ
4 DISABLE PLLM_PD_LCKDET:1 = Power down lock detect

0 = DISABLE
1 = ENABLE
3 0x0 PLLM_LOCK_OVERRIDE: Forces lock to 1
2:1 0x0 PLLM_KCP: Charge Pump Gain control
0 0x0 PLLM_KVCO:VCO gain
5.7.31 CLK_RST_CONTROLLER_PLLP_BASE_0
Offset: 0xa0 │ Read/Write: R/W │ Reset: 0x0X00010c (0b0000xxxxx000xx0000000001xxx01100)
PLLP_BYPASS:
0 = no bypass
31 RW DISABLE 1 = bypass.
0 = DISABLE
1 = ENABLE

PLLP_ENABLE:
1 = ENABLE
PLLP_REF_DIS:
0 = enable reference clock
29 RW REF_ENABLE 1 = disable reference clock
0 = REF_ENABLE
1 = REF_DISABLE
PLLP_BASE_OVRRIDE:
0 = disallow base override
28 RW DISABLE 1 = allow base override
0 = DISABLE
1 = ENABLE
27 RO X PLLP_LOCK: 0 = not lock, 1 = lock.
22:20 RW 0x0 PLLP_DIVP: 0 = post divider (2^n).
17:8 RW 0x1 PLLP_DIVN: PLL feedback divider.
4:0 RW 0xc PLLP_DIVM: PLL input divider.
5.7.32 CLK_RST_CONTROLLER_PLLP_OUTA_0
Offset: 0xa4 │ Read/Write: R/W │ Reset: 0x00020002 (0b00000000xxxxx01000000000xxxxx010)
31:24 0x0 PLLP_OUT2_RATIO: PLLP_OUT2 divider from base PLLP (lsb denotes 0.5x).
PLLP_OUT2_OVRRIDE:
0 = disallow PLLP_OUT2 ratio override
18 DISABLE 1 = enable override
0 = DISABLE
1 = ENABLE
PLLP_OUT2_CLKEN: PLLP_OUT2 divider clock enable.

1 = ENABLE
PLLP_OUT2_RSTN: PLLP_OUT2 divider reset.

0 = reset
16 RESET_ENABLE 1 = not reset
0 = RESET_ENABLE
1 = RESET_DISABLE
PLLP_OUT1_OVRRIDE:
0 = Disallow PLLP_OUT1 ratio override
0 = DISABLE
1 = ENABLE

1 = ENABLE


0 = reset
0 = RESET_ENABLE
1 = RESET_DISABLE
5.7.33 CLK_RST_CONTROLLER_PLLP_OUTB_0
Offset: 0xa8 │ Read/Write: R/W │ Reset: 0x00020002 (0b00000000xxxxx01000000000xxxxx010)
PLLP_OUT4_OVRRIDE:
0 = disallow PLLP_OUT4 ratio override
0 = DISABLE
1 = ENABLE

1 = ENABLE

0 = reset
0 = RESET_ENABLE
1 = RESET_DISABLE
PLLP_OUT3_OVRRIDE: 0 = Disallow PLLP_OUT3 ratio override.

1 = ENABLE

1 = ENABLE
PLLP_OUT3_RSTN: PLLP_OUT3 divider reset. 0 = reset, 1 = not reset.

1 = RESET_DISABLE
5.7.34 CLK_RST_CONTROLLER_PLLP_MISC_0
Offset: 0xac │ Read/Write: R/W │ Reset: 0x00040100 (0bxxxx00000000x1000000000100000000)
27 0x0 PLLP_OUT4_DIV_BYP: 1 = bypass PLLP_OUT4 divider.
23:22 0x0 PLLP_PTS: Base PLLP test output select.

21 0x0 PLLP_CLKEN_FVCO: FVCO output clock enable
20 0x0 PLLP_DCCON: Base PLLP DCCON control.
PLLP_LOCK_ENABLE:
18 0x0 0 = DISABLE
1 = ENABLE
17:12 0x0 PLLP_LOCK_SEL: Lock select.
11:8 0x1 PLLP_CPCON: Base PLLP charge pump setup control.
7:4 0x0 PLLP_LFCON: Base PLLP loop filter setup control.
3:0 0x0 PLLP_VCOCON: Base PLLP VCO range setup control.
5.7.35 CLK_RST_CONTROLLER_PLLA_BASE_0
Offset: 0xb0 │ Read/Write: R/W │ Reset: 0x0X00010c (0b000xxxxxx000xx0000000001xxx01100)
PLLA_BYPASS: 0 = no bypass, 1 = bypass.

1 = ENABLE
PLLA_ENABLE:
1 = ENABLE
PLLA_REF_DIS:
0 = REF_ENABLE
1 = REF_DISABLE
27 RO X PLLA_LOCK: 0 = not lock, 1 = lock.
22:20 RW 0x0 PLLA_DIVP: 0 = post divider (2n).
17:8 RW 0x1 PLLA_DIVN: PLL feedback divider.
4:0 RW 0xc PLLA_DIVM: PLL input divider.
5.7.36 CLK_RST_CONTROLLER_PLLA_OUT_0
Offset: 0xb4 │ Read/Write: R/W │ Reset: 0x00000002 (0bxxxxxxxxxxxxxxxx00000000xxxxxx10)
PLLA_OUT0_RATIO: PLLA_OUT0 divider from base PLLA (lsb denotes

0.5x).
15:8 0x0
0 = DISABLE
1 = ENABLE
PLLA_OUT0_CLKEN: PLLA_OUT0 divider clk enable.

1 = ENABLE

PLLA_OUT0_RSTN: PLLA_OUT0 divider reset.

0 RESET_ENABLE 0 = reset, 1 = not reset.
0 = RESET_ENABLE
1 = RESET_DISABLE
5.7.37 CLK_RST_CONTROLLER_PLLA_MISC_0
Offset: 0xbc │ Read/Write: R/W │ Reset: 0x00000100 (0bx0xxxxxx0000x0000000000100000000)
30 0x0 PLLA_OUT0_DIV_BYP: 1 = bypass PLLA_OUT0 divider.
23:22 0x0 PLLA_PTS: Base PLLA test output select.
21 0x0 PLLA_CLKEN_FVCO: FVCO output clock enable
20 0x0 PLLA_DCCON: Base PLLA DCCON control.
PLLA_LOCK_ENABLE:
18 0x0 0 = DISABLE
1 = ENABLE
17:12 0x0 PLLA_LOCK_SEL: Lock select.
11:8 0x1 PLLA_CPCON: Base PLLA charge pump setup control.
7:4 0x0 PLLA_LFCON: Base PLLA loop filter setup control.
3:0 0x0 PLLA_VCOCON: Base PLLA VCO range setup control.
5.7.38 CLK_RST_CONTROLLER_PLLU_BASE_0
Offset: 0xc0 │ Read/Write: R/W │ Reset: 0x0X00010c (0b000xxx010000xx0000000001xxx01100)
PLLU_BYPASS: 0 = no bypass, 1 = bypass.

1 = ENABLE
PLLU_ENABLE: This bit is used only when the PLLU_OVERRIDE bit is set.
1 = ENABLE
PLLU_REF_DIS:
0 = REF_ENABLE
1 = REF_DISABLE
27 RO X PLLU_LOCK: 0 = not lock, 1 = lock.
PLLU_CLKENABLE_48M: FO_48M output enable. This bit is use only when

25 RW 0x0
the PLLU_OVERRIDE bit is set.
PLLU_CLKENABLE_ICUSB: FO_ICUSB output enable. This bit is used only

23 RW 0x0
when the PLLU_OVERRIDE bit is set.

PLLU_CLKENABLE_HSIC: FO_HSIC output enable. This bit is used only

when the PLLU_OVERRIDE bit is set. Otherwise, USB controllers will control
22 RW 0x0 this automatically.
0 = disable
1 = enable
PLLU_CLKENABLE_USB: FO_USB output enable. This bit is used only when

the PLLU_OVERRIDE bit is set. Otherwise, USB controllers will control this
21 RW 0x0 automatically.
0 = disable
1 = enable
20 RW 0x0 PLLU_VCO_FREQ: 0 = post-divider of 2, 1 = post-divider of 1.
17:8 RW 0x1 PLLU_DIVN: PLL feedback divider.
4:0 RW 0xc PLLU_DIVM: PLL input divider.
5.7.39 CLK_RST_CONTROLLER_PLLU_MISC_0
Offset: 0xcc │ Read/Write: R/W │ Reset: 0x00407100 (0bxx000xxxx1xxxx000111000100000000)
29:27 0x0 PLLU_PTS: Base PLLU test output select.
PLLU_LOCK_ENABLE:
22 0x1 0 = DISABLE
1 = ENABLE
17:12 0x7 PLLU_LOCK_SEL: Lock select.
11:8 0x1 PLLU_CPCON: Base PLLU charge pump setup control.
7:4 0x0 PLLU_LFCON: Base PLLU loop filter setup control.
3:0 0x0 PLLU_VCOCON: Base PLLU VCO range setup control.
5.7.40 CLK_RST_CONTROLLER_PLLD_BASE_0
Offset: 0xd0 │ Read/Write: R/W │ Reset: 0x0X00010c (0b000xx00x0000x00000000001xxx01100)
PLLD_BYPASS: 0 = no bypass, 1 = bypass.

1 = ENABLE
PLLD_ENABLE:
1 = ENABLE
PLLD_REF_DIS: 0 = Enable reference clock, 1 = Disable reference clock.

1 = REF_DISABLE
27 RO X PLLD_LOCK: 0 = not lock, 1 = lock.
PLLD_CLKENABLE_CSI: 0 = disable, 1 = normal operation. Enable CSI fast

26 RW 0x0
and slow P/N clocks to pad macros

DSIA_CLK_SRC: Only PLLD is the source because it is only MIPI PLL.

25 RW PLL_D 0 = PLL_D
1 = PLL_D1
23 RW 0x0 CSI_CLK_SRC: 0 = Brick, 1 = PLL_D.
22:20 RW 0x0 PLLD_DIVP: 0 = Post divider (2n).
18:8 RW 0x1 PLLD_DIVN: PLL feedback divider.
4:0 RW 0xc PLLD_DIVM: PLL input divider.
5.7.41 CLK_RST_CONTROLLER_PLLD_MISC_0
Offset: 0xdc │ Read/Write: R/W │ Reset: 0x00000100 (0b00000000000000000000000100000000)
31 0x0 PLLD_FO_MODE: 1 = 5-125 MHz, 0 = 40-1000 MHz.
30 0x0 PLLD_CLKENABLE: 0 = disable, 1 = normal operation.
29:27 0x0 PLLD_PTS: Base PLLD test output select.
26:24 0x0 PLLD_LOADADJ: Load pulse position adjust.
23 0x0 PLLD_DIV_RST: 0 = normal operation, 1 = reset.
PLLD_LOCK_ENABLE:
22 0x0 0 = DISABLE
1 = ENABLE
21:16 0x0 PLLD_LOCK_SEL: Lock select.
15:12 0x0 PLLD_DCCON: Base PLLD DCCON control.
11:8 0x1 PLLD_CPCON: Base PLLD charge pump setup control.
7:4 0x0 PLLD_LFCON: Base PLLD loop filter setup control.
3:0 0x0 PLLD_VCOCON: Base PLLD VCO range setup control.
5.7.42 CLK_RST_CONTROLLER_PLLX_BASE_0
Bypass is not supported. This field is kept for legacy purposes.
Offset: 0xe0 │ Read/Write: R/W │ Reset: 0x0X00010c (0b000xxxxx0000xxxx0000000100001100)
PLLX_BYPASS: PLLX_BYPASS: 0 = no bypass, 1 = bypass.

1 = ENABLE
PLLX_ENABLE:
1 = ENABLE
PLLX_REF_DIS: 0 = Enable reference clock, 1 = Disable reference clock.

1 = REF_DISABLE

27 RO X PLLX_LOCK: 0 = Not lock, 1 = Lock.
23:20 RW 0x0 PLLX_DIVP: 0 = Post divider (2n).
15:8 RW 0x1 PLLX_DIVN: PLL feedback divider.
7:0 RW 0xc PLLX_DIVM: PLL input divider.
5.7.43 CLK_RST_CONTROLLER_PLLX_MISC_0
Note: PLLX source to cpulp (PLLX_OUT0) is divided by 2 by default. DIV2 is controlled by the
PLLX_DIV2_BYPASS_LP bit. See the warning about DIV2 programming in the
CLK_RST_CONTROLLER_CCLKLP_BURST_POLICY_0 register.
Offset: 0xe4 │ Read/Write: R/W │ Reset: 0x00000000 (0bxx00xxxx00xxx0xxxxxxxxxxxxxxxxxx)
29 0x0 PLLX_FO_LP_DISABLE: PLLX FO_LP output disable. 0=ON, 1=OFF
28 0x0 PLLX_FO_G_DISABLE: PLLX FO_G output disable. 0=ON, 1=OFF
PLLX_PTS: Base PLLX test output select.

0 = DISABLE
23:22 0x0
1 = FO
2 = VCO
PLLX_LOCK_ENABLE: 0 = DISABLE
18 0x0
1 = ENABLE
5.7.44 CLK_RST_CONTROLLER_PLLE_BASE_0
Offset: 0xe8 │ Read/Write: R/W │ Reset: 0x0d00c801 (0bx0001101000000001100100000000001)
PLLE_ENABLE: PLL enable.

1 = ENABLE
29 0x0 PLLE_LOCK_OVERRIDE: Forces PLL_LOCK and PLL_FREQLOCK to 1.
PLLE_FDIV4B: 0 = vcoclk/4, 1 = vcoclk/2 clock to the interpolator logic. Normally

28 0x0
set to 0.
27:24 0xd PLLE_PLDIV_CML: Divider control for CLOCKOUT_CML/CLOCKOUTB_CML.
23:16 0x0 PLLE_EXT_SETUP_23_16: Base PLLE setup [19:16].
15:8 0xc8 PLLE_NDIV: Feedback divider.
7:0 0x1 PLLE_MDIV: Input divider.
5.7.45 CLK_RST_CONTROLLER_PLLE_MISC_0
Offset: 0xec │ Read/Write: R/W │ Reset: 0x0000XX00 (0b0000000000000000x11xx00000000000)
31:16 RW 0x0 PLLE_SETUP: Base PLLE setup [15:0].

PLLE_IDDQ_SWCTL: 0 = The PLLE is put in IDDQ mode by hardware (SATA

+AFI+CAR) signals.1 = The PLLE is put in IDDQ by software.
14 RW 0x1
0 = OFF
1 = ON (default)
PLLE_IDDQ_OVERRIDE_VALUE: 0 = The PLLE is powered up. 1 = Software

can put the PLLE in IDDQ by setting this bit and PLLE_IDDQ_SWCTL
13 RW 0x1
0 = OFF
1 = ON (default)
PLLE_FREQLOCK: 0 = frequency acquisition not achieved, 1 = frequency

12 RO X
acquisition occurred. PLLE_LOCK_ENABLE must be enabled.
PLLE_LOCK: 0 = not lock (phase+frequency), 1 = lock (phase+frequency).

11 RO X
PLLE_LOCK_ENABLE must be enabled.
PLLE_REF_DIS:
0 = REF_ENABLE
1 = REF_DISABLE
PLLE_LOCK_ENABLE:
9 RW 0x0 0 = DISABLE
1 = ENABLE
PLLE_PTS: Bypass PLL (similar to PTO control of other PLLs).

0 = PTO is always 0 if PLLE_ENABLE=0 (SYN_CLOCKOUT=0)
8 RW 0x0
0 = PTO = PLLE CLOCKIN if PLLE_ENABLE=1
1 = PTO = PLLE FO (SYN_CLOCKOUT=VCOCLOCK/PLDIV).
7:6 RW 0x0 PLLE_KCP: Base PLLE charge pump gain control.
5:4 RW 0x0 PLLE_VREG_BG_CTRL: Base PLLE VREG BG control.
3:2 RW 0x0 PLLE_VREG_CTRL: Base PLLE VREG control.
PLLE_EN_FSTLCK:
1 = ENABLE
0 RW 0x0 PLLE_KVCO: Base PLLE VCO gain.
5.7.46 CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0
Clock Configuration for Each Peripheral

In general, each block or module has a dedicated CLK_SOURCE_ register that provides clock source and clock divider control
to that device. The clock source select is typically 2 bits long to select one of the four clock sources. The divider is typically
8 bits long, consisting of a 7-bit integer and a 1-bit fraction. Furthermore, depending on the specific module, the
CLOCK_SOURCE_ register may contain additional control bits.
Note: The 16-bit UARTA/UARTB/UARTC clock divider control is provided by the UART register
set and not by the CLK_SOURCE_ registers.
To switch from one clock source to the next, both clock sources must be active/running.
Special PLL Clock Usage by Certain Peripherals

As mentioned previously, each peripheral has a clock source select in its corresponding CLK_SOURCE_ register. There are a
number of modules that take in an additional fixed PLL clock source for portion of their logic.

Listed below are the modules/logic and the fixed PLL clock source they use.
Module/Logic Fixed PLL Clock Source Used
LFSR pllM_out0
DSI pllP_out3
DSIB pllP_out3
CSI pllP_out3
I2C1 pllP_out3
I2C2 pllP_out3
I2C3 pllP_out3
UARTA pllP_out3
UARTB pllP_out3
UARTC pllP_out3
UARTD pllP_out3
More information about clock sources and divider widths can be found under “Hardware Features” in this section.
Audio Sync Clock

The audio sync clock synchronizes communication between 2 audio devices to prevent a FIFO overrun/underrun condition in
either of the audio devices. For example, one can receive data from SPDIFIN and transmit the same data back out to an I2S
speaker. But if the SPDIFIN stream is 43.9 kHz while transmitting a 44.1 kHz sample rate to I2S, the SPDIFIN receive FIFO
can get overrun while the I2S transmit FIFO can get underrun.
Note: There is no clock switching protection for the audio sync clock so one needs to set up the
desired clock source before enabling the audio transmit/receive device.
Offset: 0x100 │ Read/Write: R/W │ Reset: 0xd0000000 (0b1101xxxxxxxxxxxxxxxxxxxx00000000)
I2S1_CLK_SRC:
000 = pllA_out0
010 = audio SYNC_CLK 1x or 2x
100 = pllP_out0
31:29 CLK_M 110 = clk_m
0 = PLLA_OUT0
2 = SYNC_CLK
4 = PLLP_OUT0
6 = CLK_M
28 0x1 I2S1_MASTER_CLKEN: Reserved.
7:0 0x0 I2S1_CLK_DIVISOR: N = Divide by (n+1) (lsb denotes 0.5x)

I2S2_CLK_SRC:
000 = pllA_out0
100 = pllP_out0
31:29 CLK_M 110 = clk_m
0 = PLLA_OUT0
2 = SYNC_CLK
4 = PLLP_OUT0
6 = CLK_M
7:0 0x0 I2S2_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.48 CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0
Offset: 0x108 │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxxxxxxxxxx00000000)
SPDIFOUT_CLK_SRC:
000 = pllA_out0
100 = pllP_out0
31:29 CLK_M 110 = clk_m
0 = PLLA_OUT0
2 = SYNC_CLK
4 = PLLP_OUT0
6 = CLK_M
7:0 0x0 SPDIF_OUT_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.49 CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0
Offset: 0x10c │ Read/Write: R/W │ Reset: 0x00000000 (0b000xxxxxxxxxxxxxxxxxxxxx00000000)
SPDIF_IN_CLK_SRC:
000 = pllP_out0
001 = pllC2_out0
010 = pllC_out0
011 = pllC3_out0
31:29 PLLP_OUT0 100 = pllM_out0
0 = PLLP_OUT0
1 = PLLC2_OUT0
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
7:0 0x0 SPDIF_IN_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)

5.7.50 CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0
PWM_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

pllC3_out0, 100 = clk_s, 110 = clk_m
0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = CLK_S
6 = CLK_M
7:0 0x0 PWM_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.51 CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0
SPI2_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

pllC3_out0, 100 = pllM_out0, 110 = clk_m
0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
7:0 0x0 SPI2_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
Offset: 0x11c │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxxxxxxxxxx00000000)

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M

5.7.53 CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0
Offset: 0x124 │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxx0000000000000000)
I2C1_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
15:0 0x0 I2C1_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 1.0x)
5.7.54 CLK_RST_CONTROLLER_CLK_SOURCE_ I2C5_0


0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M

5.7.56 CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0
Offset: 0x138 │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
DISP1_CLK_SRC: 000 = pllP_out0, 010 = pllD_out0, 100 = pllC_out0, 110 =

clk_m, 001 = pllM_out0, 011 = pllA_out0, 101 = pllD2_out0, 111 = 1'b0 Non
sequential mapping used to preserve 2 MSBs to match legacy source select.
0 = PLLP_OUT0
2 = PLLD_OUT0
31:29 CLK_M
4 = PLLC_OUT0
6 = CLK_M
1 = PLLM_OUT0
3 = PLLA_OUT0
5 = PLLD2_OUT0
5.7.57 CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0
Offset: 0x13c │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
DISP2_CLK_SRC: 000 = pllP_out0, 010 = pllD_out0, 011 = pllA_out0, 100 =

pllC_out0, 101 = pllD2_out0, 110 = clk_m, 111 = 1'b0 Non sequential mapping
used to preserve 2 MSBs to match legacy source select.
0 = PLLP_OUT0
1 = PLLM_OUT0
31:29 CLK_M
2 = PLLD_OUT0
3 = PLLA_OUT0
4 = PLLC_OUT0
5 = PLLD2_OUT0
6 = CLK_M
5.7.58 CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0
Offset: 0x144 │ Read/Write: R/W │ Reset: 0x00000000 (0b000xxx00xxxxxxxxxxxxxxxx00000000)
ISP_CLK_SRC: 000 = pllM_out0, 001 = pllC_out0, 010 = pllP_out0, 011 =

pllA_out0, 100 = pllC2_out0, 101 = pllC3_out0, 110 = clk_m, 111 = pllC4_out0
0 = PLLM_OUT0
1 = PLLC_OUT0
31:29 PLLM_OUT0 2 = PLLP_OUT0
3 = PLLA_OUT0
4 = PLLC2_OUT0
5 = PLLC3_OUT0
6 = CLK_M
7 = PLLC4_OUT0
7:0 0x0 ISP_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)

5.7.59 CLK_RST_CONTROLLER_CLK_SOURCE_VI_0
VI_CLK_SRC: 000 = pllM_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

pllC3_out0, 100 = pllP_out0, 110 = pllA_out0, 111 = pllC4_out0
0 = PLLM_OUT0
1 = PLLC2_OUT0
31:29 PLLM_OUT0 2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLP_OUT0
6 = PLLA_OUT0
7 = PLLC4_OUT0
25 0x0 PD2VI_CLK_SEL: 0 = pd2vi_clk, 1 = vi_sensor_clk.
VI_CLK_SEL: 0 = select internal clock, 1 = select external clock (pd2vi_clk).

24 INTERNAL 0 = INTERNAL
1 = EXTERNAL
7:0 0x0 VI_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.60 CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0
SDMMC1_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

pllC3_out0, 100 = pllM_out0, 101 = pllE_out0, 110 = clk_m
0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M 2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
5 = PLLE_OUT0
6 = CLK_M
7:0 0x0 SDMMC1_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)

0 = PLLP_OUT0
1 = PLLC2_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
5 = PLLE_OUT0
6 = CLK_M


pllC3_out0, 100 = pllM_out0, 101 = pllE_out0, 110 = CLK_M
0 = PLLP_OUT0
1 = PLLC2_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
5 = PLLE_OUT0
6 = CLK_M
5.7.63 CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0
VFIR_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
7:0 0x0 VFIR_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.64 CLK_RST_CONTROLLER_CLK_SOURCE_HSI_0
HSI_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
7:0 0x0 HSI_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.65 CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0
Offset: 0x178 │ Read/Write: R/W │ Reset: 0xc0000002 (0b110xxxx0xxxxxxxx0000000000000010)
UARTA_CLK_SRC: UART baud clock divisors by default come directly from the
UART DLM/DLL registers in 16.0 format. Enable UART_DIV_ENB to use the 15.1
divisor below. 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =
0 = PLLP_OUT0
31:29 CLK_M
1 = PLLC2_OUT0
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M

UARTA_DIV_ENB: 0=Use UART DLM/DLL, 1=Use divisor below

1 = ENABLE
15:0 0x2 UARTA_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.66 CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0
Offset: 0x17c │ Read/Write: R/W │ Reset: 0xc0000002 (0b110xxxx0xxxxxxxx0000000000000010)
UARTB_CLK_SRC: UART baud clock divisors by default come directly from the
0 = PLLP_OUT0
31:29 CLK_M
1 = PLLC2_OUT0
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
UARTB_DIV_ENB: 0=Use UART DLM/DLL, 1=Use divisor below

1 = ENABLE
15:0 0x2 UARTB_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.67 CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0
Offset: 0x180 │ Read/Write: R/W │ Reset: 0x00000000 (0b000xxxxxxxxxxxxx0000000000000000)
HOST1X_CLK_SRC: 000 = pllM_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

pllC3_out0, 100 = pllP_out0, 110 = pllA_out0
0 = PLLM_OUT0
1 = PLLC2_OUT0
31:29 PLLM_OUT0
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLP_OUT0
6 = PLLA_OUT0
HOST1X_IDLE_DIVISOR: N = Divide by (n+1) (lsb denotes 0.5x). If all 0s, this idle
15:8 0x0 divisor field will not be used. For non-zero values, when host1x is idle, this field will
be used instead of HOST1X_CLK_DIVISOR.
7:0 0x0 HOST1X_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)

5.7.68 CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0
HDMI_CLK_SRC: 000 = pllP_out0, 001 = pllM_out0, 010 = pllD_out0, 011 =

pllA_out0, 100 = pllC_out0, 101 = pllD2_out0, 110 = clk_m, 101 = pllD2_out0, 111
= 1'b0. Non sequential mapping is used to preserve 2 MSBs to match legacy
source select.
0 = PLLP_OUT0
1 = PLLM_OUT0
31:29 CLK_M
2 = PLLD_OUT0
3 = PLLA_OUT0
4 = PLLC_OUT0
5 = PLLD2_OUT0
6 = CLK_M
7:0 0x0 HDMI_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
5.7.70 CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0
When changing the EMC frequency, internal logic sequencing handles the requirement that the DRAMs must be placed into
self-refresh before its clock frequency is changed.
To support this, certain register fields when written do not get immediately applied but rather are applied at the correct time
during the sequencing. These registers are referred to as "shadowed".
Other register fields initiate the sequencing state machine and therefore should be written last. Note that the value of the field
must change to start the state machine - simply writing the same value to the field is insufficient.
At the end of the sequencing, the DRAMs are restored to being operational.
As an alternative to writing one of the sequencing initiating fields, the FORCE_CC_TRIGGER is provided to force the state
machine to run. This is not the recommended method.
There are EMC/MC configuration registers that are shadowed or can initiate a clock change sequence are described below:
 Initiates sequencing (value must change):

 CLK_SOURCE_EMC.EMC_2X_CLK_SRC
 EMC_2X_CLK_DIVISOR
 MC_EMC_SAME_FREQ

 FORCE_CC_TRIGGER
 Shadowed (will be applied during sequencing):
 CLK_SOURCE_EMC.EMC_2X_CLK_SRC
 EMC_2X_CLK_DIVISOR
 MC_EMC_SAME_FREQ
 Not shadowed:
 CLK_SOURCE_EMC.EMC_INVERT_DCD (must be set during initial configuration and before the EMC clock is
started)
Offset: 0x19c │ Read/Write: R/W │ Reset: 0x60000000 (0b0110000xxxxxxxx0xxxxxxxx00000000)
EMC_2X_CLK_SRC: 000 = pllM_out0, 001 = pllC_out0, 010 = pllP_out0, 011 =

clk_m, 100 = pllM_out_for_emc undivided PllM_out0, 101 = pllC2_out, 110 =
pllC3_out, 111 = PLLC_UD.
0 = PLLM_OUT0
1 = PLLC_OUT0
31:29 CLK_M 2 = PLLP_OUT0
3 = CLK_M
4 = PLLM_UD
5 = PLLC2_OUT0
6 = PLLC3_OUT0
7 = PLLC_UD
CLK_DIS_SOC_MC: 1 = Disable the SOC leg of the mcclk (instead of setting

28 0x0
emcclk = OSC, and killing OSC.
FORCE_CC_TRIGGER: 1 = force a trigger of clock change sequence even if

27 0x0
EMC_2X_CLK_SRC/EMC_2X_CLK_DIVISOR fields are unchanged.
EMC_INVERT_DCD: 1 = Enable inversion of DCD (duty-cycle distortion), 0 =

Disable inversion of DCD.
1 = ENABLE
25 0x0 USE_32KHZ_AS_CLK_M: 1 = CLK_M = 32kHz clock; 0 = CLK_M = OSC = clk_m
MC_EMC_SAME_FREQ: 0 = MC is 1/2 the frequency of EMC. 1 = MC has the

same frequency as the EMC.
16 DISABLE
0 = DISABLE
1 = ENABLE
7:0 0x0 EMC_2X_CLK_DIVISOR: N = Divide by (n+1) (lsb denotes 0.5x)
5.7.71 CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0
Offset: 0x1a0 │ Read/Write: R/W │ Reset: 0xc0000002 (0b110xxxx0xxxxxxxx0000000000000010)
UARTC_CLK_SRC: UART baud clock divisors by default come directly from the
pllC3_out0, 100 = pllM_out0, 110 = CLK_M.
0 = PLLP_OUT0
31:29 CLK_M
1 = PLLC2_OUT0
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M

UARTC_DIV_ENB: 0=Use UART DLM/DLL, 1=Use divisor below

1 = ENABLE
15:0 0x2 UARTC_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.72 CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0
Offset: 0x1a8 │ Read/Write: R/W │ Reset: 0x00000000 (0b000xxxxxxxxxxxxxxxxxxxxx00000000)
VI_SENSOR_CLK_SRC: 000 = pllM_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

pllC3_out0, 100 = pllP_out0, 110 = pllA_out0
0 = PLLM_OUT0
1 = PLLC2_OUT0
31:29 PLLM_OUT0
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLP_OUT0
6 = PLLA_OUT0
7:0 0x0 VI_SENSOR_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
Offset: 0x1b4 │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxxxxxxxxxx00000000)

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
Offset: 0x1b8 │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxx0000000000000000)

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
15:0 0x0 I2C3_CLK_DIVISOR: N = Divide by (n+1) (lsb denotes 1.0x)

Offset: 0x1bc │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxxxxxxxxxx00000000)

0 = PLLP_OUT0
1 = PLLC2_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
5 = PLLE_OUT0
6 = CLK_M
5.7.76 CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0
Offset: 0x1c0 │ Read/Write: R/W │ Reset: 0xc0000002 (0b110xxxx0xxxxxxxx0000000000000010)
UARTD_CLK_SRC: UART baud clock divisors by default come directly from the
divisor below. 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 = pllC3_out0,
100 = pllM_out0, 110 = clk_m
0 = PLLP_OUT0
31:29 CLK_M
1 = PLLC2_OUT0
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
UARTD_DIV_ENB: 0=Use UART DLM/DLL, 1=Use divisor below.

1 = ENABLE
15:0 0X2 UARTD_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.77 CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0
Offset: 0x1c8 │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxxxxxxxxxx00000000)
VDE_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
7:0 0x0 VDE_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)

5.7.78 CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0
Offset: 0x1cc │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxxxxxxxxxx00000000)
OWR_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
7:0 0x0 OWR_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.79 CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0
Offset: 0x1d0 │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxxxxxxxxxx00000000)
SNOR_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
7:0 0x0 SNOR_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.80 CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0
Offset: 0x1d4 │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxxxxxxxxxx00000000)
CSITE_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
7:0 0x0 CSITE_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
Offset: 0x1d8 │ Read/Write: R/W │ Reset: 0xd0000000 (0b1101xxxxxxxxxxxxxxxxxxxx00000000)
I2S0_CLK_SRC: 000 = pllA_out0, 010 = audio SYNC_CLK 1x or 2x, 100 = pllP_out0,

110 = clk_m
0 = PLLA_OUT0
31:29 CLK_M
2 = SYNC_CLK
4 = PLLP_OUT0
6 = CLK_M

5.7.82 CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0
Offset: 0x1dc │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxx0xxxxxxxxxxxxxxxxxxxxxxxxx)
25 0x0 DTV_INV_CLK: 1 = invert DTV clock.
5.7.83 CLK_RST_CONTROLLER_CLK_SOURCE_MSENC_0
Offset: 0x1f0 │ Read/Write: R/W │ Reset: 0x00000000 (0b000xxxxxxxxxxxxxxxxxxxxx00000000)
31:29 PLLM_OUT0 MSENC_CLK_SRC: 000 = pllM_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 = pllC3_out0, 100
= pllP_out0, 110 = pllA_out0
0 = PLLM_OUT0
1 = PLLC2_OUT0
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLP_OUT0
6 = PLLA_OUT0
7:0 0x0 MSENC_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.84 CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0
TSEC_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 = pllC3_out0, 100 =
pllM_out0, 101 = pllA_out0, 110 = CLK_M (osc)
0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 PLLM_OUT0 2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
5 = PLLA_OUT0
6 = CLK_M
7:0 0x0 TSEC_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.85 CLK_RST_CONTROLLER_CLK_SPARE2_0
Offset: 0x1fc │ Read/Write: R/W │ Reset: 0x00000000 (0b00000000000000000000000000000000)
31:0 0x0 OSC_CLK_SRC: RESERVED_CLK_SOURCE_OSC.
5.7.86 CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0
Offset: 0x280 │ Read/Write: R/W │ Reset: 0x01000000 (0bxxxxxx01x000x000x0xx0xxxx000xxx0)
25 DISABLE CLK_ENB_AMX1: Enable clock - AMX1


0 = DISABLE
1 = ENABLE
CLK_ENB_GPU: Enable clock - GPU

1 = ENABLE
CLK_ENB_SOR0: Enable clock - SOR0

1 = ENABLE
CLK_ENB_DPAUX: Enable clock - DPAUX

1 = ENABLE
CLK_ENB_ADX1: Enable clock - ADX1

1 = ENABLE
CLK_ENB_VIC: Enable clock - VIC

1 = ENABLE
CLK_ENB_CLK72MHZ: Enable clock - CLK72MHZ

1 = ENABLE
CLK_ENB_HDMI_AUDIO: Enable clock - HDMI AUDIO

1 = ENABLE
CLK_ENB_EMC_DLL: Enable clock - EMC DLL

1 = ENABLE
CLK_ENB_VIM2_CLK: Enable clock - CAMERA ifc 2

1 = ENABLE
CLK_ENB_I2C6: Enable clock - I2C6

1 = ENABLE
CLK_ENB_CAM_MCLK2: Enable clock - CAM_MCLK2

1 = ENABLE
CLK_ENB_CAM_MCLK: Enable clock - CAM_MCLK

1 = ENABLE
CLK_ENB_SPARE: Enable clock - SPARE

1 = ENABLE
5.7.87 CLK_RST_CONTROLLER_CLK_ENB_X_SET_0
SET_CLK_ENB_AMX1: Set enable clock - AMX1

1 = ENABLE
SET_CLK_ENB_GPU: Set enable clock - GPU

1 = ENABLE
22 DISABLE SET_CLK_ENB_SOR0: Set enable clock - SOR0

0 = DISABLE


1 = ENABLE
SET_CLK_ENB_DPAUX: Set enable clock - DPAUX

1 = ENABLE
SET_CLK_ENB_ADX1: Set enable clock - ADX1

1 = ENABLE
SET_CLK_ENB_VIC: Set enable clock - VIC

1 = ENABLE
SET_CLK_ENB_CLK72MHZ: Set enable clock - CLK72MHZ

1 = ENABLE
SET_CLK_ENB_HDMI_AUDIO: Set enable clock - HDMI AUDIO

1 = ENABLE
SET_CLK_ENB_EMC_DLL: Set enable clock - EMC DLL

1 = ENABLE
SET_CLK_ENB_VIM2_CLK: Set enable clock - CAMERA ifc 2

1 = ENABLE
SET_CLK_ENB_I2C6: Set enable clock - I2C6

1 = ENABLE
SET_CLK_ENB_CAM_MCLK2: Set enable clock - CAM_MCLK2

1 = ENABLE
SET_CLK_ENB_CAM_MCLK: Set enable clock - CAM_MCLK

1 = ENABLE
SET_CLK_ENB_SPARE: Set enable clock - SPARE

1 = ENABLE
5.7.88 CLK_RST_CONTROLLER_CLK_ENB_X_CLR_0
CLR_CLK_ENB_AMX1: Clear enable clock - AMX1

1 = ENABLE
CLR_CLK_ENB_GPU: Clear enable clock - GPU

1 = ENABLE
CLR_CLK_ENB_SOR0: Clear enable clock - SOR0

1 = ENABLE
CLR_CLK_ENB_DPAUX: Clear enable clock - DPAUX

1 = ENABLE
20 DISABLE CLR_CLK_ENB_ADX1: Clear enable clock - ADX1

0 = DISABLE


1 = ENABLE
CLR_CLK_ENB_VIC: Clear enable clock - VIC

1 = ENABLE
CLR_CLK_ENB_CLK72MHZ: Clear enable clock - CLK72MHZ

1 = ENABLE
CLR_CLK_ENB_HDMI_AUDIO: Clear enable clock - HDMI AUDIO

1 = ENABLE
CLR_CLK_ENB_EMC_DLL: Clear enable clock - EMC DLL

1 = ENABLE
CLR_CLK_ENB_VIM2_CLK: Clear enable clock - CAMERA ifc 2

1 = ENABLE
CLR_CLK_ENB_I2C6: Clear enable clock - I2C6

1 = ENABLE
CLR_CLK_ENB_CAM_MCLK2: Clear enable clock - CAM_MCLK2

1 = ENABLE
CLR_CLK_ENB_CAM_MCLK: Clear enable clock - CAM_MCLK

1 = ENABLE
CLR_CLK_ENB_SPARE: Clear enable clock - SPARE

1 = ENABLE
5.7.89 CLK_RST_CONTROLLER_RST_DEVICES_X_0
Offset: 0x28c │ Read/Write: R/W │ Reset: 0xff740041 (0b11111111x111x1xxxxxxxxxxx1xxxxx1)
SWR_AFC0_RST: Reset - AFC0

1 = ENABLE
SWR_AFC1_RST: Reset – AFC1

1 = ENABLE

1 = ENABLE

1 = ENABLE

1 = ENABLE

1 = ENABLE
25 ENABLE SWR_AMX1_RST: Reset – AMX1

0 = DISABLE


1 = ENABLE
SWR_GPU_RST: Reset - GPU

1 = ENABLE
SWR_SOR0_RST: Reset – SOR0

1 = ENABLE
SWR_DPAUX_RST: Reset - DPAUX

1 = ENABLE
SWR_ADX1_RST: Reset – ADX1

1 = ENABLE
SWR_VIC_RST: Reset - VIC

1 = ENABLE
SWR_I2C6_RST: Reset – I2C6

1 = ENABLE
SWR_SPARE_RST: Reset - SPARE

1 = ENABLE
5.7.90 CLK_RST_CONTROLLER_RST_DEV_X_SET_0
Offset: 0x290 │ Read/Write: R/W │ Reset: 0xff740041 (0b11111111x111x1xxxxxxxxxxx1xxxxx1)
SET_AFC0_RST: Set reset - AFC0

1 = ENABLE
SET_AFC1_RST: Set reset – AFC1

1 = ENABLE

1 = ENABLE

1 = ENABLE

1 = ENABLE

1 = ENABLE
SET_AMX1_RST: Set reset – AMX1

1 = ENABLE
SET_GPU_RST: Set reset - GPU

1 = ENABLE
22 ENABLE SET_SOR0_RST: Set reset – SOR0

0 = DISABLE


1 = ENABLE
SET_DPAUX_RST: Set reset - DPAUX

1 = ENABLE
SET_ADX1_RST: Set reset – ADX1

1 = ENABLE
SET_VIC_RST: Set reset - VIC

1 = ENABLE
SET_I2C6_RST: Set reset – I2C6

1 = ENABLE
SET_SPARE_RST: Set reset - SPARE

0 0x1 0 = DISABLE
1 = ENABLE
5.7.91 CLK_RST_CONTROLLER_RST_DEV_X_CLR_0
Offset: 0x294 │ Read/Write: R/W │ Reset: 0x00000001 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1)
CLR_AFC0_RST: Clear reset - AFC0

1 = ENABLE
CLR_AFC1_RST: Clear reset – AFC1

1 = ENABLE

1 = ENABLE

1 = ENABLE

1 = ENABLE

1 = ENABLE
CLR_AMX1_RST: Clear reset – AMX1

1 = ENABLE
CLR_GPU_RST: Clear reset - GPU

1 = ENABLE
CLR_SOR0_RST: Clear reset – SOR0

1 = ENABLE
CLR_DPAUX_RST: Clear reset - DPAUX

1 = ENABLE
20 ENABLE CLR_ADX1_RST: Clear reset – ADX1

0 = DISABLE


1 = ENABLE
CLR_VIC_RST: Clear reset - VIC

1 = ENABLE
CLR_I2C6_RST: Clear reset – I2C6

1 = ENABLE
CLR_SPARE_RST: Clear reset - SPARE

0 0x1 0 = DISABLE
1 = ENABLE
5.7.92 CLK_RST_CONTROLLER_DFLL_BASE_0
Offset: 0x2f4 │ Read/Write: R/W │ Reset: 0x00000001 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1)
DVFS_DFLL_RESET: Assert the reset to DFLL.

1 = ENABLE
5.7.93 CLK_RST_CONTROLLER_RST_DEV_L_SET_0
The RST_DEV_(L,H,U, V, W, X)_(SET,CLR) and CLK_ENB_(L,H,U, V, W, X)_(SET,CLR) registers are provided as an
alternate method of programming the same registers found in RST_DEVICES_(L,H,U, V, W, X) and CLK_OUT_ENB_(L,H,U,
V, W, X) registers, respectively.
Therefore, using either methods will change the same underlying peripherals reset, and clock enable control for writes. For
reads, you can use either method to retrieve the reset/clock-enable state of each peripheral.
Offset: 0x300 │ Read/Write: R/W │ Reset: 0x7cd7dXXX (0b011111xx11x1x11111x1111x11xx100x)
SET_CACHE2_RST: Set reset for the COP cache controller.

1 = ENABLE
SET_I2S0_RST: Set reset for the I2S0 controller.

1 = ENABLE
SET_VCP_RST: Set reset for the vector coprocessor.

1 = ENABLE
SET_HOST1X_RST: Set reset for the HOST1X.

1 = ENABLE
SET_DISP1_RST: Set reset for the DISP1 controller.

1 = ENABLE
SET_DISP2_RST: Set reset for the DISP2 controller.

1 = ENABLE

SET_ISP_RST: Set reset for the ISP controller.

1 = ENABLE
SET_USBD_RST: Set reset for the USB controller.

1 = ENABLE
SET_VI_RST: Set reset for the VI controller.

1 = ENABLE

1 = ENABLE
SET_PWM_RST: Set reset for the Pulse Width Modulator.

1 = ENABLE
SET_SDMMC4_RST: Set reset for the SDMMC4 controller.

1 = ENABLE

1 = ENABLE
SET_I2C1_RST: Set reset for the I2C1 controller.

1 = ENABLE

1 = ENABLE
SET_SPDIF_RST: Set reset for the S/PDIF controller.

1 = ENABLE

1 = ENABLE
SET_GPIO_RST: Set reset for the GPIO controller.

1 = ENABLE
SET_UARTB_RST: Set reset for the UARTB/VFIR controller.

1 = ENABLE
SET_UARTA_RST: Set reset for the UARTA controller.

1 = ENABLE
5 RO x SET_TMR_RST: Reserved
3 RW 0x1 SET_ISPB_RST: Set reset - ISPB
SET_TRIG_SYS_RST: Write 1 to pulse the System Reset signal.

1 = ENABLE

SET_COP_RST: Set/reset COP.

1 = ENABLE
SET_CPU_RST: Set the reset for the CPU. [CCLK Multi-Address]. This bit
can be written but it always reads as 0.
0 RO x
0 = DISABLE
1 = ENABLE
5.7.94 CLK_RST_CONTROLLER_RST_DEV_L_CLR_0
Offset: 0x304 │ Read/Write: R/W │ Reset: 0x7cd7dXXX (0b011111xx11x1x11111x1111x11xx1x0x)
CLR_CACHE2_RST: Clear reset for the COP cache controller.

1 = ENABLE
CLR_I2S0_RST: Clear reset for the I2S0 controller.

1 = ENABLE
CLR_VCP_RST: Clear reset for the vector coprocessor.

1 = ENABLE
CLR_HOST1X_RST: Clear reset for the HOST1X.

1 = ENABLE
CLR_DISP1_RST: Clear reset for the DISP1 controller.

1 = ENABLE
CLR_DISP2_RST: Clear reset for the DISP2 controller.

1 = ENABLE.
CLR_ISP_RST: Clear reset for the ISP controller.

1 = ENABLE
CLR_USBD_RST: Clear reset for the USB controller.

1 = ENABLE
CLR_VI_RST: Clear reset for the VI controller.

1 = ENABLE
CLR_I2S2_RST: Clear reset for the I2S 2 controller.

1 = ENABLE
CLR_PWM_RST: Clear reset for the Pulse Width Modulator.

1 = ENABLE
CLR_SDMMC4_RST: Clear reset for the SDMMC4 controller.

1 = ENABLE


1 = ENABLE
CLR_I2C1_RST: Clear reset for the I2C1 controller.

1 = ENABLE
CLR_I2S1_RST: Clear reset for the I2S1 controller.

1 = ENABLE
CLR_SPDIF_RST: Clear reset for the S/PDIF controller.

1 = ENABLE

1 = ENABLE
CLR_GPIO_RST: Clear reset for the GPIO controller.

8 RO X 0 = DISABLE
1 = ENABLE
CLR_UARTB_RST: Clear reset for the UARTB/VFIR controller.

1 = ENABLE
CLR_UARTA_RST: Clear reset for the UARTA controller.

1 = ENABLE
5 RO X CLR_TMR_RST: Reserved
CLR_ISPB_RST: Clear reset - ISBP

1 = ENABLE
CLR_COP_RST: Clear reset for the COP.

1 = ENABLE
CLR_CPU_RST: Clear reset for the CPU. [CCLK Multi-Address] This bit can be written but it
always reads as 0.
0 RW X
0 = DISABLE
1 = ENABLE
5.7.95 CLK_RST_CONTROLLER_RST_DEV_H_SET_0
Offset: 0x308 │ Read/Write: R/W │ Reset: 0xefddf32X (0b111x111111x111x11111x0110x1xx11x)
SET_BSEV_RST: Set reset for the BSEV controller.

1 = ENABLE
SET_BSEA_RST: Set reset for the BSEA controller.

1 = ENABLE

SET_VDE_RST: Set reset for the VDE controller.

1 = ENABLE
SET_USB3_RST: Set reset for the USB3 controller.

1 = ENABLE
SET_USB2_RST: Set reset for the USB2 controller.

1 = ENABLE
SET_EMC_RST: Set reset for the EMC controller.

1 = ENABLE
SET_MIPI_CAL_RST: Set reset for the MIPI CAL logic.

1 = ENABLE
SET_UARTC_RST: Set reset for the UARTC controller.

1 = ENABLE

1 = ENABLE
SET_CSI_RST: Set reset for the CSI controller.

1 = ENABLE
SET_HDMI_RST: Set reset for the HDMI

1 = ENABLE
SET_HSI_RST: Set reset for the MIPI baseband HSI controller.

1 = ENABLE
SET_DSI_RST: Set reset for the DSI controller.

1 = ENABLE
SET_ I2C5_RST: Set reset for the I2C5 controller.

1 = ENABLE
SET_SPI3_RST: Set reset for the SPI3 controller.

1 = ENABLE

1 = ENABLE
SET_SNOR_RST: Set reset for the NOR Flash controller.

1 = ENABLE
SET_SPI1_RST: Set reset for the SPI1 Controller.

1 = ENABLE

SET_KFUSE_RST: Set reset for the KFuse controller.

1 = ENABLE
SET_STAT_MON_RST: Set reset for the statistic monitor

1 = ENABLE
SET_APBDMA_RST: Set reset for the APB-DMA.

1 = ENABLE
SET_AHBDMA_RST: Set reset for the AHB-DMA.

1 = ENABLE
SET_MEM_RST: Set reset MC. This bit is disabled. This bit can be written but it always reads as
0.
0 RO X
0 = DISABLE
1 = ENABLE
5.7.96 CLK_RST_CONTROLLER_RST_DEV_H_CLR_0
Offset: 0x30c │ Read/Write: R/W │ Reset: 0xefddf32X (0b111x111111x111x11111x0110x1xx11x)
CLR_BSEV_RST: Clear reset for the BSEV controller.

1 = ENABLE
CLR_BSEA_RST: Clear reset for the BSEA controller.

1 = ENABLE
CLR_VDE_RST: Clear reset for the VDE controller.

1 = ENABLE
CLR_USB3_RST: Clear reset for the USB3 controller.

1 = ENABLE
CLR_USB2_RST: Clear reset for the USB2 controller.

1 = ENABLE
CLR_EMC_RST: Clear reset for the EMC controller.

1 = ENABLE
CLR_MIPI_CAL_RST: Clear reset for the MIPI CAL logic.

24 RW 0X1 0 = DISABLE
1 = ENABLE
CLR_UARTC_RST: Clear reset for the UARTC controller.

1 = ENABLE

1 = ENABLE

CLR_CSI_RST: Clear reset for the CSI controller.

1 = ENABLE
CLR_HDMI_RST: Clear reset for the HDMI.

1 = ENABLE
CLR_MIPI_RST: Clear reset for the MIPI baseband HSI controller.

1 = ENABLE
CLR_DSI_RST: Clear reset for the DSI controller.

1 = ENABLE
CLR_ I2C5_RST: Clear reset for the I2C5 controller.

1 = ENABLE
CLR_SPI3_RST: Clear reset for the SPI3 controller.

1 = ENABLE

1 = ENABLE
CLR_SNOR_RST: Clear reset for the NOR Flash controller.

1 = ENABLE

1 = ENABLE
CLR_KFUSE_RST: Clear reset for the KFuse controller.

1 = ENABLE
CLR_STAT_MON_RST: Clear reset for the statistic monitor.

1 = ENABLE
CLR_APBDMA_RST: Clear reset for the APB-DMA.

1 = ENABLE
CLR_AHBDMA_RST: Clear reset for the AHB-DMA.

1 = ENABLE
CLR_MEM_RST: Clear reset for the MC. This bit is disabled. This bit can be written but it always
reads as 0.
0 RO X
0 = DISABLE
1 = ENABLE

5.7.97 CLK_RST_CONTROLLER_RST_DEV_U_SET_0
Offset: 0x310 │ Read/Write: R/W │ Reset: 0x8a8ed5fe (0b1xxx1x1x1xxx111x110101011111111x)
SET_XUSB_DEV_RST: Set reset for the XUSB DEV logic.

31 0x1 0 = DISABLE
1 = ENABLE
SET_MSENC_RST: Set reset for the MSENC logic.

27 0x1 0 = DISABLE
1 = ENABLE
SET_XUSB_HOST_RST: Set reset for the XUSB HOST logic.

25 0x1 0 = DISABLE
1 = ENABLE
SET_EMUCIF_RST: Set reset for the EMUCIF logic

23 0x1 0 = DISABLE
1 = ENABLE
SET_TSEC_RST: Set reset for the TSEC logic

19 0x1 0 = DISABLE
1 = ENABLE
SET_DSIB_RST: Set reset for the DSIB controller

18 0x1 0 = DISABLE
1 = ENABLE
SET_I2C_SLOW_RST: Set reset for the I2C_SLOW

17 0x1 0 = DISABLE
1 = ENABLE
SET_DTV_RST: Set reset for the DTV controller.

15 0x1 0 = DISABLE
1 = ENABLE
SET_SOC_THERM_RST: Set reset for the SOC_THERM controller.

14 0x1 0 = DISABLE
1 = ENABLE
SET_TRACECLKIN_RST: Set reset for the TRACECLKIN controller.

13 0x0 0 = DISABLE
1 = ENABLE
SET_AVPUCQ_RST: Set reset for the AVPUCQ logic.

11 0x0 0 = DISABLE
1 = ENABLE
SET_PCIEXCLK_RST: Set reset for the PCIEXCLK logic.

10 0x1 0 = DISABLE
1 = ENABLE
SET_CSITE_RST: Set reset for the CSITE controller.

9 0x0 0 = DISABLE
1 = ENABLE
SET_AFI_RST: Set reset for the AFI controller.

8 0x1 0 = DISABLE
1 = ENABLE
SET_OWR_RST: Set reset for the OWR controller.

7 0x1 0 = DISABLE
1 = ENABLE

SET_PCIE_RST: Set reset for the PCIe controller.

6 0x1 0 = DISABLE
1 = ENABLE

5 0x1 0 = DISABLE
1 = ENABLE

4 0x1 0 = DISABLE
1 = ENABLE

3 0x1 0 = DISABLE
1 = ENABLE
2 0x1 SET_UARTE_RST: Reserved.
SET_UARTD_RST: Set reset for the UARTD controller.

1 0x1 0 = DISABLE
1 = ENABLE
5.7.98 CLK_RST_CONTROLLER_RST_DEV_U_CLR_0
Offset: 0x314 │ Read/Write: R/W │ Reset: 0x8a8ed5fe (0b1xxx1x1x1xxx111x110101011111111x)
CLR_XUSB_DEV_RST: Clear reset for the XUSB DEV logic.

31 0x1 0 = DISABLE
1 = ENABLE
CLR_MSENC_RST: Clear reset for the MSENC logic

27 0x1 0 = DISABLE
1 = ENABLE
CLR_XUSB_HOST_RST: Clear reset for the XUSB HOST logic.

25 0x1 0 = DISABLE
1 = ENABLE
CLR_EMUCIF_RST: Clear reset for the EMUCIF logic

23 0x1 0 = DISABLE
1 = ENABLE
CLR_TSEC_RST: Clear reset for the TSEC logic

19 0x1 0 = DISABLE
1 = ENABLE
CLR_DSIB_RST: Clear reset for the DSIB Controller

18 0x1 0 = DISABLE
1 = ENABLE
CLR_I2C_SLOW_RST: Clear reset for the I2C_SLOW

17 0x1 0 = DISABLE
1 = ENABLE
CLR_DTV_RST: Clear reset for the DTV controller

15 0x1 0 = DISABLE
1 = ENABLE
CLR_SOC_THERM_RST: Clear reset for the SOC_THERM controller.

14 0x1 0 = DISABLE
1 = ENABLE

CLR_TRACECLKIN_RST: Clear reset for the TRACECLKIN controller.

13 0x0 0 = DISABLE
1 = ENABLE
CLR_AVPUCQ_RST: Clear reset for the AVPUCQ logic.

11 0x0 0 = DISABLE
1 = ENABLE
CLR_PCIEXCLK_RST: Clear reset for the PCIEXCLK logic.

10 0x1 0 = DISABLE
1 = ENABLE
CLR_CSITE_RST: Clear reset for the CSITE controller.

9 0x0 0 = DISABLE
1 = ENABLE
CLR_AFI_RST: Clear reset for the AFI controller.

8 0x1 0 = DISABLE
1 = ENABLE
CLR_OWR_RST: Clear reset for the OWR controller.

7 0x1 0 = DISABLE
1 = ENABLE
CLR_PCIE_RST: Clear reset for the PCIe controller.

6 0x1 0 = DISABLE
1 = ENABLE

5 0x1 0 = DISABLE
1 = ENABLE

4 0x1 0 = DISABLE
1 = ENABLE

3 0x1 0 = DISABLE
1 = ENABLE
2 0x1 CLR_UARTE_RST: Reserved.
CLR_UARTD_RST: Clear reset for the UARTD controller.

1 0x1 0 = DISABLE
1 = ENABLE
5.7.99 CLK_RST_CONTROLLER_CLK_ENB_L_SET_0
SET_CLK_ENB_CACHE2: Set enable clock to COP cache controller.

31 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_I2S0: Set enable clock to I2S0 controller

30 0x0 0 = DISABLE
1 = ENABLE

SET_CLK_ENB_VCP: Set enable clock to vector coprocessor.

29 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_HOST1X: Set enable clock to HOST1X.

28 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_DISP1: Set enable clock to DISP1 controller.

27 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_DISP2: Set enable clock to DISP2 controller.

26 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_ISP: Set enable clock to ISP controller.

23 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_USBD: Set enable clock to USB controller

22 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_VI: Set enable clock to VI controller.

20 0x0 0 = DISABLE
1 = ENABLE

18 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_PWM: Set enable clock to PWM (Pulse Width Modulator)

17 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_SDMMC4: Set enable clock to SDMMC4 controller.

15 0x0 0 = DISABLE
1 = ENABLE

14 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_I2C1: Set enable clock to I2C1 controller

12 0x0 0 = DISABLE
1 = ENABLE

11 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_SPDIF: Set enable clock to S/PDIF controller

10 0x0 0 = DISABLE
1 = ENABLE

9 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_GPIO: Set enable clock to GPIO Controller

8 0x1 0 = DISABLE
1 = ENABLE

SET_CLK_ENB_UARTB: Set enable clock to UARTB/VFIR controller

7 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_UARTA: Set enable clock to UARTA controller

6 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_TMR: Set enable clock to Timer controller

5 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_RTC: Set enable clock to RTC controller

4 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_ISPB: Set enable clock - ISPB

3 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_CPU: Set enable clock to CPU. [CCLK Multi-Address]

0 0x0 0 = DISABLE
1 = ENABLE
5.7.100 CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0
CLR_CLK_ENB_CACHE2: Clear enable clock to COP cache controller.

31 0x1 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_I2S0: Clear enable clock to I2S0 controller

30 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_VCP: Clear enable clock to vector coprocessor.

29 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_HOST1X: Clear enable clock to HOST1X.

28 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_DISP1: Clear enable clock to DISP1 controller.

27 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_DISP2: Clear enable clock to DISP2 controller.

26 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_ISP: Clear enable clock to ISP controller.

23 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_USBD: Clear enable clock to USB controller

22 0x0 0 = DISABLE
1 = ENABLE

CLR_CLK_ENB_VI: Clear enable clock to VI controller.

20 0x0 0 = DISABLE
1 = ENABLE

18 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_PWM: Clear enable clock to PWM (Pulse Width Modulator)

17 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SDMMC4: Clear enable clock to SDMMC4 controller.

15 0x0 0 = DISABLE
1 = ENABLE

14 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_I2C1: Clear enable clock to I2C1 controller

12 0x0 0 = DISABLE
1 = ENABLE

11 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SPDIF: Clear enable clock to S/PDIF controller

10 0x0 0 = DISABLE
1 = ENABLE

9 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_GPIO: Clear enable clock to GPIO controller

8 0x1 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_UARTB: Clear enable clock to UARTB/VFIR controller

7 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_UARTA: Clear enable clock to UARTA controller

6 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_TMR: Clear enable clock to Timer controller

5 0x1 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_RTC: Clear enable clock to RTC controller

4 0x1 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_ISPB: Clear enable clock - ISPB

3 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_CPU: Clear enable clock to CPU.

0 0x0 0 = DISABLE
1 = ENABLE

5.7.101 CLK_RST_CONTROLLER_CLK_ENB_H_SET_0
Offset: 0x328 │ Read/Write: R/W │ Reset: 0x00000480 (0b000x000000x000x00000x1001000x000)
SET_CLK_ENB_BSEV: Set enable clock to BSEV controller.

31 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_BSEA: Set enable clock to BSEA controller

30 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_VDE: Set enable clock to VDE controller

29 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_USB3: Set enable clock to USB3 controller.

27 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_USB2: Set enable clock to USB2 controller.

26 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_EMC: Set enable clock to MC/EMC controller.

25 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_MIPI_CAL: Set enable clock to MIPI CAL logic.

24 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_UARTC: Set enable clock to UARTC controller

23 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_I2C2: Set enable clock to I2C2 controller.

22 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_CSI: Set enable clock to CSI controller.

20 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_HDMI: Set enable clock to HDMI.

19 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_HSI: Set enable clock to MIPI baseband HSI controller.

18 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_DSI: Set enable clock to DSI controller.

16 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_ I2C5: Set enable clock to I2C5 controller.

15 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_SPI3: Set enable clock to SPI 3 controller.

14 0x0 0 = DISABLE
1 = ENABLE

SET_CLK_ENB_SPI2: Set enable clock to SPI 2 controller.

12 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_SNOR: Set enable clock to NOR Flash controller.

10 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_SPI1: Set enable clock to SPI1 controller.

9 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_KFUSE: Set enable clock to KFUSE controller.

8 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_FUSE: Set enable clock to FUSE controller.

7 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_PMC: Set enable clock to PMC controller.

6 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_STAT_MON: Set enable clock to statistic monitor.

5 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_KBC: Set enable clock to keyboard controller.

4 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_APBDMA: Set enable clock to APB-DMA.

2 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_AHBDMA: Set enable clock to AHB-DMA.

1 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_MEM: Set enable clock to MC.

0 0x0 0 = DISABLE
1 = ENABLE
5.7.102 CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0
Offset: 0x32c │ Read/Write: R/W │ Reset: 0x00000480 (0b000x000000x000x00000x1001000x000)
CLR_CLK_ENB_BSEV: Clear enable clock to BSEV controller.

31 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_BSEA: Clear enable clock to BSEA controller

30 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_VDE: Clear enable clock to VDE controller

29 0x0 0 = DISABLE
1 = ENABLE

CLR_CLK_ENB_USB3: Clear enable clock to USB3 controller.

27 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_USB2: Clear enable clock to USB2 controller.

26 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_EMC: Clear enable clock to MC/EMC controller.

25 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_MIPI_CAL: Clear enable clock to MIPI CAL logic.

24 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_UARTC: Clear enable clock to UARTC controller.

23 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_I2C2: Clear enable clock to I2C2 controller.

22 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_CSI: Clear enable clock to CSI controller.

20 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_HDMI: Clear enable clock to HDMI.

19 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_HSI: Clear enable clock to MIPI base-band HSI controller.

18 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_DSI: Clear enable clock to DSI controller.

16 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_ I2C5: Clear enable clock to -I2C5 controller.

15 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SPI3: Clear enable clock to SPI3 controller.

14 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SPI2: Clear enable clock to SPI2 Controller.

12 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SNOR: Clear enable clock to NOR Flash Controller.

10 0x1 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SPI1: Clear enable clock to SPI1 Controller.

9 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_KFUSE: Clear enable clock to KFUSE controller.

8 0x0 0 = DISABLE
1 = ENABLE

CLR_CLK_ENB_FUSE: Clear enable clock to FUSE controller.

7 0x1 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_PMC: Clear enable clock to PMC controller.

6 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_STAT_MON: Clear enable clock to statistic monitor.

5 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_KBC: Clear enable clock to keyboard controller.

4 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_APBDMA: Clear enable clock to APB-DMA.

2 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_AHBDMA: Clear enable clock to AHB-DMA.

1 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_MEM: Clear enable clock to MC

0 0x0 0 = DISABLE
1 = ENABLE
5.7.103 CLK_RST_CONTROLLER_CLK_ENB_U_SET_0
SET_CLK_ENB_XUSB_DEV: Set enable clock to XUSB DEV.

31 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_DEV1_OUT: Set enable clock to DEV1 pad.

30 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_DEV2_OUT: Set enable clock to DEV2 pad.

29 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_SUS_OUT: Set enable clock to SUS pad.

28 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_MSENC: Set enable clock to the MSENC clock.

27 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_XUSB_HOST: Set enable clock to XUSB HOST.

25 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_CRAM2: Set enable clock for the COP cache RAM clock.
24 0x1 0 = DISABLE
1 = ENABLE

SET_CLK_ENB_IRAMD: Set enable clock for the IRAMD clock.

23 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_IRAMC: Set enable clock for the IRAMC clock.

22 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_IRAMB: Set enable clock for the IRAMB clock.

21 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_IRAMA: Set enable clock for the IRAMB clock.

20 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_TSEC: Set enable clock for the TSEC clock.

19 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_DSIB: Set enable clock to DSIB controller

18 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_I2C_SLOW: Set enable clock to I2C_SLOW

17 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_DTV: Set enable clock to DTV Controller. Moved to U:15

15 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_SOC_THERM: Set enable clock to SOC_THERM controller.

14 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_TRACECLKIN: Set enable clock to TRACECLKIN.

13 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_AVPUCQ: Set enable clock to AVPUCQ.

11 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_CSITE: Set enable clock to CSITE.

9 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_AFI: Set enable clock to AFI.

8 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_OWR: Set enable clock to OWR.

7 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_PCIE: Set enable clock to PCIe.

6 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_SDMMC3: Set enable clock to SDMMC3.

5 0x0 0 = DISABLE
1 = ENABLE

SET_CLK_ENB_SPI4: Set enable clock to SPI4.

4 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_I2C3: Set enable clock to I2C3.

3 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_UARTD: Set enable clock to UARTD.

1 0x0 0 = DISABLE
1 = ENABLE
5.7.104 CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0
CLR_CLK_ENB_XUSB_DEV: Clear enable clock to XUSB DEV.

31 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_DEV1_OUT: Clear enable clock to DEV1 pad.

30 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_DEV2_OUT: Clear enable clock to DEV2 pad.

29 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SUS_OUT: Clear enable clock to SUS pad.

28 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_MSENC: Clear enable clock to the MSENC clock.

27 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_XUSB_HOST: Clear enable clock to XUSB HOST.

25 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_CRAM2: Clear enable clock to the COP cache RAM clock.

24 0x1 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_IRAMD: Clear enable clock to the IRAMD clock.

23 0x1 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_IRAMC: Clear enable clock to the IRAMC clock.

22 0x1 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_IRAMB: Clear enable clock to the IRAMB clock.

21 0x1 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_IRAMA: Clear enable clock to the IRAMB clock.

20 0x1 0 = DISABLE
1 = ENABLE

CLR_CLK_ENB_TSEC: Clear enable clock to the TSEC clock.

19 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_DSIB: Clear enable clock to DSIB controller.

18 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_I2C_SLOW: Clear enable clock to I2C_SLOW

17 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_DTV: Clear enable clock to DTV controller.

15 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SOC_THERM: Clear enable clock to SOC_THERM controller.

14 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_TRACECLKIN: Clear enable clock to TRACECLKIN.

13 0x1 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_AVPUCQ: Clear enable clock to AVPUCQ.

11 0x1 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_CSITE: Clear enable clock to CSITE.

9 0x1 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_AFI: Clear enable clock to AFI.

8 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_OWR: Clear enable clock to OWR.

7 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_PCIE: Clear enable clock to PCIe.

6 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SDMMC3: Clear enable clock to SDMMC3.

5 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SPI4: Clear enable clock to SPI4.

4 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_I2C3: Clear enable clock to I2C3.

3 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_UARTD: Clear enable clock to UARTD.

1 0x0 0 = DISABLE
1 = ENABLE

5.7.105 CLK_RST_CONTROLLER_CCPLEX_PG_SM_OVRD_0
CCPLEX Power Gate State-Machine Overrides

This register provides the override controls for the state-machine outputs.
Offset: 0x33c │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxx000000000000000000000000)
CLKSTOP_OVRD_SCPU_NC: 1 = Clamp the corresponding clocks

23 0x0 0 = DISABLE
1 = ENABLE
CLKSTOP_OVRD_SCPU_0: 1 = Clamp the corresponding clocks

22 0x0 0 = DISABLE
1 = ENABLE
CLKSTOP_OVRD_FCPU_RAIL: 1 = Clamp the corresponding clocks

21 0x0 0 = DISABLE
1 = ENABLE
CLKSTOP_OVRD_FCPU_NC: 1 = Clamp the corresponding clocks

20 0x0 0 = DISABLE
1 = ENABLE
CLKSTOP_OVRD_FCPU_3: 1 = Clamp the corresponding clocks

19 0x0 0 = DISABLE
1 = ENABLE

18 0x0 0 = DISABLE
1 = ENABLE

17 0x0 0 = DISABLE
1 = ENABLE

16 0x0 0 = DISABLE
1 = ENABLE
RST_OVRD_SCPU_NC: 1 = Assert the corresponding reset

15 0x0 0 = DISABLE
1 = ENABLE
RST_OVRD_SCPU_0: 1 = Assert the corresponding reset

14 0x0 0 = DISABLE
1 = ENABLE
RST_OVRD_FCPU_RAIL: 1 = Assert the corresponding reset

13 0x0 0 = DISABLE
1 = ENABLE
RST_OVRD_FCPU_NC: 1 = Assert the corresponding reset

12 0x0 0 = DISABLE
1 = ENABLE
RST_OVRD_FCPU_3: 1 = Assert the corresponding reset

11 0x0 0 = DISABLE
1 = ENABLE

10 0x0 0 = DISABLE
1 = ENABLE

9 0x0 0 = DISABLE
1 = ENABLE
8 0x0 RST_OVRD_FCPU_0: 1 = Assert the corresponding reset

0 = DISABLE


1 = ENABLE
EN_RST_CG_OVRD_SCPU_NC: 1 = Select the OVRD controls in this register

7 0x0 0 = DISABLE
1 = ENABLE
EN_RST_CG_OVRD_SCPU_0: 1 = Select the OVRD controls in this register

6 0x0 0 = DISABLE
1 = ENABLE
EN_RST_CG_OVRD_FCPU_RAIL: 1 = Select the OVRD controls in this register

5 0x0 0 = DISABLE
1 = ENABLE
EN_RST_CG_OVRD_FCPU_NC: 1 = Select the OVRD controls in this register

4 0x0 0 = DISABLE
1 = ENABLE
EN_RST_CG_OVRD_FCPU_3: 1 = Select the OVRD controls in this register

3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE

1 0x0 0 = DISABLE
1 = ENABLE

0 0x0 0 = DISABLE
1 = ENABLE
5.7.106 CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0
Note: When transitioning to a new 4-bit value, all DBGRESET bits in this register which are transitioning to 1 must be set
before all DBGRESET bits which are transitioning to 0 are cleared.
Offset: 0x340 │ Read/Write: R/W │ Reset: 0x2000feef (0bx010xxx0000000001111111011101111)
SET_PRESETDBG: 1 = Assert nPRESETDBG to the debug APB interface.

30 0x0 0 = DISABLE
1 = ENABLE
SET_SCURESET: 1 = Assert reset to the whole nonCPU region of the CPU.

29 0x1 0 = DISABLE
1 = ENABLE
28 0x0 SET_PERIPHRESET: Reserved.
SET_L2RESET: 1 = Assert nL2RESET to the CPU.

24 0x0 0 = DISABLE
1 = ENABLE
SET_CXRESET3: 1 = Assert nCXRESET to CPU3.

23 0x0 0 = DISABLE
1 = ENABLE

22 0x0 0 = DISABLE
1 = ENABLE


21 0x0 0 = DISABLE
1 = ENABLE

20 0x0 0 = DISABLE
1 = ENABLE
SET_CORERESET3: 1 = Assert nCORERESET to CPU3.

19 0x0 0 = DISABLE
1 = ENABLE

18 0x0 0 = DISABLE
1 = ENABLE

17 0x0 0 = DISABLE
1 = ENABLE

16 0x0 0 = DISABLE
1 = ENABLE
SET_DBGRESET3: 1 = Assert nDBGRESET to CPU3.

15 0x1 0 = DISABLE
1 = ENABLE

14 0x1 0 = DISABLE
1 = ENABLE

13 0x1 0 = DISABLE
1 = ENABLE

12 0x1 0 = DISABLE
1 = ENABLE
11 0x1 SET_WDRESET3: Reserved.
7 0x1 SET_DERESET3: Reserved.
SET_CPURESET3: 1 = assert nCPUPORRESET to CPU3.

3 0x1 0 = DISABLE
1 = ENABLE

2 0x1 0 = DISABLE
1 = ENABLE


1 0x1 0 = DISABLE
1 = ENABLE

0 0x1 0 = DISABLE
1 = ENABLE
5.7.107 CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0
Note: When transitioning to a new 4-bit value, all DBGRESET bits in this register which are transitioning to 1 must be set
before all DBGRESET bits which are transitioning to 0 are cleared.
CLR_PRESETDBG: 1 = De-assert nPRESETDBG to the CoreSight.

30 0x0 0 = DISABLE
1 = ENABLE
CLR_NONCPURESET: 1 = De-assert reset to the whole nonCPU region of the CPU.

29 0x1 0 = DISABLE
1 = ENABLE
28 0x0 CLR_PERIPHRESET: Reserved.
CLR_L2RESET: 1 = De-assert nL2RESET to CPU.

24 0x0 0 = DISABLE
1 = ENABLE
CLR_CXRESET3: 1 = De-assert nCXRESET to CPU30 = DISABLE

23 0x0
1 = ENABLE
CLR_CXRESET2: 1 = De-assert nCXRESET to CPU2.

22 0x0 0 = DISABLE
1 = ENABLE

21 0x0 0 = DISABLE
1 = ENABLE

20 0x0 0 = DISABLE
1 = ENABLE
CLR_CORERESET3: 1 = De-assert nCORERESET to CPU3.

19 0x0 0 = DISABLE
1 = ENABLE

18 0x0 0 = DISABLE
1 = ENABLE

17 0x0 0 = DISABLE
1 = ENABLE

16 0x0 0 = DISABLE
1 = ENABLE

CLR_DBGRESET3: 1 = De-assert nDBGRESET to CPU3.

15 0x1 0 = DISABLE
1 = ENABLE

14 0x1 0 = DISABLE
1 = ENABLE

13 0x1 0 = DISABLE
1 = ENABLE

12 0x1 0 = DISABLE
1 = ENABLE
11 0x1 CLR_WDRESET3: Reserved.
7 0x1 CLR_DERESET3: Reserved.
CLR_CPURESET3: 1 = De-assert nCPUPORRESET to CPU3.

3 0x1 0 = DISABLE
1 = ENABLE

2 0x1 0 = DISABLE
1 = ENABLE

1 0x1 0 = DISABLE
1 = ENABLE

0 0x1 0 = DISABLE
1 = ENABLE
5.7.108 CLK_RST_CONTROLLER_CLK_CPU_CMPLX_SET_0
Offset: 0x348 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxx0000xxxxxxxx)
SET_CPU3_CLK_STP: 1 = Assert CPU3 clock stop

11 0x0 0 = DISABLE
1 = ENABLE

10 0x0 0 = DISABLE
1 = ENABLE


9 0x0 0 = DISABLE
1 = ENABLE

8 0x0 0 = DISABLE
1 = ENABLE
5.7.109 CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR_0
Offset: 0x34c │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxx0000xxxxxxxx)
CLR_CPU3_CLK_STP: 1 = De-assert CPU3 clock stop

11 0x0 0 = DISABLE
1 = ENABLE

10 0x0 0 = DISABLE
1 = ENABLE

9 0x0 0 = DISABLE
1 = ENABLE

8 0x0 0 = DISABLE
1 = ENABLE
5.7.110 CLK_RST_CONTROLLER_RST_DEVICES_V_0
Expanded Register Set

Bank V for required clock reset register changes. A gap is left after bank V to allow another bank, if necessary.
Offset: 0x358 │ Read/Write: R/W │ Reset: 0xff81ffeX (0b111111111xxxxxx111111111111x1xxx)
SWR_HDA_RST: Reset High Definition Audio

1 = ENABLE
SWR_SATA_RST: Reset SATA

1 = ENABLE
SWR_ACTMON_RST: Reset ACTMON

1 = ENABLE
SWR_ATOMICS_RST: Reset ATOMICS

1 = ENABLE
SWR_HDA2CODEC_2X_RST: Reset HDA2CODEC_2X

1 = ENABLE
SWR_DAM2_RST: Reset DAM2

1 = ENABLE
13 RW ENABLE SWR_DAM1_RST: Reset DAM1


0 = DISABLE
1 = ENABLE
SWR_DAM0_RST: Reset DAM0

1 = ENABLE
SWR_APBIF_RST: Reset APBIF

1 = ENABLE
SWR_AUDIO_RST: Reset AUDIO

1 = ENABLE
SWR_SPI6_RST: Reset SPI6

1 = ENABLE
SWR_SPI5_RST: Reset SPI5

1 = ENABLE
SWR_I2C4_RST: Reset I2C4

1 = ENABLE
SWR_I2S4_RST: Reset I2S4

1 = ENABLE
SWR_I2S3_RST: Reset I2S3

1 = ENABLE
SWR_MSELECT_RST: Reset MSELECT

1 = ENABLE
1 RO X SWR_CPULP_RST: Reset CPUG.
0 RO X SWR_CPUG_RST: Reserved.
5.7.111 CLK_RST_CONTROLLER_RST_DEVICES_W_0
Offset: 0x35c │ Read/Write: R/W │ Reset: 0x1f407fff (0bxxx11111x10xxxxxx111111111111111)
SWR_XUSB_SS_RST: Reset XUSB_SS logic.

1 = ENABLE
SWR_DVFS_RST: Reset CLDVFS

1 = ENABLE
SWR_ADX0_RST: Reset ADX0

1 = ENABLE
SWR_AMX0_RST: Reset AMX0

1 = ENABLE
SWR_ENTROPY_RST: Reset Entropy logic.

1 = ENABLE
14 ENABLE SWR_XUSB_PADCTL_RST: Reset XUSB PADCTL logic. IOBIST control has clock enable
only.


0 = DISABLE
1 = ENABLE
13 0x1 SWR_RESERVED10_RST: Reserved
SWR_CEC_RST: Reset CEC

1 = ENABLE
SWR_SATACOLD_RST: Reset SATACOLD

1 = ENABLE
SWR_HDA2HDMICODEC_RST: Reset HDA2HDMICODEC (no dedicated module or clock.).

1 = ENABLE
5.7.112 CLK_RST_CONTROLLER_CLK_OUT_ENB_V_0
Offset: 0x360 │ Read/Write: R/W │ Reset: 0x00400000 (0b0000000001xxxxx00000000000000x00)
CLK_ENB_HDA: Enable clock to High Definition Audio

1 = ENABLE
CLK_ENB_SATA: Enable clock to SATA

1 = ENABLE
CLK_ENB_SATA_OOB: Enable clock to SATA_OOB

1 = ENABLE
CLK_ENB_EXTPERIPH3: Enable clock to EXTPERIPH3

1 = ENABLE

1 = ENABLE

1 = ENABLE
CLK_ENB_ACTMON: Enable clock to ACTMON

1 = ENABLE

CLK_ENB_SPDIF_DOUBLER: Enable S/PDIF audio sync clock doubler.

1 = ENABLE
CLK_ENB_ATOMICS: Enable clock to ATOMICS

1 = ENABLE
CLK_ENB_HDA2CODEC_2X: Enable clock to HDA2CODEC_2X

1 = ENABLE
CLK_ENB_DAM2: Enable clock to DAM2

1 = ENABLE

1 = ENABLE

1 = ENABLE
CLK_ENB_APBIF: Enable clock to APBIF

1 = ENABLE
CLK_ENB_AUDIO: Enable clock to AUDIO

1 = ENABLE
CLK_ENB_SPI6: Enable clock to SPI6

1 = ENABLE
CLK_ENB_SPI5: Enable clock to SPI5

1 = ENABLE
CLK_ENB_I2C4: Enable clock to I2C4

1 = ENABLE
CLK_ENB_I2S4: Enable clock to I2S4

1 = ENABLE
CLK_ENB_I2S3: Enable clock to I2S3

1 = ENABLE
CLK_ENB_TSENSOR: Enable clock to TSENSOR

1 = ENABLE
CLK_ENB_MSELECT: Enable clock to MSELECT

1 = ENABLE
CLK_ENB_CPULP: Enable clock to CPULP.

1 = ENABLE
CLK_ENB_CPUG: Enable clock to CPUG.

1 = ENABLE

5.7.113 CLK_RST_CONTROLLER_CLK_OUT_ENB_W_0
Offset: 0x364 │ Read/Write: R/W │ Reset: 0x002000fc (0bxx000000x01000000x00000011111100)
CLK_ENB_EMC_LATENCY: Enable clock to EMC latency

1 = ENABLE
CLK_ENB_XUSB_SS: Enable clock to XUSB_SS

1 = ENABLE
CLK_ENB_DVFS: Enable clock to CLDVFS

1 = ENABLE
CLK_ENB_ADX0: Enable clock to ADX0

1 = ENABLE
CLK_ENB_AMX0: Enable clock to AMX0

1 = ENABLE
CLK_ENB_ENTROPY: Enable clock to ENTROPY.

1 = ENABLE
CLK_ENB_DSIB_LP: Enable clock to DSIB LP.

1 = ENABLE
CLK_ENB_DSIA_LP: Enable clock to DSIA LP.

1 = ENABLE
CLK_ENB_CILE: Enable clock to CSI CILE.

1 = ENABLE
CLK_ENB_CILCD: Enable clock to CSI CILC and CILD.

1 = ENABLE
CLK_ENB_CILAB: Enable clock to CSI CILA and CILB.

1 = ENABLE
CLK_ENB_XUSB: Enable clock to XUSB. IOBIST control has clock enable only.
1 = ENABLE
CLK_ENB_MIPI_IOBIST: Enable clock to MIPI IOBIST.

1 = ENABLE
CLK_ENB_SATA_IOBIST: Enable clock to SATA IOBIST.

1 = ENABLE
CLK_ENB_HDMI_IOBIST: Enable clock to HDMI IOBIST.

1 = ENABLE
CLK_ENB_EMC_IOBIST: Enable clock to EMC IOBIST.

1 = ENABLE
CLK_ENB_PCIE2_IOBIST: Enable clock to PCIE2 IOBIST.

1 = ENABLE

CLK_ENB_CEC: Enable clock to CEC.

1 = ENABLE
CLK_ENB_PCIERX5: Enable clock to PCIERX5. CLK_ENB_PCIE is also the master

7 0x1
control for all PCIERX* clocks.

6 0x1

5 0x1

4 0x1

3 0x1

2 0x1
CLK_ENB_RESERVED0: Unused clock enable for satacoldrstn

1 = ENABLE
CLK_ENB_HDA2HDMICODEC: Enable clock to HDA2HDMICODEC (no dedicated

module or clock).
0 DISABLE
0 = DISABLE
1 = ENABLE
5.7.114 CLK_RST_CONTROLLER_CCLKG_BURST_POLICY_0
Offset: 0x368 │ Read/Write: R/W │ Reset: 0x10XX0000 (0b00010000xxxxxxxx0000000000000000)
CPU_STATE: 0000=32 kHz Clock source; 0001=IDLE Clock Source; 001X=Run clock
0 = STDBY
31:28 RW 0x1 1 = IDLE
2 = RUN
4 = IRQ
8 = FIQ
27 RW 0x0 COP_AUTO_CWAKEUP_FROM_FIQ: 0 = NOP ; 1 = Burst on COP FIQ
26 RW 0x0 CPU_AUTO_CWAKEUP_FROM_FIQ: 0 = NOP ; 1 = Burst on CPU FIQ
25 RW 0x0 COP_AUTO_CWAKEUP_FROM_IRQ: 0 = NOP ; 1 = Burst on COP IRQ
24 RW 0x0 CPU_AUTO_CWAKEUP_FROM_IRQ: 0 = NOP ; 1 = Burst on CPU IRQ
TSENSOR_SLOWDOWN: 0 = Normal ; 1 = cpug_clk/2 triggered by the temperature

23 RO X
sensor.
16 RO X CCLK_RESERVED: Reserved. cpulp uses this bit for div2 bypass.

pllM_out0, 0100 = pllP_out0, 0101 = pllP_out4, 0110 = pllC2_out0, 0111 = pllC3_out0,
1000 = PLLX_out0 (low jitter), 1001 = dvfs_cpu_clk, 1110 = PLLX_out0, 1111 =
dvfs_cpu_clk, (low jitter)
15:12 RW 0x0 0 = CLKM
1 = PLLC_OUT0
2 = CLKS
3 = PLLM_OUT0
4 = PLLP_OUT0
5 = PLLP_OUT4


6 = PLLC2_OUT0
7 = PLLC3_OUT0
8 = PLLX_OUT0_LJ
9 = DVFS_CPU_CLK
14 = PLLX_OUT0
15 = DVFS_CPU_CLK_LJ

0 = CLKM
1 = PLLC_OUT0
2 = CLKS
3 = PLLM_OUT0
4 = PLLP_OUT0
6 = PLLC2_OUT0
7 = PLLC3_OUT0
8 = PLLX_OUT0_LJ
9 = DVFS_CPU_CLK
14 = PLLX_OUT0

0 = CLKM
1 = PLLC_OUT0
2 = CLKS
3 = PLLM_OUT0
4 = PLLP_OUT0
6 = PLLC2_OUT0
7 = PLLC3_OUT0
8 = PLLX_OUT0_LJ
9 = DVFS_CPU_CLK
14 = PLLX_OUT0

0 = CLKM
1 = PLLC_OUT0
2 = CLKS
3 = PLLM_OUT0
4 = PLLP_OUT0
6 = PLLC2_OUT0
7 = PLLC3_OUT0
8 = PLLX_OUT0_LJ
9 = DVFS_CPU_CLK
14 = PLLX_OUT0
5.7.115 CLK_RST_CONTROLLER_SUPER_CCLKG_DIVIDER_0
Offset: 0x36c │ Read/Write: R/W │ Reset: 0x00000000 (0b00x00000000000000000000000000000)

1 = ENABLE
SUPER_CDIV_USE_THERM_CONTROLS: 1 = Use thermal controls for pulse skipper

1 = ENABLE

inversion of DCD
28 DISABLE
0 = DISABLE
1 = ENABLE


5.7.116 CLK_RST_CONTROLLER_CCLKLP_BURST_POLICY_0
WARNING! The PLLX_DIV2_BYPASS_LP default is low selecting source (0b1000)= pllx/2.
This is not a glitch-less switch. Do not change the register field while CPULP is using
PLLX as a clock source.
Offset: 0x370 │ Read/Write: R/W │ Reset: 0x10X00000 (0b00010000xxxxxxx00000000000000000)
CPULP_STATE: 0000=32 kHz Clock source; 0001=IDLE Clock Source; 001X=Run

clock source; 01XX=IRQ Clock Source; 1XXX=FIQ Clock Source
0 = STDBY
31:28 RW 0x1 1 = IDLE
2 = RUN
4 = IRQ
8 = FIQ
27 RW 0x0 COP_AUTO_CWAKEUP_FROM_FIQ: 0 = NOP ; 1=Burst on COP FIQ
26 RW 0x0 CPU_AUTO_CWAKEUP_FROM_FIQ: 0 = NOP ; 1=Burst on CPU FIQ
25 RW 0x0 COP_AUTO_CWAKEUP_FROM_IRQ: 0 = NOP ; 1=Burst on COP IRQ
24 RW 0x0 CPU_AUTO_CWAKEUP_FROM_IRQ: 0 = NOP ; 1=Burst on CPU IRQ
23 RO X RESERVED: Reserved for tsensor_slowdown status for CPUG.
16 RW 0x0 PLLX_DIV2_BYPASS_LP: 0 = PLLX/2 ; 1 = PLLX/1 for source=1000

pllM_out0, 0100 = pllP_out0, 0101 = pllP_out4, 0110 = pllC2_out0, 0111 = pllC3_out0,
1000 = PLLX_out0, 1001 = Reserved, 1110 = PLLX_out0, 1111 = Reserved
0 = CLKM
1 = PLLC_OUT0
2 = CLKS
3 = PLLM_OUT0
15:12 RW 0x0 4 = PLLP_OUT0
5 = PLLP_OUT4
6 = PLLC2_OUT0
7 = PLLC3_OUT0_LJ
8 = PLLX_OUT0
9 = RESERVED9
14 = PLLX_OUT0
15 = RESERVED15

11:8 RW 0x0 0 = CLKM
1 = PLLC_OUT0
2 = CLKS


3 = PLLM_OUT0
4 = PLLP_OUT0
5 = PLLP_OUT4
6 = PLLC2_OUT0
7 = PLLC3_OUT0
8 = PLLX_OUT0_LJ
9 = RESERVED9
14 = PLLX_OUT0
15 = RESERVED15

0 = CLKM
1 = PLLC_OUT0
2 = CLKS
3 = PLLM_OUT0
4 = PLLP_OUT0
6 = PLLC2_OUT0
7 = PLLC3_OUT0
8 = PLLX_OUT0_LJ
9 = RESERVED9
14 = PLLX_OUT0
15 = RESERVED15

0 = CLKM
1 = PLLC_OUT0
2 = CLKS
3 = PLLM_OUT0
4 = PLLP_OUT0
6 = PLLC2_OUT0
7 = PLLC3_OUT0
8 = PLLX_OUT0_LJ
9 = RESERVED9
14 = PLLX_OUT0
15 = RESERVED15
5.7.117 CLK_RST_CONTROLLER_SUPER_CCLKLP_DIVIDER_0
Offset: 0x374 │ Read/Write: R/W │ Reset: 0x00000000 (0b00x00000000000000000000000000000)

1 = ENABLE
RESERVED: Reserved for cpug override of thermal control

1 = ENABLE

inversion of DCD
1 = ENABLE

5.7.118 CLK_RST_CONTROLLER_CLK_CPUG_CMPLX_0
[CCLK Multi-Address]: See “Multi-Address Tagging” in this section for more details..
The CPUG complex consists of the CPUG, L2 cache controller, and a number of bridge devices interfacing the CPUG and L2
cache to the rest of the system. Except for the CPUG, L2 cache controller, and bridge logic to external memory which always
runs at the non-divided-down CPUG frequency, other bridge devices can run at various programmable divided-down CPUG
clock ratios.
Note: Because the CPUG clock can be selected from 1-of-9 clock sources (refer to the
CCLKG_BURST_POLICY register), it is the user’s responsibility to not select a bridge divide-down CPUG
clock ratio that will exceed 1/4 of the maximum CPUG frequency supported. The maximum CPUG
frequency is 1.1 GHz.
Offset: 0x378 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxx0000xxxxxx00)
11 0x0 CPUG3_CLK_STP: 1 = CPUG3 clock stop, 0 = CPUG3 clock run.
1:0 0x0 CPU_BRIDGE_CLKDIV: Unused but available.
5.7.119 CLK_RST_CONTROLLER_CLK_CPULP_CMPLX_0
The CPULG complex consists of the CPULG, L2 cache controller, and a number of bridge devices interfacing the CPULG and
L2 cache to the rest of the system. Except for the CPULG, L2 cache controller, and bridge logic to external memory which
always runs at the non-divided-down CPULG frequency, other bridge devices can run at various programmable divided-down
CPULG clock ratios.
Note: Because the CPUG clock can be selected from 1-of-9 clock sources (refer to the
CCLKLP_BURST_POLICY register), it is the user’s responsibility to not select a bridge divide-down
CPULG clock ratio that will exceed 1/4 of the maximum CPULG frequency supported. The maximum
CPULG frequency is 1.1 GHz.
Offset: 0x37c │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxx0xxxxxxxx)
8 0x0 CPULP0_CLK_STP: 1 = CPULP0 clock stop, 0 = CPULP0 clock run.
5.7.120 CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL_0
Earlier Tegra chips had a single state-machine that took care of sequencing reset (delaying reset de-assertion based on a
timer value) in case of a flow-controller request or a WatchDog Timer (WDT) expiry request. This changed in Tegra K1 devices
because a flow-controller initiated request has more to do. The timer control of reset de-assertion for WDT initiated requests is
in the same place while the new controls have been added to the new registers.

Offset: 0x380 │ Read/Write: R/W │ Reset: 0x00000010 (0bxxxxxxxxxxxxxxxxxxxxxxxx00010000)
CPU_SOFTRST_LEGACY_WIDTH: CPU soft reset de-assertion counter value for

7:0 0x10
legacy WDT resets.
5.7.121 CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL1_0
Offset: 0x384 │ Read/Write: R/W │ Reset: 0x00040004 (0bxxxx000000000100xxxx000000000100)
27:16 0x4 CPU_SOFTRST_DEASSERT_WIDTH: CPU soft reset de-assertion counter value.
11:0 0x4 CPU_SOFTRST_ASSERT_WIDTH: CPU soft reset assertion counter value.
5.7.122 CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0
Offset: 0x388 │ Read/Write: R/W │ Reset: 0x07000200 (0b00xx011100000000xxxx001000000000)
IGNORE_HW_ACK_WIDTH: Instructs the flow control state machine to ignore the 16-
31 0x0
cpuclk counter and rely only on the sclk counts defined below.
IGNORE_SW_ACK_WIDTH: Instructs the flow control state machine to ignore the

30 0x0
ACK widths below and rely only on 16 cpuclks worth of clamp and reset.
CAR2PMC_NONCPU_ACK_WIDTH: Counter value for ack de-assertion from car2pmc

27:16 0x700 for c0nc/c1nc/crail. Program this field to 1700 cycles of 300M sclk. (~70 cycles of
osc_clk-12M)
CAR2PMC_CPU_ACK_WIDTH: Counter value for ack de-assertion from car2pmc for

11:0 0x200 fcpu0/fcpu1/fcpu2/fcpu3/scpu. Program this field to 500 cycles of 300M sclk. (~20
cycles of osc_clk - 12M)
5.7.123 CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT_0
MSELECT_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

pllC3_out0, 100 = pllM_out0, 101 = clk_s, 110 = clk_m
0 = PLLP_OUT0
1 = PLLC2_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
5 = CLK_S
6 = CLK_M
7:0 0x0 MSELECT_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.124 CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0
TSENSOR_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

pllC3_out0, 100 = clk_m, 110 = clk_s
31:29 CLK_S 0 = PLLP_OUT0
1 = PLLC2_OUT0
2 = PLLC_OUT0
3 = PLLC3_OUT0


4 = CLK_M
6 = CLK_S
7:0 0x0 TSENSOR_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
Offset: 0x3bc │ Read/Write: R/W │ Reset: 0xd0000000 (0b1101xxxxxxxxxxxxxxxxxxxx00000000)

110 = clk_m
0 = PLLA_OUT0
31:29 CLK_M
2 = SYNC_CLK
4 = PLLP_OUT0
6 = CLK_M
Offset: 0x3c0 │ Read/Write: R/W │ Reset: 0xd0000000 (0b1101xxxxxxxxxxxxxxxxxxxx00000000)

110 = clk_m
0 = PLLA_OUT0
31:29 CLK_M
2 = SYNC_CLK
4 = PLLP_OUT0
6 = CLK_M
Offset: 0x3c4 │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxx0000000000000000)

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
Offset: 0x3c8 │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxxxxxxxxxx00000000)

31:29 CLK_M pllC3_out0, 100 = pllM_out0, 110 = clk_m
0 = PLLP_OUT0


1 = PLLC2_OUT0
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
Offset: 0x3cc │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxxxxxxxxxx00000000)

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
5.7.130 CLK_RST_CONTROLLER_CLK_SOURCE_AUDIO_0
Offset: 0x3d0 │ Read/Write: R/W │ Reset: 0xd0000000 (0b1101xxxxxxx00000xxxxxxxx00000000)
AUDIO_CLK_SRC: 000 = pllA_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

pllC3_out0, 100 = pllP_out0, 110 = clk_m, 111 = audio_clk_src_alt
0 = PLLA_OUT0
1 = PLLC2_OUT0
3 = PLLC3_OUT0
4 = PLLP_OUT0
6 = CLK_M
7 = CLK_SRC_ALT
28 0x1 AUDIO_MASTER_CLKEN: Reserved.
AUDIO_CLK_SRC_DIS: 0 = Enable audio_clk_src_alt

20 ENABLE 0 = ENABLE
1 = DISABLE
AUDIO_CLK_SRC_RATE: 0000 = SPDIFIN recovered bit clock. 0001 = I2S0 bit clock.
0010 = I2S1 bit clock. 0011 = I2S2 bit clock. 0100 = I2S3 bit clock. 0101 = I2S4 bit
clock. 0110 = pllA_out0. 0111 = external vimclk (vimclk). 1xxx = Reserved.
0 = SPDIFIN
1 = I2S0
19:16 SPDIFIN 2 = I2S1
3 = I2S2
4 = I2S3
5 = I2S4
6 = PLLA_OUT0
7 = EXT_VIMCLK
7:0 0x0 AUDIO_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.131 CLK_RST_CONTROLLER_CLK_SOURCE_DAM0_0
Offset: 0x3d8 │ Read/Write: R/W │ Reset: 0xd0000000 (0b1101xxxxxxx00000xxxxxxxx00000000)

DAM0_CLK_SRC: 000 = pllA_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

pllC3_out0, 100 = pllP_out0, 110 = clk_m, 111 = dam0_clk_src_alt
0 = PLLA_OUT0
1 = PLLC2_OUT0
3 = PLLC3_OUT0
4 = PLLP_OUT0
6 = CLK_M
7 = CLK_SRC_ALT
28 0x1 DAM0_MASTER_CLKEN: Reserved.
DAM0_CLK_SRC_DIS: 0 = Enable dam0_clk_src_alt

1 = DISABLE
DAM0_CLK_SRC_RATE: 0000 = SPDIFIN recovered bit clock. 0001 = I2S0 bit clock.
0 = SPDIFIN
1 = I2S0
3 = I2S2
4 = I2S3
5 = I2S4
6 = PLLA_OUT0
7 = EXT_VIMCLK
7:0 0x0 DAM0_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
Offset: 0x3dc │ Read/Write: R/W │ Reset: 0xd0000000 (0b1101xxxxxxx00000xxxxxxxx00000000)

0 = PLLA_OUT0
1 = PLLC2_OUT0
3 = PLLC3_OUT0
4 = PLLP_OUT0
6 = CLK_M
7 = CLK_SRC_ALT

1 = DISABLE
0 = SPDIFIN
1 = I2S0
3 = I2S2
4 = I2S3
5 = I2S4
6 = PLLA_OUT0
7 = EXT_VIMCLK

Offset: 0x3e0 │ Read/Write: R/W │ Reset: 0xd0000000 (0b1101xxxxxxx00000xxxxxxxx00000000)

0 = PLLA_OUT0
1 = PLLC2_OUT0
3 = PLLC3_OUT0
4 = PLLP_OUT0
6 = CLK_M
7 = CLK_SRC_ALT

1 = DISABLE
0 = SPDIFIN
1 = I2S0
3 = I2S2
4 = I2S3
5 = I2S4
6 = PLLA_OUT0
7 = EXT_VIMCLK
5.7.134 CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0
Offset: 0x3e4 │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxxxxxxxxxx00000000)
HDA2CODEC_2X_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0,

011 = pllC3_out0, 100 = pllM_out0, 110 = clk_m
0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
7:0 0x0 HDA2CODEC_2X_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.135 CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0
Offset: 0x3e8 │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxxxxxxxxxx00000000)
ACTMON_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = CLK_S
6 = CLK_M
7:0 0x0 ACTMON_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)

5.7.136 CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0
Offset: 0x3ec │ Read/Write: R/W │ Reset: 0x60000000 (0b011xxxxxxxxxxxxxxxxxxxxx00000000)
EXTPERIPH1_CLK_SRC: 000 = pllA_out0, 001 = clk_s, 010 = pllP_out0, 011 = clk_m,

100 = pllE_out0
0 = PLLA_OUT0
31:29 CLK_M 1 = CLK_S
2 = PLLP_OUT0
3 = CLK_M
4 = PLLE_OUT0
7:0 0x0 EXTPERIPH1_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)

100 = pllE_out0
0 = PLLA_OUT0
31:29 CLK_M 1 = CLK_S
2 = PLLP_OUT0
3 = CLK_M
4 = PLLE_OUT0

100 = pllE_out0
0 = PLLA_OUT0
31:29 CLK_M 1 = CLK_S
2 = PLLP_OUT0
3 = CLK_M
4 = PLLE_OUT0
5.7.139 CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0
Offset: 0x3fc │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxxxxxxxxxx00000000)
I2C_SLOW_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = CLK_S
6 = CLK_M
7:0 0x0 I2C_SLOW_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)

5.7.140 CLK_RST_CONTROLLER_CLK_SOURCE_SYS_0
Divider only. All other controls are in SCLK_BURST_POLICY and SUPER_SCLK_DIVIDER.
7:0 0x0 SYS_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.141 CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0
Offset: 0x414 │ Read/Write: R/W │ Reset: 0xc0000000 (0b110xxxxxxxxxxxxx00xxxxxx00000000)
SOR0_CLK_SRC: 000 = pllP_out0, 001 = pllM_out0, 010 = pllD_out0, 011 =

pllA_out0, 100 = pllC_out0, 101 = PLLD2_out0, 110 = clk_m, 111 = 1'b0 Non
sequential mapping used to preserve 2 MSBS to match legacy source select.
0 = PLLP_OUT0
1 = PLLM_OUT0
31:29 CLK_M
2 = PLLD_OUT0
3 = PLLA_OUT0
4 = PLLC_OUT
5 = PLLD2_OUT2
6 = CLK_M
15 0x0 SOR0_CLK_SEL1: 0 = safe clock 24 MHz, 1 = LVDS pixel clock
SOR0_CLK_SEL0: 0 = mux output of safe_clk or LVDS pixel clock, 1 = eDP Macro

14 0x0
output
7:0 0x0 I2C_SLOW_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.142 CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0
SATA_OOB_CLK_SRC: 000 = pllP_out0, 010 = pllC_out0, 100 = pllM_out0, 110 =

clk_m
0 = PLLP_OUT0
31:29 CLK_M
2 = PLLC_OUT0
4 = PLLM_OUT0
6 = CLK_M
7:0 0x0 SATA_OOB_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.143 CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0
Offset: 0x424 │ Read/Write: R/W │ Reset: 0xc1000000 (0b110xxxx1xxxxxxxxxxxxxxxx00000000)
SATA_CLK_SRC: 000 = pllP_out0, 010 = pllC_out0, 100 = pllM_out0, 110 = clk_m

0 = PLLP_OUT0
4 = PLLM_OUT0
6 = CLK_M
SATA_AUX_CLK_ENB: ENABLE SATA Tx/Rx clocks

1 = ENABLE
7:0 0x0 SATA_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)

5.7.144 CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0
HDA_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
7:0 0x0 HDA_CLK_DIVISOR: N = Divide by (n+1) (lsb denotes 0.5x)
5.7.145 CLK_RST_CONTROLLER_RST_DEV_V_SET_0
SET_HDA_RST: Set reset for the HDA

1 = ENABLE
SET_SATA_RST: Set reset for the SATA

1 = ENABLE
SET_ACTMON_RST: Set reset for the ACTMON

1 = ENABLE
SET_ATOMICS_RST: Set reset for the ATOMICS

1 = ENABLE
SET_HDA2CODEC_2X_RST: Set reset for the HDA2CODEC_2X

1 = ENABLE
SET_DAM2_RST: Set reset for the DAM2

1 = ENABLE

1 = ENABLE

1 = ENABLE
SET_APBIF_RST: Set reset for the APBIF

1 = ENABLE
SET_AUDIO_RST: Set reset for the AUDIO

1 = ENABLE
SET_SPI6_RST: Set reset for the SPI6

1 = ENABLE
SET_SPI5_RST: Set reset for the SPI5

1 = ENABLE
7 RW 0x1 SET_I2C4_RST: Set reset for the I2C4


0 = DISABLE
1 = ENABLE
SET_I2S4_RST: Set reset for the I2S4

1 = ENABLE
SET_I2S3_RST: Set reset for the I2S3

1 = ENABLE
SET_MSELECT_RST: Set reset for the MSELECT

1 = ENABLE
SET_CPULP_RST: Set reset for the CPULP. [CCLK Multi-Address]. This bit can be written but it
always reads as 0.
1 RO X
0 = DISABLE
1 = ENABLE
SET_CPUG_RST: Set reset for the CPUG. [CCLK Multi-Address]. This bit can be written but it
always reads as 0.
0 RO X
0 = DISABLE
1 = ENABLE
5.7.146 CLK_RST_CONTROLLER_RST_DEV_V_CLR_0
CLR_HDA_RST: Clear reset for HDA

1 = ENABLE
CLR_SATA_RST: Clear reset for SATA

1 = ENABLE
CLR_ACTMON_RST: Clear reset for ACTMON

1 = ENABLE
CLR_ATOMICS_RST: Clear reset for ATOMICS

1 = ENABLE
CLR_HDA2CODEC_2X_RST: Clear reset for HDA2CODEC_2X

1 = ENABLE
CLR_DAM2_RST: Clear reset for DAM2

1 = ENABLE

1 = ENABLE

1 = ENABLE
CLR_APBIF_RST: Clear reset for APBIF

1 = ENABLE
CLR_AUDIO_RST: Clear reset for AUDIO

1 = ENABLE

CLR_SPI6_RST: Clear reset for SPI6

1 = ENABLE
CLR_SPI5_RST: Clear reset for SPI5

1 = ENABLE
CLR_I2C4_RST: Clear reset for I2C4

1 = ENABLE
CLR_I2S4_RST: Clear reset for I2S4

1 = ENABLE
CLR_I2S3_RST: Clear reset for I2S3

1 = ENABLE
CLR_MSELECT_RST: Clear reset for MSELECT

1 = ENABLE
CLR_CPULP_RST: Clear reset for CPULP. [CCLK Multi-Address]. This bit can be written but it
always reads as 0.
1 RO X
0 = DISABLE
1 = ENABLE
CLR_CPUG_RST: Clear reset for CPUG. [CCLK Multi-Address]. This bit can be written but it
always reads as 0.
0 RO X
0 = DISABLE
1 = ENABLE
5.7.147 CLK_RST_CONTROLLER_RST_DEV_W_SET_0
Offset: 0x438 │ Read/Write: R/W │ Reset: 0x1f407fff (0bxxx11111x10xxxxxx111111111111111)
SET_XUSB_SS_RST: Set reset for the XUSB_SS logic

28 0x1 0 = DISABLE
1 = ENABLE
SET_DVFS_RST: Set reset for the CLDVFS

27 0x1 0 = DISABLE
1 = ENABLE
SET_ADX0_RST: Set reset for the ADX0

26 0x1 0 = DISABLE
1 = ENABLE
SET_AMX0_RST: Set reset for the AMX0

25 0x1 0 = DISABLE
1 = ENABLE
SET_ENTROPY_RST: Set reset for the ENTROPY logic.

21 0x0 0 = DISABLE
1 = ENABLE
SET_XUSB_PADCTL_RST: Set reset for the XUSB_PADCTL logic.

14 0x1 0 = DISABLE
1 = ENABLE
13 0x1 SET_RESERVED10_RST: Reserved.

SET_CEC_RST: Set the reset for the CEC

8 0x1 0 = DISABLE
1 = ENABLE
SET_SATACOLD_RST: Set reset for the SATACOLD

1 0x1 0 = DISABLE
1 = ENABLE
SET_HDA2HDMICODEC_RST: Set reset for the HDA2HDMICODEC

0 0x1 0 = DISABLE
1 = ENABLE
5.7.148 CLK_RST_CONTROLLER_RST_DEV_W_CLR_0
Offset: 0x43c │ Read/Write: R/W │ Reset: 0x1f407fff (0bxxx11111x10xxxxxx111111111111111)
CLR_XUSB_SS_RST: Clear reset for the XUSB_SS logic.

1 = ENABLE
CLR_DVFS_RST: Clear reset for CLDVFS

1 = ENABLE
CLR_ADX0_RST: Clear reset for ADX0

1 = ENABLE
CLR_AMX0_RST: Clear reset for AMX0

1 = ENABLE
CLR_ENTROPY_RST: Clear reset for the ENTROPY logic

1 = ENABLE
CLR_XUSB_PADCTL_RST: Clear reset for XUSB_PADCTL logic

1 = ENABLE
13 RW 0x1 CLR_RESERVED10_RST: Reserved.
CLR_CEC_RST: Clear reset for CEC

1 = ENABLE

CLR_SATACOLD_RST: Clear reset for SATACOLD

1 = ENABLE
CLR_HDA2HDMICODEC_RST: Clear reset for HDA2HDMICODEC

1 = ENABLE
5.7.149 CLK_RST_CONTROLLER_CLK_ENB_V_SET_0
Offset: 0x440 │ Read/Write: R/W│ Reset: 0x00400000 (0b0000000001xxxxx00000000000000x00)
SET_CLK_ENB_HDA: Set enable clock to HDA

29 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_SATA: Set enable clock to SATA

28 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_SATA_OOB: Set enable clock to SATA_OOB

27 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_EXTPERIPH3: Set enable clock to EXTPERIPH3

26 0x0 0 = DISABLE
1 = ENABLE

25 0x0 0 = DISABLE
1 = ENABLE

24 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_ACTMON: Set enable clock to ACTMON

23 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_SPDIF_DOUBLER: Set enable clock to S/PDIF audio sync doubler

22 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_ATOMICS: Set enable clock to ATOMICS

16 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_HDA2CODEC_2X: Set enable clock to HDA2CODEC_2X

15 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_DAM2: Set enable clock to DAM2

14 0x0 0 = DISABLE
1 = ENABLE
13 0x0 SET_CLK_ENB_DAM1: Set enable clock to DAM1


0 = DISABLE
1 = ENABLE
SET_CLK_ENB_DAM0: Set enable clock to DAM0

12 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_APBIF: Set enable clock to APBIF

11 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_AUDIO: Set enable clock to AUDIO

10 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_SPI6: Set enable clock to SPI6

9 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_SPI5: Set enable clock to SPI5

8 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_I2C4: Set enable clock to I2C4

7 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_I2S4: Set enable clock to I2S4

6 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_I2S3: Set enable clock to I2S3

5 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_TSENSOR: Set enable clock to TSENSOR

4 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_MSELECT: Set enable clock to MSELECT

3 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_CPULP: Set enable clock to CPULP. [CCLK Multi-Address]

1 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_CPUG: Set enable clock to CPUG. [CCLK Multi-Address]

0 0x0 0 = DISABLE
1 = ENABLE
5.7.150 CLK_RST_CONTROLLER_CLK_ENB_V_CLR_0
Offset: 0x444 │ Read/Write: R/W │ Reset: 0x00400000 (0b0000000001xxxxx00000000000000x00)
CLR_CLK_ENB_HDA: Clear enable clock to HDA

29 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SATA: Clear enable clock to SATA

28 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SATA_OOB: Clear enable clock to SATA_OOB

27 0x0 0 = DISABLE
1 = ENABLE
26 0x0 CLR_CLK_ENB_EXTPERIPH3: Clear enable clock to EXTPERIPH3

0 = DISABLE


1 = ENABLE
CLR_CLK_ENB_EXTPERIPH2: Clear enable clock to EXTPERIPH2

25 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_EXTPERIPH1: Clear enable clock to EXTPERIPH1

24 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_ACTMON: Clear enable clock to ACTMON

23 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SPDIF_DOUBLER: Clear enable clock to S/PDIF audio sync doubler

22 0x1 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_ATOMICS: Clear enable clock to ATOMICS

16 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_HDA2CODEC_2X: Clear enable clock to HDA2CODEC_2X

15 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_DAM2: Clear enable clock to DAM2

14 0x0 0 = DISABLE
1 = ENABLE

13 0x0 0 = DISABLE
1 = ENABLE

12 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_APBIF: Clear enable clock to APBIF

11 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_AUDIO: Clear enable clock to AUDIO

10 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SPI6: Clear enable clock to SPI6

9 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SPI5: Clear enable clock to SPI5

8 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_I2C4: Clear enable clock to I2C4

7 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_I2S4: Clear enable clock to I2S4

6 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_I2S3: Clear enable clock to I2S3

5 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_TSENSOR: Clear enable clock to TSENSOR

4 0x0 0 = DISABLE
1 = ENABLE
3 0x0 CLR_CLK_ENB_MSELECT: Clear enable clock to MSELECT

0 = DISABLE


1 = ENABLE
CLR_CLK_ENB_CPULP: Clear enable clock to CPULP. [CCLK Multi-Address]

1 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_CPUG: Clear enable clock to CPUG. [CCLK Multi-Address]

0 0x0 0 = DISABLE
1 = ENABLE
5.7.151 CLK_RST_CONTROLLER_CLK_ENB_W_SET_0
Offset: 0x448 │ Read/Write: R/W │ Reset: 0x002000fc (0bxx000000x01000000x00000011111100)
SET_CLK_ENB_EMC_DLL: Set enable clock to EMC_DLL

29 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_XUSB_SS: Set enable clock to XUSB_SS

28 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_DVFS: Set enable clock to CLDVFS

27 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_ADX0: Set enable clock to ADX0

26 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_AMX0: Set the enable clock to AMX0

25 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_ENTROPY: Set the enable clock to ENTROPY.

21 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_DSIB_LP: Set the enable clock to DSIB LP.

20 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_DSIA_LP: Set the enable clock to DSIA LP.

19 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_CILE: Set the enable clock to CSI CILE.

18 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_CILCD: Set the enable clock to CSI CILC and CILD.

17 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_CILAB: Set the enable clock to CSI CILA and CILB.

16 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_XUSB: Set the enable clock to XUSB

15 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_MIPI_IOBIST: Set the enable clock to MIPI IOBIST

13 0x0 0 = DISABLE
1 = ENABLE
12 0x0 SET_CLK_ENB_SATA_IOBIST: Set the enable clock to SATA IOBIST

0 = DISABLE


1 = ENABLE
SET_CLK_ENB_HDMI_IOBIST: Set the enable clock to HDMI IOBIST

11 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_EMC_IOBIST: Set the enable clock to EMC IOBIST

10 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_PCIE2_IOBIST: Set the enable clock to PCIE2 IOBIST

9 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_CEC: Set the enable clock to CEC

8 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_PCIERX5: Set the enable clock to PCIERX5

7 0x1 0 = DISABLE
1 = ENABLE

6 0x1 0 = DISABLE
1 = ENABLE

5 0x1 0 = DISABLE
1 = ENABLE

4 0x1 0 = DISABLE
1 = ENABLE

3 0x1 0 = DISABLE
1 = ENABLE

2 0x1 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_RESERVED0: Reserved SATACOLD

1 0x0 0 = DISABLE
1 = ENABLE
SET_CLK_ENB_HDA2HDMICODEC: Set the enable clock to HDA2HDMICODEC

0 0x0 0 = DISABLE
1 = ENABLE
5.7.152 CLK_RST_CONTROLLER_CLK_ENB_W_CLR_0
Offset: 0x44c │ Read/Write: R/W │ Reset: 0x002000fc (0bxx000000x01000000x00000011111100)
CLR_CLK_ENB_EMC_LATENCY: Clear the enable clock to EMC_LATENCY

29 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_XUSB_SS: Clear the enable clock to XUSB_SS

28 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_DVFS: Clear the enable clock to CLDVFS

27 0x0 0 = DISABLE
1 = ENABLE
26 0x0 CLR_CLK_ENB_ADX0: Clear the enable clock to ADX0

0 = DISABLE


1 = ENABLE
CLR_CLK_ENB_AMX0: Clear the enable clock to AMX0

25 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_ENTROPY: Clear the enable clock to ENTROPY.

21 0x1 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_DSIB_LP: Clear the enable clock to DSIB LP.

20 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_DSIA_LP: Clear the enable clock to DSIA LP.

19 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_CILE: Clear the enable clock to CSI CILE.

18 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_CILCD: Clear the enable clock to CSI CILC and CILD.

17 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_CILAB: Clear the enable clock to CSI CILA and CILB.

16 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_XUSB: Clear the enable clock to XUSB

15 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_MIPI_IOBIST: Clear the enable clock to MIPI IOBIST

13 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_SATA_IOBIST: Clear the enable clock to SATA IOBIST

12 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_HDMI_IOBIST: Clear the enable clock to HDMI IOBIST

11 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_EMC_IOBIST: Clear the enable clock to EMC IOBIST

10 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_PCIE2_IOBIST: Clear the enable clock to PCIE2 IOBIST

9 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_CEC: Clear the enable clock to CEC

8 0x0 0 = DISABLE
1 = ENABLE
CLR_CLK_ENB_PCIERX5: Clear the enable clock to PCIERX5

7 0x1 0 = DISABLE
1 = ENABLE

6 0x1 0 = DISABLE
1 = ENABLE

5 0x1 0 = DISABLE
1 = ENABLE
4 0x1 CLR_CLK_ENB_PCIERX2: Clear the enable clock to PCIERX2

0 = DISABLE


1 = ENABLE

3 0x1 0 = DISABLE
1 = ENABLE

2 0x1 0 = DISABLE
1 = ENABLE
1 0x0 CLR_CLK_ENB_RESERVED0: Reserved.
CLR_CLK_ENB_HDA2HDMICODEC: Clear the enable clock to HDA2HDMICODEC

0 0x0 0 = DISABLE
1 = ENABLE
5.7.153 CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET_0
SET_PRESETDBG: 1 = assert nPRESETDBG to the CoreSight.

30 0x0 0 = DISABLE
1 = ENABLE
SET_NONCPURESET: 1 = Assert reset to the whole nonCPU region of the CPU. For
FCCPLEX, by default the NONCPU region is not power-gated but the reset is asserted
29 0x1 because CRAIL is power-gated by default.
0 = DISABLE
1 = ENABLE
28 0x0 SET_PERIPHRESET: Reserved.
SET_L2RESET: 1 = Assert nL2RESET to CPU.

24 0x0 0 = DISABLE
1 = ENABLE

23 0x0 0 = DISABLE
1 = ENABLE

22 0x0 0 = DISABLE
1 = ENABLE

21 0x0 0 = DISABLE
1 = ENABLE

20 0x0 0 = DISABLE
1 = ENABLE

19 0x0 0 = DISABLE
1 = ENABLE

18 0x0 0 = DISABLE
1 = ENABLE

17 0x0 0 = DISABLE
1 = ENABLE
16 0x0 SET_CORERESET0: 1 = Assert nCORERESET to CPU0.

0 = DISABLE


1 = ENABLE

15 0x1 0 = DISABLE
1 = ENABLE

14 0x1 0 = DISABLE
1 = ENABLE

13 0x1 0 = DISABLE
1 = ENABLE

12 0x1 0 = DISABLE
1 = ENABLE
SET_CPURESET3: 1 = Assert nCPUPORRESET to CPU3.

3 0x1 0 = DISABLE
1 = ENABLE

2 0x1 0 = DISABLE
1 = ENABLE

1 0x1 0 = DISABLE
1 = ENABLE

0 0x1 0 = DISABLE
1 = ENABLE
5.7.154 CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR_0

30 0x0 0 = DISABLE
1 = ENABLE

For FCCPLEX, by default the NONCPU region is not power-gated but the reset is
29 0x1 asserted because CRAIL is power-gated by default.
0 = DISABLE
1 = ENABLE
24 0x0 CLR_L2RESET: 1 = De-assert nL2RESET to CPU.


0 = DISABLE
1 = ENABLE

23 0x0 0 = DISABLE
1 = ENABLE

22 0x0 0 = DISABLE
1 = ENABLE

21 0x0 0 = DISABLE
1 = ENABLE

20 0x0 0 = DISABLE
1 = ENABLE

19 0x0 0 = DISABLE
1 = ENABLE

18 0x0 0 = DISABLE
1 = ENABLE

17 0x0 0 = DISABLE
1 = ENABLE

16 0x0 0 = DISABLE
1 = ENABLE

15 0x1 0 = DISABLE
1 = ENABLE

14 0x1 0 = DISABLE
1 = ENABLE

13 0x1 0 = DISABLE
1 = ENABLE

12 0x1 0 = DISABLE
1 = ENABLE

3 0x1 0 = DISABLE
1 = ENABLE
2 0x1 CLR_CPURESET2: 1 = De-assert nCPUPORRESET to CPU2.

0 = DISABLE


1 = ENABLE

1 0x1 0 = DISABLE
1 = ENABLE

0 0x1 0 = DISABLE
1 = ENABLE
5.7.155 CLK_RST_CONTROLLER_RST_CPULP_CMPLX_SET_0
Offset: 0x458 │ Read/Write: R/W │ Reset: 0x20001001 (0bx010xxx0xxx0xxx0xxx1xxx0xxx0xxx1)
SET_PRESETDBG: 1 = assert nPRESETDBG to the CoreSight.

30 0x0 0 = DISABLE
1 = ENABLE
SET_NONCPURESET: 1 = Assert reset to the whole nonCPU region of the CPU.

29 0x1 0 = DISABLE
1 = ENABLE
28 0x0 SET_PERIPHRESET: Reserved
SET_L2RESET: 1 = Assert nL2RESET to the CPU.

24 0x0 0 = DISABLE
1 = ENABLE

20 0x0 0 = DISABLE
1 = ENABLE

16 0x0 0 = DISABLE
1 = ENABLE

12 0x1 0 = DISABLE
1 = ENABLE
1 0x1 SET_CPURESET1: N/A

0 0x1 0 = DISABLE
1 = ENABLE
5.7.156 CLK_RST_CONTROLLER_RST_CPULP_CMPLX_CLR_0
Offset: 0x45c │ Read/Write: R/W │ Reset: 0x20001001 (0bx010xxx0xxx0xxx0xxx1xxx0xxx0xxx1)

30 0x0 0 = DISABLE
1 = ENABLE

29 0x1 0 = DISABLE
1 = ENABLE

CLR_L2RESET: 1 = De-assert nL2RESET to CPU.

24 0x0 0 = DISABLE
1 = ENABLE

20 0x0 0 = DISABLE
1 = ENABLE

16 0x0 0 = DISABLE
1 = ENABLE

12 0x1 0 = DISABLE
1 = ENABLE

0 0x1 0 = DISABLE
1 = ENABLE
5.7.157 CLK_RST_CONTROLLER_CLK_CPUG_CMPLX_SET_0

11 0x0 0 = DISABLE
1 = ENABLE

10 0x0 0 = DISABLE
1 = ENABLE

9 0x0 0 = DISABLE
1 = ENABLE

8 0x0 0 = DISABLE
1 = ENABLE
5.7.158 CLK_RST_CONTROLLER_CLK_CPUG_CMPLX_CLR_0

11 0x0 0 = DISABLE
1 = ENABLE

10 0x0 0 = DISABLE
1 = ENABLE
9 0x0 CLR_CPU1_CLK_STP: 1 = De-assert CPU1 clock stop

0 = DISABLE


1 = ENABLE

8 0x0 0 = DISABLE
1 = ENABLE
5.7.159 CLK_RST_CONTROLLER_CLK_CPULP_CMPLX_SET_0
Offset: 0x468 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxx0xxxxxxxx)

8 0x0 0 = DISABLE
1 = ENABLE
5.7.160 CLK_RST_CONTROLLER_CLK_CPULP_CMPLX_CLR_0
Offset: 0x46c │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxx0xxxxxxxx)

8 0x0 0 = DISABLE
1 = ENABLE
5.7.161 CLK_RST_CONTROLLER_CPU_CMPLX_STATUS_0
Offset: 0x470 │ Read/Write: RO │ Reset: 0xXXXXXX0X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
PRESETDBG: ENABLE = nPRESETDBG asserted to the CoreSight.

30 X 0 = DISABLE
1 = ENABLE
NONCPURESET: ENABLE = Reset asserted to the whole nonCPU region of the CPU
29 X 0 = DISABLE
1 = ENABLE
MCRESET: ENABLE = mcreset_ asserted

28 X 0 = DISABLE
1 = ENABLE
CSITEPTMRESET: ENABLE = nCSITEPTMRESET asserted

27 X 0 = DISABLE
1 = ENABLE
AXICIFRESET: ENABLE = nAXICIFRESET asserted

26 X 0 = DISABLE
1 = ENABLE
MPSELECTRESET: ENABLE = mselectreset asserted

25 X 0 = DISABLE
1 = ENABLE
L2RESET: ENABLE = L2RESET asserted to the CPU

24 X 0 = DISABLE
1 = ENABLE
CXRESET3: ENABLE = nCXRESET asserted to CPU3

23 X 0 = DISABLE
1 = ENABLE


22 X 0 = DISABLE
1 = ENABLE

21 X 0 = DISABLE
1 = ENABLE

20 X 0 = DISABLE
1 = ENABLE
CORERESET3: ENABLE = nCORERESET asserted to CPU3

19 X 0 = DISABLE
1 = ENABLE

18 X 0 = DISABLE
1 = ENABLE

17 X 0 = DISABLE
1 = ENABLE

16 X 0 = DISABLE
1 = ENABLE
DBGRESET3: ENABLE = nDBGRESET asserted to CPU3

15 X 0 = DISABLE
1 = ENABLE

14 X 0 = DISABLE
1 = ENABLE

13 X 0 = DISABLE
1 = ENABLE

12 X 0 = DISABLE
1 = ENABLE
11 X WDRESET3: Reserved.
CPURESET3: ENABLE = nCPUPORRESET asserted to CPU3

3 X 0 = DISABLE
1 = ENABLE

2 X 0 = DISABLE
1 = ENABLE

1 X 0 = DISABLE
1 = ENABLE

0 X 0 = DISABLE
1 = ENABLE

5.7.162 CLK_RST_CONTROLLER_INTSTATUS_0
Interrupt Status Register.
 car_int[0] = axicifreset
 car_int[1] = csiteptmreset
 car_int[2] = periphreset
 car_int[3] = scureset
 car_int[4] = cpureset_cpu0
 car_int[8] = dbgreset_cpu0
 car_int[12] = wdreset_cpu0
 car_int[16] = tsensor2car_slowdown_sclk
 car_int[17] = spare
Offset: 0x478 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxx00000000000000000000)
19:0 0x0 CAR_INT: Clear on 1-write. The init value is cleared.
5.7.163 CLK_RST_CONTROLLER_INTMASK_0
Interrupt Mask Register.
Offset: 0x47c │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxx00000000000000000000)
19:0 0x0 CAR_INTMASK: Mask 0=masked, 1=unmasked. Init masked
5.7.164 CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0
The data sampling frequency relies on a 960 MHz clock, so the goal of the PLL is to have:
In_Frequency * (PLL_VCOMULTBY2+1) * (PLL_NDIV/PLL_MDIV) = 960 MHz. With a 12 MHz input from PLL_U, the default
setting of PLL_VCOMULTBY2 = 1, PLL_NDIV = 40, and PLL_MDIV = 1 results in a correct output.
This register is used to configure the PHY PLL contained in the UTMIP module.

UTMIP PLL Configuration Register 0

Offset: 0x480 │ Read/Write: R/W │ Reset: 0x005001XX (0bx00000000101000000000001xxxxx000)
UTMIP_PLL_VREG_BG_CTRL: Voltage regulator and band-gap probe mux control.

VREG_BG_CTRL = 0 => VREG_BG_PRB = 0. VREG_BG_CTRL = 1 =>
30:29 RW 0x0
VREG_BG_PRB = bandgap. VREG_BG_CTRL = 2 => VREG_BG_PRB = Vregulator.
See cell specification.
UTMIP_PLL_VREG_CTRL: Voltage regulator voltage level control. See cell

28:27 RW 0x0
specification.
UTMIP_PLL_KCP: KCP of the UTMIP PHY PLL. Charge Pump Gain control. Default
26:25 RW 0x0
value is zero. See cell specification.
UTMIP_PLL_NDIV: NDIV[7:0] input of UTMIP PLL. This is the feedback divider on the
23:16 RW 0x50
VCO feedback. 0x0 is not allowed. See cell specification.
UTMIP_PLL_MDIV: MDIV[7:0] input of the UTMIP PLL. This is the predivide on the
15:8 RW 0x1
PLL. 0x0 is not allowed. See cell specification.
3 RO X UTMIP_PLL_RESERVED: Reserved.
UTMIP_PLL_LOCK_OVR: LOCK_OVERRIDE control of the UTMIP PLL. Forces

2 RW 0x0
PLL_LOCK to 1. See cell specification.
UTMIP_PLL_EN_FSTLCK: EN_FSTLCK input of UTMIP PLL. Reserving pin for PLL

1 RW 0x0
fast lock circuitry. See cell specification.
UTMIP_PLL_ENB_LCKDET: ENB_LCKDET input of UTMIP PLL. When set to 1,

powers down the lock detect. Setting ENB_LCKDET=X, LOCK_OVERRIDE=1,
0 RW 0x0 PLL_LOCK=1, and PLL_FREQLOCK=1 also powers down lock detect.
0 0 0->1(after lock) 0->1 (after lock) 1 0 0 0 lock detect power down. See cell
specification.
UTMIP PLL Configuration and Parameters

In normal operation, the following clock generators are in play for USB:
Crystal (Xtal) clock -> enters PLL_U to generate 12 MHz clock -> enters USB_PHY PLL to generate 480/60 MHz clock.
The following parameters control the bring-up of the PLLs (coming out of reset or suspend):
 PllUOnState: start pllu_enable_count and pll_lock_count

o Wait ~1 µs to enable the PLL_U (pllu_enable_count == ClkXtal * PLLU_ENABLE_DLY_COUNT * 8)
o Wait ~1 ms until PLL_U is stable (pll_lock_count == ClkXtal * PLLU_STABLE_COUNT * 256) => USB_PHY
PLL_ENABLE
o pll_active_count = 0
 Wait 5 µs to enable pll_active: pll_active_count == ClkXtal * PLL_ACTIVE_DLY_COUNT * 16 =>
USB_PHY PLL_ACTIVE
o Wait ~2.5 ms until USB_PHY is stable (pll_lock_count == ClkXtal * XTAL_FREQ_COUNT * 256) =>
USB_PHY
Values for a 19.2 MHz Xtal clock are:
 PLLU_ENABLE_DLY_COUNT[4:0] = 1 * 12 / 8 = 2.4 = 3 = 0x03

 PLLU_STABLE_COUNT[11:0] = 1000 * 19.2 / 256 = 75 = 0x4b
 PLL_ACTIVE_DLY_COUNT[4:0] = 10 * 19.2 / 16 = 12 = 0x0c
 XTAL_FREQ_COUNT[11:0] = 2500 * 19.2 / 256 = 187 = 0xbb

UTMIP PLL and PLLU Configuration Register 1

Offset: 0x484 │ Read/Write: R/W │ Reset: 0x180150c0 (0b00011000000000010101000011000000)
UTMIP_PLLU_ENABLE_DLY_COUNT: Controls the wait time to enable PLL_U when

31:27 0x3
coming out of suspend or reset.
26:18 0x0 UTMIP_PLL_RSVD: Reserved
17 0x0 UTMIP_FORCE_PLLU_POWERUP: Force PLL_U into power up.
UTMIP_FORCE_PLLU_POWERDOWN: Force PLL_U into power down. (Overrides

16 0x1
FORCE_PLLU_POWERUP.)
15 0x0 UTMIP_FORCE_PLL_ENABLE_POWERUP: Force UTMIP PLL pll_enable input on.
UTMIP_FORCE_PLL_ENABLE_POWERDOWN: Force UTMIP PLL pll_enable input

14 0x1
off. (Overrides FORCE_PLL_ENABLE_POWERUP.)
13 0x0 UTMIP_FORCE_PLL_ACTIVE_POWERUP: Obsolete.
12 0x1 UTMIP_FORCE_PLL_ACTIVE_POWERDOWN: Obsolete.
UTMIP_XTAL_FREQ_COUNT: Determines the time to wait until the output of UTMIP

11:0 0xc0
PLL is considered stable.
UTMIP Miscellaneous Configurations

Offset: 0x488 │ Read/Write: R/W │ Reset: 0xXX318015 (0bx1xxxx01001100011000000000010101)
UTMIP_PHY_XTAL_CLOCKEN: Selects whether to enable the crystal clock in the

30 RW 0x1
module.
29:26 RO X UTMIP_FORCE_PD_RESERVED: Reserved.
UTMIP_FORCE_PD_SAMP_D_POWERUP: Force UTMIP PLL PD_SAMP_D input

25 RW 0x0
(XUSB DEV) into power up.
UTMIP_FORCE_PD_SAMP_D_POWERDOWN: Force UTMIP PLL PD_SAMP_D

24 RW 0x1
input (XUSB DEV) into power down. (Overrides FORCE_PD_SAMP_D_POWERUP.)
23:18 RW 0xc UTMIP_PLL_ACTIVE_DLY_COUNT: 10 us / (1/19.2MHz) = 192 / 16 = 12
UTMIP_PLLU_STABLE_COUNT: PLLU frequency lock delay (See comments above

17:6 RW 0x600
on correct delay and calculation)
UTMIP_FORCE_PD_SAMP_C_POWERUP: Force UTMIP PLL PD_SAMP_C input

5 RW 0x0
into power up.
UTMIP_FORCE_PD_SAMP_C_POWERDOWN: Force UTMIP PLL PD_SAMP_C

4 RW 0x1
input into power down. (Overrides FORCE_PD_SAMP_C_POWERUP.)
UTMIP_FORCE_PD_SAMP_B_POWERUP: Force UTMIP PLL PD_SAMP_B input

3 RW 0x0
(XUSB HOST) into power up.
UTMIP_FORCE_PD_SAMP_B_POWERDOWN: Force UTMIP PLL PD_SAMP_B

2 RW 0x1
input (XUSB HOST) into power down. (Overrides FORCE_PD_SAMP_B_POWERUP.)
UTMIP_FORCE_PD_SAMP_A_POWERUP: Force UTMIP PLL PD_SAMP_A input

1 RW 0x0
into power up.
UTMIP_FORCE_PD_SAMP_A_POWERDOWN: Force UTMIP PLL PD_SAMP_A

0 RW 0x1
input into power down. (Overrides FORCE_PD_SAMP_A_POWERUP.)

5.7.167 CLK_RST_CONTROLLER_PLLE_AUX_0
The range value is the recommended range. All counters support 0-255 step range.
Offset: 0x48c │ Read/Write: R/W │ Reset: 0x0X044070 (0b0xx0xx10000001000100000001110000)
PLLE_SS_SEQ_INCLUDE: 0=Skip, 1=Include. Include PLLE spread spectrum power

sequencer. If this bit needs to be toggled, do it before writing '1' to
31 RW SKIP PLLE_SEQ_ENABLE.
0 = SKIP
1 = INCLUDE
PLLE_REF_SEL_PLLREFE: PLLE input reference clock source select2. 0 = Select

28 RW 0x0 the setting of the PLLE_REF_SRC field mentioned below, 1 = Select PLLREFE_out
which is 600M (use pre-divM=50 for 12 MHz reference)
PLLE_SEQ_STATE: PLLE power sequencer state

0 = SEQ_OFF
27:26 RO X
1 = SEQ_ON
2 = SEQ_BUSY
PLLE_SEQ_START_STATE: PLLE power sequencer start state

25 RW SEQ_ON 0 = SEQ_OFF
1 = SEQ_ON
PLLE_SEQ_ENABLE: PLLE power sequencer enable. Start state is loaded on first

cycle after set.
24 RW DISABLE
0 = DISABLE
1 = ENABLE
PLLE_SS_DLY: PT6: Delay between spread spectrum ON<->OFF transitions in SS

23:16 RW 0x4
power toggle sequence: ON->OFF->ON. Range is 0-255 ms in 1 ms steps.
PLLE_LOCK_DLY: PT5: Delay from PLLE ENABLE to lock. Range is 0-128 µs in 1 µs

15:8 RW 0x40
steps
TEST_FAST_PT: 0=Normal timer steps. 1=Fast timer steps. Fast programmable timer
7 RW 0x0 steps size for testing. Normal is per µs or ms, fast is per oscillator clock. Applies to all
programmable timer counters in SATA, PCIe and PLLE seq.
PLLE_SS_SWCTL: 0=PLLE spread spectrum configuration setup by hardware,

6 RW 0x1
1=Setup by software during training
PLLE_CONFIG_SWCTL: This bit should never be written to 0. Do not change the

setup bits once written by software. 0=PLLE config setup by hardware, 1=PLLE setup
5 RW 0x1 by software during training. Affects resettable bits when PLL is off (SETUP and
EXT_SETUP bits). All other config bits are left untouched as initialized, for example,
M/N/P, SS coefficient.
4 RW 0x1 PLLE_ENABLE_SWCTL: 0=PLLE enable by hardware, 1=PLLE enable by software
PLLE_USE_LOCKDET: 0=Use programmable delay, 1=use lockdet signals from

3 RW 0x0
PLLE
PLLE_REF_SRC: PLLE input reference clock source select. 0=OSC_DIV (options:

mux (PLLs, ext_osc), /2, /4), 1=PLLP_OUT0 (use pre-divM=18 for 12 MHz reference)
2 RW OSC_DIV
0 = OSC_DIV
1 = PLLP_OUT0
PLLE_CML1_OEN: PLLE CML1 clock out enable. Used for SATA.

1 = ENABLE
PLLE_CML0_OEN: PLLE CML0 clock out enable. Used for PCIe.

1 = ENABLE

5.7.168 CLK_RST_CONTROLLER_SATA_PLL_CFG0_0
SATA Power Sequencer Input Software Control Program Guide

The software control input can be used for test coverage or diving the power sequencer SM via software. The SATA power
sequencer is driven by 3 primary reset and power-down input signals: reset, lane_pd, and padpll_pd. The normal power-up
sequence de-asserts in this order: padpll_pd > lane_pd > reset. The normal power-down sequence asserts in this order: reset
> lane_pd > padpll_pd.
It is acceptable to assert all three signals at the same time. It is also acceptable for reset or lane_pd to return to the power-up
state in the middle of a power-down sequence.
Offset: 0x490 │ Read/Write: R/W │ Reset: 0x0X000003 (0bxxxxxx10xxxxxxxxxxxxxxxx0000x011)
SATA_SEQ_STATE: SATA power sequencer state

0 = SEQ_OFF
27:26 RO X
1 = SEQ_ON
2 = SEQ_BUSY
SATA_SEQ_START_STATE: SATA power sequencer start state

1 = SEQ_ON
SATA_SEQ_ENABLE: SATA power sequencer enable. Start state is loaded on first

cycle after set.
24 RW DISABLE
0 = DISABLE
1 = ENABLE
SATA_SEQ_PADPLL_PD_INPUT_VALUE: 0=Pad PLL is powered up, 1=Software

7 RW 0x0
control pad PLL powered down (PD) by setting this and SATA_SEQ_IN_SWCTL bit
SATA_SEQ_LANE_PD_INPUT_VALUE: 0=IO PHY is powered up, 1=Software control

6 RW 0x0
I/O PHY powered down by setting this and SATA_SEQ_IN_SWCTL bit
SATA_SEQ_RESET_INPUT_VALUE: 0=SATA reset de-asserted, 1=Software control

5 RW 0x0
reset by setting this and SATA_SEQ_IN_SWCTL bit
4 RW 0x0 SATA_SEQ_IN_SWCTL: 0=Seq input by hardware, 1=Seq input by software
SATA_PADPLL_USE_LOCKDET: 0=Use programmable delay, 1=Use lockdet signals

2 RW 0x0
from PLL
SATA_PADPLL_RESET_OVERRIDE_VALUE: 0=Pad PLL is powered up, 1=Software

1 RW 0x1
control reset by setting this and SATA_PADPLL_RESET_SWCTL bit
0 RW 0x1 SATA_PADPLL_RESET_SWCTL: 0=Reset by hardware, 1=Reset by software
5.7.169 CLK_RST_CONTROLLER_SATA_PLL_CFG1_0
The range value is the recommended range. All counters support 0-255 µs range in 1 µs steps
Offset: 0x494 │ Read/Write: R/W │ Reset: 0x20202008 (0b00100000001000000010000000001000)
SATA_LANE_IDDQ2_PADPLL_RESET_DLY: PT4: Delay from placing lane out of

31:24 0x20
IDDQ to PAD PLL in reset. Range is 0-200 µs.
SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY: PT3: Delay from SATA PAD PLL out

23:16 0x20
of IDDQ to lane placed out of IDDQ. Range is 0-64 µs.
SATA_PADPLL_PU_POST_DLY: PT2: Delay from RESET to SATA PAD PLL lock.

15:8 0x20
Range is 0-64 µs.
SATA_LANE_IDDQ2_PADPLL_IDDQ_DLY: PT1: Delay from placing lane in IDDQ to

7:0 0x8
PAD PLL in IDDQ. Range is 0-16 µs.

5.7.170 CLK_RST_CONTROLLER_PCIE_PLL_CFG_0
PCIe Power Sequencer Input Software Control Program Guide

The software control input can be used for test coverage or driving power sequencer SM via software.
The PCIe power sequencer is driven by 1 primary reset input signal: reset. Reset is expected to be held static until the power-
up or power-down sequence is complete.
Offset: 0x498 │ Read/Write: R/W │ Reset: 0x0X00000c (0bxxxxxx10xxxxxxxxxxxxxxxxxx0011xx)
PCIE_SEQ_STATE: PCIe power sequencer state

0 = SEQ_OFF
27:26 RO X
1 = SEQ_ON
2 = SEQ_BUSY
PCIE_SEQ_START_STATE: PCIe power sequencer start state

1 = SEQ_ON
PCIE_SEQ_ENABLE: PCIe power sequencer enable. Start state is loaded on first

cycle after set.
24 RW DISABLE
0 = DISABLE
1 = ENABLE
PCIE_SEQ_RESET_INPUT_VALUE: 0=PCIe reset de-asserted, 1=Software control

5 RW 0x0
reset by setting this and PCIE_SEQ_IN_SWCTL bit
PCIE_SEQ_IN_SWCTL: 0=Sequencer input by hardware, 1=Sequencer input by

4 RW 0x0
software
PCIE_XCLK_ENABLE_OVERRIDE_VALUE: Override value used only when

PCIE_XCLK_ENABLE_SWCTL is set
3 RW ENABLE
0 = DISABLE
1 = ENABLE
PCIE_XCLK_ENABLE_SWCTL: 0=XCLK enabled by hardware, 1=XCLK enabled by

2 RW 0x1
software
5.7.171 CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0
 Clock doubler with 1X/2X is available for the S/PDIF clock.
 The CLK_ENB_SPDIF_DOUBLE bits in the CLK_OUT_ENB_V register must be enabled for either SYNC_1X_CLK
or SYNC_2X_CLK to operate.
 PROG_DLY_CLK_SPDIF provides programmable delay for the S/DIF clock doublers.
Enable Sync Clocks
There are 3 related clock enables/selects to enable the sync clocks:
 CG_1. AUDIO_SYNC_CLK_SPDIF-SYNC_CLK_DIS: disable output of sync_clk mux

 CG_2. CLK_OUT_ENB_V-CLK_ENB_SPDIF_DOUBLER: disable input to doubler
 SEL_3. PROG_AUDIO_DLY_CLK-SPDIF_1X_SEL: Select 1x sync clock. 0=2x, 1=1x
Flow of Clock Logic

sync_clk mux (CG_1) -> (CG_2) (SEL_3) doubler -> clk switch
Suggested Programming for Sync Clock Enable:
 Leave CG_2 as default enabled.

 Use CG_1 to disable or enable (default) sync clock.

 Use SEL_3 to select 1x or 2x sync clock.

SYNC_CLK_DIS CLK_ENB_SPDIF_DOUBLER SPDIF_1X_SEL SYNC_CLK
0 1 0 2x (Default)
0 1 1 1x
1 1 X 0 (off, recommended)
1 X X 0 (off)
X 0 X 0 (off)
Offset: 0x49c │ Read/Write: R/W │ Reset: 0x00700000 (0bxx0xxxxx0111xxxxxxxxxxxxxxxxxxxx)
29 0x0 SPDIF_1X_SEL: Select S/PDIF 1x sync_clk. 0=sync_2x_clk, 1=sync_clk
SYNC_CLK_SPDIF_DELCLK_SEL: 16 taps of selectable delay for SYNC_CLK clock

23:20 0x7
doubler
5.7.172 CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S0_0
Audio Sync Clock Source Select

Offset: 0x4a0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx00000)
4 0x0 SYNC_CLK_DIS: 0 = Enable Audio sync clock.
SYNC_CLK_RATE: 0000 = SPDIFIN recovered bit clock. 0001 = I2S0 bit clock. 0010 =
I2S1 bit clock. 0011 = I2S2 bit clock. 0100 = I2S3 bit clock. 0101 = I2S4 bit clock. 0110
= pllA_out0. 0111 = external vimclk (vimclk). 1xxx = Reserved.
0 = SPDIFIN
1 = I2S0
3:0 0x0 2 = I2S1
3 = I2S2
4 = I2S3
5 = I2S4
6 = PLLA_OUT0
7 = EXT_VIMCLK

4 0x0 SYNC_CLK_DIS: 0 = Enable Audio sync clock
= pllA_out0. 0111 = external vimclk (vimclk). 1xxx = reserved
0 = SPDIFIN
1 = I2S0
3:0 0x0 2 = I2S1
3 = I2S2
4 = I2S3
5 = I2S4
6 = PLLA_OUT0
7 = EXT_VIMCLK


0 = SPDIFIN
1 = I2S0
3:0 0x0 2 = I2S1
3 = I2S2
4 = I2S3
5 = I2S4
6 = PLLA_OUT0
7 = EXT_VIMCLK

Offset: 0x4ac │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx00000)
0 = SPDIFIN
1 = I2S0
3:0 0x0 2 = I2S1
3 = I2S2
4 = I2S3
5 = I2S4
6 = PLLA_OUT0
7 = EXT_VIMCLK

Offset: 0x4b0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx00000)
0 = SPDIFIN
1 = I2S0
3:0 0x0 2 = I2S1
3 = I2S2
4 = I2S3
5 = I2S4
6 = PLLA_OUT0
7 = EXT_VIMCLK

5.7.177 CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0

Offset: 0x4b4 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx00000)
0 = SPDIFIN
1 = I2S0
3:0 0x0 2 = I2S1
3 = I2S2
4 = I2S3
5 = I2S4
6 = PLLA_OUT0
7 = EXT_VIMCLK
5.7.178 CLK_RST_CONTROLLER_PLLD2_BASE_0
Offset: 0x4b8 │ Read/Write: R/W │ Reset: 0xXX08010c (0b000xx00000001xx00000000100001100)
PLLD2_BYPASS: 0 = no bypass, 1 = bypass.

1 = ENABLE
PLLD2_ENABLE: 0 = disable, 1 = enable.

1 = ENABLE
PLLD2_REF_DIS: 0 = enable reference clock, 1 = disable reference clock.

1 = REF_DISABLE
28 RO X PLLD2_FREQLOCK: 0 = not lock, 1 = lock frequency
27 RO X PLLD2_LOCK: 0 = not lock, 1 = lock.
PLLD2_REF_SRC_SEL: Reference source select

sel[0]=0 && sel[1]=1 => ref_src = pllP_out0
26:25 RW 0x0 sel[0]=0 && sel[1]=0 => ref_src = osc_div_clk
0 = PLL_D
1 = PLL_D2
24 RW 0x0 PLLD2_LOCK_OVERRIDE:Forces PLL_LOCK to 1.
23:20 RW 0x0 PLLD2_PLDIV: 0 = PL divider.
PLLD2_IDDQ: 0 The PLL is powered up 1: Software can put the PLL in IDDQ by
setting this bit
19 RW 0x1
0 = OFF
1 = ON
16 RW 0x0 PLLD2_PTS: Base PLLD2 test output select.
15:8 RW 0x1 PLLD2_NDIV: N divider.
7:0 RW 0xc PLLD2_MDIV: M divider.
5.7.179 CLK_RST_CONTROLLER_PLLD2_MISC_0
Offset: 0x4bc │ Read/Write: R/W │ Reset: 0xXX000000 (0b00xxx000000000000000000000000000)

PLLD2_ EN_FSTLCK: Enables Fast lock

1 = ENABLE
PLLD2_ LOCK_ENABLE: 0 = Disable, 1 = Enable.

1 = ENABLE
29:27 RO X PLLD2_MON_TEST_OUT
26:25 RW 0x0 PLLD2_ KCP:Charge pump gain control.
24 RW 0x0 PLLD2_ KVCO:VCO gain.
23:0 RW 0x0 PLLD2_ SETUP: setup[23:0].
UTMIP_PLL_CFG3_0
Offset: 0x4c0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxx0000000000000000000000000)
UTMIP_PLL_SETUP: Debug control bits. Default is 0.

setup[6:0]: Lock Detect Controls
setup[8:7]: Current source control
23:0 0x0 setup [9]: Forces loop filter to VDDA/2
setup [10]: Corevdd detection override
setup [11:20] TBD
setup [23:21]: Phase selection on CLKOUTMUX60
5.7.181 CLK_RST_CONTROLLER_PLLREFE_BASE_0
Offset: 0x4c4 │ Read/Write: R/W │ Reset: 0x00000000 (0b000000xxxxxx00000000000000000000)
PLLREFE_BYPASS: 0 = no bypass, 1 = bypass.

1 = ENABLE
PLLREFE_ENABLE:
1 = ENABLE
PLLREFE_REF_DIS: 0 = enable reference clock, 1 = disable reference clock.

29 REF_ENABLE 0 = REF_ENABLE
1 = REF_DISABLE
28:27 0x0 PLLREFE_KCP
26 0x0 PLLREFE_KVCO
19:16 0x0 PLLREFE_PLDIV
15:8 0x0 PLLREFE_NDIV
7:0 0x0 PLLREFE_MDIV

5.7.182 CLK_RST_CONTROLLER_PLLREFE_MISC_0
Offset: 0x4c8 │ Read/Write: R/W │ Reset: 0x0X010000 (0b000xxxxxxxxxx0010000000000000000)
PLLREFE_EN_FSTLCK:
1 = ENABLE
PLLREFE_LOCK_ENABLE:
1 = ENABLE
PLLREFE_LOCK_OVERRIDE. Forces PLLREFE_LOCK and PLLREFE_FREQLOCK

29 RW 0x0
to 1.
PLLREFE_FREQLOCK: 0 = frequency acquisition not achieved, 1 = frequency

25 RO X
acquisition occurred. PLLREFE_LOCK_ENABLE must be enabled.
PLLREFE_LOCK: 0 = not lock (phase+frequency), 1 = lock (phase+frequency).

24 RO X
PLLREFE_LOCK_ENABLE must be enabled.
PLLREFE_PTS:
00 = PTO is 0 (DISABLE);
18:17 RW 0x0 01 = PTO is FO;
10 = PTO is VCO out;
11 = Reserved.
PLLREFE_IDDQ: 0 = The PLLREFE is powered up. 1 = Software can put the

PLLREFE in IDDQ by setting this bit.
16 RW 0x1
0 = OFF
1 = ON
15:0 RW 0x0 PLLREFE_SETUP
5.7.183 CLK_RST_CONTROLLER_CPU_FINETRIM_BYP_0
CPU Trimmer Registers

Default
Bit Name Direction Description
Value
7 byp Read/Write 0 When asserted, the trimmer is bypassed.
When asserted, rise'rise clock propagation delay will be specified by {dr,r} fields.
6 select Read/Write 0 Otherwise, hardwired default delay will be applied. Similarly, fall'fall clock
propagation delay will be specified by {df, f} fields when select is asserted.
0: Minimal rise'rise clock propagation delay

5 dr Read/Write 0
1: Use one of the four delay steps specified by the {r} field.
4:3 r Read/Write 0 00,01,10,11: Increment rise'rise clock delay by 1, 2, 3, or 4 steps
0: Minimal fall'fall clock propagation delay

2 df Read/Write 0
1: Use one of the four delay steps specified by {f} field.
1:0 f Read/Write 0 00, 01, 10, 11: Increment fall'fall clock delay by 1, 2, 3, or 4 steps
®
These registers control the delay through the programmable trimmers (CORE_CLOCKS_shaper) inside the Cortex -A15
partitions.
 CPU_FINETRIM_BYP
 CPU_FINETRIM_SELECT
 CPU_FINETRIM_DR
 CPU_FINETRIM_DF

 CPU_FINETRIM_F
 CPU_FINETRIM_R
The naming convention of the fields of these registers is:
 FCPU_n: partition n in fast CPU cluster

 SCPU_n: partition n in slow CPU cluster
The partitions related to these registers are as follows:
 FCPU_1: fcpu0 partition

 FCPU_5: fl2 partition
 FCPU_6: ftop partition
 SCPU_7: not used
Offset: 0x4d0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxx000000000)
8 0x0 SCPU_9
7 0x0 SCPU_8
6 0x0 SCPU_7
5 0x0 FCPU_6
4 0x0 FCPU_5
3 0x0 FCPU_4
2 0x0 FCPU_3
1 0x0 FCPU_2
0 0x0 FCPU_1
5.7.184 CLK_RST_CONTROLLER_CPU_FINETRIM_SELECT_0
8 0x0 SCPU_9
7 0x0 SCPU_8
6 0x0 SCPU_7
5 0x0 FCPU_6
4 0x0 FCPU_5
3 0x0 FCPU_4
2 0x0 FCPU_3
1 0x0 FCPU_2
0 0x0 FCPU_1

5.7.185 CLK_RST_CONTROLLER_CPU_FINETRIM_DR_0
8 0x0 SCPU_9
7 0x0 SCPU_8
6 0x0 SCPU_7
5 0x0 FCPU_6
4 0x0 FCPU_5
3 0x0 FCPU_4
2 0x0 FCPU_3
1 0x0 FCPU_2
0 0x0 FCPU_1
5.7.186 CLK_RST_CONTROLLER_CPU_FINETRIM_DF_0
Offset: 0x4dc | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxx000000000)
8 0x0 SCPU_9
7 0x0 SCPU_8
6 0x0 SCPU_7
5 0x0 FCPU_6
4 0x0 FCPU_5
3 0x0 FCPU_4
2 0x0 FCPU_3
1 0x0 FCPU_2
0 0x0 FCPU_1
5.7.187 CLK_RST_CONTROLLER_CPU_FINETRIM_F_0
Offset: 0x4e0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxx000000000000000000)
17:16 0x0 SCPU_9
15:14 0x0 SCPU_8
13:12 0x0 SCPU_7
11:10 0x0 FCPU_6
9:8 0x0 FCPU_5
7:6 0x0 FCPU_4
5:4 0x0 FCPU_3
3:2 0x0 FCPU_2
1:0 0x0 FCPU_1

5.7.188 CLK_RST_CONTROLLER_CPU_FINETRIM_R_0
Offset: 0x4e4 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxx000000000000000000)
17:16 0x0 SCPU_9
15:14 0x0 SCPU_8
13:12 0x0 SCPU_7
11:10 0x0 FCPU_6
9:8 0x0 FCPU_5
7:6 0x0 FCPU_4
5:4 0x0 FCPU_3
3:2 0x0 FCPU_2
1:0 0x0 FCPU_1
5.7.189 CLK_RST_CONTROLLER_PLLC2_BASE_0
There are special startup and programming considerations for this digital PLL. Consult the datasheet for details
Some field descriptions will have a LATCHED or a DIRECT keyword:
 LATCHED: The writes to this field are latched by STROBE. Software should note that while readback will tell the last
written value, that might not be the latched value.
 DIRECT: It is a DIRECT read/write field. The writes to this field are not latched by STROBE. So, readback will always
tell the correct state.
Offset: 0x4e8 │ Read/Write: R/W │ Reset: 0x0X000101 (0b000xxxxxx000xxxx00000001xxxxxx01)
PLLC2_BYPASS: DIRECT. 0 = no bypass, 1 = bypass.

1 = ENABLE
PLLC2_ENABLE: DIRECT. 0 = disable, 1 = enable. Will invert and connect to IDDQ

1 = ENABLE
PLLC2_REF_DIS: 0 = enable reference clock, 1 = disable reference clock. To go into

the minimum power mode for the PLL, this bit must be asserted.
29 RW REF_ENABLE
0 = REF_ENABLE
1 = REF_DISABLE
27 RO X PLLC2_FREQ_LOCK: 0 = not lock, 1 = frequency is locked.
26 RO X PLLC2_PHASE_LOCK: 0 = not lock, 1 = phase is locked.
22:20 RW 0x0 PLLC2_DIVP: DIRECT. 0 = post divider (divide by N+1). “DIRECT”
15:8 RW 0x1 PLLC2_DIVN: PLL feedback divider. ” LATCHED”
PLLC2_DIVM: PLL input divider. DIRECT. 00 = Divide by 1. 01 = Divide by 1. 10 =

1:0 RW 0x1
Divide by 2. 11 = Divide by 4.

5.7.190 CLK_RST_CONTROLLER_PLLC2_MISC_0_0
Offset: 0x4ec │ Read/Write: R/W │ Reset: 0x40000000 (0b01000000000000000000000000000000)
PLLC2_STROBE: STROBE for various PLL input controls. Those controls are transparent
31 0x0
only when STROBE is high.
PLLC2_RESET: Reset for digital logic of the PLL. DIRECT. 0 = Out of reset, 1 = Reset
asserted.
30 0x1
0 = DISABLE
1 = ENABLE
PLLC2_SDM_DIV: SDM Clock Divide Ratio. LATCHED. 00 = Divide by 4. 01 =

29:28 0x0
Divide by 8. 10 = Divide by 16. 11 = Divide by 32.
PLLC2_FILT_DIV: Filter Clock Divide Ratio. LATCHED. 00 = Divide by 8. 01 =

27:26 0x0
Divide by 16. 10 = Divide by 32. 11 = Divide by 64.
25:18 0x0 PLLC2_ALPHA: IIR pole location. LATCHED.
17:9 0x0 PLLC2_KB: IIR filter feed-forward gain. LATCHED.
8:2 0x0 PLLC2_KA: IIR filter input gain. LATCHED.
1:0 0x0 PLLC2_KVCO: VCO gain adjustment. DIRECT.
Offset: 0x4f0 │ Read/Write: R/W │ Reset: 0x08000000 (0bxxxx1000xx000000xx00xx00xxxx0000)
PLLC2_IDDQ:
27 0x1 0 = OFF
1 = ON
PLLC2_VCO_BAND_SW: If calibration is not being done, this field can force the VCO
26:24 0x0
band (select n+1 band, 1 to 8). LATCHED.
PLLC2_DAC_CODE_SW: For calibration at Vmin, the voltage is controlled by this field.

21:16 0x0
LATCHED.
PLLC2_CAL_NUM_FRM: Number of frames during calibration for which the delta is

13:12 0x0
collected for taking an average. LATCHED. 00 = 2, 01 = 4, 10 = 8, 11 = 16.
9 0x0 PLLC2_CAL_EN: Calibration is enabled (1) or disabled (0). DIRECT.
PLLC2_PD_AFTER_FD: Hold Phase-Detector output at '0' until Frequency Detector is

8 0x0
locked. LATCHED. 1: Enable, 0: Disable
3:0 0x0 PLLC2_SDM_GAIN: SDM Gain Control. LATCHED.
Offset: 0x4f4 │ Read/Write: R/W │ Reset: 0x00000000 (0bx000xx00xx00xx00xx00xx00xx00xx00)
30 0x0 PLLC2_PTS: Base PLLC2 test output select.
PLLC2_PD_ULCK_FRM: pd_unlock_num_frames. Refer to the NVIDIA Tegra K1 Mobile

29:28 0x0
Processor Data Sheet (DS-06742-001) for details. LATCHED.
PLLC2_PD_LCK_FRM: pd_lock_num_frames. Refer to the Tegra K1 data sheet for

25:24 0x0
details. LATCHED.
PLLC2_PD_OUT_HYST: pd_pullout_hyst_val. Refer to the Tegra K1 data sheet for

21:20 0x0
details. LATCHED.

PLLC2_PD_IN_HYST: pd_pullin_hyst_val. Refer to the Tegra K1 data sheet for details.

17:16 0x0
LATCHED.
PLLC2_FD_ULCK_FRM: fd_unlock_num_frames. Refer to the Tegra K1 data sheet for

13:12 0x0
details. LATCHED
PLLC2_FD_LCK_FRM: fd_lock_num_frames. Refer to the Tegra K1 data sheet for details.

9:8 0x0
LATCHED
PLLC2_FD_OUT_HYST: fd_pullout_hyst_val. Refer to the Tegra K1 data sheet for details.

5:4 0x0
LATCHED.
PLLC2_FD_IN_HYST: fd_pullin_hyst_val. Refer to the Tegra K1 data sheet for details.

1:0 0x0
LATCHED.
Offset: 0x4f8 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxx00000000000000000000000000)
25:0 0x0 PLLC2_SETUP: Read the PLL data sheet for the description of each bit. DIRECT.
Offset: 0x4fc │ Read/Write: R/W │ Reset: 0x0X000101 (0b000xxxxxx000xxxx00000001xxxxxx01)
PLLC3_BYPASS: DIRECT. 0 = no bypass, 1 = bypass.

1 = ENABLE
PLLC3_ENABLE: DIRECT. 0 = disable, 1 = enable. Will invert and connect to IDDQ.

1 = ENABLE
PLLC3_REF_DIS: 0 = enable reference clock, 1 = disable reference clock. To enter

the minimum power mode for the PLL, this bit must be asserted.
29 RW REF_ENABLE
0 = REF_ENABLE
1 = REF_DISABLE
27 RO X PLLC3_FREQ_LOCK: 0 = not locked, 1 = frequency is locked.
26 RO X PLLC3_PHASE_LOCK: 0 = not locked, 1 = phase is locked.
22:20 RW 0x0 PLLC3_DIVP: 0 = post divider (divide by N+1). DIRECT.
15:8 RW 0x1 PLLC3_DIVN: PLL feedback divider. LATCHED.
PLLC3_DIVM: PLL input divider. DIRECT. 00 = Divide by 1, 01 = Divide by 1. 10 =

1:0 RW 0x1
Divide by 2. 11 = Divide by 4.
Offset: 0x500 │ Read/Write: R/W │ Reset: 0x40000000 (0b000000000000000000000000000) | Default: 0x00644650
Bit Reset SW Default Description
PLLC3_STROBE: STROBE for various PLL input controls.

31 0x0 NONE
Those controls are transparent only when STROBE is high.
PLLC3_RESET: Reset for digital logic of the PLL. DIRECT. 0

= Out of reset, 1 = Reset asserted.
30 0x1 NONE
0 = DISABLE
1 = ENABLE

PLLC3_SDM_DIV: SDM Clock Divide Ratio. LATCHED. 00 =

29:28 0x0 NONE Divide by 4. 01 = Divide by 8. 10 = Divide by 16. 11 = Divide
by 32.
PLLC3_FILT_DIV: Filter Clock Divide Ratio. LATCHED. 00 =

27:26 0x0 NONE Divide by 8. 01 = Divide by 16. 10 = Divide by 32. 11 = Divide
by 64.
25:18 0x0 0x19 PLLC3_ALPHA: IIR pole location. LATCHED.
17:9 0x0 0x23 PLLC3_KB: IIR filter feed-forward gain. LATCHED.
8:2 0x0 0x14 PLLC3_KA: IIR filter input gain. LATCHED.
1:0 0x0 NONE PLLC3_KVCO: VCO gain adjustment. DIRECT.
Offset: 0x504 │ Read/Write: R/W │ Reset: 0x08000000 (0bxxxx1000xx000000xx00xx00xxxx0000)
PLLC3_IDDQ:
27 0x1 0 = OFF
1 = ON
PLLC3_VCO_BAND_SW: If calibration is not being done, this field can force the VCO
26:24 0x0
band (select n+1 band, 1 to 8). LATCHED.
PLLC3_DAC_CODE_SW: For calibration at Vmin, the voltage is controlled by this field.

21:16 0x0
LATCHED.
PLLC3_CAL_NUM_FRM: Number of frames during calibration for which the delta is

13:12 0x0
collected for taking an average. LATCHED. 00 = 2, 01 = 4, 10 = 8, 11 = 16.
9 0x0 PLLC3_CAL_EN: Calibration is enabled (1) or disabled (0). DIRECT.
PLLC3_PD_AFTER_FD: Hold Phase-Detector output at '0' until Frequency Detector is

8 0x0
locked. 1: Enable, 0: Disable. LATCHED.
3:0 0x0 PLLC3_SDM_GAIN: SDM Gain Control. LATCHED.
Offset: 0x508 │ Read/Write: R/W │ Reset: 0x00000000 (0bx000xx00xx00xx00xx00xx00xx00xx00)
30 0x0 PLLC3_PTS: Base PLLC3 test output select.
PLLC3_PD_ULCK_FRM: pd_unlock_num_frames. Refer to the NVIDIA Tegra K1 Mobile

29:28 0x0
Processor Data Sheet (DS-06742-001) for details. LATCHED.
PLLC3_PD_LCK_FRM: pd_lock_num_frames. Refer to the Tegra K1 data sheet for

25:24 0x0
details. LATCHED.
PLLC3_PD_OUT_HYST: pd_pullout_hyst_val. Refer to the Tegra K1 data sheet for

21:20 0x0
details. LATCHED.
PLLC3_PD_IN_HYST: pd_pullin_hyst_val. Refer to the Tegra K1 data sheet for details.

17:16 0x0
LATCHED.
PLLC3_FD_ULCK_FRM: fd_unlock_num_frames. Refer to the Tegra K1 data sheet for

13:12 0x0
details. LATCHED.
PLLC3_FD_LCK_FRM: fd_lock_num_frames. Refer to the Tegra K1 data sheet for

9:8 0x0
details. LATCHED.
5:4 0x0 PLLC3_FD_OUT_HYST: fd_pullout_hyst_val. Refer to the Tegra K1 data sheet for


details. LATCHED.
PLLC3_FD_IN_HYST: fd_pullin_hyst_val. Refer to the Tegra K1 data sheet for details.

1:0 0x0
LATCHED.
Offset: 0x50c │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxx00000000000000000000000000)
25:0 0x0 PLLC3_SETUP: Refer to the PLL datasheet for the descriptions of each bit. DIRECT.
5.7.199 CLK_RST_CONTROLLER_PLLX_MISC_1_0
Offset: 0x510 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxx000000000000000000000000)
23:0 0x0 PLLX_SETUP: Base PLLX test output select.
Offset: 0x514 │ Read/Write: R/W │ Reset: 0x0000000X (0b000000000000000000000000xx00xx00)
31:24 RW 0x0 PLLX_DYNRAMP_STEPB: MISC_2 PLLX DYNRAMP
23:16 RW 0x0 PLLX_DYNRAMP_STEPA: MISC_2 PLLX DYNRAMP
15:8 RW 0x0 PLLX_NDIV_NEW: MISC_2 PLLX DYNRAMP
5 RW 0x0 PLLX_EN_FSTLCK: MISC_2 PLLX DYNRAMP
4 RW 0x0 PLLX_LOCK_OVERRIDE: MISC_2 PLLX DYNRAMP
3 RO X PLLX_PLL_FREQLOCK: MISC_2 PLLX DYNRAMP
2 RO X PLLX_DYNRAMP_DONE: MISC_2 PLLX DYNRAMP
1 RW 0x0 PLLX_CLAMP_NDIV: MISC_2 PLLX DYNRAMP
0 RW 0x0 PLLX_EN_DYNRAMP: MISC_2 PLLX DYNRAMP
Offset: 0x518 │ Read/Write: R/W │ Reset: 0x00000008 (0bxxxxxxxx00000000xxxx0000xxxx1000)
PLLX_PRB_OBS_SEL:
0 = CSITE
1 = FCPU0_LEAF
2 = FCPU1_LEAF
23:16 0x0 3 = FCPU2_LEAF
4 = FCPU3_LEAF
5 = MC
6 = MSELECT
7 = FTOP_SHAPER
11:10 0x0 PLLX_PRB_DRV_CTRL
9:8 0x0 PLLX_SEL_PRB
3 0x1 PLLX_IDDQ:0:


The PLLX is powered up.
1:Software can put the PLLX in IDDQ by setting this bit.
2:1 0x0 PLLX_KCP: Charge Pump Gain control
0 0x0 PLLX_KVCO:VCO gain
5.7.202 CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0
XUSB I/O PLL Power Sequencer Input Software Control Program Guide
The software control input can be used for test coverage or driving power sequencer SM via software.
The XUSB power sequencer is driven by a primary reset input signal: reset. Reset is expected to be held static until the power-
up or power-down sequence is complete.
Offset: 0x51c │ Read/Write: R/W │ Reset: 0x0X00000d (0bxxxxxx10xxxxxxxxxxxxxxxxx0001101)
XUSBIO_SEQ_STATE: XUSBIO power sequencer state

0 = SEQ_OFF
27:26 RO X
1 = SEQ_ON
2 = SEQ_BUSY
XUSBIO_SEQ_START_STATE: XUSBIO power sequencer start state

1 = SEQ_ON
XUSBIO_SEQ_ENABLE: XUSBIO power sequencer enable. Start state is loaded on first

cycle after set.
24 RW DISABLE
0 = DISABLE
1 = ENABLE
XUSBIO_PADPLL_USE_LOCKDET: 0=Use programmable delay, 1=use lockdet signals

6 RW 0x0
from PLL
XUSBIO_SEQ_RESET_INPUT_VALUE: 0=XUSBIO PLL ON, 1=XUSB IOPLL OFF.

5 RW 0x0 Software controls the state machine by setting this and the XUSBIO_SEQ_IN_SWCTL
bit
4 RW 0x0 XUSBIO_SEQ_IN_SWCTL: 0=seq input by hardware, 1=seq input by software.
XUSBIO_CLK_ENABLE_OVERRIDE_VALUE: Override value used only when

XUSBIO_CLK_ENABLE_SWCTL is set
3 RW ENABLE
0 = DISABLE
1 = ENABLE
XUSBIO_CLK_ENABLE_SWCTL: 0=ioclks enabled by hardware, 1=ioclks enabled by

2 RW 0x1
software
XUSBIO_PADPLL_RESET_OVERRIDE_VALUE: 0=XUSBIO PLL on, 1=PLL reset.

1 RW 0x0
Override value used only when XUSBIO_PADPLL_RESET_SWCTL is set
0 RW 0x1 XUSBIO_PADPLL_RESET_SWCTL: 0=Reset by hardware, 1=Reset by software
5.7.203 CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0
The range value is the recommended range. All counters support 0-255 µs range in 1 µs steps.
Offset: 0x520 │ Read/Write: R/W │ Reset: 0x000a0a0f (0bxxxxxxxx000010100000101000001111)
XUSBIO_PADPLL_RESET2_PADPLL_IDDQ_DLY: PT1: Delay from XUSBIO PAD PLL

23:16 0xa
RESET assertion to the PAD PLL IDDQ assertion. Range is 0 - 10 µs.

XUSBIO_PADPLL_IDDQ2_PADPLL_RESET_DLY: PT2: Delay from XUSBIO PAD PLL

15:8 0xa
IDDQ de-assertion to the PAD PLL reset de-assertion. Range is 0 - 10 µs.
XUSBIO_PADPLL_PU_POST_DLY: PT3: Delay from XUSBIO PAD PLL Reset de-

7:0 0xf
assertion to the PLL LOCK. Range is 0 -15 µs.
5.7.204 CLK_RST_CONTROLLER_PLLE_AUX1_0
The range value is the recommended range. All counters support 0-255 step range.
Offset: 0x524 │ Read/Write: R/W │ Reset: 0x00000105 (0bxxxxxxxxxxxxxxxx0000000100000101)
PLLE_INTRESET_DLY: Delay between PLLE SSC_BYP -> PLLE INTERP_RESET

15:8 0x1 [delay 300 ns-500 ns minimum]. 300 ns to 500 ns delay is required for the interpolator
biasing to stabilize. The state machine can give a minimum 1 µs of delay.
PLLE_ENABLE_DLY: Delay from PLLE IDDQ de-assertion to PLLE ENABLE assertion.

7:0 0x5 [~5 µs] IDDQ enables Vregulator. ENABLE starts PLL. It takes 5 µs for the voltage
regulator to come up. The voltage regulator needs to be up before the PLL is started.
5.7.205 CLK_RST_CONTROLLER_PLLP_RESHIFT_0
Offset: 0x528 │ Read/Write: R/W │ Reset: 0x0000003b (0bxxxxxxxxxxxxxxxxxxxxxx0000111011)
PLLP_OUT0_RATIO: PLLP_OUT0 divider from base PLLP (lsb denotes 0.5x). The
9:2 0xe
default is 408/8=51 MHz.

1 = ENABLE

0 RESET_DISABLE 0 = RESET_ENABLE
1 = RESET_DISABLE
5.7.206 CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0
Offset: 0x52c │ Read/Write: R/W │ Reset: 0xXX00000f (0bxxxxxx10xxxxxxxxxxxxxxxx00001111)
31 RO X UTMIPLL_LOCK: 0 = not lock, 1 = lock. (Phase and Frequency)
UTMIPLL_SEQ_STATE: UTMIPLL power sequencer state

0 = SEQ_OFF
27:26 RO X
1 = SEQ_ON
2 = SEQ_BUSY
UTMIPLL_SEQ_START_STATE: UTMIPLL power sequencer start state

1 = SEQ_ON
UTMIPLL_SEQ_ENABLE: UTMIPLL power sequencer enable. Start state is loaded

on first cycle after set.
24 RW DISABLE
0 = DISABLE
1 = ENABLE
UTMIPLL_IDDQ_PD_INCLUDE: While powering down through the HW state

7 RW 0x0
machine, puts the PLL in IDDQ as well to save more power.
UTMIPLL_USE_LOCKDET: 0=Use programmable delay, 1=use lockdet signals from

6 RW 0x0
PLL and programmable delay on top of that.

UTMIPLL_SEQ_RESET_INPUT_VALUE: 0=UTMIPLL ON, 1=UTMIPLL OFF.

5 RW 0x0 Software controls the state machine by setting this and UTMIPLL_SEQ_IN_SWCTL
bit
4 RW 0x0 UTMIPLL_SEQ_IN_SWCTL: 0=seq input by hardware, 1=seq input by software
UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE: Override value used only when

UTMIPLL_CLK_ENABLE_SWCTL is set
3 RW ENABLE
0 = DISABLE
1 = ENABLE
UTMIPLL_CLK_ENABLE_SWCTL: 0=UTMIP clocks enable by hardware, 1=UTMIP

2 RW 0x1
clocks enable by software
UTMIPLL_IDDQ_OVERRIDE_VALUE: 0=PLL not in IDDQ mode, 1=PLL in IDDQ

1 RW 0x1
mode. Override value used only when UTMIPLL_IDDQ_SWCTL is set
0 RW 0x1 UTMIPLL_IDDQ_SWCTL: 0=IDDQ by hardware, 1=IDDQ by software.
5.7.207 CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_0
Offset: 0x530 │ Read/Write: R/W │ Reset: 0x0X00008d (0bxxxxxx10xxxxxxxxxxxxxxxx100011x1)
PLLU_SEQ_STATE: PLLU power sequencer state

0 = SEQ_OFF
27:26 RO X
1 = SEQ_ON
2 = SEQ_BUSY
PLLU_SEQ_START_STATE: PLLU power sequencer start state

1 = SEQ_ON
PLLU_SEQ_ENABLE: PLLU power sequencer enable. Start state is loaded on the

first cycle after set.
24 RW DISABLE
0 = DISABLE
1 = ENABLE
PLLU_USE_SWITCH_DETECT: 0=Use programmable delay, 1=Use hardware

7 RW 0x1
switch detect logic.
PLLU_USE_LOCKDET: 0=Use programmable delay, 1=Use lockdet signals from PLL

6 RW 0x0
and programmable delay on top of that.
PLLU_SEQ_RESET_INPUT_VALUE: 0=PLLU ON, 1=PLLU OFF. Software controls

5 RW 0x0
the state machine by setting this and the PLLU_SEQ_IN_SWCTL bit
4 RW 0x0 PLLU_SEQ_IN_SWCTL: 0=Seq input by hardware, 1=Seq input by software
PLLU_CLK_ENABLE_OVERRIDE_VALUE: Override value used only when

PLLU_CLK_ENABLE_SWCTL is set
3 RW ENABLE
0 = DISABLE
1 = ENABLE
PLLU_CLK_ENABLE_SWCTL: 0=PLLU clocks enabled by hardware, 1=PLLU clocks

2 RW 0x1
enabled by software
PLLU_CLK_SWITCH_SWCTL: 0=Control SS/FS clock frequency through hardware,

0 RW 0x1
1=Control FS/SS clock frequency through software

5.7.208 CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0
Note that default value is the recommended range.
PLLU_CLK_SWITCH_DLY: Delay from SS Clock source change to the actual frequency

31:24 0x80
change to 32 kHz clock. Range is ~100 µs.
PLLU_LOCK_DLY: Delay from PLLU ENABLE assertion to the PLL LOCK. Range is
23:14 0x64
100 µs-1 ms.
UTMIPLL_IDDQ2_ENABLE_DLY: Delay from UTMIPLL IDDQ de-assertion to the

13:10 0x5
UTMIPLL ENABLE assertion. Range ~5 µs.
UTMIPLL_LOCK_DLY: Delay from UTMIPLL ENABLE assertion to the PLL LOCK.

9:0 0x80
Range 5-15 µs.
5.7.209 CLK_RST_CONTROLLER_CLK_CPU_MISC_0
Offset: 0x53c │ Read/Write: R/W │ Reset: 0x00000002 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx010)
CPU_ATCLK_RATIO: Clock divider ratio for the ATB clocks in CCPLEX

000 = div-by-2.
001 = div-by-3.
2:0 0x2 010 = div-by-4.
011 = div-by-5.
100 = div-by-6.
Other values = Reserved
5.7.210 CLK_RST_CONTROLLER_CLK_CPUG_MISC_0
Offset: 0x540 │ Read/Write: R/W │ Reset: 0x00000002 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx010)
CPUG_ATCLK_RATIO: Clock divider ratio for the ATB clocks in CCPLEX

000 = div-by-2.
001 = div-by-3.
2:0 0x2 010 = div-by-4.
011 = div-by-5.
100 = div-by-6.
5.7.211 CLK_RST_CONTROLLER_CLK_CPULP_MISC_0
CPULP_ATCLK_RATIO: Clock divider ratio for the ATB clocks in CCPLEX

000 = div-by-2.
2:0 0x2
001 = div-by-3.
010 = div-by-4.


011 = div-by-5.
100 = div-by-6.
5.7.212 CLK_RST_CONTROLLER_PLLX_HW_CTRL_CFG_0
Offset: 0x548 │ Read/Write: R/W │ Reset: 0x00000001 (0bxxxxxxxxxxxxxxxxxxxxxxxxx0000001)
FORCE_FSM_CLEAR:
1 = ENABLE
SLOWDOWN_CYA:
0 = REF_DIVM
5:4 REF_DIVM 1 = REF_DIVM_DIV4
2 = SCLK_DIV1
3 = SCLK_DIV16
RAMP_MODE:
3 SLOW 0 = SLOW
1 = FAST
SEQ_TRIGGER:
1 = ENABLE
SW_OVERRIDE:
1 = ENABLE
SWCTL:
1 = ENABLE
5.7.213 CLK_RST_CONTROLLER_PLLX_SW_RAMP_CFG_0
Offset: 0x54c │ Read/Write: R/W │ Reset: 0x00000000 (0b00000000000000000000000000000000)
31:24 0x0 DYNRAMP_STEPA: PLL ramp rate
23:16 0x0 DYNRAMP_STEPB: PLL ramp rate
15:8 0x0 NDIV_NEW: PLL ramp rate
7:0 0x0 NDIV: PLL ramp rate
5.7.214 CLK_RST_CONTROLLER_PLLX_HW_CTRL_STATUS_0
Offset: 0x550 │ Read/Write: RO │ Reset: 0xXX000XXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
FSM_STATE:
0 = DISABLE
1 = SEQ_AWAIT
2 = SEQ_FAST_BEGIN
31:28 X 3 = SEQ_FAST_BUSY0
4 = SEQ_FAST_BUSY1
5 = SEQ_FAST_BUSY2
6 = SEQ_FAST_BUSY3
7 = SEQ_SLOW_BEGIN
8 = SEQ_SLOW_BUSY0


9 = SEQ_SLOW_BUSY1
10 = SEQ_SLOW_BUSY2
11 = SEQ_SLOW_BUSY3
12 = SEQ_DONE
13 = ILLEGAL
CFG_REG_SELECT:
0 = NONE
27:26 X
1 = HW
2 = SW
HW_RAMP_DONE:
10 X 0 = FALSE
1 = TRUE
SW_RAMP_DONE:
9 X 0 = FALSE
1 = TRUE
LONG_LATENCY_THROTTLE:
8 X 0 = DISABLE
1 = ENABLE
HW_RESTORE_EN:
7 X 0 = DISABLE
1 = ENABLE
HW_THROTTLE_EN:
6 X 0 = DISABLE
1 = ENABLE
SW_RAMP_STATUS:
5 X 0 = DONE
1 = INPROGRESS
HW_RAMP_STATUS:
4 X 0 = DONE
1 = INPROGRESS
SEQ_STATUS:
0 = SEQ_DIABLE
3:2 X 1 = SEQ_ENABLE
2 = SEQ_BUSY_FAST_MODE
3 = SEQ_BUSY_SLOW_MODE
SW_OVERRIDE_STATUS:
1 X 0 = DISABLE
1 = ENABLE
SWCTL_STATUS:
0 X 0 = DISABLE
1 = ENABLE
5.7.215 CLK_RST_CONTROLLER_SPARE_REG0_0
31:6 0x0 VAL
DIVIDER_FSM_CYA: Disable ability to change rate and ratio while module clock is off.
5 0x0
Module should be off when changing this value.
4 0x0 VAL1
3:2 0x0 CLK_M_DIVISOR: N = Divide by (n+1).
1 0x0 TMR_CLKEN_STICKY
0 0x0 EMC_LATENCY_OVERRIDE

5.7.216 CLK_RST_CONTROLLER_PLLD2_SS_CFG_0
Offset: 0x570 | Read/Write: R/W | Reset: 0x1XX00000 (0b00010xxxx0xxxxxxxxxxxxxxxxxxxxxx)
PLLD2_EN_SDM:Fractional N divider enable

1 = ENABLE
PLLD2_EN_SSC: Spread spectrum enable 0 = disable, 1 = enable.

1 = ENABLE
29 RW 0x0 PLLD2_EN_DITHER2
28 RW 0x1 PLLD2_EN_DITHER
27 RW 0x0 PLLD2_SDM_RESET
25:23 RO X PLLD2_SDM_TEST_OUT
22 RW 0x0 PLLD2_CLAMP
5.7.217 CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0
31:16 0x0 PLLD2_SDM_SSC_MAX
15:0 0x0 PLLD2_SDM_SSC_MIN
5.7.218 CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0
31:16 0x0 PLLD2_SDM_SSC_STEP
15:0 0x0 PLLD2_SDM_DIN
5.7.219 CLK_RST_CONTROLLER_PLLDP_BASE_0
PLLDP Registers
Table 22: PLDIV - Divider Control for CLKOUT
PLDIV[3:0] CLKOUT
0000 vcoclock/1 (pdivider is powered down)
0001 vcoclock/2
0010 vcoclock/3
0011 vcoclock/4

PLDIV[3:0] CLKOUT
0100 vcoclock/5
0101 vcoclock/6
0110 vcoclock/8
0111 vcoclock/10
1000 vcoclock/12
1001 vcoclock/16
1010 vcoclock/12
1011 vcoclock/16
1100 vcoclock/20
1101 vcoclock/24
1110 vcoclock/32
1111 Reserved
vcoclock Frequency:
 Normal mode: EN_SDM=DISABLE, SDM_RESET=0

Fvco = Fref / MDIV * NDIV
 Fractional NDIV mode: EN_SDM=ENABLE, EN_SSC=DISABLE, SDM_RESET=0
Fvco = Fref / MDIV * (NDIV + 0.5 + SDM_DIN / 8192)
 Spread Spectrum mode: EN_SDM=ENABLE, EN_SSC=ENABLE, SDM_RESET=0
Fvco_max = Fref / MDIV * (NDIV + 0.5 + SDM_SSC_MAX / 8192), SDM_SSC_MAX < 0x300
Fvco_min = Fref / MDIV * (NDIV + 0.5 + SDM_SSC_MIN / 8192), SDM_SSC_MIN > -0x300 (0xD000)
Fvco_step = 2 * (Fmod * MDIV / Fref) * (SDM_SSC_MAX-SDM_SSC_MIN), Fmod-modulation frequency,e.g., 33KHz
= SDM_SSC_STEP[11:0] / (SDM_SSC_STEP[15:12] + 1)
Offset: 0x590 | Read/Write: R/W | Reset: 0xXX080000 (0b000xx00000001xx00000000000000000)
PLLDP_BYPASS: 0 = no bypass, 1 = bypass.

1 = ENABLE
PLLDP_ENABLE: 0 = disable, 1 = enable.

1 = ENABLE
PLLDP_REF_DIS: 0 = enable reference clk, 1 = disable reference

REF_ clk.
29 RW
ENABLE 0 = REF_ENABLE
1 = REF_DISABLE
28 RO X PLLDP_FREQLOCK: 0 = not lock, 1 = lock freq

27 RO X PLLDP_LOCK: 0 = not lock, 1 = lock freq + phase
PLLDP_REF_SRC_SEL:Reference source select sel[0]=1 =>

26:25 RW 0x0 ref_src = PLLREFE_CLKOUTsel[0]=0 && sel[1]=1 => ref_src =
pllP_out0sel[0]=0 && sel[1]=0 => ref_src = osc_div_clk
24 RW 0x0 PLLDP_LOCK_OVERRIDE:Forces PLL_LOCK to 1
23:20 RW 0x0 PLLDP_PLDIV: PL divider
PLLDP_IDDQ: 0 = The PLL is powered up, 1 = Software can put

the PLL in IDDQ by setting this bit
19 RW 0x1
0 = OFF
1 = ON
16 RW 0x0 PLLDP_PTS: Base PLLDP test output select.
15:8 RW 0x0 PLLDP_NDIV:N divider
7:0 RW 0x0 PLLDP_MDIV:M divider
5.7.220 CLK_RST_CONTROLLER_PLLDP_MISC_0
Offset: 0x594 | Read/Write: R/W | Reset: 0xXX000000 (0b00xxx000000000000000000000000000)
PLLDP_EN_FSTLCK:Enables Fast lock

1 = ENABLE
PLLDP_LOCK_ENABLE: 0 = disable, 1 = enable.

1 = ENABLE
29:27 RO X PLLDP_MON_TEST_OUT
26:25 RW 0x0 PLLDP_KCP: Charge pump gain control
24 RW 0x0 PLLDP_KVCO:VCO gain
23:0 RW 0x0 PLLDP_SETUP:setup[23:0]

5.7.221 CLK_RST_CONTROLLER_PLLDP_SS_CFG_0
Offset: 0x598 | Read/Write: R/W | Reset: 0x1XX00000 (0b00010xxxx0xxxxxxxxxxxxxxxxxxxxxx)
PLLDP_EN_SDM: Fractional N divider enable

1 = ENABLE
PLLDP_EN_SSC: Spread spectrum enable 0 = disable, 1 = enable.

1 = ENABLE
29 RW 0x0 PLLDP_EN_DITHER2
28 RW 0x1 PLLDP_EN_DITHER
27 RW 0x0 PLLDP_SDM_RESET
25:23 RO X PLLDP_SDM_TEST_OUT
22 RW 0x0 PLLDP_CLAMP
5.7.222 CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0
31:16 0x0 PLLDP_SDM_SSC_MAX
15:0 0x0 PLLDP_SDM_SSC_MIN
5.7.223 CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0
Offset: 0x5a0 | Read/Write: R/W | Reset: 0x00000000 (0b00000000000000000000000000000000)
31:16 0x0 PLLDP_SDM_SSC_STEP
15:0 0x0 PLLDP_SDM_DIN
Offset: 0x5a4 | Read/Write: R/W | Reset: 0xXX080101 (0b000xx00000001xx00000000100000001)

PLLC4_BYPASS: 0 = no bypass, 1 = bypass.

1 = ENABLE
PLLC4_ENABLE: 0 = disable, 1 = enable.

1 = ENABLE
PLLC4_REF_DIS: 0 = enable reference clk, 1 = disable

reference clk.
29 RW REF_ENABLE
0 = REF_ENABLE
1 = REF_DISABLE
28 RO X PLLC4_FREQLOCK: 0 = not lock, 1 = lock feq
27 RO X PLLC4_LOCK: 0 = not lock, 1 = lock feq + phase
PLLC4_REF_SRC_SEL:Reference source select sel[0]=1 =>

26:25 RW 0x0 ref_src = PLLREFE_CLKOUTsel[0]=0 && sel[1]=1 => ref_src =
pllP_out0sel[0]=0 && sel[1]=0 => ref_src = osc_div_clk
24 RW 0x0 PLLC4_LOCK_OVERRIDE:Forces PLL_LOCK to 1
23:20 RW 0x0 PLLC4_PLDIV:PL divider
PLLC4_IDDQ: 0 The PLL is powered up, 1 Software can put

the PLL in IDDQ by setting this bit
19 RW 0x1
0 = OFF
1 = ON
16 RW 0x0 PLLC4_PTS: Base PLLC4 test output select.
15:8 RW 0x1 PLLC4_NDIV:N divider
7:0 RW 0x1 PLLC4_MDIV:M divider
5.7.225 CLK_RST_CONTROLLER_PLLC4_MISC_0
Offset: 0x5a8 | Read/Write: R/W | Reset: 0xXX000000 (0b00xxx000000000000000000000000000)
31 RW DISABLE PLLC4_EN_FSTLCK:Enables Fast lock

0 = DISABLE

1 = ENABLE
PLLC4_LOCK_ENABLE: 0 = disable, 1 = enable.

1 = ENABLE
29:27 RO X PLLC4_MON_TEST_OUT
26:25 RW 0x0 PLLC4_KCP:Charge pump gain control
24 RW 0x0 PLLC4_KVCO:VCO gain
23:0 RW 0x0 PLLC4_SETUP:setup[23:0]
5.7.226 CLK_RST_CONTROLLER_PLLC4_SS_CFG_0
Offset: 0x5ac | Read/Write: R/W | Reset: 0x1XX00000 (0b00010xxxx0xxxxxxxxxxxxxxxxxxxxxx)
PLLC4_EN_SDM:
1 = ENABLE
PLLC4_EN_SSC: 0 = disable, 1 = enable.

1 = ENABLE
29 RW 0x0 PLLC4_EN_DITHER2
28 RW 0x1 PLLC4_EN_DITHER
27 RW 0x0 PLLC4_SDM_RESET
25:23 RO X PLLC4_SDM_TEST_OUT
22 RW 0x0 PLLC4_CLAMP
5.7.227 CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0
Offset: 0x5b0 | Read/Write: R/W | Reset: 0x00000000 (0b00000000000000000000000000000000)
31:16 0x0 PLLC4_SDM_SSC_MAX

15:0 0x0 PLLC4_SDM_SSC_MIN
5.7.228 CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0
Offset: 0x5b4 | Read/Write: R/W | Reset: 0x00000000 (0b00000000000000000000000000000000)
31:16 0x0 PLLC4_SDM_SSC_STEP
15:0 0x0 PLLC4_SDM_DIN
Offset: 0x5c4 | Read/Write: R/W | Reset: 0x00000000 (0b00000000000000000000000000000000)
31:0 0x0 RESERVED
Offset: 0x5c8 | Read/Write: R/W | Reset: 0x00000000 (0b00000000000000000000000000000000)
31:0 0x0 RESERVED
5.7.231 CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0
Offset: 0x5cc | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
CAR_ISOB_EN: Enable/Disable the idle slowdown on boot (ISoB) to

the GPU
0 DISABLE
0 = DISABLE
1 = ENABLE

5.7.232 CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0
Offset: 0x600 │ Read/Write: R/W │ Reset: 0x00000000 (0b000xxxxxxxxxxxxxxxxxxxxx00000000)
XUSB_CORE_HOST_CLK_SRC: 000 = clk_m, 001 = pllP_out0, 010 = pllC2_out0, 011 =

pllC_out0, 100 = pllC3_out0, 101 = pllRefe_OUT
0 = CLK_M
1 = PLLP_OUT0
31:29 CLK_M
2 = PLLC2_OUT0
3 = PLLC_OUT0
4 = PLLC3_OUT0
5 = PLLREFE_CLKOUT
7:0 0x0 XUSB_CORE_HOST_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.233 CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0
XUSB_FALCON_CLK_SRC: 000 = clk_m, 001 = pllP_out0, 010 = pllC2_out0, 011 =

0 = CLK_M
1 = PLLP_OUT0
31:29 CLK_M
2 = PLLC2_OUT0
3 = PLLC_OUT0
4 = PLLC3_OUT0
5 = PLLREFE_CLKOUT
7:0 0x0 XUSB_FALCON_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.234 CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0
XUSB_FS_CLK_SRC: 000 = clk_m, 010 = FO_48M, 100 = pllP_out0, 110 = HSIC_480

0 = CLK_M
31:29 CLK_M 2 = FO_48M
4 = PLLP_OUT0
6 = HSIC_480
7:0 0x0 XUSB_FS_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.235 CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0
Offset: 0x60c │ Read/Write: R/W │ Reset: 0x00000000 (0b000xxxxxxxxxxxxxxxxxxxxx00000000)
XUSB_CORE_DEV_CLK_SRC: 000 = clk_m, 001 = pllP_out0, 010 = pllC2_out0, 011 =

0 = CLK_M
1 = PLLP_OUT0
31:29 CLK_M
2 = PLLC2_OUT0
3 = PLLC_OUT0
4 = PLLC3_OUT0
5 = PLLREFE_CLKOUT
7:0 0x0 XUSB_CORE_DEV_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)

5.7.236 CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0
XUSB_SS_CLK_SRC: 000 = clk_m, 001 = pllRefe_OUT, 010 = clk_s, 011 = HSIC_480,

100 = pllC_out0, 101 = pllC2_out0, 110 = pllC3_out0, 111 = osc_div
0 = CLK_M
1 = PLLREFE_CLKOUT
2 = CLK_S
31:29 CLK_M
3 = HSIC_480
4 = PLLC_OUT0
5 = PLLC2_OUT0
6 = PLLC3_OUT0
7 = OSC_DIV
XUSB_HS_CLK_BYPASS_SWITCH: 0 = HS clock is switch/dividers output 1 = HS Clock

25 0x0
is derived from PLLU 60M output directly.
XUSB_SS_CLK_BYPASS_SWITCH: 0 = SS clock is switch/dividers output 1 = SS Clock

24 0x0
is derived from osc_div clock directly.
7:0 0x0 XUSB_SS_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.237 CLK_RST_CONTROLLER_CLK_SOURCE_CILAB_0
CILAB_CLK_SRC: 000 = pllP_out0, 010 = pllC_out0, 110 = clk_m

0 = PLLP_OUT0
31:29 CLK_M
2 = PLLC_OUT0
6 = CLK_M
7:0 0x0 CILAB_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.238 CLK_RST_CONTROLLER_CLK_SOURCE_CILCD_0
CILCD_CLK_SRC: 000 = pllP_out0, 010 = pllC_out0, 110 = clk_m

0 = PLLP_OUT0
31:29 CLK_M
2 = PLLC_OUT0
6 = CLK_M
7:0 0x0 CILCD_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.239 CLK_RST_CONTROLLER_CLK_SOURCE_CILE_0
CILE_CLK_SRC: 000 = pllP_out0, 010 = pllC_out0, 110 = clk_m

0 = PLLP_OUT0
31:29 CLK_M
2 = PLLC_OUT0
6 = CLK_M
7:0 0x0 CILE_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)

5.7.240 CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0
DSIA_LP_CLK_SRC: 000 = pllP_out0, 010 = pllC_out0, 110 = clk_m

0 = PLLP_OUT0
31:29 CLK_M
2 = PLLC_OUT0
6 = CLK_M
7:0 0x0 DSIA_LP_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.241 CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0
Offset: 0x624 │ Read/Write: R/W │ Reset: 0xc0000000 (0b11xxxxxxxxxxxxxxxxxxxxxx00000000)
DSIB_LP_CLK_SRC: 000 = pllP_out0, 010 = pllC_out0, 110 = clk_m

0 = PLLP_OUT0
31:29 CLK_M
2 = PLLC_OUT0
6 = CLK_M
7:0 0x0 DSIB_LP_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.242 CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0
Offset: 0x628 │ Read/Write: R/W │ Reset: 0x20000000 (0b001xxxxxxxxxxxxxxxxxxxx000000000)
ENTROPY_CLK_SRC: 000 = pllP_out0, 001 = clk_m, 010 = clk_s, 011 = pllE_out0

0 = PLLP_OUT0
31:29 CLK_M 1 = CLK_M
2 = CLK_S
3 = PLLE_OUT0
ENTROPY_CLK_LOCK: 1 = Lock entire CLK_SOURCE_ENTROPY register, can only be

8 0x0
unlocked by reset.
7:0 0x0 ENTROPY_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.243 CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0
Offset: 0x62c │ Read/Write: R/W │ Reset: 0xd0000000 (0b1101xxxxxxxxxxxxxxxxxxxx00000000)
DVFS_REF_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
28 0x1 DVFS_REF_MASTER_CLKEN: Reserved.
7:0 0x0 DVFS_REF_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)

5.7.244 CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_SOC_0
DVFS_SOC_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
28 0x1 DVFS_SOC_MASTER_CLKEN: Reserved.
7:0 0x0 DVFS_SOC_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.245 CLK_RST_CONTROLLER_CLK_SOURCE_TRACECLKIN_0
TRACECLKIN_CLK_SRC: 000 = pllP_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
7:0 0x0 TRACECLKIN_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.246 CLK_RST_CONTROLLER_CLK_SOURCE_ADX0_0
ADX0_CLK_SRC: 000 = pllA_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 = pllC3_out0,

100 = pllP_out0, 110 = clk_m
0 = PLLA_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLP_OUT0
6 = CLK_M
28 0x1 ADX0_MASTER_CLKEN: Reserved.
7:0 0x0 ADX0_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)

5.7.247 CLK_RST_CONTROLLER_CLK_SOURCE_AMX0_0
Offset: 0x63c │ Read/Write: R/W │ Reset: 0xd0000000 (0b1101xxxxxxxxxxxxxxxxxxxx00000000)
AMX0_CLK_SRC: 000 = pllA_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 = pllC3_out0,

100 = pllP_out0, 110 = clk_m
0 = PLLA_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLP_OUT0
6 = CLK_M
28 0x1 AMX0_MASTER_CLKEN: Reserved.
7:0 0x0 AMX0_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.248 CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0
EMC_LATENCY_CLK_SRC: 000 = pllM_out0, 001 = pllC_out0, 010 = pllP_out0, 011 =

clk_m, 100 = pllM_out_for_emc, same as PLLM, 101 = pllC2_out, 110 = pllC3_out, 111 =
empty
0 = PLLM_OUT0
1 = PLLC_OUT0
31:29 CLK_M
2 = PLLP_OUT0
3 = CLK_M
4 = PLLM_UD
5 = PLLC2_OUT0
6 = PLLC3_OUT0
7:0 0x0 EMC_LATENCY_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.249 CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0
SOC_THERM_CLK_SRC: 000 = pllM_out0, 001 = pllC_out0, 010 = pllP_out0, 011 =

pllA_out0, 100 = pllC2_out0, 101 = pllC3_out0
0 = PLLM_OUT0
1 = PLLC_OUT0
31:29 PLLP_OUT0
2 = PLLP_OUT0
3 = PLLA_OUT0
4 = PLLC2_OUT0
5 = PLLC3_OUT0
7:0 0x0 SOC_THERM_CLK_DIVISOR: N = Divide by (n+1). (lsb denotes 0.5x)
5.7.250 CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR2_0
Offset: 0x658 | Read/Write: R/W | Reset: 0x00000000 (0b000xxxxxxxxxxxxxxxxxxxxx00000000)
VI_SENSOR2_CLK_SRC: 000 = pllM_out0, 001 = pllC2_out0, 010 =

31:29 PLLM_OUT0 pllC_out0, 011 = pllC3_out0, 110 = pllA_out0
0 = PLLM_OUT0

1 = PLLC2_OUT0
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLP_OUT0
6 = PLLA_OUT0
7:0 0x0 VI_SENSOR2_CLK_DIVISOR: N = Divide by (n+1) (lsb denote 0.5x)
Offset: 0x65c | Read/Write: R/W | Reset: 0xc0000000 (0b110xxxxxxxxxxxxx0000000000000000)

0 = PLLP_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLM_OUT0
6 = CLK_M
15:0 0x0 I2C6_CLK_DIVISOR: N = Divide by (n+1) (lsb denote 1.0x)
5.7.252 CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0
Offset: 0x664 | Read/Write: R/W | Reset: 0x60000000 (0b011xxxxxxxxxxxx0xxxxxxxx00000000)
EMC_DLL_CLK_SRC: 000 = pllM_out0, 001 = pllC_out0, 010 = pllP_out0, 011

= clk_m, 100 = pllM_out_for_emc, same as pllM_out0, 101 = pllC2_out, 110 =
pllC3_out, 111 = empty
0 = PLLM_OUT0
1 = PLLC_OUT0
31:29 CLK_M
2 = PLLP_OUT0
3 = CLK_M
4 = PLLM_UD
5 = PLLC2_OUT0
6 = PLLC3_OUT0
EMC_DLL_DYN_MUX_CTRL: 0 = CDB is the source for DLL clock. 1 = The

16 0x0
output of this switch is the source for DLL clock.
7:0 0x0 EMC_DLL_CLK_DIVISOR: N = Divide by (n+1) (lsb denote 0.5x)

5.7.253 CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_AUDIO_0
Offset: 0x668 | Read/Write: R/W | Reset: 0x00000000 (0b000xxxxxxxxxxxxxxxxxxxxx00000000)
HDMI_AUDIO_CLK_SRC: 000 = pllP_out0, 001 = pllC_out0, 010 =

pllC2_out0, 011 = CLK_M
0 = PLLP_OUT0
31:29 PLLP_OUT0
1 = PLLC_OUT0
2 = PLLC2_OUT0
3 = CLK_M
7:0 0x0 HDMI_AUDIO_CLK_DIVISOR: N = Divide by (n+1) (lsb denote 0.5x)
5.7.254 CLK_RST_CONTROLLER_CLK_SOURCE_CLK72MHZ_0
Offset: 0x66c | Read/Write: R/W | Reset: 0x00000000 (0b000xxxxxxxxxxxxxxxxxxxxx00000000)
CLK72MHZ_CLK_SRC: 000 = pllP_out3 001 = pllC_out0, 010 = pllC2_out0,

011 = CLK_M
0 = PLLP_OUT3
31:29 PLLP_OUT3
1 = PLLC_OUT0
2 = PLLC2_OUT0
3 = CLK_M
7:0 0x0 CLK72MHZ_CLK_DIVISOR: N = Divide by (n+1) (lsb denote 0.5x)
5.7.255 CLK_RST_CONTROLLER_CLK_SOURCE_ADX1_0
Offset: 0x670 | Read/Write: R/W | Reset: 0xd0000000 (0b1101xxxxxxxxxxxxxxxxxxxx00000000)
ADX1_CLK_SRC: 000 = pllA_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

pllC3_out0, 100 = pllP_out0, 110 = clk_m
0 = PLLA_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLP_OUT0
6 = CLK_M
ADX1_MASTER_CLKEN: Obsolete. Use CLK_ENB_ADX1 to control clock

28 0x1
enable
7:0 0x0 ADX1_CLK_DIVISOR: N = Divide by (n+1) (lsb denote 0.5x)

5.7.256 CLK_RST_CONTROLLER_CLK_SOURCE_AMX1_0
Offset: 0x674 | Read/Write: R/W | Reset: 0xd0000000 (0b1101xxxxxxxxxxxxxxxxxxxx00000000)
AMX1_CLK_SRC: 000 = pllA_out0, 001 = pllC2_out0, 010 = pllC_out0, 011 =

pllC3_out0, 100 = pllP_out0, 110 = clk_m
0 = PLLA_OUT0
1 = PLLC2_OUT0
31:29 CLK_M
2 = PLLC_OUT0
3 = PLLC3_OUT0
4 = PLLP_OUT0
6 = CLK_M
AMX1_MASTER_CLKEN: Obsolete. Use CLK_ENB_AMX1 to control clock

28 0x1
enable
7:0 0x0 AMX1_CLK_DIVISOR: N = Divide by (n+1) (lsb denote 0.5x)
5.7.257 CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0
Offset: 0x678 | Read/Write: R/W | Reset: 0x00000000 (0b000xxxxxxxxxxxxx0000000000000000)
VIC_CLK_SRC: 000 = pllM_out0, 001 = pllC_out0, 010 = pllP_out0, 011 =

pllA_out0, 100 = pllC2_out0, 101 = pllC3_out0, 110 = clk_m
0 = PLLM_OUT0
1 = PLLC_OUT0
31:29 PLLM_OUT0 2 = PLLP_OUT0
3 = PLLA_OUT0
4 = PLLC2_OUT0
5 = PLLC3_OUT0
6 = CLK_M
VIC_IDLE_DIVISOR: N = Divide by (n+1) (lsb denote 0.5x) if all 0's, this idle
15:8 0x0 divisor field will not be used. For non-zero values, when host1x is idle, this
field will be used instead of VIC_CLK_DIVISOR.
7:0 0x0 VIC_CLK_DIVISOR: N = Divide by (n+1) (lsb denote 0.5x)
5.7.258 CLK_RST_CONTROLLER_PLLP_OUTC_0
Offset: 0x67c | Read/Write: R/W | Reset: 0x00030000 (0b00000000xxxxx011xxxxxxxxxxxxxxxx)
31:24 0x0 PLLP_OUT5_RATIO: PLLP_OUT5 divider from base PLLP (lsb denote 0.5x).

PLLP_OUT5_OVRRIDE: 0 = disallow PLLP_OUT5 ratio override, 1 = enable

override.
18 DISABLE
0 = DISABLE
1 = ENABLE
PLLP_OUT5_CLKEN: PLLP_OUT5 divider clk enable. 0 = disable, 1 = enable.

1 = ENABLE

RESET_DI
16 0 = RESET_ENABLE
SABLE
1 = RESET_DISABLE
5.7.259 CLK_RST_CONTROLLER_PLLP_MISC1_0
Offset: 0x680 | Read/Write: R/W | Reset: 0x30000000 (0bx011xxxxxxxxxxxxxxxxxxxxxxxxxxxx)
PLLP_HSIO_CLK_EN: Clock gate control for PLLP clock branch to HSIO. 1 =

enable, 0 = disable
29 ENABLE
0 = DISABLE
1 = ENABLE
PLLP_XUSB_CLK_EN: Clock gate control for PLLP clock branch to XUSB. 1 =

enable, 0 = disable
28 ENABLE
0 = DISABLE
1 = ENABLE
5.7.260 CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0
EMC_DIV_CLK_SHAPER_CTRL and EMC_PLLC_SHAPER_CTRL shaper control registers should only be changed when
the shaper paths are not being selected
EMC_DIV_CLK_SHAPER_CTRL shaper path is selected when ENABLE_EMC_DIV_SHAPER is set and EMC_2X_CLK_SRC

is not 111
EMC_PLLC_SHAPER_CTRL shaper is selected when ENABLE_EMC_PLLC_SHAPER is set and EMC_2X_CLK_SRC is 111
Offset: 0x68c | Read/Write: R/W | Reset: 0x00000c00 (0b0xxxxxxxxxxxxxxxxxxx110000000000)
ENABLE_EMC_DIV_SHAPER: DISABLE: Not using the shaped clock for

31 DISABLE int_div_clk in the EMC switch
0 = DISABLE

1 = ENABLE
EMC_DIV_CLK_SHAPER_N0: Adjust Duty Cycle in step sizes smaller than the

11 0x1
delay of the inverter
EMC_DIV_CLK_SHAPER_N1: Adjust Duty Cycle in step sizes smaller than the

10 0x1
EMC_DIV_CLK_SHAPER_P0: Adjust Duty Cycle in step sizes smaller than the

9 0x0
EMC_DIV_CLK_SHAPER_P1: Adjust Duty Cycle in step sizes smaller than the

8 0x0
EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT:
DEFAULT_SETTING: Controlled by shaper pins (RTL): default_values[5:0].
DEFAULT SW_PROG: Controlled by Software programmable register
7
_SETTING EMC_DIV_CLK_SHAPER_CTRL[5:0]
0 = DEFAULT_SETTING
1 = SW_PROG
EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS:
ACTIVE: Shaper circuit in clock path
6 ACTIVE BYPASS: Shaper Bypassed. S -> Y path to reduce distortion
0 = ACTIVE
1 = BYPASS
EMC_DIV_CLK_SHAPER_CTRL_DF:
DISABLE: No delay on CLKIN(fall) -> CLKOUT(fall)
ENABLE: Delay added on CLKIN(fall) -> CLKOUT(fall)
5 DISABLE
Based on the EMC_DIV_CLK_SHAPER_CTRL[4:3] register
0 = DISABLE
1 = ENABLE
4:3 0x0 EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY
EMC_DIV_CLK_SHAPER_CTRL_DR:
DISABLE: No delay on CLKIN(rise) -> CLKOUT(rise)
ENABLE: Delay added on CLKIN(rise) -> CLKOUT(rise)
2 DISABLE
Controlled by the EMC_DIV_CLK_SHAPER_CTRL[1:0] register.
0 = DISABLE
1 = ENABLE
1:0 0x0 EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY
5.7.261 CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0
EMC_DIV_CLK_SHAPER_CTRL and EMC_PLLC_SHAPER_CTRL shaper control registers should only be changed when
the shaper paths are not being selected
EMC_DIV_CLK_SHAPER_CTRL shaper path is selected when ENABLE_EMC_DIV_SHAPER is set and EMC_2X_CLK_SRC

is not 111
EMC_PLLC_SHAPER_CTRL shaper is selected when ENABLE_EMC_PLLC_SHAPER is set and EMC_2X_CLK_SRC is 111

Offset: 0x690 | Read/Write: R/W | Reset: 0x00000c00 (0b0xxxxxxxxxxxxxxxxxxx110000000000)
ENABLE_EMC_PLLC_SHAPER: DISABLE: Not using the shaped clock for

PLLC in the EMC switch
31 DISABLE
0 = DISABLE
1 = ENABLE
EMC_PLLC_SHAPER_N0: Adjust Duty Cycle in step sizes smaller than the

11 0x1
EMC_PLLC_SHAPER_N1: Adjust Duty Cycle in step sizes smaller than the

10 0x1
EMC_PLLC_SHAPER_P0: Adjust Duty Cycle in step sizes smaller than the

9 0x0
EMC_PLLC_SHAPER_P1: Adjust Duty Cycle in step sizes smaller than the

8 0x0
EMC_PLLC_SHAPER_CTRL_TRIM_SELECT:
DEFAULT_SETTING: Controlled by shaper pins (RTL): default_values[5:0].
DEFAULT SW_PROG: Controlled by Software programmable register
7
_SETTING EMC_PLLC_SHAPER_CTRL[5:0]
0 = DEFAULT_SETTING
1 = SW_PROG
EMC_PLLC_SHAPER_CTRL_SW_BYPASS:
ACTIVE: Shaper circuit in clock path
6 ACTIVE BYPASS: Shaper Bypassed. S->Y path to reduce distortion
0 = ACTIVE
1 = BYPASS
EMC_PLLC_SHAPER_CTRL_DF:
DISABLE: No delay on CLKIN(fall) -> CLKOUT(fall)
ENABLE: Delay added on CLKIN(fall) -> CLKOUT(fall) based on the
5 DISABLE
EMC_PLLC_SHAPER_CTRL[4:3] register
0 = DISABLE
1 = ENABLE
4:3 0x0 EMC_PLLC_SHAPER_CTRL_FALL_DELAY
EMC_PLLC_SHAPER_CTRL_DR:
DISABLE: No delay on CLKIN(rise) -> CLKOUT(rise)
ENABLE: Delay added on CLKIN(rise) -> CLKOUT(rise)
2 DISABLE
Controlled by the EMC_PLLC_SHAPER_CTRL[1:0] register
0 = DISABLE
1 = ENABLE
1:0 0x0 EMC_PLLC_SHAPER_CTRL_RISE_DELAY

6.0 CL-DVFS
The CL_DVFS module contains control logic that provides a hardware mechanism for controlling the clock rate and power
supply voltage of the fast CPU complex.
This section describes the closed-loop dynamic voltage and frequency scaling (CL-DVFS) registers. It is not intended to be a
programming guide to CL-DVFS, as it is expected that NVIDIA supplied drivers will always be used with it. However, the
register interface is documented to aid with understanding those drivers.
6.1 CL-DVFS Registers

6.1.1 CL_DVFS_CTRL_0
Offset: 0x0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00)
DFLL_CTRL_MODE: DFLL Control Mode.

0 = DISABLE: Disabled. The ring oscillator does not run.
1 = ENABLE_OPEN_LOOP: In Enable Open Loop mode, the ring oscillator will run, but the control loop
1:0 0x0 will remain inactive.
2 = ENABLE_CLOSED_LOOP: In Enable Closed Loop mode, the control loop is enabled and the I2C
interface will continuously update the control output in order to maintain the desired frequency set in the
DFLL_FREQ_REQ_xxxx fields.
6.1.2 CL_DVFS_CONFIG_0
Offset: 0x4 | Read/Write: R/W | Reset: 0x00000006 (0bxxxxxxxxxxxxxxxxxxxxxxxx00000110)
DFLL_CONFIG_DIV_S: Refclk divider for setting DFLL control loop sample rate. Refclk is divided by 32x
7:0 0x6
the value in this field
6.1.3 CL_DVFS_PARAMS_0
Offset: 0x8 | Read/Write: R/W | Reset: 0x000000f0 (0bxxxxxxx000000000xxxxx00011110000)
24 0x0 DFLL_PARAMS_CG_SCALE: If set to 1, reduces the overall loop gain by a factor of 8.
DFLL_PARAMS_FORCE_MODE:
0 = DISABLE : Disabled. The I2C control value is never forced during a frequency change.
23:22 0x0
1 = FIXED : In Fixed Delay mode, the I2C control value is forced for a fixed number of sample periods.
2 = AUTO: In Auto mode, the I2C control value is forced for a calculated number of sample periods.
DFLL_PARAMS_CF_PARAM: Length of time that a forced I2C control value will be applied after a
frequency change if forcing was requested for that change. In Fixed Delay mode, it provides the number
21:16 0x0
of sample periods to force the I2C control value. In Auto mode, the force time is equal to I2C control
output delta * cf_param / 16
DFLL_PARAMS_CI_PARAM: Integral term gain in the control loop controls how a cycle deficit/surfeit
after a frequency change is cleared. It temporarily raises or lowers the core voltage to allow the total
clock cycle count to converge with the ideal number of cycles that should have been produced since the
last frequency change request.
10:8 0x0 0 = DISABLE
1 = DIV2
2 = DIV4 :
3 = DIV8
4 = DIV16

CL-DVFS

5 = DIV32 :
6 = DIV64
7 = DIV128
DFLL_PARAMS_CG_PARAM: Overall loop gain control (SIGNED value), controls the overall response
7:0 0xf0
time of the control loop
6.1.4 CL_DVFS_TUNE0_0
Offset: 0xc | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxx000000000000000000000000)
23:16 0x0 DFLL_TUNE0_DLY_STK: Input bits to both coarse (4) and fine (4) tune the delay
15:8 0x0 DFLL_TUNE0_DLY_SRAM: Input bits to both coarse (3) and fine (5) tune the delay of the SRAM path.
7:0 0x0 DFLL_TUNE0_DLY_INV: Input bits to both coarse (3) and fine (5) tune the delay of the inverter path
6.1.5 CL_DVFS_TUNE1_0
Offset: 0x10 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxx00000000000000000000)
DFLL_TUNE1_DLY_FINE: Input bits to tune the two phases of the clock. 8 bits to tune, and 1 bit to
19:11 0x0
choose high vs. low
DFLL_TUNE1_DLY_WIRE: Input bits to both coarse (2) and fine (9) tune the delay of wire dominated
10:0 0x0
path
6.1.6 CL_DVFS_FREQ_REQ_0
Offset: 0x14 | Read/Write: R/W | Reset: 0x0000ff40 (0bxxx00000000000001111111101000000)
DFLL_FREQ_REQ_FORCE_EN: Set to '1' to force I2C control output to initial value specified by the
28 0x0
'force_val' field
DFLL_FREQ_REQ_FORCE_VAL: Value forced onto the integrator during a frequency transition, only
27:16 0x0 used if the 'force_en' field below is '1' AND the global 'force_mode' field of the dfll_params register is not
set to 'disable'. The best value is (desired I2C control value - safe I2C control value) x 128) / Cg.
DFLL_FREQ_REQ_SCALE: Proportion of output clock cycles (+1) to *not* skip over a period of 256
15:8 0xff
cycles
DFLL_FREQ_REQ_VALID: Set to '1' to indicate that the frequency configuration is valid and should be
7 0x0 used. If this bit is '0', the control loop will revert to 'open loop' mode, and the I2C control interface value
will be determined by the 'safe' value.
DFLL_FREQ_REQ_MULT: Primary frequency multiplication factor 'F'. The ring oscillator output
6:0 0x40
frequency will be (REF_CLK/2) x F.
6.1.7 CL_DVFS_SCALE_RAMP_0
Offset: 0x18 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000)
DFLL_OUTPUT_RAMP_RATE: The ramp up/ramp down rate of the control signal to the output scaler.
3:0 0x0
Determines the number of cycles (+1) to wait for each counter step.

CL-DVFS
6.1.8 CL_DVFS_DROOP_CTRL_0
Offset: 0x1c | Read/Write: R/W | Reset: 0x00000810 (0bxxxxxxxx00000000xxxx100000010000)
DFLL_DROOP_CTRL_MIN_FREQ: The minimum allowed ring oscillator frequency before the 'droop'
23:16 0x0 clock skipper is enabled. The value written determines the minimum number of cycles that are allowed
in 4 REF_CLK cycles' Fmin = droop_ctrl.min_freq * (REF_CLK / 4)
DFLL_DROOP_CTRL_CUT: CPU clock is scaled by (cut+1)/16 immediately after reaching the minimum
11:8 0x8
ring oscillator frequency
DFLL_DROOP_CTRL_RATE: Controls the rate at which clock cycles are re-introduced to the droop
7:0 0x10 skipper after it has been ramped down to compensate for a frequency droop. It is the number of cycles
(+1) to wait for each counter step
6.1.9 CL_DVFS_OUTPUT_CFG_0
Offset: 0x20 | Read/Write: R/W | Reset: 0x50200000 (0bx1010000xx100000xx00000000000000)
DFLL_OUTPUT_CONFIG_I2C_ENABLE: Master enable control for I2C control value updates. If this
30 0x1
field is '0', then I2C control messages are inhibited, regardless of the DFLL mode.
DFLL_OUTPUT_CONFIG_SAFE: 'Safe' value for the OUTPUT control interface. This value will be
29:24 0x10
output whenever OUTPUT is enabled but the DFLL is disabled, or in open loop mode.
21:16 0x20 DFLL_OUTPUT_CONFIG_MAX: Maximum allowed value on the OUTPUT control interface.
13:8 0x0 DFLL_OUTPUT_CONFIG_MIN: Minimum allowed value on the OUTPUT control interface.
DFLL_OUTPUT_CONFIG_DELTA_EN:
1: In conjunction with 'clk_en'=1, causes the PWM clock/data output to only become active (for 32
7 0x0
cycles) whenever a change in the PWM value occurs.
0: The PWM data/clock outputs run continuously when enabled.
DFLL_OUTPUT_CONFIG_CLK_EN: Enables the PMIC control clock output for digitally controlled
6 0x0
PMICs.
DFLL_OUTPUT_CONFIG_DIV_D: Divider setting for PWM PMIC control output (divides the SOC
5:0 0x0
clock).
6.1.10 CL_DVFS_OUTPUT_FORCE_0
Offset: 0x24 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxx0000000)
6 0x0 DFLL_OUTPUT_FORCE_ENABLE: Enable the force value onto the OUTPUT control output
DFLL_OUTPUT_FORCE_VALUE: Value to force OUTPUT control output whenever the

5:0 0x0
i2c_ctrl_force_enable field is set to 1.

CL-DVFS
6.1.11 CL_DVFS_MONITOR_CTRL_0
Offset: 0x28 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000)
DFLL_MONITOR_CTRL_SELECT: Selects a control loop data source for monitoring

0 = DISABLE
1 = CYCLE_INT
2 = PRO_TERM
2:0 0x0
3 = INT_TERM
4 = OUTPUT_INT
5 = OUTPUT_VALUE
6 = FREQ
6.1.12 CL_DVFS_MONITOR_DATA_0
Offset: 0x2c | Read/Write: RO | Reset: 0x000XXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
16 X DFLL_MONITOR_DATA_NEW: Set to '1' whenever a new sample is generated. Cleared on reads.
DFLL_MONITOR_DATA_VAL: Read data monitor source selected by dfll_monitor_ctrl_select. If

15:0 X
monitoring is enabled, this field is updated every sample period.
6.1.13 CL_DVFS_I2C_CFG_0
Offset: 0x40 | Read/Write: R/W | Reset: 0x0010f000 (0bxxxxxxxxxxx1x0001111x00000000000)
20 0x1 I2C_BUS_ARB: Enables arbitration for bus
18:16 0x0 I2C_MASTER_CODE: Master code for high-speed transfers
15 0x1 I2C_PACKET_MODE: Enables Packet mode for high-speed transfers
14:12 0x7 I2C_SIZE: Size of voltage values from 1 to 7
I2C_ADDR_7BIT_10BIT:
10 0x0 0: Selects 7-bit addressing
1: Select 10-bit addressing
9:0 0x0 I2C_SLAVE_ID: External slave ID address
6.1.14 CL_DVFS_I2C_VDD_REG_ADDR_0
Offset: 0x44 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxx0000000000000000)
15:8 0x0 I2C_DEFAULT_DATA: Default data
7:0 0x0 I2C_ADDR_DATA: Address for voltage sel
6.1.15 CL_DVFS_I2C_STS_0
Offset: 0x48 | Read/Write: RO | Reset: 0x000000XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
6:1 X I2C_LAST_VALUE: Output value from the DFLL of last I2C request that was completed successfully
0 X I2C_REQ_PENDING: Indicates there is an outstanding I2C request

CL-DVFS
6.1.16 CL_DVFS_INTR_STS_0
Offset: 0x5c | Read/Write: RO | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00)
MAX_VDD_LIMIT_INTR: Interrupt to indicate the DFLL has hit the VDD ceiling as programmed in
1 0x0
DFLL_OUTPUT_CONFIG_MAX
MIN_VDD_LIMIT_INTR: Interrupt to indicate the DFLL has hit the VDD floor as programmed in
0 0x0
DFLL_OUTPUT_CONFIG_MIN
6.1.17 CL_DVFS_INTR_EN_0
MAX_VDD_LIMIT_INTR_EN: Enable for interrupt to indicate the DFLL has hit the VDD ceiling as
1 0x0
programmed in DFLL_OUTPUT_CONFIG_MAX
MIN_VDD_LIMIT_INTR_EN: Enable for interrupt to indicate the DFLL has hit the VDD floor as
0 0x0
programmed in DFLL_OUTPUT_CONFIG_MIN
6.1.18 CL_DVFS_I2C_CLK_DIVISOR_REGISTER_0
The divisor values (N) must be programmed so that:
 SCL frequency (Std/Fast/Fm+ modes) = ClkSourceFreq/((tlow+thigh+3)*(N+1)) for lower values of N, up to 3

 SCL frequency (Std/Fast/Fm+ modes) = ClkSourceFreq/((tlow+thigh+2)*(N+1)) for higher values of N, above 3
 SCL frequency (HS mode) = ClkSourceFreq/((ths_low+ths_high+4)*(N+1)) for lower values of N, up to 4
 SCL frequency (HS mode) = ClkSourceFreq/ ((ths_low+ths_high+2)*(N+1)) for higher values of N, above 4
31:16 0x19 I2C_CLK_DIVISOR_STD_FAST_MODE:N = Divide by n+1
15:0 0x1 I2C_CLK_DIVISOR_HSMODE:N = Divide by n+1
6.1.19 CL_DVFS_OUTPUT_LUT_0
This lookup table (LUT) contains voltage LUT values stored in a 33-deep by 8 bit wide RAM. To program the LUT, simply
sequentially address the RAM, using the base offset address of 0x20 (10’b10xxxxxxxx). Addresses are DWORD aligned, not
BYTE aligned. PMIC values must be programmed to span the entire desired operating range, and be monotonically
increasing. The logic assumes that the middle entry (16th) corresponds to the ‘safe’ initial voltage, as specified in the
DFLL_OUTPUT_CONFIG.SAFE field. DFLL_OUTPUT_CONFIG_SAFE is initialized by default to 0x10, which corresponds to
the middle of the LUT. However, the safe value can point to any LUT entry.

CL-DVFS

7.0 TIMERS
®
This section documents the various timers available to software in a Tegra K1 system. The following table summarizes these
timers.
Note: The same logic is present in both Tegra K1 variants. References to Shadow CPU, Cluster1, and CPUs 2 and 3 in
the Fast CPU (FCPU) cluster are not relevant to Tegra K1 64-bit.
Table 23: List of Timers

Name Primary Use Related Secure Freq. Notes
Interrupt
RTC Wall Clock Timer RTC Pseudo 32kHz See the Real-Time Clock section in this
TRM for detailed information.
TMR NVIDIA® Generic Timers TMR9-0 Cfg 1MHz Configurable to be secure
WDT TMR timers used as Watchdog WDT_<> Cfg 1MHz Configurable to be secure
TSC Reference for GIT N/A Yes OSC Counter value can only be updated in
secure mode.
GIT ARM CPU Generic Timers PPIs* Yes TSC These timers use TSC as reference.
*PPIs are per CPU Private Peripheral Interrupts
7.1 ARM CPU Generic Timers (GITs)

®
The ARM Generic Timer architecture defines generic CPU timer requirements. The architecture requires that the SoC supply
a timestamp counter reference that is independent of the CPU clock frequency.
The CPU Generic Timer includes:
 A physical counter that contains the count value of the system counter.
 A virtual counter that indicates virtual time. The virtual counter contains the value of the physical counter minus a 64-
bit virtual offset.
 A set of four timers per CPU.
The four timers are the following:
 Secure Physical Timer

 Non-Secure Physical Timer
 Hypervisor Timer
 Virtual Timer
Refer to the appropriate ARM Architecture Reference Manual for generic timer specifications.
7.2 Generic Timer System Counter (TSC)

The ARM Generic Timer Specification requires a system time-stamp counter (TSC) supplied by the SoC.
The TSC is implemented as part of the Tegra K1 Power Management Controller (PMC). It is a 56-bit counter which runs at the
crystal oscillator clock frequency. Refer to the Power Management Controller section in this TRM for additional TSC
information.

Timers
7.3 NVIDIA Timers (TMR)

The programmable timer block contains ten 29-bit programmable timer counters and one 32-bit timestamp counter.
Timer interval, one-shot, or periodic interrupts are configured in the Timer Present Value register (PTV). When enabled, the
timer loads the Timer Present Value count and begins decrementing every one microsecond. The timer generates a timer
request when the count reaches zero.
If the PTV periodic control bit is set, the timer reloads the PTV interval and continues decrementing the timer.
The timer count is 29 bits wide, supporting timer intervals of 536.87 seconds maximum or 1 microsecond minimum. Bit 30 of
the periodic Timer Value (PTV) is the enable bit for the timer. Reading the PTV Register clears any pending timer interrupt.
A read-only Preset count register (PCR) allows the processor to inspect the current value of the timer decrement counter. The
timestamp counter (32 bits wide) is cleared to zero on reset, and counts upwards every 1 µs.
The figure below shows a reference decomposition of the timers in functional blocks.
Figure 13: Timer Functional Block Diagram
Reset
nReset controller
nReset[i]
Pmc2carReset
Core[i]
System reset
nFIQ Interrupt
nFIQ[i]
controller
Only for COP
i=5
Timers
Timer0
Timer1 Legacy OR OR OR
Timer2 WD
Timer3
Timer4
Timer5
CoreWD[0]
CoreWD[1]
TimerN
CoreWD[4]
 The timers are numbered 0 to 9

 All timers have a dedicated interrupt bit
 Timers 0, 6, 7, 8, and 9 also share a common interrupt called SharedTimerInterrupt.
 Timer interrupts are assigned as follows:
- Timer 1 = primary interrupt controller bit 0
Timers
- Timer 2 = primary interrupt controller bit 1

- Timer 3 = secondary interrupt controller bit 9
- Timer 4 = secondary interrupt controller bit 10
- Timer 5 = fourth interrupt controller bit 25
- Timer 6 = fifth interrupt controller bit 24
- SharedTimerInterrupt = hierarchical group 1, bit 10
7.4 Watchdog Timers (WDTs)

A watchdog timer facilitates recovery from system lockup conditions. The watchdog timer can interrupt the processor when the
selected timer counter expires. Under normal operation, this interrupt is serviced by reading the timer status register
(TIMER_WDTx_STATUS). Any timer in the Tegra K1 timer block may be configured as a watchdog timer.
 The Tegra K1 series processor provides five Watchdog Timers, one each for main CPUs and one for COP (AVP):
WDT0 is allocated to CPU0 of cluster0 or the shadow CPU of cluster1
 WDT1 is allocated to CPU1
 WDT4 is allocated to COP (AVP)
The 5 watchdog timers are directly associated with a processor core, i.e., 4 CPU cores and the COP:
 The watchdog is reset by the corresponding core reset signal

 WD timers 0 to 3 are associated with CPU 0 to 3, WD 4 is associated with COP
There are no dedicated timers for the WDTs. Each WDT can be configured to use any one of the TMRs as its timer source.
Based on the configuration of the TIMER_WDTx_CONFIG register, a WDT works as follows:
 When the timer decrements to zero the first time, a WDT interrupt can be generated
 When the timer consecutively decrements down to zero a second time, without the processor reading the interrupt
status register (TIMER_TMRx_TMR_PCR), a per core FIQ can be generated. This feature only works for the COP;
the corresponding signal does not propagate to the CPU cores.
 When the timer consecutively decrements down to zero a third time, without the processor reading the interrupt
status register (TIMER_TMRx_TMR_PCR), a per CPU reset can be generated.
 When the timer consecutively decrements down to zero a fourth time, a system reset can be generated. The cause of
this system reset can be read by reading PMC_RST_STATUS[RST_SOURCE] (see the Power Management
Controller section for more information).
7.5 Secure TMRs and Secure WDTs

The Tegra K1 series processor TMRs and/or WDTs can be configured to be secure timers. As described in
TIMER_SECURE_CFG register table later in this section, a secure register TIMER_SECURE_CFG -- which itself can only be
written by secure writes – can be configured such that each of the TMRs and WDTs can be independently configured to be
secure. By default all of TMRs and WDTs are non-secure and backward compatible.

Timers
7.6 Legacy Watchdog Timer

The legacy watchdog timer can use one TMR1 or TMR2 as the source and can generate a set of reset signals. This facility is
deprecated and replaced by the more versatile WDTs.
Figure 14: Watchdog Block Diagram
WDT_EN & TMR_EN &

TMR_PERIODIC & Interrupt &
TMR => 0
COP (AVP) Reset
Reset
CPU Reset
Controller
WDT_SEL
System Reset
WDT_COP_RST_EN,
WDT_CPU_RST_EN,
WDT_SYS_RST_EN
The legacy watchdog timer can be programmed to reset just the CPU, just the AVP, or the entire system.
If only the CPU is reset, then the AVP will continue running as-is. The CPU reset vector should be programmed in advance so
that it skips the iROM boot code and jumps directly into its own CPU boot routine (which can be anywhere).
If only the AVP is reset, the same is true. The CPU keeps running as-is. If the AVP reset vector is set to default, it runs the
normal boot code. It is up to the Boot Loader to decide if it needs to restart the CPU as well.
The watchdog timer can be programmed to the maximum timeout value of 0x3fffffff. At 1 µs/count, this is more than one
thousand seconds.
The watchdog timer operates as follows:
1. Watchdog generates an interrupt based on the Timer
a. TMR1 or TMR2 can be selected as source
b. Timer should be programmed as Periodic with Interrupt.
c. CAR.RST_SOURCE.WDT_EN = 1
d. CAR.RST_SOURCE.WDT_SEL selects TMR2/TMR1
2. Reset can be for the AVP, CPU, or full system
a. CAR.RST_SOURCE.WDT_***_RST_EN = 1
3. Upon reboot, CAR.RST_SOURCE.WDT_*_RST_STA indicates the cause of the reset

Timers
7.7 Watchdog Timer Programming Guide

The five watchdog timers operate as follows:
 Select any one of the general-purpose timers as timing reference

 Standard down counter with programmable period, that also counts expirations, specific action are taken at the
counter expiration
- If the expiration count is 0, a normal interrupt may be generated (probably pooled)
- If the expiration count is 1, the FIQ for the corresponding processor may be asserted, this operation bypasses
the normal interrupt controller
- If the expiration count is 2, the reset for a programmable set of processors is asserted, this may be the null set
- If the expiration count is 3, a system wide reset may be asserted (two variants, standard system or closer to
external hardware reset)
Figure 15: Watchdog Example Timing Diagram
Ref Timer
Reload value
Restart
WD Timer CPU0
Current count
0
1st expiration: 2nd expiration: 3rd expiration: 4th expiration:
Shared interrupt Directed FIQ Directed reset System reset
WD Timer CPU0
X 0 1 2 3 0
Expiration count
WD interrupt
CPU0 nFIQ
CPUx nRESET
COP nRESET
SYS nRESET
Any operation that targets CPU0 is done in the following way:
 Any output is broadcast to both instances of CPU0, in CPU cluster 0 (G) and 1 (LP). This applies to the reset and
FIQ signals.
 Resetting any of the CPU0 results in resetting the WD associated with CPU 0
Although the timing diagram implies that you need to restart the timer when you service the interrupt, this is not necessary as
long as you can always service the interrupt (clear the TMR interrupt) before the next timeout occurs. The reset only happens
if a new timeout occurs when the TMR interrupt is still active.

Timers
7.8 Timers Registers

Each timer uses two registers called PTV and PCR at two consecutive word addresses. The format is the same for all 10
timers and is defined only once with <t> taking values between 0 and 9. Note that the start offset sequence is haphazard for
legacy reasons.
Table 24: Start Offsets for PTV and PCR Timer Registers
Timer Start Offset for Register Pair
TMR1 0x00
TMR2 0x08
TMR3 0x50
TMR4 0x58
TMR5 0x60
TMR6 0x68
TMR7 0x70
TMR8 0x78
TMR9 0x80
TMR0 0x88
7.8.1 TIMER_TMR<t>_TMR_PTV_0
Parameter <t> takes a value from 0 to 9. The start offset for the timer is defined relative to the start address in Table 24.
Before programming the timer:
 Input oscillator frequency must be specified in the TIMERUS_USEC_CFG register.

 Program the number of 1 µs timer counts per "tick" in the PTV (Present Trigger Value) register.
 Set the PTV EN (enable bit) to start counting down.
 When the count reaches zero, an interrupt is generated.
 To auto-reload the timer counter, set the PTV PER (periodic) bit. Otherwise, leave it clear for a one-shot.
Timer Present Trigger Value (Set) Register

Offset: See Table 24 │ Read/Write: R/W │ Reset: 0x00000000 (0b00x00000000000000000000000000000)
31 0x0 EN: Enable Timer

0 = DISABLE
1 = ENABLE
30 0x0 PER: Enable Periodic Interrupt

0 = DISABLE
1 = ENABLE
28:0 0x0 TMR_PTV: Trigger Value: count trigger value (count length). This is in n+1 scheme. If
you program the value n, the count trigger value will actually be n+1.

Timers
7.8.2 TIMER_TMR<t>_TMR_PCR_0
Parameter <t> takes a value from 0 to 9. The start offset for the timer is defined relative to the start address in Table 24.
When an interrupt is generated, write "1" to PCR[30] to clear the interrupt
Timer Present Count Value (Status) Register

Offset: See Table 24 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bx0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
30 RW 0x0 INTR_CLR: 1 = clears the interrupt, 0 = no affect. Write-1-to-Clear
28:0 RO X TMR_PCV: Counter value: decrements from PTV.
7.9 Fixed Time Base Registers

The USEC_CFG/CNTR_1US registers provide a fixed time base (in microseconds) to be used by the rest of the system
regardless of the clk_m frequency (i.e., 12 MHz, 13 MHz, 19.2 MHz, 26 MHz, or other frequencies).
7.9.1 TIMERUS_CNTR_1US_0
This free-running read-only register/counter changes once every microsecond and is used mainly by hardware (can also be
used by software). It starts counting from 0 once it is out of system reset and will continue counting forever, unless the
oscillator clock is stopped or during a system reset.
(A) Software Use

Although there is no interrupt mechanism for this register, software can read the content of this register multiple times to
determine the amount of time that has elapsed.
(B) Hardware Use

 Used by the 4 timers to determine whether the programmed timer value has been reached; these 4 timers can trigger
interrupts.
 To provide a periodic USEC pulse to be used by the flow controller to count the programmable number of
microseconds before a flow control condition is triggered.
 Used by secure boot logic.
31:16 x HIGH_VALUE: Elapsed time in microseconds
15:0 x LOW_VALUE: Elapsed time in microseconds
7.9.2 TIMERUS_USEC_CFG_0
Software should first configure this register by telling what fraction of 1 microsecond each clk_m represents. For example, if
the clk_m is running at 12 MHz, then each clk_m represents 1/12 of a microsecond.
"USEC_DIVIDEND" and "USEC_DIVISOR" are used to indicate what fraction of 1 microsecond each clk_m represents.

Timers
Table 25: clk_m Frequency Indicator for USEC
clk_m Frequency Dividend/Divisor USEC_DIVIDEND/USEC_DIVISOR
12 MHz 1/12 0x00 / 0x0b
13 MHz 1/13 0x00 / 0x0c
19.2 MHz 5/96 0x04 / 0x5f
26 MHz 1/26 0x00 / 0x19
16.8 MHz 5/84 0x04 / 0x53
38.4 MHz 5/192 0x04 / 0xbf
48 MHz 1/48 0x00 / 0x2f
Offset: 0x4 | Read/Write: R/W | Reset: 0x0000000c (0bxxxxxxxxxxxxxxxx0000000000001100) | Default: 0x0000000b
15:8 0x0 NONE USEC_DIVIDEND: Microsecond dividend. (n+1)
7:0 0xc 0xb USEC_DIVISOR: Microsecond divisor. (n+1)
7.9.3 TIMERUS_CNTR_FREEZE_0
Offset: 0x3c | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx00000)
4 0x0 DBG_FREEZE_COP: 1 = freeze timers when COP is in debug state, 0 = no freeze.
3 0x0 DBG_FREEZE_CPU3: 1 = freeze timers when CPU3 is in debug state, 0 = no freeze.
7.10 Watchdog Timers

Each Watchdog timer uses four registers called CONFIG, STATUS, COMMAND, and UNLOCK PATTERN, at four
consecutive word addresses. The format is the same for all four timers and is defined only once with <w> taking values from 0
to 4.
The following register offsets are relative to the TMR block base.
Each Watchdog timer has the following:
 CoreWatchdog Configuration Register

 Timer sources are numbered 1 through 10 (0 is not used and results in undefined behavior)

Timers
 Period of 0 results in MAX period

 The generated interrupt is dependent on the WD index.
 WD0 to 3 generate a CPU_WD_Interrupt,
 WD4 generates a COP_WD_Interrupt
 CPU0 settings apply to both clusters
 Core numbering: 0-3 applies to CPU0-CPU3, 4 applies to COP
7.10.1 TIMER_WDT<w>_CONFIG_0
Parameter <w> takes a value from 0 to 4.
Core Watchdog Configuration Register

Offset: 0x100 + (0x20 * <w>) | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxx000000000000000000000)
20:16 0x0 CoreResetBitmapEn: Enable reset of a set of cores at third expiration counter (one bit
per processor) same level the signal from PMC asserted in case of external reset.
15 0x0 Pmc2CarResetEn: Enable Full system reset at fourth expiration of the counter
0 = DISABLE
1 = ENABLE
14 0x0 SystemResetEnable: Enable system reset at fourth expiration of the counter, at same
level as existing watchdog interrupt
0 = DISABLE
1 = ENABLE
FIQEnable: Enable FIQ assertion at second expiration of the counter

13 0x0 0 = DISABLE
1 = ENABLE
InterruptEnable: Enable interrupt at first expiration of the counter

12 0x0 0 = DISABLE
1 = ENABLE
11:4 0x0 Period: Measured in periods of selected timer, this is the reload value
TimerSource: Select the timer used as reference (TMR0 – TMR9)

0 = TMR0
1 = TMR1
2 = TMR2
3 = TMR3
3:0 0x0 4 = TMR4
5 = TMR5
6 = TMR6
7 = TMR7
8 = TMR8
9 = TMR9

Timers
7.10.2 TIMER_WDT<w>_STATUS_0
Core Watchdog Status

Offset: 0x104 + (0x20 * <w>) | Read/Write: RO | Reset: 0x0000XXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
13:12 X CurrentExpirationCount: Current count of expiration since the last start of expiration
11:4 X CurrentCount: Current value of the counter
2 X FiqStatus: Current status of FIQ, cleared by start
1 X InterruptStatus: Current status of interrupt, cleared by start
Enabled: 1 when counter is active. When true, writes to the corresponding config
0 X
register are ignored
7.10.3 TIMER_WDT<w>_COMMAND_0
The StartCounter bit enables watchdog counter operation, loads the watchdog counter, starts the watchdog timer to count
down, resets the expiration count to 0, and clears all flags. Also used as restart.
The counter can be disabled by setting the DisableCounter bit, but only if the unlock register has been programmed before
with the correct pattern. Writing to the command register always clears the disable unlock register. When set while
StartCounter is 0 and the unlock register contains the unlock pattern the Watchdog transitions back to disabled.
The register fields are Write to set only.
CoreWatchdogCommand Register
Offset: 0x108 + (0x20 * <w>) | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00)
1 0x0 DisableCounter: Write 1 to disable WDT counter if unlocked
0 0x0 StartCounter: Write 1 to enable WDT counter
7.10.4 TIMER_WDT<w>_UNLOCK_PATTERN_0
CoreWatchdogDisableUnlock Register
Offset: 0x10c + (0x20 * <w>) | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxx0000000000000000)
UnlockPattern: Must be written with value 0xC45A to allow write to DisableCounter to

15:0 0x0
take effect. The pattern is reset at each write to Command Reg.

Timers
7.11 Timer Shared Interrupt Status

TimerSrcBitmap is used for Timers 6 through 10 which share a common interrupt line to the controller. Bit b is set if timer 6+b
generated an interrupt. The corresponding bit is cleared by writing INTR_CLR bit of the TMR_PCR register.
WatchdogSrcBitmap is used for the 5 watchdog timers. This is the set of Interrupt Status bits from the corresponding
CoreWatchdogStatus, but as a bitmap.
7.11.1 SHARED_INTR_STATUS_0
Offset: 0x0 | Read/Write: RO | Reset: 0x00000XXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
10:6 X TimerSrcBitmap: Timer[0,9:6] interrupt status in bitmap form
4:0 X WatchdogSrcBitmap: WDT[4:0] interrupt status in bitmap form
7.11.2 SHARED_TIMER_SECURE_CFG_0
Offset: 0x4 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxx0xxx00000xx0000000000)
USEC: TIMERUS_USEC_CFG secure mode config. If this bit is set (=1) then
TIMERUS_USEC_CFG register can only be written by secure writes. If this bit is cleared
then TIMERUS_USEC_CFG register can be written by secure or non-secure writes. This
20 0x0 register can always be read by secure or non-secure reads. Note: this bit should be set if
any one of the TMR is enabled to be secure.
1: ENABLE
0: DISABLE
WDT4: WDT4 secure mode config. See the WDT0 bit description. This bit is reserved since
16 0x0
WDT4 belongs to COP and it has no notion of Secure or Non-Secure transactions
15 0x0 WDT3: WDT3 secure mode config. See the WDT0 bit description.
WDT0: WDT0 secure mode config. If this bit is set (=1) then WDT0 registers (i.e.
TIMER_WDT0_{CONFIG,COMMAND,UNLOCK_PATTERN}) can only be written by secure
writes. A non-secure read will not trigger read-side-effect, but would return proper read
value. If this bit is cleared then the WDT0 registers can be written by secure or non-secure
12 0x0 writes. WDT0 registers can always be read by secure or non-secure reads.
Note: if this bit is set, then the TMR used for this WDT0 should be enabled to be secure.
1: ENABLE
0: DISABLE
9 0x0 TMR9: Timer9 secure mode config. See the TMR0 bit description.

Timers
TMR0: Timer0 secure mode config. If this bit is set (=1) then TMR0 registers (i.e.,
TIMER_TMR0_TMR_{PTV,PCR}) can only be written by secure writes. A non-secure read
will not trigger read-side-effect, but would return proper read value. If this bit is cleared then
0 0x0 TMR0 registers can be written by secure or non-secure writes. TMR0 registers can always
be read by secure or non-secure reads.
0: DISABLE
1: ENABLE

8.0 MULTI-PURPOSE I/O PINS AND PIN MULTIPLEXING (PINMUXING)
8.1 Overview
®
Tegra K1 devices can be configured with different I/O functions on particular pins to allow use in a variety of different
configurations. This section discusses how this is controlled and how the pins themselves are set up.
Many of the pins on Tegra K1 devices are connected to multi-purpose I/O (MPIO) pads. An MPIO can operate in two modes:
either acting as a signal for a particular I/O controller, referred to as a Special-Function I/O (SFIO); or as a software-controlled
general-purpose I/O function, referred to as GPIO. Each MPIO has up to four SFIO functions as well as being a GPIO.
Though each MPIO has up to 5 functions (a GPIO function and up to 4 SFIO functions), a given MPIO can only act as a single
function at a given point in time. The Pinmux controller in Tegra K1 devices includes the logic and registers to select a
particular function for each MPIO.
This section describes the following features of MPIOs, the Pinmux controller, and the GPIO controller:
 Basic capabilities of the MPIO pads

 Differences between the variety of MPIO pads
 Mapping of MPIO pads to I/O controllers (i.e., pinmuxing)
 Behavior of the MPIO pads during power-up
 Behavior of the MPIO pads before, during, and after deep sleep
 Recommendations for software programming related to the MPIO pads.
This section covers the Multi-Purpose digital I/O pads. It does not address the special-purpose I/O pads, such as those used
for USB, IC_USB, SATA, PCIE, TVO/DAC, MIPI DSI, MIPI CSI, the oscillator, or DRAM interfaces.
8.2 Terms and Acronyms

Some common terms used with Tegra K1 processor pinmuxing are as follows:
Term Definition
CZ Controlled-output impedance MPIO pads
DD Dual-driver MPIO pads
Deep sleep Also known as LP0. A full-chip power state in which
VDD_CORE is turned off but VDD_RTC (i.e., VDD_AO)
and many of the I/O power rails remain on
DPD Deep Power Down (a mode in which the pad can tolerate
VDD_CORE being turned off)
GPIO General-Purpose I/O
LV Low-voltage MPIO pads
MPIO Multi-Purpose I/O
OD Open-drain MPIO pads
SFIO Special-Function I/O
ST Standard MPIO pads
8.3 MPIO Pad Description

Each MPIO pad consists of:
 An output driver with:

- Tristate capability
- Drive strength controls AND

Multi-Purpose I/O Pins and Pin Multiplexing
- Push-pull mode, open-drain mode, or both

 An input receiver with:
- Schmitt mode, CMOS mode, or both
 A weak pull-up and a weak pull-down
Tegra K1 devices include five types of MPIO pads, which all share a common structure. The following table summarizes the
differences between the five MPIO pad types.
Table 26: MPIO Pad Types

Nominal
Pad I/O Rail Input Output I/O Voltage “Slew Rate” Drive Strength
Pull
Type Voltage Buffer Buffer Tolerance Control Control
Strength
Schmitt &
ST 1.8, 2.8-3.3 push-pull VDDIO 100 kΩ 2 bits, up & down 5 bits, up & down
CMOS
Schmitt &
CZ 1.8, 2.8-3.3 push-pull VDDIO 15 kΩ 2 bits, up & down 7 bits, up & down
CMOS
3.3V for open-
Schmitt & push-pull &
DD 1.8, 2.8-3.3 drain, VDDIO 50 kΩ 2 bits, up & down 5 bits, up & down
CMOS open-drain
otherwise
LV 1.2, 1.8 CMOS push-pull VDDIO 15 kΩ 4 bits, up & down 5 bits, up & down
Schmitt & 100 kΩ --
OD 1.8, 2.8-3.3 open-drain 5V 2 bits, down only 5 bits, up
CMOS down only
The ST (standard) MPIO pads are the most common pads on the chip.
The DD (dual-driver) MPIO pads are similar to the ST pads with the addition of a 3.3V tolerant true open-drain mode. A DD
pad can tolerate its I/O pin being pulled up to 3.3V (regardless of supply voltage) as long as the pad’s output-driver is set to
open-drain mode. There are special power-sequencing considerations when using this functionality.
Note: Refer to “Power Sequencing” in the NVIDIA Tegra K1 Processors Data Sheet (DS-06742-001) for a
complete description of the power-up sequencing requirements for Tegra K1 processors.
Refer to the same section in the NVIDIA Tegra K1 64-Bit Processors Data Sheet (DS-07070-001) for
Tegra K1 64-bit processors.
The OD (open drain) MPIO pads are optimized to tolerate 5V on the I/O pin regardless of the supply voltage. They are similar
to ST pads except for an improved I/O voltage tolerance, the absence of a weak pull-up, and the absence of a push-pull output
driver.
The CZ (controlled output impedance) MPIO pads are optimized for use in applications requiring a tightly controlled output
impedance. They are similar to ST pads except for changes in the drive strength circuitry and in the weak pull-ups/pull-downs.
Tegra K1 processors include CZ pads on the VDDIO_SDMMC1 and VDDIO_SDDMC3 power rails. Each of those rails also
includes a pair of CZ_COMP pads. Circuitry within the Tegra K1 device continually matches the output impedance of the CZ
pads to the on-board pull-up/-down resistors attached to the CZ_COMP pads.
The LV (low voltage) MPIO pads are optimized for use with a 1.2V supply voltage (and signaling level). They support a 1.8V
supply voltage (and signaling level) as a secondary mode. The Tegra K1 processors include LV pads on VDDIO_SDMMC4.
The SDMMC4 interface also has a pair of COMP pads, i.e., LV_COMP pads, to generate impedance code.
Note: Refer to “Pin Definitions” in the NVIDIA Tegra K1 Processors Data Sheet (DS-06742-001) for the list of the
pad types and the nominal pull-up/-down strength associated with each MPIO. See the columns labeled
“MPIO Pad Type” and “Nominal Pull Strength.” The power rail information is located in the “Power
Sequencing” section.

8.4 Pad Controls

The Tegra K1 devices include many controls for each MPIO pad. Some of these controls can be set on a per-pin basis. Other
controls are shared across multiple pins.
8.4.1 Per Pad Options

The following controls can be independently configured on a per-pad basis:
PUPD Internal Pull-up/down option: Option to enable internal Pull-up, Pull-down resistors or neither
TRISTATE Tristate (high-z) option: Disables or enables the pad’s output driver. This setting overrides any other
functional setting and also whether pad is selected for SFIO or GPIO. Can be used when the pad
direction changes or the pad is assigned to different SFIO to avoid glitches.
E_INPUT Input Receiver (Enable/Disable): Enables or disables input receiver.
OD Open Drain option: (Applies to DD pads only) Selects between an open-drain output driver and a
push-pull driver.
IO_RESET Not used.
RCV_SEL (Applies to OD pads only). Selects between “High VIL/VIH” and “Normal VIL/VIH” receivers.
RCV_SEL=1: “High VIL/VIH”
RCV_SEL=0: “Normal VIL/VIH”
During normal operation, these per-pad controls are driven by the pinmux controller registers. See the section called
“Pinmuxing” below for more information.
During deep sleep, the PMC bypasses and then resets the pinmux controller registers. Software should reprogram these
registers as necessary after returning from deep sleep. See the section called “Deep Sleep Behaviors” for more information
on the interaction of PMC, software, and the pinmux controller following deep sleep.
8.4.2 Per Pad Control Group

The MPIO pads are partitioned into 35 “pad control groups”. The following controls can be configured independently for each
pad control group. Pad control groups are associated with a group of pads that share similar functionality for example, GMI,
SDMMC.
HSM High Speed Mode (Enable/Disable)
SCHMT Schmitt Trigger (Enable/Disable)
LPMD Low Power Mode. Select Low Power Modes (different impedance/current values)
Drive Down / Up. Driver Output Pull-Up/Pull-Down drive strength code. Normally, the code is 5
DRVDN / UP
bits but for CZ type pads, it is 7 bits.
Slew Falling / Rising. Driver Output Pull-Up/Pull-Down slew control code. Normally, the code is 2
SLWR/ SLWF
bits. In general, the code corresponding to the minimum slew is set (2’b11).
The controls are configured via the “pad control group registers”. There is one pad control register per pad control group.
During deep sleep, all of these pad control registers automatically return to their power-on-reset state. Software should
reprogram these registers as necessary following deep sleep.
Table 27 lists the register address for each pad control group. Additionally, the table describes the bit positions of the controls
within each register.
For example, writing a 1 to bit 3 of register 0x700000884 will enable the Schmitt trigger mode for the pads in group “cdev1cfg”
pins, DAP_MCLK1 and DAM_MCLK1_REQ. Similarly, clearing bits 14 through 23 of register 0x70000900 will minimize the
drive strength (both up and down) of pads in the gmacfg pad control group.

Table 27: Pad Control Groups Register Addresses

Register
Pad Control Group PREEMP HSM SCHMT DRV_TYPE DRVDN DRVUP SLWR SLWF
Address
gmacfg 0x70000900 0 2 3 7:6 18:14 24:20 29:28 31:30
sdio1cfg 0x700008ec 2 3 18:12 26:20 29:28 31:30
sdio3cfg 0x700008b0 2 3 18:12 26:20 29:28 31:30
sdio4cfg 0x700009c4 2 3 16:12 24:20 29:28 31:30
aocfg0 0x700009b0 2 3 16:12 24:20 29:28 31:30
aocfg1 0x70000868 2 3 16:12 24:20 29:28 31:30
aocfg2 0x7000086c 2 3 16:12 24:20 29:28 31:30
aocfg3 0x700009a8 2 3 16:12 29:28
aocfg4 0x700009c8 2 3 7:6 18:12 26:20 29:28 31:30
cdev1cfg 0x70000884 2 3 16:12 24:20 29:28 31:30
cdev2cfg 0x70000888 2 3 16:12 24:20 29:28 31:30
ceccfg 0x70000938 2 3 16:12 24:20 29:28 31:30
dap1cfg 0x70000890 2 3 16:12 24:20 29:28 31:30
dap2cfg 0x70000894 2 3 16:12 24:20 29:28 31:30
dap3cfg 0x70000898 2 3 16:12 24:20 29:28 31:30
dap4cfg 0x7000089c 2 3 16:12 24:20 29:28 31:30
dap5cfg 0x70000998 2 3 16:12 24:20 29:28 31:30
dbgcfg 0x700008a0 2 3 16:12 24:20 29:28 31:30
ddccfg 0x700008fc 2 3 16:12 24:20 29:28 31:30
dev3cfg 0x7000092c 2 3 16:12 24:20 29:28 31:30
owrcfg 0x70000920 2 3 16:12 24:20 29:28 31:30
spicfg 0x700008b4 2 3 16:12 24:20 29:28 31:30
uaacfg 0x700008b8 2 3 16:12 24:20 29:28 31:30
uabcfg 0x700008bc 2 3 16:12 24:20 29:28 31:30
uart2cfg 0x700008c0 2 3 16:12 24:20 29:28 31:30
uart3cfg 0x700008c4 2 3 16:12 24:20 29:28 31:30
udacfg 0x70000924 2 3 16:12 24:20 29:28 31:30
atcfg1 0x70000870 2 3 7:6 18:12 26:20 29:28 31:30
atcfg2 0x70000874 2 3 7:6 18:12 26:20 29:28 31:30
atcfg3 0x70000878 2 3 7:6 18:12 26:20 29:28 31:30
atcfg4 0x7000087c 2 3 7:6 18:12 26:20 29:28 31:30
atcfg5 0x70000880 2 3 18:14 23:19 29:28 31:30
atcfg6 0x70000994 2 3 7:6 18:12 26:20 29:28 31:30
gmecfg 0x70000910 2 3 18:14 23:19 29:28 31:30
gmfcfg 0x70000914 2 3 18:14 23:19 29:28 31:30
gmgcfg 0x70000918 2 3 18:14 23:19 29:28 31:30
gmhcfg 0x7000091c 2 3 18:14 23:19 29:28 31:30
hvcfg0 0x700009b4 2 3 16:12 29:28
gpvcfg 0x70000928 2 3 16:12 24:20 29:28 31:30
usb_vbus_en_cfg 0x7000099c 2 3 16:12 24:20 29:28 31:30
8.4.3 Per I/O Power Rail

These per-power-rail controls are included in the PMC registers which maintain their state during deep sleep. Software does
NOT need to reprogram these register following deep sleep. The following table summarizes the functionality of these signals
along with how they are controlled in the PMC.
Pin Name Pin Description Control/Grouping Mechanism in PMC
E_33V Active high 3.3V mode select. When low, Generated based on respective PWR_DET signal and the logic is
selects VDDP 1.8V mode. maintained in the PMC, i.e., AO domain
By default, it is maintained at Logic 1 to ensure safe power up of I/Os

that are pulled to 3.3V
E_NO_IOPWR Active high. When high, prevents leakage Maintained per power rails for 16 power rails. Ideally, should have

Pin Name Pin Description Control/Grouping Mechanism in PMC

when I/O power is gone while core power is been set during Cold Reset so that I/O rail voltage ramping does not
still on. affect the pad. However, it is reset in the chips. Whenever an I/O
power rail is shut off on any specific use case, this bit has to be set to
Logic1 before the I/O rails are brought down to avoid excessive
leakage to the pad.
Nine pads are used for Power Detect status of various I/O rails. They are used to sense the I/O rail voltage level (3.3V or not).
They are reflected through the PWR_DET set of registers in the PMC which will in turn control the E_33V pin of the pad.
8.5 Pinmuxing
2
Tegra K1 processors include many types of I/O controllers (such as I C, SDMMC, NAND, and GMI). For some of these
controller types, Tegra K1 processors include multiple “controller instances”. For example, Tegra K1 processors include five
2
active I C controller instances.
Each controller instance on a Tegra K1 processor communicates with external devices via a set of “external signals”. For
2
each controller instance, each signal can be brought out on (at least) one MPIO. For example, each I C controller has two
external signals: CLK and DAT. The CLK signal of the I2C1 controller is available on the MPIO whose ball name is
GEN1_I2C_SCL.
Many of the pins on Tegra K1 devices are connected to multi-purpose I/O (MPIO) pads. To connect an MPIO to a particular
I/O controller, configure it as a Special-Function I/O (SFIO) rather than a General-Purpose I/O (GPIO). Each MPIO has up to
four SFIO functions. Each MPIO can as also be programmed to function as a GPIO. For example, the pin named
UART3_CTS_can act in one of these five ways:
 As a GPIO
 As the signal CTS for UART3
 As the signal CMD for SDMMC
 As the signal CLK for DTV
 As the signal CS3 for SPI4B controller
Though each MPIO supports multiple functions, a given MPIO can only act as a single function at a given point in time. The
Pinmux controller on a Tegra K1 device includes the logic and registers to select a particular function for each MPIO.
Some controller instances have a particular signal available on more than one MPIO. Before using any controller, make sure
that the pinmux registers are programmed to bring each signal out on at most ONE MPIO. For example, UART3’s TXD signal
is available on the MPIOs whose ball names are ULPI_CLK, GMI_A16, etc. In a system which brings out UART3’s TXD
signal on the GMI_A16 ball, the pinmux registers for ULPI_CLK should be programmed to select some other signal.
Some controller instances make their entire set of signals available on two or more sets of MPIOs. That is, such controllers
have more than one “interface”. Before using any controller, make sure that the pinmux registers are programmed to bring out
the controller’s signals on at most ONE interface.
Note: The Pinmux controller includes one register per MPIO. It can be controlled on a per-pin basis.

Figure 16 shows the pinmux logic associated with a single MPIO. The ENB in the diagram (equivalent to the EN pin at the
pad) is active Low. Thus, the pad is active when ENB is Low and is in the High-Z state when ENB is High.
In the figure below, GPIO_OE and SFIO_OE[3:0] are considered active Low; that is, when they are Low, the pad’s output is
enabled.
Figure 16: Structure of Pinmux Controller (per MPIO)

PUPD==2 Legend
Input port Output port
Signal coming from or going to
the SFIO controllers
TRISTATE
Signal coming from or going to Signal coming from or going to
the GPIO controller the pinmux controller
Gpio_oe
Generic IO pad
sfio_oe[3:0]
PINMUX[1:0]
Gpio_sf_sel
sfio_out[3:0]
ENB I/O
Gpio_out
Gpio_sf_sel ENB
Gpio_in
Reg_pinmux[1:0]==0
Reg_pinmux[1:0]==1
Reg_pinmux[1:0]==2
sfio_in[3:0]
Reg_pinmux[1:0]==3
E_INPUT
PUPD==1
Table 28 describes the layout of each Pinmux controller register.
Table 28: Pinmux Register Format
Field Name Bit Position Default Value Description
RCV_SEL 9 0/1 (depends on Applicable for “OD” pads

the type of
interface)
IO_RESET 8 - This is a dummy pin for MPIO pads and not used. The effect of
applying IO_RESET is achieved by keeping A and EN pins of the
pads to Logic 0.

Field Name Bit Position Default Value Description
LOCK 7 0 0: Writes to this register are accepted

1: Writes to this register are ignored (until the next wake from Deep
Sleep)
This is a sticky bit. Once software sets this bit to 1, the only way to
clear it is to reset the chip or enter and exit Deep Sleep.
E_OD 6 DD pads:1 0: the pad’s output driver operates in push-pull mode.

1: the pad’s output driver operates in open-drain mode.
WARNING: the DD pads are only 3.3V tolerant when this bit is set.
When this bit is cleared, the voltage tolerance is limited to the I/O
power supply voltage.
Before pulling/driving external I/Os to a value greater than the I/O

power supply, this bit must be set to avoid excessive leakage.
Default value recommended for DD pads is 1 to ensure that during
power up no excessive leakage occurs irrespective of I/O voltage.
Weak pull-ups are disabled if E_OD is set to 1 for DD pads.
Other pads: 0 This bit only matters for DD pads. It is not implemented for other
MPIO pad types.
E_INPUT 5 0/1 (depends on 0: the pad’s input receiver is disabled.

the type of 1: the pad’s input receiver is enabled.
functionality) Refer to the Tegra K1 Pinmux spreadsheet.
TRISTATE 4 0/1 (depends on 0: the pad’s output driver is enabled.

the type of 1: the pad’s output driver is disabled (i.e., the output driver is in a
functionality) high-impedance state).
Refer to the Tegra K1 Pinmux spreadsheet.
PUPD 3:2 0-2 (depends on 0: the pad’s weak pull-up and pull-down are both disabled
the type of 1: the pad’s weak pull-down is enabled and the weak pull-up is
functionality) disabled.
2: the pad’s weak pull-up is enabled and the weak pull-down is
disabled.
3: this is an illegal combination.
PINMUX 1:0 00 0: set the pinmux logic for SFIO0.

1: set the pinmux logic for SFIO1.
Note that the choice between SFIO and GPIO is controlled via the
GPIO registers.
Refer to the Tegra K1 Pinmux spreadsheet for a list of the SFIO functions supported by each MPIO on Tegra K1 devices.
Each SFIO is listed in the table with the following format: <ControllerType><ControllerInstance><InterfaceLetter>-<Signal>
 ControllerType indicates the type of I/O controller associated with this SFIO function
 ControllerInstance indicates the I/O controller, if the Tegra K1 processor has more than one I/O controller of the
specified type
 InterfaceLetter differentiates between the pin sets, if the controller instance can connect to more than one set of pins
 Signal identifies the particular role this SFIO plays for the I/O controller.
For some of the MPIOs, the hardware includes SFIO functions that are omitted from the spreadsheet. Many of these are
deprecated. Contact NVIDIA for more information.

8.6 Cold Boot Reset

The following list is a simplified description of the device power on/boot process for Tegra K1 devices concentrating on those
aspects which relate to the MPIO pins.
 System-level hardware executes the power-up sequence. This sequence ends when system-level hardware releases
SYS_RESET_N.
 Each MPIO pin has a deterministic power-on-reset state. The particular reset state for each pin is chosen to
minimize the need of on-board components like pull-up resistors in a Tegra K1 based system. For example, the on-
chip weak pull-ups are enabled during power-on-reset for pins which are usually used to drive active-low chip selects.
 Pins that act as a strap source for cold boot must have their inputs enabled (through E_INPUT control). If they have
MPIO Pinmuxing enabled, the strap source should be the primary function.
 The rising edge of SYS_RESET_N does not trigger any of the MPIOs to change their output state.
Note: Refer to “POR Behavior” in the NVIDIA Tegra K1 Processors Data Sheet (DS-06742-001) for a list of the
power-on-reset states for each of the MPIOs.
Following the power-up sequence, most of the MPIOs on the chip will stay in their power-on-reset state until system-
dependent software (e.g., the Boot Loader or the OS) reprograms them. However, depending on the secondary boot device
used in a given system, the Boot ROM may change the state of some of the MPIOs. The following sections list the MPIOs that
the Boot ROM uses for each type of secondary boot device.
8.7 Secondary Boot

The following list is a simplified description of the device boot process for Tegra K1 devices concentrating on those aspects
which relate to the MPIO pins.
1. System-level hardware executes the power-up sequence. This sequence ends when system-level hardware releases
SYS_RESET_N.
2. The Boot ROM on the Tegra K1 device begins executing and programs the on-chip I/O controllers to access the
secondary boot device.
3. The Boot ROM on the Tegra K1 device fetches the BCT and Boot Loader from the secondary boot device.
4. If the BCT and Boot Loader are fetched successfully, Boot ROM on the Tegra K1 device yields to the Boot Loader.
5. Otherwise, Boot ROM on the Tegra K1 device enters USB recovery mode.
Each MPIO pin has a deterministic power-on-reset state. The particular reset state for each pin is chosen to minimize the
need of on-board components like pull-up resistors in a Tegra K1 based system. For example, the on-chip weak pull-ups are
enabled during power-on-reset for pins which are usually used to drive active-low chip selects.
Pins that act as a strap source must have their inputs enabled by default. If they have MPIO functionality, then the default
configuration group should choose strap functionality.
Note: Refer to “ POR Behavior” in the NVIDIA Tegra K1 Processors Data Sheet (DS-06742-001) for a list of the
power-on-reset states for each of the MPIOs.
System designs must adhere to the described power-up sequence.
Following the power-up sequence, most MPIOs on the Tegra K1 device will stay in their power-on-reset state until system-
dependent software (the Boot Loader or the OS) reprograms them. However, depending on the secondary boot device used in
a given system, the Boot ROM may change the state of some of the MPIOs and associated pinmux so that the Boot ROM can
interface with the secondary device to fetch the Boot Loader.
The following subsections list the MPIOs that the Boot ROM uses for each type of secondary boot device. Depending on the
type of secondary boot device used, the associated I/O rails have to be brought up by the Boot ROM/PMIC to facilitate the
data exchange.
8.7.1 SPI Boot

SPI4C is used for a SPI interface for secondary boot. The pins are spread across different MPIOs as summarized below.
Default Pinmux
Ball Name SFIO Usage I/O Power Rail Change Needed?
Selection
YES. To be changed to
GPIO_PI3 SPI4C_CS0 vddio_gmi ALTERNATE2
ALTERNATE3
GPIO_PG5 SPI4C_SCK vddio_gmi ALTERNATE2
ALTERNATE3
GPIO_PG7 SPI4C_DIN vddio_gmi ALTERNATE2
ALTERNATE3
GPIO_PG6 SPI4C_DOUT vddio_gmi ALTERNATE2
ALTERNATE3
TRISTATE control of all the pins needs to be changed to NORMAL. Also the pinmux selection should be changed to select
ALTERNATE3.
8.7.2 eMMC Boot

There are four SDMMC interfaces; the one used as a secondary boot interface is SDMMC4. SDMMC4 has all the necessary
functionality for SDMMC assigned as primary function, and thus there is no need to change the Pinmux configuration.
However, the Boot ROM has to remove the TRISTATE control bit on these pins (through the Pinmux control register) to
ensure the pins do not have the overriding TRISTATE that is making the pins inputs.
Ball names include:
 SDMMC4_CLK
 SDMMC4_CMD
 SDMMC4_DAT0
 SDMMC4_DAT1
 SDMMC4_DAT2
 SDMMC4_DAT3
 SDMMC4_DAT4
 SDMMC4_DAT5
 SDMMC4_DAT6
 SDMMC4_DAT7
8.8 Deep Sleep Behaviors

Deep Sleep is an ultra-low-power standby state in which a Tegra K1 device maintains much of its I/O state while most of the
chip is powered off. The following lists offer a simplified description of the deep sleep entry and exit concentrating on those
aspects which relate to the MPIO pads.
8.8.1 Deep Sleep Entry

The steps to enter deep sleep are as follows:
1. LP-entry software programs the PMC to alert about Deep Sleep entry.

2. LP-entry software also programs the APBDEV_PMC_IO_DPD_REQ registers to emulate a software based overriding
request to enter the DPD. This is done to control the deassertion of E_DPD during LP0 exit which is needed to arrest
glitches associated with I/Os on the LP0 sequence.
3. I/O controllers are brought into the IDLE state.
4. The PMC latches much of Tegra K1’s I/O state, i.e., currently driven by functional logic by sampling the pinmux
controllers output. There are small variations on this logic depending on the pad type (mentioned below). Latching of
the I/O state is triggered by writing into APBDEV_PMC_DPD_SAMPLE_0 register maintained in the PMC register
space.
5. Along with latching the I/O values, various pad controls, such as E_IO_HV,E_33V, have to be latched and driven
depending on the pad type.
6. The PMC runs the state machine to drive the control pins in the pad that puts them in the DPD state. There are two
control pins (E_DPD and SEL_DPD) which have to be driven with proper timing as per the Pad data sheet. The PMC
logic provides a configurable timer to select this. The timer is provided in the APBDEV_PMC_SEL_DPD_TIM_0
register. Entering into DPD is triggered through APBDEV_PMC_IO_DPD_REQ_0. Both registers are in the PMC
register space.
7. The PMC deasserts CORE_PWR_REQ.
8. The PMIC powers down VDD_CORE.
9. The PMC continues to drive the I/O state that it has latched
10. As a result of the LP0 entry sequence, the pads are put in the DPD state by asserting E_DPD and SEL_DPD. When
these signals are asserted, the core supply to the pad (VAUXC_CORE) can be successfully removed and the pad
can be powered using VDD_AO/VDD_RTC. This way the pads keep the I/O states yet consume low power.
Note: For more information about deep sleep entry, refer to the NVIDIA Tegra K1 Processors Data Sheet (DS-
06742-001) .or the NVIDIA Tegra K1 64-Bit Processors Data Sheet (DS-07070-001) as well as the PMC
section in this TRM.
8.8.2 Deep Sleep Exit

1. The PMC detects a wake event (for example, a rising edge on an appropriately configured MPIO)
2. The PMC asserts CORE_PWR_REQ.
3. The PMIC powers up VDD_CORE.
4. The PMC resets the logic within VDD_CORE.
5. The Boot ROM executes Warm Boot code, and it does not clear the APBDEV_PMC_DPD_SAMPLE_0 register.
6. The LP0-exit code in DRAM retrieves pinmux registers for every pin and ensures the TRISTATE/PARKED bit is set to
1 in the respective pinmux register.
7. The LP-exit code in DRAM deasserts APBDEV_PMC_IO_DPD_REQ so that the PMC removes E_DPD.
8. The PMC takes the I/Os out of E_DPD but continues to drive them in SEL_DPD mode. This way the I/O values do
not change during Deep Sleep exit until platform-specific software (i.e., typically customer owned) takes control of the
I/Os.
9. The LP0-exit code in DRAM re-initializes the I/O controllers.
10. The LP0-exit code in DRAM changes the Pinmux configurations to the appropriate controller (based on what was
configured during LP0) and clears TRISTATE/PARKED in the Pinmux register of each pin.
11. The LP0-exit code in DRAM, after restoring all the Pinmux register, clears the APBDEV_PMC_DPD_SAMPLE_0
register, which results in SEL_DPD removal of the pad through hardware logic.
Note: For more information about deep sleep exits, refer to the NVIDIA Tegra K1 Processors Data Sheet (DS-
06742-001) .or the NVIDIA Tegra K1 64-Bit Processors Data Sheet (DS-07070-001) as well as the PMC
section in this TRM.

8.8.3 Pad Capabilities During Deep Sleep

The MPIO pads do not all have identical behavior during deep sleep. They differ with respect to:
 Output buffer behavior during deep sleep:

- Does it maintain a programmable (0, 1, or tristate) constant value OR
- Is it capable of changing state while the chip is still in deep sleep (for example, a pin related to the keyboard
controller)?
 Input buffer behavior during deep sleep:
- Is it forcibly disabled OR
- Can it be enabled for use as a “GPIO wake event” OR
- Can it be enabled for some other purpose (for example, a “clock request” pin)?
 Weak pull-up/pull-down behavior during deep sleep
- Are they forcibly disabled OR
- Can they be configured?
 Behavior coming out of deep sleep
- All the pads should maintain the state until software configures the I/O controller
 Pads that do not enter DPD mode during LP0
- Some pads whose outputs are dynamic have a special type and they don’t enter DPD mode during LP0. The
PMC has a configurable option to exclude specific pads from entering DPD during LP0 (see the PMC register
APBDEV_PMC_DPD_PADS_ORIDE_0)
- Pads that are associated with PMIC logic do not enter DPD mode during LP0
- Some pads like JTAG do not enter DPD mode.
Refer to the “Deep Sleep Behavior” section in the NVIDIA Tegra K1 Processors Data Sheet (DS-06742-001) or the NVIDIA
Tegra K1 64-Bit Processors Data Sheet (DS-07070-001) for a summary of the capabilities of each MPIO during deep sleep.
8.8.3.1 Output Buffers During Deep Sleep

The output buffers of most MPIO pads are “configurable” during deep sleep. Immediately prior to entering deep sleep, the
PMC latches the state of the output buffers for such pads. If the pad was driving high (or low) prior to entering deep sleep, the
PMC ensures that it continues to drive high (or low) throughout deep sleep. If the pad was tristated during deep sleep, the
PMC ensures that it remains tristated throughout deep sleep.
The weak pull-ups and pull-downs of most of the MPIO pads are “disabled” or “not available” during deep sleep to reduce the
Tegra K1 device’s static current consumption. For the remainder of the MPIO pads, the weak pull-up and pull-down are
“configurable” during deep sleep. If the pull-up (or pull-down) was enabled prior to entering deep sleep, the PMC ensures that
it remains enabled throughout deep sleep. Similarly, if the pull-up (or pull-down) was disabled prior to entering deep sleep, the
PMC ensures that it remains enabled throughout deep sleep.
Some MPIO pads have an output buffer which behaves in a “special” way during deep sleep. The output state of these pads
may change while the Tegra K1 device remains in deep sleep. For example, the keyboard controller may continue scanning
the keypad matrix during deep sleep.
8.8.3.2 Input Buffers During Deep Sleep

The input buffers of most MPIO pads are “disabled” during deep sleep. The input buffers are placed in an ultra-low power
state. The Tegra K1 device will not respond to transitions on these pads while it is in deep sleep.

Some MPIO pads have an input buffer which has a “special” behavior during deep sleep. Most of these pads can act as
“Deep Sleep Wake Sources”. Others offer some other functional behavior. For example, SYS_CLK_REQ can function as a
clock request pin even during deep sleep.
For a complete description of the behavior of these pads during deep sleep, refer to the NVIDIA Tegra K1 Processors Data
Sheet (DS-06742-001) or the NVIDIA Tegra K1 64-Bit Processors Data Sheet (DS-07070-001). Pads whose input can be
sampled during Deep Sleep are mentioned as ENABLED in the input buffer column. To ensure the PMC wake logic can
sense these wake events, the signals must be directly taken from the ZI pin of the pad because pinmux controls are not
available during LP0. Pads that are acting as wake source should satisfy the following condition: The pad’s power rail should
be active.
8.8.3.3 Behavior During Deep Sleep Exit

MPIO pads “hold” their deep sleep state until system-dependent software deasserts the TRISTATE bit in the associated
Pinmux controller registers. This gives software the opportunity to re-initialize the pinmux and I/O controllers without any
glitches in the state of the MPIO pads.
8.9 GPIO Controller

The GPIO controller for Tegra K1 devices provides the tools for configuring each MPIO for use as a software-controlled GPIO.
The GPIO controller is divided into 8 banks. Each bank handles the GPIO functionality for up to 32 MPIOs. Within a bank, the
GPIOs are arranged as four ports of 8 bits each. The ports are labeled consecutively from A through Z and then AA through
FF. Ports A through D are in bank 0. Ports E through H are in bank 1. In total, there are 162 GPIOs, and the banking and
numbering conventions will have some break in between but will maintain backward compatibility in register configurations for
the GPIOs as that of previous generation chips.
Note: Refer to the “Pin Descriptions” section in NVIDIA Tegra K1 Processors Data Sheet (DS-06742-001) or the
NVIDIA Tegra K1 64-Bit Processors Data Sheet (DS-07070-001) for a map of each of the Tegra K1 device
MPIO pads to a particular GPIO port and bit. See the column labeled “GPIO.”
Each GPIO can be individually configurable as Output/Input/Interrupt sources with level/edge controls.
GPIO configuration has a lock bit controlling every bit separately. When the LOCK bit is set, the associated control aspects of
the bits (for example, whether it is an Output/Input or used as GPIO or SFIO or values driven) cannot be modified (locked).
The LOCK bit gets cleared only by system reset; it is sticky. This bit can be used for security-related functionality where an
authorized entity owning the GPIO can set the configuration and lock it. The lock bit also covers the GPIO output value, so
this may not be varied dynamically once lock is enabled.
The GPIO controller also has masked-write registers. Values written to these registers specify both a mask of bits to be
updated in the underlying state (the mask bits are not sticky) as well as new values for that state. Individual bits of the state
can be updated without the need for a read-modify-write sequence. Thus different portions of software can modify the GPIO
controller state without coordination.
8.10 Programming Considerations
8.10.1 Controller Instances with Multiple Pin-outs

Several of the I/O controller instances on a Tegra K1 device have more than one pin-out. That is, the controller can
communicate with the outside world via more than one set of pins. Special care is warranted when programming the Pinmux
controller for these SFIOs. For a given signal on a given controller’s interface, only a single pin-out should be selected in the
pinmux registers.

For example, TXD is an output signal from UART A. It is available on six pins: ULPI_DATA0, SDMMC1_DATA2,
SDMMC3_DATA1, GPIO_PU0, GPIO_PS1, and UART2_RTS_N. Depending on the value programmed into the
corresponding pinmux registers, each of those six pins might toggle when UART A transmits data.
Similarly, RXD is an input signal to UART A. It is available on six pins: ULPI_DATA1, SDMMC1_DATA1, SDMMC3_CMD,
GPIO_PU1, GPIO_PS2, and UART2_CTS_N. Depending on the value programmed into the corresponding pinmux registers,
UART A might see the logical-OR of the signal on those six pins. This scenario will almost certainly lead to data corruption. If
the UART A RXD signal is brought out on ULPI_DATA1, the pinmux registers for the other five pins should be programmed to
some other function.
8.10.2 Resume From Deep Sleep

As the Tegra K1 device enters Deep Sleep, most of its register state is lost. In particular the pinmux, GPIO, and pad control
registers lose their state during LP0. Software is responsible for reprogramming those registers upon resume from deep
sleep.
8.10.3 Unused Pins

For each unused MPIO, assert its tristate and disable its input buffer. For pins whose internal pull-up is enabled during power-
on-reset, assert the internal pull-up. Otherwise, assert the internal pull-down.
If all of the pins in a pad-control group are unused, set the drive strengths and slew rates to minimum.
If all of the pins on a power-rail are unused, assert E_NOIOPOWER for that rail in the PMC registers.
8.10.4 Security Considerations for the Pinmux Register

Though attacks via Pinmux are mostly Denial Of Service (DoS) attacks, there are specific cases which are a concern, for
example:
 Pins interfacing with Platform PMICs (by reprogramming those pinmuxes, one can cause severe user disruption)
 Any I/O device that is transferring secret data (typically like Serial PROMs having keys). By reprogramming the
pinmux, it is possible to redirect the data to wrong interface
In such cases, it is better to make use of the LOCK bit in the Pinmux control register so that values cannot be tampered with.
The Boot Loader can perform this task so that customer software does not have to configure those pins. As part of LP0 exit,
the lock bit will have to be re-enabled, because the lock is not retained across LP0. Similarly, the GPIO controller has a lock
bit for each GPIO to preserve the configuration, value driven, and also the pin is configured as GPIO or SFIO. The
configuration can be protected using the lock bit in the GPIO register. This way secure software such as a Boot Loader can
ensure that certain pins have the required configuration, irrespective of the actions of less secure software.
8.10.5 Drive Strengths

For all pads that do not have corresponding calibration pads, the drive strength has to be programmed. The common default
value assumed for the pad drive impedance is 50 ohms and hence pads have to be programmed with a code that can give 50
ohm impedance. Because the code depends on VDDP, i.e., I/O rail, and also PVT (Process, Voltage and Temperature)
corners default a code corresponding to TT-NV-NT (Typical process, Normal Voltage, and Normal Temperature) corner as a
function of VDDP voltage is chosen.
In Tegra K1 devices, the primary boot device (SDMMC4) has an auto-calibration option. Thus those pads get an impedance
code that matches the PVT conditions, etc. and hence enable the boot process. For all other MPIO pads (which are not
involved during boot), the BCT can have a value of the code based on the I/O rail and pad data sheet. The same is
programmed by the Boot Loader or any platform-specific software, and it overrides the default Power on Reset values. If the
values have to be changed based on SI results, then the same can be loaded in the primary device.

8.11 GPIO Registers

Each port of each GPIO controller has several registers for the control and monitoring of the port’s 8 GPIO pins. The registers
provide per-pin control of the following features:
 GPIO_CNF_* / GPIO_MSK_CNF Select SPIO or GPIO

 GPIO_OE_* / GPIO_MSK_OE_* Output Enable
 GPIO_OUT_* / GPIO_MSK_OUT_* GPIO Output Value
 GPIO_IN_* GPIO Input Value (Read Only)
 GPIO_INT_STA_* / GPIO_MSK_INT_STA_* GPIO Interrupt Status
 GPIO_INT_ENB_* / GPIO_MSK_INT_ENB_* Interrupt Enable
 GPIO_INT_LVL_* / GPIO_MSK_INT_LVL_* Interrupt Selection (Edge/Level)
 GPIO_INT_CLR_* Interrupt Flag Set-to-Clear
Many of the control registers are accessible from two offsets. Accesses to the lower offsets affect all 8 pins for the GPIO port.
Accesses to the upper offsets provide a per-pin mask capability allowing adjustments to a subset of the pins. Using the upper
offsets can eliminate the need for Read-Modify-Write operations. For example, a write to GPIO_MSK_CNF can substitute for
a Read-Modify-Write of GPIO_CNF.
Table 29: Tegra K1 GPIO Register Summary
Register Name Offset (Lower: Read-Modify-Write) Offset (Upper: Per-Pin Mask Write)
GPIO Controller 1 – Port A B C D A B C D

GPIO_CNF_0 000 004 008 00C 080 084 088 08C
GPIO_OE_0 010 014 018 01C 090 094 098 09C
GPIO_OUT_0 020 024 028 02C 0A0 0A4 0A8 0AC
GPIO_IN_0 030 034 038 03C
GPIO_INT_STA_0 040 044 048 04C 0C0 0C4 0C8 0CC
GPIO_INT_ENB_0 050 054 058 05C 0D0 0D4 0D8 0DC
GPIO_INT_LVL_0 060 064 068 06C 0E0 0E4 0E8 0EC
GPIO_INT_CLR_0 070 074 078 07C
GPIO Controller 2 – Port E F G H E F G H
GPIO_CNF_1 100 104 108 10C 180 184 188 18C
GPIO_OE_1 110 114 118 11C 190 194 198 19C
GPIO_OUT_1 120 124 128 12C 1A0 1A4 1A8 1AC
GPIO_IN_1 130 134 138 13C
GPIO_INT_CLR_1 170 174 178 17C
GPIO Controller 3 – Port I J K L I J K L
GPIO_CNF_2 200 204 208 20C 280 284 288 28C
GPIO_OE_2 210 214 218 21C 290 294 298 29C

GPIO_OUT_2 220 224 228 22C 2A0 2A4 2A8 2AC

GPIO_IN_2 230 234 238 23C
GPIO_INT_CLR_2 270 274 278 27C
GPIO Controller 4 – Port M N O P M N O P
GPIO_CNF_3 300 304 308 30C 380 384 388 38C
GPIO_OE_3 310 314 318 31C 390 394 398 39C
GPIO_OUT_3 320 324 328 32C 3A0 3A4 3A8 3AC
GPIO_IN_3 330 334 338 33C
GPIO_INT_CLR_3 370 374 378 37C
GPIO Controller 5 – Port Q R S T Q R S T
GPIO_CNF_4 400 404 408 40C 480 484 488 48C
GPIO_OE_4 410 414 418 41C 490 494 498 49C
GPIO_OUT_4 420 424 428 42C 4A0 4A4 4A8 4AC
GPIO_IN_4 430 434 438 43C
GPIO_INT_CLR_4 470 474 478 47C
GPIO Controller 6 – Port U V W X U V W X
GPIO_CNF_5 500 504 508 50C 580 584 588 58C
GPIO_OE_5 510 514 518 51C 590 594 598 59C
GPIO_OUT_5 520 524 528 52C 5A0 5A4 5A8 5AC
GPIO_IN_5 530 534 538 53C
GPIO_INT_CLR_5 570 574 578 57C
GPIO Controller 7 – Port Y Z AA BB Y Z AA BB
GPIO_CNF_6 600 604 608 60C 680 684 688 68C
GPIO_OE_6 610 614 618 61C 690 694 698 69C
GPIO_OUT_6 620 624 628 62C 6A0 6A4 6A8 6AC
GPIO_IN_6 630 634 638 63C

GPIO_INT_CLR_6 670 674 678 67C

GPIO Controller 8 – Port CC DD EE CC DD EE
GPIO_CNF_7 700 704 708 780 784 788
GPIO_OE_7 710 714 718 790 794 798
GPIO_OUT_7 720 724 728 7A0 7A4 7A8
GPIO_IN_7 730 734 738
GPIO_INT_STA_7 740 744 748 7C0 7C4 7C8
GPIO_INT_ENB_7 750 754 758 7D0 7D4 7D8
GPIO_INT_LVL_7 760 764 768 7E0 7E4 7E8
GPIO_INT_CLR_7 770 774 778
8.11.1 GPIO_CNF_0
Designate whether each pin operates as a GPIO or as an SFIO. By default all pins come up in SFIO mode. These can be
programmed to GPIO mode at any stage. This is an array of 4 identical register entries; the register fields below apply to each
entry.
Lock bits are used to control the access to the CNF and OE registers. When set, no one can write to the CNF and OE bits.
They can be programmed ONLY during Boot and get reset by chip reset only.
GPIO Port Configuration Registers

Offset: 0h..fh | Read/Write: R/W | Reset: 0b0000000000000000
15 DISABLE LOCK_7: Lock access to pin 7 CNF, OE and OUT

0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
7 0x0 BIT_7: Configures each pin to be in either GPIO or SFIO mode
0 = SPIO
1 = GPIO


0 = SPIO
1 = GPIO
0 = SPIO
1 = GPIO
0 = SPIO
1 = GPIO
0 = SPIO
1 = GPIO
0 = SPIO
1 = GPIO
0 = SPIO
1 = GPIO
0 = SPIO
1 = GPIO
8.11.2 GPIO_OE_0
GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid.
The set of registers below are used to either drive the signal out or as an Input. This needs to be programmed depending upon
whether the pin needs to be in either Input or Output.
This is an array of 4 identical register entries; the register fields below apply to each entry.
GPIO Port Enable Registers

Offset: 10h..1fh | Read/Write: R/W | Reset: 0b00000000
7 0x0 BIT_7: GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid.
0 = TRI_STATE
1 = DRIVEN
6 0x0 BIT_6: GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
0 = TRI_STATE
1 = DRIVEN
0 = TRI_STATE
1 = DRIVEN
0 = TRI_STATE
1 = DRIVEN
0 = TRI_STATE
1 = DRIVEN
0 = TRI_STATE
1 = DRIVEN

0 = TRI_STATE
1 = DRIVEN
0 = TRI_STATE
1 = DRIVEN
8.11.3 GPIO_OUT_0
GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO output enabled) must be true for this to be valid. This register will
take affect only in GPIO mode. This register is used to drive the value out on a given pin.
GPIO Port Output Value Registers (Read/Write)

7 0x0 BIT_7: GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO output enabled) must
be true for this to be a valid state
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
8.11.4 GPIO_IN_0
GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. This is a read-only register used to read the value
from the pin. This is an array of 4 identical register entries; the register fields below apply to each entry.

GPIO Port Input Value Registers (Read Only)

0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
All GPIO inputs can be independently programmed to generate an interrupt request.
In addition, the individual trigger level for interrupt on each input pin can be programmed as either active-on-high or active-on-
low. For example, to program an active-on-high interrupt on bit 3 of GPIO-PORT_C, write '1' into bit 3 of GPIO_INT.LVL.C
register (this sets the interrupt to be active-on-high), and then write '1' into bit 3 of GPIO_INT.ENB.C (this enables interrupt on
the named bit).
The interrupt flag status can be read in the appropriate bit of the GPIO_INT.STA.C register. Once the programmed interrupt
occurs, status should be cleared by writing into the appropriate bit of the GPIO_INT.CLR.C register. Note that the interrupt
thus generated is routed to the processor only if the corresponding bit for GPIO interrupts in the Secondary interrupt controller
is enabled.
8.11.5 GPIO_INT_STA_0
GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid. Every GPIO pin generates
an Interrupt when switching from Low-High to High-Low. Interrupt status for each port is saved in an Interrupt status register.
GPIO Port Interrupt Status Registers

7 0x0 BIT_7: GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this
condition to be valid.
0 = IN_ACTIVE
= ACTIVE

0 = IN_ACTIVE
1 = ACTIVE
0 = IN_ACTIVE
1 = ACTIVE
0 = IN_ACTIVE
1 = ACTIVE
0 = IN_ACTIVE
1 = ACTIVE
0 = IN_ACTIVE
1 = ACTIVE
0 = IN_ACTIVE
1 = ACTIVE
0 = IN_ACTIVE
1 = ACTIVE
8.11.6 GPIO_INT_ENB_0
Every bit of the GPIO pin has an enable which, when enabled, routes the Interrupt to the Interrupt controller. This is an array of
4 identical register entries; the register fields below apply to each entry.
GPIO Port Interrupt Enable Registers

0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
8.11.7 GPIO_INT_LVL_0
The GPIO can detect an interrupt for any edge- or level-sensitive signal.
This is an array of 4 identical register entries; the register fields below apply to each entry
GPIO Port Interrupt Activation Level Registers

23 0x0 DELTA_7: 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
15 0x0 EDGE_7: 1 means Configure as Edge-Triggered Interrupt
7 0x0 BIT_7: Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH

0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
0 = LOW
1 = HIGH
8.11.8 GPIO_INT_CLR_0
This write-only register clears the Interrupts that are set. This is valid only in GPIO mode when GPIO_INT.ENB is set.
GPIO Port Interrupt Flag Set-to-Clear Registers

0 = SET
1 = CLEAR
0 = SET
1 = CLEAR
0 = SET
1 = CLEAR
0 = SET
1 = CLEAR
0 = SET
1 = CLEAR
0 = SET
1 = CLEAR
0 = SET
1 = CLEAR

0 = SET
1 = CLEAR
8.11.9 GPIO_MSK_CNF_0
Each register is provided with an individual 16-bit version for enabling Masked Writes to avoid a Read-Modify-Write operation
by the firmware. The exception is for the interrupt clear register, whose functionality is combined in the interrupt status register.
Individual pins only can be programmed by suitably enabling the write masks in the upper byte of these 16-bit registers.
MASKED PRIMARY GPIO/SFIO Config Registers (Masked Writes)

15 WO 0x0 MSK7: 0=Disable bit for write

0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
7 RW 0x0 BIT_7:
0 = SPIO
1 = GPIO
6 RW 0x0 BIT_6:
0 = SPIO
1= GPIO
5 RW 0x0 BIT_5:
0 = SPIO
1 = GPIO
4 RW 0x0 BIT_4:
0 = SPIO
1 = GPIO

3 RW 0x0 BIT_3:
0 = SPIO
1 = GPIO
2 RW 0x0 BIT_2:
0 = SPIO
1 = GPIO
1 RW 0x0 BIT_1:
0 = SPIO
1 = GPIO
0 RW 0x0 BIT_0:
0 = SPIO
1 = GPIO
8.11.10 GPIO_MSK_OE_0
GPIO Masked Output Enable (Masked Writes)


0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
7 RW 0x0 BIT_7:
0 = TRI_STATE
1 = DRIVEN
6 RW 0x0 BIT_6:
0 = TRI_STATE
1 = DRIVEN
5 RW 0x0 BIT_5:
0 = TRI_STATE
1 = DRIVEN

4 RW 0x0 BIT_4:
0 = TRI_STATE
1 = DRIVEN
3 RW 0x0 BIT_3:
0 = TRI_STATE
1 = DRIVEN
2 RW 0x0 BIT_2:
0 = TRI_STATE
1 = DRIVEN
1 RW 0x0 BIT_1:
0 = TRI_STATE
1 = DRIVEN
0 RW 0x0 BIT_0:
0 = TRI_STATE
1 = DRIVEN
8.11.11 GPIO_MSK_OUT_0
GPIO A-D Masked Output Enable (Masked Writes)

Offset: a0h..afh | Read/Write: R/W | Reset: 0b0000000000000000

0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
7 RW 0x0 BIT_7:
0 = LOW
1 = HIGH
6 RW 0x0 BIT_6:
0 = LOW
1 = HIGH

5 RW 0x0 BIT_5:
0 = LOW
1 = HIGH
4 RW 0x0 BIT_4:
0 = LOW
1 = HIGH
3 RW 0x0 BIT_3:
0 = LOW
1 = HIGH
2 RW 0x0 BIT_2:
0 = LOW
1 = HIGH
1 RW 0x0 BIT_1:
0 = LOW
1 = HIGH
0 RW 0x0 BIT_0:
0 = LOW
1 = HIGH
8.11.12 GPIO_MSK_INT_STA_0
GPIO A-D Masked Interrupt Status (Masked Clears)

Offset: c0h..cfh | Read/Write: R/W | Reset: 0b0000000000000000

0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
7 RW 0x0 BIT_7:
0 = IN_ACTIVE
1 = ACTIVE

6 RW 0x0 BIT_6:
0 = IN_ACTIVE
1 = ACTIVE
5 RW 0x0 BIT_5:
0 = IN_ACTIVE
1 = ACTIVE
4 RW 0x0 BIT_4:
0 = IN_ACTIVE
1 = ACTIVE
3 RW 0x0 BIT_3:
0 = IN_ACTIVE
1 = ACTIVE
2 RW 0x0 BIT_2:
0 = IN_ACTIVE
1 = ACTIVE
1 RW 0x0 BIT_1:
0 = IN_ACTIVE
1 = ACTIVE
0 RW 0x0 BIT_0:
0 = IN_ACTIVE
1 = ACTIVE
8.11.13 GPIO_MSK_INT_ENB_0
GPIO A-D Masked Interrupt Enable (Masked Writes)

Offset: d0h..dfh | Read/Write: R/W | Reset: 0b0000000000000000

0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE

7 RW 0x0 BIT_7:
0 = DISABLE
1 = ENABLE
6 RW 0x0 BIT_6:
0 = DISABLE
1 = ENABLE
5 RW 0x0 BIT_5:
0 = DISABLE
1 = ENABLE
4 RW 0x0 BIT_4:
0 = DISABLE
1 = ENABLE
3 RW 0x0 BIT_3:
0 = DISABLE
1 = ENABLE
2 RW 0x0 BIT_2:
0 = DISABLE
1 = ENABLE
1 RW 0x0 BIT_1:
0 = DISABLE
1 = ENABLE
0 RW 0x0 BIT_0:
0 = DISABLE
1 = ENABLE
8.11.14 GPIO_MSK_INT_LVL_0
GPIO Masked Write Interrupt Activation Levels

Offset: e0h..efh | Read/Write: R/W | Reset: 0b0000000000000000

1 = ENABLE
1 = ENABLE
1 = ENABLE
1 = ENABLE
1 = ENABLE
1 = ENABLE
1 = ENABLE
1 = ENABLE
7 RW 0x0 BIT_7:
0 = LOW
1 = HIGH

6 RW 0x0 BIT_6:
0 = LOW
1 = HIGH
5 RW 0x0 BIT_5:
0 = LOW
1 = HIGH
4 RW 0x0 BIT_4:
0 = LOW
1 = HIGH
3 RW 0x0 BIT_3:
0 = LOW
1 = HIGH
2 RW 0x0 BIT_2:
0 = LOW
1 = HIGH
1 RW 0x0 BIT_1:
0 = LOW
1 = HIGH
0 RW 0x0 BIT_0:
0 = LOW
1 = HIGH
8.12 Pinmux Registers

This section defines the Pinmux selects, Pullup, Pulldn, and E_input programmability for each pin/ball in Tegra K1 devices.
Every register has 7 bits defined for Functional Pin Select. The rest are specific to a few pads such as OD and IO_RESET.
1:0 PM --> Functional Pin Select.
3:2 PUPD --> Pullup / PullDn control.
4 Tristate --> Tristate Enable / Disable.
5 E_INPUT --> Input Receiver Enable/Disable.
7 LOCK --> Locks access to all configurable bits for pins, including itself.
--> 1 = Enable (preferably done during boot)
--> 0 = Disable (can only be done by full system reset)
8 IO_RESET --> Forces output drivers disabled (PU/PD control only). Required to guarantee pin state on *LPDDR2* pads
during POR.
--> IO_RESET_N will override the enable signal of main driver. After power-up, core controls should be enabled first to drive
the pad with the same value as programmed by E_PULL. Then IO_RESET_N / E_PULL can be deasserted.
--> If IO_RESET_N is deasserted before core controls come up, there could be unknown outputs or glitches.
Optional bits:
6 OD --> Open Drain Enable / Disable. Specifically for I2C pads.
9 RCV_SEL --> Select between High and Normal VIL/VIH receivers. RCVR_SEL=1: High VIL/VIH RCVR_SEL=0: Normal
VIL/VIH

8.12.1 PINMUX_AUX_ULPI_DATA0_0
Offset: 0x3000 | Read/Write: R/W | Reset: 0x00000038 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x111000)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
4 TRISTATE TRISTATE:
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI3 PM:
0 = SPI3
1 = HSI
2 = UARTA
3 = ULPI

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI3 PM:
0 = SPI3
1 = HSI
2 = UARTA
3 = ULPI

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI3 PM:
0 = SPI3
1 = HSI
2 = UARTA
3 = ULPI
Offset: 0x300c | Read/Write: R/W | Reset: 0x00000038 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x111000)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI3 PM:
0 = SPI3
1 = HSI
2 = UARTA
3 = ULPI

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 SPI2 PM:
0 = SPI2
1 = HSI
2 = UARTA
3 = ULPI

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI2 PM:
0 = SPI2
1 = HSI
2 = UARTA
3 = ULPI

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI2 PM:
0 = SPI2
1 = HSI
2 = UARTA
3 = ULPI


7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI2 PM:
0 = SPI2
1 = HSI
2 = UARTA
3 = ULPI
8.12.9 PINMUX_AUX_ULPI_CLK_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI1 PM:
0 = SPI1
1 = SPI5
2 = UARTD
3 = ULPI
8.12.10 PINMUX_AUX_ULPI_DIR_0
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE

0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI1 PM:
0 = SPI1
1 = SPI5
2 = UARTD
3 = ULPI
8.12.11 PINMUX_AUX_ULPI_NXT_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI1 PM:
0 = SPI1
1 = SPI5
2 = UARTD
3 = ULPI
8.12.12 PINMUX_AUX_ULPI_STP_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 SPI1 PM:
0 = SPI1
1 = SPI5
2 = UARTD
3 = ULPI
8.12.13 PINMUX_AUX_DAP3_FS_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S2 PM:
0 = I2S2
1 = SPI5
2 = DISPLAYA
3 = DISPLAYB
8.12.14 PINMUX_AUX_DAP3_DIN_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S2 PM:
0 = I2S2
1 = SPI5
2 = DISPLAYA
3 = DISPLAYB

8.12.15 PINMUX_AUX_DAP3_DOUT_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S2 PM:
0 = I2S2
1 = SPI5
2 = DISPLAYA
3 = RSVD3
8.12.16 PINMUX_AUX_DAP3_SCLK_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S2 PM:
0 = I2S2
1 = SPI5
2 = RSVD2
3 = DISPLAYB
8.12.17 PINMUX_AUX_GPIO_PV0_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 RSVD0 PM:
0 = RSVD0
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.18 PINMUX_AUX_GPIO_PV1_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 RSVD0 PM:
0 = RSVD0
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.19 PINMUX_AUX_SDMMC1_CLK_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 SDMMC1 PM:
0 = SDMMC1
1 = CLK12
2 = RSVD2
3 = RSVD3
8.12.20 PINMUX_AUX_SDMMC1_CMD_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SDMMC1 PM:
0 = SDMMC1
1 = SPDIF
2 = SPI4
3 = UARTA
8.12.21 PINMUX_AUX_SDMMC1_DAT3_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SDMMC1 PM:
0 = SDMMC1
1 = SPDIF
2 = SPI4
3 = UARTA


7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SDMMC1 PM:
0 = SDMMC1
1 = PWM0
2 = SPI4
3 = UARTA

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SDMMC1 PM:
0 = SDMMC1
1 = PWM1
2 = SPI4
3 = UARTA

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SDMMC1 PM:
0 = SDMMC1
1 = RSVD1
2 = SPI4
3 = UARTA
8.12.25 PINMUX_AUX_CLK2_OUT_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 EXTPERIPH2 PM:
0 = EXTPERIPH2
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.26 PINMUX_AUX_CLK2_REQ_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
4 NORMAL TRISTATE:
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 DAP PM:
0 = DAP
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.27 PINMUX_AUX_HDMI_INT_0
Offset: 0x3110 | Read/Write: R/W | Reset: 0x00000034 (0bxxxxxxxxxxxxxxxxxxxxxx0x0x110100)

9 0x0 RCV_SEL:
0 = NORMAL
1 = HIGH
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 RSVD0 PM:
0 = RSVD0
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.28 PINMUX_AUX_DDC_SCL_0

9 0x1 RCV_SEL:
0 = NORMAL
1 = HIGH
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2C4 PM:
0 = I2C4
1 = RSVD1
2 = RSVD2
3 = RSVD3

8.12.29 PINMUX_AUX_DDC_SDA_0

9 0x1 RCV_SEL:
0 = NORMAL
1 = HIGH
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2C4 PM:
0 = I2C4
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.30 PINMUX_AUX_UART2_RXD_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 IRDA PM:
0 = IRDA
1 = SPDIF
2 = UARTA
3 = SPI4
8.12.31 PINMUX_AUX_UART2_TXD_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE


5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 IRDA PM:
0 = IRDA
1 = SPDIF
2 = UARTA
3 = SPI4
8.12.32 PINMUX_AUX_UART2_RTS_N_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 UARTA PM:
0 = UARTA
1 = UARTB
2 = GMI
3 = SPI4
8.12.33 PINMUX_AUX_UART2_CTS_N_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 UARTA PM:
0 = UARTA
1 = UARTB
2 = GMI
3 = SPI4
8.12.34 PINMUX_AUX_UART3_TXD_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 UARTC PM:
0 = UARTC
1 = RSVD1
2 = GMI
3 = SPI4
8.12.35 PINMUX_AUX_UART3_RXD_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 UARTC PM:
0 = UARTC
1 = RSVD1
2 = GMI
3 = SPI4

8.12.36 PINMUX_AUX_UART3_CTS_N_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 UARTC PM:
0 = UARTC
1 = SDMMC1
2 = DTV
3 = GMI
8.12.37 PINMUX_AUX_UART3_RTS_N_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 UARTC PM:
0 = UARTC
1 = PWM0
2 = DTV
3 = GMI
8.12.38 PINMUX_AUX_GPIO_PU0_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 OWR PM:
0 = OWR
1 = UARTA
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 RSVD0 PM:
0 = RSVD0
1 = UARTA
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 RSVD0 PM:
0 = RSVD0
1 = UARTA
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 PWM0 PM:
0 = PWM0
1 = UARTA
2 = GMI
3 = DISPLAYB

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 PWM1 PM:
0 = PWM1
1 = UARTA
2 = GMI
3 = DISPLAYB


7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 PWM2 PM:
0 = PWM2
1 = UARTA
2 = GMI
3 = DISPLAYB

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 PWM3 PM:
0 = PWM3
1 = UARTA
2 = RSVD2
3 = GMI
8.12.45 PINMUX_AUX_GEN1_I2C_SDA_0
Offset: 0x31a0 | Read/Write: R/W | Reset: 0x00000070 (0bxxxxxxxxxxxxxxxxxxxxxxxx01110000)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
6 ENABLE OD:
0 = DISABLE
1 = ENABLE


5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2C1 PM:
0 = I2C1
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.46 PINMUX_AUX_GEN1_I2C_SCL_0
Offset: 0x31a4 | Read/Write: R/W | Reset: 0x00000070 (0bxxxxxxxxxxxxxxxxxxxxxxxx01110000)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
6 ENABLE OD:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2C1 PM:
0 = I2C1
1 = RSVD1
2 = RSVD2
3 = RSVD3
Offset: 0x31a8 | Read/Write: R/W | Reset: 0x00000034 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x110100)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE


3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S3 PM:
0 = I2S3
1 = GMI
2 = DTV
3 = RSVD3
Offset: 0x31ac | Read/Write: R/W | Reset: 0x00000034 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x110100)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S3 PM:
0 = I2S3
1 = GMI
2 = RSVD2
3 = RSVD3
Offset: 0x31b0 | Read/Write: R/W | Reset: 0x00000034 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x110100)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S3 PM:
0 = I2S3
1 = GMI
2 = DTV
3 = RSVD3


7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S3 PM:
0 = I2S3
1 = GMI
2 = RSVD2
3 = RSVD3
8.12.51 PINMUX_AUX_CLK3_OUT_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
4 NORMAL TRISTATE:
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 EXTPERIPH3 PM:
0 = EXTPERIPH3
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.52 PINMUX_AUX_CLK3_REQ_0
Offset: 0x31bc | Read/Write: R/W | Reset: 0x00000020 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x100000)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


4 NORMAL TRISTATE:
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 DEV3 PM:
0 = DEV3
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.53 PINMUX_AUX_GPIO_PC7_0
Offset: 0x31c0 | Read/Write: R/W | Reset: 0x0000003a (0bxxxxxxxxxxxxxxxxxxxxxxxx0x111010)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = RSVD1
2 = GMI
3 = GMI_ALT
8.12.54 PINMUX_AUX_GPIO_PI5_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 GMI PM:
0 = SDMMC2A
1 = RSVD1
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = TRACE
2 = GMI
3 = DTV
8.12.56 PINMUX_AUX_GPIO_PK0_0
Offset: 0x31cc | Read/Write: R/W | Reset: 0x0000003a (0bxxxxxxxxxxxxxxxxxxxxxxxx0x111010)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = SDMMC3
2 = GMI
3 = SOC

Offset: 0x31d0 | Read/Write: R/W | Reset: 0x00000036 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x110110)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC2A
1 = TRACE
2 = GMI
3 = RSVD3
8.12.58 PINMUX_AUX_GPIO_PJ0 _0
Offset: 0x31d4 | Read/Write: R/W | Reset: 0x0000003a (0bxxxxxxxxxxxxxxxxxxxxxxxx0x111010)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = RSVD1
2 = GMI
3 = USB
8.12.59 PINMUX_AUX_GPIO_PJ2_0
Offset: 0x31d8 | Read/Write: R/W | Reset: 0x0000003a (0bxxxxxxxxxxxxxxxxxxxxxxxx0x111010)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = RSVD1
2 = GMI
3 = SOC
Offset: 0x31dc | Read/Write: R/W | Reset: 0x0000003a (0bxxxxxxxxxxxxxxxxxxxxxxxx0x111010)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC2A
1 = TRACE
2 = GMI
3 = CCLA
Offset: 0x31e0 | Read/Write: R/W | Reset: 0x0000003a (0bxxxxxxxxxxxxxxxxxxxxxxxx0x111010)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 GMI PM:
0 = SDMMC2A
1 = RSVD1
2 = GMI
3 = GMI_ALT

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = RSVD1
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = RSVD1
2 = GMI
3 = SPI4

Offset: 0x31ec | Read/Write: R/W | Reset: 0x0000003a (0bxxxxxxxxxxxxxxxxxxxxxxxx0x111010)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = RSVD1
2 = GMI
3 = SDMMC2A
8.12.65 PINMUX_AUX_GPIO_PG0_0
Offset: 0x31f0 | Read/Write: R/W | Reset: 0x00000032 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x110010)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = RSVD1
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = RSVD1
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = TRACE
2 = GMI
3 = RSVD3
Offset: 0x31fc | Read/Write: R/W | Reset: 0x00000032 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x110010)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 GMI PM:
0 = RSVD0
1 = TRACE
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = TMDS
2 = GMI
3 = SPI4

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = RSVD1
2 = GMI
3 = SPI4


7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = RSVD1
2 = GMI
3 = SPI4

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = RSVD1
2 = GMI
3 = SPI4
8.12.73 PINMUX_AUX_GPIO_PH0_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = PWM0
1 = TRACE
2 = GMI
3 = DTV

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = PWM1
1 = TMDS
2 = GMI
3 = DISPLAYA

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 GMI PM:
0 = PWM2
1 = TMDS
2 = GMI
3 = CLDVFS

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = PWM3
1 = SPI4
2 = GMI
3 = CLDVFS
Offset: 0x3220 | Read/Write: R/W | Reset: 0x0000003a (0bxxxxxxxxxxxxxxxxxxxxxxxx0x111010)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC2A
1 = RSVD1
2 = GMI
3 = RSVD3


7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC2A
1 = RSVD1
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC2A
1 = TRACE
2 = GMI
3 = DTV
Offset: 0x322c | Read/Write: R/W | Reset: 0x0000003a (0bxxxxxxxxxxxxxxxxxxxxxxxx0x111010)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC2A
1 = TRACE
2 = GMI
3 = DTV
8.12.81 PINMUX_AUX_GPIO_PJ7_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = UARTD
1 = RSVD1
2 = GMI
3 = GMI_ALT
8.12.82 PINMUX_AUX_GPIO_PB0_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 GMI PM:
0 = UARTD
1 = RSVD1
2 = GMI
3 = RSVD3
8.12.83 PINMUX_AUX_GPIO_PB1_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = UARTD
1 = RSVD1
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = UARTD
1 = RSVD1
2 = GMI
3 = RSVD3


7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = RSVD1
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = RSVD0
1 = RSVD1
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC2A
1 = TRACE
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SPI4
1 = TRACE
2 = GMI
3 = DISPLAYA
8.12.89 PINMUX_AUX_GEN2_I2C_SCL_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
6 ENABLE OD:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 I2C2 PM:
0 = I2C2
1 = RSVD1
2 = GMI
3 = RSVD3
8.12.90 PINMUX_AUX_GEN2_I2C_SDA_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
6 ENABLE OD:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2C2 PM:
0 = I2C2
1 = RSVD1
2 = GMI
3 = RSVD3
Offset: 0x3258 | Read/Write: R/W | Reset: 0x00000136 (0bxxxxxxxxxxxxxxxxxxxxxxx10x110110)

8 IORESET IO_RESET:
0 = NORMAL
1 = IORESET
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC4
1 = RSVD1
2 = GMI
3 = RSVD3

Offset: 0x325c | Read/Write: R/W | Reset: 0x0000013a (0bxxxxxxxxxxxxxxxxxxxxxxx10x111010)

8 IORESET IO_RESET:
0 = NORMAL
1 = IORESET
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC4
1 = RSVD1
2 = GMI
3 = RSVD3
Offset: 0x3260 | Read/Write: R/W | Reset: 0x0000013a (0bxxxxxxxxxxxxxxxxxxxxxxx10x111010)

8 IORESET IO_RESET:
0 = NORMAL
1 = IORESET
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC4
1 = SPI3
2 = GMI
3 = RSVD3


8 IORESET IO_RESET:
0 = NORMAL
1 = IORESET
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC4
1 = SPI3
2 = GMI
3 = RSVD3

8 IORESET IO_RESET:
0 = NORMAL
1 = IORESET
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC4
1 = SPI3
2 = GMI
3 = RSVD3


8 IORESET IO_RESET:
0 = NORMAL
1 = IORESET
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC4
1 = SPI3
2 = GMI
3 = RSVD3

8 IORESET IO_RESET:
0 = NORMAL
1 = IORESET
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC4
1 = SPI3
2 = GMI
3 = RSVD3


8 IORESET IO_RESET:
0 = NORMAL
1 = IORESET
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 RSVD2 PM:
0 = SDMMC4
1 = SPI3
2 = RSVD2
3 = RSVD3

8 IORESET IO_RESET:
0 = NORMAL
1 = IORESET
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC4
1 = SPI3
2 = GMI
3 = RSVD3


8 IORESET IO_RESET:
0 = NORMAL
1 = IORESET
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC4
1 = RSVD1
2 = GMI
3 = RSVD3
8.12.101 PINMUX_AUX_CAM_MCLK_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 VI_ALT3 PM:
0 = VI
1 = VI_ALT1
2 = VI_ALT3
3 = SDMMC2B
8.12.102 PINMUX_AUX_GPIO_PCC1_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE


5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S4 PM:
0 = I2S4
1 = RSVD1
2 = RSVD2
3 = SDMMC2B
8.12.103 PINMUX_AUX_GPIO_PBB0_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 VGP6 PM:
0 = VGP6
1 = VIMCLK2
2 = SDMMC2B
3 = VIMCLK2_ALT
8.12.104 PINMUX_AUX_CAM_I2C_SCL_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
6 ENABLE OD:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE


3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 VGP1 PM:
0 = VGP1
1 = I2C3
2 = RSVD2
3 = SDMMC2B
8.12.105 PINMUX_AUX_CAM_I2C_SDA_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
6 ENABLE OD:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 VGP2 PM:
0 = VGP2
1 = I2C3
2 = RSVD2
3 = SDMMC2B

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 VGP3 PM:
0 = VGP3
1 = DISPLAYA
2 = DISPLAYB
3 = SDMMC2B

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 VGP4 PM:
0 = VGP4
1 = DISPLAYA
2 = DISPLAYB
3 = SDMMC2B

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 VGP5 PM:
0 = VGP5
1 = DISPLAYA
2 = RSVD2
3 = SDMMC2B


7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S4 PM:
0 = I2S4
1 = RSVD1
2 = DISPLAYB
3 = SDMMC2B

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S4 PM:
0 = I2S4
1 = RSVD1
2 = RSVD2
3 = SDMMC2B
8.12.111 PINMUX_AUX_GPIO_PCC2_0
Offset: 0x32ac | Read/Write: R/W | Reset: 0x00000038 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x111000)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S4 PM:
0 = I2S4
1 = RSVD1
2 = SDMMC3
3 = SDMMC2B
8.12.112 PINMUX_AUX_JTAG_RTCK_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
4 NORMAL TRISTATE:
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 RTCK PM:
0 = RTCK
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.113 PINMUX_AUX_PWR_I2C_SCL_0
Offset: 0x32b4 | Read/Write: R/W | Reset: 0x00000070 (0bxxxxxxxxxxxxxxxxxxxxxxxx01110000)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
6 ENABLE OD:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 I2CPWR PM:
0 = I2CPWR
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.114 PINMUX_AUX_PWR_I2C_SDA_0
Offset: 0x32b8 | Read/Write: R/W | Reset: 0x00000070 (0bxxxxxxxxxxxxxxxxxxxxxxxx01110000)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
6 ENABLE OD:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2CPWR PM:
0 = I2CPWR
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.115 PINMUX_AUX_KB_ROW0_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = RSVD2
3 = RSVD3

Offset: 0x32c0 | Read/Write: R/W | Reset: 0x00000034 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x110100)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = RSVD2
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = RSVD2
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


4 NORMAL TRISTATE:
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SYS PM:
0 = KBC
1 = DISPLAYA
2 = SYS
3 = DISPLAYB
Offset: 0x32cc | Read/Write: R/W | Reset: 0x00000034 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x110100)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = DISPLAYA
2 = RSVD2
3 = DISPLAYB

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 KBC PM:
0 = KBC
1 = DISPLAYA
2 = RSVD2
3 = DISPLAYB

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = DISPLAYA
2 = DISPLAYA_ALT
3 = DISPLAYB

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = CLDVFS
3 = UARTA

Offset: 0x32dc | Read/Write: R/W | Reset: 0x00000034 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x110100)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = CLDVFS
3 = UARTA
Offset: 0x32e0 | Read/Write: R/W | Reset: 0x00000034 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x110100)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = RSVD2
3 = UARTA

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = RSVD2
3 = UARTA
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = RSVD2
3 = IRDA
Offset: 0x32ec | Read/Write: R/W | Reset: 0x00000034 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x110100)
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = RSVD2


3 = IRDA
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = SPI2
3 = RSVD3
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = SPI2
3 = RSVD3
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE


5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = SOC
2 = RSVD2
3 = RSVD3
8.12.131 PINMUX_AUX_KB_COL0_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = SPI2
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD


1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = SPI2
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = SPI2
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = DISPLAYA
2 = PWM2
3 = UARTA


7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = OWR
2 = SDMMC3
3 = UARTA

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = SDMMC3
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = SPI2
3 = UARTD

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = SPI2
3 = UARTD
8.12.139 PINMUX_AUX_CLK_32K_OUT_0
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD

1:0 BLINK PM:

0 = BLINK
1 = SOC
2 = RSVD2
3 = RSVD3
8.12.140 PINMUX_AUX_CORE_PWR_REQ_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
4 NORMAL TRISTATE:
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 PWRON PM:
0 = PWRON
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.141 PINMUX_AUX_CPU_PWR_REQ_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
4 NORMAL TRISTATE:
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 CPU PM:
0 = CPU
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.142 PINMUX_AUX_PWR_INT_N_0


7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
4 NORMAL TRISTATE:
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 PMI PM:
0 = PMI
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.143 PINMUX_AUX_CLK_32K_IN_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
4 NORMAL TRISTATE:
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 CLK PM:
0 = CLK
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.144 PINMUX_AUX_OWR_0

9 0x0 RCV_SEL:
0 = NORMAL
1 = HIGH
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL


1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 OWR PM:
0 = OWR
1 = RSVD1
2 = RSVD2
3 = RSVD3
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S0 PM:
0 = I2S0
1 = HDA
2 = GMI
3 = RSVD3
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S0 PM:
0 = I2S0
1 = HDA
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S0 PM:
0 = I2S0
1 = HDA
2 = GMI
3 = SATA

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S0 PM:
0 = I2S0
1 = HDA
2 = GMI
3 = RSVD3
8.12.149 PINMUX_AUX_DAP_MCLK1_REQ_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


4 NORMAL TRISTATE:
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 DAP PM:
0 = DAP
1 = DAP1
2 = SATA
3 = RSVD3
8.12.150 PINMUX_AUX_DAP_MCLK1_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 EXTPERIPH1 PM:
0 = EXTPERIPH1
1 = DAP2
2 = RSVD2
3 = RSVD3
8.12.151 PINMUX_AUX_SPDIF_IN_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPDIF PM:
0 = SPDIF
1 = RSVD1


2 = RSVD2
3 = I2C3
8.12.152 PINMUX_AUX_SPDIF_OUT_0
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPDIF PM:
0 = SPDIF
1 = RSVD1
2 = RSVD2
3 = I2C3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S1 PM:
0 = I2S1
1 = HDA
2 = GMI
3 = RSVD3


7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S1 PM:
0 = I2S1
1 = HDA
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S1 PM:
0 = I2S1
1 = HDA
2 = GMI
3 = RSVD3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE


0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 I2S1 PM:
0 = I2S1
1 = HDA
2 = GMI
3 = RSVD3
8.12.157 PINMUX_AUX_DVFS_PWM_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI6 PM:
0 = SPI6
1 = CLDVFS
2 = GMI
3 = RSVD3
8.12.158 PINMUX_AUX_GPIO_X1_AUD_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI6 PM:
0 = SPI6
1 = RSVD1


2 = GMI
3 = RSVD3
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI6 PM:
0 = SPI6
1 = SPI1
2 = GMI
3 = RSVD3
8.12.160 PINMUX_AUX_DVFS_CLK_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI6 PM:
0 = SPI6
1 = CLDVFS
2 = GMI
3 = RSVD3


7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI1 PM:
0 = GMI
1 = SPI1
2 = SPI2
3 = DAP2

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI1 PM:
0 = GMI
1 = SPI1
2 = SPI2
3 = RSVD3
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE

0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI1 PM:
0 = SPI6
1 = SPI1
2 = SPI2
3 = GMI

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI1 PM:
0 = RSVD0
1 = SPI1
2 = SPI2
3 = RSVD3
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD

1:0 SDMMC3 PM:

0 = SDMMC3
1 = RSVD1
2 = RSVD2
3 = SPI3
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SDMMC3 PM:
0 = SDMMC3
1 = PWM3
2 = UARTA
3 = SPI3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SDMMC3 PM:
0 = SDMMC3
1 = RSVD1
2 = RSVD2
3 = SPI3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SDMMC3 PM:
0 = SDMMC3
1 = PWM2
2 = UARTA
3 = SPI3

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SDMMC3 PM:
0 = SDMMC3
1 = PWM1
2 = DISPLAYA
3 = SPI3
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE

0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SDMMC3 PM:
0 = SDMMC3
1 = PWM0
2 = DISPLAYB
3 = SPI3
8.12.171 PINMUX_AUX_PEX_L0_RST_N_0
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 PE0 PM:
0 = PE0
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.172 PINMUX_AUX_PEX_L0_CLKREQ_N_0
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 PE0 PM:
0 = PE0
1 = RSVD1
2 = RSVD2


3 = RSVD3
8.12.173 PINMUX_AUX_PEX_WAKE_N_0
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 PE PM:
0 = PE
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.174 PINMUX_AUX_PEX_L1_RST_N_0
Offset: 0x33cc | Read/Write: R/W | Reset: 0x00000030 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x110000)
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 PE1 PM:
0 = PE1
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.175 PINMUX_AUX_PEX_L1_CLKREQ_N_0
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE


1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 PE1 PM:
0 = PE1
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.176 PINMUX_AUX_HDMI_CEC_0
Offset: 0x33e0 | Read/Write: R/W | Reset: 0x00000070 (0bxxxxxxxxxxxxxxxxxxxxxxxx01110000)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
6 ENABLE OD:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 CEC PM:
0 = CEC
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.177 PINMUX_AUX_SDMMC1_WP_N_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE


3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SDMMC1 PM:
0 = SDMMC1
1 = CLK12
2 = SPI4
3 = UARTA
8.12.178 PINMUX_AUX_SDMMC3_CD_N_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SDMMC3 PM:
0 = SDMMC3
1 = OWR
2 = RSVD2
3 = RSVD3
8.12.179 PINMUX_AUX_GPIO_W2_AUD_0
Offset: 0x33ec | Read/Write: R/W | Reset: 0x00000039 (0bxxxxxxxxxxxxxxxxxxxxxxxx0x111001)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 RSVD1 PM:
0 = SPI6
1 = RSVD1
2 = SPI2
3 = I2C1

8.12.180 PINMUX_AUX_GPIO_W3_AUD_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_UP PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SPI1 PM:
0 = SPI6
1 = SPI1
2 = SPI2
3 = I2C1
8.12.181 PINMUX_AUX_USB_VBUS_EN0_0
Offset: 0x33f4 | Read/Write: R/W | Reset: 0x00000060 (0bxxxxxxxxxxxxxxxxxxxxxxxx01100000)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
6 ENABLE OD:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
4 NORMAL TRISTATE:
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 USB PM:
0 = USB
1 = RSVD1
2 = RSVD2
3 = RSVD3
Offset: 0x33f8 | Read/Write: R/W | Reset: 0x00000060 (0bxxxxxxxxxxxxxxxxxxxxxxxx01100000)

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE


6 ENABLE OD:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
4 NORMAL TRISTATE:
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 USB PM:
0 = USB
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.183 PINMUX_AUX_SDMMC3_CLK_LB_IN_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
4 NORMAL TRISTATE:
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SDMMC3 PM:
0 = SDMMC3
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.184 PINMUX_AUX_SDMMC3_CLK_LB_OUT_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL


1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SDMMC3 PM:
0 = SDMMC3
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.185 PINMUX_AUX_ GMI_CLK_LB_0


7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 GMI PM:
0 = SDMMC2A
1 = RSVD1
2 = GMI
3 = RSVD3
8.12.186 PINMUX_AUX_RESET_OUT_N_0

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
4 NORMAL TRISTATE:
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 RSVD0 PM:
0 = RSVD0
1 = RSVD1
2 = RSVD2
3 = RESET_OUT_N

7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = RSVD2
3 = UARTC
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 KBC PM:
0 = KBC
1 = RSVD1
2 = RSVD2
3 = UARTC
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
6 ENABLE OD:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
4 NORMAL TRISTATE:
0 = NORMAL
1 = TRISTATE


3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 USB PM:
0 = USB
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.190 PINMUX_AUX_GPIO_PFF2_0
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
6 ENABLE OD:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 SATA PM:
0 = SATA
1 = RSVD1
2 = RSVD2
3 = RSVD3
8.12.191 PINMUX_AUX_DP_HPD_0
7 DISABLE LOCK:
0 = DISABLE
1 = ENABLE
5 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
0 = NORMAL
1 = TRISTATE
3:2 NORMAL PUPD:
0 = NORMAL
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
1:0 DP PM:
0 = DP
1 = RSVD1
2 = RSVD2
3 = RSVD3


9.0 POWER MANAGEMENT CONTROLLER
9.1 Register Definitions for the PMC

To speed up operation, the PMC register file operates in the local peripheral interface bus domain (APB) rather than in the 32
kHz clock domain used for PMC processing.
Registers in the PMC control entering/exiting Deep Sleep/Suspend mode, power detect, and I/O power functions. They also
control CORE_PWR_REQ, SYS_CLK_REQ, and LED_BLINK pins.
The following registers should be programmed/read for different power events in order for PMC to function properly.
IMPORTANT: NO_IO_POWER REGISTER (APBDEV_PMC_NO_IOPOWER_0)

Before an I/O power rail is turned off, ramping up, or no longer used and ready to
turn off, the corresponding bit in this register should be set to 1.
The bit only needs to be turned on when the I/O power rail is stable and you are
ready to enable some interface on the I/O power rail.
BEFORE/ON ENTERING DEEP SLEEP MODE

 PMC Control Register (bits PWRREQ_POLARITY, PWRREQ_OE, SYSCLK_POLARITY,SYSCLK_OE,
LATCHWAKE_EN)
 WAKE_MASK
 WAKE_LVL
 DPD_PADS_ORIDE (for required overrides)
 PWRGOOD_TIMER
 DPD_SAMPLE
 DPD_ENABLE
AFTER WAKE-UP FROM DEEP SLEEP

 WAKE_STATUS
 SW_WAKE_STATUS
 DPD_ENABLE
 PMC Control Register (bit LATCHWAKE_EN)
BEFORE/ON POWERING DOWN PARTITIONS

 PWRGATE_STATUS
 PWRGATE_TIMER_OFF (for power down)
 PWRGATE_TIMER_ON (for power up). This has been deprecated.
 PWRGATE_TOGGLE
 REMOVE_CLAMPING_CMD (for power up)
FOR POWER DETECT SEQUENCE

 PWR_DET
 PWR_DET_LATCH

Power Management Controller
FOR BLINK
 BLINK_TIMER
 PMC Control Register (bit BLINK_EN)
 DPD_PADS_ORIDE (for blink field)
All other operations require single register access.
9.2 PMC Registers

9.2.1 APBDEV_PMC_CNTRL_0
This register controls the clock to the RTC, and the reset to the CAR and RTC. It also manages polarity and output enable of
the sys_clk_req and core_pwr_req pins. At reset, both are disabled since the PMIC properties are unknown.
Auxiliary functions include enabling of blinking functions, side-effect option, and software wake-up latching.
The LP0 entry is to be triggered by the PMC side-effect option. Software needs to configure the PMC for the side-effect option
before triggering the power off of last CPU. If the side-effect option is set, then the PMC would initiate LP0 in the following
cases:
 A power-off request for the CPU rail will lead to CPU rail power-off followed by LP0 entry.
 A power-gating request for cluster1 non-CPU (i.e., C1NC) will lead to power-gating of the C1NC followed by LP0
entry
PMC Control Register

Offset: 0x0 │ Read/Write: R/W │ Reset: 0x00010a00 (0bxxxxxxxxxx0000010000101000000000)
CPUPWRGOOD_SEL: CPUPWRGOOD pin select. There are 4 potential source pins

(soc_therm_oc{1,2,3,4}) used as PWRGOOD. This field needs to be programmed (at
boot) based on which pin is used as PWRGOOD.
21:20 0x0 0 = SOC_THERM_OC1 (default)
1 = SOC_THERM_OC2
2 = SOC_THERM_OC3
3 = SOC_THERM_OC4
CPUPWRGOOD_EN:CPU_PWR_GOOD (From PMIC to PMC) signal is enabled.

19 0x0 0 = DISABLE
1 = ENABLE
18 0x0 FUSE_OVERRIDE: Fuse override

0 = DISABLE
1 = ENABLE
17 0x0 INTR_POLARITY: Inverts INTR polarity

0 = DISABLE
1 = ENABLE
16 0x1 CPUPWRREQ_OE: Power request output enable. Resets to tri-state

0 = DISABLE
1 = ENABLE
15 0x0 CPUPWRREQ_POLARITY: Inverts power request polarity

0 = NORMAL
1 = INVERT

14 0x0 SIDE_EFFECT_LP0: When set, causes the side effect of entering LP0 after powering
down the CPU
0 = DISABLE
1 = ENABLE
13 0x0 AOINIT: AO initialized purely software diagnostic and interpretation

0 = NOTDONE
1 = DONE
12 0x0 PWRGATE_DIS: Disable power gating - global override, will override function of
PWRGATE_TOGGLE register. All partitions will stay enabled.
Note: Only write to this bit when CRAIL is on.
0 = DISABLE
1 = ENABLE
11 0x1 SYSCLK_OE: Enables output of system enable clock - works only if the SYS_CLK
field in DPD_PADS_ORIDE is set to 1.
0 = DISABLE
1 = ENABLE
10 0x0 SYSCLK_POLARITY: Inverts SYS_CLK_REQ enable polarity

0 = NORMAL
1 = INVERT
9 0x1 PWRREQ_OE: CORE_PWR_REQ output enable. Resets to tristate

0 = DISABLE
1 = ENABLE
8 0x0 PWRREQ_POLARITY: Inverts CORE_PWR_REQ polarity

0 = NORMAL
1 = INVERT
7 0x0 BLINK_EN: Enables blinking counter and blink output works only if the BLINK field in
DPD_PADS_ORIDE is set to 1.
0 = DISABLE
1 = ENABLE
6 0x0 GLITCHDET_DIS: Reserved
5 0x0 LATCHWAKE_EN: Enables latching wakeup events - stops latching on transition from
1 to 0 (sequence - set to 1,set to 0)
0 = DISABLE
1 = ENABLE
4 0x0 MAIN_RST: Resets everything but scratch 0 and reset status.

0 = DISABLE
1 = ENABLE
3 0x0 KBC_RST: Reserved
2 0x0 RTC_RST: Software reset to RTC.

0 = DISABLE
1 = ENABLE
1 0x0 RTC_CLK_DIS: Disable 32 KHz clock to RTC.

0 = DISABLE
1 = ENABLE
0 0x0 KBC_CLK_DIS: Reserved

9.2.2 APBDEV_PMC_SEC_DISABLE_0
On separate reset (same as CAR), this register disables access (read/write to secure scratch registers). Once writes are
disabled, secure registers cannot be written until power on reset or reset when exiting Deep Sleep mode.
Once reads are disabled, reads from scratch registers will return 0 until power on reset or reset when exiting Deep Sleep
mode.
Single register can be disabled for reads/writes; bits 0 and 1 have an overwrite function.
Secure Register Disable

Offset: 0x4 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxx0000000000000000000000)
TSC_NS_WRITE: Non-secure (i.e., non-TZ) write-disable for the PMC_TSC_MULT

register and the PMC_DPD_ENABLE[TSC_MULT_EN] register-bit.
0: Non-secure or secure can write.
1: Only secure can write.
21 0x0
This bit is write-once only. Once it is set to '1', it remains '1' until reset by LP0 or
system reset.
0 = OFF
1 = ON
AMAP_WRITE: Disable writes to the PMC_GLB_AMAP_CFG register

20 0x0 0 = OFF
1 = ON
19 0x0 READ7: Disable reads from secure register 7

0 = OFF
1 = ON
18 0x0 WRITE7: Disable writes to secure register 7

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON


0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON
3:2 0x0 NOT_USED: legacy - redundant - not used
1 0x0 READ: Disable reads from all secure registers

0 = OFF 1 = ON
0 0x0 WRITE: Disable writes to all secure registers

0 = OFF
1 = ON
9.2.3 APBDEV_PMC_PMC_SWRST_0
Reset only by the POR cell; sets itself back to inactive after 2 clock cycles. Only used for emergency debugging purposes; not
to be used in any functional mode.
Note: Defunct. Kept only for binary code compatibility only. Will not do anything
Register Write which Resets PMC Only

0 0x0 RST: Software reset to the PMC only

0 = DISABLE
1 = ENABLE
9.2.4 APBDEV_PMC_WAKE_MASK_0
The APBDEV_PMC_WAKE registers handle wake events whose number is less than or equal to 32. For wake events whose
number is greater than 32, refer to the APBDEV_PMC_WAKE2 registers below.
Current pin assignments wake_mask, wake_status, sw_wake_status, and wake levels:

 WAKE_STATUS[0] = ulpi_data4 (wake event 0)

 WAKE_STATUS[1] = gp3_pv[1] (wake event 1)
 WAKE_STATUS[3] = sdmmc3_dat1 (wake event 3)
 WAKE_STATUS[4] = hdmi_int (wake event 4)
 WAKE_STATUS[6] = gp3_pu[5] (wake event 6)
 WAKE_STATUS[7] = gp3_pu[6] (wake event 7)
 WAKE_STATUS[8] = gpio_pc[7] (wake event 8)
 WAKE_STATUS[9] = kb_row10 (wake event 9)
 WAKE_STATUS[11] = gpio_w3_aud (wake event 11)
 WAKE_STATUS[12] = gpio_w2_aud (wake event 12)
 WAKE_STATUS[14] = pe_wake_n (wake event 14)
 WAKE_STATUS[15] = gpio_pj[2] (wake event 15)
 WAKE_STATUS[16] = rtc_irq (wake event 16)
 WAKE_STATUS[17] = kbc_interrupt (wake event 17)
 WAKE_STATUS[18] = pwr_int (wake event 18)
 WAKE_STATUS[19] = usb1_vbus (wake event 19)
 WAKE_STATUS[20] = usb_vbus_wakeup[1] (wake event 20)
 WAKE_STATUS[23] = gpio_pi[5] (wake event 23)
 WAKE_STATUS[24] = gp3_pv[0] (wake event 24)
 WAKE_STATUS[30] = dap1_dout (wake event 30)
This register masks which event can cause a wake-up from Deep Sleep mode. It has to be set up before entering Deep Sleep
mode. It works in conjunction with the WAKE_LVL register.
Only enabled events at the proper wake_lvl will cause exit from Deep Sleep mode.
PMC Wake-up Event Mask

Offset: 0xc │ Read/Write: R/W │ Reset: 0x00000000 (0b00000000000000000000000000000000)
31 0x0 RESET_N: External reset wake enable

0 = DISABLE
1 = ENABLE
30:23 0x0 EVENT_RES:

0 = DISABLE
1 = ENABLE

22:19 0x0 USB_EVENT:

0 = ACTIVE_LOW
1 = ACTIVE_HIGH
18 0x0 PWR_INT_N: PWR_INT_N wake enable

0 = DISABLE
1 = ENABLE
17 0x0 KBC: KBC wake enable

0 = DISABLE
1 = ENABLE
16 0x0 RTC: RTC wake enable

0 = DISABLE
1 = ENABLE
15:0 0x0 EVENT: pin 0-15 wake enable

0 = DISABLE
1 = ENABLE
9.2.5 APBDEV_PMC_WAKE_LVL_0
This register sets the active level for the wake event. It will cause an exit from Deep Sleep mode if the input signal level
matches the level set in this register and WAKE_MASK is set for the event to 1.
PMC Wake Level

Offset: 0x10 │ Read/Write: R/W │ Reset: 0x7f9fffff (0b01111111100111111111111111111111)
31 0x0 RESET_N: External reset wake level (low active)

0 = ACTIVE_LOW
1 = ACTIVE_HIGH
30:23 0xff EVENT_RES:

0 = ACTIVE_LOW
1 = ACTIVE_HIGH
22:19 0x3 USB_EVENT:

0 = ACTIVE_LOW
1 = ACTIVE_HIGH
18 0x1 PWR_INT_N: Power interrupt - permanently tied to bit 18

0 = ACTIVE_LOW
1 = ACTIVE_HIGH
17 0x1 KBC: KBC wake level

0 = ACTIVE_LOW
1 = ACTIVE_HIGH
16 0x1 RTC: RTC wake level

0 = ACTIVE_LOW
1 = ACTIVE_HIGH
15:0 0xffff EVENT: Pin 0-15 wake level

0 = ACTIVE_LOW
1 = ACTIVE_HIGH

9.2.6 APBDEV_PMC_WAKE_STATUS_0
This register stores the status of the wake events. The event will be set if the level matches and is not masked.
A write will reset the set wake event.
PMC Wake Status

31 0x0 RESET_N: external reset

0 = NOT_SET
1 = SET

0 = NOT_SET
1 = SET
22:19 0x0 USB_EVENT: USB wake events

0 = NOT_SET
1 = SET
18 0x0 PWR_INT_N: power interrupt

0 = NOT_SET
1 = SET
17 0x0 KBC: KBC wake

0 = NOT_SET
1 = SET
16 0x0 RTC: RTC wake

0 = NOT_SET
1 = SET
15:0 0x0 EVENT: pin 0-15 wake

0 = NOT_SET
1 = SET
9.2.7 APBDEV_PMC_SW_WAKE_STATUS_0
This register stores status of the wake events. Latching of the events in software wake status is enabled by the PMC_CNTRL
register bit LATCHWAKE_EN.
Latching will stop at a 1-to-0 transition on this bit. An event will be set if the level matches. Masking does not affect this
register. A write will reset the set wake events.
PMC Software Wake Status

31 0x0 RESET_N: External reset

0 = NOT_SET
1 = SET


0 = NOT_SET
1 = SET
22:19 0x0 USB_EVENT: USB wake events

0 = NOT_SET
1 = SET
18 0x0 PWR_INT: Power interrupt

0 = NOT_SET
1 = SET
17 0x0 KBC: KBC wake

0 = DISABLE
1 = ENABLE
16 0x0 RTC: RTC wake

0 = DISABLE
1 = ENABLE
15:0 0x0 EVENT: Pin 0-15 wake

0 = DISABLE
1 = ENABLE
9.2.8 APBDEV_PMC_DPD_PADS_ORIDE_0
This register enables overriding values from pinmux with values driven by the KBC (keyboard) or the PMC (sys_clk_req, blink).
If a bit is set to 1, the associated I/O will drive the direct value from the KBC or PMC, not the pinmux value. During Deep Sleep
mode, the pads with the bit set to 1 will not be in Deep Power Down mode. It will not drive data from mini pad macros stored
during sample cycle, but direct data from the KBC or PMC.
Note: This register has to be set before entering Deep Sleep mode.
DPD Pads Override

KBC_ROW16: Override DPD idle state with row 16 output

31 0x0 0 = DISABLE
1 = ENABLE

30 0x0 0 = DISABLE
1 = ENABLE

29 0x0 0 = DISABLE
1 = ENABLE

28 0x0 0 = DISABLE
1 = ENABLE

27 0x0 0 = DISABLE
1 = ENABLE


26 0x0 0 = DISABLE
1 = ENABLE
25 0x0 KBC_ROW10: Override DPD idle state with row 10 output

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE
21 0x1 SYS_CLK_REQ: Override DPD idle state with column with SYS_CLK_REQ output
0 = DISABLE
1 = ENABLE
20 0x0 BLINK: Override DPD idle state with blink output

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE
18 0x0 KBC_ROW5: Override DPD idle state of the gp3_pq[7] pad

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE
12 0x0 KBC_COL12: Override DPD idle state with row 17 output

0 = DISABLE
1 = ENABLE

11 0x0 KBC_COL11: Override DPD idle state of the gp3_pq[0] pad

0 = DISABLE
1 = ENABLE
10 0x0 KBC_COL10: Override DPD idle state of the gp3_ps[2] pad

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE
7 0x0 KBC_COL7: Override DPD idle state of the gp3_pr[7] pad

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE
9.2.9 APBDEV_PMC_DPD_SAMPLE_0
Setting this register will trigger sampling pads data and direction in which the pad will be driven during Deep Sleep mode.
Before writing to this register, all interfaces going to pads must be set to the ideal "idle" mode, which is expected to be driven
by pads when the Tegra K1 chip enters Deep Sleep.
DPS Power Down Sample has to precede Deep Power Down Enable write. The DPD sample should not be deasserted until
the transition from Deep Sleep to WB0.
This affects only for MPIO pads.

Note: Only one sample signal exists to perform sampling while entering DPD mode. Thus all interfaces are sampled
at the same time. The sequence of multiple DPD groups requires keeping all interfaces (already in DPD mode)
in idle.
Deep Power Down Sample

0 0x0 ON: Sets the sampling of pads value

0 = DISABLE
1 = ENABLE
9.2.10 APBDEV_PMC_DPD_ENABLE_0
Setting this register will trigger entering Deep Sleep state. It must be preceded by a DPD_SAMPLE write.
Will cause request for shutting down the system clock and the core req power. Puts the PLLs and I/Os in Deep Power Down
mode. Will cut off (clamp) all signals going from core power to AO and pads.
If none of the wake-up events is set, only power-on reset can re-enable access to the chip.
After servicing of the wake-up event is completed, the register should be set back to 0 to complete a Deep Sleep cycle.
Deep Power Down Enable

Offset: 0x24 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00)
TSC_MULT_EN: TSC multiplier enable.

0: DISABLE (i.e., counter runs at oscillator clock and increments by 1 every clock
cycle).
1 0x0 1: ENABLE (i.e., counter runs at 32 kHz and increments by TSC_MULT_VALUE every
clock cycle).
0 = DISABLE
1 = ENABLE
0 0x0 ON: Sets sampling of pads value

0 = DISABLE
1 = ENABLE
9.2.11 APBDEV_PMC_PWRGATE_TIMER_OFF_0
Specifies the number of APB cycles after which the rail line goes off (turns the power to part of power-gated partition). Each
rail controls part of the powered partition. This register should be set before the write to Power Gate Toggle. Shared between
all power partitions.
Power Gate Timer Off Register

Offset: 0x28 │ Read/Write: R/W │ Reset: 0xedcba987 (0b11101101110010111010100110000111)
31:28 0xe RAIL7: Timer value for rail 7
27:24 0xd RAIL6: Timer value for rail 6

23:20 0xc RAIL5: Timer value for rail 5
19:16 0xb RAIL4: Timer value for rail 4
15:12 0xa RAIL3: Timer value for rail 3
11:8 0x9 RAIL2: Timer value for rail 2
9.2.12 APBDEV_PMC_CLAMP_STATUS_0
This register is kept for backward code compatibility; the timer is based on PWRGATE_TIMER_OFF only.
Offset: 0x2c │ Read/Write: RO │ Reset: 0x0XXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
IRAM: Clamp status of IRAM partition

24 X 0 = DISABLE
1 = ENABLE
VIC: Clamp status of VIC partition

23 X 0 = DISABLE
1 = ENABLE
22 X XUSBC: Clamp status of XUSBC partition

0 = DISABLE
1 = ENABLE
21 X XUSBB: Clamp status of XUSBB partition

0 = DISABLE
1 = ENABLE
20 X XUSBA: Clamp status of XUSBA partition

0 = DISABLE
1 = ENABLE
19 X DISB: Clamp status of DISB partition

0 = DISABLE
1 = ENABLE
18 X DIS: Clamp status of DIS partition

0 = DISABLE
1 = ENABLE
SOR: Clamp status of SOR partition

17 X 0 = DISABLE
1 = ENABLE
16 X C1NC: Clamp status of cluster1 nENABLE CPU partition

0 = DISABLE
1 = ENABLE
15 X C0NC: Clamp status of cluster0 nENABLE CPU partition

0 = DISABLE
1 = ENABLE
14 X CE0: Clamp status of CE0 partition

0 = DISABLE
1 = ENABLE
12 X CELP: Clamp status of CELP partition

0 = DISABLE
1 = ENABLE


0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE
SAX: Clamp status of SAX partition

8 X 0 = DISABLE
1 = ENABLE
7 X HEG: Clamp status of HEG partition

0 = DISABLE
1 = ENABLE
6 X MPE: Clamp status of MPE partition

0 = DISABLE
1 = ENABLE
VDE: Clamp status of VDE partition

4 X 0 = DISABLE
1 = ENABLE
3 X PCX: Clamp status of PCX partition

0 = DISABLE
1 = ENABLE
2 X VE: Clamp status of VE partition

0 = DISABLE
1 = ENABLE
1 X TD: Clamp status of TD partition

0 = DISABLE
1 = ENABLE
0 X CRAIL: Clamp status of CPU Rail

0 = DISABLE
1 = ENABLE
9.2.13 APBDEV_PMC_PWRGATE_TOGGLE_0
Write to this register will turn power on/off to the specified power-gated partition. Only one partition is turned on/off at a time.
PWRGATE_STATUS should be read to determine the state of the partition before writing to this register.
Turning the partition off will cause automatic clamping of all signals generated by the power-gated partition being turned off.
Before the partition is turned off, all clocks to the partition should be stopped, and the reset to the partition should be asserted.
Turning the partition on will not remove clamping. Clamping is removed only after a REMOVE_CLAMPING_CMD write.
The user must allow a minimum 20 APB clock cycles between consecutive partition Power-Gate Toggle requests.
The role of the START bit has changed from prior Tegra devices. The START bit is cleared by hardware when the PMC
accepts the request to power-gate or unpower-gate the partition. So in order to power-gate/unpower-gate a partition, software
needs to do the following:
 Check to see if the partition is already in the correct state, by looking at the PWRGATE_STATUS register.
 If the partition is not in the correct state, software reads the PWRGATE_TOGGLE register to see if the START bit is
0.
 If the START bit is not 0, software polls until the start bit is set to 0.

 Then program the PWRGATE_TOGGLE register with the START bit set to 1 and choose the required partition to be
power-gated.
 Ideally, software can poll to check the START bit going back to 0, which indicates that the PMC has accepted the
request, and then poll the STATUS register to make sure the required partition is power-gated/unpower-gated.
Power Gate Toggle

Offset: 0x30 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxx0xxx00000)
8 0x0 START: Start power down/up

0 = DISABLE
1 = ENABLE
4:0 0x0 PARTID: ID of the partition to be toggled

0 = CRAIL
1 = TD
2 = Video Encode
3 = PCX
4 = Video Decode
5 = L2 Cache
6 = MPEG Encode
7 = HEG
8 = SAX
9 = CE1
10 = CE2
11 = CE3
12 = CELP
14 = CE0
15 = C0NC
16 = C1NC
17 = SOR
18 = DIS
19 = DISB
20 = XUSBA
21 = XUSBB
22 = XUSBC
23 = VIC
24 = IRAM
9.2.14 APBDEV_PMC_REMOVE_CLAMPING_CMD_0
This is a bitmap with one bit per power partition controller by the PMC.
When written to 1b, the PMC removes the clamp signals to the corresponding partition. If the partition is not powered on, the
register write will be ignored.
The bit is automatically reset to 0b when the clamping has been removed. Software is responsible for writing to this register at
the correct time, that is, when the clocks are started but the blocks in that partition are still held in reset.
Remove Clamping
Offset: 0x34 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxx00000000000x0000000000000)
IRAM: Remove clamping from IRAM partition

24 0x0 0 = DISABLE
1 = ENABLE

VIC: Remove clamping from VIC partition

23 0x0 0 = DISABLE
1 = ENABLE
XUSBC: Remove clamping from XUSBC partition

22 0x0 0 = DISABLE
1 = ENABLE
XUSBB: Remove clamping from XUSBB partition

21 0x0 0 = DISABLE
1 = ENABLE
XUSBA: Remove clamping from XUSBA partition

20 0x0 0 = DISABLE
1 = ENABLE
DISB: Remove clamping from DISB partition

19 0x0 0 = DISABLE
1 = ENABLE
DIS: Remove clamping from DIS partition

18 0x0 0 = DISABLE
1 = ENABLE
SOR: Remove clamping from SOR partition

17 0x0 0 = DISABLE
1 = ENABLE
C1NC: Remove clamping from cluster 1 non-CPU partition

16 0x0 0 = DISABLE
1 = ENABLE
C0NC: Remove clamping from cluster 0 non-CPU partition

15 0x0 0 = DISABLE
1 = ENABLE
CE0: Remove clamping from CE0 partition

14 0x0 0 = DISABLE
1 = ENABLE
12 0x0 A9LP: Remove clamping from CELP partition

0 = DISABLE
1 = ENABLE
11 0x0 CE3: Remove clamping from CE3 partition

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE
SAX: Remove clamping from SAX partition

8 0x0 0 = DISABLE
1 = ENABLE
7 0x0 HEG: Remove clamping from HEG partition

0 = DISABLE
1 = ENABLE

6 0x0 MPE: Remove clamping from MPE_CACHE partition

0 = DISABLE
1 = ENABLE
5 0x0 L2C: Remove clamping from L2_CACHE partition

0 = DISABLE
1 = ENABLE
PCX: Remove clamping from PCX partition

4 0x0 0 = DISABLE
1 = ENABLE
3 0x0 VDE: Remove clamping from VDE partition

0 = DISABLE
1 = ENABLE
2 0x0 VE: Remove clamping from VE partition

0 = DISABLE
1 = ENABLE
1 0x0 TD: Remove clamping from TD partition

0 = DISABLE
1 = ENABLE
0 0x0 CRAIL: Remove clamping from CPU Rail domain

0 = DISABLE
1 = ENABLE
9.2.15 APBDEV_PMC_PWRGATE_STATUS_0
This read-only register displays the status of the power partitions. This register should be read before writing to
PWRGATE_TOGGLE.
Power Gate Status

Offset: 0x38 │ Read/Write: RO │ Reset: 0x0XXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
IRAM: Status of IRAM partition

24 X 0 = OFF
1 = ON
VIC: Status of VIC partition

23 X 0 = OFF
1 = ON
XUSBC: Status of XUSBC partition

22 X 0 = OFF
1 = ON
XUSBB: Status of XUSBB partition

21 X 0 = OFF
1 = ON
XUSBA: Status of XUSBA partition

20 X 0 = OFF
1 = ON

DISB: Status of DISB partition

19 X 0 = OFF
1 = ON
DIS: Status of DIS partition

18 X 0 = OFF
1 = ON
SOR: Status of SOR partition

17 X 0 = OFF
1 = ON
C1NC: Status of cluster1 non-CPU partition

16 X 0 = OFF
1 = ON
C0NC: Status of cluster0 non-CPU partition

15 X 0 = OFF
1 = ON
CE0: Status of CE0 partition

14 X 0 = OFF
1 = ON
12 X CELP: Status of CELP partition

0 = OFF
1 = ON
11 X CE3: Status of CE3 partition

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON
SAX: Status of SAX partition

8 X 0 = OFF
1 = ON
7 X HEG: Status of HEG partition

0 = OFF
1 = ON
6 X MPE: Status of MPE partition

0 = OFF
1 = ON
5 X L2C: Status of L2C partition

0 = OFF
1 = ON
4 X VDE: Status of VDE partition

0 = OFF
1 = ON
PCX: Status of PCX partition

3 X 0 = OFF
1 = ON

2 X VE: Status of VE partition

0 = OFF
1 = ON
1 X TD: Status of TD partition

0 = OFF
1 = ON
0 X CRAIL: Status of CPU Rail

0 = OFF
1 = ON
9.2.16 APBDEV_PMC_PWRGOOD_TIMER_0
This register programs the length of the wake-up reset, asserted after wake-up from Deep Sleep. This register should be set
before entering Deep Sleep mode.
Programmed values depend on the properties of the PMIC.
Timer value x 30.51 µs = reset pulse length
Power Good Timer

Offset: 0x3c │ Read/Write: R/W │ Reset: 0x003f007f (0bxxxxxxxx001111110000000001111111)
OSC_PREPWR: OSC clock stabilization timer prior to SoC rail pwr-req assertion. The
23:16 0x3f timer value is 4*OSC_PREPWR+1 number of 32.768 kHz clock cycles; that is, the
timer value is (OSC_PREPWR*122.07)+30.518 µs.
15:8 0x0 OSC_POSTPWR: OSC clock stabilization timer after SoC rail power is stabilized. The
timer value is 4*OSC_POSTPWR+1 number of 32.768 kHz clock cycles; that is, the
timer value is (OSC_POSTPWR*122.07)+30.518 µs.
7:0 0x7f PWRGOOD: SoC rail power-on stabilization timer.The timer value is PWRGOOD+1
number of 32.768 kHz clock cycles; that is, the timer value is
(PWRGOOD*30.52)+30.518 µs.
9.2.17 APBDEV_PMC_BLINK_TIMER_0
Will output value to pad only if the PMC Control register has BLINK_EN set and DPD_PADS_ORIDE has blink bit set.
Setting bit 15 to 1 will output 32 kHz clock (the registers above still have to be set)
 On time DATA_ON << 2 x 30.51 µs

 Off time DATA_OFF << 2 x 30.51 µs.
Blinker Timer for External Blinker

Offset: 0x40 │ Read/Write: R/W │ Reset: 0xffffffff (0b11111111111111111111111111111111)
31:16 0xffff DATA_OFF: Time off
15 0x1 FORCE_BLINK: if 0 32 kHz clock
14:0 0x7fff DATA_ON: Time on

9.2.18 APBDEV_PMC_NO_IOPOWER_0
IMPORTANT: Before an I/O power rail is turned off, ramping up, or no longer used and ready to turn off, the corresponding bit
in this register should be set to 1. The bit only needs to be turned on when the I/O power rail is stable and you are ready to
enable some interface on the I/O power rail.
No I/O Power Register

Offset: 0x44 │ Read/Write: R/W │ Reset: 0x00010080 (0bxxxxxxxxxxxxxx010000000x1x000000)
SYS_2:rail AO I/Os
17 0x0 0 = DISABLE
1 = ENABLE
MEM_COMP:MEM0 ADDR1 (comp cell I/Os)

16 0x1 0 = DISABLE
1 = ENABLE
HV: rail HV I/Os

15 0x0 0 = DISABLE
1 = ENABLE
14 0x0 SDMMC4: rail SDMMC4 I/Os

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE
PEX_CNTRL: PEX
11 0x0 0 = DISABLE
1 = ENABLE
10 0x0 CAM: Cam rail I/Os

0 = DISABLE
1 = ENABLE
9 0x0 MIPI: MIPI rail I/Os

0 = DISABLE
1 = ENABLE
7 0x1 MEM: rail memory I/Os

0 = DISABLE
1 = ENABLE
5 0x0 AUDIO: rail I2S I/Os

0 = DISABLE
1 = ENABLE
4 0x0 VI: Defunct DVI I/Os

0 = DISABLE
1 = ENABLE
3 0x0 BB: rail DLCD I/Os

0 = DISABLE
1 = ENABLE

2 0x0 UART: rail DBG I/Os

0 = DISABLE
1 = ENABLE
1 0x0 NAND: rail AT3 I/Os

0 = DISABLE
1 = ENABLE
0 0x0 SYS: rail AO I/Os

0 = DISABLE
1 = ENABLE
9.2.19 APBDEV_PMC_PWR_DET_0
Active high, sets power detection for nine power rails only. - MIPI does not have power detect.
The proper sequence for turning on power detects:
 Write 1 to PWR_DET register for fields requiring power detect

 Allow for 3 µs delay (in APB clock cycles)
 Write 1 to PWR_DET_LATCH
For turning PWR_DET off:
 Write 0 to PWR_DET_LATCH
 No delay is necessary
 Write 0 to PWR_DET
Power Detect
Offset: 0x48 │ Read/Write: R/W │ Reset: 0x0002bc2f (0bxxxxxxxxxxxxxx1x1x1111xxxx1x1111)
SYS_2:rail AO I/Os
17 0x1 0 = DISABLE
1 = ENABLE
15 0x1 HV:HV rail

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE
PEX_CNTRL: PEX rail

11 0x1 0 = DISABLE
1 = ENABLE
10 0x1 CAM: rail Cam I/Os

0 = DISABLE
1 = ENABLE
5 0x1 AUDIO: rail I2S I/Os

0 = DISABLE
1 = ENABLE

3 0x1 BB:rail DLCD I/Os

0 = DISABLE
1 = ENABLE
2 0x1 UART: rail DBG I/Os

0 = DISABLE
1 = ENABLE
1 0x1 NAND: rail GMI I/Os

0 = DISABLE
1 = ENABLE
0 0x1 SYS: rail AO I/Os

0 = DISABLE
1 = ENABLE
9.2.20 APBDEV_PMC_PWR_DET_LATCH_0
Latches power detect for power rails enabled by Power Detect register.
Power Detect Latch

Offset: 0x4c │ Read/Write: R/W │ Reset: 0x00000001 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1)
0 0x1 LATCH: power detect latch, latches value as long set to 1

0 = DISABLE
1 = ENABLE
9.2.21 APBDEV_PMC_SCRATCH0_0
Scratch Register
Scratch registers for restoring context after wake-up. On a cold power up, the content of register 0 will be reset to 0x0.
31:0 0x0 SCRATCH0: General-purpose register storage
Scratch Register
Offset: 0x54 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X SCRATCH1: General-purpose register storage

Scratch Register
Scratch Register
Offset: 0x5c │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Scratch Register
Scratch Register
Scratch Register

Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register

Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register

Scratch Register
Scratch Register
Scratch Register
Scratch Register
Offset: 0xa0 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Scratch Register

Scratch Register
Scratch Register
Offset: 0xac │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
9.2.45 APBDEV_PMC_SECURE_SCRATCH0_0
Secure Scratch Register

Offset: 0xb0 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X SECURE_SCRATCH0




Offset: 0xbc │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)

Offset: 0xc0 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)

Offset: 0xc4 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
9.2.51 APBDEV_PMC_CPUPWRGOOD_TIMER_0
CPU Power Good Timer

The behavior for the DATA timers 0 to 2 is the same (i.e., 2 cycles of delay).
This timer runs on the APB clock.
It should also be used to mask OC during CPU rail power up when OC is multiplexed to the PG pin using
APBDEV_PMC_CNTRL_0_CPUPWRGOOD_EN based on how long the PMIC drives PG on this signal.
Offset: 0xc8 │ Read/Write: R/W │ Reset: 0x0000ffff (0b00000000000000001111111111111111)
31:0 0xffff DATA: Timer data

9.2.52 APBDEV_PMC_CPUPWROFF_TIMER_0
CPU Power Off Timer

Used for On-to-Off transitions.
This timer runs on the APB clock
It should also be used to mask OC during CPU rail power down when OC is multiplexed to the PG pin using
APBDEV_PMC_CNTRL_0_CPUPWRGOOD_EN based on how long the PMIC keeps PG low.
Note: This timer must always have a non-zero value.
Offset: 0xcc │ Read/Write: R/W │ Reset: 0x0000ffff (0b00000000000000001111111111111111)
31:0 0xffff DATA: Timer data
9.2.53 APBDEV_PMC_PG_MASK_0
Offset: 0xd0 │ Read/Write: R/W │ Reset: 0xffffffff (0b11111111111111111111111111111111)
31:24 0xff PCX: Mask PCX rail
23:16 0xff VD: Mask VDE rail
15:8 0xff VE: Mask VE rail
7:0 0xff TD: Mask TD rail
9.2.54 APBDEV_PMC_PG_MASK_1_0
Offset: 0xd4 │ Read/Write: R/W │ Reset: 0xffffff01 (0b111111111111111111111111xxxxxxx1)
31:24 0xff SAX: Mask SAX rail
23:16 0xff HEG: Mask HEG rail
15:8 0xff MPE: Mask MPE rail
0 0x1 L2C: Mask L2C rail
9.2.55 APBDEV_PMC_AUTO_WAKE_LVL_0
Note: This register is not used.
The wake levels are snapped just before entering DPD by default.
Offset: 0xd8 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
SMPL: Causes PMC to sample the wake pads

0 0x0 0 = DISABLE
1 = ENABLE

9.2.56 APBDEV_PMC_AUTO_WAKE_LVL_MASK_0
This register is used by software to enable sampling of the wake pads before entering Deep Sleep.
Setting a '1' causes the associated pad to be sampled, and the value transferred to the WAKE_LVL register.
Offset: 0xdc │ Read/Write: R/W │ Reset: 0x00000000 (0b00000000000000000000000000000000)
31:0 0x0 VALUE
9.2.57 APBDEV_PMC_WAKE_DELAY_0
WAKE_DELAY should be a non-zero value.
Offset: 0xe0 │ Read/Write: R/W │ Reset: 0x00000001 (0bxxxxxxxxxxxxxxxx0000000000000001)
15:0 0x1 VALUE
9.2.58 APBDEV_PMC_PWR_DET_VAL_0
This register is used to override the power-detect cells and manually set the values (in the unlikely case the power-detect cells
are broken). A write to this register also causes the values from the power-detect cells to be captured and which can be
subsequently read out.
Offset: 0xe4 │ Read/Write: R/W │ Reset: 0x0002bc2f (0bxxxxxxxxxxxxxx1x1x1111xxxx1x1111)
SYS_2: rail AO I/Os

17 0x1 0 = ENABLE
1 = DISABLE
HV:rail HV I/Os
15 0x1 0 = ENABLE
1 = DISABLE
SDMMC3: rail SDMMC3 I/Os

13 0x1 0 = ENABLE
1 = DISABLE
SDMMC1: rail SDMMC1 I/Os

12 0x1 0 = ENABLE
1 = DISABLE
PEX_CNTRL: PEX rail

11 0x1 0 = ENABLE
1 = DISABLE
CAM: rail cam I/Os

10 0x1 0 = ENABLE
1 = DISABLE
AUDIO: rail I2S I/Os

5 0x1 0 = ENABLE
1 = DISABLE
BB: rail DLCD I/Os

3 0x1 0 = ENABLE
1 = DISABLE
UART: rail DBG I/Os

2 0x1 0 = ENABLE
1 = DISABLE
1 0x1 NAND: rail AT3 I/Os


0 = ENABLE
1 = DISABLE
SYS: rail AO I/Os

0 0x1 0 = ENABLE
1 = DISABLE
9.2.59 APBDEV_PMC_DDR_PWR_0
This register is used to program the "E_18V" pin of the DDR pads.
Offset: 0xe8 │ Read/Write: R/W │ Reset: 0x00000003 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11)
EMMC: GMI pins

1 0x1 0 = E_12V
1 = E_18V
VAL: DVI pins

0 0x1 0 = E_12V
1 = E_18V
9.2.60 APBDEV_PMC_USB_DEBOUNCE_DEL_0
Determines number of 32 kHz clock cycles to debounce USB signal events.
Note: The programmed debounce values must be greater than 1.
Reset values are for Cold Hardware Reset only.
Offset: 0xec │ Read/Write: R/W │ Reset: 0x00000002 (0bxxxxxxxx000000000000000000000010)
23:20 0x0 UHSIC_LINE_DEB_CNT: Number of 32 kHz debounce cycles for UHSIC port 0
19:16 0x0 UTMIP_LINE_DEB_CNT: Number of 32 kHz debounce cycles for UTMIP port 0
VAL: Debounce period for ID and VBUS events on all USB ports. The programmed value
15:0 0x2
must be greater than 1.
9.2.61 APBDEV_PMC_USB_AO_0
Power downs for various USB features controlled by the PMC.
Each UTMIP has the following power downs for features that can lead to wake-up events.
 USBOP_VAL_PD: Power down for D+ value detector (I/O pad)

 USBON_VAL_PD: Power down for D- value detector (I/O pad)
 ID_PD: Power down for ID detector (bias pad)
 VBUS_WAKEUP_PD: Power down for VBUS detector (bias pad)
Each UHSIC port has the following power downs for features that can lead to wake-up events:
 STROBE_VAL_PD: Power down for STROBE VALUE detector

 DATA_VAL_PD: Power down for DATA VALUE detector
Note: These HSIC pins have not been added to the pad yet.

Line Debounce Periods for UTMIP and HSIC PORTS

Offset: 0xf0 │ Read/Write: R/W │ Reset: 0x000fffff (0bxxxxxxxxxxxx11111111111111111111)
19:18 0x3 UHSIC_RESERVED_P1: 2 bits reserved for UHSIC P1
17 0x1 DATA_VAL_PD_P1: Power Down D- DATA_VAL receiver for UHSIC P1
16 0x1 STROBE_VAL_PD_P1: Power Down D+ STROBE_VAL receiver for UHSIC P1
15:14 0x3 UHSIC_RESERVED_P0: 2 bits reserved for UHSIC P1
13 0x1 DATA_VAL_PD_P0: Power Down D- DATA_VAL receiver for UHSIC P0
12 0x1 STROBE_VAL_PD_P0: Power Down D+ STROBE_VAL receiver for UHSIC P0
11 0x1 ID_PD_P2: Power Down ID Wake up for UTMIP
10 0x1 VBUS_WAKEUP_PD_P2: Power Down Vbus Wake Up for UTMIP P2
9 0x1 USBON_VAL_PD_P2: Power Down D- USBOP_VAL receiver for UTMIP P0
8 0x1 USBOP_VAL_PD_P2: Power Down D+ USBOP_VAL receiver for UTMIP P0
7 0x1 ID_PD_P1: Power Down ID Wake up for UTMIP P1
3 0x1 ID_PD_P0: Power Down ID Wake up for UTMIP
9.2.62 APBDEV_PMC_CRYPTO_OP_0
A complete solution requires a "semi-sticky" bit in the always-on domain. The Boot ROM would clear this semi-sticky bit for
cold boots, but use its value to propagate the crypto-disable flag across LP0. (The Boot ROM always requires crypto
functionality, so a pure hardware solution probably isn't reasonable.)
The Boot ROM would be able to clear (to zero) and read the sticky bit, but outside the Boot ROM users would only be able to
set (to one) and read the sticky bit. On cold boot, the Boot ROM would always clear the stick bit. On WB0, the Boot ROM
would read the sticky bit and copy it's setting to the crypto disable flag.
Crypto Engine Disable Sticky Bit

Offset: 0xf4 │ Read/Write: R/W │ Reset: 0x00000001 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1)
VAL: Disabled by default

0 0x1 0 = ENABLE
1 = DISABLE

9.2.63 APBDEV_PMC_PLLP_WB0_OVERRIDE_0
Master control for all WB0 PLL overrides.
Offset: 0xf8 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxx0000000000000)
12 0x0 PLLM_ENABLE: 1 = enable PLLM, 0 = disable PLLM
PLLM_OVERRIDE_ENABLE: 1 = override CAR PLLM setting, 0 = no override. PLLM WB

11 0x0
to programmable frequency.
10 0x0 PLLU_ENABLE: 1 = enable PLLU, 0 = disable PLLU.
PLLU_OVERRIDE_ENABLE: 1 = override CAR PLLU setting, 0 = no override. PLLU WB

9 0x0
to fixed frequency
OSC_OVERRIDE_ENABLE: 1 = override CAR OSC setting, 0 = no override. Controls

8 0x0
OSC_FREQ and PLL_REF_DIV
PLL_REF_DIV: PLL reference clock divide for all PLLs. 00 = /1, 01 = /2, 10 = /4, 11 =
7:6 0x0
reserve.
OSC_FREQ: Oscillator frequency for shared PLL reference

0000 = 13MHz
0100 = 19.2MHz
5:2 0x0 1000 = 12MHz
1100 = 26MHz
0001 = 16.8MHz
0101 = 38.4MHz
1001 = 48.0MHz
1 0x0 PLLP_ENABLE: 1 = enable PLLP, 0 = disable PLLP
PLLP_OVERRIDE_ENABLE: 1 = override CAR PLLP setting, 0 = no override. PLLP WB

0 0x0
to fixed frequency.
Scratch Register
Offset: 0xfc │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Scratch Register

Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register

Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register

Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register
9.2.83 APBDEV_PMC_BONDOUT_MIRROR0_0

31:0 X BONDOUT_MIRROR0



9.2.86 APBDEV_PMC_SYS_33V_EN_0
VAL:
0 0x0 1 = 3.3V
0 = 1.8V
9.2.87 APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0
On separate reset (same as the CAR) disables access (read/write to secure scratch registers)
BREAD: disable read from bondout secure registers

1 0x0 0 = OFF
1 = ON
BWRITE: disable write to bondout secure registers

0 0x0 0 = OFF
1 = ON
9.2.88 APBDEV_PMC_GATE_0
This register is used for software controlled synchronization between APB domain and the 32 kHz domain. Software is
expected to set the GAKE_WAKE/GATE_DBNS field high to cut the 32 kHz gated clock before updating WAKE_LVL,
AUTO_WAKE_LVL, WAKE_MASK and USB_DEBOUNCE_DEL registers. After these registers have been written the
GATE_WAKE/GATE_DBNS bit should be written back to '0' to enable the 32 kHz gated clock.
This gates the 32 kHz clock to just the flops that store the above fields.
GATE_WAKE:
0 0x0 0 = OFF
1 = ON

GATE_DBNS:
0 0x0 0 = OFF
1 = ON
9.2.89 APBDEV_PMC_WAKE2_MASK_0
Auto-wake is not present for wake2 events in Tegra K1 devices.
The APBDEV_PMC_WAKE2 registers handle wake events whose number exceeds 32. For wake events whose number is
less than or equal to 32, refer to the APBDEV_PMC_WAKE registers above.
Wake2 alignments for masks, level, and status:
 WAKE2_*[0] = ulpi_data3 (wake event 32)

 WAKE2_*[1] = gpio_pj[0] (wake event 33)
 WAKE2_*[2] = gpio_pk[2] (wake event 34)
 WAKE2_*[3] = gpio_pi[6] (wake event 35)
 WAKE2_*[7]= utmip0_line_wakup_event (wake event 39)
 WAKE2_*[10]= uhsic_line_wakup_event (wake event 42)
 WAKE2_*[11]= uhsic2_line_wakup_event (wake event 43)
 WAKE2_*[12]= gen1_i2c1_sda (wake event 44)
 WAKE2_*[13]= gpio_pbb6 (wake event 45)
 WAKE2_*[14]= pwr_i2c_sda (wake event 46)
 WAKE2_*[15]= gen2_i2c_sda (wake event 47)
 WAKE2_*[16]= cam_i2c_sda (wake event 48)
 WAKE2_*[17]= kb_row7 (wake event 49)
 WAKE2_*[18]= kb_row4 (wake event 50)
 WAKE2_*[19]= kb_col0 (wake event 51)
 WAKE2_*[20]= hdmi_cec (wake event 52)
 WAKE2_*[21]= cam_i2c_scl (wake event 53)
 WAKE2_*[22]= kb_col5 (wake event 54)
 WAKE2_*[23]= uart3_cts_n (wake event 55)
 WAKE2_*[24]= sdmmc3_cd_n (wake event 56)
 WAKE2_*[25]= spdif_in (wake event 57)
 WAKE2_*[26] = wake2pmc_xusb_system_wakeup (wake event 58)
Offset: 0x160 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxx00000000000000000000000000000)
EVENT_REST_1:
28:12 0x0 0 = DISABLE
1 = ENABLE
EVENT_REST:
11:7 0x0 0 = DISABLE
1 = ENABLE

USB_EVENT:
6:5 0x0 0 = ACTIVE_LOW
1 = ACTIVE_HIGH
EVENT:
4:0 0x0 0 = DISABLE
1 = ENABLE
9.2.90 APBDEV_PMC_WAKE2_LVL_0
This register sets the active level for a wake event. It causes an exit from the Deep Sleep state if the input signal level matches
the level set in this register and if WAKE2_MASK is set for the event to 1. A level is not needed for 4 line wakeup events; the
level is always 1.
Set the following PMC register bits to ‘1’ to set the wake signal active level to ‘HIGH’:
 APBDEV_PMC_WAKE2_LVL_0[5] for VBUS wakeup

 APBDEV_PMC_WAKE2_LVL_0[6] for ID wakeup
 APBDEV_PMC_WAKE2_LVL_0[7] for USB2.0 port 0 wakeup
 APBDEV_PMC_WAKE2_LVL_0[10] for HSIC port 0 wakeup
 APBDEV_PMC_WAKE2_LVL_0[11] for HSIC port 1 wakeup
 APBDEV_PMC_WAKE2_LVL_0[26] for USB3.0 ports wakeup
PMC Wake Level

Offset: 0x164 │ Read/Write: R/W │ Reset: 0x19ffffe7 (0b00011001111111111111111111100111)
31 0x0 ALLOW_PULSE_WAKE: Reserved
30:29 0x0 FUTURE_CNTL: Reserved
EVENT_REST_1:
28:12 0x19fff 0 = ACTIVE_LOW
1 = ACTIVE_HIGH
EVENT_REST:
11:7 0x1f 0 = ACTIVE_LOW
1 = ACTIVE_HIGH
USB_EVENT:
1 = ACTIVE_HIGH
EVENT: Pin 0-2 wake level

1 = ACTIVE_HIGH
9.2.91 APBDEV_PMC_WAKE2_STATUS_0
This register stores status of the wake events. An event is set if the level matches and is not masked.
Writes will reset the set wake event.
PMC Wake Status


EVENT_REST_1:
28:12 0x0 0 = NOT_SET
1 = SET
EVENT_REST: Internally set USB events

11:7 0x0 0 = NOT_SET
1 = SET
USB_EVENT: USB wake events

6:5 0x0 0 = NOT_SET
1 = SET
EVENT: Pin 0-2 wake enable

4:0 0x0 0 = NOT_SET
1 = SET
9.2.92 APBDEV_PMC_SW_WAKE2_STATUS_0
This register stores the status of the wake events. Latching of the events in software wake status is enabled by the
PMC_CNTRL register bit LATCHWAKE_EN. Latching will stop at a 1-to-0 transition on this bit.
An event is set if the level matches. Masking does not affect this register. Writes will reset the set wake events.
PMC Software Wake Status

Offset: 0x16c │Read/Write: R/W │ Reset: 0x00000000 (0bxxx00000000000000000000000000000)
EVENT_REST_1:
28:12 0x0 0 = NOT_SET
1 = SET
11:7 0x0 EVENT_REST
USB_EVENT: USB wake events

6:5 0x0 0 = NOT_SET
1 = SET
EVENT: pin 0-2 wake

4:0 0x0 0 = DISABLE
1 = ENABLE
9.2.93 APBDEV_PMC_AUTO_WAKE2_LVL_MASK_0
Auto-wake is not present for wake2 events in Tegra K1 devices.
28:12 0x0 EVENT_REST_1
11:7 0x0 EVENT_REST
6:0 0x0 VALUE
Power-Gate mask registers for power-gated fields. Need 32 bits for CPU.
Offset: 0x174 │ Read/Write: R/W │ Reset: 0xffffffff (0b11111111111111111111111111111111)

31:24 0xff IRAM: Mask IRAM rail
23:16 0xff VIC: Mask CELP rail
15:8 0xff CELP: Mask CELP rail
7:0 0xff TD2: Mask TD2 rail - Defunct
9.2.95 APBDEV_PMC_PG_MASK_CE1_0
Offset: 0x178 │ Read/Write: R/W │ Reset: 0x000000ff (0bxxxxxxxxxxxxxxxxxxxxxxxx11111111)
7:0 0xff MASK: Mask CE1 rail
Offset: 0x17c │ Read/Write: R/W │ Reset: 0x000000ff (0bxxxxxxxxxxxxxxxxxxxxxxxx11111111)
Offset: 0x180 │ Read/Write: R/W │ Reset: 0x000000ff (0bxxxxxxxxxxxxxxxxxxxxxxxx11111111)
9.2.98 APBDEV_PMC_PWRGATE_TIMER_CE_0_0
Separate power_gate_off, on, for CE counters - 4 bits each.
Offset: 0x184 │ Read/Write: R/W │ Reset: 0xedcba987 (0b11101101110010111010100110000111)
31:28 0xe RAIL7: Timer Value for rail 7
27:24 0xd RAIL6: Timer Value for rail 6
23:20 0xc RAIL5: Timer Value for rail 5
19:16 0xb RAIL4: Timer Value for rail 4
15:12 0xa RAIL3: Timer Value for rail 3
11:8 0x9 RAIL2: Timer Value for rail 2
PWRGATE_TIMER CE_1 removed but kept for backward compatibility.
Offset: 0x188 │ Read/Write: R/W │ Reset: 0x1240e30a (0bxx010010010000001110001100001010)

17:12 0xe RAIL7: Timer Value for rail 7
11:6 0xc RAIL6: Timer Value for rail 6
5:0 0xa RAIL5: Timer Value for rail 5
Offset: 0x18c │ Read/Write: R/W │ Reset: 0x1c698594 (0bxx011100011010011000010110010100)
29:24 0x1c RAIL14: Timer Value for rail 14
23:18 0x1a RAIL13: Timer Value for rail 13
Offset: 0x190 │ Read/Write: R/W │ Reset: 0x2692281e (0bxx100110100100100010100000011110)
5:0 0x1e RAIL15: Timer Value for rail 15
Offset: 0x194 │ Read/Write: R/W │ Reset: 0x30bacaa8 (0bxx110000101110101100101010101000)
23:18 0x2e RAIL23: Timer Value for rail 23

Offset: 0x198 │ Read/Write: R/W │ Reset: 0x3ae36d32 (0bxx111010111000110110110100110010)
Offset: 0x19c │ Read/Write: R/W │ Reset: 0x00000f3b (0bxxxxxxxxxxxxxxxxxxxx111100111011)
5:0 0x3b RAIL30: Timer Value for rail 30
9.2.105 APBDEV_PMC_PCX_EDPD_CNTRL_0
Defunct
Offset: 0x1a0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
EN: when set to 1, sets the EDPD to PCX (PLL toggle)

0 0x0 0 = OFF
1 = ON
9.2.106 APBDEV_PMC_OSC_EDPD_OVER_0
This register can be programmed to keep the oscillator ON during LP0 mode. It cuts the latency time on LP0 wake if the
oscillator pad does not have to be restarted.
When the oscillator pad is on, during LP0 mode, DSPARE, duty, strength, and bypass are controlled by the fields below.
The oscillator can be in one in four modes during LP0 - in DPD, not in DPD but not enabled, running, or running only when an
external request is active.
Offset: 0x1a4 │ Read/Write: R/W │ Reset: 0x0000007e (0bxxxxxxxx000000000000000001111110)
CLK_OK: Crystal oscillator clk_ok signal

23 0x0 0 = DISABLE
1 = ENABLE
OSC_CTRL_SELECT: select whether the CAR's OSC_CTRL or the PMC's

OSC_CTRL_OVER affects the oscillator cell. This bit should always be "1" in LP0.
22 0x0
0 = CAR
1 = PMC
XO_LP0_MODE: control the behavior of the oscillator during LP0 (assuming

OSC_CTRL_SELECT is set to PMC during LP0). Put the oscillator in DPD mode during
21:20 0x0 LP0, bypass DPD, but do not enable the oscillator during LP0, force the oscillator to run
during LP0, or run the oscillator when requested by an external clock request pin
0 = DPD.
1 = OFF


2 = ON
3 = EXT_REQ
19:12 0x0 OSCFI_SPARE: Crystal oscillator spare register control.
11:7 0x0 XODS: Crystal oscillator duty cycle control.
6:1 0x3f XOFS: Crystal oscillator drive strength control.
0 0x0 XOBP: Crystal oscillator bypass enable (1 = enable bypass).
9.2.107 APBDEV_PMC_CLK_OUT_CNTRL_0
This register controls 3 clock outputs of the Tegra K1 chip. Each of the clock outputs can be in 1 of 4 modes: not running,
running when request is active high, running when request is active low, or always running. The clock output when not running
can be tristated, high, or low.
The clock source might be from the CAR unit (not available when in LP0 mode), osc, osc_div2, or osc_div4.
The clock source switching on dap_mclk1_out , clk3_out and clk2_out is not glitch free. If dpd_override is not set before
entering LP0, the selected clock source will get latched to "0" or "1" in LP0 (which is not glitch free).dpd_override can be "0"
only when external device does not need clock in LP0, and it should be in reset before PMC_SAMPLE bit is written by LP0
entry code.
The clock source should only be switched when the pad output is not being used by an external device.
When an external device requests for a clock, the first few clocks should not be used by the external device.
Offset: 0x1a8 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxx000000000000000000000000)
CLK3_SRC_SEL:
0 = OSC_DIV1
23:22 0x0 1 = OSC_DIV2
2 = OSC_DIV3
3 = CAR
CLK3_IDLE_STATE:
0 = LOW
21:20 0x0
1 = HIGH
2 = TRIS
19 0x0 CLK3_RESERVED: reserved
18 0x0 CLK3_FORCE_EN: force the clock to run regardless of ACCEPT_REQ or INVERT_REQ
17 0x0 CLK3_INVERT_REQ:
16 0x0 CLK3_ACCEPT_REQ:
CLK2_SRC_SEL:
0 = OSC_DIV1
15:14 0x0 1 = OSC_DIV2
2 = OSC_DIV3
3 = CAR
CLK2_IDLE_STATE:
0 = LOW
13:12 0x0
1 = HIGH
2 = TRIS

CLK1_SRC_SEL:
0 = OSC_DIV1
7:6 0x0 1 = OSC_DIV2
2 = OSC_DIV3
3 = CAR
CLK1_IDLE_STATE: state of the output line before clock request is active

0 = LOW
5:4 0x0
1 = HIGH
2 = TRIS
9.2.108 APBDEV_PMC_SATA_PWRGT_0
This register controls the SATA PLLs
PLLE or PADPLL can be disabled/enabled by a software or hardware request.
The SATA PWRGT is reserved for backward compatibility.
Offset: 0x1ac │ Read/Write: R/W │ Reset: 0x0000003f (0bxxxxxxxxxxxxxxxxxxxxxxxx00111111)
SW_PLL_EDPD: Defunct.
The SATA PLL is put in the DPD state when this bit is set, independently of power-gating -
7 0x0 kept only until drivers are fixed.
0 = OFF
1 = ON
6 0x0 PG_INFO: sm2sata_pg_info
PLLE_IDDQ_OVERRIDE_VALUE: Defunct.
0: The PLLE is powered up. 1: Software can put the PLLE in IDDQ mode by setting this bit
5 0x1 and PLLE_IDDQ_SWCTL (default)
0 = OFF
1 = ON
PLLE_IDDQ_SWCTL: 0: Defunct.
The PLLE is put in IDDQ mode by hardware (SATA +AFI+CAR) signals. 1: The PLLE is
4 0x1 put in IDDQ mode by software -- default
0 = OFF
1 = ON
PADPHY_IDDQ_OVERRIDE_VALUE: Defunct. Shared with XUSB0.

0: The PHY is powered up. 1: Software can put the PHY in IDDQ mode by setting this bit
3 0x1 and SATA_PADPHY_IDDQ_SWCT (default)
0 = OFF
1 = ON
PADPHY_IDDQ_SWCTL: Defunct. Shared with XUSB0.

0 The SATA PHY is put in IDDQ mode by hardware (SATA +AFI+CAR) signals. 1 The
2 0x1 SATA PHY is put in IDDQ mode by software (default)
0 = OFF
1 = ON
PADPLL_IDDQ_OVERRIDE_VALUE: Defunct.
0: The pad PLL is powered up 1: Software can put the pad PLL in IDDQ mode by setting
1 0x1 this bit and SATA_PADPLL_IDDQ_SWCTL (default)
0 = OFF
1 = ON

PADPLL_IDDQ_SWCTL: Defunct.
0: The SATA pad PLL is put in IDDQ mode by hardware (SATA +AFI+CAR) signals.1: The
0 0x1 SATA pad PLL is put in IDDQ mode by software (default)
0 = OFF
1 = ON
9.2.109 APBDEV_PMC_SENSOR_CTRL_0
For sensor shutdown and control.
The sensor control register defines chip behavior when a sensor request is triggered. It can power-gate down all CPUs if
enabled. It can trigger a reset (will cause a CPU power request to go down and power-gates down all CPUs)
IMPORTANT-- to preserve RAM content, any reads/writes to scratch registers will be blocked after a sensor triggered reset.
Software must reset BLOCK_SCRATCH_WRITE to enable writes to scratch registers.
Offset: 0x1b0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000)
BLOCK_SCRATCH_WRITE: Reset by user, set by the PMC when entering sensor reset
2 0x0 0 = OFF
1 = ON
ENABLE_RST: Enables reset on sensor going up.

1 0x0 0 = OFF
1 = ON
ENABLE_PG: Power gates CPUs on temperature sensor going up.

0 0x0 0 = OFF
1 = ON
9.2.110 APBDEV_PMC_RST_STATUS_0
Simplified Reset and Reset Source

Offset: 0x1b4 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000)
RST_SOURCE: Source of reset

0 = POR
1 = WATCHDOG
2:0 0x0
2 = SENSOR
3 = SW_MAIN
4 = LP0
9.2.111 APBDEV_PMC_IO_DPD_REQ_0
Puts I/O rails in or out of DPD mode, even though the chip is not in LP0. Multiple bits are allowed to be set at the same time.
No new operation will be triggered until previous one completes. Consecutive operations issued by completion time of first one
will be dropped. The register is still updated.
Setting IO_DPD_REQ should be preceded by writing to the DPD_SAMPLE registers (to enable a snapshot of data to be
driven) and the SEL_DPD_TIM register. SEL_DPD_TIM is set to a safe value, but it can be lowered if SYS clock is slower (a
minimum of 200 ns is required).
Note: Only one sample signal exists to perform sampling while entering DPD mode. Thus all interfaces are sampled
at the same time. The sequence of multiple DPD groups requires keeping all interfaces (already in DPD mode)
in idle.

DPD Request
Offset: 0x1b8 │ Read/Write: R/W │ Reset: 0x00000000 (0b0000000000000x000000000xx0000000)
CODE: Code of operation for all set bits

0 = IDLE
31:30 0x0
1 = DPD_OFF
2 = DPD_ON
USB_IC: Defunct. Puts usb_ic_pad in/out of deep power down mode

29 0x0 0 = OFF
1 = ON
HDMI: Puts hdmi_pad in/out of Deep Power Down mode

28 0x0 0 = OFF
1 = ON
DDR_DATA: Defunct.
27 0x0 0 = OFF
1 = ON
DISC_ADDR_CMD: Defunct
26 0x0 0 = OFF
1 = ON
DDR_ADDR_CMD: Defunct
25 0x0 0 = OFF
1 = ON
POP_ADDR_CMD: Defunct
24 0x0 0 = OFF
1 = ON
POP_CLK: Defunct
23 0x0 0 = OFF
1 = ON
22 0x0 COMP: puts xm0_comp_pd_pad, xm0_comp_pu_pad in/out of deep power down mode
DISC_VTTGEN: Defunct.
21 0x0 0 = OFF
1 = ON
POP_VTTGEN: Defunct.
20 0x0 0 = OFF
1 = ON
HSIC: puts HSIC rail in/out of Deep Power Down mode

19 0x0 0 = OFF
1 = ON
AUDIO: Puts audio rail in/out of Deep Power Down mode

17 0x0 0 = OFF
1 = ON
VI: Defunct.
16 0x0 0 = OFF
1 = ON
BB: Puts the BB rail in/out of Deep Power Down mode

15 0x0 0 = OFF
1 = ON
UART: Puts the UART rail in/out of Deep Power Down mode
14 0x0 0 = OFF
1 = ON
NAND: Puts the NAND rail in/out of Deep Power Down mode
13 0x0 0 = OFF
1 = ON
12 0x0 USB_BIAS: Puts usb_bias in/out of Deep Power Down mode


0 = OFF
1 = ON
USB2: Puts USB2 in/out of Deep Power Down mode

11 0x0 0 = OFF
1 = ON
USB1:Puts USB1 in/out of Deep Power Down mode

10 0x0 0 = OFF
1 = ON
USB0: Puts USB0 in/out of Deep Power Down mode

9 0x0 0 = OFF
1 = ON
PEX_CLK2: PEX clk2 pad-DPD control

6 0x0 0 = OFF
1 = ON
PEX_CLK1: PEX clk1 pad- DPD control

5 0x0 0 = OFF
1 = ON
PEX_BIAS:PEX bias pad- DPD control

4 0x0 0 = OFF
1 = ON
MIPI_BIAS: Puts mipi_bias in/out of Deep Power Down mode

3 0x0 0 = OFF
1 = ON
DSI: Puts DSI in/out of Deep Power Down mode

2 0x0 0 = OFF
1 = ON
CSIB: Puts CSIB in/out of Deep Power Down mode

1 0x0 0 = OFF
1 = ON
CSIA: Puts CSIA in/out of Deep Power Down mode

0 0x0 0 = OFF
1 = ON
9.2.112 APBDEV_PMC_IO_DPD_STATUS_0
Reflects the DPD status of each I/O rail.
DPD Status
Offset: 0x1bc │ Read/Write: R/W │ Reset: 0x0000000X (0bxx00000000000x000000000xx000xxxx)
USB_IC: Defunct. usb_ic_pad in/out of Deep Power Down mode

29 RW 0x0 0 = OFF
1 = ON
HDMI: hdmi_pad in Deep Power Down mode

28 RW 0x0 0 = OFF
1 = ON
DDR_DATA: Defunct.
27 RW 0x0 0 = OFF
1 = ON
DISC_ADDR_CMD: Defunct
26 RW 0x0 0 = OFF
1 = ON
25 RW 0x0 DDR_ADDR_CMD: Defunct


0 = OFF
1 = ON
POP_ADDR_CMD: Defunct
24 RW 0x0 0 = OFF
1 = ON
POP_CLK: Defunct
23 RW 0x0 0 = OFF
1 = ON
COMP: Puts xm0_comp_pd_pad, xm0_comp_pu_pad in Deep Power Down

22 RW 0x0
mode
DISC_VTTGEN: Defunct
21 RW 0x0 0 = OFF
1 = ON
POP_VTTGEN: Defunct
20 RW 0x0 0 = OFF
1 = ON
HSIC: Puts HSIC rail in Deep Power Down mode

19 RW 0x0 0 = OFF
1 = ON
AUDIO: Puts audio rail in Deep Power Down mode

17 RW 0x0 0 = OFF
1 = ON
VI: Defunct. Puts VI rail in Deep Power Down mode

16 RW 0x0 0 = OFF
1 = ON
BB: BB rail in Deep Power Down mode

15 RW 0x0 0 = OFF
1 = ON
UART: UART rail in Deep Power Down mode

14 RW 0x0 0 = OFF
1 = ON
NAND: NAND rail in Deep Power Down mode

13 RW 0x0 0 = OFF
1 = ON
USB_BIAS: usb_bias in Deep Power Down mode

12 RW 0x0 0 = OFF
1 = ON
USB2: USB2 in Deep Power Down mode

11 RW 0x0 0 = OFF
1 = ON

10 RW 0x0 0 = OFF
1 = ON

9 RW 0x0 0 = OFF
1 = ON
PEX_CLK2:PEX clk2 pad-DPD control

6 RW 0x0 0 = OFF
1 = ON
PEX_CLK1:PEX clk1 pad-DPD control

5 RW 0x0 0 = OFF
1 = ON

PEX_BIAS:PEX bias pad-DPD control

4 RW 0x0 0 = OFF
1 = ON
MIPI_BIAS: mipi_bias in Deep Power Down mode

3 RO X 0 = OFF
1 = ON
DSI: DSI in Deep Power Down mode

2 RO X 0 = OFF
1 = ON
CSIB: CSIB in Deep Power Down mode

1 RO X 0 = OFF
1 = ON
CSIA: CSIA in Deep Power Down mode

0 RO X 0 = OFF
1 = ON
9.2.113 APBDEV_PMC_IO_DPD2_REQ_0
Second set of DPD requests due to additional rails.
Offset: 0x1c0 │ Read/Write: R/W │ Reset: 0x00000000 (0b00000000000000000000000000000000)
31:30 0x0 CODE: code of operation for all set bits

0 = IDLE
1 = DPD_OFF
2 = DPD_ON
29:27 0x0 NEW_RAILS: Reserved for future rails
SYS_DDC: for direcct DC pads

26 0x0 0 = OFF
1 = ON
LVDS: LVDS is in DPD by default

25 0x0 0 = OFF
1 = ON
24 0x0 DDR1_DATA: Defunct

0 = OFF
1 = ON
23 0x0 DDR1_CLK: Defunct

0 = OFF
1 = ON
22 0x0 DDR1_ADDR2_CMD: Defunct

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF


1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON
15 0x0 DISC_VTTGEN4: Defunct

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON
12 0x0 CSIE: Puts CSIE in/out of Deep Power Down mode

0 = OFF
1 = ON
11 0x0 CSID: Defunct

0 = OFF
1 = ON
10 0x0 CSIC: Defunct

0 = OFF
1 = ON
9 0x0 DSID: Puts DSID in/out of Deep Power Down mode

0 = OFF
1 = ON
8 0x0 DSIC: Puts DSIC in/out of Deep Power Down mode

0 = OFF
1 = ON
7 0x0 DSIB: Puts DSIB in/out of Deep Power Down mode

0 = OFF
1 = ON
6 0x0 HV: Puts HV rail in/out of Deep Power Down mode

0 = OFF
1 = ON
5 0x0 RES_RAIL:
0 = OFF
1 = ON
4 0x0 CAM: Puts the camera in/out of Deep Power Down mode
0 = OFF
1 = ON
3 0x0 SDMMC4: Puts SDMMC4 in/out of Deep Power Down mode

0 = OFF
1 = ON
2 0x0 SDMMC3:puts SDMMC3 in/out of Deep Power Down mode

0 = OFF
1 = ON
1 0x0 SDMMC1:puts SDMMC1 in/out of Deep Power Down mode

0 = OFF
1 = ON
0 0x0 PEX_CNTRL: Puts pex_cntrl in/out of Deep Power Down mode.

0 = OFF


1 = ON
9.2.114 APBDEV_PMC_IO_DPD2_STATUS_0
DPD2 Status
Offset: 0x1c4 │ Read/Write: R/W │ Reset: 0x02000000 (0bxx000010000000000000000000000000)
29:27 0x0 NEW_RAILS: Reserved for future rails
SYS_DDC: For direct DC pads

26 0x0 0 = OFF
1 = ON
LVDS: LVDS is in DPD by default

25 0x1 0 = OFF
1 = ON
24 0x0 DDR1_DATA: Defunct

0 = OFF
1 = ON
23 0x0 DDR1_CLK: XM1 _MCLK: Defunct

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON
12 0x0 CSIE:CSIE in/out of Deep Power Down mode

0 = OFF


1 = ON
11 0x0 CSID:CSID in/out of Deep Power Down mode

0 = OFF
1 = ON
10 0x0 CSIC:CSIC in/out of Deep Power Down mode

0 = OFF
1 = ON
9 0x0 DSID:DSID in/out of Deep Power Down mode

0 = OFF
1 = ON
8 0x0 DSIC:DSIC in/out of Deep Power Down mode

0 = OFF
1 = ON
7 0x0 DSIB: DSI in Deep Power Down mode

0 = OFF
1 = ON
6 0x0 HV: HV rail in/out of Deep Power Down mode

0 = OFF
1 = ON
5 0x0 RES_RAIL: reserved

0 = OFF
1 = ON
4 0x0 CAM: CAM in/out of Deep Power Down mode

0 = OFF
1 = ON
3 0x0 SDMMC4: SDMMC4 in/out of Deep Power Down mode

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON
0 0x0 PEX_CNTRL: PEX DPD status

0 = OFF
1 = ON
9.2.115 APBDEV_PMC_SEL_DPD_TIM_0
This timer guarantees proper timing spacing in hardware between the sel_dpd and e_dpd signals issued to pads.
A minimum of 200 ns is required, timer in APB/SYS clock.
Offset: 0x1c8 │ Read/Write: R/W │ Reset: 0x0000007f (0bxxxxxxxxxxxxxxxxxxxxxxxxx1111111)
SEL_DPD_TIM: Timer which separates e_dpd deassertion time from sel_dpd deassertion
6:0 0x7f
time in apb_clk units.
9.2.116 APBDEV_PMC_VDDP_SEL_0
Power set for new DDR pads. Safe value is 11.
Offset: 0x1cc │ Read/Write: R/W │ Reset: 0x00000003 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11)

1:0 0x3 DATA: VDDP sel bits to DDR pads
9.2.117 APBDEV_PMC_DDR_CFG_0
Package Type for CAR/PMC Control

Offset: 0x1d0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxx000000000000000000)
XM0_MCKE_B1_TRI: Tristate control for xm2_mcke_b_1_pad

17 0x0 0 = DISABLE
1 = ENABLE
XM0_MCKE_B0_TRI: Tristate control for xm2_mcke_b_0_pad

16 0x0 0 = DISABLE
1 = ENABLE
XM0_MCKE1_TRI: Tristate control for xm2_mcke_1_pad

15 0x0 0 = DISABLE
1 = ENABLE
XM0_MCKE0_TRI: Tristate control for xm2_mcke_0_pad

14 0x0 0 = DISABLE
1 = ENABLE
XM0_RESET_DPDIO_0: DPD output control for RESET pad

13 0x0 0 = DISABLE
1 = ENABLE
XM0_RESET_TRI: Tristate control for reset pad

12 0x0 0 = DISABLE
1 = ENABLE
11 0x0 XM1_MCLK_TRI: Defunct

0 = DISABLE
1 = ENABLE
10 0x0 XM0_MCLK_TRI: Defunct

0 = DISABLE
1 = ENABLE
9 0x0 XM1_TRI: Defunct

0 = DISABLE
1 = ENABLE
8 0x0 XM0_TRI: Defunct

0 = DISABLE
1 = ENABLE
7:4 0x0 RESET_SWIZZLE: Defunct
3 0x0 DDR_SPARE: Defunct
2 0x0 CHAN_SWIZZLE: Defunct

0 = DISABLE
1 = ENABLE
1 0x0 IF: Defunct

0 = LPDDR2
1 = DDR3
0 0x0 PKG: Defunct

0 = DISC
1 = POP

9.2.118 APBDEV_PMC_PLLM_WB0_OVERRIDE_FREQ_0
PLL WB Override Registers to Accelerate Warm Boot Time
Offset: 0x1dc │ Read/Write: R/W │ Reset: 0x0000010c (0bxxxxxxxxxxxxxxxx0000000100001100)
15:8 0x1 PLLM_DIVN: PLL feedback divider.
7:0 0xc PLLM_DIVM: PLL input divider.
9.2.119 APBDEV_PMC_TEST_PWRGATE_0
Force Test Power Gate Override Off/On
Offset: 0x1e0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx00000)
RESET_DEBUG: used for debug, assertion of reset will be disabled, if this bit is set
4 0x0 0 = OFF
1 = ON
DPD_ENABLE_DEBUG: used for debug, assertion of dpd_enable will be disabled if this

bit is set
3 0x0
0 = OFF
1 = ON
MAIN_CLAMP_DEBUG: used for debug, assertion of main clamp will be disabled if this bit
is set
2 0x0
0 = OFF
1 = ON
OP: FORCE_ON - force power gated partition to be powered, FORCE_OFF - force power
gating partition to be powered down
1:0 0x0 0 = NONE
1 = FORCE_ON
2 = FORCE_OFF
9.2.120 APBDEV_PMC_PWRGATE_TIMER_MULT_0
The time for each rail set by PWRGATE_TIMER_OFF will be multiplied by MULT for power-gating up/down any power-gated
region except CPU. In the CPU power-gated case, MULT_CPU will be used with PWRGATE_TIMER_CE* registers value. All
timers are in sys_clk units.
Offset: 0x1e4 │ Read/Write: R/W │ Reset: 0x0000001b (0bxxxxxxxxxxxxxxxxxxxxxxxxxx011011)
MULT_CPU:
0 = ONE
1 = TWO
5:3 0x3
2 = FOUR
3 = EIGHT
4 = SIXTEEN
MULT:
0 = ONE
1 = TWO
2:0 0x3 2 = FOUR
3 = EIGHT
4 = SIXTEEN

9.2.121 APBDEV_PMC_DSI_SEL_DPD_0
Register to control sel_dpd for the DSI pad. Allows driving LP0 value on the DSI pad beyond LP0 exit. This enables the DSI to
be programmed properly at LP0 exit while the LP0 value is still driven by the brick pad.
Offset: 0x1e8 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000)
SET_DSID:
3 0x0 0 = OFF
1 = ON
SET_DSIC:
2 0x0 0 = OFF
1 = ON
SET_DSIB:
1 0x0 0 = OFF
1 = ON
SET_DSIA:
0 0x0 0 = OFF
1 = ON
9.2.122 APBDEV_PMC_UTMIP_UHSIC_TRIGGERS_0
PMC trigger events for the UTMIP ports as well as the UHSIC port. Sleep walk clearing returns the walk pointer to 00, the first
entry in a USB line walk. This is the only way to return a pointer to 0.
Pad configuration captures a set of FLLS parameters prior to resting the port so their value can be retained in deep sleep.
The trigger should only happen on the fields that are set to TRIG (1) when writing. The returned read value should always be
all NULL fields.
The FORCE_WALK bits trigger a SLEEP.
Any value read back should be 0.
Triggers for USB Ports

Offset: 0x1ec │ Read/Write: R/W │ Reset: 0x0000XXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
UHSIC_CLR_WAKE_ALARM_P0: Clear wake event for UHSIC port 0

15 X 0 = NULL
1 = TRIG
UTMIP_CLR_WAKE_ALARM_P2: Clear wake event for UTMIP port 2

14 X 0 = NULL
1 = TRIG

13 X 0 = NULL
1 = TRIG

12 X 0 = NULL
1 = TRIG
UHSIC_FORCE_WALK_P0: Force pointer walk for UHSIC port 0

11 X 0 = NULL
1 = TRIG
UTMIP_FORCE_WALK_P2: Force pointer walk for UTMIP port 2

10 X 0 = NULL
1 = TRIG


9 X 0 = NULL
1 = TRIG

8 X 0 = NULL
1 = TRIG
UHSIC_RESERVED_P0: Reserved for UHSIC port 0

7 X 0 = NULL
1 = TRIG
UTMIP_CAP_CFG_P2: Capture pad configuration for UTMIP port 2

6 X 0 = NULL
1 = TRIG

5 X 0 = NULL
1 = TRIG

4 X 0 = NULL
1 = TRIG
UHSIC_CLR_WALK_PTR_P0: Clear sleep walk pointer for UHSIC port 0

3 X 0 = NULL
1 = TRIG
UTMIP_CLR_WALK_PTR_P2: Clear sleep walk pointer for UTMIP port 2

2 X 0 = NULL
1 = TRIG

1 X 0 = NULL
1 = TRIG

0 X 0 = NULL
1 = TRIG
9.2.123 APBDEV_PMC_UTMIP_UHSIC_SAVED_STATE_0
Save some critical information about USB port prior to entering DPD in a suspend state.
SPEED:
 HS - Suspend DPD was entered from a high speed mode, restore high speed at DPD exit
 FS - Suspend DPD was entered from a full speed mode, restore full speed at DPD exit
 LS - Suspend DPD was entered from a low speed mode, restore low speed at DPD exit
 RST - Reset Port, Hardware reset or DPD was not entered suspended bus, Reset and Re-enumerate port
SCRATCH -- save other critical information about the port, software choice.
Reset value should read 0x0F0F0F0F, reset should occur on Cold Hardware Reset only
Saved DPD State for all UTMIP and UHSIC Ports

Offset: 0x1f0 │ Read/Write: R/W │ Reset: 0x0f0f0f0f (0b00001111000011110000111100001111)
UHSIC_WAKE_EX_P0: Wake up on anything except a Particular Line Value

31 0x0 0 = OFF
1 = ON
30 0x0 UHSIC_IGNORE_MASTER_CFG_P0

29:25 0x7 UHSIC_SCRATCH_P0
UHSIC_MODE_P0: UHSIC Speed prior to DPD

24 0x1 0 = HS
1 = RST
UTMIP_WAKE_EX_P2: Wake up on anything except a Particular Line Value

23 0x0 0 = OFF
1 = ON
22 0x0 UTMIP_IGNORE_MASTER_CFG_P2
21:18 0x3 UTMIP_SCRATCH_P2
UTMIP_SPEED_P2: UTMIP Speed prior to DPD

0 = HS
17:16 0x3 1 = FS
2 = LS
3 = RST

15 0x0 0 = OFF
1 = ON

0 = HS
9:8 0x3 1 = FS
2 = LS
3 = RST

7 0x0 0 = OFF
1 = ON

0 = HS
1:0 0x3 1 = FS
2 = LS
3 = RST
9.2.124 APBDEV_PMC_UTMIP_PAD_CFG_0
Set of static configuration values for USB I/O pads under DPD mode. These were configuration values captured at a time prior
to entering DPD. These values are read only. Registers must take into account DFT.
I/O Pad Config for Port 0

Offset: 0x1f4 │ Read/Write: RO │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
29 X LSBIAS_SEL_P2: I/O pad LSBIAS_SEL for UTMIP P2
28 X LO_SPD_P2: I/O pad LO_SPD for UTMIP P2
27:26 X SPARE_P2: I/O pad SPARE1..0 for UTMIP P2
25:24 X FS_SLEW_P2: I/O pad FS_SLEW1..0 for UTMIP P2
23:22 X LS_FSLEW_P2: I/O pad LS_FSLEW1..0 for UTMIP P2
21:20 X LS_RSLEW_P2: I/O pad LS_RSLEW1..0 for UTMIP P2

9.2.125 APBDEV_PMC_UTMIP_TERM_PAD_CFG_0
Set of termination configuration values for USB I/O pads under DPD mode. These configuration values are programmed, not
captured, at a time prior to entering DPD. Capturing them would be complex because it would require costly synchronizers as
well as some logic. The range for RCTRL and TCTRL is 0 to 16.
These values need to be converted to a thermal encoding (only one 0 to 1 transition allowed in the word from MSB to LSB).
For example:
0 - 0000_0000_0000_0000
1 - 0000_0000_0000_0001
2 - 0000_0000_0000_0011
...
15 - 0111_1111_1111_1111
16 - 1111_1111_1111_1111
I/O Termination Configuration for all UTMIP Ports

Offset: 0x1f8 │ Read/Write: R/W │ Reset: 0x00000108 (0bxxxxxxxxxxxxxxxxxxxxxx0100001000)
9:5 0x8 TCTRL_VAL: HS termination calibration value, range 0 to 16
4:0 0x8 RCTRL_VAL: 1.5kOhm pull up calibration value, range 0 to 16
9.2.126 APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG_0
Register that configures the value of the line that could cause a wake-up event.
 ANY -- signifies any line change DM EDGE or DP EDGE for UTMIP.

 NONE -- signifies no wakeup possible.
One can use the two most significant bits (3:2) of the WAKE_VAL to 4x1 select whether:
 00: Check both bits for value on two LSB (1:0).

 01: Check bit DM (or strobe for HSIC) against bit 0

 10: Check bit DP (or DATA for HSIC) against bit 1

 11: Check for edge on DP against bit 1, edge on DM against bit 0
Sleep Walk Sequence Enables

Offset: 0x1fc │ Read/Write: R/W │ Reset: 0xc0c0c0c0 (0b11000000110000001100000011000000)
UHSIC_WAKE_VAL_P0: Line Value Wake Up Condition on UHSIC P0

0 = SD00
1 = SD01
2 = SD10
3 = SD11
4 = S0
31:28 0xc 5 = S1
8 = D0
10 = D1
12 = NONE
13 = SEDGE
14 = DEDGE
15 = ANY
27:25 0x0 UHSIC_RESERVED_P0: Reserved for later use for UHSIC P0
24 0x0 UHSIC_MASTER_ENABLE_P0: Enable use of master pins on UHSIC P0
UTMIP_WAKE_VAL_P2: Line Value Wake Up Condition on UTMIP P2

0 = SE0
1 = FSK
2 = FSJ
3 = SE1
4 = DM0
23:20 0xc 5 = DM1
8 = DP0
10 = DP1
12 = NONE
13 = DMEDGE
14 = DPEDGE
15 = ANY
19 0x0 UTMIP_TCTRL_USE_PMC_P2: Use PMC Saved TCTRL on UTMIP P2
18 0x0 UTMIP_RCTRL_USE_PMC_P2: Use PMC Saved RCTRL on UTMIP P2
17 0x0 UTMIP_FSLS_USE_PMC_P2: Use PMC Saved Pad config on UTMIP P2
16 0x0 UTMIP_MASTER_ENABLE_P2: Enable use of master pins on UTMIP P2
UTMIP_WAKE_VAL_P1: Line Value Wake Up Condition on UTMIP P1

0 = SE0
1 = FSK
2 = FSJ
3 = SE1
4 = DM0
15:12 0xc 5 = DM1
8 = DP0
10 = DP1
12 = NONE
13 = DMEDGE
14 = DPEDGE
15 = ANY
7:4 0xc UTMIP_WAKE_VAL_P0: Line Value Wake Up Condition on UTMIP P0


0 = SE0
1 = FSK
2 = FSJ
3 = SE1
4 = DM0
5 = DM1
8 = DP0
10 = DP1
12 = NONE
13 = DMEDGE
14 = DPEDGE
15 = ANY
9.2.127 APBDEV_PMC_UTMIP_UHSIC_SLEEPWALK_CFG_0
This register determines when sleep walking should take effect: upon a specific GPIO event, on any wake event, or on a line
value change.
It is also possible to force a sleep walk; see register UTMIP_UHSIC_TRIGGERS to force the event.

31 0x0 UHSIC_LINEVAL_WALK_EN_P0: Perform Walk on USB line value wake up for UHSIC P0
30 0x0 UHSIC_WAKE_WALK_EN_P0: Perform Walk on any chip wake up event for UHSIC P0
29 0x0 UHSIC_GPIO_WALK_EN_P0: Perform Walk on associated GPIO event for UHSIC P0
28:24 0x0 UHSIC_DESIGNATED_GPIO_P0: GPIO Number associated with UHSIC P0
23 0x0 UTMIP_LINEVAL_WALK_EN_P2: Perform Walk on USB line value wake up for UTMIP P2
22 0x0 UTMIP_WAKE_WALK_EN_P2: Perform Walk on any chip wake up event for UTMIP P2
21 0x0 UTMIP_GPIO_WALK_EN_P2: Perform Walk on associated GPIO event for UTMIP P2
20:16 0x0 UTMIP_DESIGNATED_GPIO_P2: GPIO Number associated with UTMIP P2

9.2.128 APBDEV_PMC_UTMIP_SLEEPWALK_P0_0
These registers hold the sequence of control values to the UTMIP pads on the four consecutive cycles of a walk. The pad pins
that are controlled are:
 MASTER_USBOP_RPD
 MASTER_USBON_RPD
 MASTER_USBOP_RPU
 MASTER_USBON_RPU
 MASTER_AP
 MASTER_AN
 MASTER_HIGHZ
For the walk to take effect at the pad, the MASTER_ENABLE pin must be set high in the config register. Otherwise the pad will
ignore the values.
If no walk is enabled or forced, then the walk pointer remains stuck on phase A. The walk pointer should use a 2 bit Gray code
so that Phase A is 00, Phase B is 01, Phase C is 11, and Phase D is 10. Once Phase D is reached, only a reset of the phase
pointer can bring it back to Phase A.
Four phases should be sufficient to handle most wake-up events.
Signaling Sequence for UTMIP Port 0 Wakeup

31 0x0 RESERVED_D: Phase D Unused Bit
30 0x0 HIGHZ_D: Phase D Enable Single Ended Drivers
29 0x1 AN_D: Phase D Drive Single Ended Value on D- line
28 0x0 AP_D: Phase D Drive Single Ended Value on D+ line
27 0x0 USBON_RPU_D: Phase D 1.5kOhm Pull up on D- Line
26 0x0 USBOP_RPU_D: Phase D 1.5kOhm Pull Up on D+ Line
25 0x1 USBON_RPD_D: Phase D 15kOhm Pull Down on D- Line
24 0x1 USBOP_RPD_D: Phase D 15kOhm Pull Down on D+ Line
23 0x0 RESERVED_C: Phase C Unused Bit
22 0x0 HIGHZ_C: Phase C Enable Single Ended Drivers
21 0x1 AN_C: Phase C Drive Single Ended Value on D- line
20 0x0 AP_C: Phase C Drive Single Ended Value on D+ line
19 0x0 USBON_RPU_C: Phase C 1.5kOhm Pull up on D- Line
18 0x0 USBOP_RPU_C: Phase C 1.5kOhm Pull Up on D+ Line
17 0x1 USBON_RPD_C: Phase C 15kOhm Pull Down on D- Line
16 0x1 USBOP_RPD_C: Phase C 15kOhm Pull Down on D+ Line
15 0x0 RESERVED_B: Phase B Unused Bit
14 0x0 HIGHZ_B: Phase B Enable Single Ended Drivers
13 0x1 AN_B: Phase B Drive Single Ended Value on D- line
12 0x0 AP_B: Phase B Drive Single Ended Value on D+ line

11 0x0 USBON_RPU_B: Phase B 1.5kOhm Pull up on D- Line
10 0x0 USBOP_RPU_B: Phase B 1.5kOhm Pull Up on D+ Line
9 0x1 USBON_RPD_B: Phase B 15kOhm Pull Down on D- Line
8 0x1 USBOP_RPD_B: Phase B 15kOhm Pull Down on D+ Line
7 0x0 RESERVED_A: Phase A Unused Bit
6 0x1 HIGHZ_A: Phase A Enable Single Ended Drivers
5 0x1 AN_A: Phase A Drive Single Ended Value on D- line
4 0x0 AP_A: Phase A Drive Single Ended Value on D+ line
3 0x0 USBON_RPU_A: Phase A 1.5kOhm Pull up on D- Line
2 0x0 USBOP_RPU_A: Phase A 1.5kOhm Pull Up on D+ Line
1 0x1 USBON_RPD_A: Phase A 15kOhm Pull Down on D- Line
0 0x1 USBOP_RPD_A: Phase A 15kOhm Pull Down on D+ Line

30 0x0 HIGHZ_D: Phase D Enable Single Ended Drivers
22 0x0 HIGHZ_C: Phase C Enable Single Ended Drivers
14 0x0 HIGHZ_B: Phase B Enable Single Ended Drivers

6 0x1 HIGHZ_A: Phase A Enable Single Ended Drivers

30 0x0 HIGHZ_D: Phase D Enable Single Ended Drivers, active low
22 0x0 HIGHZ_C: Phase C Enable Single Ended Drivers, active low
14 0x0 HIGHZ_B: Phase B Enable Single Ended Drivers, active low

6 0x1 HIGHZ_A: Phase A Enable Single Ended Drivers, active low
9.2.131 APBDEV_PMC_UHSIC_SLEEPWALK_P0_0
These registers hold the sequence of control values to the UTMIP pads on the four consecutive cycles of a walk. The pad pins
 STROBE_RPD
 DATA_RPD
 STROBE_RPU
 DATA_RPU
At this time there are no STROBE, DATA ports that should be driven by the host. So these outputs from the module should be
left unconnected until a time that departure may be implemented.
Signaling Sequence for UHSIC Port 0 Wakeup

31:28 0x0 RESERVED_D: Phase D Unused Bit
27 0x0 UHSIC_DATA_RPU_D: Phase D Pull up on DATA Line
26 0x1 UHSIC_STROBE_RPU_D: Phase D Pull Up on STROBE Line
25 0x1 UHSIC_DATA_RPD_D: Phase D Pull Down on DATA Line
24 0x0 UHSIC_STROBE_RPD_D: Phase D Pull Down on STROBE Line
23:20 0x0 RESERVED_C: Phase C Unused Bit
19 0x0 UHSIC_DATA_RPU_C: Phase C Pull up on DATA Line
18 0x1 UHSIC_STROBE_RPU_C: Phase C Pull Up on STROBE Line
17 0x1 UHSIC_DATA_RPD_C: Phase C Pull Down on DATA Line
16 0x0 UHSIC_STROBE_RPD_C: Phase C Pull Down on STROBE Line
15:12 0x0 RESERVED_B: Phase B Unused Bit
11 0x0 UHSIC_DATA_RPU_B: Phase B Pull up on DATA Line
10 0x1 UHSIC_STROBE_RPU_B: Phase B Pull Up on STROBE Line
9 0x1 UHSIC_DATA_RPD_B: Phase B Pull Down on DATA Line
8 0x0 UHSIC_STROBE_RPD_B: Phase B Pull Down on STROBE Line

7:4 0x0 RESERVED_A: Phase A Unused Bit
3 0x0 UHSIC_DATA_RPU_A: Phase A Pull up on DATA Line
2 0x1 UHSIC_STROBE_RPU_A: Phase A Pull Up on STROBE Line
1 0x1 UHSIC_DATA_RPD_A: Phase A Pull Down on DATA Line
0 0x0 UHSIC_STROBE_RPD_A: Phase A Pull Down on STROBE Line
9.2.132 APBDEV_PMC_UTMIP_UHSIC_STATUS_0
Read-only register that provides current walk pointer information as well as line value.
Status of UTMIP UHSIC Wake-up Circuitry

Offset: 0x214 │ Read/Write: RO │ Reset: 0x000XXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
19 X UHSIC_WAKE_ALARM_P0: A wake event occurred on UHSIC port 0
18 X UTMIP_WAKE_ALARM_P2: A wake event occurred on UTMIP port 2
15 X DATA_VAL_P0: Value of DATA line detector for UHSIC port 0
14 X STROBE_VAL_P0: Value of STROBE line detector for UHSIC port 0
13 X USBON_VAL_P2: Value of D- line detector for UTMIP port 2
12 X USBOP_VAL_P2: Value of D+ line detector for UTMIP port 2
7:6 X UHSIC_WALK_PTR_P0: Walk pointer for UHSIC port 0
5:4 X UTMIP_WALK_PTR_P2: Walk pointer for UTMIP port 2
3:2 X UTMIP_WALK_PTR_P1: Walk pointer for UTMIP port 1
1:0 X UTMIP_WALK_PTR_P0: Walk pointer for UMTIP port 0
9.2.133 APBDEV_PMC_UTMIP_UHSIC_FAKE_0
Instead of using the pad value for USBOP_VAL, USBON_VAL, STROBE_VAL, DATA_VAL, VBUS_WAKEUP, ID from the
UTMIP and HSIC pads, force a 2x1 mux at the input of the PMC pad macro when fake values are enabled. This could the
useful feature of putting a line at rest when needed. It also has important debug merits. This mux should be placed in front of
the NP synchronizer for these signals (saved power on the synchronizer). This will have to be waived in our sync checks.
Fake the Line Value for the PMC Pad Macro

Offset: 0x218 │ Read/Write: R/W │ Reset: 0x01111111 (0bxxxx0001000100010001000100010001)
27 0x0 UTMIP_ID_FAKE_EN_P2: Enable the fake ID value for UTMIP P2

26 0x0 UTMIP_ID_FAKE_VAL_P2: Fake ID value for UTMIP P2
25 0x0 UTMIP_VBUS_FAKE_EN_P2: Enable the fake VBUS WAKEUP value for UTMIP P2
24 0x1 UTMIP_VBUS_FAKE_VAL_P2: Fake VBUS WAKEUP value for UTMIP P2
UHSIC_FAKE_DATA_EN_P0: Enable the fake line value for DATA for the PMC pad
15 0x0
macro for UHSIC P0
UHSIC_FAKE_STROBE_EN_P0: Enable the fake line value for STROBE for the PMC
14 0x0
pad macro for UHSIC P0
UHSIC_FAKE_DATA_VAL_P0: Fake line value for DATA for the PMC pad macro for
13 0x0
UHSIC P0
UHSIC_FAKE_STROBE_VAL_P0: Fake line value for STROBE for the PMC pad macro
12 0x1
for UHSIC P0
UTMIP_FAKE_USBON_EN_P2: Enable the fake line value for D- for the PMC pad macro
11 0x0
for UTMIP P2
UTMIP_FAKE_USBOP_EN_P2: Enable the fake line value for D+ for the PMC pad macro
10 0x0
for UTMIP P2
UTMIP_FAKE_USBON_VAL_P2: Fake line value for D- for the PMC pad macro for
9 0x0
UTMIP P2
UTMIP_FAKE_USBOP_VAL_P2: Fake line value for D+ for the PMC pad macro for
8 0x1
UTMIP P2
7 0x0
for UTMIP P1
6 0x0
for UTMIP P1
5 0x0
UTMIP P1
4 0x1
UTMIP P1
3 0x0
for UTMIP P0
2 0x0
for UTMIP P0
1 0x0
UTMIP P0
0 0x1
UTMIP P0





Scratch Register
SCRATCH43: General-purpose register storage. Currently used for power-gating progress

31:0 X
status in RTAPI.

Scratch Register
Offset: 0x230 │ Read/Write: R/W V Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
SCRATCH44: General-purpose register storage. Currently used for storing ARM SP in

31:0 X
power-gating by RTAPI.
Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register

Scratch Register
Scratch Register
Scratch Register
This register is valid in I2C mode. It is used for the WATCHDOG_RESET I2C command. In GPIO and SPI modes, this register
is reserved.
31:16 X SCRATCH_PMU_A_0_HIWORD_RANGE
15:0 X SCRATCH_PMU_A_0_LOWORD_RANGE
Scratch Register
This register is valid in I2C mode. It is used for the WATCHDOG_RESET I2C command. In GPIO and SPI modes, this register
is reserved.
31 X SCRATCH_PMU_B_0_RST_ENABLE_RANGE: Reset enable.
30 X SCRATCH_PMU_B_0_CNTLR_TYPE_RANGE: This bit is reserved. Set it to 0.
SCRATCH_PMU_B_0_CNTLR_ID_RANGE: Controller ID.

0: I2C1
1: I2C2
29:27 X
2: I2C3
3: I2C4
4: I2C PMU
SCRATCH_PMU_B_0_PINMUX_RANGE. Pinmux Range. Refer to “Pinmux Support” in

26:24 X
the Boot Process section for the encoding of this field.
SCRATCH_PMU_B_0_CHKSUM_RANGE: Checksum Range. Every byte in this register

23:16 X must add to 0. Refer to “Checksum Calculation” in the Boot Process section for the
encoding of this field.

15 X SCRATCH_PMU_B_0_16BITOP_RANGE: 16-Bit Op.
14 X SCRATCH_PMU_B_0_USE_GPIO_RANGE. Set this bit to 0.
13:7 X Reserved. Set these bits to 0.
6:0 X SCRATCH_PMU_B_0_I2CSLV1_RANGE: I2C Slave Address.
Scratch Register
This register is valid in I2C mode. It is used for the TSENSE_RESET I2C command. In GPIO and SPI modes, this register is
reserved.
31:16 X SCRATCH_PMU_A_0_HIWORD_RANGE
15:0 X SCRATCH_PMU_A_0_LOWORD_RANGE
Scratch Register
This register is valid in I2C mode. It is used for the TSENSE_RESET I2C command. In GPIO and SPI modes, this register is
reserved.
31 X SCRATCH_PMU_B_0_RST_ENABLE_RANGE: Reset enable.
30 X SCRATCH_PMU_B_0_CNTLR_TYPE_RANGE: This bit is reserved. Set it to 0.
SCRATCH_PMU_B_0_CNTLR_ID_RANGE: Controller ID.

0: I2C1
1: I2C2
29:27 X
2: I2C3
3: I2C4
4: I2C PMU
SCRATCH_PMU_B_0_PINMUX_RANGE. Pinmux Range. Refer to “Pinmux Support” in

26:24 X
the Boot Process section for the encoding of this field.
SCRATCH_PMU_B_0_CHKSUM_RANGE: Checksum Range. Every byte in this register

23:16 X must add to 0. Refer to “Checksum Calculation” in the Boot Process section for the
encoding of this field.
15 X SCRATCH_PMU_B_0_16BITOP_RANGE: 16-Bit Op.
14 X SCRATCH_PMU_B_0_USE_GPIO_RANGE. Set this bit to 0.
13:7 X Reserved. Set these bits to 0.
6:0 X SCRATCH_PMU_B_0_I2CSLV1_RANGE: I2C Slave Address.

9.2.151 APBDEV_PMC_SCRATCH0_ECO_0
Scratch Register
31 0x0 CAR_USE_NEW_LP0_EXIT_SEQ: Reserved.
30:0 0x0 ECO0: Reserved.
9.2.152 APBDEV_PMC_POR_DPD_CTRL_0
Offset: 0x264 │ Read/Write: R/W │ Reset: 0x80000003 (0b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxx11)
MEM0_HOLD_CKE_LOW_OVR: Register control to pull CKE low. Using

31 0x1
HOLD_CKE_LOW to guarantee that CKE stays low when DDR I/O rails are ramping up.
1 0x1 MEM0_ADDR1_CLK_SEL_DPD: sets sel_dpd to clock buffer.
0 0x1 MEM0_ADDR0_CLK_SEL_DPD: sets sel_dpd to clock buffer.
Scratch Register
31:0 0x0 ECO2: Reserved.
9.2.154 APBDEV_PMC_UTMIP_UHSIC_LINE_WAKEUP_0
Offset: 0x26c │ Read/Write: R/W │ Reset: 0x0000000f (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111)
3 0x1 UHSIC_LINE_WAKEUP_EN_P0: enables latching line wakeup event on UHSIC p0
2 0x1 UTMIP_LINE_WAKEUP_EN_P2: enables latching line wakeup event on UTMIP p2
9.2.155 APBDEV_PMC_UTMIP_BIAS_MASTER_CNTRL_0
Offset: 0x270 │ Read/Write: R/W │ Reset: 0x0000000d (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx1101)
UTMIP_BIAS_MASTER_AWAKE_AND: When not PROGRAMMABLE and E_DPD=0,

3 0x1
AND the MASTER_ENABLE of all IO ports for bias cell. If not AND or OR, force to 0.
UTMIP_BIAS_MASTER_AWAKE_OR: When not PROGRAMMABLE and E_DPD=0, OR

2 0x1
the MASTER_ENABLE of all IO ports for bias cell
UTMIP_BIAS_MASTER_PROG_VAL: When PROGRAMMABLE, this is the value to

1 0x0
program too
UTMIP_BIAS_MASTER_PROG_CTRL: MASTER_ENABLE pin uses a programmable

0 0x1
value on BIAS pad, at all times

9.2.156 APBDEV_PMC_UTMIP_MASTER_CONFIG_0
MASTER_CONFIG selects the MASTER function's mode of operation, in this case:
 0 for 500 µA usage

 1 for smaller current usage when driving.
Offset: 0x274 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000)
3 0x0 UHSIC_PWR_P0: enables UHSIC p0 low power mode
2 0x0 UTMIP_PWR_P2: enables UTMIP p2 low power mode
9.2.157 APBDEV_PMC_TD_PWRGATE_INTER_PART_TIMER_0
TD Power-Gating Timing Between Partition Power-Gating

Offset: 0x278 │ Read/Write: R/W │ Reset: 0x0000000f (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111)
3:0 0xf DATA: timing between consecutive partitions
9.2.158 APBDEV_PMC_UTMIP_UHSIC2_TRIGGERS_0
PMC trigger events for the UTMIP ports as well as the UHSIC port. Sleep walk clearing returns the walk pointer to 00, the first
entry in a USB line walk. This is the only way to return a pointer to 0.
Pad configuration capture a set of FLLS parameters prior to resting the port so their value can be retained in deep sleep.
The trigger should only happen on the fields that are set to TRIG (1) when writing. Returned read value should always be all
NULL fields. The FORCE_WALK bits trigger a SLEEP
This does not need to be a real register, so it should not consume much area. Any value read back should be 0.
Triggers for USB Ports

Offset: 0x27c │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
3 X UHSIC_CLR_WAKE_ALARM_P1: Clear wake event for UHSIC port 0

0 = NULL
1 = TRIG
2 X UHSIC_FORCE_WALK_P1: Force pointer walk for UHSIC port 0

0 = NULL
1 = TRIG
1 X UHSIC_RESERVED_P1: Reserved for UHSIC port 0

0 = NULL
1 = TRIG
0 X UHSIC_CLR_WALK_PTR_P1: Clear sleep walk pointer for UHSIC port 1

0 = NULL
1 = TRIG

9.2.159 APBDEV_PMC_UTMIP_UHSIC2_SAVED_STATE_0
Save some critical information about USB port prior to entering DPD in a suspend state.
SPEED
 HS: Suspend DPD was entered from a high speed mode, restore high speed at DPD exit
 FS: Suspend DPD was entered from a full speed mode, restore full speed at DPD exit
 LS: Suspend DPD was entered from a low speed mode, restore low speed at DPD exit
 RST: Reset Port, Hardware reset or DPD was not entered suspended bus, Reset and Re-enumerate port
SCRATCH -- Save other critical information about the port, software choice. Reset value should read 0x0F0F0F0F, reset
should occur on Cold Hardware Reset only
Saved DPD State for all UTMIP and UHSIC Ports

7 0x0 UHSIC_WAKE_EX_P1: Wake up on anything except a particular line value

0 = OFF
1 = ON
6 0x0 UHSIC_IGNORE_MASTER_CFG_P1
5:1 0x3 UHSIC_SCRATCH_P1
0 0x1 UHSIC_MODE_P1: UHSIC Speed prior to DPD

0 = HS
1 = RST
9.2.160 APBDEV_PMC_UTMIP_UHSIC2_SLEEP_CFG_0
This register configures the value of the line that could cause a wake-up event.
 ANY: signifies any line change DM EDGE or DP EDGE for UTMIP.

 NONE: signifies no wake-up possible.
One can use the two most significant bits (3:2) of the WAKE_VAL to 4x1 select whether:
 00: Check both bits for value on two LSB (1:0).

 01: Check bit DM (or strobe for HSIC) against bit 0
 10: Check bit DP (or DATA for HSIC) against bit 1
 11: Check for edge on DP against bit 1, edge on DM against bit 0

Offset: 0x284 │ Read/Write: R/W │ Reset: 0x000000c0 (0bxxxxxxxxxxxxxxxxxxxxxxxx11000000)
7:4 0xc UHSIC_WAKE_VAL_P1: Line Value Wake Up Condition on UHSIC P1

0 = SD00
1 = SD01
2 = SD10
3 = SD11
4 = S0
5 = S1
8 = D0
10 = D1
12 = NONE


13 = SEDGE
14 = DEDGE
15 = ANY
3:1 0x0 UHSIC_RESERVED_P1: Reserved for later use for UHSIC P1
0 0x0 UHSIC_MASTER_ENABLE_P1: Enable use of master pins on UHSIC P1
9.2.161 APBDEV_PMC_UTMIP_UHSIC2_SLEEPWALK_CFG_0
This register determines when sleep walking should take effect: upon a specific GPIO event, on any wake event, or on a line
value change.
Note that it is also possible to force a sleep walk: see register UTMIP_UHSIC_TRIGGERS to force the event.

7 0x0 UHSIC_LINEVAL_WALK_EN_P1: Perform walk on USB line value wake up for UHSIC
P1
6 0x0 UHSIC_WAKE_WALK_EN_P1: Perform walk on any chip wake up event for UHSIC P1
5 0x0 UHSIC_GPIO_WALK_EN_P1: Perform walk on associated GPIO event for UHSIC P1
4:0 0x0 UHSIC_DESIGNATED_GPIO_P1: GPIO Number associated with UHSIC P1
9.2.162 APBDEV_PMC_UHSIC2_SLEEPWALK_P1_0
This register holds the sequence of control values to the UTMIP pads on the four consecutive cycles of a walk. The pad pins
 STROBE_RPD
 DATA_RPD
 STROBE_RPU
 DATA_RPU
At this time there are no STROBE, DATA ports that should be driven by the host. So these outputs from the module should be
left dangling (unconnected) until a time that feature may be implemented.
Signaling Sequence for UHSIC Port 0 Wakeup

31:28 0x0 RESERVED_D: Phase D Unused Bit
27 0x0 UHSIC_DATA_RPU_D: Phase D Pull up on DATA Line
26 0x1 UHSIC_STROBE_RPU_D: Phase D Pull Up on STROBE Line
25 0x1 UHSIC_DATA_RPD_D: Phase D Pull Down on DATA Line
24 0x0 UHSIC_STROBE_RPD_D: Phase D Pull Down on STROBE Line
23:20 0x0 RESERVED_C: Phase C Unused Bit
19 0x0 UHSIC_DATA_RPU_C: Phase C Pull up on DATA Line
18 0x1 UHSIC_STROBE_RPU_C: Phase C Pull Up on STROBE Line

17 0x1 UHSIC_DATA_RPD_C: Phase C Pull Down on DATA Line
16 0x0 UHSIC_STROBE_RPD_C: Phase C Pull Down on STROBE Line
15:12 0x0 RESERVED_B: Phase B Unused Bit
11 0x0 UHSIC_DATA_RPU_B: Phase B Pull up on DATA Line
10 0x1 UHSIC_STROBE_RPU_B: Phase B Pull Up on STROBE Line
9 0x1 UHSIC_DATA_RPD_B: Phase B Pull Down on DATA Line
8 0x0 UHSIC_STROBE_RPD_B: Phase B Pull Down on STROBE Line
7:4 0x0 RESERVED_A: Phase A Unused Bit
3 0x0 UHSIC_DATA_RPU_A: Phase A Pull up on DATA Line
2 0x1 UHSIC_STROBE_RPU_A: Phase A Pull Up on STROBE Line
1 0x1 UHSIC_DATA_RPD_A: Phase A Pull Down on DATA Line
0 0x0 UHSIC_STROBE_RPD_A: Phase A Pull Down on STROBE Line
9.2.163 APBDEV_PMC_UTMIP_UHSIC2_STATUS_0
Read-only register that provides current walk pointer information as well as the line value.
Status of UTMIP UHSIC Wakeup Circuitry

4 X UHSIC_WAKE_ALARM_P1: A wake event occurred on UHSIC port 1
3 X DATA_VAL_P1: Value of DATA line detector for UHSIC port 1
2 X STROBE_VAL_P1: Value of STROBE line detector for UHSIC port 1
1:0 X UHSIC_WALK_PTR_P1: Walk pointer for UHSIC port 0
9.2.164 APBDEV_PMC_UTMIP_UHSIC2_FAKE_0
Instead of using the pad value for USBOP_VAL, USBON_VAL, STROBE_VAL, DATA_VAL, VBUS_WAKEUP, ID from the
UTMIP and HSIC pads, force a 2x1 mux at the input of the PMC pad macro when fake values are enabled. This could the
useful feature of putting a line at rest when needed. It also has important debug merits. This mux should be placed in front of
the NP synchronizer for these signals (saved power on the synchronizer). This will have to be waived in our sync checks.
Fake the Line Value for the PMC Pad Macro

Offset: 0x294 │ Read/Write: R/W │ Reset: 0x00000001 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx0001)
3 0x0 UHSIC_FAKE_DATA_EN_P1: Enable the fake line value for DATA for the PMC pad
macro for UHSIC P0
2 0x0 UHSIC_FAKE_STROBE_EN_P1: Enable the fake line value for STROBE for the PMC
pad macro for UHSIC P0
1 0x0 UHSIC_FAKE_DATA_VAL_P1: Fake line value for DATA for the PMC pad macro for
UHSIC P0
0 0x1 UHSIC_FAKE_STROBE_VAL_P1: Fake line value for STROBE for the PMC pad macro
for UHSIC P0

9.2.165 APBDEV_PMC_UTMIP_UHSIC2_LINE_WAKEUP_0
0 0x1 UHSIC_LINE_WAKEUP_EN_P1: enables latching line wake-up event on UHSIC P1
9.2.166 APBDEV_PMC_UTMIP_MASTER2_CONFIG_0
MASTER_CONFIG selects the MASTER functions mode of operation, in this case 0 for 500uA usage, 1 for smaller current
usage when driving.
0 0x0 UHSIC_PWR_P1: enables UHSIC P1 low power mode
9.2.167 APBDEV_PMC_UTMIP_UHSIC_RPD_CFG_0
Offset: 0x2a0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxx000000000)
8 0x0 WEAKPD_ANYTIME_P2
7 0x0 DP_WEAKPD_CFG_P2
6 0x0 DM_WEAKPD_CFG_P2
Offset: 0x2a4 │ Read/Write: R/W │ Reset: 0x000000ff (0bxxxxxxxxxxxxxxxxxxxxxxxx11111111)
Offset: 0x2a8 │ Read/Write: R/W │ Reset: 0xffffffff (0b11111111111111111111111111111111)
31:24 0xff DISB: Mask DISB rail
23:16 0xff DIS: Mask DIS rail
15:8 0xff C1NC: Mask C1NC rail
7:0 0xff C0NC: Mask C0NC rail

Offset: 0x2ac │ Read/Write: R/W │ Reset: 0xffffffff (0b11111111111111111111111111111111)
31:24 0xff SOR: Mask SOR rail
23:16 0xff XUSBC: Mask XUSBC rail
15:8 0xff XUSBB: Mask XUSBB rail
7:0 0xff XUSBA: Mask XUSBA rail
9.2.171 APBDEV_PMC_PLLM_WB0_OVERRIDE2_0
Offset: 0x2b0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxx0000000000000000000000000000)
27 0x0 DIV2: New divide by 2
26 0x0 KVCO: KVCO/VCO gain
25:24 0x0 KCP: Charge pump control
23:0 0x0 SETUP: Setup
9.2.172 APBDEV_PMC_TSC_MULT_0
Offset: 0x2b4 │ Read/Write: R/W │ Reset: 0x000016e0 (0bxxxxxxxxxxxx000x0001011011100000)
19:17 RW 0x0 TICK_SEL: This bit selects one of the six binary time stamp counter bits.
0 = BIT0
1 = BIT1
2 = BIT2
3 = BIT3
4 = BIT4
5 = BIT5
16 RO X FREQ_STS: Clock frequency being used for counter.

0 = Fast (i.e., oscillator frequency).
1 = Slow (i.e., 32 kHz).
When the PMC_DPD_ENABLE[TSC_MULT_EN] bit is set to '1', the PMC waits for first
rising edge on the slow clock before switching the counter to the slow clock. This status
is also set at the first rising edge of the slow clock (to indicate the change of clock for
counter).
15:0 RW 0x16e0 MULT_VAL: TSC multiply value (default based on 12 MHz oscillator).Value is (osc-freq
* 16 / 32.768 kHz) when the oscillator is disabled and the TSC runs at the 32 kHz clock.
For example, for a 12 MHz oscillator, VALUE = 5856.
9.2.173 APBDEV_PMC_CPU_VSENSE_OVERRIDE_0
Offset: 0x2b8 │ Read/Write: R/W │ Reset: 0x0000001f (0bxxxxxxxxxxxxxxxxxxxxxxxxxx011111)
5 0x0 VDD: VDD sensing override.
4 0x1 C0NC: C0NC VVDD partition sensing override.
3 0x1 CE3:CE3 VVDD partition sensing override.

9.2.174 APBDEV_PMC_GLB_AMAP_CFG_0
This register configures some of the address apertures (in CCPLEX-AXD) to be MMIO or DRAM. Each bit is used to
configurable one of the address aperture. For each bit 0=>MMIO and 1=>DRAM.
By default, all configurable apertures are MMIO address space. But they can be configured (at boot time) to be DRAM by
programming this register. This register can be write-disabled (by the PMC_SEC_DISABLE register). The bits of this register
are used as follows.
GLB_AMAP_CFG
Offset: 0x2bc │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxx000000000000000000)
17 0x0 IROM_HIVEC aperture: Defunct

0 = MMIO
1 = DRAM
16 0x0 AHB_A2_RSVD aperture:

0 = MMIO
1 = DRAM
15 0x0 AHB_A1_RSVD aperture:

0 = MMIO
1 = DRAM
14 0x0 AHB_A1 aperture:

0 = MMIO
1 = DRAM
13 0x0 APB_RSVD aperture:

0 = MMIO
1 = DRAM
12 0x0 EXTIO_RSVD aperture:

0 = MMIO
1 = DRAM
11 0x0 PPSB_RSVD aperture:

0 = MMIO
1 = DRAM
10 0x0 GART_GPU aperture:

0 = MMIO
1 = DRAM
9 0x0 GFX_HOST_RSVD aperture:

0 = MMIO
1 = DRAM
8 0x0 VERIF_RSVD aperture:

0 = MMIO
1 = DRAM
7 0x0 NOR_A3 aperture:

0 = MMIO
1 = DRAM

0 = MMIO
1 = DRAM


0 = MMIO
1 = DRAM
4 0x0 IRAM_RSVD aperture:

0 = MMIO
1 = DRAM
3 0x0 PCIE_A3 aperture:

0 = MMIO
1 = DRAM

0 = MMIO
1 = DRAM

0 = MMIO
1 = DRAM
0 0x0 IROM_LOVEC aperture:

0 = MMIO
1 = DRAM
9.2.175 APBDEV_PMC_STICKY_BITS_0
Offset: 0x2c0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxx000000000)
VI: This bit is set to '1' only by a write of '1'. All other writes are ignored. Once it is set
8 0x0 to '1', it remains '1' and only resets by a system reset (same reset that resets the
main PMC).This bit is sent to the VI via a sideband signal.
CDD_EN: Customer Denver DFD Enable. This bit can only be written to during
secure_boot_mode. It is reset by the main PMC reset. This bit value drives the
7 0x0 cust_denver_dfd_en signal to CCPLEX.
0: DFD disabled
1: DFD enabled
6 0x0 JTAG_STS: Secure Sticky One bit to propagate JTAG enable/disable across
LP0.This bit is set to '1' only by a secure write of '1'. All other writes are ignored. Once
it is set to '1', it remains '1' and only resets by a system reset (same reset that resets
the main PMC).
0 = ENABLE
1 = DISABLE
5 0x0 VDE4:See VDE0 description
1 0x0 VDE0: This bit is set to '1' only by a write of '1'. All other writes are ignored. Once it is
set to '1', it remains '1' and only resets by system reset (same resets which resets
main PMC).This bit is send to VDE via a sideband signal.
0 0x0 HDA_LPBK_DIS: Sticky one bit to disable the loopback in HDA codec.
This bit is set to ‘1’ only by a write of ‘1’. All other writes are ignored. Once it is set to
‘1’, it remains ‘1’ and only resets by system reset (the same reset which resets the
main PMC).

9.2.176 APBDEV_PMC_SEC_DISABLE2_0
Offset: 0x2c4 │ Read/Write: R/W │ Reset: 0x00000000 (0b00000000000000000000000000000000)
31 0x0 READ23: disable reads from secure register 23

0 = OFF
1 = ON
30 0x0 WRITE23: disable writes to secure register 23

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON


0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON

0 = OFF
1 = ON
9.2.177 APBDEV_PMC_WEAK_BIAS_0
Offset: 0x2c8 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxx000000000000000000)
17:16 0x0 XM0_DATA1: mem0_data1_vttgen_4_6_pad, mem0_data1_vttgen_5_7_pad
15:14 0x0 XM0_ADDR1: mem0_addr1_vttgen_0_pad, mem0_addr2_vttgen_0_pad
13:12 0x0 XM0_CLK_B: Defunct

11:10 0x0 XM0_DATA0: mem0_data0_vttgen_0_2_pad, mem0_data0_vttgen_1_3_pad
9:8 0x0 EMMC
7:6 0x0 XM1_EXCLK: Defunct
5:4 0x0 XM1_CLK: Defunct
3:2 0x0 XM0_ADDR0: mem0_addr0_vttgen_0_pad,mem0_addr3_vttgen_0_pad
1:0 0x0 XM0_CLK: weak_bias controls for CH0 VTTGEN for clk -
mem0_mclk0_vttgen_0_pad
9.2.178 APBDEV_PMC_REG_SHORT_0
Offset: 0x2cc │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxx00000000000000000000)
19 0x0 DPD_VAL_XM1_DATA: Defunct
18 0x0 DPD_VAL_XM1_ADDR1: Defunct
DPD_VAL_XM0_DATA1: reg_short value during DPD operation for

17 0x0
mem0_data1_vttgen_4_6_pad, mem0_data1_vttgen_5_7_pad
DPD_VAL_XM0_ADDR1: reg_short value during DPD operation for

16 0x0
mem0_addr1_vttgen_0_pad, mem0_addr2_vttgen_0_pad
15 0x0 VAL_XM1_DATA: Defunct
14 0x0 VAL_XM1_ADDR1: Defunct
VAL_XM0_DATA1: reg_short value during normal operation for

13 0x0
VAL_XM0_ADDR1: reg_short value during normal operation for

12 0x0
mem0_addr1_vttgen_0_pad, mem0_addr2_vttgen_0_pad
DPD_VAL_XM0_CLK_B: reg_short value during DPD operation for

11 0x0
mem0_mclk1_vttgen_0_pad - DEFUNCT, this pad was removed
DPD_VAL_XM0_DATA0: reg_short value during DPD operation for

10 0x0
VAL_XM0_CLK_B: reg_short value during normal operation for

9 0x0
mem0_mclk1_vttgen_0_pad - DEFUNCT, this pad was removed
VAL_XM0_DATA0: reg_short value during normal operation for

8 0x0
7 0x0 DPD_VAL_XM1_EXCLK: Defunct
6 0x0 DPD_VAL_XM1_CLK: Defunct
5 0x0 DPD_VAL_XM0_ADDR0: reg_short value during DPD operation for

mem0_addr0_vttgen_0_pad,mem0_addr3_vttgen_0_pad
4 0x0 DPD_VAL_XM0_CLK: reg_short value during DPD operation for

3 0x0 VAL_XM1_EXCLK: Defunct
2 0x0 VAL_XM1_CLK: Defunct
1 0x0 VAL_XM0_ ADDR0: reg_short value during normal operation for

mem0_addr0_vttgen_0_pad,mem0_addr3_vttgen_0_pad
0 0x0 VAL_XM0_CLK: reg_short value during normal operation for


9.2.179 APBDEV_PMC_PG_MASK_ANDOR_0
Power Gate Mask AND (for force power-gating) or OR (for force power-ungating) the mask value comes from the
corresponding PG_MASK* register
Offset: 0x2d0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxx00000000000x0000000x00000)
IRAM:
24 0x0 0 = AND
1 = OR
VIC:
23 0x0 0 = AND
1 = OR
22 0x0 XUSBC: Used as AND or OR override for XUSBC.

0 = AND
1 = OR
21 0x0 XUSBB: Used as AND or OR override for XUSBB.

0 = AND
1 = OR
20 0x0 XUSBA: Used as AND or OR override for XUSBA.

0 = AND
1 = OR
19 0x0 DISB: Used as AND or OR override for DISB partition.

0 = AND
1 = OR
18 0x0 DIS: Used as AND or OR override for DIS partition.

0 = AND
1 = OR
SOR:
17 0x0 0 = AND
1 = OR
16 0x0 C1NC: Used as AND or OR override for Cluster 1 Non-CPU partition.

0 = AND
1 = OR
15 0x0 C0NC: Used as AND or OR override for Cluster 0 Non-CPU partition.

0 = AND
1 = OR
14 0x0 CE0: Used as AND or OR override for CPU0 partition.

0 = AND
1 = OR
12 0x0 CELP: Used as AND or OR override for CELP partition.

0 = AND
1 = OR
11 0x0 CE3: Used as AND or OR override for CE3 partition.

0 = AND
1 = OR

0 = AND
1 = OR

0 = AND
1 = OR
SAX:
8 0x0 0 = AND
1 = OR

7 0x0 HEG: Used as AND or OR override for HEG partition.

0 = AND
1 = OR
6 0x0 MPE: Used as AND or OR override for MPE partition.

0 = AND
1 = OR
4 0x0 VDE: Used as AND or OR override for VDE0 partition.

0 = AND
1 = OR
PCX:
3 0x0 0 = AND
1 = OR
2 0x0 VE: Used as AND or OR override for VE partition.

0 = AND
1 = OR
1 0x0 TD: Used as AND or OR override for TD.

0 = AND
1 = OR
Note: The PMC generates sleep enables that are active High (that is, 1 = power on).
0 0x0 RESERVED:
0 = AND
1 = OR
9.2.180 APBDEV_PMC_GPU_RG_CNTRL_0
GPU Rail Gating Register

Offset: 0x2d4 | Read/Write: R/W | Reset: 0x00000001 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1)
RAIL_CLAMP: Enabling and removing GPU-SOC clamps

0 0x1 0 = DISABLE
1 = ENABLE
9.2.181 APBDEV_PMC_SEC_DISABLE3_0
Offset: 0x2d8 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxx000000000000000000000000)
READ35: disable reads from secure register 35

23 0x0 0 = OFF
1 = ON
WRITE35: disable writes to secure register 35

22 0x0 0 = OFF
1 = ON

21 0x0 0 = OFF
1 = ON

20 0x0 0 = OFF
1 = ON

19 0x0 0 = OFF
1 = ON


18 0x0 0 = OFF
1 = ON

17 0x0 0 = OFF
1 = ON

16 0x0 0 = OFF
1 = ON

15 0x0 0 = OFF
1 = ON

14 0x0 0 = OFF
1 = ON

13 0x0 0 = OFF
1 = ON

12 0x0 0 = OFF
1 = ON

11 0x0 0 = OFF
1 = ON

10 0x0 0 = OFF
1 = ON

9 0x0 0 = OFF
1 = ON

8 0x0 0 = OFF
1 = ON

7 0x0 0 = OFF
1 = ON

6 0x0 0 = OFF
1 = ON

5 0x0 0 = OFF
1 = ON

4 0x0 0 = OFF
1 = ON

3 0x0 0 = OFF
1 = ON

2 0x0 0 = OFF
1 = ON

1 0x0 0 = OFF
1 = ON


0 0x0 0 = OFF
1 = ON








Offset: 0x318 │ Read/Write: R/W │Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)




















Secure scratch register

Offset: 0x360 | Read/Write: R/W | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)



Offset: 0x36c | Read/Write: R/W | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
9.2.210 APBDEV_PMC_CNTRL2_0
Wake interrupt, LP0BB, and Some Miscellaneous Controls

Offset: 0x440 | Read/Write: R/W | Reset: 0x00001000 (0bxxxxxxxxxxxxxxxxxx0100xxxxxxxxxx)
13 0x0 KB_SYSCLK_PM_CFG: This register bit muxes between net kb_row3 and SYS_CLK_REQ and drives
that as the net kb_row3 to the I/O pad. The default setting of this bit is to select SYS_CLK_REQ. This bit is


only modified in clamshell by Boot Loader.
0 = DISABLE
1 = ENABLE
HOLD_CKE_LOW_EN: Enable for the PMC to assert CKE low

12 0x1 0 = DISABLE
1 = ENABLE
11 0x0 SYSCLK_DATA: SYS_CLK_REQ data value. This is used when SYSCLK_ORRIDE is set to '1'
SYSCLK_ORRIDE: SYS_CLK_REQ data override mux control

0: data is driven by hardware
10 0x0 1: data is driven by SYSCLK_DATA
0 = DISABLE
1 = ENABLE
9.2.211 APBDEV_PMC_IO_DPD3_REQ_0
DPD Request 3 Register

CODE: code of operation for all set bits

0 = IDLE
31:30 0x0
1 = DPD_OFF
2 = DPD_ON
29:28 0x0 NEW_RAILS: Reserved for future use
DDR_DATA1_VTTGEN: mem0_data1_vttgen_4_6_pad, mem0_data1_vttgen_5_7_pad

27 0x0 0 = OFF
1 = ON
DDR_DATA0_VTTGEN: mem0_data0_vttgen_0_2_pad, mem0_data0_vttgen_1_3_pad

26 0x0 0 = OFF
1 = ON
DDR_CLKBUF1: mem0_addr2_clkbuf_1_pad, mem0_addr1_clkbuf_0_pad,

mem0_addr2_clkbuf_0_pad
25 0x0
0 = OFF
1 = ON
DDR_CLKBUF0: mem0_addr0_clkbuf_1_pad, mem0_addr0_clkbuf_0_pad,

mem0_addr3_clkbuf_0_pad
24 0x0
0 = OFF
1 = ON
DDR_ADDR1_VTTGEN: mem0_addr1_vttgen_0_pad,mem0_addr2_vttgen_0_pad
23 0x0 0 = OFF
1 = ON
DDR_ADDR0_VTTGEN: mem0_addr0_vttgen_0_pad,mem0_addr3_vttgen_0_pad
22 0x0 0 = OFF
1 = ON
DDR_CLK_B_VTTGEN: mem0_mclk1_vttgen_0_pad - DEFUNCT

21 0x0 0 = OFF
1 = ON
DDR_CLK_VTTGEN: mem0_mclk0_vttgen_0_pad
20 0x0 0 = OFF
1 = ON
DDR_CLK_B: xm2_mclkb_pad
19 0x0 0 = OFF
1 = ON

DDR_CLK: xm2_mclk_pad
18 0x0 0 = OFF
1 = ON
DISC_BIAS: mem0_bias_0_pad
17 0x0 0 = OFF
1 = ON
DDR_MCS_B1: xm2_mcs_b_1_pad
16 0x0 0 = OFF
1 = ON
DDR_MCS_B0: xm2_mcs_b_0_pad
15 0x0 0 = OFF
1 = ON
DDR_MCKE_B1: xm2_mcke_b_1_pad
14 0x0 0 = OFF
1 = ON
DDR_MCKE_B0: xm2_mcke_b_0_pad
13 0x0 0 = OFF
1 = ON
DDR_ODT_B1: xm2_odt_b_1_pad
12 0x0 0 = OFF
1 = ON
DDR_ODT_B0: xm2_odt_b_0_pad
11 0x0 0 = OFF
1 = ON
DDR_ADDR1: xm2_ma[10,11,12,13,14,15]_pad, xm2_mba[0,1,2]_pad, xm2_ma_b[3,4,5]_pad

10 0x0 0 = OFF
1 = ON
DDR_ADDR0: xm2_ma[0,1,2,3,4,5,6,7,8,9]_pad, xm2_mras_n_pad, xm2_mcas_n_pad,

xm2_mwe_n_pad
9 0x0
0 = OFF
1 = ON
DDR_RESET: xm2_reset_pad
8 0x0 0 = OFF
1 = ON
DDR_MCS1: xm2_mcs_1_pad
7 0x0 0 = OFF
1 = ON
DDR_MCS0: xm2_mcs_0_pad
6 0x0 0 = OFF
1 = ON
DDR_MCKE1: xm2_mcke_1_pad
5 0x0 0 = OFF
1 = ON
DDR_MCKE0: xm2_mcke_0_pad
4 0x0 0 = OFF
1 = ON
DDR_ODT1: xm2_odt_1_pad
3 0x0 0 = OFF
1 = ON
DDR_ODT0: xm2_odt_0_pad
2 0x0 0 = OFF
1 = ON
1 0x0 DDR_DATA1: xm2_data(0,1,2,3)_pad

0 = OFF


1 = ON
DDR_DATA0: xm2_data(4,5,6,7)_pad
0 0x0 0 = OFF
1 = ON
9.2.212 APBDEV_PMC_IO_DPD3_STATUS_0
DPD Status 3 Register

Offset: 0x460 | Read/Write: R/W | Reset: 0x000dfeff (0bxx000000000011011111111011111111)
29:28 0x0 NEW_RAILS: Reserved for future use
DDR_DATA1_VTTGEN:mem0_data1_vttgen_4_6_pad, mem0_data1_vttgen_5_7_pad
27 0x0 0 = OFF
1 = ON
DDR_DATA0_VTTGEN:mem0_data0_vttgen_0_2_pad, mem0_data0_vttgen_1_3_pad
26 0x0 0 = OFF
1 = ON
DDR_CLKBUF1:mem0_addr2_clkbuf_1_pad, mem0_addr1_clkbuf_0_pad, mem0_addr2_clkbuf_0_pad

25 0x0 0 = OFF
1 = ON
DDR_CLKBUF0:mem0_addr0_clkbuf_1_pad, mem0_addr0_clkbuf_0_pad, mem0_addr3_clkbuf_0_pad

24 0x0 0 = OFF
1 = ON
DDR_ADDR1_VTTGEN:mem0_addr1_vttgen_0_pad,mem0_addr2_vttgen_0_pad
23 0x0 0 = OFF
1 = ON
DDR_ADDR0_VTTGEN:mem0_addr0_vttgen_0_pad,mem0_addr3_vttgen_0_pad
22 0x0 0 = OFF
1 = ON
DDR_CLK_B_VTTGEN:mem0_mclk1_vttgen_0_pad - DEFUNCT
21 0x0 0 = OFF
1 = ON
DDR_CLK_VTTGEN:mem0_mclk0_vttgen_0_pad
20 0x0 0 = OFF
1 = ON
DDR_CLK_B:xm2_mclkb_pad
19 0x1 0 = OFF
1 = ON
DDR_CLK:xm2_mclk_pad
18 0x1 0 = OFF
1 = ON
DISC_BIAS:mem0_bias_0_pad
17 0x0 0 = OFF
1 = ON
DDR_MCS_B1:xm2_mcs_b_1_pad
16 0x1 0 = OFF
1 = ON
DDR_MCS_B0:xm2_mcs_b_0_pad
15 0x1 0 = OFF
1 = ON
14 0x1 DDR_MCKE_B1:xm2_mcke_b_1_pad


0 = OFF
1 = ON
DDR_MCKE_B0:xm2_mcke_b_0_pad
13 0x1 0 = OFF
1 = ON
DDR_ODT_B1:xm2_odt_b_1_pad
12 0x1 0 = OFF
1 = ON
DDR_ODT_B0:xm2_odt_b_0_pad
11 0x1 0 = OFF
1 = ON
DDR_ADDR1:xm2_ma[10,11,12,13,14,15]_pad, xm2_mba[0,1,2]_pad, xm2_ma_b[3,4,5]_pad

10 0x1 0 = OFF
1 = ON
DDR_ADDR0:xm2_ma[0,1,2,3,4,5,6,7,8,9]_pad, xm2_mras_n_pad, xm2_mcas_n_pad,

xm2_mwe_n_pad
9 0x1
0 = OFF
1 = ON
DDR_RESET:xm2_reset_pad
8 0x0 0 = OFF
1 = ON
DDR_MCS1:xm2_mcs_1_pad
7 0x1 0 = OFF
1 = ON
DDR_MCS0:xm2_mcs_0_pad
6 0x1 0 = OFF
1 = ON
DDR_MCKE1:xm2_mcke_1_pad
5 0x1 0 = OFF
1 = ON
DDR_MCKE0:xm2_mcke_0_pad
4 0x1 0 = OFF
1 = ON
DDR_ODT1:xm2_odt_1_pad
3 0x1 0 = OFF
1 = ON
DDR_ODT0:xm2_odt_0_pad
2 0x1 0 = OFF
1 = ON
DDR_DATA1:xm2_data(0,1,2,3)_pad
1 0x1 0 = OFF
1 = ON
DDR_DATA0:xm2_data(4,5,6,7)_pad
0 0x1 0 = OFF
1 = ON
9.2.213 APBDEV_PMC_STRAPPING_OPT_A_0
Strapping Options Register

Offset: 0x464 | Read/Write: R/W | Reset: 0xXXX000X0 (0bxxxxxxxxxxxxxxxxxxxxxx00xxxxxxx0)
29:26 X BOOT_SELECT: read at power-on reset time from gmi_ad[3:0] strap pads.


0 = MPCORE_G
1 = MPCORE_LP
BOOT_SRC_USB_RECOVERY_MODE: read at power-on reset time from gmi_oe_n strap pad

25 X 0 = DISABLED
1 = ENABLED
BOOT_SRC_NOR_BOOT: read at power-on reset time from gmi_wr_n strap pad

24 X 0 = IROM
1 = NOR
ARM_JTAG: read at power-on reset time from gmi_ad[19:18] strap pads

00=Serial_JTAG
01=CPU_only
10=COP_only
23:22 X 11=Serial_JTAG(same as 00 case)
0 = SERIAL
1 = CPU
2 = COP
3 = SERIAL_ALT
BOOT_FAST_UART: UART Boot speed from TMC JTAG config bit

0=57600 baud
9 0x0 1=Osc Frequency (1 bit per OSC clock)
0 = SLOW
1 = FAST
MIO_WIDTH:
8 RSVD1 0 = RSVD1
1 = RSVD2
RAM_CODE: read at power-on reset time from gmi_ad[7:4] strap pads. In emulation
(HIDREV_MAJORREV==0), this field indicates the RAM type connected. For QT
(HIDREV_MINORREV==0): 0=SIM, 1=DDR, 2=DDR2, 3=LPDDR2. For FPGA
(HIDREV_MINORREV==1): 0=SIM, 1=DDR, 2=DDR2, 3=LPDDR2
0 = LPDDR3_800
1 = ELPIDA_LPDDR2
2 = RSVD2
3 = DDR3_2GB
7:4 X
4 = RSVD4
5 = DDR3_2GB_NO_DSR
6 = DDR3_934
7 = DDR3_800
8 = RSVD8
9 = DDR3_x64_2GB
10 = DDR3_X64_8GB_667
11 = DDR3_X64_8GB_800
NOR_WIDTH:
0 RSVD1 0 = RSVD1
1 = RSVD2
Scratch register
31:0 X SCRATCH56: General purpose register storage

Scratch register
Scratch register
Scratch register
Scratch register
Scratch register
Scratch register

Scratch register
Scratch register
Scratch register
Scratch register
Scratch register
Scratch Register

Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register

Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register

Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register

Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register
Scratch Register

Scratch Register
Scratch Register
Scratch Register
Scratch Register
Offset: 0x6a0 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Scratch Register
Scratch Register

Scratch Register
Offset: 0x6ac │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Scratch Register
Offset: 0x6b0 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Scratch Register
Scratch Register
Scratch Register
Offset: 0x6bc │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Scratch Register
Offset: 0x6c0 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)

Scratch Register
Scratch Register
Scratch Register
Offset: 0x6cc │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Scratch Register
Offset: 0x6d0 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Scratch Register
Scratch Register

Scratch Register
Offset: 0x6dc │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Scratch Register
Offset: 0x6e0 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Scratch Register
Scratch Register
Scratch Register
Offset: 0x6ec │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Scratch Register
Offset: 0x6f0 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)

Scratch Register
Scratch Register
Scratch Register
Offset: 0x6fc │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Scratch register
31:0 0x0 Reserved

9.3 PMC Counter 0 Registers

9.3.1 SYSCTR0_CNTCR_0
The control registers are read/written by secure accesses only except the CNTFID0 and COUNTERID11-0 registers, which
can be written only once by secure or non-secure access.
The CNTFID0 and COUNTERID11-0 registers are read-only; however, to initialize them at boot (by the ARM7 or main CPU),
they are defined as write once.
A non-secure write to the control registers is ignored. A non-secure read to the control registers returns all 1s.
Counter Control Register

Offset: 0x0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxx0xxxxxx00)
8 0x0 FCREQ: Requested frequency modes table entry. This bit is not used.
1 0x0 HDBG: Halt-on-debug. Controls whether a Halt-on-debug signal halts the system counter or not. 0: System
counter ignores Halt-on-debug.1: Asserted Halt-on-debug signal halts the system counter update.
0 = DISABLE
1 = ENABLE
0 0x0 EN: Enables the counter. When this bit is written to '1', then the TSC is loaded with the CNTCVx register’s
value, and starts incrementing from that value. When this bit is written to '0', the TSC halts counting and
stays at that value.
0: System counter disabled
1: System counter enabled.
0 = DISABLE
1 = ENABLE
9.3.2 SYSCTR0_CNTSR_0
Counter Status Register

Offset: 0x4 | Read/Write: RO | Reset: 0x00000X0X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
8 X FCREQ: Frequency change acknowledge. This bit is a copy of the value of the CNTCR[FCREQ] bit.
1 X HDBG: Indicates whether or not the counter is halted because the Halt-on-Debug signal is asserted:
0: Counter is not halted.
1: Counter is halted.
0 = DISABLE
1 = ENABLE
0 X RESERVED: Reserved, no impact.
9.3.3 SYSCTR0_CNTCV0_0
Counter Count Value [31:0] Register

31:0 0x0 CV: Counter value [31:0]. A read of this register provides the TSC[31:0] value at the time of the read.
When CNTCR[EN]=0, a write to this register is used to initialize the TSC[31:0] value. When


CNTCR[EN]=1, a write to this register has an unpredictable behavior.
Counter Count Value[63:32] Register

Offset: 0xc | Read/Write: R/W | Reset: 0x00000000 (0b00000000000000000000000000000000)
31:0 0x0 CV: Counter value [63:32]. A read of this register provides the TSC[63:32] value at the time of the read.
When CNTCR[EN]=0, a write to this register is used to initialize the TSC[63:32] value. When
CNTCR[EN]=1, a write to this register has an unpredictable behavior.
9.3.5 SYSCTR0_CNTFID0_0
Frequency Table Entry Register

Offset: 0x20 | Read/Write: R/W | Reset: 0x00b71b00 (0b00000000101101110001101100000000)
31:0 0xb71b00 FV: Counter frequency value in Hz. The default is set to 12 MHz. This register can be written only
once.
9.3.6 SYSCTR0_CNTFID1_0
Frequency Table End Marker

31:0 X FV: Counter frequency value end marker (all 0s, read-only).
9.3.7 SYSCTR0_COUNTERID4_0
The COUNTERID11-0 registers are read-only; however, to initialize them at boot (by the ARM7™ or main CPU), they are
defined as write once.
Offset: 0xfd0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxx00000000)
7:0 0x0 VALUE: Peripheral ID value
Offset: 0xfd4 | Read/Write: RO | Reset: 0x000000XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
7:0 X RESERVED: Reserved. A read will return all 0s.

Offset: 0xfdc | Read/Write: RO | Reset: 0x000000XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Offset: 0xfe0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxx00000000)
Offset: 0xfec | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxx00000000)
Offset: 0xff0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxx00000000)
7:0 0x0 VALUE: Component ID value

Offset: 0xff4 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxx000000000000)
Offset: 0xff8 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxx00000000)
Offset: 0xffc | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxx00000000)
9.4 PMC Counter 1 Registers

The status registers are some control registers readable via the CNTReadBase base address by secure or non-secure
accesses.
These are the same physical registers that are described in the Control Register section.

31:0 X CV: Counter value [31:0]

Offset: 0xc | Read/Write: RO | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X CV: Counter value [63:32]

7:0 X VALUE: Peripheral ID value.
Offset: 0xfdc | Read/Write: RO | Reset: 0x000000XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Offset: 0xfe0 | Read/Write: RO | Reset: 0x000000XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
7:0 X VALUE: Peripheral ID value

Offset: 0xfec | Read/Write: RO | Reset: 0x000000XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
Offset: 0xff0 | Read/Write: RO | Reset: 0x000000XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
7:0 X VALUE: Component ID value
Offset: 0xffc | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxx00000000)
9.5 Secure Boot Registers

9.5.1 SB_CSR_0
Secure Boot Control Status Register

Offset: 0x0 | Read/Write: R/W | Reset: 0x0000002X (0bxxxxxxxxxxxxxxxx000000000010xx01)
15:12 RW 0x0 COT_FAIL_COUNT: Chain-of-Trust Fail Count
11:8 RW 0x0 SWDM_FAIL_COUNT: Secure Watchdog Monitor fail Count
SWDM_ENABLE: Secure Watchdog Monitor Enable

7 RW 0x0 1 = ENABLE
0 = DISABLE
HANG: Secure Boot Hang

6 RW 0x0 1 = ENABLE
0 = DISABLE
5 RW 0x1 JTAG_DISABLE: Secure JTAG Disable


0 = ENABLE
1 = DISABLE
PIROM_DISABLE: Protected iROM Disable

4 RW 0x0 0 = ENABLE
1 = DISABLE
3:2 RO X Rsrvd_31: Reserved
NS_RST_VEC_WR_DIS: Non-secure reset vector write disable

1 RW 0x0 0 = ENABLE
1 = DISABLE
SECURE_BOOT_FLAG: 1 = Booted into Secure Mode

0 RW 0x1 1 = ENABLE
0 = DISABLE
9.5.2 SB_PIROM_START_0
This specifies the offset from the start of the Boot ROM to the protected Region. This register is only programmable while in
Secure_Mode (SECURE_BOOT_FLAG above == 1)
The lower 7 bits (6:0) are not significant and are assumed to be zero.
Secure Boot Protected ROM Start

31:0 0x1000 PROTECTED_ROM_START: PROTECTED_ROM_START
9.5.3 SB_PFCFG_0
Secure Boot Processor Feature Configuration Register

Offset: 0x8 | Read/Write: R/W | Reset: 0x00XX008f (0bxxxxxxx0110xxxxxxxx0000010001111)
CS_DEADSTATUS_EN: Coresight™ Debug bit to enable return codes on bad accesses

24 RW 0x0 1 = ENABLE
0 = DISABLE
CS_ACCESS_CHECK_EN: Debug bit to Enable Checking for bad Csite accesses such as when
CPU not in active partition
23 RW 0x1
1 = ENABLE
0 = DISABLE
CS_CODES_EN: Coresight Debug bit to Enable Status Codes

0 = DISABLE
CS_TIMEOUT_TM: Coresight Timeout Testmode

0 = DISABLE
DBGACK_AVP: DBGACKnowledge Status from AVP

20 RO X 1 = ENABLE
0 = DISABLE
DBGACK_CPU3: DBGACKnowledge Status from CPU3

19 RO X 1 = ENABLE
0 = DISABLE
18 RO X DBGACK_CPU2: DBGACKnowledge Status from CPU2


1 = ENABLE
0 = DISABLE
DBGACK_CPU1: DBGACKnowledge Status from CPU1

17 RO X 1 = ENABLE
0 = DISABLE
DBGACK_CPU0: DBGACKnowledge Status from CPU0. The following bits assert the Processor
External Debug Request signal. Setting these bits can cause a break. Clearing these bits will NOT
restart the processor, but the request needs to be cleared before the debugger can restart the
16 RO X
processor
1 = ENABLE
0 = DISABLE
EDBGRQ_AVP: External Debug Request for AVP

0 = DISABLE
EDBGRQ_CPU3: External Debug Request for CPU3 via CoreSight

0 = DISABLE

0 = DISABLE

9 RW 0x0 1 = ENABLE
0 = DISABLE
EDBGRQ_CPU0: External Debug Request for CPU0 via CoreSight.Coresight Timeout Enable for
bus transactions
8 RW 0x0
1 = ENABLE
0 = DISABLE
CS_TIMEOUT_EN: Coresight Timeout Enable RTCK delay control

7 RW 0x1 1 = ENABLE
0 = DISABLE
CS_RTCK_SPEED: RTCK delay (Synchronized or Direct) The following bits configure the
Processor Feature pins. Once these bit values are assigned to the Most-Secure mode, they cannot
6 RW 0x0 be flipped back again
0 = SLOW
1 = FAST
CP15SDISABLE: Disable access to system control registers

0 = ENABLE
CFGSDISABLE: Disable access to secure control registers

0 = ENABLE
DBGEN: Debug Enable (Not the same as JTAG enable)

3 RW 0x1 1 = ENABLE
0 = DISABLE
NIDEN: Non-Invasive Debug Enable

2 RW 0x1 1 = ENABLE
0 = DISABLE
SPIDEN: Secure Privileged Invasive Debug Enable

1 RW 0x1 1 = ENABLE
0 = DISABLE
SPNIDEN: Secure Privileged Non-Invasive Debug Enable

0 RW 0x1 1 = ENABLE
0 = DISABLE

9.5.4 SB_SECURE_SPAREREG_0_0
Offset: 0xc | Read/Write: R/W | Reset: 0x00000000 (0b00000000000000000000000000000000)
31:0 0x0 SECURE_SPAREREG_0



10.0 ACTIVITY MONITOR

This section describes the activity monitor (ACTMON) block. The ACTMON acts as a central repository for activity indicators
from various units, performs averaging of past samples, and indicates any abnormality in activity levels by sending an interrupt
to software. Devices provide an idle/busy signal to the ACTMON block.

Activity monitoring is a means to dynamically measure the utilization of units in the system to help drive software power
management policies. In Tegra processors, Dynamic Voltage and Frequency Scaling (DVFS) is used as a power management
mechanism. It uses utilization information from various units to select an efficient voltage and frequency that the unit should
operate at, while providing the requisite performance. Voltage change decisions are handled by this central software agent,
but the unit frequency can be modulated in one of the following ways:
 The unit controls its own frequency - no need for activity monitoring support.
 The device driver controls the unit frequency based on calculated workload or hints from a user-level driver – no need
for activity monitoring support.
 The device driver controls the unit frequency based on utilization information from a “unit ACTMON”.
 The central DVFS agent controls the unit frequency based on utilization information from a “central ACTMON”.
In addition to tracking utilization, activity monitoring is also used to provide hardware support to make the process of activity
monitoring interrupt-driven instead of polling-based. This support is in the form of averaging, watermark detection, and
histogram hardware. This reduces software overhead in procuring and tracking utilization data.
The ACTMON block has the following features:
 One 32-bit counter for each signaling device that accumulates activity counts.
 Running average computation for each counter over past N samples (N=128).
 Watermark breach detection logic for each counter. This is used to detect abrupt change in utilization.
 Interrupt-driven operation.
The DVFS thread can directly access and use the activity monitors to compute the target frequency (and consequently,
voltage) for each unit for the next sampling interval.
The following table summarizes the Tegra K1 activity monitors.
Table 30: Activity Monitors
Module Counter Description (Counter Width = 32 Bits)
A7AVP Number of system clock cycles that A7AVP is in the halt state
Number of AHB clock cycles when no data transfer is detected on the bus.
AHB
Can select one specific master or all of them.
Number of APB clock cycles when no data transfer is detected on the bus.
APB
Can select one specific master or all of them.
CPU The flow controller asserts a signal when ALL the cores are halted.
Number of Memory Controller clock cycles when any (including CCPLEX)

MC-ALL memory access event is detected. The MC toggles a signal to ACTMON every
‘W’ cycles.
Number of MC clock cycles when any memory access event from CCPLEX is
MC-CPU
detected. MC toggles a signal to ACTMON every ‘W’ cycles.

Activity Monitor
Module Counter Description (Counter Width = 32 Bits)
VDE Number of video pipe cycles when the pipe is empty.
The table above assumes that the following units either run at a fixed frequency or do their own frequency management based
on fixed workload, so they do not need central ACTMON support.
 VI/CSI (fixed)
 Display (workload-based, no monitors needed)
 Host (fixed)
 ISP (workload-based)
 MSENC/VIC (utilization-based and uses per-unit ACTMON)
 SEC (fixed frequency)
 USB3 –Falcon (workload-based)
 MSELECT (frequency is based on other units and cannot be controlled independently)
10.2 ACTMON Registers

10.2.1 ACTMON GLB Status Register
10.2.1.1 ACTMON_GLB_STATUS_0
Offset: 0x0 | Read/Write: RO | Reset: 0xXX00XX00 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
CPU_INTR: CPU Monitor Interrupt status. 1 = Interrupt detected; 0 = Interrupt not detected
31 X 0 = NOINTR
1 = INTR
COP_INTR: COP Monitor Interrupt status. 1 = Interrupt detected; 0 = Interrupt not detected
30 X 0 = NOINTR
1 = INTR
AHB_INTR: AHB Monitor Interrupt status. 1 = Interrupt detected; 0 = Interrupt not detected
29 X 0 = NOINTR
1 = INTR
APB_INTR: APB Monitor Interrupt status. 1 = Interrupt detected; 0 = Interrupt not detected
28 X 0 = NOINTR
1 = INTR
VDE_INTR: VDE Interrupt status. 1 = Interrupt detected; 0 = Interrupt not detected

27 X 0 = NOINTR
1 = INTR
MCALL_INTR: MC_ALL Interrupt status. 1 = Interrupt detected; 0 = Interrupt not detected

26 X 0 = NOINTR
1 = INTR
MCCPU_INTR: MC_CPU Interrupt status. 1 = Interrupt detected; 0 = Interrupt not detected

25 X 0 = NOINTR :
1 = INTR
CPU_MON_ACT: CPU monitor active status. 1 = active

15 X 0 = INACTIVE
1 = ACTIVE

Activity Monitor
COP_MON_ACT: COP monitor active status. 1 = active

14 X 0 = INACTIVE
1 = ACTIVE
AHB_MON_ACT: 0 = inactive. 1 = active

13 X 0 = INACTIVE
1 = ACTIVE
APB_MON_ACT: 0 = inactive. 1 = active

12 X 0 = INACTIVE
1 = ACTIVE
VDE_MON_ACT: 0 = inactive. 1 = active

10 X 0 = INACTIVE
1 = ACTIVE
MCALL_MON_ACT: 0 = inactive. 1 = active

9 X 0 = INACTIVE
1 = ACTIVE
MCCPU_MON_ACT: 0 = inactive. 1 = active

8 X 0 = INACTIVE
1 = ACTIVE
10.2.2 ACTMON Global Period Register
10.2.2.1 ACTMON_GLB_PERIOD_CTRL_0
Offset: 0x4 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxx000000000)
SOURCE:
8 0x0 0 = MSEC : Sampling period time base in milliseconds
1 = USEC : Sampling period time base in microseconds
SAMPLE_PERIOD: Sampling period in milliseconds/microseconds (implemented as n+1 counter).

7:0 0x0
Programming a 0 implies a 1 millisecond/microsecond sampling period.
10.2.3 CPU Registers
10.2.3.1 ACTMON_CPU_CTRL_0
Monitor Control Register

Offset: 0x80 | Read/Write: R/W | Reset: 0x00001800 (0b00000000000000xxxxx110xxxxxxxxxx)
ENB: Enable Monitor. Set by software to enable sampling. Cleared in one of the following ways: (a)
When software intends to stop the monitor, it can do so by clearing this field, (b) when the sampling
31 0x0 period expires (and we are not in the periodic mode)
0 = DISABLE
1 = ENABLE
CONSECUTIVE_ABOVE_WMARK_EN: Enable interrupt when consecutive

'CONSECUTIVE_UPPER_NUM' upper watermark breaches are detected
30 0x0
0 = DISABLE : interrupt is disabled.
1 = ENABLE: interrupt is enabled
CONSECUTIVE_BELOW_WMARK_EN: Enable interrupt when consecutive

'CONSECUTIVE_LOWER_NUM' lower watermark breaches are detected.
29 0x0
28:26 0x0 CONSECUTIVE_ABOVE_WMARK_NUM: Number (N+1) of consecutive upper watermark breaches

Activity Monitor

that need to occur to raise an interrupt
CONSECUTIVE_BELOW_WMARK_NUM: Number (N+1) of consecutive lower watermark breaches

that need to occur to raise an interrupt
25:23 0x0
WHEN_OVERFLOW_EN: Enable interrupt for number of consecutive lower watermark breaches that
need to occur to raise an interrupt.
22 0x0
AVG_ABOVE_WMARK_EN: Enable interrupt when AVG value is above its upper watermark value.
21 0x0 0 = DISABLE : interrupt is disabled.
AVG_BELOW_WMARK_EN: Enable interrupt when AVG value is below its lower watermark value.
AT_END_EN:Enable interrupt at the end of sample period.

ENB_PERIODIC: Enable periodic mode. Sample for one sample period or periodic sampling
0 = DISABLE : periodic mode is disabled, samples for only 1 period
18 0x0
1 = ENABLE: periodic mode is enabled, keeps on sampling and updating value after every sample
period
12:10 0x6 K_VAL: variable for IIR filter. Default is 6, which translates to 2^(K+1) = 128.
10.2.3.2 ACTMON_CPU_UPPER_WMARK_0
Upper Watermark Register

31:0 X VAL: Upper watermark for count value.
10.2.3.3 ACTMON_CPU_LOWER_WMARK_0
Lower Watermark Register

31:0 X VAL: Lower watermark for count value.
10.2.3.4 ACTMON_CPU_INIT_AVG_0
Initial AVG value, specified by SW to set up the filter
31:0 X VAL

Activity Monitor
10.2.3.5 ACTMON_CPU_AVG_UPPER_WMARK_0
AVG Upper Watermark Register

10.2.3.6 ACTMON_CPU_AVG_LOWER_WMARK_0
AVG Lower Watermark Register

10.2.3.7 ACTMON_CPU_COUNT_WEIGHT_0
Count Weight Register

31:0 X VAL: weight value for count measurements.
10.2.3.8 ACTMON_CPU_COUNT_0
Monitor Status0 Register

31:0 X VAL: Indicates the number of active count pulses in one period
10.2.3.9 ACTMON_CPU_AVG_COUNT_0

Offset: 0xa0 | Read/Write: RO | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X VAL: Indicates the AVG count value
10.2.3.10 ACTMON_CPU_INTR_STATUS_0
Monitor Interrupt Register

Offset: 0xa4 | Read/Write: R/W | Reset: 0x00000000 (0b000xx000xxxxxxxxxxxxxxxxxxxxxxxx)
CONSECUTIVE_UPPER: Assert at the end of sampling period, if count value crosses upper watermark
31 0x0 value consecutively for the number of times specified in CONSECUTIVE_UPPER_NUM field. A write
value of 1 clears this interrupt, writing a 0 has no effect

Activity Monitor

0 = NOINTR : 0 = interrupt not detected
1 = INTR : 1 = interrupt detected
CONSECUTIVE_LOWER: Assert at the end of sampling period, if count value crosses lower watermark
value consecutively for the number of times specified in CONSECUTIVE_LOWER_NUM field. A write
30 0x0 value of 1 clears this interrupt, writing a 0 has no effect
AT_END: Assert at the end of sampling period, if interrupt at end of sample period is enabled. A write
value of 1 clears this interrupt; writing a 0 has no effect
29 0x0
WHEN_OVERFLOW: Assert at the end of sampling period, if there is an overflow. A write value of 1 clears
this interrupt; writing a 0 has no effect
26 0x0
AVG_BELOW_WMARK: Assert at the end of sampling period, if AVG count value crosses lower AVG
watermark value. A write value of 1 clears this interrupt, writing a 0 has no effect.
25 0x0
AVG_ABOVE_WMARK: Assert at the end of sampling period, if AVG count value crosses upper AVG
watermark value. A write value of 1 clears this interrupt, writing a 0 has no effect
24 0x0
10.2.4 COP Registers
10.2.4.1 ACTMON_COP_CTRL_0

Offset: 0xc0 | Read/Write: R/W | Reset: 0x00001800 (0b00000000000000xxxxx110xxxxxxxxxx)
0 = DISABLE
1 = ENABLE

'CONSECUTIVE_UPPER_NUM' upper watermark breaches are detected.
30 0x0
1 = ENABLE : interrupt is enabled.

29 0x0
CONSECUTIVE_ABOVE_WMARK_NUM: Number (N+1) of consecutive upper watermark breaches

that need to occur to raise an interrupt.
28:26 0x0

25:23 0x0
WHEN_OVERFLOW_EN: Enable interrupt for the Number of consecutive lower watermark breaches
22 0x0 that need to occur to raise an interrupt.

Activity Monitor

AT_END_EN: Enable interrupt at the end of sample period.

18 0x0
1 = ENABLE : periodic mode is enabled, keeps on sampling and updating value after every sample
period
10.2.4.2 ACTMON_COP_UPPER_WMARK_0

Offset: 0xc4 | Read/Write: R/W | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
10.2.4.3 ACTMON_COP_LOWER_WMARK_0

Offset: 0xc8 | Read/Write: R/W | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
10.2.4.4 ACTMON_COP_INIT_AVG_0
Initial AVG value, specified by software to set up the filter
Offset: 0xcc | Read/Write: R/W | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X VAL
10.2.4.5 ACTMON_COP_AVG_UPPER_WMARK_0

Offset: 0xd0 | Read/Write: R/W | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)

Activity Monitor
10.2.4.6 ACTMON_COP_AVG_LOWER_WMARK_0

10.2.4.7 ACTMON_COP_COUNT_WEIGHT_0

10.2.4.8 ACTMON_COP_COUNT_0

Offset: 0xdc | Read/Write: RO | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
10.2.4.9 ACTMON_COP_AVG_COUNT_0

Offset: 0xe0 | Read/Write: RO | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
10.2.4.10 ACTMON_COP_INTR_STATUS_0

Offset: 0xe4 | Read/Write: R/W | Reset: 0x00000000 (0b000xx000xxxxxxxxxxxxxxxxxxxxxxxx)
value consecutively for the number of times specified in CONSECUTIVE_UPPER_NUM field. A write

Activity Monitor

this interrupt, writing a 0 has no effect
26 0x0
25 0x0
24 0x0
10.2.5 AHB Registers
10.2.5.1 ACTMON_AHB_CTRL_0

Offset: 0x100 | Read/Write: R/W | Reset: 0x00001800 (0b00000000000000xxxxx1100000000000)
ENB: Enable Monitor. Set by SW to enable sampling. Cleared in one of the following ways: (a) When
software intends to stop the monitor, it can do so by clearing this field, (b) when the sampling period
31 0x0 expires (and we are not in the periodic mode)
0 = DISABLE
1 = ENABLE

30 0x0

29 0x0

28:26 0x0

25:23 0x0
that need to occur to raise an interruptd.
22 0x0
AVG_ABOVE_WMARK_EN:Enable interrupt when AVG value is above its upper watermark value.
AVG_BELOW_WMARK_EN:Enable interrupt when AVG value is below its lower watermark value.
19 0x0 AT_END_EN:Enable interrupt at the end of sample period.


Activity Monitor

18 0x0
period
MONITOR_COND: Selection criteria on parent module for the activity signal, used only for APB/AHB
monitors. Indicates which AHB master to monitor. All 1s means any master.
0 = CPU
1 = COP
2 = VCP
3 = CSITE
4 = ARC
5 = AHBDMA
6 = USB
7 = APBDMA
8 = NA1
9 = NA2
10 = NA3
11 = SNOR
9:4 0x0
12 = NA4
13 = BSEV
14 = SE
15 = DDS
16 = BSEA
17 = USB3
18 = USB2
19 = NA5
20 = NA6
21 = MIPIHSI
22 = NA7
23 = NA8
24 = NA9
63 = ALL
SAMPLE_COND: Selection criteria on parent module for type of pulse signal, used only for APB/AHB
monitor.
0 = AHB_MASTER_ACTIVE
1 = AHB_MASTER_SLAVE_ACTIVE
3:0 0x0 2 = AHB_DATA_XFER
3 = AHB_IDLE
4 = MASTER_IDLE
5 = AHB_BUSY
6 = DISABLE
10.2.5.2 ACTMON_AHB_UPPER_WMARK_0

10.2.5.3 ACTMON_AHB_LOWER_WMARK_0


Activity Monitor
10.2.5.4 ACTMON_AHB_INIT_AVG_0
31:0 X VAL
10.2.5.5 ACTMON_AHB_AVG_UPPER_WMARK_0

10.2.5.6 ACTMON_AHB_AVG_LOWER_WMARK_0

10.2.5.7 ACTMON_AHB_COUNT_WEIGHT_0

10.2.5.8 ACTMON_AHB_COUNT_0

10.2.5.9 ACTMON_AHB_AVG_COUNT_0


Activity Monitor
10.2.5.10 ACTMON_AHB_INTR_STATUS_0

Offset: 0x124 | Read/Write: R/W | Reset: 0x00000000 (0b000xx000xxxxxxxxxxxxxxxxxxxxxxxx)
29 0x0
26 0x0
25 0x0
24 0x0
10.2.6 APB Registers
10.2.6.1 ACTMON_APB_CTRL_0

Offset: 0x140 | Read/Write: R/W | Reset: 0x00001800 (0b00000000000000xxxxx1100000000000)
ENB: Enable Monitor. Set by SW to enable sampling. Cleared in one of the following ways: (a) When
SW intends to stop the monitor, it can do so by clearing this field, (b) when the sampling period expires
31 0x0 (and we are not in the periodic mode)
0 = DISABLE
1 = ENABLE

30 0x0

29 0x0 'CONSECUTIVE_LOWER_NUM' lower watermark breaches are detected.

Activity Monitor


28:26 0x0

25:23 0x0
22 0x0

18 0x0
period
MONITOR_COND: Selection criteria on parent module for the activity signal, used only for APB/AHB
monitors. Indicates which APB slave to monitor. All 1s means any slave.
0 = AUDIO
1 = UARTA
2 = UARTB
3 = UARTC
4 = UARTD
5 = VFIR
6 = DTV
7 = I2C1
8 = I2C2
9:4 0x0 9 = I2C3
10 = I2C4
11 = DVC
12 = I2C6
13 = SPI1
14 = SPI2
15 = SPI3
16 = SPI4
17 = SPI5
18 = SPI6
19 = OWR
63 = ALL
SAMPLE_COND: Selection criteria on parent module for type of pulse signal, used only for APB/AHB
monitor.
0 = PSEL_ACTIVE
3:0 0x0 1 = PREADY_ACTIVE
2 = PENABLE_PSEL_ACTIVE
3 = APB_IDLE
4 = DISABLE

Activity Monitor
10.2.6.2 ACTMON_APB_UPPER_WMARK_0

10.2.6.3 ACTMON_APB_LOWER_WMARK_0

10.2.6.4 ACTMON_APB_INIT_AVG_0
31:0 X VAL
10.2.6.5 ACTMON_APB_AVG_UPPER_WMARK_0

10.2.6.6 ACTMON_APB_AVG_LOWER_WMARK_0

10.2.6.7 ACTMON_APB_COUNT_WEIGHT_0


Activity Monitor
10.2.6.8 ACTMON_APB_COUNT_0

10.2.6.9 ACTMON_APB_AVG_COUNT_0

10.2.6.10 ACTMON_APB_INTR_STATUS_0

29 0x0
26 0x0
25 0x0
24 0x0
10.2.6.11 ACTMON_APB_CTRL_SAPB_0

Offset: 0x168 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxx0000000000)

Activity Monitor
MONITOR_COND_SAPB: Selection criteria on parent module for the activity signal, used only for
APB/AHB monitors.
0 = DVFS
1 = PWM
2 = MISC
3 = RTC
4 = KBC
5 = PMC
6 = SYSCTR0
7 = SYSCTR1
8 = FUSE
9 = KFUSE
10 = LA
11 = DDS
12 = DP2
13 = SNOR
14 = SE
15 = CSITE
16 = MC
9:4 0x0
17 = EMC
18 = MIPI_CAL
19 = ATOMICS
20 = CED
21 = HDA
22 = SATA
23 = SDMMC1
24 = SDMMC2
25 = SDMMC3
26 = SDMMC4
27 = SATA_AUX
28 = APB2JTAG
29 = SOC_THERM
30 = XUSB_HOST
31 = XUSB_DEV
32 = XUSB_PADCTL
33 = PINMUX_AUX
34 = SECURE_REGS
63 = ALL
SAMPLE_COND_SAPB: Selection criteria on parent module for type of pulse signal, used only for
APB/AHB monitor.
0 = PSEL_ACTIVE
3:0 0x0 1 = PREADY_ACTIVE
2 = PENABLE_PSEL_ACTIVE
3 = APB_IDLE
4 = DISABLE
10.2.7 VDE Registers
10.2.7.1 ACTMON_VDE_CTRL_0

When SW intends to stop the monitor, it can do so by clearing this field, (b) when the sampling period
31 0x0 expires (and we are not in the periodic mode)
0 = DISABLE
1 = ENABLE

30 0x0

Activity Monitor

29 0x0

28:26 0x0
1 = ENABLE

25:23 0x0
22 0x0

18 0x0
period
10.2.7.2 ACTMON_VDE_UPPER_WMARK_0

10.2.7.3 ACTMON_VDE_LOWER_WMARK_0

10.2.7.4 ACTMON_VDE_INIT_AVG_0

Activity Monitor
31:0 X VAL
10.2.7.5 ACTMON_VDE_AVG_UPPER_WMARK_0

10.2.7.6 ACTMON_VDE_AVG_LOWER_WMARK_0

10.2.7.7 ACTMON_VDE_COUNT_WEIGHT_0

10.2.7.8 ACTMON_VDE_COUNT_0

10.2.7.9 ACTMON_VDE_AVG_COUNT_0

Offset: 0x1a0 | Read/Write: RO | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
10.2.7.10 ACTMON_VDE_INTR_STATUS_0

Offset: 0x1a4 | Read/Write: R/W | Reset: 0x00000000 (0b000xx000xxxxxxxxxxxxxxxxxxxxxxxx)

Activity Monitor
value consecutively for the number of times specified in CONSECUTIVE_UPPER_NUM field. a write value
31 0x0 of 1 clears this interrupt, writing a 0 has no effect
value consecutively for the number of times specified in CONSECUTIVE_LOWER_NUM field. a write
29 0x0
26 0x0
25 0x0
24 0x0
10.2.8 MC_ALL Registers
10.2.8.1 ACTMON_MCALL_CTRL_0

Offset: 0x1c0 | Read/Write: R/W | Reset: 0x00001800 (0b00000000000000xxxxx110xxxxxxxxxx)
0 = DISABLE
1 = ENABLE

30 0x0

'CONSECUTIVE_LOWER_NUM' lower watermark breaches are detectedd.
29 0x0

28:26 0x0

25:23 0x0

Activity Monitor
22 0x0
AVG_ABOVE_WMARK_EN:Enable interrupt when AVG value is above its upper watermark value.
AVG_BELOW_WMARK_EN:Enable interrupt when AVG value is below its lower watermark value.
AT_END_EN:Enable interrupt at the end of sample period.

18 0x0
period
10.2.8.2 ACTMON_MCALL_UPPER_WMARK_0

Offset: 0x1c4 | Read/Write: R/W | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
10.2.8.3 ACTMON_MCALL_LOWER_WMARK_0

Offset: 0x1c8 | Read/Write: R/W | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
10.2.8.4 ACTMON_MCALL_INIT_AVG_0
Offset: 0x1cc | Read/Write: R/W | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X VAL
10.2.8.5 ACTMON_MCALL_AVG_UPPER_WMARK_0

Offset: 0x1d0 | Read/Write: R/W | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)

Activity Monitor
10.2.8.6 ACTMON_MCALL_AVG_LOWER_WMARK_0

10.2.8.7 ACTMON_MCALL_COUNT_WEIGHT_0

10.2.8.8 ACTMON_MCALL_COUNT_0

Offset: 0x1dc | Read/Write: RO | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
10.2.8.9 ACTMON_MCALL_AVG_COUNT_0

Offset: 0x1e0 | Read/Write: RO | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
10.2.8.10 ACTMON_MCALL_INTR_STATUS_0

Offset: 0x1e4 | Read/Write: R/W | Reset: 0x00000000 (0b000xx000xxxxxxxxxxxxxxxxxxxxxxxx)

Activity Monitor

26 0x0
25 0x0
24 0x0
10.2.9 MC_CPU Registers
10.2.9.1 ACTMON_MCCPU_CTRL_0

0 = DISABLE
1 = ENABLE

30 0x0

29 0x0

28:26 0x0

25:23 0x0
22 0x0
19 0x0 AT_END_EN: Enable interrupt at the end of sample period.


Activity Monitor

18 0x0
period
10.2.9.2 ACTMON_MCCPU_UPPER_WMARK_0

10.2.9.3 ACTMON_MCCPU_LOWER_WMARK_0

10.2.9.4 ACTMON_MCCPU_INIT_AVG_0
31:0 X VAL
10.2.9.5 ACTMON_MCCPU_AVG_UPPER_WMARK_0

10.2.9.6 ACTMON_MCCPU_AVG_LOWER_WMARK_0


Activity Monitor
10.2.9.7 ACTMON_MCCPU_COUNT_WEIGHT_0

10.2.9.8 ACTMON_MCCPU_COUNT_0

10.2.9.9 ACTMON_MCCPU_AVG_COUNT_0

10.2.9.10 ACTMON_MCCPU_INTR_STATUS_0
Monitor interrupt Register

29 0x0
26 0x0
25 0x0

Activity Monitor
24 0x0
10.2.10 Histogram Registers
10.2.10.1 ACTMON_HISTOGRAM_CONFIG_0
Histogram Configuration
Offset: 0x300 | Read/Write: R/W | Reset: 0x00000XXX (0bxxxxxxxxxxxxxxxx0000xxxxxxxxxxxx)
SOURCE:
0 = NONE
1 = AHB
2 = APB
3 = COP
15:12 NONE 4 = CPU
5 = MC_ALL
6 = MC_CPU
7 = VDE
8 = VDEA
9 = APB_MMIO
8:4 X SHIFT: Scaling factor for the idle counter before the value is used to update histogram bucket.
STALL_ON_SINGLE_SATURATE:
FALSE : continue incrementing buckets even when another bucket has saturated
3 X TRUE : stop incrementing bucket when at least one other bucket has saturated
0 = FALSE
1 = TRUE
NO_UNDERFLOW_BUCKET:
FALSE : increase bucket 0 when idle time is less than the minimum value
2 X TRUE : ignore idle times that are less than the minimum value
0 = FALSE
1 = TRUE
LINEAR_MODE:
DISABLE : bucket width increases exponentially with a power of two
1 X ENABLE : bucket width is the same for all buckets
0 = DISABLE
1 = ENABLE
ACTIVE: ENABLE : enable histogram recording

0 X 0 = DISABLE
1 = ENABLE
10.2.10.2 ACTMON_HISTOGRAM_CTRL_0
Offset: 0x304 | Read/Write: R/W | Reset: 0x0000000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
0 X CLEAR: Clear all

Activity Monitor
10.2.10.3 ACTMON_HISTOGRAM_DATA_0
Offset: 0x380..0x3ff | Read/Write: RO | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X VALUE

11.0 REAL-TIME CLOCK

The Real-Time Clock (RTC) module maintains seconds and milliseconds counters, and five alarm registers. The RTC is in the
‘always-on’ power domain, allowing for the counters to run and alarms to trigger when the system is in low-power state. If
configured, interrupts triggered by the RTC can cause the system to wake up from a low-power state.
Features
 10-bit milliseconds counter that runs off of a 32.768 KHz clock source.
 32-bit seconds counter that increment for every 1000 milliseconds.
 Alarm feature that triggers an interrupt when the specified value matches the milliseconds counter.
 Alarm feature that triggers an interrupt when the specified value matches the seconds counter.
 Count-down alarm feature that triggers an alarm after counting down the specified number of seconds.
 Count-down alarm feature that triggers an alarm after counting down the specified number of milliseconds.
 Security bit that disables further processor writes to the seconds counter and ensures that the RTC clock keeps
running.
 Hardware adjusts drift in clock which can occur due to PPM variations in oscillator output.

The RTC operates in two clock domains: the APB clock domain and the 32 KHz clock domain. The RTC continues updating
the millisecond and second counters and continues triggering interrupts even when the MAIN partition is powered down. Since
the APB clock is disabled when MAIN is powered down, registers are implemented in the 32 KHz clock domain.
All the registers except the BUSY register are implemented in the 32 KHz clock domain. Writes are transferred to the 32 KHz
domain with BUSY.STATUS set to BUSY until the transfer is completed. Reads are shadowed in the APB clock domain and
return immediately.
The RTC implements a Seconds Counter register, a Milliseconds Counter register, three Alarm registers, two countdown
alarms, and various interrupt-related registers.
Writes to the seconds counter can be disabled by writing to the CONTROL.DIS_WR_SEC_CNT bit. Alarm registers and
countdown alarm registers set interrupt bits when corresponding events occur. Interrupt status, mask, set and source registers
reflect the status and also allow setting and clearing of various bits. All registers (except the BUSY register) are implemented
in the 32K clock domain. Writes are transferred to the 32K domain with BUSY STATUS set to BUSY until the transfer
completes. Reads are shadowed in the APB domain and will return immediately.
Resets
The RTC receives an asynchronous reset which is synchronized to the APB clock and RTC clock domains.

Real-Time Clock
11.2 RTC Registers

11.2.1 APBDEV_RTC_CONTROL_0
Control Register
Offset: 0x0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
WR_SEC_CNT: When set, writes to the SECONDS counter are disabled. Can only be cleared
by resetting the RTC module
0 0x0
0 = DISABLE
1 = ENABLE
11.2.2 APBDEV_RTC_BUSY_0
Busy Register
Offset: 0x4 | Read/Write: RO | Reset: 0x0000000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
STATUS: This bit is set when a write is initiated on the APB side. It is cleared once the write
completes in RTC 32 KHz clock domain, which could be several thousands of APB clocks. This
0 X must be IDLE before a write is initiated. Note that this bit is only for writes.
0 = IDLE
1 = BUSY
11.2.3 APBDEV_RTC_SECONDS_0
Seconds Counter Register

The SECONDS register is copied over to the APB side every eight 32 KHz clocks (~250 µs). Because of this, performing a
read immediately after a write might return an old value. This covers 49710.26 Days (or) 136.192 Years of 365 days each.
31:0 0x0 SECONDS: The seconds counter is incremented every 1000 milliseconds.
11.2.4 APBDEV_RTC_SHADOW_SECONDS_0
Shadowed Seconds Counter Register

Shadow SECONDS register is updated over to the APB side whenever there is a read to milliseconds counter.
Since the software cannot read both registers at any given point of time, the Seconds register content is captured in this
register. If software needs to read both seconds and milliseconds, read the MILLI_SECONDS register followed by a read of
this register.
SHADOW_SECONDS: A snapshot of the SECONDS counter is taken, whenever there is a

31:0 X
read to MILLI_SECONDS Register.

Real-Time Clock
11.2.5 APBDEV_RTC_MILLI_SECONDS_0
Milliseconds Counter Register

The Milliseconds register is copied over to the APB side every eight 32 KHz clocks (~250 µs). Because of this, performing a
read immediately after a write might return an old value.
9:0 X MILLI_SECONDS: Milliseconds counter is incremented using the Bresenham algorithm
11.2.6 APBDEV_RTC_SECONDS_ALARM0_0
Seconds Alarm0 Registers

When the value in this register matches the seconds counter, the corresponding interrupt status bit is set. If enabled, the
interrupt line is asserted. A value of zero disables the alarm.
31:0 0x0 SECS_MATCH_VALUE: Match value to trigger the alarm
11.2.7 APBDEV_RTC_SECONDS_ALARM1_0
Seconds Alarm1 Registers

When the value in this register matches the seconds counter, the corresponding interrupt status bit is set. If enabled, the
31:0 0x0 SECS_MATCH_VALUE: Match value to trigger the alarm
11.2.8 APBDEV_RTC_MILLI_SECONDS_ALARM_0
Milliseconds Alarm Register

When the value in this register matches the milliseconds counter, the corresponding interrupt status bit is set. If enabled, the
Offset: 0x1c | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxx0000000000)
9:0 0x0 MSEC_MATCH_VALUE: Milliseconds match value.
11.2.9 APBDEV_RTC_SECONDS_COUNTDOWN_ALARM_0
Countdown Alarm Register

If ENABLE is set to ENABLED, an internal counter is loaded with VALUE and counted down. The interrupt bit corresponding to
the countdown_alarm_0 is set after the specified number of seconds have elapsed.

Real-Time Clock
The interrupt bit corresponding to the countdown alarm (SEC_CDN_ALARM) is set after the specified interval has expired. If
REPEAT is ENABLED, the countdown operation is performed repeatedly.
ENABLE: Enable bit for the countdown operation. If repeat is not set, this bit is cleared once the
internal counters counts down to specified value.
31 0x0
0 = DISABLED
1 = ENABLED
REPEAT: Repeat bit for the countdown operation

30 0x0 0 = DISABLED
1 = ENABLED
29:0 0x0 VALUE: Number of seconds to countdown
11.2.10 APBDEV_RTC_MILLI_SECONDS_COUNTDOWN_ALARM_0
Countdown Alarm Register

If ENABLE is set to ENABLED, an internal counter is loaded with VALUE and counted down. The interrupt bit corresponding to
the countdown_alarm_0 is set after the specified number of milliseconds have elapsed.
The interrupt bit corresponding to the countdown alarm (MSEC_CDN_ALARM) is set after the specified interval has expired. If
REPEAT is ENABLED, the countdown operation is performed repeatedly.
ENABLE: Enable bit for the countdown operation. If repeat is not set, this bit is cleared once the
internal counters counts down to specified value.
31 0x0
0 = DISABLED
1 = ENABLED
REPEAT: Repeat bit for the countdown operation

30 0x0 0 = DISABLED
1 = ENABLED
29:0 0x0 VALUE: Number of milliseconds to countdown
11.2.11 APBDEV_RTC_INTR_MASK_0
Interrupt Mask Register

This register stores the masks for the interrupts. If a bit is set 1 and the corresponding interrupt condition is satisfied, interrupt
line to system interrupt controller is asserted.
Offset: 0x28 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx00000)
4 0x0 MSEC_CDN_ALARM
3 0x0 SEC_CDN_ALARM
2 0x0 MSEC_ALARM
1 0x0 SEC_ALARM1
0 0x0 SEC_ALARM0

Real-Time Clock
11.2.12 APBDEV_RTC_INTR_STATUS_0
Interrupt Status Register

Bits in this register are high after the interrupt condition is satisfied. Any bits that are set to one in the data written to this
register will clear their corresponding data bits. Any bits set to zero have no effect.
3 0x0 SEC_CDN_ALARM
2 0x0 MSEC_ALARM
1 0x0 SEC_ALARM1
0 0x0 SEC_ALARM0
11.2.13 APBDEV_RTC_INTR_SOURCE_0
Interrupt Source Register

This read-only register returns the AND of the Interrupt Source and Interrupt Mask registers.
Offset: 0x30 | Read/Write: RO | Reset: 0x000000XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
4 X MSEC_CDN_ALARM
3 X SEC_CDN_ALARM
2 X MSEC_ALARM
1 X SEC_ALARM1
0 X SEC_ALARM0
11.2.14 APBDEV_RTC_INTR_SET_0
Interrupt Set Register

Reserved. This write-only register is used for testing purposes only.
3 0x0 SEC_CDN_ALARM
2 0x0 MSEC_ALARM
1 0x0 SEC_ALARM1
0 0x0 SEC_ALARM0

Real-Time Clock
11.2.15 APBDEV_RTC_CORRECTION_FACTOR_0
Correction Factor (Digital Trimming) Register

Support is for +/- 500 ppm. The expected maximum deviation of the standard clock sources is +/- 50 ppm.
Offset: 0x38 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxx0000000000)
DIRECTION:
9 0x0 0 = DECREMENT
1 = INCREMENT
8:0 0x0 PPM

12.0 HOST SUBSYSTEM

The host controller (referred to as Host1x) provides a sophisticated programming and control interface to various graphic and
video engines, and display. In addition to Host1x’s control interfaces with these units, it also has a slave (IP) interface to the
ARM7 crossbar (xbar), TSEC, and a direct memory interface to fetch command structures from system memory. Commands
are either gathered from a push buffer in memory or provided directly by the CPU, and then supplied to the clients behind
Host1x via Host1x channels. The channels also provide a means of synchronization between software and any individual
block or amongst the blocks themselves via hardware Sync Point signals (syncpts).
12.1 Glossary
Term Definition
The command DMA. It is responsible for reading

commands from memory and supplying them to all
CDMA channels. It starts from the address in the channel’s
DMASTART register and continues until it reaches the
address in the channel’s DMAPUT register.
A piece of hardware that provides a programming interface

to one or more classes. A channel contains a sequence of
commands embodied in a command FIFO. This sequence
of commands can also be thought of as a thread of
Channel
execution and of a single context. There exists only one
sequence of commands or context per channel. That is to
say, there is no hardware-managed context switching
within a single channel.
Entries in the command FIFO. Commands take a common

form interpretable by Host and are used for 3 main
Channel Commands functions: controlling class ownership and class
virtualization of the channel; command expansion via
gather commands; and issuing class methods.
A transfer of ownership of a client from one channel to

another; a type of context switch. Sometimes a source of
Channel switch confusion, this is not a transfer of ownership of a channel,
but of a client. This is the preferred narrowed
nomenclature to context switch in order to avoid confusion.
An abstraction of a client, device, or resource. It is a

collection of methods. A class can only be owned by
multiple channels, but only one channel may actively be
Class using any class, which is known as a channel’s working
class. The transfer of working class from one channel to
another is known as a context switch, which is managed by
Host.
Class ID A unique tag corresponding to each class.
Class method A method that belongs to an unspecified class.
A change in the current in the active class of a client; a type

of context switch. In the event that a class switch also
Class switch
involves a channel switch, channel switch is the preferred
declaration.
A piece of hardware that resides behind Host, connected

via the HRD and HRW buses. Client is the preferred
Client, device, resource
terminology for this document. Generally mapped one-to-
one with a class, although this is not a strict requirement.
Holds channel commands supplied by the CDMA or PIO

Command FIFO accesses. It is stalled by synchronization methods,
backpressure from its destination client, or ownership of the

Host Subsystem
Term Definition
destination client by a different channel
A Host event where it facilitates a client's state transition.

Context switch A context switch is either a channel switch or a class
switch.
Access to a client initiated by the CPU. If a channel and

the CPU initiate a data transaction to the same client at the
Direct register access
same time, the CPU gets priority. Direct register accesses
are orthogonal to channels in regards to client ownership.
Holds the current address of the CDMA. One exists per

DMAGET register
channel.
Holds the end address of a command stream in memory.

DMAPUT register
One exists per channel.
Holds the start address of a command stream in memory.

DMASTART register
One exists per channel.
A channel command to gather contiguous chunks of

Gather
memory and inserts it into the command stream.
General term to indicate an entity that can control Host.

Host Master
The current list is the CPU, AVP, and TSEC.
Host method A method that belongs to the Host class.
A channel command that specifies an offset and a count.

Increment Increment works like nonincrement, except the offset is
incremented by one on each on each write.
Access to a client initiated by the CPU, but requires two

Host register accesses. This is deprecated in the SOC
version of the host; it comes from the companion-chip
Indirect register access mode where fixed-latency interfaces to the CPU may
exist. Like direct register accesses, indirect takes priority
over channel transactions. Indirect register accesses must
be tied a channel because they require a read return FIFO.
A channel command that specifies an offset and a mask. A

mask command works much like increment and non-
increment, except the offsets are calculated by looking at
Mask the bits set in the mask. The bit position indicates the
relative offset from the specified offset in the command.
Mask expects the number of words to follow to be equal to
the number of bits set in the mask.
An operation on a class. The most common example is a

Method
single register write.
A channel command that specifies an offset and a count.

The offset specifies a method in the current class and the
Nonincrement
count indicates the number of subsequent words to be
written at that offset.
Deprecated feature previously used by software for flow

Protected Channel
control.
A set of commands residing contiguously in memory. It is a

communication method between the processor and Host.
Push-buffer
Commands are placed at the end of the buffer and a
pointer is updated in Host.
A channel command that takes a class id as an argument.

SetClass SetClass is the sole means to indicate the current
virtualization of the channel. It also the sole means that a
channel can acquire ownership of a class. Subsequent

Host Subsystem
Term Definition
channel commands are directed towards this class.
A counter used for synchronization. Every time a specified

event occurs, the counter is incremented. A channel can
Sync Point (Syncpt) wait until the syncpt attains a specified value, or an
interrupt can be generated when a specified value is
reached.
Can be either a module or channel teardown. Essentially,

it means all links and references within Host between the
Teardown
specified module or the specified channel are removed and
reset.
Tick Count Running count of the Host clock after it has been enabled.
A host method that takes a single vector argument. It is

used in conjunction with syncpt. A WAIT stalls the
WAIT
command FIFO until the supplied vector intersects the
RAISE register at all.
12.2 Features
The key features of the Host1x controller are summarized below:
 12 Channels
 192 Sync Points
 64 Syncpt Base Registers
 32-bit Syncpt Comparison
 32-bit Timeout register
 Stall and transfer counters
 Unit Activity Monitor (ACTMON): MSENC and VIC
 Master clients: Crossbar and TSEC
 TZ secure bit In MMIO path
 Master Interface protocol: Native Crossbar
 Client Interface protocol: Hwr/Hrd
 32-bit Host1x2MC address
12.2.1 Class Based Programming

GPUs support a programming interface that is based on writing to offsets within a “class” that implements a function, rather
than to specific register offsets and formats.
By using “class” interface register offsets/formats need not to remain fixed so there is nothing chip specific in the API. This will
allow both hardware flexibility and software driver compatibility.
12.2.2 Command Buffer DMA

To maximize the Host1x bandwidth, it is important to burst as many write cycles as possible, which requires the processor to
first combine writes. The write buffering typically requires sequential offsets to be written and also may not follow strict
programming order. The CPU will first store this buffered data directly to memory and then program the Host1x engine to DMA
it.

Host Subsystem
12.2.3 Multiple Channels

A channel is a thread of execution within Host1x. Similar to a multithreaded CPU, a channel helps defining a context that can
be used to allow multiple users of the Host1x and plays a role in context switching.
A channel switch does not always require a client module context switch. There will be a state change within the Host1x, but if
channels have non-overlapping usage (e.g., possibly a VIC channel and MSENC encode channel), there may be no need to
context switch any Host1x client module.
12.3.1 Channels
The Tegra K1 processor has 12 Host1x channels. Each channel has a set of registers and a command FIFO. Each channel
can be associated with one or more Host1x clients. The channel is the primary means of delivering commands to clients,
which is described in the Host1x Programming Model section.
12.3.1.1 Channel Registers

Channel registers are broken into two functional groups: one grouping is associated with the command FIFO and command
delivery to clients; the other grouping is associated with register and memory access.
CDMA Registers
 HOST1X_CHANNEL_DMASTART_0: This register triggers a DMA fetch from memory for this channel, if PUT
register does not equal the GET register.
 HOST1X_CHANNEL_DMAPUT_0: This register triggers a DMA fetch from memory for this channel, if the PUT
register does not equal the GET register. This address is relative to the DMASTART base address. It does not
support byte writes. All 4-byte data need to be programmed.
 HOST1X_CHANNEL_DMAGET_0: This register tracks the MC offset, which DMA engine has read. It gets
incremented as entries are loaded from the channels command buffer into the FIFO. This address is relative to the
DMASTART base address.
 HOST1X_CHANNEL_DMAEND_0: This is the boundary of illegal addresses (either end of push-buffer or end of
physical memory). This is designed to prevent DMA from prefetching illegal addresses. If DMA reaches this address
before seeing a RESTART, it will stop. This would be a software error condition.
 HOST1X_CHANNEL_DMACTRL_0: The various fields of DMA control register are described as below:
- DMAGETRST: Reset GET pointer to '0'. Useful for cleaning up crashed channels. DMAGET value is not
updated instantly. It takes 4 cycles between programming of reset and valid DMAGET.
- DMAGETINIT: Reset GET pointer to the value of DMAPUT when DMAGETRST is asserted.
- DMASTOP: Stop DMA from fetching on this channel.
Note: A Command DMA channel needs to be enabled for PIO-gather to work.
Access Registers
 HOST1X_CHANNEL_INDOFF_0 and HOST1X_CHANNEL_INDOFF2_0: The INDOFF and INDOFF2 registers
(along with INDCNT and INDDATA) are used to indirectly read/write modules outside the host. If AUTOINC is set,
INDOFFSET value is increments by 4 on every access of INDDATA. REGFNUMEMPTY is polled to determine when
valid data can be read from INDDATA. The INDOFF register has limited capability on chips with large memory maps.
If the top bit of the memory address is >= 27, all of memory cannot be addressed with INDOFF. In these cases, use

Host Subsystem
INDOFF2 to set the offset while still using INDOFF to set other parameters. Always have INDOFFUPD set to
NO_UPDATE in these cases.
 For register accesses, using INDOFF (with INDOFFUPD set to UPDATE) is always more efficient, since it only
requires one write.
 HOST1X_CHANNEL_INDCNT_0: Indirect register access count used to trigger indirect reads. Holds the number of
registers/memory locations that will be read out. Channels should not request more than there is space available in
their output FIFO. For indirect frame buffer reads, each channel cannot issue more than
NV_HOST1X_MAX_IND_FB_READS at once. The read data must return and be written into the per-channel output
FIFO before any additional reads can be issued.
 HOST1X_CHANNEL_INDDATA_0: This register, when written, writes to the data to the INDOFFSET in INDOFF. For
reads, a REGFNUMEMPTY number of 32-bit values can be read before needing to poll FIFOSTAT again. The per-
channel output FIFO (OUTFENTRIES) is readable via this offset. A read of INDDATA will pop an entry off of the per-
channel output FIFO.
 HOST1X_CHANNEL_CMDSWAP_0: Command swap control. Affects swapping on writes to the PIO region and the
frame-buffer buffered memory write region.
 HOST1X_CHANNEL_FIFOSTAT_0: CFNUMEMPTY is the number of free slots available in the per-channel
command FIFO (needed for PIO or polling for completion of a wait).
12.3.1.2 Channel Command FIFO

The command FIFO is loaded either the CDMA or via PIO access. PIO is mainly used for debug purposes, but it allows a
Host1x master to fill the command FIFO with channel commands by writing into “command FIFO” region of the channel's
address space. PIO Command FIFO accesses should not be issued while a “Gather” process is busy.
A command FIFO has a set of registers that point to a location in memory where a sequence of channel commands resides.
This sequence of commands is generally referred to as a “Push-buffer”.
A Host1x master can write either to DMAPUT or DMASTART register to trigger command fetching by the CDMA. DMASTART
indicates where to start fetching, and DMAPUT indicates where to stop. DMAGET is a read-only reference to the present
location of the command FIFO; it is incremented when the command is popped from the command FIFO. DMAPUT and
DMAGET are relative addresses to DMASTART.
DMAEND provides an upper boundary to prevent the CDMA from fetching illegal addresses; fetching will cease when
DMAGET equals DMAEND.
The command FIFO can be halted by writing the DMASTOP field in the Dmactrl register. Dmactrl also provides a mechanism
to reset the DMAGET pointer (Dmagetrst field) to either 0 or to the value of DMAPUT (Dmainitget field).
12.3.1.3 Channel Commands

Channel commands can be split into two categories:
 Class commands: A class command is a mechanism to communicate a class write to a client. The channel must
have an active class when processing class commands. The active class is set by a SETCL (SetClass) command.
 DMA commands: DMA commands control what is being fetched. They are processed at the top of the command
FIFO while class commands are processed at the bottom of the command FIFO. This is because DMA commands
change the command stream and must be processed before entering the FIFO.
Offsets in class commands are relative to the active class' base as they are limited to only the methods in the active class.

Host Subsystem
Channel Commands
 SETCL (SetClass) – A channel command that takes a class ID as an argument. SetClass is the sole means to
indicate the current virtualization of the channel. It also means that a channel can acquire ownership of a class.
Subsequent channel commands are directed towards this class.
 NONINCR (NonIncrement) – Takes an offset and count as arguments. There will be <count> data following this
class command that will be written to the specified offset. Nonincrement indicates that the offset will not be
incremented per data write.
 INCR (Increment) – Takes an offset and count as arguments. There will be <count> data following this command
that will be written starting at the specified offset. The offset is incremented after each write.
 MASK (Mask) – Takes an offset and count as arguments. The number of data to write after the command is equal to
the number of set bits in the count. Each data is written to the specified offset plus the next active bit location. For
example, a count equal to 0x5, would have 2 data that are written to (offset+0) and (offset+2).
 IMM (Immediate) – Takes an offset and 16-bit data as arguments. The 16-bit data is written to the offset.
DMA Commands
 RESTART (Restart or Jump) – This command specifies an offset relative to DMASTAT. The next command fetched
will be from (DMASTART + offset).
 GATHER – Command comprises 2 words and has arguments: offset, insert, type, count, and address. When
GATHER is processed, <count> data is fetched from the address and inserted into the command stream. If the
<insert> argument is enabled, it will insert either an INCR or NONINCR opcode preceding the fetched data, which is
specified by <type>.
DMA commands do not need an active class, but often are processed when an active class exists. In the case of GATHER, if
<insert> is enabled, there must be an active class.
12.3.1.4 Channel Control

Channel status and control resides in the synchronous register space of the Host1x address map. These registers are aliased
in each channel's space. The details of these registers are as below:
 CH<0..n>_STATUS: Status includes client ownership and whether the channel is blocked or not (n is the number of
channels – 1).
 CH_TEARDOWN: Using this register each channel can be reset, which is referred to as a teardown. This means all
channel state is cleared and all client and class ownership is relinquished.
 MOD_TEARDOWN: Similar to channel teardown, there exists a mechanism to reset modules. Setting this register
can clears all state associated with a given client/module.
 <client>_STATUS : This register indicates the client’s currently active class.
12.3.2 Host1x Class

Host1x has its own class that can be executed from the command FIFO. It is comprised of methods to access client registers
as well as methods to control channel flow.
12.3.2.1 INDOFF
The following Host1x methods operate identically to the channel registers used for indirect access. Refer to the Host Channel
Registers and Indirect Register Access sections.
 INDOFF
 INDOFF2
 INDCTRL

Host Subsystem
 INDDATA
INDCNT is absent from the list above. In Host1x master-initiated indirect register reads, INDCNT is written to trigger the read.
Conversely, reads from the command FIFO are trigged by a write to INDDATA. Reads issued from the command FIFO are
returned to the channel's register return FIFO (return_FIFO).
12.3.2.2 DELAY_USEC
Delay_Usec stalls the command FIFO for the number of microseconds specified. This command has no impact on indirect
register accesses if not initiated from the command FIFO. The microsecond period is calculated based on setting in the
Usec_Clk register. The Usec_Clk register is programmed on the basis of Host1x clock for example if host clock is 250 MHz,
then this register should be programmed to a value of 250.
12.3.2.3 TICKCOUNT
Tickcount_Hi, Tickcount_Lo, and Tickctrl can also be controlled from the command FIFO. Their operation is identical whether
controlled from the command FIFO or a Host1x master.
12.3.2.4 INCR_SYNCPT
All Host1x modules, including the Host1x itself, implement the Incr_Syncpt class.
Incr_Syncpt <Cond> <Indx>
For the Host1x, this method immediately increments Syncpt[Indx] irrespective of the cond.
12.3.2.5 WAIT_SYNCPT
Wait on syncpt – the command dispatch will stall until the syncpt counter pointed by the index field reaches the threshold value
specified in the Thresh field:-
Wait_Syncpt <Indx> <Thresh>
The channel will wait until the following is true:
Syncpt[Indx][15:0] >= Thresh[15:0]
where the “>=” takes into account wrapping (see the “Sync Points (SYNCPTs)” section for more information on wrapping).
More specifically, the channel will wait until:
((Syncpt[indx] – thresh) & (1 << 15)) != 0
12.3.2.6 WAIT_SYNCPT_BASE
This method uses Syncpt Base registers to calculate threshold value for channel wait operation. The syncpt index, base index
and also optional offset will be a part of Wait_Syncpt_Base command:-
Wait_Syncpt_Base <Indx> <Base_Indx> <Offset>
The channel will wait until the following is true:
Syncpt[Indx][15:0] >= (Syncpt_Base[Base_Indx] + Offset)[15:0]
Where the “>=” takes into account wrapping. See the “Sync Points (SYNCPTs)” section for more information on wrapping.

Host Subsystem
12.3.2.7 WAIT_SYNCPT_INCR
Wait until syncpt increments:
Wait_Syncpt_Incr <Indx>
The channel will stall until Syncpt[Indx] is incremented. Note that this wait method is not recommended.
12.3.2.8 LOAD_SYNCPT_BASE
Load a new value into the Syncpt_Base register:
load_syncpt_base <base_indx> <value>
Syncpt_Base[Base_Indx] will be loaded with <Value>.
12.3.2.9 INCR_SYNCPT_BASE
Add an offset to the value in the Syncpt_Base register:
Incr_Syncpt_Base <Base_Indx> <Offset>
The following operation will be done:
Syncpt_Base[Base_Indx] += Offset
12.3.2.10 STALLCOUNT
STALLCOUNT_HI, STALLCOUNT_LO, and STALLCTRL are methods to control “stall counters” through the command FIFO.
Details of stall counters are given later in this document.
12.3.2.11 XFERCOUNT
Channel_Xfer_Hi, Channel_Xfer_Lo, and Xferctrl are methods to control “xfer counters” through the command FIFO.
12.3.2.12 32-Bit Sync Point Comparison Methods

Five methods are used for 32-bit sync point comparison. Software should send these commands using the following format:
LOAD_SYNCPT_PAYLOAD_32, <other_command>
where <other_command> is one of the following::
 WAIT_SYNCPT_32
 WAIT_SYNCPT_BASE_32 ,
 LOAD_SYNCPT_BASE_32,
 INCR_SYNCPT_BASE_32
LOAD_SYNCPT_PAYLOAD_32 <Payload(32)>
This method loads a 32-bit value into the corresponding channel's Channel_Syncpt_Payload register:
Channel_Syncpt_Payload[31:0 ]= <Payload(32)>
WAIT_SYNCPT_32 <Indx(8)>
This method stalls the current channel until following condition is true:-
(SYNCPT [<indx>][31:0] - PAYLOAD[31:0]) & 0x80000000) == 0
Here the Payload value is taken from Channel_Syncpt_Payload of the current channel.

Host Subsystem
This is essentially a wrapping stall until ((SYNCPT [<indx>][31:0] >= PAYLOAD[31:0])
WAIT_SYNCPT_BASE_32 <Indx(8)> <Base_Indx(8)> :

This method stalls the current channel until following condition is true:-
((Syncpt [<Indx>][31:0] - (Payload[31:0] + Syncpt_Base[<Base_Indx>][31:0]) & 0x80000000) == 0
Here the Payload value is taken from Channel_Syncpt_Payload register of the current channel.
This is essentially a wrapping:-
stall until ((Syncpt [<Indx>][31:0] >= (Payload[31:0] + Syncpt_Base[<Base_Indx>][31:0]))
LOAD_SYNCPT_BASE_32 <Base_Indx(8)>
This method copies the value from the current channel's Channel_Syncpt_Payload register into the Syncpt_Base register
specified through the Base_Indx field:-
Syncpt_Base[<Base_Indx>][31:0] = Channel_Syncpt_Payload[31:0]
INCR_SYNCPT_BASE_32 <Base_Indx(8)>
This method adds the value of the current channel's Channel_Syncpt_Payload register into the Syncpt_Base register specified
through Base_Indx:-
Syncpt_Base[<Base_Indx>][31:0] += Channel_Syncpt_Payload[31:0]
12.3.3 Context Switching

Context management of Host1x 1x-based modules will be completely under software control (there will be no automatic
context switching done by hardware). This mean a module will never produce a context switch interrupt, it will always operate
in auto-acknowledge mode.
12.3.4 Behavior of SetClass

The SetClass does not mean implicit acquisition of a module’s ownership. It is possible to send commands simultaneously
from more than one channel to the same module. If exclusive ownership of a module is required for software correctness,
then acquire_mlock and release_mlock opcodes should be used, which acquire and release the MLOCKn semaphore bits. An
acquire_mlock that fails will cause that channel's commands to stall until it wins subsequent MLOCK arbitration (arbitrations
happen with each release_mlock).
Here is the summary of SetClass behavior:-
 SetClass simply instructs the channel hardware which module and context to use for the following commands.
 If multiple channels write simultaneously to the same class ID, and no MLOCKs are used, then the actual commands
are interleaved in round-robin fashion (one command per channel).
 If multiple channels write simultaneously to different class IDs in the same hardware module (and no MLOCKs are
used), then the actual commands are interleaved, but in blocks of N-cycle bursts (each burst of commands must be
preceded with a CTXSW to the module giving the new context ID).
N in this case is programmable number configured through Ctxsw_Timeout_Cfg register.
12.3.5 Sync Points (SYNCPTs)

A Sync point is a mechanism to synchronize between software and Host1x clients and also in between Host1x clients. This is
implemented as 32-bit counters which are incremented by 1 whenever some predestinated condition (or event) occurs. When
a counter reaches its maximum value, it wraps back to zero on the next increment.

Host Subsystem
Tegra K1 processors have 192 sync points. Sync points are not permanently associated with a channel; sync point allocation
is done by software during initialization time.
There are two basic ways for sync point increments: -
 When a CPU writes an index to the Host1x’s “syncpt_cpu_incr” register.

 When a Host1x client has received an “incr_syncpt” method and the condition specified by this method has become
true.
Synchronization using sync points can be done in the following ways:
 A CPU can be interrupted when a sync point reaches a pre-specified value.

 A Host1x channel can have “wait” commands so that channel will wait for a pre-specified sync point value.
Sync points are normally not reset, but can wrap -- the comparison takes into account the possibility of wrapping.
Note: Sync point wrapping works only if (Syncpt value - Syncpt Threshold) <= 2(syncpt_width-1)
For 16-bit syncpt comparisons, the difference should be less than or equal to 32768.
Software must take care of wrapping issues.
For 32-bit comparisons, the difference should be less than or equal to 2,147,483,648,
Because of the large value, software will not see any wrapping issues.
All Host1x clients (e.g., VI) implement the following increment syncpt method:
Incr_Syncpt <Condition> <Index>
The Host1x client would receive the “Incr_Syncpt” method and store the index for each condition. Whenever the "condition"
event occurs, the client would return the index back to Host1x.
12.3.5.1 Client Model for Syncpt Behavior
Software Programming Model

The basic programming model that software will follow is:
Each module will be programmed to do a unit of work (an operation) by Host1x using CDMA and push buffers.
Examples of an operation include:-
 BLT (VIC)
 Draw a set of triangles (GPU)
 Encode a single frame (MSENC).
If nothing else is programmed, then module will go idle until Host1x sends commands to start another operation (no
continuous mode).To do its operation, a module reads data from memory and writes the results to memory. Modules interact
with each other using memory buffers: one module is the producer of data, and another is the consumer of that data.
There are exceptions to this model which we will discuss in detail later, but should be mentioned here. The exceptions include
VI and DISPLAY which work in continuous mode (they continue to process data without the need of additional Host1x
programming).
Basic Synchronization
There are two basic needs for synchronization: management of memory buffers and timing of control register writes.
Memory buffers used to pass data from one module to the next use a producer/consumer model with circular buffers. To
prevent buffer underflow and overflow, synchronization needs to be done in both directions:
 The consumer cannot read until producer is done writing (and the writes are committed to memory).

Host Subsystem
 The producer cannot reuse an output buffer (i.e., write to buffer) until the consumer is done reading the buffer.
Thus, the synchronization events required for memory buffers are:
 The module has completed all reads from the buffer.

 The module has completed all writes to the buffer (and they are committed by the memory controller).
To understand the requirements for timing the writes to control registers, a typical sequence is provided below:
1. reg wr for operation A

2. reg wr for operation A
3. reg wr (trigger) for operation A
4. reg wr for operation B
5. reg wr for operation B
6. reg wr (trigger) for operation B
If no WAIT method is placed between the trigger for A and the first register write for B, then in the worst case, corruption of
operation A may occur because the new value of the control register is used before operation A is done. For modules that
protect against this corruption, there is still the undesirable behavior of the module delaying the register write and
subsequently causing back pressure on the Host1x write bus. If we wish to allow direct register reads to be used by ISRs they
will happen asynchronously to the channel command writes, so one must ensure that the Host1x bus does not stall for
significant periods of time.
For synchronizing writes to control register, a safe time to start writing register for the next operation is defined to be when:
 No corruption will occur for previous operations.

 No stall of the HWRBUS bus will result.
12.3.5.2 Standard Set of Incr_Syncpt Conditions

The following values of the “incr_syncpt cond” field are predefined:
 0 (Immediate): Return indx to Host1x immediately (used by software push-buffer allocation and helpful for debug).
 1 (Op_Done): Return indx to Host1x when all previously triggered operations have completed and their writes to
memory are committed.
 2 (Rd_Done): Return indx to Host1x when all previously triggered operations have completed their reads from
memory.
 3 (Reg_Wr_Safe): Return indx to Host1x when it is safe to program registers for the next operation. Safe means no
corruption to previous operations and no stalling of Host1x write bus will occur.
There are special cases which would require use of additional condition values. Some modules have multiple read buffers
condition = 2 (all reads done) would mean all reads to all buffers done, but it might be useful to software to know when reads
are done to a specific input buffer. For some modules, e.g., VI, there are different safe times to update different sets of
registers, so condition = 3 will need several variations (one for each "safe time"). If a module can have two operations
happening at one time (as in VI), then special considerations will need to be made for these cases: either two separate
Incr_Syncpt methods or one Incr_Syncpt method with many special conditions.
For some modules, one condition can replace another if the two conditions always happen within a short period of time of each
other. Then the condition that always happens last can be used for both.
12.3.5.3 Continuous Mode — Display and VI

For each display, software wants a free-running syncpt increment on every display “Vsync”. The most appropriate
implementation of this is to have an additional register which has “Enable” and “Indx” fields to control the increment of syncpt
on every “Vsync” event. If enable is set, then on every “Vsync”, display would return this “Indx” back to Host1x.

Host Subsystem
A similar situation exists for VI, where besides a set of conditions for the “Incr_Syncpt” method, it would also need a register
with “Enable” and “Indx” which would control the incrementing of a syncpt on every camera “Vsync”.
Host1x clients will implement the logic associated with these registers. When this continuous mode is enabled, the client
should set a pending bit for when the condition occurs. When the pending bit is set, the client will arbitrate for the
hrd_<client>2host1x bus and if selected it will send “Indx” tagged with “Syncpt type” on hrd_ bus. After successfully sending
the indx on hrd bus, the client will clear the pending bit.
One of the issues for continuous operation of VI is that not all modes of operation allow the consumer of their output buffers to
signal backpressure when the consumer has fallen behind in reading. To alleviate this problem, VI has registers which, when
written to, signal that the reading of one buffer has completed.
See Table 32 for a list of the Host1x clients.
12.3.5.4 Allowing Multiple Pending INCR_SYNCPTS

Clients can have multiple pending syncpts which are queued into the client’s syncpt FIFOs, which are dedicated ones for each
syncpt conditions.
The behavior of these syncpt FIFOs is controlled by an “Incr_Syncpt_Cntrl” register in client’s register space:
INCR_SYNCPT_CNTRL< No_Stall>< Soft_Reset>

 No_Stall:
If this bit is 1 and an Incr_Syncpt method is received but the syncpt FIFO for that condition is full, then this method
will be dropped and the Incr_Syncpt_Error[Cond] bit will be set.
If this bit is 0, then instead of dropping next method in case of a syncpt FIFO full condition, the client will just stall the
host interface.
 Soft_Reset:
if Soft_Reset is set, then all internal state of the client syncpt block will be reset. To do a soft reset, first set
Soft_Reset of all Host1x clients affected, then clear all Soft_Resets.
INCR_SYNCPT_ERROR<Cond_Status>
This register stores error status in case of above mentioned syncpt FIFO full condition.
12.3.5.5 32-bit Sync Point Comparison

In Tegra 3 and previous chips, sync point counters were implemented as 32-bit registers but comparison takes into account
16-bit value only. In Tegra K1 devices, sync point comparison is extended to 32 bits. To support this feature, Host1x has the
following changes:-
Host1x 32-Bit Registers

The following registers are extended to 32 bits:
 Syncpoint base register [Host1x 1x_Sync_Syncpt_Base]

 Syncpt Threshold register [Host1x 1x_Sync_Syncpt_Int_Thresh]
The following 32-bit register stores the payload value required in syncpt methods:
 Channel_Syncpt_Payload[31:0]
Host1x Method Changes

To support 32-bit syncpt comparisons, new Host1x methods have been introduced and are described later in this document.

Host Subsystem
12.4 Unit Description

Host1x has a master client interface with the CPU Xbar bus and also a TSEC unit to receive CPU/TSEC read/write
commands. The incoming commands are either processed inside Host1x if they are Host1x specific or routed to clients.
Host1x has a point-to-point interface with its clients using HWR/HRD buses, which are used for sending requests and
accepting responses from clients.
There is a memory controller interface to fetch Push-Buffer commands from memory through the “Command DMA” unit. The
incoming Push-Buffer commands are processed inside “Command Processor” and afterwards either consumed inside Host1x
or it will generate tractions to client interface. There is an internal “syncpt” unit which is used to synchronize between Host1x
clients and also between software.
There is a “Unit ActMon” block to monitor activities of Host1x clients. The ActMon statistics are used by software for power
management.
Figure 17: Host1x Top-Level Block Diagram
Tsec HOST1X
Bus
Unit
CPU/TSEC
ActMon Unit Idle Signal
CPU Interface
Bus
Xbar GPU
SyncPts
Interface
Interrupt
Interrupt Logic Command
Controller Command DMA
Processor
Host1x Client
Memory Controller
Interfaces
12.4.1 Activity Monitor

The Host1x unit implements 32-bit activity monitor (ACTMON) counters to monitor the idleness of the MSENC/VIC units.
The MSENC/VIC units send active information to Host1x through the same “active” signal (which is a level signal). The
ACTMON block provides averaging, watermark detection, and interrupt functionality similar to the central activity monitors. The
Host1x driver manages these monitors.

Host Subsystem
Figure 18: ACTMON Interface
ActMon Clock
Host1x
Host1x
Reset
Host1x
Host1x XBAR Address
interface Decoder
Logic MSENC msenc_active
ACTMON
Host1x
Host1x XBAR Read
interface Return
Path
VIC
ACTMON vic_active
Host1x general
Interrupt_CPU Host1x
Host1x general
Interrupt ACTMON
Interrupt_COP Logic Unit
The clock for the ACTMON unit is a low-frequency (10 MHz ~ 50 MHz), non gateable clock.
There is 1 interrupt status bit (per MSENC and VIC ACTMON interrupt) in Host1x, which is set by the actmon_intr_set_msenc
and actmon_intr_set_vic signals and cleared by software. Also there are corresponding interrupt mask bits for these interrupt
lines to enable/disable interrupts.
The ACTMON register accesses are handled by the ACTMON itself. The Host1x will forward the access control/address/data
signal to the ACTMON unit.
The ACTMON registers are a part of Host1x register space.
12.4.2 Filtering Out Kernel Commands from the Gather Buffer

This feature maintains user mode driver versus kernel driver protection. The host1x kernel driver sets up mode bits, which
need to be protected from the user mode driver, so that driver cannot directly break the kernel.
Host1x checks the incoming commands from the gather buffer. If it contains the SetClass kernel mode command, then Host1x
should drop these commands and raise an “Invalid Gbuffer cmd” interrupt to software. Software will read the interrupt status
register to detect the channel that received the invalid gbuffer command. That particular channel needs to be restarted through
the “channel teardown” mechanism.
 HOST1X_SYNC_HINTSTATUS_EXT1_0[0:11]
Bit (i) :-ch(i)_Invalid_gbuffer_cmd_int_status
Where i = 0..11

Host Subsystem
 HOST1X_SYNC_HINTMASK_EXT1_0[0:11]
Bit (i) :- ch(i)_Invalid_gbuffer_cmd _int_mask
Where i = 0..11
There might be some cases where a channel can still see setClass, for example, context switching. For those channels this
feature must be disabled. This feature is controlled through CHANNELCTRL for each channel:
CHANNELCTRL[2]
- 0: disable filtering of kernel command(setClass).
- 1: enable filtering of kernel command(setClass).
12.4.3 Timeout Mechanism

Host1x has a mechanism to generate an interrupt for unserviced CPU read/write requests, which is controlled through a
timeout register (HOST1X 1x_IP_TIMEOUT). Host1x generates a timeout Interrupt, and a violating address is stored in the
following registers:
 IP_READ_TIMEOUT_ADDR
 IP_WRITE_TIMEOUT_ADDR
The width of the timeout register is 32 bits to provide a timeout value of ~19 seconds.
The TSEC master client interface also uses this mechanism to generate a timeout interrupt to CPU in case of illegal read/write
access. The HINTSTATUS_EXT register has been modified to indicate if the timeout is from native CPU access or TSEC
access.
Also in case of a TSEC read timeout, the returned response packet will have an additional bit (tsec2host1x
1x_iprdata_timeout) to indicate a timeout error.
HINTSTATUS[Timeout_source=bit10] =
- 0 Timeout from TSEC access.
- 1 Timeout from XBAR access.
The current scheme saves only the last timeout address in case of multiple timeout happens before clearing the timeout
interrupt by software.
12.4.4 Performance Statistics Counters

Host1x has performance counters for profiling, which can be enabled independent of push-buffer commands. Host1x needs
the following statistics per channel:
 Total clocks
 Clocks stalled waiting for syncpt
 Clocks transferring data
12.4.4.1 Tick Counter

Each channel has its own 64-bit tick counter that is incremented on each Host1x clock, given that it is enabled. TICKCTRL
enables and disables the tick counter.
The 32-bit TICKCOUNT_LO and TICKCOUNT_HI registers can be written to initialize the tick counter. Reads of these
registers return the tick count. TICKCOUNT_LO stores the lower 32 bits, and TICKCOUNT_HI stores the upper 32 bits.
TICKCOUNT_HI is calculated as follows:
if (TICKCOUNT_LO == 0xFFFF_FFFF && TICKCTRL == enable) TICKCOUNT_HI++;

Host Subsystem
12.4.4.2 Channel Stall Counter

The 64-bit CHANNEL_STALL counter per channel, when enabled, is incremented on each clock cycle if that particular channel
is waiting for syncpt.
The following registers control this counter:
 STALLCTRL: This 1-bit register enables/disables the CHANNEL_STALL counter.

 STALLCOUNT_LO: This 32-bit register initializes the lower 32 bits of the CHANNEL_STALL counter.
 STALLCOUNT_HI: This 32-bit register initializes the upper 32 bits of the CHANNEL_STALL counter.
The following Host1x class methods are used to program this counter:
 STALLCOUNT_HI: This method initializes the high 32 bits of the tick count value in the CHANNEL_STALL counter.
 STALLCOUNT_LO: This method initializes the low 32 bits of the tick count value in the CHANNEL_STALL counter.
 STALLCTRL: This method enables/disables the CHANNEL_STALL counter.
12.4.4.3 Channel Xfer Counter

There is a 64-bit CHANNEL_XFER counter per channel to measure the data transfer interval per channel. This counter is
incremented at each clock cycle, if the channel is not idle (busy in fetching channel commands).
The following registers are used to initialize this counter:
 XFERCTRL: This 1-bit register enables/disables the CHANNEL_XFER counter.

 CHANNEL_XFER_LO[31:0]: This 32-bit register initializes the lower 32 bits of the CHANNEL_XFER counter.
 CHANNEL_XFER_HI[31:0]: This 32-bit register initializes the lower 32 bits of the CHANNEL_XFER counter.
The following Host1x class methods are used to program this counter:
 CHANNEL_XFER_HI: This method initializes the high 32 bits of the tick count value in the CHANNEL_XFER counter.
 CHANNEL_XFER_LO: This method initializes the low 32 bits of the tick count value in the CHANNEL_XFER counter.
 XFERCTRL: This method enables/disables the CHANNEL_XFER counter.
Note: Counter operations are identical irrespective of whether they are controlled through registers or other
methods.
12.4.5 TZ Non-Secure Bit for the Display Engine

To support programming of a Host1x client (display engines) in TZ (Trust Zone) mode through direct register access, the
Host1x needs to transfer a TZ non-secure bit from the CPU to the display and VI engines.
The following table describes the behavior of TZ non-secure signal to clients.
Table 31: Behavior of TZ Non-Secure Signal
Access-Mode CPU TZ NS bit TZ Non-Secure Bit to Client
Direct MMIO access(read/write) 0 0
Direct MMIO access(read/write) 1 1

Host Subsystem
Access-Mode CPU TZ NS bit TZ Non-Secure Bit to Client
Indirect MMIO access(read/write) 1 0 X
Indirect MMIO access(read/write) 1 1
Push-buffer access(write)(DMA/PIO) X 1
Push-buffer access(Indirect
X 1
reads)(DMA/PIO)
12.4.6 Interrupts
Host1x has following types of interrupts:
12.4.6.1 Host1x Client Interrupt

Host1x is the collection point for all of its clients interrupts. Also it has control over those using status and mask registers with
fields for each client. These client interrupts are forwarded to the central interrupt controller unit, individually through per client
interrupt lines.
12.4.6.2 Host1x Interrupts

Host1x -specific interrupts are specified through the HOST1X_SYNC_HINTSTATUS_0 register while additional interrupts have
been specified through the HOST1X_SYNC_HINTSTATUS_EXT_0 register (see Registers below). Each Host1x interrupt also
has a corresponding mask. An interrupt is cleared by writing a 1 to the corresponding bit.
12.4.6.3 Host1x Syncpt Interrupts

Host1x can generate a syncpt interrupt upon reaching a threshold value by syncpt registers. It can also generate an interrupt
to either CPU (referred to as CPU0 below) or AVP (referred to as CPU1 below).
An interrupt is routed to cpuN when:
(SYNCPT[indx] >= SYNCPT_INT_THRESH[indx]) && (SYNCPT_THRESH_INT_MASK[indx] == cpuN)

The comparison takes wrapping into account. See the “Sync Points (SYNCPTs)” section for more information on
wrapping.
The status is sticky and is PENDING until cleared. Write 1's to clear.
12.4.7 Indirect Register Access

Host1x provides indirect register access to all its clients. An indirect register access involves multiple steps and requires a
channel for the read return data. All registers required for indirect accesses reside in a channel.
Writes involve two Host1x register writes in the owning channel's space; the first write indicates the address (INDOFF, or
INDOFF2 and INDCTRL), and the second indicates the data (INDDATA).
Reads involve two direct Host1x writes, the first indicates the address (again INDOFF, or INDOFF2 and INDCTRL), and the
second indicates the number of reads (INDCNT). It also requires an indeterminable number of direct Host1x reads to the read
return FIFO status register followed by a read to the read return FIFO.
 INDOFF
 INDOFF2
 INDCTRL
1
This mode is not supported for “secure access”, The CPU has to use only “direct access” in “secure mode”.

Host Subsystem
 INDDATA
 INDCNT
Pitfalls — Indirect accesses require a software mutex to ensure that no other software threads access the indirect registers
while issuing the access (since the series of accesses is non-atomic). Indirect reads can only issue counts less than the read
return FIFO size to prevent a deadlock – too many read requests can block popping of the read return FIFO. This restriction
may be even tighter. All module accesses must also be tied to a channel.
In case an indirect write is sent, software must check whether the previous indirect write is through using an immediate sync
increment command to the client.
12.4.8 Direct Register Access

All clients under Host1x have 256KB of address space, which originates from the space specified by indirect offset register
(INDOFF). Host1x’s client address map is dictated by its client's module IDs; these IDs are used in INDOFF to specify the
target module of the register access. A client's address in the Host1x space is calculated as:
address = direct_access_base_address (0x54000000) + (module_id << 18) + 4 * register_offset
Only one pending read per interface can exist. Reads are returned from the client when the client is ready. There are no
latency restrictions.
Indirect versus Direct — a pitfall of direct addressing is variable latency of Host1x’s clients. While this has no impact on writes,
the CPU is blocked until the read returns rendering the CPU idle during that time.
12.4.9 Host Clients

The following table lists the clients that are accessed via Host1x with their module (client) ID, which is used to determine
addresses for direct addressing.
Table 32: Host1x Clients
Client ID
Host1x 0x0
VI 0x2
Display A 0x8
Display B 0x9
HDMI 0xa
DSI 0xc
VIC 0xd
CSI 0xf
DSIB 0x10
MSENC 0x13
TSEC 0x14
SOR 0x15
DPAUX 0x17
ISP 0x18
ISPB 0x1a
12.4.10 Class IDs

The following table lists the class IDs.

Host Subsystem
Class ID
NV_HOST1X_CLASS_ID 0x01
NV_VIDEO_ENCODE_MSENC_CLASS_ID 0x21
NV_VIDEO_STREAMING_VI_CLASS_ID 0x30
NV_VIDEO_STREAMING_ISP_CLASS_ID 0x32
NV_VIDEO_STREAMING_ISPB_CLASS_ID 0x34
NV_GRAPHICS_VIC_CLASS_ID 0x5D
NV_DISPLAY_CLASS_ID 0x70
NV_DISPLAYB_CLASS_ID 0x71
NV_HDMI_CLASS_ID 0x77
NV_DISPLAY_DSI_CLASS_ID 0x79
NV_DISPLAY_DSIB_CLASS_ID 0x7A
NV_TSEC_CLASS_ID 0xE0
NV_SOR_CLASS_ID 0x7B
NV_DPAUX_CLASS_ID 0x7D
12.4.11 Host Address Space

Each channel is allocated 16KB of space, and they are aligned contiguously at the top of the Host's address space. A
channel's space consists of channel registers, the command FIFO, and an aliased frame buffer region, which are unique per
channel. The rest of the space consists of asynchronous, synchronous and read DMA registers, which are aliased in each
channel – there exists only one copy.
12.4.11.1 Channel Map

The following table gives offsets from the channel base address for different sets of registers available to each channel.
Table 33: Host1x Channel Map
0x0000 Channel Registers
0x0600 RDMA Registers
0x0800 Command FIFO
0x1000 Frame Buffer
ACTMON1(MSENC) = 0x2000 – 0x203F

Unit ACTMON
0x2000-0x20FF ACTMON2(VIC) =0x2040 – 0x207F
Registers
ACTMONRSVD =0x2080 – 0x20FF
0x2100* Synchronous Registers
0x3FFF Bottom
* 0x2100 is the synchronous registers base (HOST1X_CHANNEL_SYNC_REG_BASE)

Host Subsystem
12.4.11.2 Host1x Map

The following table shows the Host1x addresses for the CPU. Channels start at the lowest addresses and are aligned
contiguously. Direct access to Host clients starts at 5400_0000, but this is configurable through a BAR register.
Table 34: Host1x Map

Address Range Channel
5000_0000-5000_3FFF Channel 0 (16KB)
5000_4000-5000_7FFF Channel 1 (16KB)
5000_8000-5000_BFFF Channel 2 (16KB)
5000_E000-5001_2FFF Channel 3 (16KB)
5001_3000-5001_6FFF Channel 4 (16KB)
5001_7000-5001_AFFF Channel 5 (16KB)
5001_B000-5001_BFFF Channel 6 (16KB)
5001_C000-5001_FFFF Channel 7 (16KB)
5002_0000-5002_3FFF Channel 8 (16KB)
5002_4000-5002_7FFF Channel 9 (16KB)
5002_8000-5002_BFFF Channel 10 (16KB)
5002_C000-5002_FFFF Channel 11 (16KB)
12.5 Performance
12.5.1 Key Use Cases

Command throughput must be sufficient when all channels are active, the CDMA is active, and spooling is active.
12.5.2 Latency Targets

Direct read latency must be under 1 ms. Clients that cannot guarantee that a read will return in under 1 ms must not be read
directly but indirectly.
12.5.3 Bandwidth Targets

As Host1x unit is used only for sending control commands to clients and usually at the frame interval.
As these control commands are short (~200 to 300 words maximum), it is expected that the bandwidth requirement on each
client should be less than 1MB/s, whereas the maximum available bandwidth per client on the HWR bus will be (206*4B)/12
=68MB/s at 206 MHz Host1x clock. The minimum bandwidth on the HWR bus per client is 33.34 MB/s at 100 MHz clock which
should easily meet the client requirement.
12.6 Host1x Programming Model

The Host programming models resides on top of the concept of channels. A channel provides the means for software to
supply an ordered sequence of commands to one or more classes. There are no restrictions on how many classes a channel
may own or how often it can switch between classes, but it can only operate on one class at a time (known as the working
class) and one command at a time. A stalled channel does not allow any commands to proceed from any class – there is a

Host Subsystem
strict ordering of commands. A channel starts processing commands simply when commands are present, either supplied by
the CPU or gathered from memory. A channel can be stopped explicitly by a CPU write to channel state.
A single channel owning multiple classes and clients:
Figure 19: Single Channel Example
12.6.1 Concurrency
Channels operate in parallel and are unhindered by one another except in two specific cases:
 Synchronization points
 Class contention

Host Subsystem
The following figure depicts such concurrency.
Figure 20: Channel Concurrency Example
In the example above, no channel is blocked by another at any time so both can work concurrently. Care must be taken when
assigning clients to channels. Channel concurrency as well as channel throughput is crucial for performance. For example, a
client that is event-driven with a low latency requirement should exist in its own channel. Conversely, two clients that must be
steadily supplied with commands could possibly coexist in the same channel given that their synchronization points are not
conflicting (if they have any real synchronization points at all). Clients that operate sequentially on the same piece of data can
easily reside in the same channel.
Clients with low-latency requirements like described in the first example above should possibly be moved to a PIO
programming model and away from a channel-based model.
12.6.2 Synchronization
There are 192 total synchronization points (syncpts). Similar to semaphores, syncpt methods are issued to clients, mentioning
syncpt counter index and returning condition. Any channel can be made to wait on a syncpt value of a particular syncpt index
through Host1x “wait” method. Once the syncpt method is received by clients, based on syncpt condition, they will return a
syncpt index back to Host1x. On receiving a syncpt index from the client, Host1x will increment that particular syncpt counter.
The following simple example below details how syncpts and waits allow for synchronization. The arrows simply indicate
channel dependencies, which channel is waiting for syncpt increment from other channel.

Host Subsystem
Figure 21: Channel Synchronization Example
12.6.3 Progress Status

Channel progress is monitored through two means – GET and syncpts. GET is a channel state that indicates the address of
the last command that has executed in the channel. GET is the same as DMAGET.
Syncpts are counter registers that are incremented when specified events occur (e.g., after the completion of each operation
done by a module). The 32-bit syncpt values typically are monotonically increasing and can be used for in channel waits and
out-of-channel interrupts.
The GET and syncpt registers can also be read directly (out-of-band) by the CPU.
12.6.4 Syncpt Base Register Use Case

The syncpt base registers are modified through LOAD_SYNCPT_BASE_32 or INCR_SYNCPT_BASE_32 methods and are
used with the WAIT_SYNCPT_BASE_32 method.
This mechanism is useful when software wants to wait for a particular syncpt increment, but software does not know the
absolute value of the sync point register until later.
The "future-value" of a sync point is the value that the syncpt register contains right after a particular increment has occurred.
Consider this example:
In this example, time increases downward (later (lower) lines are ahead in time).
Software "knows" the syncpointA future-value equals N at this point; software "knows" the baseA future-value equals N at this
point.
1. command1
2. increment syncpointA to N+1
3. command2

Host Subsystem
4. increment syncpointA to N+2
5. command3
6. wait until command1 is done (syncpoint == N+1)
7. command4
8. wait until command2 is done (syncpoint == N+2)
9. command5
If software actually DOES know the value of N then regular WAIT_SYNCPT works fine here. However, the user space
software driver (which is creating this list of commands) does not know what the value N is until after these commands (1-9)
are all flushed to the kernel space driver.
The kernel space driver receives packets of commands from many different user space processes. When it receives a packet
of commands it queues those commands (i.e., writes the Host1x PUT pointer). It also keeps track of all increments that have
occurred in all commands that have been queued so far. The "future-value" of each sync point is simply the total number of
increments that have occurred since the beginning of time (actually "beginning of time" is really the point in time where the
kernel space driver was initialized and reset all the syncpt registers to 0).
So when the kernel space driver queues these commands (1-9), it knows the value N (i.e., the sum of all increments since the
beginning of time). It can pass this back to the user space driver. But the user space driver does not know how many
increments will be queued before commands 1-9 are queued because any other process can queue commands (including
increments) at any time (e.g., after the user space driver has written commands 2 and 4 to the buffer, but before those
commands have been queued by the kernel driver).
To solve this, we add a command at the end of each packet that increments the base register the same number of times as
the sync point was incremented:
10. baseA += 2
This means that, at the start of any packet of commands, the future value of syncpointA and the future value of baseA are
always the same. So command 6 can be:
WAIT_SYNCPT_BASE syncpt=A base=A offset=1
and command 8 can be:
WAIT_SYNCPT_BASE syncpt=A base=A offset=2
Note: Software never writes a new value to the syncpointA or baseA register except when the kernel driver
is initialized (e.g., when the system boots). After that only the syncpoint register is incremented and
only the base register is added to. All of this depends on all software that creates cooperating
command buffers. Software has this policy (e.g., the user space driver always tells the kernel driver
how many increments are contained in each packet of commands).
12.6.5 Indirect/Direct Register Addressing Scheme

The indirect addressing scheme works as follows:
 An address is decoded and either routed to a channel register or to a synchronous register

 A write to INDCNT or INDDATA triggers a register access to the register specified in INDOFF
 A transaction is created and pushed into the REGF FIFO. The owning channel is specified by which INDCNT or
INDDATA is written. The client and offset are specified in INDOFF.
 The transaction is routed to the target client over the HWR bus.

Host Subsystem
 If the access is a write, the transaction is complete. In the case of a read, the processor polls the channel's read
return FIFO status (FIFOSTAT), waiting for a nonempty FIFO.
 The client returns the read to the channel's return FIFO.
 The processor reads INDDATA register of that particular channel to pops data from the return FIFO.
Direct addressing uses the same flow with some adjustments:
 An address is decoded and either routed to a channel register, a synchronous register, or a client
 This step is nonexistent; direct accesses do not require a trigger.
 In the case of a client decode, a transaction is created and pushed into a FIFO called REGF. The owning channel is
specified as CPU_READ_RETURN_TAG. The client and offset are indicated by the address: the client is created by
shifting the address down by 18; the offset is simply the lower 18 bits.
 The transaction is routed to the target client over the HWR bus. If the access is a write, the transaction is complete.
 In case of a read, client returns the read data and channel ID in the returned packet indicates its destination, be it
interface or a channel’s return FIFO. If the channel is 0-8, it is an indirect read and returned to the indicated channel.
If the channel matches CPU_READ_RETURN_TAG(0xf), the data is returned to the IP interface.
Currently, there is support for only one pending read per interface.
12.7 Host Channel Opcodes

This section provides the format of opcodes that can be sent through the command FIFO.
HCFCMD
Generic command FIFO packet (contains fields common to all opcodes) and is used for initial decode. All command FIFO
packets are multiples of 32 bits.
HCFSETCL
The SetClass opcode specifies which class is being referenced (may cause rerouting of subsequent methods/data). In addition
to switching classes, the opcode allows some methods to be programmed on the switch similar to an HCFMASK opcode.
HCFINCR
The Incrementing opcode indicates the offset should be incremented for each data that is part of the packet. The count
argument indicates how many 32-bit values are following. If channel protect is enabled, the host should prevent a channel
switch from occurring at the end of this command packet.
HCFNONINCR
The Non-Incrementing opcode indicates the same offset should be sent for each data that is part of the packet. The count
argument indicates how many 32-bit values are following. If channel protect is enabled, the host should prevent a channel
HCFMASK
The Mask opcode, from the starting offset, generates offsets based on where the bits are set in the mask. The host expects
the amount of data following to equal the number of bits set. If channel protect is enabled, the host should prevent a channel

Host Subsystem
HCFIMM
The Immediate opcode indicates the offset and data are contained in the same 32-bit data. Only the lowest 16 bits of data are
sent to the module (IMMDATA). The upper 16 bits are zeroed out.
HCFRESTART
The Restart opcode is specific to DMA operation and causes the host to set DMAGET to (ADDRESS << 4), so the next
command fetch will be from (DMASTART + DMAGET).
In legacy chips, bits 27:0 were not decoded and assumed to be 0's (allowing only simply wrapping of GET back to the top of
the command buffer). ADDRESS can be 0 for compatible RESTARTs or non-zero acting as a JUMP.
Note that the jump address granularity is 16 bytes, since the bottom 4 bits cannot be specified.
HCFGATHER
The Gather opcode allows contiguous portions of memory to be fetched and placed in line with the command stream,
replacing the two words of the gather command. It optionally can put an incrementing or non-incrementing opcode in the
stream ahead of the gathered data. This allows for the gathered data to be a pure data stream and not be required to have
host opcodes inside.
HCFCHDONE
This opcode indicates to the command processor that the current channel is done processing for now and is willing to give up
any of its owned modules to other channels that need them.
12.8 Host Channel Registers

12.8.1 HOST1X_CHANNEL_FIFOSTAT_0
CFNUMEMPTY is the number of free slots available in the per-channel command. A FIFO is needed for PIO or polling for
completion of a wait.
31 X INDRDY: Indicates that INDCOUNT==0, so it should be OK to issue another read
28:24 X OUTFENTRIES: Number of entries available for reading in this channel's output FIFO
20:16 X REGFNUMEMPTY: Register write/read FIFO free count
CFGATHER: Indicates whether GATHER is active. If a GATHER command issued via

PIO, software must wait for the GATHER to be IDLE before issuing another command.
12 X
0 = IDLE
1 = BUSY
CFEMPTY: Indicates whether the command FIFO is empty or not

11 X 0 = NOTEMPTY
1 = EMPTY
10:0 X CFNUMEMPTY: Command FIFO free count

Host Subsystem
12.8.2 HOST1X_CHANNEL_INDOFF_0
The INDOFF and INDOFF2 registers (along with INDCNT and INDDATA) are used to indirectly read/write modules outside the
host. If AUTOINC is set, INDOFFSET increments by 4 on every access of INDDATA. REGFNUMEMPTY is polled to
determine when valid data can be read from INDDATA.
The INDOFF register has limited capability on chips with large memory maps. If the top bit of the memory address is >= 27, all
of memory cannot be addressed with INDOFF. In these cases, use INDOFF2 to set the offset while still using INDOFF to set
the other parameters. Always have INDOFFUPD set to NO_UPDATE in these cases. For register accesses, using INDOFF
(with INDOFFUPD set to UPDATE) is always more efficient, since it only requires one write.
Indirect frame buffer writes are STRONGLY DISCOURAGED. There are better ways to write to memory (direct and through
the channel memory map) and there is limited flow control in the host. It is very easy to get into trouble with indirect frame
buffer writes.
Offset: 0x4 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
AUTOINC: Auto increment of read/write address

31 X 0 = DISABLE
1 = ENABLE
ACCTYPE: Access type: indirect register or indirect frame buffer

30 X 0 = REG
1 = FB
BUF32B: Buffer up 32 bits of register data before sending it. Otherwise, register writes will
be sent as soon as they are received. Does not support byte writes in 16-bit host. Does
29 X not affect frame buffer writes.
0 = NOBUF
1 = BUF
INDSWAP: Indirect frame buffer access swap control.

00 = No byte swap
01 = 16-bit byte swap ([31:0] -> {[23:16],[31:24],[7:0],[15:8]})
10 = 32-bit byte swap ([31:0] -> {[7:0],[15:8],[23:16],[31:24]})
28:27 X 11 = 32-bit word swap ([31:0] -> {[15:8],[7:0],[31:24],[23:16]})
0 = NONE
1 = BYTE16
2 = BYTE32
3 = WORD32
INDMODID: ACCTYPE=REG: Register module ID

0 = HOST1X
2 = VI
8 = DISPLAY
9 = DISPLAYB
10 = HDMI
11 = TVO
12 = DSI
25:18 X
13 = VIC
16 = DSIB
19 = MSENC
20 = TSEC
21 = SOR
23 = DPAUX
24 = ISP
26 = ISPB
25:2 X INDOFFSET: ACCTYPE=FB: frame buffer address
17:2 X INDROFFSET: ACCTYPE=REG: register offset ([15:0])
INDOFFUPD: Optionally disable the update of INDOFFSET when writing this register
0 X 0 = UPDATE
1 = NO_UPDATE

Host Subsystem
12.8.3 HOST1X_CHANNEL_INDCNT_0
Indirect Register Access Count

Used to trigger indirect reads. Holds the number of registers/memory locations that will be read out. Channels should not
request more than there is space available in their output FIFO. Only the protected channel should make liberal use of this
feature for speeding up context switching.
For indirect frame buffer reads, each channel cannot issue more than NV_HOST1X_MAX_IND_FB_READS at once. The
read data must return and be written into the per-channel output FIFO before any additional reads can be issued.
15:0 0x0 INDCOUNT
12.8.4 HOST1X_CHANNEL_INDDATA_0
This register, when written, writes to the data to the INDOFFSET in INDOFF. For reads, a REGFNUMEMPTY number of 32-bit
values can be read before needing to poll FIFOSTAT again. The per-channel output FIFO (OUTFENTRIES) is readable via
this offset. A read of INDDATA will pop an entry off of the per-channel output FIFO.
Offset: 0xc │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X INDDATA: read or write data
12.8.5 HOST1X_CHANNEL_RAISE_0
The general-purpose channels have DMA and RAISE/REFCOUNT functionality.
Any raise values returned from a client module are converted to vectors and update the per-channel raise register. The RAISE
vector is also writable by the CPU. Any bits set in the RAISE field when written will be set in the RAISE register, allowing any
pending WAITs to continue.
31:2 X RAISE: This channel's RAISE vector
12.8.6 HOST1X_CHANNEL_DMASTART_0
This register triggers a DMA fetch from the frame buffer for this channel, if the Put register does not equal the DMA Get
register.
31:2 X DMASTART: cmdbuf frame buffer offset
12.8.7 HOST1X_CHANNEL_DMAPUT_0
This register triggers a DMA fetch from the frame buffer for this channel, if the PUT register does not equal the GET register.
This address is relative to the DMASTART base address. Does not support byte writes. All 4-byte data need to be
programmed.

Host Subsystem
Offset: 0x18 │ Read/Write: R/W │ Reset: 0x00000000 (0b000000000000000000000000000000xx)
31:2 0x0 DMAPUT: cmdbuf frame buffer offset
12.8.8 HOST1X_CHANNEL_DMAGET_0
This register tracks the frame-buffer offset the DMA engine has read up to (incremented as entries are loaded from the
channels command buffer into the FIFO). This address is relative to the DMASTART base address.
31:2 X DMAGET: cmdbuf frame buffer offset
12.8.9 HOST1X_CHANNEL_DMAEND_0
The boundary of illegal addresses (either end of push-buffer or end of physical memory). This is designed to prevent DMA
from prefetching illegal addresses. If DMA reaches this address before seeing a RESTART, it will stop. This would be a
software error condition.
31:2 X DMAEND: cmdbuf frame buffer offset
12.8.10 HOST1X_CHANNEL_DMACTRL_0
DMA Control Register

DMAGETRST: Reset GET pointer to '0'. Useful for cleaning up crashed channels. DMAGET is not updated instantly. Takes
4 cycles between programming of reset and a valid DMAGET.
DMAGETINIT: Reset the GET pointer to the value of DMAPUT when DMAGETRST is asserted.
DMASTOP: Stop DMA from fetching on this channel.
Note: A Command DMA channel needs to be enabled for PIO-gather to work.
DMAINITGET: Reset GET pointer to the value of DMAPUT when DMAGETRST is

asserted.
2 0x0
0 = DISABLE
1 = ENABLE
DMAGETRST: Reset GET pointer to '0'. Useful for cleaning up crashed channels.
1 0x0 0 = DISABLE
1 = ENABLE
DMASTOP: Stop DMA from fetching on this channel. NOTE: a Command DMA channel
needs to be enabled for PIO gather to work.
0 0x1
0 = RUN
1 = STOP

Host Subsystem
12.8.11 HOST1X_CHANNEL_INDOFF2_0
Indirect frame-buffer writes are STRONGLY DISCOURAGED. There are better ways to write to memory (direct and through
the channel memory map) and there is limited flow control in the host. It is very easy to get into trouble with indirect frame-
buffer writes.
INDMODID2: ACCTYPE=REG: register module ID

0 = HOST1X
2 = VI
8 = DISPLAY
9 = DISPLAYB
10 = HDMI
11 = TVO
12 = DSI
25:18 X
13 = VIC
16 = DSIB
19 = MSENC
20 = TSEC
21 = SOR
23 = DPAUX
24 = ISP
26 = ISPB
31:2 X INDOFFSET2: ACCTYPE=FB: frame buffer address
17:2 X INDROFFSET2: ACCTYPE=REG: register offset ([15:0])
12.8.12 HOST1X_CHANNEL_TICKCOUNT_HI_0
This register holds the high 32 bits of the tick count value.
31:0 X TICKS_HI
12.8.13 HOST1X_CHANNEL_TICKCOUNT_LO_0
This register holds the low 32 bits of tick count value.
31:0 X TICKS_LO

Host Subsystem
12.8.14 HOST1X_CHANNEL_CHANNELCTRL_0
This register will be used for controlling some channel-related commands including enabling/disabling of the tick counter,
including enabling/disabling of Kernel command filtering from the gather buffers.
Offset: 0x98 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0x0)
KERNEL_FILTER_GBUFFER: Enable setclass command filter for gather buffers

1 = ENABLE
ENABLETICKCNT: enable or disable tick counter

1 = ENABLE
12.8.15 HOST1X_CHANNEL_PAYLOAD_0
31:0 0x0 PAYLOAD
12.8.16 HOST1X_CHANNEL_STALLCTRL_0
Offset: 0xa0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
0 0x0 ENABLE_CHANNEL_STALL
12.8.17 HOST1X_CHANNEL_STALLCOUNT_HI_0
Offset: 0xa4 │ Read/Write: R/W │ Reset: 0x00000000 (0b00000000000000000000000000000000)
31:0 0x0 STALLCOUNT_HI
12.8.18 HOST1X_CHANNEL_STALLCOUNT_LO_0
31:0 0x0 STALLCOUNT_LO
12.8.19 HOST1X_CHANNEL_XFERCTRL_0
Offset: 0xac │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
0 0x0 ENABLE_CHANNEL_XFER
12.8.20 HOST1X_CHANNEL_CHANNEL_XFER_HI_0
Offset: 0xb0 │ Read/Write: R/W │ Reset: 0x00000000 (0b00000000000000000000000000000000)

Host Subsystem
31:0 0x0 CHANNEL_XFER_HI
12.8.21 HOST1X_CHANNEL_CHANNEL_XFER_LO_0
31:0 0x0 CHANNEL_XFER_LO
12.8.22 HOST1X_CHANNEL_HOST1X_CHANNEL_SPARE_0
Offset: 0xb8 │ Read/Write: R/W │ Reset: 0x00ff0000 (0b00000000111111110000000000000000)
31:16 0xff CHANNEL_SPARE_HI
15:0 0x0 CHANNEL_SPARE_LO
12.9 Host SYNC Registers

12.9.1 HOST1X_SYNC_INTSTATUS_0
INTSTATUS - interrupt status contains the interrupt status for all of the client modules. These status bits are only status.
Writing '1' to them will not clear them. Software must clear the interrupt in the appropriate module, which should be reflected
here.
Offset: 0x0 │ Read/Write: RO │ Reset: 0xXXXXXX0X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
SYNCPT_CPU1_INT: set if SYNCPT_CPU1_INTSTATUS has a pending interrupt

31 X 0 = NOT_PENDING
1 = PENDING
SYNCPT_CPU0_INT: set if SYNCPT_CPU0_INTSTATUS has a pending interrupt

1 = PENDING
ISPB_INT:
1 = PENDING
ISP_INT:
1 = PENDING
DPAUX_INT:
1 = PENDING
SOR_INT:
1 = PENDING
TSEC_INT:
1 = PENDING

Host Subsystem
MSENC_INT:
1 = PENDING
DSIB_INT:
1 = PENDING
VIC_INT:
1 = PENDING
DSI_INT:
1 = PENDING
HDMI_INT:
1 = PENDING
DISPLAYB_INT:
9 X 0 = NOT_PENDING
1 = PENDING
DISPLAY_INT:
8 X 0 = NOT_PENDING
1 = PENDING
VI_INT:
2 X 0 = NOT_PENDING
1 = PENDING
HOST_INT:
0 X 0 = NOT_PENDING
1 = PENDING
12.9.2 HOST1X_SYNC_INTMASK_0
Contains a master interrupt mask for all interrupt signals. If the interface's MASK_ALL bit is disabled, no interrupts will be
triggered on that interface. This applies to only the non-syncpt interrupts.
CPU1_INT_MASK_ALL:
1 0x0 0 = DISABLE
1 = ENABLE
CPU0_INT_MASK_ALL:
0 0x0 0 = DISABLE
1 = ENABLE
12.9.3 HOST1X_SYNC_INTC0MASK_0
INTC0MASK - Interrupt Mask for CPU0

Contains the interrupt mask bits for all of the client modules. If the INT_MASK is ENABLED for a particular module, the
modules INT bit from INTSTATUS contributes to CPU0's interrupt signal.
Offset: 0x8 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxx0x00x000xx0xx00x000xxxxx0x0)
26 0x0 ISPB_INT_C0MASK:
0 = DISABLE

Host Subsystem

1 = ENABLE
ISP_INT_C0MASK:
24 0x0 0 = DISABLE
1 = ENABLE
DPAUX_INT_C0MASK:
23 0x0 0 = DISABLE
1 = ENABLE
SOR_INT_C0MASK:
21 0x0 0 = DISABLE
1 = ENABLE
TSEC_INT_C0MASK:
20 0x0 0 = DISABLE
1 = ENABLE
MSENC_INT_C0MASK:
19 0x0 0 = DISABLE
1 = ENABLE
DSIB_INT_C0MASK:
16 0x0 0 = DISABLE
1 = ENABLE
VIC_INT_C0MASK:
13 0x0 0 = DISABLE
1 = ENABLE
DSI_INT_C0MASK:
12 0x0 0 = DISABLE
1 = ENABLE
HDMI_INT_C0MASK:
10 0x0 0 = DISABLE
1 = ENABLE
DISPLAYB_INT_C0MASK:
9 0x0 0 = DISABLE
1 = ENABLE
DISPLAY_INT_C0MASK:
8 0x0 0 = DISABLE
1 = ENABLE
VI_INT_C0MASK:
2 0x0 0 = DISABLE
1 = ENABLE
HOST_INT_C0MASK:
0 0x0 0 = DISABLE
1 = ENABLE
12.9.4 HOST1X_SYNC_INTC1MASK_0
INTC1MASK - Interrupt Mask for CPU1

Contains the interrupt mask bits for all of the client modules. If the INT_MASK is ENABLED for a particular module, the
modules INT bit from INTSTATUS contributes to the CPU1's interrupt signal.
Offset: 0xc │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxx0x00x000xx0xx00x000xxxxx0x0)
ISPB_INT_C1MASK:
26 0x0 0 = DISABLE
1 = ENABLE

Host Subsystem
ISP_INT_C1MASK:
24 0x0 0 = DISABLE
1 = ENABLE
DPAUX_INT_C1MASK:
23 0x0 0 = DISABLE
1 = ENABLE
SOR_INT_C1MASK:
21 0x0 0 = DISABLE
1 = ENABLE
TSEC_INT_C1MASK:
20 0x0 0 = DISABLE
1 = ENABLE
MSENC_INT_C1MASK:
19 0x0 0 = DISABLE
1 = ENABLE
DSIB_INT_C1MASK:
16 0x0 0 = DISABLE
1 = ENABLE
VIC_INT_C1MASK:
13 0x0 0 = DISABLE
1 = ENABLE
DSI_INT_C1MASK:
12 0x0 0 = DISABLE
1 = ENABLE
HDMI_INT_C1MASK:
10 0x0 0 = DISABLE
1 = ENABLE
DISPLAYB_INT_C1MASK:
9 0x0 0 = DISABLE
1 = ENABLE
DISPLAY_INT_C1MASK:
8 0x0 0 = DISABLE
1 = ENABLE
VI_INT_C1MASK:
2 0x0 0 = DISABLE
1 = ENABLE
HOST_INT_C1MASK:
0 0x0 0 = DISABLE
1 = ENABLE
12.9.5 HOST1X_SYNC_HINTSTATUS_0
Host Interrupt Status

Contains the interrupt status for the various host interrupts. The status is sticky and is PENDING until cleared (write 1's to
INTSTATUS to clear).
Offset: 0x20 │ Read/Write: R/W │ Reset: 0xX0000000 (0bx00xxxxxxxxx00000x00000000000000)
HINTSTATUS_EXT_INT: Additional interrupts pending in the

HINSTATUS_EXT register
31 RO X
0 = NOT_PENDING
1 = PENDING
30 RW 0x0 TIMER_INTP: Timer Interrupt from the Protected Channel

Host Subsystem

0 = NOT_PENDING
1 = PENDING
29 RW 0x0 CSW_HOST1XW2MC_INT: Host write client FIFO has filled up
RDMA_DATABUF_THOLD_INT0: Read DMA data FIFO in port0 reached

high level watermark
19 RW 0x0
0 = NOT_PENDING
1 = PENDING
RDMA_BUF_THOLD_INT0: Buffer threshold reached in read DMA port0

18 RW 0x0 0 = NOT_PENDING
1 = PENDING
RDMA_BUF_OFLOW_INT0: Buffer overflow in read DMA port0

1 = PENDING
RDMA_INVAL_CLREQ_INT: Invalid client request to read DMA

1 = PENDING
XBAR_TSEC_TIMEOUT_ID: ID of the CPU which timed out and updated

the timeout address
15 RW 0x0
0 = TSEC
1 = XBAR
UNIT2_ACTMON_INTR: Unit2 ACTMON generates interrupt

1 = PENDING
UNIT1_ACTMON_INTR: Unit1 ACTMON generates interrupt

1 = PENDING
WAIT_INT11: WAIT has completed on channel 11

1 = PENDING

1 = PENDING

1 = PENDING

1 = PENDING

1 = PENDING

1 = PENDING

1 = PENDING

1 = PENDING

1 = PENDING
2 RW 0x0 WAIT_INT2: WAIT has completed on channel 2

Host Subsystem

0 = NOT_PENDING
1 = PENDING

1 = PENDING

1 = PENDING
12.9.6 HOST1X_SYNC_HINTMASK_0
Host Interrupt Mask

Contains the interrupt mask bits for all of the host interrupts. If the INT_MASK is ENABLED for a particular module, the
modules INT bit from INTSTATUS contributes to the global interrupt signal.
Offset: 0x24 │ Read/Write: R/W │ Reset: 0x00000000 (0b000xxxxxxxxx0000xx00000000000000)
HINTSTATUS_EXT_INTMASK:
31 0x0 0 = DISABLE
1 = ENABLE
TIMER_INTMASKP: Timer Interrupt Mask for the Protected Channel

30 0x0 0 = DISABLE
1 = ENABLE
CSW_HOST1XW2MC_INTMASK:
29 0x0 0 = DISABLE
1 = ENABLE
RDMA_DATABUF_THOLD_INTMASK0:
19 0x0 0 = DISABLE
1 = ENABLE
RDMA_BUF_THOLD_INTMASK0:
18 0x0 0 = DISABLE
1 = ENABLE
RDMA_BUF_OFLOW_INTMASK0:
17 0x0 0 = DISABLE
1 = ENABLE
RDMA_INVAL_CLREQ_INTMASK:
16 0x0 0 = DISABLE
1 = ENABLE
UNIT2_ACTMON_INTRMASK:
13 0x0 0 = DISABLE
1 = ENABLE
UNIT1_ACTMON_INTRMASK:
12 0x0 0 = DISABLE
1 = ENABLE
WAIT_INTMASK11:
11 0x0 0 = DISABLE
1 = ENABLE
WAIT_INTMASK10:
10 0x0 0 = DISABLE
1 = ENABLE
WAIT_INTMASK9:
9 0x0
0 = DISABLE

Host Subsystem

1 = ENABLE
WAIT_INTMASK8:
8 0x0 0 = DISABLE
1 = ENABLE
WAIT_INTMASK7:
7 0x0 0 = DISABLE
1 = ENABLE
WAIT_INTMASK6:
6 0x0 0 = DISABLE
1 = ENABLE
WAIT_INTMASK5:
5 0x0 0 = DISABLE
1 = ENABLE
WAIT_INTMASK4:
4 0x0 0 = DISABLE
1 = ENABLE
WAIT_INTMASK3:
3 0x0 0 = DISABLE
1 = ENABLE
WAIT_INTMASK2:
2 0x0 0 = DISABLE
1 = ENABLE
WAIT_INTMASK1:
1 0x0 0 = DISABLE
1 = ENABLE
WAIT_INTMASK0:
0 0x0 0 = DISABLE
1 = ENABLE
12.9.7 HOST1X_SYNC_HINTSTATUS_EXT_0
Extended Host Interrupt Status

Contains additional interrupt status bits that did not fit in the HINTSTATUS register. When any of these bits is set, the
HINTSTATUS_EXT_INT bit will also be set in the HINSTATUS register. Each status bit is sticky and PENDING until cleared
(write 1's to HINTSTATUS_EXT to clear).
Offset: 0x28 │ Read/Write: R/W │ Reset: 0x00000000 (0b00xxxxxxxxxxxxxxxxxx000000000000)
IP_WRITE_INT: Write transaction timeout occurred after IP_BUSY_TIMEOUT cycles.

Offending address in IP_WRITE_TIMEOUT_ADDR.
31 0x0
0 = NOT_PENDING
1 = PENDING
IP_READ_INT: Read transaction timeout occurred after IP_BUSY_TIMEOUT cycles.

Offending address in IP_READ_TIMEOUT_ADDR.
30 0x0
0 = NOT_PENDING
1 = PENDING
CMDPP_ILLEGAL_OPCODE_INT11: CMDPP11 has seen an illegal opcode.

11 0x0 0 = NOT_PENDING
1 = PENDING

1 = PENDING

Host Subsystem

1 = PENDING

1 = PENDING

1 = PENDING

1 = PENDING

1 = PENDING

1 = PENDING

1 = PENDING

1 = PENDING

1 = PENDING

1 = PENDING
12.9.8 HOST1X_SYNC_HINTMASK_EXT_0
Offset: 0x2c │ Read/Write: R/W │ Reset: 0x00000000 (0b00xxxxxxxxxxxxxxxxxx000000000000)
IP_WRITE_INTMASK:
31 0x0 0 = DISABLE
1 = ENABLE
IP_READ_INTMASK:
30 0x0 0 = DISABLE
1 = ENABLE
CMDPP_ILLEGAL_OPCODE_INTMASK11: See
CMDPP_ILLEGAL_OPCODE_INTMASK0
11 0x0
0 = DISABLE
1 = ENABLE
CMDPP_ILLEGAL_OPCODE_INTMASK10: See
CMDPP_ILLEGAL_OPCODE_INTMASK0
10 0x0
0 = DISABLE
1 = ENABLE
CMDPP_ILLEGAL_OPCODE_INTMASK9: See CMDPP_ILLEGAL_OPCODE_INTMASK0

9 0x0 0 = DISABLE
1 = ENABLE
8 0x0 CMDPP_ILLEGAL_OPCODE_INTMASK8: See CMDPP_ILLEGAL_OPCODE_INTMASK0

0 = DISABLE

Host Subsystem

1 = ENABLE

7 0x0 0 = DISABLE
1 = ENABLE

6 0x0 0 = DISABLE
1 = ENABLE

5 0x0 0 = DISABLE
1 = ENABLE

4 0x0 0 = DISABLE
1 = ENABLE

3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE

1 0x0 0 = DISABLE
1 = ENABLE
CMDPP_ILLEGAL_OPCODE_INTMASK0: Mask CMDPP_ILLEGAL_OPCODE_INT0

interrupt bit.
0 0x0
0 = DISABLE
1 = ENABLE
12.9.9 HOST1X_SYNC_CF_SETUPDONE_0
Write to this register to trigger an update of the FIFO's pointers. ONLY DO THIS WHEN THE FIFO IS EMPTY.
Offset: 0xa0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
0 X CF_SETUPDONE: Dummy bit
12.9.10 HOST1X_SYNC_CMDPROC_CTRL_0
Offset: 0xa4 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxx0xx00x)
5 0x0 INTFC_CLKEN_OVR
2 0x0 GATHER_PARSE_DISABLED
1 0x0 DROP_ILLEGAL_OPCODES
12.9.11 HOST1X_SYNC_CMDPROC_STAT_0
Offset: 0xa8 │ Read/Write: RO │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
11:0 X ILLEGAL_OPCODE

Host Subsystem
12.9.12 HOST1X_SYNC_CMDPROC_STOP_0
CH*_CMDPROC_STOP stops issuing commands from the command FIFO. This is useful to stop other channels when a
channel teardown is needed to prevent unwanted traffic from happening at the same time.
Offset: 0xac │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxx000000000000)
CH11_CMDPROC_STOP:
11 0x0 0 = RUN
1 = STOP
CH10_CMDPROC_STOP:
10 0x0 0 = RUN
1 = STOP
CH9_CMDPROC_STOP:
9 0x0 0 = RUN
1 = STOP
CH8_CMDPROC_STOP:
8 0x0 0 = RUN
1 = STOP
CH7_CMDPROC_STOP:
7 0x0 0 = RUN
1 = STOP
CH6_CMDPROC_STOP:
6 0x0 0 = RUN
1 = STOP
CH5_CMDPROC_STOP:
5 0x0 0 = RUN
1 = STOP
CH4_CMDPROC_STOP:
4 0x0 0 = RUN
1 = STOP
CH3_CMDPROC_STOP:
3 0x0 0 = RUN
1 = STOP
CH2_CMDPROC_STOP:
2 0x0 0 = RUN
1 = STOP
CH1_CMDPROC_STOP:
1 0x0 0 = RUN
1 = STOP
CH0_CMDPROC_STOP:
0 0x0 0 = RUN
1 = STOP
12.9.13 HOST1X_SYNC_CH_TEARDOWN_0
Channel teardown register. Tells the hardware that a channel has gone away. Will reset that channel's command FIFO and
release any locks it has in the arbiter. Will NOT reset that channel's output FIFO, which can be emptied by reading out all
remaining entries.
Offset: 0xb0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
CH11_TEARDOWN:
11 X 0 = NO_ACTION
1 = TEARDOWN

Host Subsystem
CH10_TEARDOWN:
10 X 0 = NO_ACTION
1 = TEARDOWN
CH9_TEARDOWN:
9 X 0 = NO_ACTION
1 = TEARDOWN
CH8_TEARDOWN:
8 X 0 = NO_ACTION
1 = TEARDOWN
CH7_TEARDOWN:
7 X 0 = NO_ACTION
1 = TEARDOWN
CH6_TEARDOWN:
6 X 0 = NO_ACTION
1 = TEARDOWN
CH5_TEARDOWN:
5 X 0 = NO_ACTION
1 = TEARDOWN
CH4_TEARDOWN:
4 X 0 = NO_ACTION
1 = TEARDOWN
CH3_TEARDOWN:
3 X 0 = NO_ACTION
1 = TEARDOWN
CH2_TEARDOWN:
2 X 0 = NO_ACTION
1 = TEARDOWN
CH1_TEARDOWN:
1 X 0 = NO_ACTION
1 = TEARDOWN
CH0_TEARDOWN:
0 X 0 = NO_ACTION
1 = TEARDOWN
12.9.14 HOST1X_SYNC_MOD_TEARDOWN_0
Module teardown register. If a module is reset, the host needs to reset its state with respect to which channels own that
module. Whenever a module is reset, the corresponding teardown bit in this register should be written. Module teardown will
only work if the command FIFO and command processor are in a good state (the FIFO is empty of traffic for that channel and
the command processor is at an opcode boundary). If an entire channel needs to be reset, the CH_TEARDOWN register
should be used instead.
Offset: 0xb4 │ Read/Write: R/W │ Reset: 0x0XXXXX0X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
ISPB_TEARDOWN:
26 X 0 = NO_ACTION
1 = TEARDOWN
ISP_TEARDOWN:
24 X 0 = NO_ACTION
1 = TEARDOWN
DPAUX_TEARDOWN:
23 X 0 = NO_ACTION
1 = TEARDOWN

Host Subsystem
SOR_TEARDOWN:
21 X 0 = NO_ACTION
1 = TEARDOWN
TSEC_TEARDOWN:
20 X 0 = NO_ACTION
1 = TEARDOWN
MSENC_TEARDOWN:
19 X 0 = NO_ACTION
1 = TEARDOWN
DSIB_TEARDOWN:
16 X 0 = NO_ACTION
1 = TEARDOWN
VIC_TEARDOWN:
13 X 0 = NO_ACTION
1 = TEARDOWN
DSI_TEARDOWN:
12 X 0 = NO_ACTION
1 = TEARDOWN
HDMI_TEARDOWN:
10 X 0 = NO_ACTION
1 = TEARDOWN
DISPLAYB_TEARDOWN:
9 X 0 = NO_ACTION
1 = TEARDOWN
DISPLAY_TEARDOWN:
8 X 0 = NO_ACTION
1 = TEARDOWN
VI_TEARDOWN:
2 X 0 = NO_ACTION
1 = TEARDOWN
12.9.15 HOST1X_SYNC_DISPLAY_STATUS_0
The per-client status registers indicate which channel owns each client as well as the current working class for each client.
This is useful for determining each client's state with regard to granting context switches. _CURRCL is the current class ID for
that module.
Offset: 0xdc │ Read/Write: RO │ Reset: 0x0XXX0000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
25:16 X DISPLAY_CURRCL
12.9.16 HOST1X_SYNC_DISPLAYB_STATUS_0
Offset: 0xe0 │ Read/Write: RO │ Reset: 0x0XXX0000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
25:16 X DISPLAYB_CURRCL

Host Subsystem
12.9.17 HOST1X_SYNC_ISP_STATUS_0
25:16 X ISP_CURRCL
12.9.18 HOST1X_SYNC_DSI_STATUS_0
25:16 X DSI_CURRCL
12.9.19 HOST1X_SYNC_HDMI_STATUS_0
Offset: 0xec │ Read/Write: RO │ Reset: 0x0XXX0000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
25:16 X HDMI_CURRCL
12.9.20 HOST1X_SYNC_SOR_STATUS_0
Offset: 0xf0 │ Read/Write: RO │ Reset: 0x0XXX0000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
25:16 X SOR_CURRCL
12.9.21 HOST1X_SYNC_DPAUX_STATUS_0
25:16 X DPAUX_CURRCL
12.9.22 HOST1X_SYNC_VI_STATUS_0
25:16 X VI_CURRCL
12.9.23 HOST1X_SYNC_DSIB_STATUS_0
Offset: 0xfc │ Read/Write: RO │ Reset: 0x0XXX0000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
25:16 X DSIB_CURRCL
12.9.24 HOST1X_SYNC_VIC_STATUS_0
Offset: 0x100 │ Read/Write: RO │ Reset: 0x0XXX0000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)

Host Subsystem
25:16 X VIC_CURRCL
12.9.25 HOST1X_SYNC_MSENC_STATUS_0
25:16 X MSENC_CURRCL
12.9.26 HOST1X_SYNC_TSEC_STATUS_0
25:16 X TSEC_CURRCL
12.9.27 HOST1X_SYNC_ISPB_STATUS_0
Offset: 0x10c │ Read/Write: RO │ Reset: 0x0XXX0000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
25:16 X ISPB_CURRCL
12.9.28 HOST1X_SYNC_DIRECT_MODULE_CONFIG_0
Offset: 0x1a0 │ Read/Write: R/W │ Reset: 0x54000000 (0b010101000000000000000000000000xx)
31:2 0x15000000 BASE
12.9.29 HOST1X_SYNC_USEC_CLK_0
Number of host clocks needed to make a microsecond. Used for the DELAY host method. For example, if the host clock is
250 MHz, this register should be programmed to 250. If the host clock is 150 MHz, this register should be programmed to
150.
Offset: 0x1a4 │ Read/Write: R/W │ Reset: 0x0000015e (0bxxxxxxxxxxxxxxxxxxxx000101011110)
11:0 0x15e USEC_CLKS
12.9.30 HOST1X_SYNC_CTXSW_TIMEOUT_CFG_0
When a channel writes to a new class on a client, it generates a context switch. To keep from continually switching contexts if
channels are addressing the same client, this register is used, so that the Host1x does not switch until the channel has either
received WAIT_CTXSW_CNT clocks before switching or the channel stops targeting the particular client. If two channels are
accessing two classes of a client, to guarantee a channel sending multiple commands for a class, this register can be used.
Offset: 0x1a8 │ Read/Write: R/W │ Reset: 0x0000000f (0bxxxxxxxxxxxxxxxxxxxxxxxx00001111)
7:0 0xf WAIT_CTXSW_CNT: Number of cycles to wait

Host Subsystem
12.9.31 HOST1X_SYNC_INDREG_DMA_CTRL_0
Enable use of DMA engine to move data from indirect register interface to memory. ATTN_LVL controls flow between host and
DMA. DMA will not start a transfer until the set number of slots are full:
 00 = 1 slot
 01 = 4 slots
 10 = 8 slots
Offset: 0x1ac │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxx000x0000)
AHBDMA_ENABLE: Enable generation of request to DMA engine

7 0x0 0 = DISABLE
1 = ENABLE
AHBDMA_ATTN_LVL: Number of entries to receive before sending DMA request, 1, 4, or

6:5 0x0
8
AHBDMA_CHID: channel being used by indirect read for DMA (which chout FIFO to
3:0 0x0
monitor)
12.9.32 HOST1X_SYNC_CHANNEL_PRIORITY_0
Set channel priority for dual ring arbitration (hi/lo). Used in arbitrating MLOCKs.
Offset: 0x1b0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxx000000000000)
HIPRI_CH11:
11 0x0 0 = DISABLE
1 = ENABLE
HIPRI_CH10:
10 0x0 0 = DISABLE
1 = ENABLE
HIPRI_CH9:
9 0x0 0 = DISABLE
1 = ENABLE
HIPRI_CH8:
8 0x0 0 = DISABLE
1 = ENABLE
HIPRI_CH7:
7 0x0 0 = DISABLE
1 = ENABLE
HIPRI_CH6:
6 0x0 0 = DISABLE
1 = ENABLE
HIPRI_CH5:
5 0x0 0 = DISABLE
1 = ENABLE
HIPRI_CH4:
4 0x0 0 = DISABLE
1 = ENABLE
HIPRI_CH3:
3 0x0 0 = DISABLE
1 = ENABLE
2 0x0 HIPRI_CH2:
0 = DISABLE

Host Subsystem

1 = ENABLE
HIPRI_CH1:
1 0x0 0 = DISABLE
1 = ENABLE
HIPRI_CH0:
0 0x0 0 = DISABLE
1 = ENABLE
12.9.33 HOST1X_SYNC_CDMA_ASM_TIMEOUT_0
Timeout value determines how long the assembly logic will wait before it flushes data from the data FIFO to avoid head-of-line
blocking.
Note: Do not use a value of zero -- causes immediate flushing so no forward progress is made.
Offset: 0x1b4 │ Read/Write: R/W │ Reset: 0x00000404 (0bxxxxxxxxxxxxxxxxxxx00100xxx00100)
12:8 0x4 CDMA_ASM_GFIFO_TIMEOUT
4:0 0x4 CDMA_ASM_DFIFO_TIMEOUT
12.9.34 HOST1X_SYNC_CDMA_MISC_0
CDMA_DELAY_PUT
Delay put_addr updates. This can potentially increase MC performance slightly by gathering multiple consecutive put_addr
updates into 1 update, which reduces the amount of requests to the MC. In addition, it can be used to cover a race condition
where a write to memory has not completed before CDMA starts fetching the data. But in this case, the counter has to be set
to a high value, which *will* affect performance.
CDMA_SIMPLE_PREFETCH
Reduce per-channel requests to 1 every 3 cycles. This can reduce performance in 2 ways:
 The memory request FIFO will fill up slightly slower, but the impact will be minimal.
 It will cause the channel arbiter to switch to other channels when they have a request available, which will reduce
locality. On the plus side, it has much less nasty corner cases.
CDMA_PUT_SYNC_DISABLE
CDMA_EN_STATS
Enable statistics counters.
 - Count the number of 128-bit words fetched by CDMA

 - Count the number of 128-bit words thrown away by CDMA
This allows us to get an idea how efficient the CDMA really is when there are multiple push-buffers active at the same time.
Offset: 0x1b8 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxx0x000xx000000)
12 0x0 CDMA_EN_STATS
10 0x0 CDMA_CLKEN_OVR

Host Subsystem
9 0x0 CDMA_PUT_SYNC_DISABLE
8 0x0 CDMA_SIMPLE_PREFETCH
5:0 0x0 CDMA_DELAY_PUT
12.9.35 HOST1X_SYNC_IP_BUSY_TIMEOUT_0
Offset: 0x1bc │ Read/Write: R/W │ Reset: 0x00000000 (0b00000000000000000000000000000000)
31:0 0x0 IP_BUSY_TIMEOUT: Number of busy cycles before requesting a retry. 0 = disabled
12.9.36 HOST1X_SYNC_IP_READ_TIMEOUT_ADDR_0
Offset: 0x1c0 │ Read/Write: RO │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:2 X IP_READ_TIMEOUT_ADDR: Address of transaction that caused an AXI read timeout
12.9.37 HOST1X_SYNC_IP_WRITE_TIMEOUT_ADDR_0
Offset: 0x1c4 │ Read/Write: RO │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:2 X IP_WRITE_TIMEOUT_ADDR: Address of transaction that caused an AXI write timeout
12.9.38 HOST1X_SYNC_MCCIF_THCTRL_0
Memory write client FIFO status. Reads out the available 128-bit entries. If writing through the buffered frame buffer write
region, writes are accumulated up to 128 bits before being flushed, so 10 entries can mean up to 40 writes. Memory client
high-priority threshold control register. Sets the threshold of when the client becomes high priority.
Offset: 0x1d8 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxx000000xxxxxxxx)
13:8 RW 0x0 CSW_HOST1XW2MC_HPTH
5:0 RO X CSW_HOST1XW_FIFOSTAT
12.9.39 HOST1X_SYNC_HC_MCCIF_FIFOCTRL_0
Memory Client Interface FIFO Control (where applicable) and Clock Gating Control Register
Note: This FIFO timing aspects of this register are no longer supported, but are retained for software
compatibility.
The clock override/ovr_mode fields of this register control the 2nd-level clock gating for the client and MC side of the MCCIF.
All clock gating is enabled by default.
A '1' written to the rclk/wclk override field results in one of the following:
 With wclk/rclk override mode = LEGACY, the clock reverts to legacy mode of operation where the clock is on
whenever the client clock is enabled.

Host Subsystem
 With wclk/rclk override mode = ON, the clock is always on inside the MCCIF and PC.
A '1' written to the cclk override field keeps the client's clock always on inside the MCCIF.
Offset: 0x1dc │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxx00000xxxxxxxxxxxx0000)
HC_RCLK_OVR_MODE:
20 LEGACY 0 = LEGACY
1 = ON
HC_WCLK_OVR_MODE:
1 = ON
18 0x0 HC_CCLK_OVERRIDE
17 0x0 HC_RCLK_OVERRIDE
16 0x0 HC_WCLK_OVERRIDE
HC_MCCIF_RDCL_RDFAST:
1 = ENABLE
HC_MCCIF_WRMC_CLLE2X:
1 = ENABLE
HC_MCCIF_RDMC_RDFAST:
1 = ENABLE
HC_MCCIF_WRCL_MCLE2X:
1 = ENABLE
12.9.40 HOST1X_SYNC_TIMEOUT_WCOAL_HC_0
Write Coalescing Time-Out Register
Note: Write coalescing is no longer supported by the MCCIF clients. Registers are retained for software
compatibility but are not used by the hardware.
Offset: 0x1e0 │ Read/Write: R/W │ Reset: 0x00000032 (0bxxxxxxxxxxxxxxxxxxxxxxxx00110010)
7:0 0x32 HOST1XW_WCOAL_TMVAL
12.9.41 HOST1X_SYNC_MLOCK_0_0
MLOCK Registers
MLOCK is 1 whenever someone holds the lock, and is 0 otherwise. MLOCK is normally set and cleared using the host
methods ACQUIRE_MLOCK and RELEASE_MLOCK.
If a CPU wants to acquire a lock, then it reads this register. If the value returned is 0, it has successfully acquired the MLOCK.
A return value of 1 indicates that the acquire failed. At any time, the CPU can write 0 to MLOCK, releasing the MLOCK (note
that hardware does not check if the CPU owned the lock). If the CPU writes a 1 to MLOCK, this is undefined and is ignored by
the hardware (a NOP). Use MLOCK_OWNER to read the status of a lock (since reading MLOCK itself has a side effect).

Host Subsystem
Offset: 0x2c0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
0 0x0 MLOCK_0
0 0x0 MLOCK_1
0 0x0 MLOCK_2
Offset: 0x2cc │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
0 0x0 MLOCK_3
Offset: 0x2d0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
0 0x0 MLOCK_4
0 0x0 MLOCK_5
0 0x0 MLOCK_6
Offset: 0x2dc │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
0 0x0 MLOCK_7

Host Subsystem
Offset: 0x2e0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
0 0x0 MLOCK_8
0 0x0 MLOCK_9
0 0x0 MLOCK_10
Offset: 0x2ec │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
0 0x0 MLOCK_11
0 0x0 MLOCK_12
0 0x0 MLOCK_13
0 0x0 MLOCK_14

Host Subsystem
Offset: 0x2fc │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
0 0x0 MLOCK_15
12.9.57 HOST1X_SYNC_MLOCK_OWNER_0_0
MLOCK_OWNER is a read-only status for MLOCK. When MLOCK_*_OWNS are all zeros, it indicates that the MLOCK is free
(zero). When MLOCK has been acquired (set), then one of MLOCK_*_OWNS will be non-zero.
Either bit 0 or 1 will be set -- indicating whether a channel or a CPU has acquired the MLOCK. If a channel owns the MLOCK,
then the channel number is given by the MLOCK_OWNER_CHID field.
11:8 X MLOCK_OWNER_CHID_0
1 X MLOCK_CPU_OWNS_0
0 X MLOCK_CH_OWNS_0
0 X MLOCK_CH_OWNS_1
0 X MLOCK_CH_OWNS_2
0 X MLOCK_CH_OWNS_3

Host Subsystem
0 X MLOCK_CH_OWNS_4
0 X MLOCK_CH_OWNS_5
0 X MLOCK_CH_OWNS_6
0 X MLOCK_CH_OWNS_7
0 X MLOCK_CH_OWNS_8

Host Subsystem
0 X MLOCK_CH_OWNS_9
0 X MLOCK_CH_OWNS_10

Host Subsystem
12.9.73 HOST1X_SYNC_MLOCK_ERROR_0_0
If a channel attempts to release an MLOCK that it does not own, then the release has no effect on MLOCK, but the
corresponding error bit is set (this includes releasing an MLOCK owned by no one).
Offset: 0x3c0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
15 0x0 MLOCK_ERROR_15
9 0x0 MLOCK_ERROR_9
8 0x0 MLOCK_ERROR_8
7 0x0 MLOCK_ERROR_7
6 0x0 MLOCK_ERROR_6
5 0x0 MLOCK_ERROR_5
4 0x0 MLOCK_ERROR_4
3 0x0 MLOCK_ERROR_3
2 0x0 MLOCK_ERROR_2
1 0x0 MLOCK_ERROR_1
0 0x0 MLOCK_ERROR_0
12.9.74 HOST1X_SYNC_SYNCPT_BASE_n_0
Syncpt base registers are used by wait_syncpt_base method. The wait will be released when SYNCPT[indx] >=
(BASE[base_indx] + offset), where indx, base_indx, and offset are supplied by the wait method.

Host Subsystem
There are 64 Syncpt base registers, where n = 0 through 63.
Offset: 0x600 + (n * 0x4) │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X BASE_n
12.10 Host Class Methods

Class offsets are always relative to the class (based at 0).
12.10.1 NV_CLASS_HOST_INCR_SYNCPT_0
All Classes have the INCR_SYNCPT method. For host, this method, immediately increments SYNCPT[indx], irrespective of
the condition. Note that INCR_SYNCPT_CNTRL and INCR_SYNCPT_ERROR are included for consistency with host clients,
but writes to INCR_SYNCPT_CNTRL have no effect on the operation of Host1x, and because there are no condition FIFOs to
overflow, INCR_SYNCPT_ERROR will never be set.
Offset: 0x0 │ Byte Offset: 0x0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxx0000000000000000)
COND: Condition mapped from raise/wait

0 = IMMEDIATE
1 = OP_DONE
2 = RD_DONE
3 = REG_WR_SAFE
4 = COND_4
5 = COND_5
6 = COND_6
7 = COND_7
8 = COND_8
9 = COND_9
10 = COND_10
11 = COND_11
12 = COND_12
13 = COND_13
14 = COND_14
15 = COND_15
16 = COND_16
15:8 0x0
17 = COND_17
18 = COND_18
19 = COND_19
20 = COND_20
21 = COND_21
22 = COND_22
23 = COND_23
24 = COND_24
25 = COND_25
26 = COND_26
27 = COND_27
28 = COND_28
29 = COND_29
30 = COND_30
31 = COND_31
7:0 0x0 INDX: syncpt index value

Host Subsystem
12.10.2 NV_CLASS_HOST_INCR_SYNCPT_CNTRL_0
Offset: 0x1 │ Byte Offset: 0x4 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxx0xxxxxxx0)
INCR_SYNCPT_NO_STALL: If NO_STALL is 1, then when FIFOs are full,

INCR_SYNCPT methods will be dropped and the INCR_SYNCPT_ERROR[COND] bit will
8 0x0 be set.
If NO_STALL is 0, then when FIFOs are full, the client host interface will be stalled.
INCR_SYNCPT_SOFT_RESET: If SOFT_RESET is set, then all internal states of the

0 0x0 client syncpt block will be reset. To do a soft reset, first set SOFT_RESET of all Host1x
clients affected, then clear all SOFT_RESETs.
12.10.3 NV_CLASS_HOST_INCR_SYNCPT_ERROR_0
Offset: 0x2 │ Byte Offset: 0x8 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
COND_STATUS: COND_STATUS[COND] is set if the FIFO for COND overflows. This bit
31:0 X
is sticky and will remain set until cleared. Cleared by writing 1.
12.10.4 NV_CLASS_HOST_WAIT_SYNCPT_0
Wait on syncpt method.
Command dispatch will stall until:
SYNCPT[indx][NV_HOST1X_SYNCPT_THRESH_WIDTH-1:0] >= threshold[NV_HOST1X_SYNCPT_THRESH_WIDTH-

1:0]
The comparison takes into account the possibility of wrapping. Note that more bits are allocated for index and threshold than
may be used in an implementation. Use NV_HOST1X_SYNCPT_NB_PTS for the number of syncpts, and
NV_HOST1X_SYNCPT_THRESH_WIDTH for the number of bits used by the comparison.
31:24 X INDX
23:0 X THRESH
12.10.5 NV_CLASS_HOST_WAIT_SYNCPT_BASE_0
Wait on syncpt method using base register.
Command dispatch will stall until:
SYNCPT[indx][NV_HOST1X_SYNCPT_THRESH_WIDTH-1:0] >= (SYNCPT_BASE[base_indx]+offset)
The comparison takes into account the possibility of wrapping. Note that more bits are allocated for INDX and BASE_INDX
than may be used in an implementation. Use NV_HOST1X_SYNCPT_NB_PTS for the number of syncpts, Use
NV_HOST1X_SYNCPT_NB_BASES for the number of syncpt_bases, and NV_HOST1X_SYNCPT_THRESH_WIDTH for the
number of bits used by the comparison If NV_HOST1X_SYNCPT_THRESH_WIDTH is greater than 16, the offset is sign-
extended before it is added to SYNCPT_BASE.
31:24 X INDX

Host Subsystem
23:16 X BASE_INDX
15:0 X OFFSET
12.10.6 NV_CLASS_HOST_WAIT_SYNCPT_INCR_0
Wait on syncpt increment method.
Command dispatch will stall until the next time that SYNCPT[indx] is incremented.
Note that more bits are allocated for INDX than may be used in an implementation. Use NV_HOST1X_SYNCPT_NB_PTS for
the number of syncpts.
Offset: 0xa │ Byte Offset: 0x28 │ Read/Write: R/W │ Reset: 0xXX000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:24 X INDX
12.10.7 NV_CLASS_HOST_LOAD_SYNCPT_BASE_0
Load syncpt base method.
SYNCPT_BASE[indx] = value
Offset: 0xb │ Byte Offset: 0x2c │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:24 X BASE_INDX
23:0 X VALUE
12.10.8 NV_CLASS_HOST_INCR_SYNCPT_BASE_0
Increment syncpt base method.
SYNCPT_BASE[indx] += offset
Offset: 0xc │ Byte Offset: 0x30 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:24 X BASE_INDX
23:0 X OFFSET
12.10.9 NV_CLASS_HOST_CLEAR_0
Clear method. Any bits set in VECTOR will be cleared in the channel's RAISE vector.
Offset: 0xd │ Byte Offset: 0x34 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X VECTOR
12.10.10 NV_CLASS_HOST_WAIT_0
Wait method. Command dispatch will stall until any of the bits set in VECTOR become set in the channel's RAISE vector.
Offset: 0xe │ Byte Offset: 0x38 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)

Host Subsystem
31:0 X VECTOR
12.10.11 NV_CLASS_HOST_WAIT_WITH_INTR_0
Wait with Interrupt method. Identical to the WAIT method except an interrupt will be triggered when the WAIT requirement is
satisfied. This is obsolete and preserved here only for completeness.
Offset: 0xf │ Byte Offset: 0x3c │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X VECTOR
12.10.12 NV_CLASS_HOST_DELAY_USEC_0
Delay number of microseconds. Command dispatch will stall until the number of microseconds indicated in NUSEC has
passed. The timing of microseconds is controlled by the USEC_CLK register.
Offset: 0x10 │ Byte Offset: 0x40 │ Read/Write: R/W │ Reset: 0x000XXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
19:0 X NUSEC: Enough for 1.05 seconds
12.10.13 NV_CLASS_HOST_TICKCOUNT_HI_0
This register value will initialize the high 32 bits of the tick count value in the host clock counter.
31:0 X TICKS_HI: Read or write tick count
12.10.14 NV_CLASS_HOST_TICKCOUNT_LO_0
This register value will initialize the low 32 bits of the tick count value in the host clock counter.
31:0 X TICKS_LO: Read or write tick count
12.10.15 NV_CLASS_HOST_TICKCTRL_0
This register write enables the tick counter on the host clock to start counting.
Offset: 0x13 │ Byte Offset: 0x4c │ Read/Write: R/W │ Reset: 0x0000000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
TICKCNT_ENABLE: Enable or Disable tick counter

0 X 0 = DISABLE
1 = ENABLE

Host Subsystem
12.10.16 NV_CLASS_HOST_INDCTRL_0
Indirect Addressing
These registers (along with INDDATA) are used to indirectly read/write either register or memory. Host registers are not
accessible using this interface. If AUTOINC is set, INDOFFSET increments by 4 on every access of INDDATA.
Either INDCTRL/INDOFF2 or INDOFF can be used, but INDOFF may not be able to address all memory in chips with large
memory maps. The redundant bits in INDCTRL and INDOFF are shared, so writing either offset sets those bits.
Note: The following restrictions apply to the use of indirect memory writes:
• At initialization time, do a dummy indirect write (with all byte enables set to zero)
• Dedicate an MLOCK for indirect memory writes, then before a channel issues a
set of indirect memory writes it must acquire this MLOCK; after the writes have
been issued, the MLOCK is released -- this will restrict the use of indirect
memory writes to a single channel at a time.
Offset: 0x2b │ Byte Offset: 0xac │ Read/Write: R/W │ Reset: 0xXX00000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
INDBE: Byte enables. Will apply to all subsequent data transactions. Not applicable for
31:28 X
reads.

27 X 0 = DISABLE
1 = ENABLE
SPOOL: Route return data to spool FIFO, only applicable to reads

26 X 0 = DISABLE
1 = ENABLE

1 X 0 = REG
1 = FB
RWN: Read/write
0 X 0 = WRITE
1 = READ
12.10.17 NV_CLASS_HOST_INDOFF2_0
Offset: 0x2c │ Byte Offset: 0xb0 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
INDMODID: ACCTYPE=REG: Register module ID

0 = HOST1X
2 = VI
8 = DISPLAY
9 = DISPLAYB
10 = HDMI
11 = TVO
12 = DSI
25:18 X
13 = VIC
16 = DSIB
19 = MSENC
20 = TSEC
21 = SOR
23 = DPAUX
24 = ISP
26 = ISPB

Host Subsystem
12.10.18 NV_CLASS_HOST_INDOFF_0
Offset: 0x2d │ Byte Offset: 0xb4 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
INDBE: Byte enables. Will apply to all subsequent data transactions. Not applicable for
31:28 X
reads.

27 X 0 = DISABLE
1 = ENABLE
SPOOL: Route return data to spool FIFO, only applicable to reads

26 X 0 = DISABLE
1 = ENABLE
INDMODID: ACCTYPE=REG: register module ID

0 = HOST1X
2 = VI
8 = DISPLAY
9 = DISPLAYB
10 = HDMI
11 = TVO
12 = DSI
25:18 X
13 = VIC
16 = DSIB
19 = MSENC
20 = TSEC
21 = SOR
23 = DPAUX
24 = ISP
26 = ISPB

1 X 0 = REG
1 = FB
RWN: Read/write
0 X 0 = WRITE
1 = READ
12.10.19 NV_CLASS_HOST_INDDATA_0
These registers, when written, either write to the data to the INDOFFSET in INDOFF or trigger a read of the offset at
INDOFFSET. This is an array of 31 identical register entries; the register fields below apply to each entry.
Offset: 0x2e..0x4c │ Byte Offset: 0xb8..0x130 │ Read/Write: R/W │ Reset: 0xXXXXXXXX

(0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X INDDATA: Read or write data
12.10.20 NV_CLASS_HOST_LOAD_SYNCPT_PAYLOAD_32_0
Offset: 0x4e │ Byte Offset: 0x138 │ Read/Write: R/W │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X CHANNEL_SYNCPT_PAYLOAD

Host Subsystem
12.10.21 NV_CLASS_HOST_STALLCTRL_0
Offset: 0x4f │ Byte Offset: 0x13c │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
0 0X0 ENABLE
12.10.22 NV_CLASS_HOST_WAIT_SYNCPT_32_0
Offset: 0x50 │ Byte Offset: 0x140 │ Read/Write: R/W │ Reset: 0x000000XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
7:0 X INDX
12.10.23 NV_CLASS_HOST_WAIT_SYNCPT_BASE_32_0
Offset: 0x51 │ Byte Offset: 0x144 │ Read/Write: R/W │ Reset: 0x0000XXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
15:8 X BASE_INDX
7:0 X INDX
12.10.24 NV_CLASS_HOST_LOAD_SYNCPT_BASE_32_0
Offset: 0x52 │ Byte Offset: 0x148 │ Read/Write: R/W │ Reset: 0x000000XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
7:0 X INDX
12.10.25 NV_CLASS_HOST_INCR_SYNCPT_BASE_32_0
Offset: 0x53 │ Byte Offset: 0x14c │ Read/Write: R/W │ Reset: 0x000000XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
7:0 X INDX
12.10.26 NV_CLASS_HOST_STALLCOUNT_HI_0
Offset: 0x54 │ Byte Offset: 0x150 │ Read/Write: R/W │ Reset: 0x00000000 (0b00000000000000000000000000000000)
31:0 0X0 STALLCOUNT_HI
12.10.27 NV_CLASS_HOST_STALLCOUNT_LO_0
31:0 0X0 STALLCOUNT_LO
12.10.28 NV_CLASS_HOST_XFERCTRL_0
Offset: 0x56 │ Byte Offset: 0x158 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)

Host Subsystem
0 0X0 ENABLE
12.10.29 NV_CLASS_HOST_CHANNEL_XFER_HI_0
Offset: 0x57 │ Byte Offset: 0x15c │ Read/Write: R/W │ Reset: 0x00000000 (0b00000000000000000000000000000000)
31:0 0X0 CHANNEL_XFER_HI
12.10.30 NV_CLASS_HOST_CHANNEL_XFER_LO_0
31:0 0X0 CHANNEL_XFER_LO
12.11 Host Proto Channel Registers

12.11.1 HOST1X_PROTCHANNEL_FIFOSTAT_0
CFNUMEMPTY is the number of free slots available in the per-channel command FIFO (needed for PIO or polling for
completion of a wait).
31 X INDRDY: Indicates that INDCOUNT==0, so it should be OK to issue another read
28:24 X OUTFENTRIES: Number of entries available for reading in this channel's output FIFO
20:16 X REGFNUMEMPTY: Register write/read FIFO free count
CFGATHER: Indicates whether or not GATHER is active. If a GATHER command issued

via PIO, software must wait for the GATHER to be IDLE before issuing another command.
12 X
0 = IDLE
1 = BUSY
CFEMPTY: Indicates whether the command FIFO is empty or not

11 X 0 = NOTEMPTY
1 = EMPTY
10:0 X CFNUMEMPTY: Command FIFO free count
12.11.2 HOST1X_PROTCHANNEL_INDOFF_0

Host Subsystem
buffer writes.

31 X 0 = DISABLE
1 = ENABLE
ACCTYPE: access type: indirect register or indirect frame buffer

30 X 0 = REG
1 = FB
BUF32B: Buffer up 32 bits of register data before sending it. Otherwise, register writes will
be sent as soon as they are received. Does not support byte writes in 16-bit host. Does
29 X not affect frame buffer writes.
0 = NOBUF
1 = BUF
INDSWAP: Indirect frame buffer access swap control.

00 = No byte swap
01 = 16-bit byte swap ([31:0] -> {[23:16],[31:24],[7:0],[15:8]})
10 = 32-bit byte swap ([31:0] -> {[7:0],[15:8],[23:16],[31:24]})
28:27 X 11 = 32-bit word swap ([31:0] -> {[15:8],[7:0],[31:24],[23:16]})
0 = NONE
1 = BYTE16
2 = BYTE32
3 = WORD32
INDMODID: ACCTYPE=REG: register module ID

0 = HOST1X
2 = VI
8 = DISPLAY
9 = DISPLAYB
10 = HDMI
12 = DSI
25:18 X 13 = VIC
16 = DSIB
19 = MSENC
20 = TSEC
21 = SOR
23 = DPAUX
24 = ISP
26 = ISPB
INDOFFUPD: Optionally disable the update of INDOFFSET when writing this register
0 X 0 = UPDATE
1 = NO_UPDATE
12.11.3 HOST1X_PROTCHANNEL_INDCNT_0
Indirect register access count

Used to trigger indirect reads. Holds the number of registers/memory locations that will be read out. Channels should not
request more than there is space available in their output FIFO. Only the protected channel should make liberal use of this
feature for speeding up context switching.
For indirect frame buffer reads, each channel cannot issue more than NV_HOST1X_MAX_IND_FB_READS at once. The
read data must return and be written into the per-channel output FIFO before any additional reads can be issued.

Host Subsystem
15:0 0X0 INDCOUNT
12.11.4 HOST1X_PROTCHANNEL_INDDATA_0
This register, when written, writes the data to the INDOFFSET in INDOFF. For reads, a REGFNUMEMPTY number of 32-bit
values can be read before needing to poll FIFOSTAT again.
The per-channel output FIFO (OUTFENTRIES) is readable via this offset. A read of INDDATA will pop an entry off of the per-
channel output FIFO.
Offset: 0xc │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 0X0 INDDATA: Read or write data
12.11.5 HOST1X_PROTCHANNEL_INDOFF2_0
Note: This spec file contains additions to the "common" registers that cannot be put in the common section,
otherwise all of the other registers will shift.
buffer writes.
INDMODID2: ACCTYPE=REG: register module ID

0 = HOST1X
2 = VI
8 = DISPLAY
9 = DISPLAYB
10 = HDMI
12 = DSI
25:18 X 13 = VIC
16 = DSIB
19 = MSENC
20 = TSEC
21 = SOR
23 = DPAUX
24 = ISP
26 = ISPB
31:2 X INDOFFSET2: ACCTYPE=FB: frame buffer address
17:2 X INDROFFSET2: ACCTYPE=REG: register offset ([15:0])

Host Subsystem
12.11.6 HOST1X_PROTCHANNEL_TICKCOUNT_HI_0
This register holds the high 32 bits of the tick count value
31:0 X TICKS_HI
12.11.7 HOST1X_PROTCHANNEL_TICKCOUNT_LO_0
This register holds the low 32 bits of the tick count value
31:0 X TICKS_LO
12.11.8 HOST1X_PROTCHANNEL_CHANNELCTRL_0
This register will be used for controlling some channel-related commands including enabling/disabling of the tick counter and
enabling/disabling of Kernel command filtering from the gather buffers.
Offset: 0x98 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0x0)
KERNEL_FILTER_GBUFFER: Enable setclass command filter for gather buffers

1 = ENABLE
ENABLETICKCNT: Enable or disable tick counter

1 = ENABLE
12.11.9 HOST1X_PROTCHANNEL_PAYLOAD_0
31:0 0x0 PAYLOAD
12.11.10 HOST1X_PROTCHANNEL_STALLCTRL_0
Offset: 0xa0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
0 0x0 ENABLE_CHANNEL_STALL
12.11.11 HOST1X_PROTCHANNEL_STALLCOUNT_HI_0
31:0 0x0 STALLCOUNT_HI

Host Subsystem
12.11.12 HOST1X_PROTCHANNEL_STALLCOUNT_LO_0
31:0 0x0 STALLCOUNT_LO
12.11.13 HOST1X_PROTCHANNEL_XFERCTRL_0
Offset: 0xac │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
0 0x0 ENABLE_CHANNEL_XFER
12.11.14 HOST1X_PROTCHANNEL_CHANNEL_XFER_HI_0
31:0 0x0 CHANNEL_XFER_HI
12.11.15 HOST1X_PROTCHANNEL_CHANNEL_XFER_LO_0
31:0 0x0 CHANNEL_XFER_LO
12.11.16 HOST1X_PROTCHANNEL_HOST1X_CHANNEL_SPARE_0
Offset: 0xb8 │ Read/Write: R/W │ Reset: 0x00ff0000 (0b00000000111111110000000000000000)
31:16 0xff CHANNEL_SPARE_HI
15:0 0x0 CHANNEL_SPARE_LO
12.11.17 HOST1X_PROTCHANNEL_TICKCOUNT_THRESHOLD_HI_0
This register holds the high 32 bits of the tick count threshold value
Offset: 0xbc │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X TICKS_THRESHOLD_HI
12.11.18 HOST1X_PROTCHANNEL_TICKCOUNT_THRESHOLD_LO_0
This register holds the low 32 bits of the tick count threshold value
Offset: 0xc0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X TICKS_THRESHOLD_LO

Host Subsystem
12.11.19 HOST1X_PROTCHANNEL_TICKCOUNT_THRESHOLD_CTRL_0
Offset: 0xc4 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
THRES_CMP: Enable or disable tick threshold compare

1 = ENABLE

Video Image Compositor
13.0 VIDEO IMAGE COMPOSITOR (VIC)

The VIC is the Video Image Compositor unit. It is also referred to as the Video Scalar (VS) unit. The VIC unit is suitable for
use in mobile systems. It implements video post-processing functions needed by a video playback application to produce the
final image for the player window.
The compositor implements much of the DirectX Video Acceleration 2.0 Enhanced Video Processor specification, including
deinterlacing, scaling, color conversion, proc-amp, and compositing for up to 5 input surfaces. It supports advanced features
like histogram correction, gamma correction, and non-linear color enhancement.
13.1 Features
The VIC implements the following features:
 Deinterlacing
 Inverse Teleciné
 Scale
 Color Conversion
 Memory Format Conversion
 Blend/Composite
 Stereo Pixel Interleave
 Rotation
13.2 Block Diagram Description

The following figure shows the top-level block diagram of the Video Image Compositor.

Figure 22: VIC Block Diagram

VIDEO SCALAR UNIT
FALCON
imem
xt bus host1x
uctl code,
Tegra HRD
uctl data Host Host
DMA uctl
intrpt I/F Interface host1x
dmem
HRD
(THI)
csb irq
irq
<config>
config bus
to all modules
FETCH
Surface Fetch Surface

Cache Control List
to Tegra
Tegra
MC Frame Inverse Telecine (IVTC)
Buffer Temp. Cad.
I/F noise flt. detect
(TFBIF)
SCALE
De- Y- X-
interlace Scaling Scaling
color matrix
BLEND
CConv
Buffer
output
surface Output CConv &
Blending
Buffer ProcAmp
13.2.1 Falcon Microprocessor

The NVIDIA Falcon Microcontroller is used for method processing and performing processing related to inverse telecine.
13.2.2 Tegra Host Interface (THI)

The Tegra Host Interface (THI) shim handles incoming methods from the host1x bus and passes those methods to the Falcon
microcontroller, in addition to handling Tegra sync points.
13.2.3 Tegra Frame Buffer Interface (TFBIF)

The Tegra Frame Buffer Interface (TFBIF) interfaces with the Tegra K1 memory system. The TFBIF has one read and one
write MCCIF client.
13.2.4 Fetch Unit

During preprocessing (IVTC passes) the fetch control breaks the output surfaces into 16x16 byte tiles and processes columns
of these tiles at a time.

During main processing, the fetch control breaks the output surface up into 64x16 pixel tiles and processes those individually.
For each tile, the fetch unit loops over all input surfaces.
When processing each tile, 64*16+n pixels need to be fetched, where n is the extra padding needed for scaling and
deinterlacing. Each tile being fetched is stored in the Surface Cache. This cache holds 128 entries of 256 bytes.
13.2.5 Inverse Telecine (IVTC) Unit

The IVTC unit runs on individual video streams at a time and consists of 2 separate passes.
The first pass does noise reduction and motion buffer updates. It also calculates the weave and artifact counts used for the
IVTC decision. The final decision for IVTC is done in Falcon microcode.
The second pass combines the updated motion buffer and the previous motion buffer (which has a different parity) and
combines them for DiSi1 deinterlacing during the main processing pass.
13.2.6 Scale Unit

The Scale Unit consists of three blocks:
 The first block deinterlaces the input. The deinterlacing modes supported are DiSi1, BOB, and WEAVE. Weave is
only used on progressive content or when inverse telecine detected a cadence.
 The second block scales the data in the vertical direction producing at most 16 lines of output to the next stage.
 The third block scales the data in the horizontal direction producing at most 64 pixels of output.
13.2.7 Blend Unit

The Blend Unit consists of four blocks:
 The first block buffers the incoming data and converts from any input order into interleaved pixel order (either ARGB
or AYUV).
 The second block performs all color conversion tasks.
 The third block blends data into the output buffer. This stage is also used during preprocessing.
 The fourth block is an input-output DMA that can read original buffer data from the memory system and write back the
final blended result. The reading is only used during preprocessing.
13.3 Functionality
13.3.1 Slots
The VIC supports up to five different input pictures that can be composited on to a single surface.
Support for five input pictures enables composition of multiple video streams from Blu-ray video content in a single pass:
 Background
 Primary Video
 Secondary Video
 Presentation Graphics
 Interactive Graphics
Each slot has a state that is specified through the config structure. Control parameters, such as the input formats,
deinterlacing, scaling factors, clipping, color-space conversion, are independently set per input surface. All slots support the
same functionality.

During the composition stage, the slots are blended in ascending order (that is, the output of slot1 will be blended onto slot 0,
the output of slot 2 is blended on to slot 1, etc.).
Each slot can be programmed to access multiple surfaces. The number of surfaces used depends on the type of slot input
(e.g., interlaced versus progressive), input format (e.g., packed versus planar color formats), and also on the type of
processing (e.g., temporal noise reduction versus cadence detection versus deinterlacing).
13.3.1.1 Surface Composition
Figure 23: Programming Input and Output Surface Parameters

Slot0 Input Surface Slot1 Input Surface
Slot0 Source Rect
Slot1 Source Rect
Output Surface
Clear Rect 0
Clear Rect 1
Slot1 Destination Rect
Slot0 Destination Rect
Clear Rect 2
Target Rect
Clear Rect 3
The maximum dimension of any image on the input or output sides of the VIC is 16384 pixels. The upper two bits of any 14-bit
surface dimension will just be ignored.
Via the SurfaceListSurfaceStruct config structures, the dimensions of each input slot surface can be defined along with the
pixel and memory format types. Note that the pixel format type must also be specified in the SurfaceCache0Struct config
structure. A source rectangle defines the region of pixels of the input slot surface that will contribute to the composition of the
output surface, and a destination rectangle defines the region of the output surface that is affected by a given input slot.
Together, the source and destination rectangle parameters specify the scaling ratios desired. Each slot can also dictate how
pixel data is laid out in each surface cache entry by specifying the amount of pixel data, i.e., the number of bytes wide,
logically represented by each cache entry; this provides flexibility in reducing the memory overfetch associated with fetch of
surfaces under various use cases (e.g., scaling ratios, deinterlacing modes).

Via the Blending0Struct config structure, the dimensions of the output surface can be defined along with the pixel and memory
format types. Via the Blending0Struct and the SurfaceList0Struct config structs, a target rectangle can also be defined to
restrict the pixel processing output to a certain rectangle in the output surface. A programmable color can also be set to fill the
background of the target rectangle.
The VIC allows the programming of clear rectangles that prevent the fetch of pixels from specific rectangular regions of input
slots. The use of the clear rectangles can be used to reduce redundant pixel fetches, for example, if an opaque surface is
known to occlude a layer below it, a clear rectangle can be specified to prevent fetching of pixels from the occluded region of
the lower layer. Up to eight clear rectangles are specified via the SurfaceListClearRectStruct config structs, and per-slot clear
rect mask enables are specified via the SurfacelList0Struct config struct, Clear rectangle coordinates are specified relative to
the output surface base.
With the addition of the sub-pixel source rectangle feature, source rectangle coordinates are specified in the config structure in
a U14.16 format, allowing the source rectangle to be specified at a sub-pixel resolution. Destination, target, and clear
rectangles coordinates are pixel aligned.
13.3.2 Memory Format Support

The following memory formats must be supported on input and output. Input and output memory formats do not have to
match.
 Pitch Linear
 Block Linear (16Bx2 kind with sector ordering)
- 64x8 byte GOB format with 16x2 byte sectors
- Contiguous 64B atoms are laid out as 32x2 byte blocks
The VIC Surface Cache supports the above memory formats on input when fetching pixel data from memory.
The VIC Output Buffer supports the above memory formats on input when reading background image data when pre-
processing inverse telecine data from memory, and on the output side when writing composited image data back to memory.
Memory formats supported by the VIC are enumerated as follows:
Table 35 : Memory Format Enumerations
Encoding
Surface Kind Enumeration
(Four Bits)
BLK_KIND_PITCH 0x0
BLK_KIND_GENERIC_16Bx2_TEGRA 0x1
To fully support the Block Linear format, block height should be parameterizable. The following set of enumerations is valid.
Table 36 : Block Height Enumerations
Encoding (Four Bits, log2

Block Height Enumeration Value
Encoding)
ONE_GOB 1 0
TWO_GOBS 2 1
FOUR_GOBS 4 2
EIGHT_GOBS 8 3
SIXTEEN_GOBS 16 4

Encoding (Four Bits, log2

Block Height Enumeration Value
Encoding)
THIRTYTWO_GOBS 32 5
13.3.2.1 Surface Transformation

The Fetch Control unit will be responsible for generating the source image addressing that will implement mirroring (across X-
axis and/or Y-axis) of tiles within the Target rectangle of the output surface.
The output buffer can mirror pixels in the X and Y directions within each output tile. This ability in addition to the fetch control
changes mentioned above gives the ability to flip the contents of the entire Target rectangle about its axis.
The output buffer also supports transposition of the Target Rectangle. This ability when combined with the target rectangle
flips described above gives the ability to rotate images by any multiple of 90 degrees.
Rotation must be done in the pipeline after deinterlacing because the deinterlacer assumes a normal orientation of the input
fields (interlaced field lines run horizontal). Rotation of the image prior to deinterlacing will make the deinterlacer ineffective.
Figure 24: Interlaced Field Lines Run Horizontally
The programmed starting address of the source and destination rectangles will remain at the upper left corner of the unit. The
‘Source Image’ diagrammed below shows the logical tile traversal pattern as the input rectangle traverses the VIC unit (tiles
are read in raster order from left to right, then top to bottom), and the destination rectangle diagrammed below shows the
expected transformations when the programmer specifies the combination of flipX, flipY, and transposeXY transformations
available to be applied to the output rectangle.

Figure 25: Surface Transformation Orientations
Source Image
Normal Horizontal Flip Vertical Flip 180 Degree Rotation
Mirror on 315 Degree Axis 270 Degree Rotation 90 Degree Rotation Mirror on 45 Degree Axis
Table 37: Output Buffer Surface Transformation Controls
Transformation transposeXY flipY flipX
Normal (no transformation) 0 0 0
H flip (mirror on vertical axis) 0 0 1
V flip (mirror on horizontal axis) 0 1 0
180-degree rotation 0 1 1
Mirror on 315-degree axis 1 0 0
Mirror on 45-degree axis 1 1 1
Surface mirroring (FlipX/FlipY) is accomplished via programming of the SurfaceList0Struct, FetchControl0Struct, and the
Blending0Struct config structures. Surface transposition is accomplished via programming of the OutputTranspose field of the
Blending0Struct config structure.

The table below shows the output image for a certain surface composition and how the output transformations affect the final
output. The results of the transformations are summarized in the rules below.
1. The output surface parameters (SurfaceWidth/Height, LumaWidth/Height, ChromaWidth/Height) are not affected by
any of the transformations. It is software’s responsibility to allocate a large enough buffer so that the target
rectangle fits within the output surface even after transformation.
2. The target rectangle position in the output surface does NOT change when output flips (in X or Y) are enabled.
However, the position of the target rectangle is transposed when OutputTranspose is enabled.
3. When output flips are enabled, the entire contents of the target rectangle are flipped, including all ClearRects and
DestinationRects and their contents. The axis of the flip is the axis of the TargetRectangle.
4. When OutputTranspose is enabled, the position of the target rectangle is transposed, as well as all of its contents
(including all clear/destination rectangles).
5. When transpose and flips are enabled together, the overall effect of the transformation happens as if the flip
operations occur first, followed by the transpose operation.
6. When flip operations are enabled, every Destination Rectangle has to lie fully within the TargetRectangle. This rule
has to be enforced to get consistent results while flipping because we define the flip operation as happening about
the target rectangle axis, and clip after we do the flip.

Table 38: Output Buffer Surface Transformation Examples
Transformation TransposeXY FlipY FlipX Image
Normal (no
0 0 0
transformation)
H flip (mirror on
0 0 1
vertical axis)

V flip (mirror on
0 1 0
horizontal axis)
180-degree
0 1 1
rotation

Mirror on 315-
1 0 0
degree axis
270-degree
1 1 0
rotation

90-degree
1 0 1
rotation
Mirror on 45-
1 1 1
degree axis

13.3.3 Memory Copy

The VIC memory copy bandwidth scales with the VIC core frequency. The VIC core pixel processing pipeline can output up to
4x2 components (2 pixels) per VIC clock.
13.3.4 Temporal Noise Reduction

VIC 1.0 implemented a temporal noise reduction algorithm based on a motion adaptive IIR filter, where the filter weight was
adapted based on a few constants and the SOS difference between a 3x3 neighborhood of pixels around the current pixel in
the current and previous frames.
The VIC 1.0 TNR algorithm (hereafter called TNR1) works well for videos or captures that have good lighting conditions and
lower levels of noise in the input video. However, when the lighting conditions are poor and there is a lot of noise in the input
video/capture, the algorithm tries to be safe by not modifying it much, and allows most of the noise to pass through into the
output.
The TNR2 algorithm performs significantly better in the above mentioned cases by pre-filtering the data spatially and allowing
significantly higher alpha values in the IIR blend. This algorithm can be turned on by programming the AdvancedDenoise*
fields in the SurfaceCache0Struct. The TNR2 algorithm also requires information about the lighting conditions at which the
video or capture is being shot (information that will probably be derived from ISP statistics), and this information should be
programmed into the LightLevel fields in the SurfaceListSurfaceStructs (4 bits, 0-darkest, 15-brightest).
13.3.5 Inverse Telecine

There are two statistics that the VIC hardware calculates: the difference count and the artifact count. The VIC hardware just
calculates the statistics; a state machine on the Falcon Microcontroller has to interpret these.
13.3.6 Deinterlacing
The VIC supports various modes of deinterlacing the input video content such as DiSi1, BOB, and WEAVE. Weave is only
used on progressive content or in case inverse telecine detected a cadence.
13.3.7 Color Fill

Programming the output surface with only a background color and writing to memory will produce a color fill.
13.3.8 Bayer Pixel Formats
Bayer pixel data can come from camera sensor equipment in various sizes, for example, 6 bits, 10 bits, 14 bits, 16 bits. Most
Bayer data is stored using existing pixel formats, such as T_L8, or T_L16. In some special cases, special formats are created
to pack pixel data efficiently to work with existing memory formats, for example, T_X2Lc10Lb10La10, T_X2Le6Ld6Lc6Lb6La6.
13.3.9 Pixel Format Support

The VIC pipeline supports an increased number of pixel formats compared to what is currently comprehended by VIC1.0 on
input and output. The VIC pipeline can accept a surface of a given input pixel format and produce a given output pixel format.
The table below lists the supported pixel formats. The symbols in color conversion mode column describe the internal VIC
representation of the format, (e.g., 1P_1C represents 1 plane with 1 component pixels, 2P_1+2C represents 2 planes, 1 plane
with 1 component pixels and a second plane with 2 component pixels).

Table 39: Pixel Format Support
Input Output High Quality New

Pixel Format FOURCC Rotation Scaling Color_Conversion_Mode
Support Support Deinterlacing index
T_A8 Y Y Y Y N 0 1P_1C
T_L8/ T_Y8/ T_YUV100 Y Y Y Y N 1 1P_1C
T_A4L4 Y Y Y Y N 2 1P_2C
T_L4A4 Y Y Y Y N 3 1P_2C
T_R8 Y Y Y Y N 4 1P_1C
T_A8L8 Y Y Y Y N 5 1P_2C
T_L8A8 Y Y Y Y N 6 1P_2C
T_R8G8 Y Y Y Y N 7 1P_2C
T_G8R8 Y Y Y Y N 8 1P_2C
T_B5G6R5 Y Y Y Y N 9 1P_3C
T_R5G6B5 Y Y Y Y N 10 1P_3C
T_B6G5R5 Y Y Y Y N 11 1P_3C
T_R5G5B6 Y Y Y Y N 12 1P_3C
T_A1B5G5R5 Y Y Y Y N 13 1P_4C
T_A1R5G5B5 Y Y Y Y N 14 1P_4C
T_B5G5R5A1 Y Y Y Y N 15 1P_4C
T_R5G5B5A1 Y Y Y Y N 16 1P_4C
T_X1B5G5R5 Y Y Y Y N 21 1P_4C
T_X1R5G5B5 Y Y Y Y N 22 1P_4C
T_B5G5R5X1 Y Y Y Y N 23 1P_4C
T_R5G5B5X1 Y Y Y Y N 24 1P_4C
T_X8B8G8R8 Y Y Y Y N 33 1P_4C
T_X8R8G8B8 Y Y Y Y N 34 1P_4C
T_B8G8R8X8 Y Y Y Y N 35 1P_4C


T_R8G8B8X8 Y Y Y Y N 36 1P_4C
T_A2B10G10R10 Y N Y Y N 37 1P_4C
T_A2R10G10B10 Y N Y Y N 38 1P_4C
T_B10G10R10A2 Y N Y Y N 39 1P_4C
T_R10G10B10A2 Y N Y Y N 40 1P_4C
T_A4P4 Y N Y Y N 41 1P_2C
T_P4A4 Y N Y Y N 42 1P_2C
T_P8A8 Y N Y Y N 43 1P_2C
T_A8P8 Y N Y Y N 44 1P_2C
T_P8 Y N Y Y N 45 1P_1C
T_P1 Y N Y Y N 46 1P_1C
T_U8V8 Y Y Y Y N 47 1P_2C
T_V8U8 Y Y Y Y N 48 1P_2C
T_A8Y8U8V8 (AYUV444
Y Y Y Y N 49 1P_4C
packed)
T_V8U8Y8A8 (AYUV444
Y Y Y Y N 50 1P_4C
packed)
T_Y8_U8__Y8_V8
YUY2/YUYV Y Y Y Y N 51 1P_4C
(YUV422 packed)
T_Y8_V8__Y8_U8
YVYU Y Y Y Y N 52 1P_4C
(YUV422 packed)
T_U8_Y8__V8_Y8
UYVY Y Y Y Y N 53 1P_4C
(YUV422 packed)
T_V8_Y8__U8_Y8
Y Y Y Y N 54 1P_4C
(YUV422 packed)
T_Y8___U8V8_N444
Y Y Y Y N 55 2P_1+2C
(YUV444 semi-planar)
T_Y8___V8U8_N444
Y Y Y Y N 56 2P_1+2C
T_Y8___U8V8_N422
e.g., NV61 Y Y Y Y N 57 2P_1+2C
T_Y8___V8U8_N422
e.g., NV16 Y Y Y Y N 58 2P_1+2C
T_Y8___U8V8_N422R
Y Y Y Y N 59 2P_1+2C
(YUV422R semi-planar)
T_Y8___V8U8_N422R
Y Y Y Y N 60 2P_1+2C
(YUV422R semi-planar)
T_Y8___U8V8_N420
e.g., NV21 Y Y Y Y N 61 2P_1+2C
T_Y8___V8U8_N420
e.g., NV12 Y Y Y Y Y* 62 2P_1+2C
T_Y8___U8___V8_N444
e.g., YV24 Y Y Y Y N 63 3P_1+1+1C
(YUV444 planar)


T_Y8___U8___V8_N422
e.g., YV16 Y Y Y Y N 64 3P_1+1+1C
(YUV422 planar)
T_Y8___U8___V8_N422R
Y Y Y Y N 65 3P_1+1+1C
(YUV422R planar)
T_Y8___U8___V8_N420
e.g., YV12 Y Y Y Y Y 66 3P_1+1+1C
(YUV420 planar)
*Currently, DiSi1 deinterlacing only works on NV24 surfaces and field-based variants of NV12, YV12, YUY2, and UYVY
formats (with each field stored in a separate surface).
In the color format, the notation called “A:B:C” notation is used to describe how often U and V are sampled relative to Y.
444 (4:4:4) means no downsampling of the chroma channels.
422 (4:2:2) means 2:1 horizontal downsampling, with no vertical downsampling. Every scan line contains four Y samples for
every two U and V samples.
420 (4:2:0) means 2:1 horizontal downsampling, with 2:1 vertical downsampling.
R refers to ‘rotated’. 422 by default means horizontal downsampling; while 422R means vertical downsampling. Instead of the
chroma being shared between 2 horizontally adjacent luma components, it is shared between 2 vertically adjacent luma
components.
The VIC does not support 24-bit color formats, either RGB or YUV.
13.3.10 Scaling and Filtering

The VIC contains Y and X-scaler units that together allow 5- or 10-tap polyphase filtering and scaling of the input surface. The
hardware can be programmed with a set of filter coefficients for each filter-type (Detail/Noise/Normal), phase (0,1/32,2/32, ..
32/32), scale ratio (1:1, 2:1, 4:1, 8:1, 16:1), filter_length (5-tap, 10-tap) and stream (sub-picture or normal). Based on the
actual scale-ratio, phase, etc., the hardware can then interpolate between these programmed values for use in the actual
filters.
There are four filter types (5-tap non-substream, 5-tap substream, 10-tap non-substream, 10-tap substream). Five tables are
1
needed for each coefficient type as different tables are needed for different scale down ratio of 1:1, 2:1, 4:1, 8:1 and 16:1 .
Thus 20 tables are needed with a maximum downscale ratio of 16:1.
Each table has 16X4 memory entries (for the 5-tap filter) or 16X9 memory entries (for 10-tap filter). Each memory entry has
three 10-bit base coefficients (for Detail/Noise/Default) that will be feed into a LERP3 simultaneously to interpolate based on
different noise and detail weight. The table has 16 columns, and each column stores all the coefficients for phase 0/32, 1/32,
2/32, 3/32, 4/32, 5/32, 6/32, 7/32, 8/32, 9/32, 10/32, 11/32, 12/32, 13/32, 14/32 and 15/32, with the exception that the first
column stores coefficients for both 0/32 and 16/32.
Each column stores four sets of base coefficients for the 5-tap filter because the last coefficient can be derived from the
remaining four. phase 0/32 and 16/32 are special cases in that only two sets of base coefficients are needed for each of them
in the 5-tap case,only four sets of base coefficients are needed for phase 0/32 in the 10-tap case, and five sets of base
coefficients are needed for phase 16/32 in the 10-tap case. Therefore, phase 0/32 and 16/32 are folded into the same column.
Due to symmetry, the base coefficients for phases 17 through 31 do not need to be stored.
1
1:1 ratio contains identify filter that can be used for all scale up cases. Different scale down ratio requires different coefficients since the
filter is a low pass filter the bandwidth of which is related to the scale ratio. Coefficients for 2:1, 4:1, 8:1 and 16:1 are stored to interpolate
any downscale ratios.

13.3.10.1 Panoramic Scaling

The VIC also implements a “panoramic” scaling mode which can be used to convert images between different aspect ratios
while avoiding any letterboxing. This mode essentially implements a non-linear scaling in the horizontal direction, with the
scale ratio changing as we move away from the center of the image.
Panoramic scaling has an additional parameter p ([-1, 1]) that defines the magnitude of the second order term in a polynomial.
The polynomial parameters for scaling can then be defined as follows.
The original scaling factor f is changed based on the location x ([-1, 1]) within the destination rectangle.
1 − 1 p p<0  12 p p<0
scaling _ factorx = f ∗ ( a + 3bx 2 ) with a= 2 and b = 
 1− p p≥0  p p≥0
The source sample position x’ is therefore calculated as:
x ′ = f ∗ ( ax + bx 3 ) = a ′x + b′x 3 with a ′ = fa and b′ = fb

The new scaling factor can be calculated incrementally using 2 counters.
2 1
Panoramic scaling for 4:3 to 16:9 conversion should have p=− , while 16:9 to 4:3 conversion should have p = for 1:1
3 4
scaling in the center.
13.3.11 Pixel Format Conversion

Color conversion and proc-amp are implemented using a matrix multiplication on every pixel. The matrix only changes when
the surfaces changes.
Current chain of operations:
 Proc-amp + Output CC (4x3 matrix)

 Clamping (optional soft clamping, 2 control entry)
The 4x3 matrix values are specified in the ColorConversionMatrixStruct as S12.8 values. In addition, the result of the matrix
multiplication will be right shifted by r_shift. To allow for highest accuracy r_shift should always be as high as possible without
losing any range in the other coefficients. Note that the constant offsets (c03, c13, c23) are S12.8 and are not affected by
r_shift.
𝑖𝑛0 ≫ 𝑟_𝑠ℎ𝑖𝑓𝑡
𝑜𝑢𝑡0 𝑐00 𝑐01 𝑐02 𝑐03
�𝑜𝑢𝑡1� = �𝑐10 𝑐11 𝑐12 𝑐13� � �
𝑜𝑢𝑡2 𝑐20 𝑐21 𝑐22 𝑐23
1
Soft clamping defines a piecewise linear function consisting of three pieces. The control entries define the area of soft
clamping. For example, the following equation applies for the values a and b:
 0 v < −a
v + a −a ≤v<a
 2

′
v = v a≤v<b
v + b b≤ v < 2−b
 2

 1 2−b≤ v
When converting between pixel formats with components of varying bit width, bit replication is used for expanding component
bit widths, and truncation is used for reducing component bit widths.

Dithering and undithering are not supported.
Data Size Conversion

When expanding the number of bits in a component (e.g., from RGB565 to RGB888), expansion should use bit replication of
the MSBs of the original value to fill in the LSBs of the expanded bit length value. For example, if converting from a 5-bit value
to an 8-bit value, the first 3 MSBs of the source 5-bit value should be concatenated as the 3 new LSBs to the original 5-bit
value to produce the new expanded 8-bit value.
For example: 5-bit R5=11000’b expanded to 8 bit R8=11000110’b
When reducing the number of bits in a component (for example, from RGB888 to RGB565), the LSBs of the old value should
be truncated to arrive at the shortened value.
For example: 8-bit R8=11000000’b reduced to 5 bit R5=11000’b
Replication followed by truncation will ensure that the truncated value will equal the original pre-replicated operand, i.e.,
RGB565RGB888 expansion followed immediately by RGB888RGB565 reduction will result in the same original value.
Luminance Conversion
Conversion from luminance-only color formats (e.g., L8/Y8/YUV100, A8L8) to and from RGB or YUV formats should be done
as outlined below.
 Luminance-only to YUV
LY, 128U, 128V
 Luminance-only to RGB
LR, LG, LB
 YUV to Luminance-only
YL
 Clamp L between 0.0 and 1.0

 RGB to Luminance-only
(R*5 + G*9 + B*2)/16  L
 Clamp L between 0.0 and 1.0
Adding and Removing Alpha

If converting from a pixel format with alpha to a pixel format with no alpha, the alpha value should be dropped.
If converting from a pixel format with no alpha to a pixel format with alpha, the alpha value in the destination pixel format
should be set to 1.0.
13.3.12 Luma Keying

Coefficient values to compute the Luma value of the pixel from the pixel components can be specified in the
ColorConversionLumaAlphaStruct, along with the upper and lower luma key values. Any pixel that has a luma that falls within
the luma key range will have its alpha value zeroed out so that it can be processed appropriately in the blending stage.
13.3.13 Blender
The blender interface allows for symmetric blend modes between the VIC and Display units.
The VIC blender supports the following different blending modes:

 DXVAHD_ALPHA_FILL_MODE_OPAQUE
 DXVAHD_ALPHA_FILL_MODE_BACKGROUND
 DXVAHD_ALPHA_FILL_MODE_DESTINATION
 DXVAHD_ALPHA_FILL_MODE_SOURCE_STREAM
 DXVAHD_ALPHA_FILL_MODE_COMPOSITED
 DXVAHD_ALPHA_FILL_MODE_SOURCE_ALPHA
All modes other than _ALPHA_FILL_MODE_COMPOSITED are as defined in the Microsoft DXVA spec and are carried over
from VIC 1.0. The new mode that allows the VIC and Display blenders to match each other is enabled by setting the
AlphaFillModein the VIC Config Structure to _ALPHA_FILL_MODE_COMPOSITED. When the AlphaFillMode is set to
anything other than _ALPHA_FILL_MODE_COMPOSITED, the srcFact and dstFact parameters specified below are ignored
and do not affect the processing.
The parameterizable blender interface allows a variety of blend modes, including the following:
 Per-Pixel Non-Premultiplied Alpha Blend

output = src*src_alpha + dst*(1-src_alpha)
 Per Pixel Source Premultiplied Alpha Blend
output = src + dst*(1-src_alpha)
 Constant-Alpha Blend
output = src*const_alpha + dst*(1-const_alpha)
 Per-Pixel Non-Premultiplied Alpha Blend with constant blend
output = src*src_alpha*const_alpha + dst*(1-src_alpha*const_alpha)
 Per-Pixel Premultiplied Alpha Blend with constant blend
output = src*const_alpha + dst*(1-src_alpha*const_alpha)
Note that ColorKeySelect should always be set to disabled.
The blend data path will require the color key comparison match result, and per-slot inputs from the config structure to
formulate the blend equation.
srcFactC, srcFactA, dstFactC, and dstFactA multiplicand inputs are determined by the config structure programming and color
key comparison results. Note that VIC’s internal pixel pipeline represents each pixel component as 10 bits, and as a result,
constants from the config struct also require 10-bit representation.
Table 40 : Per-Slot Blend Configuration
Blend Spec Name Register Name Description
K1 AlphaK1 10-bit constant alpha value
K2 AlphaK2 10-bit constant alpha value
3-bit enum which sets srcFactC:

K1: AlphaK1
K1_TIMES_DST: AlphaK1*dstA
srcFactC_Match_Select srcFactCMatchSelect
NEG_K1_TIMES_DST: 1.0-(AlphaK1*dstA)
K1_TIMES_SRC: AlphaK1*srcA
ZERO: 0
3-bit enum which sets dstFactC:

K1: AlphaK1
dstFactC_Match_Select dstFactCMatchSelect
K2: AlphaK2
K1_TIMES_DST: AlphaK1*dstA

Blend Spec Name Register Name Description

NEG_K1_TIMES_SRC: 1.0-(AlphaK1*srcA)
ZERO: 0
ONE: 1.0
3-bit enum which sets srcFactA:

K1: AlphaK1
srcFactA_Match_Select srcFactAMatchSelect K2: AlphaK2
ZERO: 0
3-bit enum which sets dstFactA:

K2: AlphaK2
dstFactA_Match_Select dstFactAMatchSelect NEG_K1_TIMES_SRC: 1.0-(AlphaK1*srcA)
ZERO: 0
ONE: 1.0
1-bit Boolean to override srcR with constant

UseK3 UseOverrideR
values K3R
1-bit Boolean to override srcG with constant

UseK3 UseOverrideG
values K3G
1-bit Boolean to override srcB with constant

UseK3 UseOverrideB
values K3B
1-bit Boolean to override srcA with constant

UseK3 UseOverrideA
values K3A
K3R OverrideR 10-bit source override R value
K3G OverrideG 10-bit source override G value
K3B OverrideB 10-bit source override B value
K3A OverrideA 10-bit source override A value
MaskR MaskR 1-bit Boolean to override outputR to equal dstR
MaskG MaskG 1-bit Boolean to override outputG to equal dstG
MaskB MaskB 1-bit Boolean to override outputB to equal dstB
MaskA MaskA 1-bit Boolean to override outputA to equal dstA
Given the source and destination factor settings based on config structure inputs and color match results, the per-pixel blend
equations are as follows, where srcR, srcG, srcB, srcA, dstR, dstG, dstB, and dstA represent the incoming R, G, B, A
components of the incoming source and already present destination pixels in the SFMem buffer (blended results of
background and slot[0] through to slot[n-1] for input slot[n]).
outputR = (srcFactC * srcR) + (dstFactC * dstR)
outputG = (srcFactC * srcG) + (dstFactC * dstG)
outputB = (srcFactC * srcB) + (dstFactC * dstB)
outputA = (srcFactA * srcA) + (dstFactA * dstA)
If the ColorKeySelect is set to DISABLED, then srcFactC, srcFactA, dstFactC, and dstFactA will be programmed by
srcFactCMatchSelect, srcFactCMatchSelect, srcFactCMatchSelect, and srcFactCMatchSelect, respectively.
If the ColorKeySelect is set to ENABLED, then srcFactC, srcFactA, dstFactC, and dstFactA are programmed by
srcFactCMatchSelect, srcFactCMatchSelect, srcFactCMatchSelect, and srcFactCMatchSelect, respectively, if the destination
color key match result returns true, and programmed by srcFactCNoMatchSelect, srcFactCNoMatchSelect,
srcFactCNoMatchSelect, and srcFactCNoMatchSelect, respectively, if the destination color key match result returns false.
UseK3 allows the incoming source components to be overrided by constant color components K3R, K3G, K3B, K3A.

MaskR, MaskG, MaskB, and MaskA Boolean settings provide additional per-component mask bits to allow pass-through of the
destination pixel components to the output pixel
There is no post-blend color space conversion available. As a result, blending should be done in the destination color space.
If the destination color space is RGB, all input slots should be converted to RGB color space before blending.
A programmable background color will still be set to fill the target rectangle background via the Blending0Struct, as in VIC1.0.
13.3.14 Subpixel Source Rectangles

Source rectangles can be specified to a sub-pixel resolution. This feature can be used to smoothly zoom into a portion of an
image in real-time, for example, when using the zoom button on a camera. Specifying source and destination rectangles to a
pixel resolution quantizes the allowed zoom factor, and hence can cause the zoom to feel jerky. Allowing the source
rectangles to be specified to a sub-pixel resolution avoids this problem and makes the zoom smooth.
The config structure is therefore modified to make the source rectangle coordinates U14.16 numbers. Once we have the
(decimal) source rectangles, we can calculate adjust the starting phase of the scaling filters accordingly so as to achieve the
sub-pixel shift/scale required.
Note that all source coordinates (left, top, right, bottom) include the bounding pixels. For instance: (0,0)-(0,0) contains 1 pixel,
while (0,0)-(1-1) contains a square of 2x2 pixels. This means that rectangles which are less than 1 pixel wide or tall cannot be
used. Also, specifying a rectangle of (0.0,0.0)-(0.0,0.1) results in a source rectangle that is 1 pixel wide and 1.1 pixel high,
which is not immediately apparent.
13.3.15 Maximum Surface and Rectangle Size Support

The VIC supports surface and rectangle sizes up to 16384x16384 pixels.
This size affects all input and output surfaces parameters as well as all fetch calculations related to these parameters:
 Per-input slot and output surface width/height, luma width/height, chroma width/height
 Per-input slot source and destination rectangle dimensions
 Clear rectangle dimensions
 Output target rectangle dimensions
13.4 Programming Guidelines
13.4.1 Class Operation

The operation of this class can be summarized as follows:
1. The driver should set up input and output context DMAs as specified here.
2. After setting up the surfaces, the driver should send the parameter methods which specify:
- Control Configuration
- Configuration structure offset
- Palette buffer offset
- History buffer offset
- Input/Output/Intermediate surface offsets
- Context ID methods
- Fetch Control Engine (FCE) microcode offset
3. When Execute() method is sent, the Falcon program will be initiated.
The compositor operation requires the following buffers. These buffers are explained in more detail in the following sections.

Buffers I/O Producer Description/Restrictions
Config Buffer I Driver Configuration parameters
Palette Buffer I Driver Palette table
History Buffer I/O App Histogram and Cadence parameters
Input surfaces I Driver/VIC Input Surfaces
Noise reduced surfaces I/O VIC Noise reduced version of input
Motion map surfaces I/O VIC Motion map of input
FCE Microcode buffer I Driver FCE microcode
13.4.1.1 Restrictions
 Maximum slots (MAX_SLOTS) supported are 5.
 Maximum downscale ratio is 16:1.
 When enabling panoramic scaling, the maximum downscale ratio is 7:1. In addition, the minimum destination
rectangle size is 4x4 pixels.
 Minimum source rectangle size is 4 pixels x 4 pixels.
 The only pixel formats supported in video pre-process operations (IVTC, TNR, DiSi1 deinterlacing) are NV12, YV12,
YUY2, and UYVY.
13.4.2 Application Memory Structures
13.4.2.1 Enumerates and Constants

Below are the enumerators used in the configuration structures passed by the driver:
 DXVAHD_FRAME_FORMAT
 PIXEL_FORMAT
 DXVAHD_DEINTERLACE_MODE_PRIVATE
 DXVAHD_ALPHA_FILL_MODE
 BLK_KIND
 BLEND_SRCFACTC
 BLEND_DSTFACTC
 BLEND_SRCFACTA
 BLEND_DSTFACTA
13.4.3 Config Structure

The Config structure is read from the frame buffer by the surface cache unit and is stored in small memories inside each
subunit. The entire ConfigStruct is the concatenation of the Surface Cache, Surface List, Color Conversion, Blending and
Fetch Control structs (in this order). The structs are read in 128-bit units from memory and sent to the according subunits
memory with the correct memory address by the Surface Cache.
The config structure is broken up into smaller structs that are used depending on the active slots and their content. Each
structure is a multiple of 128 bits in size, and the start of the struct needs to be aligned to a 256 byte boundary.
Note: NV12 and NV24 share the same pixel format but can be distinguished by the fact that NV24 is a field based format (i.e.,
every surface contains a single field) whereas NV12 is frame based (i.e., every surface contains an entire frame).
Note: For highest quality, filter override mode as defined in FetchControlCoeffStruct should always be used.

The following table defines the smaller structs that comprise ConfigStruct.
Table 41: ConfigStruct Substructures
Name Data Type Offset Notes
surfaceCache0Struct SurfaceCache0Struct (128 bits) 0
surfaceList0Struct SurfaceList0Struct (128 bits) 128
surfaceListClearRectStruct[4] SurfaceListClearRectStruct (128 bits) 256 + (i * 128) Up to eight clear

rectangles supported.
Each
SurfaceListClearRectStruct
specifies two rectangles
surfaceListSurfaceStruct[5] SurfaceListSurfaceStruct (384 bits) 768 + (i * 384)
colorConversionLumaAlphaStruct[5] ColorConversionLumaAlphaStruct (128 bits) 2688 + (i * 128)
colorConversionMatrixStruct[5] ColorConversionMatrixStruct (256 bits) 3328 + (i * 256) Conversion matrix for

brightness, hue and
saturation values
colorConversionClampStruct[5] ColorConversionClampStruct (128 bits) 4608 + (i * 128)
blending0Struct Blending0Struct (256 bits) 5248
blendingSurfaceStruct[5] BlendingSurfaceStruct (128 bits) 5504 + (i * 128)
fetchControl0Struct FetchControl0Struct (512 bits) 6144
fetchControlCoeffStruct[520] FetchControlCoeffStruct (128 bits) 6656 + (i * 128) 520 coefficient structs
13.4.3.1 SurfaceCache0Struct
This structure contains enable bits for each slot, which need to be set as described below.
 Noise reduction requires a forward and a backward reference field for interlaced content and a backward reference
for progressive content (see the “Method Naming and Programming” section about how to set surfaces). Both require
a noise reduced surface (field for interlaced, frame for progressive).
 MotionMap calculation is required for DiSi1/DiNewBob and also needs a forward and a backward reference. Behavior
is not defined for progressive streams so enabling it needs to be flagged as an error.
 Cadence Detection enables artifact and weave counts. It also enables Falcon code to force deinterlace mode to
weave if a cadence was detected.
Table 42: SurfaceCache0Struct Details
DeNoise0 fixed<0,1,0> (1 bit) 0 Enable bit for noise reduction
CadenceDetect0 fixed<0,1,0> (1 bit) 1 Cadence detection enable bit
MotionMap0 fixed<0,1,0> (1 bit) 2 Motion map enable bit for each slot. Required for DiSi1/DiNewBob
MedianFilter0 fixed<0,1,0> (1 bit) 3 Do not enable Median filtering
DeNoise1 fixed<0,1,0> (1 bit) 4

CadenceDetect1 fixed<0,1,0> (1 bit) 5
MotionMap1 fixed<0,1,0> (1 bit) 6
MedianFilter1 fixed<0,1,0> (1 bit) 7
IsEven0 fixed<0,1,0> (1 bit) 20 Select if current field is even (used for cadence detection)
IsEven1 fixed<0,1,0> (1 bit) 21
MMapCombine0 fixed<0,1,0> (1 bit) 25 Enable bit for combine motion map for each slot. This is required for
DiSi1/DiNewBob. This requires MotionMap being enabled and also
required a prevMotionMap surface (see “Method Naming and
Programming”). Behavior without MotionMap enabled is undefined and
has to be flagged as an error.
MMapCombine1 fixed<0,1,0> (1 bit) 26
reserved0 fixed<0,2,0> (2 bits) 30
PixelFormat0 fixed<0,7,0> (7 bits) 32 Pixel format for each stream (PIXEL_FORMAT)

Only NV12, YUY2 and UYVY allow for motion buffer calculation and
DiSi1/DiNewBob deinterlacing and noise reduction.
reserved1 fixed<0,1,0> (1 bit) 39

PixelFormat1 fixed<0,7,0> (7 bits) 40
PPMotion0 fixed<0,1,0> (1 bit) 96 Enable bit for previous motion calculation for each slot. PPMotion is
obsolete and should not be enabled.
PPMotion1 fixed<0,1,0> (1 bit) 97
ChromaEven0 fixed<0,1,0> (1 bit) 104 Enable if chroma of current field is even
ChromaEven1 fixed<0,1,0> (1 bit) 105
AdvancedDenoise0 fixed<0,1,0> (1 bit) 112 Enable the advanced denoising algorithm (TNR2) for each slot.
AdvancedDenoise1 fixed<0,1,0> (1 bit) 113

13.4.3.2 SurfaceList0Struct
The per-slot clear rectangle masks enable or disable each of the 8 clear rectangles defined in the SurfaceListClearRectStruct
for that slot. This structure also specifies the output flip enables and Target rectangle.
Table 43: SurfaceList0Struct Details
ClearRectMask0 fixed<0,8,0> (8 bits) 0 Clear rectangle mask for slot 0
OutputFlipX fixed<0,1,0> (1 bit) 62 Flip output image horizontally
OutputFlipY fixed<0,1,0> (1 bit) 63 Flip output image vertically
TargetRectLeft fixed<0,14,0> (14 bits) 64 Target rectangle. Restricts the output to a certain rectangle inside the
output surface. Pixels outside of this area are guaranteed to remain
unmodified.
TargetRectRight fixed<0,14,0> (14 bits) 80
TargetRectTop fixed<0,14,0> (14 bits) 96
TargetRectBottom fixed<0,14,0> (14 bits) 112
13.4.3.3 SurfaceListClearRectStruct[4]
The SurfaceListClearRectStruct structures together define 8 clear rectangles. These rectangles are enabled or disabled for
each slot using the fields in SurfaceList0Struct.
Table 44: SurfaceListClearRectStruct[4] Details
ClearRect0Left fixed<0,14,0> (14 bits) 0 First clear rectangle of 128-bit chunk
ClearRect0Right fixed<0,14,0> (14 bits) 16

ClearRect0Top fixed<0,14,0> (14 bits) 32
ClearRect0Bottom fixed<0,14,0> (14 bits) 48
ClearRect1Left fixed<0,14,0> (14 bits) 64 Second clear rectangle of 128-bit chunk
ClearRect1Right fixed<0,14,0> (14 bits) 80
ClearRect1Top fixed<0,14,0> (14 bits) 96
ClearRect1Bottom fixed<0,14,0> (14 bits) 112
13.4.3.4 SurfaceListSurfaceStruct[5]
Surface parameters for each slot.
Table 45: SurfaceListSurfaceStruct[5] Details
Enable fixed<0,1,0> (1 bit) 0 Enable or disable bit for this slot
FrameFormat fixed<0,4,0> (4 bits) 1 Frame format of the frame (DXVAHD_FRAME_FORMAT)
PixelFormat fixed<0,7,0> (7 bits) 5 Pixel format for each stream (PIXEL_FORMAT)
ChromaLocHoriz fixed<0,2,0> (2 bits) 14 Horizontal chroma location

0: Co-located with even luma
1: In between even and odd luma
2: Co-located with odd luma
3: Between odd and next even luma
ChromaLocVert fixed<0,2,0> (2 bits) 16 Vertical chroma location

0: Co-located with even luma
1: In between even and odd luma
2: Co-located with odd luma
3: Between odd and next even luma
Panoramic fixed<0,12,0> (12 bits) 18 Panoramic scaling parameter. For details on this parameter, refer to
the Panoramic Scaling subsection.
SurfaceWidth fixed<0,14,0> (14 bits) 34 Width of surface minus 1. Any pixel data outside of this will not be
used inside the VIC but might still be read.

SurfaceHeight fixed<0,14,0> (14 bits) 49 Height of surface minus 1. Any pixel data outside of this will not be
used inside the VIC but might still be read.
LumaWidth fixed<0,14,0> (14 bits) 64 Padded luma width of surface minus 1. Any pixel data outside of this
will not be read.
LumaHeight fixed<0,14,0> (14 bits) 79 Padded luma height of surface minus 1. Any pixel data outside of this
will not be read.
ChromaWidth fixed<0,14,0> (14 bits) 94 Padded chroma width of surface minus 1. Any pixel data outside of
this will not be read. This value is not required for pixel interleaved
surfaces such as ARGB.
ChromaHeight fixed<0,14,0> (14 bits) 109 Padded chroma height of surface minus 1. Any pixel data outside of
this will not be read. This value is not required for pixel interleaved
surfaces such as ARGB
CacheWidth fixed<0,3,0> (3 bits) 124 Number of horizontal bytes per surface-cache cache-line. Each 256B
cache line can store a source region of size as enumerated below.
0: 16Bx16 (BL16Bx2)
1: 32Bx8 (BL16Bx2)
2: 64Bx4 (BL16Bx2, PL)
3: 128Bx2 (BL16Bx2, PL)
4: 256Bx1 (PL)
FilterLengthY fixed<0,2,0> (2 bits) 128 Filter length for each stream:

0: 1-tap (nearest neighbor)
1: 2-tap (bi-linear)
2: 5-tap
3: 10-tap
FilterLengthX fixed<0,2,0> (2 bits) 130
DetailFltClamp fixed<0,6,0> (6 bits) 132
LightLevel fixed<0,4,0> (4 bits) 140 Describes the level of lighting present when the input image was
captured. This parameter is used along with the AdvancedDenoise
bits to determine the exact denoising algorithm to be applied for noise
reduction.
BlkKind fixed<0,4,0> (4 bits) 188 Block-linear kind (BLK_KIND)

DestRectLeft fixed<0,14,0> (14 bits) 192 The destination rectangle defines the region of the output surface that
is affected by this slot. Together with the source rectangle it also
defines the scaling rations. Any pixel outside of this region will not be
affected by this input stream. For any non-4:4:4 format, all corners
need to fall on a multiple of 2 (Right and Bottom are minus 1 encoded
though).
DestRectRight fixed<0,14,0> (14 bits) 207
DestRectTop fixed<0,14,0> (14 bits) 222
DestRectBottom fixed<0,14,0> (14 bits) 237
BlkHeight fixed<0,4,0> (4 bits) 252 Block-linear height (in gobs, log2)
SourceRectLeft fixed<0,30,0> (30 bits) 256 The source rectangle defines the region of pixels that will be read from
the source surface. Any pixel data outside of this will not be used
inside the VIC but might still be read. The source rectangle
coordinates are specified in a U14.16 format, allowing fractional
coordinates to be specified. The source rectangle should lie entirely
within the input surface for the slot; that is, negative values, or values
greater than the size of the surface, are illegal.
SourceRectRight fixed<0,30,0> (30 bits) 288
SourceRectTop fixed<0,30,0> (30 bits) 320
SourceRectBottom fixed<0,30,0> (30 bits) 352
13.4.3.5 ColorConversionLumaAlphaStruct[5]
Enables luma keying and plane alpha parameters.
Table 46: ColorConversionLumaAlphaStruct[5] Details
l0 fixed<0,20,0> (20 bits) 0 Matrix entry (0) of 4x1 luma conversion matrix in S12.8
format
format
format

r_shift fixed<0,4,0> (4 bits) 60 The result of the matrix multiplication is right shifted by
r_shift. To allow for highest accuracy r_shift should always
be as high as possible without losing any range in the other
coefficients.
format. Is not affected by r_shift.
PlanarAlpha fixed<0,10,0> (10 bits) 84 10-bit planar alpha value. This planar alpha is multiplied
with the alpha value coming from the stream. In case of
palettized alpha formats (like AI44/A8P8/AI88), the stream
alpha value is the alpha value from the surface multiplied
with the alpha value from the palette.
ConstantAlpha fixed<0,1,0> (1 bit) 94 If true planar alpha value is used instead of stream alpha, if
false, stream alpha is multiplied with planar alpha. Constant
alpha has to be set for all surfaces not containing any alpha
data (like XRGB/NV12/YUY2/UYVY/YV12).
ClipEnabled fixed<0,1,0> (1 bit) 95 Enables clip against negative values after gamut matrix
LumaKeyLower fixed<0,10,0> (10 bits) 96 Lower luma key value
StereoInterleave fixed<0,3,0> (3 bits) 109 Enables pixel interleave for auto-stereoscopic panels
(STEREO_INTERLEAVE)
LumaKeyUpper fixed<0,10,0> (10 bits) 112 Upper luma key value
LumaKeyEnabled fixed<0,1,0> (1 bit) 125 Luma key enable
13.4.3.6 ColorConversionMatrixStruct[5]
The matrices defined in these structures specify the color space conversion between input and output pixel formats, if any.
Table 47: ColorConversionMatrixStruct[5] Details
c00 fixed<0,20,0> (20 bits) 0 Matrix entry (0,0) of 4x3 color conversion matrix. Precision and right
shift are the same as for the luma vector.
c10 fixed<0,20,0> (20 bits) 20 Matrix entry (1,0) of 4x3 color conversion matrix
r_shift fixed<0,4,0> (4 bits) 60 Right shift value for matrix

13.4.3.7 ColorConversionClampStruct[5]
Specifies the upper and lower clamp boundaries for pixels after the matrix multiplication.
Table 48: ColorConversionClampStruct[5] Details
Name Data Type Offset
low fixed<0,10,0> (10 bits) 0 Lower soft clamping boundaries
high fixed<0,10,0> (10 bits) 16 Upper soft clamping boundaries
13.4.3.8 Blending0Struct
Specifies parameters related to the alpha-blending of the different slots and the output surface/rectangle parameters.
Table 49: Blending0Struct Details
PixelFormat fixed<0,7,0> (7 bits) 0 Pixel format of the output surface (PIXEL_FORMAT)
AlphaFillMode fixed<0,3,0> (3 bits) 8 Alpha fill mode (DXVAHD_ALPHA_FILL_MODE)
AlphaFillSlot fixed<0,3,0> (3 bits) 11 SlotId for when AlphaFillMode == Source stream/Source

alpha
BackgroundAlpha fixed<0,10,0> (10 bits) 14 Background color A

BackgroundR fixed<0,10,0> (10 bits) 24 Background color R
BackgroundG fixed<0,10,0> (10 bits) 34 Background color G
BackgroundB fixed<0,10,0> (10 bits) 44 Background color B
ChromaLocHoriz fixed<0,2,0> (2 bits) 54 Chroma location of the output surface (see

SurfaceListSurfaceStruct)
ChromaLocVert fixed<0,2,0> (2 bits) 56
LumaWidth fixed<0,14,0> (14 bits) 64 Padded output surface luma width minus 1
LumaHeight fixed<0,14,0> (14 bits) 80 Padded output surface luma height minus 1
ChromaWidth fixed<0,14,0> (14 bits) 96 Padded output surface chroma width minus 1
ChromaHeight fixed<0,14,0> (14 bits) 112 Padded output surface chroma height minus 1
TargetRectLeft fixed<0,14,0> (14 bits) 128 Target rectangle, restricts the output of pixels to this region.
For any non-4:4:4 format, all corners need to fall on a
multiple of 2 (Right and Bottom are minus 1 encoded
though).
SurfaceWidth fixed<0,14,0> (14 bits) 192 Output surface width minus 1
SurfaceHeight fixed<0,14,0> (14 bits) 208 Output surface height minus 1
BlkKind fixed<0,4,0> (4 bits) 224 The block linear kind of the output surface (BLK_KIND)
BlkHeight fixed<0,4,0> (4 bits) 228 Block-linear height (in gobs, log2)
OutputFlipX fixed<0,1,0> (1 bit) 232 Horizontal Flip enable

OutputFlipY fixed<0,1,0> (1 bit) 233 Vertical Flip enable
OutputTranspose fixed<0,1,0> (1 bit) 234 Transpose enable
13.4.3.9 BlendingSurfaceStruct[5]
Input parameters to blend equations in DXVAHD_ALPHA_FILL_MODE_COMPOSITED alpha fill mode
 outputR = (srcFactC * srcR) + (dstFactC * dstR)

 outputG = (srcFactC * srcG) + (dstFactC * dstG)
 outputB = (srcFactC * srcB) + (dstFactC * dstB)
 outputA = (srcFactA * srcA) + (dstFactA * dstA)
Table 50: BlendingSurfaceStruct[5] Details
AlphaK1 fixed<0,10,0> (10 bits) 0 Constant Alpha value
reserved0 fixed<0,6,0> (6 bits) 10 Constant Alpha value
AlphaK2 fixed<0,10,0> (10 bits) 16 Constant Alpha value
SrcFactCMatchSelect fixed<0,3,0> (3 bits) 32 Blend Source Factor for Color if the color key
comparison matches (BLEND_SRCFACTC)
DstFactCMatchSelect fixed<0,3,0> (3 bits) 36 Blend Destination Factor for Color if the color key
comparison matches (BLEND_DSTFACTC)
SrcFactAMatchSelect fixed<0,3,0> (3 bits) 40 Blend Source Factor for Alpha if the color key
comparison matches (BLEND_SRCFACTA)
DstFactAMatchSelect fixed<0,3,0> (3 bits) 44 Blend Source Factor for Alpha if the color key
comparison matches (BLEND_DSTFACTA)
OverrideR fixed<0,10,0> (10 bits) 66 Source RGBA override values

OverrideG fixed<0,10,0> (10 bits) 76
OverrideB fixed<0,10,0> (10 bits) 86
OverrideA fixed<0,10,0> (10 bits) 96
UseOverrideR fixed<0,1,0> (1 bit) 108 Enable source RGBA value override
UseOverrideG fixed<0,1,0> (1 bit) 109
UseOverrideB fixed<0,1,0> (1 bit) 110
UseOverrideA fixed<0,1,0> (1 bit) 111
MaskR fixed<0,1,0> (1 bit) 112 Per-component blend output override enables (replace
blend output with destination RGBA values)
MaskG fixed<0,1,0> (1 bit) 113
MaskB fixed<0,1,0> (1 bit) 114
MaskA fixed<0,1,0> (1 bit) 115
13.4.3.10 FetchControl0Struct
Specifies various parameters related to scaling and filtering. Also specifies which input surfaces are enabled and the
processing required for each slot.
Table 51: FetchControl0Struct Details
TargetRectLeft fixed<0,14,0> (14 bits) 0 Target rectangle, restricts the output of pixels to this region
Enable0 fixed<0,8,0> (8 bits) 64 Indicates which surfaces are enabled for fetching:
Bit 0: Current field
Bit 1: Previous field
Bit 2: Next field
Bit 3: Next field (noise filtered, takes priority over unfiltered
field)
Bit 4: Current motion field


Bit 5: Previous motion field
Bit 6: Previous previous motion field
Bit 7: Combined motion field
Enable1 fixed<0,8,0> (8 bits) 72
DownsampleHoriz fixed<0,11,0> (11 bits) 104 TargetWidth/DownsampleWidth (U9.2 used to lob bias filter).
Set to 0 to enable filter override mode (mapping between
stream and filter is explained in “Scaling and Filtering”)
DownsampleVert fixed<0,11,0> (11 bits) 116 TargetHeight/DownsampleHeight (U9.2 used to lob bias
filter). Set to 0 to enable filter override mode (mapping
between stream and filter is explained in “Scaling and
Filtering”)
FilterNoise0 fixed<0,10,0> (10 bits) 128 Strength of the spatial noise filter for slot 0. All detail and
noise filter values (including chroma) become meaningless
and should be set to 0 as soon as filter override is enabled
FilterDetail0 fixed<0,10,0> (10 bits) 138 Strength of the detail filter for slot 0
FilterNoise1 fixed<0,10,0> (10 bits) 148 Strength of the noise filter for slot 1
ChromaNoise0 fixed<0,10,0> (10 bits) 256 Strength of the noise filter for slot 0
ChromaDetail0 fixed<0,10,0> (10 bits) 266 Strength of the detail filter for slot 0

Mode0 fixed<0,4,0> (4 bits) 384 Deinterlace mode

(DXVAHD_DEINTERLACE_MODE_PRIVATE)
AccumWeight0 fixed<0,3,0> (3 bits) 388 Accumulation weight for motion IIR filter for slot 0 (the default
is 6). The first time an even/odd motion field is calculated,
AccumWeight should be set to 0 to avoid having to clear the
motion buffer beforehand.
Iir0 fixed<0,11,0> (11 bits) 391 Accumulation weight for noise reduction IIR filter for slot 0
(default value is 0x300).
Mode1 fixed<0,4,0> (4 bits) 404
AccumWeight1 fixed<0,3,0> (3 bits) 408
Iir1 fixed<0,11,0> (11 bits) 411
Iir2 fixed<0,11,0> (11 bits) 431
Iir3 fixed<0,11,0> (11 bits) 455

Iir4 fixed<0,11,0> (11 bits) 475
OutputFlipX fixed<0,1,0> (1 bit) 494 Flip output image horizontally
OutputFlipY fixed<0,1,0> (1 bit) 495 Flip output image vertically
13.4.3.11 FetchControlCoeffStruct[520]
Specifies the coefficients used in the scalars for scaling/edge-enhancement/noise filtering. These coefficients are interpolated
in the hardware to get the exact coefficients needed for the use case.
Table 52: FetchControlCoeffStruct[520] Details
Name Data Type Offset
f00 fixed<0,10,0> (10 bits) 0 First coefficient of noise filter for 128-bit packet
f10 fixed<0,10,0> (10 bits) 10 First coefficient of normal scaling filter in 128-bit packet
f20 fixed<0,10,0> (10 bits) 20 First coefficient of detail filter in 128-bit packet
f01 fixed<0,10,0> (10 bits) 32 Second coefficient of noise filter in 128-bit packet
f11 fixed<0,10,0> (10 bits) 42 Second coefficient of normal scaling filter in 128-bit packet
f21 fixed<0,10,0> (10 bits) 52 Second coefficient of detail filter in 128-bit packet
f02 fixed<0,10,0> (10 bits) 64 Third coefficient of noise filter in 128-bit packet
f12 fixed<0,10,0> (10 bits) 74 Third coefficient of normal scaling filter in 128-bit packet
f22 fixed<0,10,0> (10 bits) 84 Third coefficient of detail filter in 128-bit packet
f03 fixed<0,10,0> (10 bits) 96 Fourth coefficient of noise filter in 128-bit packet
f13 fixed<0,10,0> (10 bits) 106 Fourth coefficient of normal scaling filter in 128-bit packet
f23 fixed<0,10,0> (10 bits) 116 Fourth coefficient of detail filter in 128-bit packet

13.4.4 Palette Structure

PaletteStruct sends palette information for indexed formats. Each slot has its own space in the palette buffer even if the format
is not indexed. For non-indexed formats the space should left blank and should not be used by any other slots to send palette
data. The number of palette entries for each slot can be at most 256.
13.4.5 History Buffer

The History buffer is used to store inter-frame communication data. It has two parts. The first part of the structure holds
cadence-related information, and the second part stores histogram data for each slot.
The first Dword of the hist_control (control_vector) should be set by the driver. It informs Falcon whether to calculate the
cadence.
13.4.6 FCE Microcode Buffer

This buffer holds the Fetch Control Engine (FCE) microcode that Falcon should load to the FCE unit. The driver should also
pass the size of the FCE microcode with the SetFceUcodeSize() method.
13.4.7 Input Picture Buffers

Each picture is a separate buffer with its own surface offset method. The driver needs to send these offset methods for only
the used pictures (source and reference) for the current execute.
13.4.8 Noise Reduced Picture Buffers

This buffer is used by the app to keep a noise-reduced picture data of future fields if DeNoise is enabled. In the next execute,
noise-reduced picture data is used as the current field, and noise-reduced picture data of the previous execute will be used as
previous picture. Noise reduction requires a forward and a backward reference field for interlaced content and a backward
reference for progressive content.
In the NV24 case, the VIC app uses an additional surface to keep noise reduced field of the current picture. In this case, the
current noise reduced surfaces are used as previous reference surfaces.
Noise-reduced picture buffer dimensions for a slot should be same as input buffer of that slot.
13.4.9 Motion Map Buffers

These buffers keep motion map data of the current and previous fields if MotionMap is enabled. The previous motion map
buffer should be initialized to 255 (both luma and chroma) at the start of the clip. Use the motion map buffer of the previous
execute pass prev motion map in the current execute for subsequent frames. MotionMap calculation is required for DiSi1 and
also needs a forward and a backward reference. Behavior is not defined for progressive streams.
Motion map buffer dimensions for a slot should be same as input buffer of that slot.
13.4.10 Output Buffer

This buffer stores output data.
13.4.11 Method Naming and Programming

The VIC uses generic names to avoid confusing name overloading to the 16 surfaces (8 luma, 8 chroma) methods for the
MAX_SLOTS
 SetSurfacexSlotyLumaOffset()
 SetSurfacexSlotyChromaOffset()
with x in [0..7] and y in [0..MAX_SLOTS]

The following sets of methods are required for a given ConfigStruct setup. Any setup not covered in this section should be
regarded as illegal.
Note:
 NV24 frames are treated as NV12 fields. The frame format for NV24 has to be set to
FRAME_FORMAT_TOP_FIELD.
 In case of noise reduction all previously noise reduced surfaces should be used as references instead of the original
ones. In case of interlaced fields this also applies to the current fields as they have previously been noise reduced.
 Surface6 has been obsoleted and should not be used.
 History buffer is always required and should be owned by Falcon.
13.4.11.1 Progressive Frames
No Preprocessing
Enable bits have to be set to 0x01 in fetchControl0Struct.
Required methods for all pixel formats:
 SetSurface0SlotLumaOffset()
Required methods for pixel formats with separate chroma plane:
 SetSurface0SlotChromaOffset()
Noise Reduction
 SetSurface1SlotLumaOffset() (backward reference surface)
 SetSurface2SlotLumaOffset() (noise reduced surface)
 SetSurface1SlotChromaOffset() (backward reference surface)
 SetSurface2SlotChromaOffset() (noise reduced surface)
13.4.11.2 Progressive Fields
No Preprocessing
 SetSurface0SlotLumaOffset() (top field)

 SetSurface1SlotLumaOffset() (bottom field)
 SetSurface0SlotChromaOffset() (top field)

 SetSurface1SlotChromaOffset() (bottom field)

Noise Reduction
Enable bits have to be set to 0x03f in fetchControl0Struct.
 SetSurface0SlotLumaOffset() (top field)

 SetSurface1SlotLumaOffset() (bottom field)
 SetSurface2SlotLumaOffset() (top field of backward reference surface)
 SetSurface3SlotLumaOffset() (bottom field of backward reference surface)
 SetSurface4SlotLumaOffset() (top field of noise reduced surface)
 SetSurface5SlotLumaOffset() (bottom field of noise reduced surface)
 SetSurface0SlotChromaOffset() (top field)

 SetSurface1SlotChromaOffset() (bottom field)
 SetSurface2SlotChromaOffset() (top field of backward reference surface)
 SetSurface3SlotChromaOffset() (bottom field of backward reference surface)
 SetSurface4SlotChromaOffset() (top field of noise reduced surface)
 SetSurface5SlotChromaOffset() (bottom field of noise reduced surface)
13.4.11.3 Interlaced Frames
No Preprocessing
Noise Reduction
 SetSurface1SlotLumaOffset() (backward reference surface)
 SetSurface2SlotLumaOffset() (noise reduced surface)
 SetSurface1SlotChromaOffset() (backward reference surface)
 SetSurface2SlotChromaOffset() (noise reduced surface)

13.4.11.4 Interlaced Fields
No Preprocessing
This is for BOB_FIELD only. For WEAVE, see “No Preprocessing” under “Progressive Fields“.
Cadence Detection
Enable bits have to be set to 0x07 in fetchControl0Struct. This also requires cadence detection to be enabled.
 SetSurface1SlotLumaOffset() (backward reference field)
 SetSurface2SlotLumaOffset() (forward reference field)
 SetSurface1SlotChromaOffset() (backward reference field)
 SetSurface2SlotChromaOffset() (forward reference field)
Motion Calculation
Enable bits have to be set to 0x17 in fetchControl0Struct. The data in the current motion field is read first and IIR filtered with
the newly calculated motion before it is written back.
 SetSurface4SlotLumaOffset() (current motion field)
 SetSurface4SlotChromaOffset() (current motion field)
Motion Calculation and Cadence Detection

Same as above in Motion Calculation except that cadence detection is enabled.

DISI1 (Motion Calculation and Motion Combine)

Enable bits have to be set to 0xb7 in fetchControl0Struct. The data in the current motion field is read first and IIR filtered with
the newly calculated motion before it is written back. The combined motion field is generated out of current motion and
previous motion to be used in DiSi1 deinterlacer.
 SetSurface5SlotLumaOffset() (previous motion field)
 SetSurface7SlotLumaOffset() (combined motion field)
 SetSurface5SlotChromaOffset() (previous motion field)
 SetSurface7SlotChromaOffset() (combined motion field)
DISI1 (Motion Calculation and Motion Combine) and Cadence Detection

Same as above in DiSi1 except that cadence detection is enabled.
Noise Reduction
Enable bits have to be set to 0x0f in fetchControl0Struct.
 SetSurface1SlotLumaOffset() (previously noise reduced backward reference field)
 SetSurface3SlotLumaOffset() (noise reduced forward reference field)
 SetSurface1SlotChromaOffset() (previously noise reduced backward reference field)
 SetSurface3SlotChromaOffset() (noise reduced forward reference field)
Noise Reduction and Cadence Detection

Same as above in Noise Reduction except that cadence detection is enabled.
Noise Reduction and Motion Calculation

Enable bits have to be set to 0x1f in fetchControl0Struct. The data in the current motion field is read first and IIR filtered with
the newly calculated motion before it is written back.
Noise Reduction and Motion Calculation and Cadence Detection

Same as above in Noise Reduction and Motion Calculation except that cadence detection is enabled.
Noise Reduction and DISI1 (Motion Calculation and Motion Combine)

Enable bits have to be set to 0xbf in fetchControl0Struct. The data in the current motion field is read first and IIR filtered with
the newly calculated motion before it is written back. The combined motion field is generated out of current motion and
previous motion to be used in DiSi1 deinterlacer.
 SetSurface5SlotLumaOffset() (previous motion field)
 SetSurface7SlotLumaOffset() (combined motion field)
 SetSurface5SlotChromaOffset() (previous motion field)
 SetSurface7SlotChromaOffset() (combined motion field)
Noise Reduction and DISI1 (Motion Calculation and Motion Combine) and Cadence Detection
Same as above in Noise Reduction and DiSi1 except that cadence detection is enabled.

13.4.12 Application ID
Application ID is not needed as there is only one application for the engine (unlike different codecs for the MSDEC). But to use
it with MSDEC infrastructure, the driver needs to pass the ApplicationId as 1 (corresponding to overlay 1).
13.4.13 Application-Specific Error Codes

The following table defines the error codes.
Table 53: Error Codes
Error Code Value Description
MSDECOS_ERROR_NONE 0x00000000 Default return code for app
MSDECOS_ERROR_EXECUTE_INSUFFICIENT_DATA 0x00000001 To be returned by the app to the OS
Insufficient semaphore methods

received. Method Data written out into
MAILBOX1.
MSDECOS_ERROR_SEMAPHORE_INSUFFICIENT_DATA 0x00000002
MAILBOX0 bits 31:20- Method ID.
MAILBOX0 bits 19-12: Method Count
(SWFIFO + MTHDCOUNT register)
MSDECOS_ERROR_INVALID_METHOD 0x00000003 Unsupported method
MSDECOS_ERROR_INVALID_DMA_PAGE 0x00000004 Unsupported method
The app has either no interrupt handler

MSDECOS_ERROR_UNHANDLED_INTERRUPT 0x00000005
or an unhandled OS error
MSDECOS_ERROR_EXCEPTION 0x00000006 Exception raised by Falcon
MSDECOS_ERROR_INVALID_CTXSW_REQUEST 0x00000007 Invalid CTXSW request to the OS
Application returned a nonzero error

MSDECOS_ERROR_APPLICATION 0x00000008
code
Exception raised to dump registers in

MSDECOS_ERROR_SWBREAKPT 0x00000009
debug mode
13.4.14 Application Method Registers

The VIC application method registers are accessed directly by the driver. Because the VIC uses the MSDEC infrastructure,
two ranges of methods are used (in the MSDEC, there are common and application specific ranges). The range of method
registers is:
 0x700-0x73F (common method range) and

 0x400-0x53F (method range corresponding to overlay 1)
The following table defines the method map.
Address Method
0x0100 VIC.Nop
0x0140 VIC.PmTrigger
0x0200 VIC.SetApplicationID
0x0204 VIC.SetWatchdogTimer
0x0240 VIC.SemaphoreA
0x0244 VIC.SemaphoreB
0x0248 VIC.SemaphoreC

Address Method
0x024c VIC.CtxSaveArea
0x0250 VIC.CtxSwitch
0x0300 VIC.Execute
0x0304 VIC.SemaphoreD
0x0400 VIC.SetSurface0Slot0LumaOffset
0x0404 VIC.SetSurface0Slot0ChromaU_Offset
0x0408 VIC.SetSurface0Slot0ChromaV_Offset
0x040c VIC.SetSurface1Slot0LumaOffset
0x041c VIC.SetSurface2Slot0ChromaU_Offset
0x042c VIC.SetSurface3Slot0ChromaV_Offset

Address Method
0x04a0 VIC.SetSurface5Slot1ChromaU_Offset
0x04a4 VIC.SetSurface5Slot1ChromaV_Offset
0x04a8 VIC.SetSurface6Slot1LumaOffset
0x04ac VIC.SetSurface6Slot1ChromaU_Offset
0x04b0 VIC.SetSurface6Slot1ChromaV_Offset
0x04b4 VIC.SetSurface7Slot1LumaOffset
0x04b8 VIC.SetSurface7Slot1ChromaU_Offset
0x04bc VIC.SetSurface7Slot1ChromaV_Offset
0x04c0 VIC.SetSurface0Slot2LumaOffset
0x04c4 VIC.SetSurface0Slot2ChromaU_Offset
0x04c8 VIC.SetSurface0Slot2ChromaV_Offset
0x04cc VIC.SetSurface1Slot2LumaOffset
0x04d0 VIC.SetSurface1Slot2ChromaU_Offset
0x04d4 VIC.SetSurface1Slot2ChromaV_Offset
0x04d8 VIC.SetSurface2Slot2LumaOffset
0x04dc VIC.SetSurface2Slot2ChromaU_Offset
0x04e0 VIC.SetSurface2Slot2ChromaV_Offset
0x04e4 VIC.SetSurface3Slot2LumaOffset
0x04e8 VIC.SetSurface3Slot2ChromaU_Offset
0x04ec VIC.SetSurface3Slot2ChromaV_Offset
0x04f0 VIC.SetSurface4Slot2LumaOffset
0x04f4 VIC.SetSurface4Slot2ChromaU_Offset
0x04f8 VIC.SetSurface4Slot2ChromaV_Offset
0x04fc VIC.SetSurface5Slot2LumaOffset

Address Method
0x05a0 VIC.SetSurface2Slot4ChromaV_Offset
0x05a4 VIC.SetSurface3Slot4LumaOffset
0x05a8 VIC.SetSurface3Slot4ChromaU_Offset
0x05ac VIC.SetSurface3Slot4ChromaV_Offset
0x05b0 VIC.SetSurface4Slot4LumaOffset
0x05b4 VIC.SetSurface4Slot4ChromaU_Offset

Address Method
0x05b8 VIC.SetSurface4Slot4ChromaV_Offset
0x05bc VIC.SetSurface5Slot4LumaOffset
0x05c0 VIC.SetSurface5Slot4ChromaU_Offset
0x05c4 VIC.SetSurface5Slot4ChromaV_Offset
0x05c8 VIC.SetSurface6Slot4LumaOffset
0x05cc VIC.SetSurface6Slot4ChromaU_Offset
0x05d0 VIC.SetSurface6Slot4ChromaV_Offset
0x05d4 VIC.SetSurface7Slot4LumaOffset
0x05d8 VIC.SetSurface7Slot4ChromaU_Offset
0x05dc VIC.SetSurface7Slot4ChromaV_Offset
0x0700 VIC.SetControlParams
0x0704 VIC.SetContextId
0x0708 VIC.SetContextIdForSlot0
0x070c VIC.SetContextIdForSlot1
0x071c VIC.SetFceUcodeSize
0x0720 VIC.SetConfigStructOffset
0x0724 VIC.SetPaletteOffset
0x0728 VIC.SetHistOffset
0x072c VIC.SetFceUcodeOffset
0x0730 VIC.SetOutputSurfaceLumaOffset
0x0734 VIC.SetOutputSurfaceChromaU_Offset
0x0738 VIC.SetOutputSurfaceChromaV_Offset
0x073c VIC.SetPictureIndex
0x1114 VIC.PmTriggerEnd
13.5 VIC THI Registers

13.5.1.1 NV_PVIC_THI_INCR_SYNCPT
Offset: 0x0 │ Read/Write: R/W │ Reset: 0x00000000
31:16 R 0 Reserved
15:8 R/W 0 NV_PVIC_THI_INCR_SYNCPT_COND:

0: COND_IMMEDIATE (default)
1: COND_OP_DONE

7:0 R/W 0 NV_PVIC_THI_INCR_SYNCPT_INDX:

0: INDX_INIT (default)
13.5.1.2 NV_PVIC_THI_INCR_SYNCPT_ERR
31:4 R 0 Reserved
1 RW1C 0 NV_PVIC_THI_INCR_SYNCPT_ERR_COND_STS_OPDONE:
0: COND_STS_OPDONE_INIT (default)
1: COND_STS_OPDONE_CLEAR
0 RW1C 0 NV_PVIC_THI_INCR_SYNCPT_ERR_COND_STS_IMM:
0: COND_STS_IMM_INIT (default)
1: COND_STS_IMM_CLEAR
13.5.1.3 NV_PVIC_THI_CTXSW_INCR_SYNCPT
Offset: 0xc │ Read/Write: R/W │ Reset: 0x00000000
31:8 R 0 Reserved
7:0 R/W 0 NV_PVIC_THI_CTXSW_INCR_SYNCPT_INDX:

0: INDX_INIT (default)
13.5.1.4 NV_PVIC_THI_CTXSW
Offset: 0x20 │ Read/Write: R/W │ Reset: 0x0000F800
31:28 R/W 0 NV_PVIC_THI_CTXSW_NEXT_CHANNEL:

0: NEXT_CHANNEL_INIT (default)
27:26 R 0 Reserved
25:16 R/W 0 NV_PVIC_THI_CTXSW_NEXT_CLASS:

0: NEXT_CLASS_INIT (default)
15:12 R/W Fh NV_PVIC_THI_CTXSW_CURR_CHANNEL:

Fh CURR_CHANNEL_INIT (default)
11 R 1 NV_PVIC_THI_CTXSW_AUTO_ACK:
1: AUTO_ACK_INIT (default)
10 R 0 Reserved
9:0 R/W 0 NV_PVIC_THI_CTXSW_CURR_CLASS:

0: CURR_CLASS_INIT (default)
13.5.1.5 NV_PVIC_THI_CONT_SYNCPT_EOF
31:9 R 0 Reserved
8 R/W 0 NV_PVIC_THI_CONT_SYNCPT_EOF_COND:
0: COND_INIT (default)

7:0 R/W 0 NV_PVIC_THI_CONT_SYNCPT_EOF_INDEX:

0: INDEX_INIT (default)
13.5.1.6 NV_PVIC_THI_METHOD0
There are two method registers METHOD0 and METHOD1
31:12 R 0 Reserved
11:0 R/W 0 NV_PVIC_THI_METHOD0_OFFSET: 0X

0: OFFSET_INIT (default)
13.5.1.7 NV_PVIC_THI_METHOD1
31:0 R/W 0 NV_PVIC_THI_METHOD1_DATA:

0: DATA_INIT (default)
13.5.1.8 NV_PVIC_THI_INT_STATUS
31:1 R 0 Reserved
0 RW1C 0 NV_PVIC_THI_INT_STATUS_FALCON_INT:
0: FALCON_INT_INIT (default)
1: FALCON_INT_CLEAR
13.5.1.9 NV_PVIC_THI_INT_MASK
Offset: 0x7c │ Read/Write: R/W │ Reset: 0x00000001
31:1 R 0 Reserved
0 R/W 1 NV_PVIC_THI_INT_MASK_FALCON_INT:
1: FALCON_INT_INIT (default)
13.6 HOSTIF Miscellaneous Registers

13.6.1 NV_PVIC_FALCON_ITFEN
31:3 R 0 Reserved
2 R/W 0 NV_PVIC_FALCON_ITFEN_PRIV_POSTWR. Indicates whether to use a post write on the main

priv interface. By default, all writes to the Control and Status Bus (CSB) from the main priv
interface are non-posted to support error reporting.
0: PRIV_POSTWR_INIT (default)


0: PRIV_POSTWR_FALSE
1: PRIV_POSTWR_TRUE
1 R/W 0 NV_PVIC_FALCON_ITFEN_MTHDEN. Method interface enable. When set, allows the host to
push methods into the method FIFO
0: MTHDEN_INIT (default)
0: MTHDEN_DISABLE
1: MTHDEN_ENABLE
0 R/W 0 NV_PVIC_FALCON_ITFEN_CTXEN. Context switch interface enable. When set, allows the
context switch state machine to react to incoming context switch requests from the host.
0: CTXEN_INIT (default)
0: CTXEN_DISABLE
1: CTXEN_ENABLE
13.7 Falcon UCTL Registers
13.7.1 NV_PVIC_FALCON_CPUCTL
Offset: 0x1100 │ Read/Write: R/W │ Reset: 0x000000XX
31:6 R 0 Reserved
5 R Unknown NV_PVIC_FALCON_CPUCTL_STOPPED: Indicates whether the CPU is currently in the

stopped state. Falcon exits this state if a 1 is written to the STARTCPU bit or if an interrupt
arrives on one of its 2 inputs and the corresponding IE bit in CSW is set.
1: STOPPED_TRUE
0: STOPPED_FALSE
4 R Unknown NV_PVIC_FALCON_CPUCTL_HALTED: Indicates whether the CPU is currently in the halted

state. Falcon can only exit this state when a 1 is written to the STARTCPU bit.
1: HALTED_TRUE
0: HALTED_FALSE
3 RW1C Unknown NV_PVIC_FALCON_CPUCTL_HRESET: Set to TRUE to apply hard reset. This bit will auto-
clear. Setting it FALSE has no effect.
1: HRESET_TRUE
0: HRESET_FALSE
2 RW1C Unknown NV_PVIC_FALCON_CPUCTL_SRESET: Set to TRUE to apply soft reset. This bit will auto-
clear. Setting it FALSE has no effect.
1: SRESET_TRUE
0: SRESET_FALSE
1 RW1C Unknown NV_PVIC_FALCON_CPUCTL_STARTCPU: Set STARTCPU to TRUE to start CPU execution

while in a HALTED state. If a start request is still pending, setting to FALSE will cancel the start
request. Writing any value has no effect while the CPU is running.
1: STARTCPU_TRUE
0: STARTCPU_FALSE
0 RW1C Unknown NV_PVIC_FALCON_CPUCTL_IINVAL: Set to TRUE to mark all blocks in IMEM except block 0
as INVALID. This bit will auto-clear. Setting to FALSE has no effect.
1: IINVAL_TRUE
0: IINVAL_FALSE
13.7.2 NV_PVIC_FALCON_BOOTVEC
31:0 R/W 0 NV_PVIC_FALCON_BOOTVEC_VEC: Stores the initial execution start address of the CPU
when it is first started after a reset.


0: VEC_INIT (default)
13.8 Falcon DMA Registers
13.8.1 NV_PVIC_FALCON_DMACTL
Offset: 0x110c │ Read/Write: R/W │ Reset: 0x000000XX
31:7 R 0 Reserved
6:3 R None NV_PVIC_FALCON_DMACTL_DMAQ_NUM: Indicates valid request number at DMA request

queue.
2:1 R 0 Reserved
0 R/W 1 NV_PVIC_FALCON_DMACTL_REQUIRE_CTX: When set to TRUE, a valid context must be

loaded before any DMA request can be serviced. Pending requests without a valid current context
remain pending, and do not prevent the engine from reporting idle. When clear, DMA requests are
serviced regardless of the current context.
Once a request is issued, it must complete before the engine can report idle, as needed for
example to process WFI context switch requests.
1: REQUIRE_CTX_INIT (default)
1: REQUIRE_CTX_TRUE
0: REQUIRE_CTX_FALSE
13.8.2 NV_PVIC_FALCON_DMATRFBASE
31:0 R/W 0 NV_PVIC_FALCON_DMATRFBASE_BASE:

0: BASE_INIT (default)
13.8.3 NV_PVIC_FALCON_DMATRFMOFFS
IMEM/DMEM offset for the transfer.
31:16 R 0 Reserved
15:0 R/W 0 NV_PVIC_FALCON_DMATRFMOFFS_OFFS:

0: OFFS_INIT (default)
13.8.4 NV_PVIC_FALCON_DMATRFCMD
Offset: 0x1118 │ Read/Write: R/W │ Reset: 0x0000XXXX
31:15 R 0 Reserved
14:12 R/W Unknown NV_PVIC_FALCON_DMATRFCMD_CTXDMA:
11 R 0 Reserved
10:8 R/W Unknown NV_PVIC_FALCON_DMATRFCMD_SIZE:

0: SIZE_4B


1: SIZE_8B
2: SIZE_16B
3: SIZE_32B
4: SIZE_64B
5: SIZE_128B
6: SIZE_256B
7:6 R 0 Reserved
5 R/W Unknown NV_PVIC_FALCON_DMATRFCMD_WRITE:

1: WRITE_TRUE
0: WRITE_FALSE
4 R/W Unknown NV_PVIC_FALCON_DMATRFCMD_IMEM:

1: IMEM_TRUE
0: IMEM_FALSE
3:2 R 0 Reserved
1 R Unknown NV_PVIC_FALCON_DMATRFCMD_IDLE: Indicates that the DMA engine is still busy with a
transfer or has more transfers pending in the queue.
1: IDLE_TRUE
0: IDLE_FALSE
0 R Unknown NV_PVIC_FALCON_DMATRFCMD_FULL: Indicates that the DMA request queue is full and a
valid request is still needed to move into the queue.
1: FULL_TRUE
0: FULL_FALSE
13.8.5 NV_PVIC_FALCON_DMATRFFBOFFS
Frame buffer (FB) offset for the transfer.
Offset: 0x111c │ Read/Write: R/W │ Reset: 0x00000000
31:0 R/W 0 NV_PVIC_FALCON_DMATRFFBOFFS_OFFS:

0: OFFS_INIT (default)


14.0 CPU
® ® ® ®
The NVIDIA Tegra K1 processor CPU complex contains quad ARM Cortex -A15 CPUs in a 4-PLUS-1 configuration with a
fifth architecturally identical power-saving Cortex-A15 Companion Core.
14.1 Cortex-A15 CPU

The Cortex-A15 CPU is an advanced processor design with many features for high instruction throughput. It integrates the L2
cache controller into the CPU complex unlike Cortex-A9 CPUs. All of the CPUs include the NEON Media Processing Engine.
Further details of the Cortex-A15 CPU itself are available from ARM.
These two documents are the key Cortex-A15 references, and both are available from ARM’s website:
 Cortex-A15
Revision: r3p3
Technical Reference Manual
Published by ARM Limited, document number ARM DDI 0438D.
 ARM Architecture Reference Manual

ARM v7-A and ARM v7-R edition
Published by ARM Limited, document number ARM DDI 0406C.
Note: These are the current versions at the time of writing. You should periodically look for
updates and always refer to the latest available version of this material.
You should also review the latest version of the ARM errata for Cortex-A15 CPUs. ARM has published this on their website as
the Software Developers’ Errata Notice.
14.1.1 Cortex-A15 Implementation Details

Many aspects of the Cortex-A15 CPU may be configured for a specific implementation. The Tegra K1 implementation has the
following features:
Cortex-A15 Processor Configuration

Option
Main Quad-Core
Feature Complex Companion Core
Processor Revision r3p3 r3p3
Number of processors 4 1
L2 Cache Size 2MB 512KB
L2 Arbitration register slice 1 0
L2 Tag RAM register slice 1 1
L2 Data RAM register slice 1 1

L2 Tag RAM latency 2 2
L2 Data RAM latency 3 cycle 2 cycle
L2 Logic idle gated clock Included Included

ECC/parity support None None
VFP and Neon Included Included

CPU
Cortex-A15 Processor Configuration
Option
Main Quad-Core
Feature Complex Companion Core
Generic Interrupt Controller Included Included
Shared Peripheral Interrupts 160 160
14.2 4-Plus-1 Configuration and Control

The NVIDIA 4-PLUS-1 processor architecture has a fifth Companion Core available for low power operation. In addition to the
main quad core CPU complex, the Companion Core is an additional CPU complex replicating CPU 0 of the main complex, and
implemented in a low-leakage technology. The Companion Core is also sometimes referred to by its engineering name, the
“shadow” core; and also is commonly referred to as the LP Core or LP CPU Cluster referring to its Low Power operating
capability.
The goal of this architecture is to provide efficient CPU operation across a very broad range of processor loads, with the quad-
core complex optimized for high-speed operation with low dynamic power, and the Companion Core optimized for low-speed
operation where transistor leakage becomes an important factor in power. These two CPU complexes operate exclusively to
each other, meaning the hardware does not support simultaneous operation in any form. The main quad core complex has
2 Megabytes of L2 cache RAM, the companion core as a separate 512 Kilobyte L2 cache RAM.
The quad core complex implements separate power-gating for each of the four cores, and also a fifth power gate domain for
the shared logic and L2.
Refer to the Flow Controller section of this document for details on how this is controlled.
14.3 Exclusive Operations

The Tegra K1 processor supports ARM exclusive operations (LDREX*, STREX* and CLREX) in cacheable memory only.
Device or Strongly-Ordered memory spaces should not be used with these instructions.
14.4 CPU Voltage Sensing Control

The Voltage Regulator (VR) delivers power to the board, then to the package and to the transistors in the silicon. The VR
regulates its voltage output based on the sense feedback. To reduce inaccuracy in the VR output voltage level, the sense
voltage needs to be as close to the transistors as possible.
For a power-gated partition, if the sense point is at the real VDD power grid, then the drop across the power-gate adds to the
inaccuracy of the sense voltage. To reduce this inaccuracy, virtual VDD can be sensed. However, if the PG partition is power-
gated, then its virtual VDD is off and cannot be used for sense feedback. Because partitions are power-gated/ungated
dynamically, there needs to be control logic to provide dynamic control for the voltage-sense mux such that the virtual VDD is
selected only when the corresponding PG partition is power-ungated.
As shown in the following diagram, a 6-input mux is used to select one (or more) of sensed voltages. The 6-input voltages are
VVDD of each of the 5 PG partitions (in cluster0) and the real CPU VDD. The mux is expected to select the VVDD of all PG
partitions that are power-ungated (powered on). If none of the 5 PG partitions are power-ungated, then real VDD is selected as
the sense voltage.

CPU
Figure 26: CPU Voltage Sensing Mux Control Signals
Cluster0 ( VDD- CPU) VDD- SOC

PMC
VVDD_override_ce1_b
VVDD_override_ce3_b
VVDD_override_c0nc_b
VVDD_override_ce0_b
VVDD_override_ce2_b
c0nc_clampen
ce2_clampen
ce3_clampen
ce1_clampen
ce0_clampen
VVDD_override
Select_VDD
CE 0 CE 1
(incl. NEON, (incl. NEON,
VFP,L1$) VFP,L1$)
C0NC
(incl. L 2 Data
[2MB] , L 2 Ctrl,
SCU, vGIC,
Debug)
CE 2 CE 3
(incl. NEON, (incl. NEON,
VFP,L1$) VFP,L1$)
SE_C0NC
SE_CE1
SE_CE0
SE_CE2
SE_CE3
SE_VDD
CE0
Sense_Out
CE1 Sense Select
CE2 MUX
CE3
C0NC
CVDD
TOP
The PMC provides a 6-bit mux select bus. The mux corresponding to 5 partitions is selected if those partitions are powered on.
During normal operation, selection of the correct voltage sense signal is handled entirely by the PMC. For debug purposes, a
per partition override register (see the APBDEV_PMC_CPU_VSENSE_OVERRIDE_0 register) is provided which can be
configured to disable input from any of the 5 PG partitions, and select real VDD. The sensing mux select control needs to be
as follows:
 Never select the VVDD of a partition which is power-gated

 Select VVDD of all partitions that are power-ungated
 When all partitions are power-gated, select real VDD
- During transition, both power-ungated (VVDD) and real VDD can be selected.

CPU

15.0 FLOW CONTROLLER

The flow controller provides the sequencing of hardware-controlled CPU power states for the main CPU complex and the AVP
coprocessor (also known as COP). It also provides hardware support for CPU cluster switching between the fast quad-core
complex and the companion core.
The flow controller receives CPU power-state requests from CPUs, prioritizes them, and sends power on/off requests to PMC,
which powers gates/ungates corresponding CPUs. It monitors per CPU interrupts and events to determine CPU wake
condition and initiates the CPU wake based on wake events/interrupts.
The flow controller provides configuration registers for software to configure wake events, etc. The flow controller provides a
mechanism to halt conditionally or unconditionally:
 Conditional halt/resume is based on a variety of events, including timers, external trigger, and internal clocks.
 COP (AVP) is halted by extending a bus cycle.
 CPU can be halted by software interaction: software issues the WFI instruction to stop the processor, the flow
controller asserts the EVENT input of the CPU to restart it.
15.1 Features and Functionality

®
The flow controller receives requests from processors (Cortex -A15 processors and the AVP) to change their power state, or
system power state. It also receives the interrupts from the interrupt controllers (vGIC and LIC) and other events which it uses
to wake them up. It also provides support for cluster switching.
Figure 27: Flow Controller Block Diagram
pg_en[31:0],clamp_en
Cluster0
FlowCtlr
PPSB
Registers
CPU0 irq/fiq CPU0

flow2all_active_cluster
standwfi/wfe FlowCtlr
Cluster
Switch
CPU1
CPU1 FlowCtlr
vGIC
CPU2
CPU2 FlowCtlr PMC
ARB
PMC
I/F
CPU3
FlowCtlr
CPU3
flow2car_mpcore_rst[4:0],
CPU
CPU-LP reset
flow2car_a9avp_rst
FlowCtlr
Cluster1
COP(ARM7)
vGIC
CPU-LP FlowCtlr
irq0,1/fiq0,1
halt
ARM7
XBAR
ARM7
Events
LIC
pg_en[7:0],clamp_en

Flow Controller
15.1.1 WFI Instructions and STANDBYWFI Signals Usage

Tegra K1 devices use the WFI (Wait For Interrupt) instruction of ARMv7-A architecture (supported by both Cortex-A15 and
Cortex-A9 processors), used by the CPU to interlock with the flow controller for the purpose of triggering low-power-state
transitions.
When executing WFI, the processor waits for all prior instructions to complete before entering the idle (low-power) state. The
WFI instruction ensures that all explicit memory accesses that are prior to the WFI instruction in program order have
completed. Also, WFI ensures that all speculative memory accesses have completed.
After executing WFI, the processor asserts the STANDBYWFI signal. Assertion of STANDBYWFI guarantees that the
processor is in idle, and there is no outstanding memory access. The processor continues to assert STANDBYWFI until one of
the interrupt (IRQ or FIQ) is asserted or processor is reset.
The flow controller can be configured to trigger (per CPU) power-gating based on WFI instruction execution.
15.1.2 CPU (A15) Low-Power States
15.1.2.1 CPU Clock Gating

If a CPU is idle for a short period of time, then it can be halted which results in its CPU clock-gating. This is referred to as LP3
CPU power-state. The WFI instruction is executed for putting CPU into LP3 (i.e. for clock-gating). After executing WFI, CPU
disables most of the clocks in the CPU except the clock for the small wake up logic clock.
Exit from halt state occurs when the CPU detects an interrupt on IRQ or FIQ pins. Note that this state is per CPU. This clock-
gating is internal to the Cortex-A15 processor, so it does not require any support from the flow controller.
15.1.2.2 CPU Power Gating

The flow controller uses a (separate) state machine to sequence power-gating for each CPU. The main CPUs flow-controller
state machines are different from that for the CPU Rail PwrUp and COP. So it has three different variants of state machines:
one for main CPUs (which is instantiated 4 times, one for each CPU), one for CPU Rail PwrUp and one for COP. If the active
cluster is cluster1, then based on CPU-ID, corresponding state machine is used for CPU-LP.
The flow controller can have one or more power-gating requests outstanding. However, it only issues one request at a time to
the PMC. A fixed priority arbiter is used to arbitrate among CPU power-gating on/off requests, and the winning request is sent
to the PMC. This is primarily for two reasons: i) to avoid power noise issues, only one partition is power gated/ungated at a
time, ii) PMC’s power-gating controller supports only one request at a time.
The flow controller to PMC interface includes core-ID which explicitly indicates which CPU or non-CPU partition should be
power gated/ungated. PMC is not expected to use cluster-ID for identifying whether request is for cluster0 or cluster1 CPU.
CPU Power Gated Domains

As shown in the figure below, each CPU is an independent power-gated domain. The cluster0 non-CPU may be power gated
as a separate domain. The cluster1 non-CPU is power-gated as a separate domain.

Flow Controller
Figure 28: CPUs PG Domains
15.1.2.3 Cluster0 CPU-Rail Gating

At boot, CPU rail is off by default, and is powered on by the AVP boot code using a direct register write to PMC (or by direct
I2C commands to PMIC). Also, at LP0 exit, the CPU rail (if need be) is powered-on (by software) by direct register write to the
PMC (or by direct I2C commands to PMIC).
The CPU rail can be powered off by software running on the companion core after a cluster switch using a direct register write
to PMC. Refer to the “Cluster Switch” section for details.
15.1.2.4 Cluster0 CPU Power Gating

Each of the cluster0 CPUs can be independently power-gated with the help of the flow controller. If the CPU being power-
gated is not the last one (or is not requesting the CPU rail to be powered off), then it is power gated/ungated as described in
the section on “CPU Power Gating/Ungating Sequence”.
The last CPU being power-gated can request non-CPU to be power-gated or CPU rail to be powered off. Similar when the first
CPU is being woken up, then the flow controller would power on (if it was off) the CPU rail or power-ungate non-CPU (if it was
power-gated).
Note: The flow controller will either sequence the CPU rail controls or the non-CPU power-gating
controls (with last CPU power-gating request), but not both.
The flow controller can be set up to power gate/ungate each of the CPU independently. In addition, the flow controller can be
set up to power gate/ungate non-CPU as a result of a CPU power gate/ungate request. The following section describes a non-

Flow Controller
CPU power gate/ungate along with CPU. The individual CPU only power gate/ungate is described in the section on “CPU
Power Gating/Ungating Sequence”.
The following table indicates power-on options which can be triggered when the flow controller receives CPU wakeup event.
Per CPU Power Ungate Non-CPU Power UnGate CPU Rail Power On Comments
Yes No No Individual CPU power-ungating
Yes Yes No
15.1.2.5 Cluster1 CPU Power Gating

The cluster1 CPU (also known as shadow CPU or CPU-LP) can be power gated/ungated with the help of the flow controller.
Along with CPU-LP power-gating, its non-CPU can be power gated (by configuring flow controller before requesting CPU
power-gating). From PMC perspective, CPU-LP and non-CPU are two separate power-gated domains. The flow controller
sends CPU-LP and non-CPU power-gating requests to the PMC as follows:
The flow controller can be set up to power gate/ungate CPU-LP only. In addition, the flow controller can be set up to power
gate/ungate non-CPU along with CPU-LP as result of CPU-LP power gate/ungate request. The next section describes non-
CPU power gate/ungate along with CPU-LP. The CPU-LP only power gate/ungate is described in the section on “CPU Power
Gating/Ungating Sequence”.
Power-Gating (Power-Off) CPU and Non-CPU

To initiate CPU-LP power-gating, SOFTWARE configures the flow-controller registers associated with CPU-ID (in MPID
register). The SOFTWARE initiates CPU-LP (with non-CPU) power-gating request as described in section on CPU Power-
Gating (Power OFF) Sequence. After that, the flow controller sequences CPU-LP and non-CPU power-gatings as follows:
 [SW-CPU] Initiate CPU-LP power gating with non-CPU power-gating rail (refer to the section on CPU Power-Gating
(Power OFF) Sequence) for details of software steps
 [HW-Flow] CPU power-gating step
- Request PMC to power-gate the CPU (Refer to the section on “CPU Power-Gating (Power OFF) Sequence”)
- Wait for PMC acknowledgment
 [HW-Flow] Non-CPU power-gating step
- If non-CPU is off (see CPU_PWR_CSR[C1NC_STS]), or in the process of being powered on or off then this step
is done.
Note: This condition should never be seen. But this makes the cluster1 sequence the same as
that of cluster0, so it is all right to make this check in the state machine.
- Update non-CPU power status register (CPU_PWR_CSR[C1NC_STS]) to be in the process powering off
- Request PMC to power-gate non-CPU (refer to the section on “Non-CPU Power Gating/Ungating Sequence”)
- Waits for PMC acknowledgment
- Update non-CPU power status (CPU_PWR_CSR[C1NC_STS]) to be powered off
Power-Ungating (Power On) CPU and Non-CPU

Based on CPU-LP wake-up event ((see HALT_CPUx_EVENT register), the flow controller power-ungates CPU-LP (and non-
CPU).
 [HW-Flow] Receives CPU-LP wake event

 [HW-Flow] Non-CPU power-ungating step
- If non-CPU is power-ungated, then this step is done. Else,

Flow Controller
- If non-CPU is in the process of being powered on, then wait for it to be powered on. After that, this step is done.
Else,
- If non-CPU is in the process of being powered off, then wait for it to be powered off. After that continue to power
it off.
Note: The above two steps should never be encountered. But making these checks is all right
and makes this sequence similar to corresponding cluster0 sequence.
- Update non-CPU power status register (CPU_PWR_CSR[C0NC_STS]) to be in the process of powering on.
- Request PMC to power-ungate non-CPU
- Wait for PMC acknowledgment
- Update non-CPU power status register (CPU_PWR_CSR[RAIL_STS]) to be powered on.
 [HW-Flow] CPU power-ungating step
- Request PMC to power-ungate CPU
- Waits for PMC ack
15.1.3 Cluster Switch

15.1.3.1 Cluster1 (Shadow) to Cluster0 Switch
The cluster switch is a variant of LP2 low-power state transition. From usage perspective, cluster1 to cluster0 switch is latency
critical. For cluster1 to cluster0 switch, the cluster1 CPU is power-gated (with its non-CPU power-gating), cluster switched is
performed, and a cluster0 CPU is powered on (either immediately or conditional on a wake event).
Following is the cluster1 to cluster0 migration sequence:
 [SW-CPU] Configure the flow controller for cluster switch

 [SW-CPU] Configure cluster0 CPU wake event
- Software has to configure wake event for the CPU which is in the CPU-ID. After cluster switch, the flow controller
can only wake-up the CPU which is pointed to by CPU-ID.
 [SW-CPU] Trigger CPU rail on sequence as described in “CPU Rail Gating/Ungating Sequence”.
Note: This step allows the CPU rail (cluster0 power) to be powered up in parallel with the
cluster1 power-gate sequence. However, cluster1 is still an active cluster (until the cluster
state is switched by the flow controller).
 [SW-CPU] Initiate power-gating of cluster1 CPU (with non-CPU)

 [HW-Flow] Perform cluster1 non-CPU and CPU-LP power-gating as described in the section on “Cluster1 CPU Power
Gating”
 [HW-Flow] After cluster1 power-gating, wait for pre-cluster-switch delay (programmed in a flow-controller register)
 [HW-Flow] Perform cluster switch
 [HW-Flow] Wait for post-cluster-switch-delay (programmed in a flow-controller register)
 [HW-Flow] Waits for the wake event (this could be immediate)
 [HW-Flow] Power-on first CPU of cluster0 as described in the section on Cluster0 CPU Power Gating
15.1.3.2 Cluster0 to Cluster1 (Shadow) Switch

The cluster switch is a variant of LP2 low-power state transition. For cluster0 to cluster1 switch, the last CPU of cluster0 is
power-gated, the cluster is switched, and cluster1 CPU is power ungated (either immediately or conditional on wake event).
Following is the cluster0 to cluster1 migration sequence:
 [SW-CPU] Configure the flow controller for cluster switch

Flow Controller
 [SW-CPU] Configure cluster1 CPU wake event

 [SW-CPU] Configure the CPU-ID of CPU which is being migrated to CPU-LP
 [SW-CPU] Initiate power-gating of last CPU (with non-CPU power gatingoption) as described in section on “Cluster0
CPU Power Gating” for CPU power-gating and non-CPU power gating.
 [HW-Flow] Wait for pre-cluster-switch delay (programmed in a flow-controller register)
 [HW-Flow] Perform cluster switch
 [SW-CPU] Software running on cluster 1 can power down the CPU rail by directly writing to the CRAIL bit of the
APBDEV_PMC_PWRGATE_TOGGLE_0 register. The CPU rail has to be brought up by software prior to switching
the cluster back to cluster 0 using the same mechanism.
 [HW-Flow] Wait for post-cluster-switch-delay (programmed in a flow-controller register)
 [HW-Flow] Waits for the wake event (if needed)
- At the wake event, the flow controller powers up cluster1 as described in section on “Cluster1 CPU Power
Gating”
15.1.4 CPU-ID Function
When the active cluster is cluster1, then the flow controller uses CPU-ID (programmed in MPID register) to associate CPU-LP
to corresponding CPU state machine which is used to power gate/ungate CPU-LP. Also, during cluster1 to cluster0 switch,
flow-controller uses CPU-ID to wake the corresponding cluster0 CPU (based on configured wake events).
Also, CPU-ID is used to drive cluster1 CPU-ID pins, which are captured in the CPU (CP15) register that software uses to read
the CPU-ID of the current CPU. Note that the CP15 register captures the MPID value, which is the virtualized MPIDR, not the
physical MPIDR. Thus, it must be read by the CPU in monitor mode or virtualization mode.
Once cluster0 is active and cluster migration has been completed, then the flow controller does not have any use for CPU-ID.
15.1.5 AVP Low-Power States
15.1.5.1 Halt (Clock Gating)

There is no specific halt instruction in the AVP. However, its memory bus cycle can be extended by any number of cycles.
When configured to put the AVP into halt, the flow controller forces its memory bus interface into wait-state. After that if the
AVP issues any bus cycle (e.g., fetching next instruction), then that bus cycle does not return unless flow-controller releases
its bus (i.e., wakes it up). The flow controller can be configured to wake up the AVP by IRQ/FIQ or other wake up events.
During an AVP halt state, its clock is automatically gated by hardware.
15.1.5.2 Power-Gating
The AVP is not power-gated.
15.1.6 CPU Power Gating/Ungating Sequence

The processor’s (A15 or A9) power-gating can be triggered by either i) a direct register write to PMC or ii) interacting with the
flow controller. This section describes the power-gating sequence via flow-controller interaction.
The flow controller interfaces with the Processors, PMC, and CAR to implement power-gating on/off hardware-sequence. The
power-gating controller is in the PMC, while clock and reset controls are in the CAR.
15.1.6.1 CPU Power-Gating (Power OFF) Sequence

 [SW-CPU] Prepare processor (flush CPU L1$, context save, set up flow controller) for power-gating

Flow Controller
 [SW-CPU] Execute WFI to make sure there is no outstanding processor transaction

 [HW-CPU] Assert STANDBYWFI to the flow controller
 [HW-Flow] Assert flow2car_*_rst
- This is not used in power gate sequence when powergate_enable is high
- When powergate enable is “0”, CAR uses this to assert CPU reset
 [HW-Flow] Request PMC (by asserting flow2pmc_req and associated bus) to power-off CPU
 [HW-PMC] Assert the clamp control signal. This goes to ccplex and also goes to CAR.
 [HW-CAR] Assert CPU reset and reset the CPU clock
- [HW-CPU] Stop CPU clock
 [HW-CAR] Ack PMC to indicate CPU clock is stopped
 [HW-PMC] Power off CPU (assert CPU PG-enables)
 [HW-PMC] Clear PWRGATE_STS register bit. This is to indicate that CPU is power-gated.
 [HW-PMC] Ack to the flow controller to confirm power-off (by asserting pmc2flow_ack)
- Note: After receiving ack from the PMC, the flow controller must not issue a new request to the PMC until
pmc2flow_ack goes idle.
 [HW-Flow] Deassert flow2pmc_req (after seeing the Ack)
 [HW-PMC] Deassert Ack (after seeing request deassertion)
 [HW-Flow] Do not start another request until Ack goes down
15.1.6.2 CPU Power-Ungating (Power ON) Sequence

The generic CPU power-ungating (power OFF) sequence is described below. The specific details of main CPU (Cortex-A15)
are described in their respective power-gating sections.
 [HW-Flow] After detecting wake up condition, request PMC to power-on CPU (by asserting flow2pmc_req and
associated bus)
 [HW-PMC] Power-on the CPU (deassert CPU PG-enables)
 [HW-PMC] Set PWRGATE_STS register bit. This indicates that the CPU is power-ungated
 [HW-PMC] Ack flow controller (by asserting pmc2flow_ack) that CPU is powered on
 [HW-Flow] Deassert flow2car_*_rst to CAR
 [HW-CAR] Request CPU to ungate CPU clock (by deasserting car2ce*_cke)
 [HW-CPU] Ungate CPU clock
 [HW-CAR] Request PMC to remove CPU clamp (by asserting car2pmc_ack)
- This is to make sure that clock gets ungated well ahead of reset deassertion
 [HW-PMC] Removes the clamping (by deasserting pmc2ce*_clamp)
- This goes to the CPU and also to the CAR
 [HW-PMC] Ack flow controller (by deasserting pmc2flow_ack)
 [HW-CAR] Deasserts reset
 [SW-CPU] CPU fetches code from reset vector.
- Note all of the Cortex-A15 CPUs share one reset-vector register (in EVP registers).
15.1.7 Non-CPU Power Gating/Ungating Sequence

From a software perspective, non-CPU power gating/ungating is done as part of CPU power gating/ungating request. The flow
controller issues a separate request (to PMC) for power-gating CPU and non-CPU domain. The main reason is that PMC can

Flow Controller
only sequence one power domain at a time, so the flow controller serializes requests on behalf of PMC. From the flow
controller hardware perspective, the sequence for non-CPU domain power gating is similar to CPU domain power
gating/ungating which is described in above sections.
There is an ARM requirement for Cortex-A15 CPUs that there must be a minimum of 16 clocks prior to clamps being
deasserted on outputs from the CPU core partitions to the non-CPU partition. To address this issue, the CAR waits for
CCPLEX to assert ccplex2car_pmc_cntr_ack before it deasserts car2pmc_<pgpart>_ack. CCPLEX implements the 16 CPU
clock cycle wait after reset is released and clocks unstopped by the CAR, before it asserts the ack to CAR. The 16-cycle
counters are implemented in the VDD_CPU power rail domain and the acks are generated from the same domain. The per-
core acks are not affected by the ce0/ce1/ce2/ce3 clamps. The c0nc, c1nc, and unpower-gated VDD_CPU logic are not
affected by the additional handshake logic between CCPLEX and CAR. So these partitions rely on the
CAR2PMC_NONCPU_ACK_WIDTH counter for CAR to allow the PMC to release the clamp controls on these partitions.
In the CAR register space, to enable the legacy mode i.e. disable the 16-cycle counter:
 Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_IGNORE_HW_ACK_WIDTH to 1
 Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_IGNORE_SW_ACK_WIDTH to 0
This will cause CPU core partition power gating FSMs in the SOC to use the
CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH counter.
To enable the fix and use both the existing T3 counter and the 16-cycle counter inside CCPLEX:
- Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_IGNORE_HW_ACK_WIDTH to 0
- Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_IGNORE_SW_ACK_WIDTH to 0
To enable the fix and use only the 16-cycle counter inside CCPLEX but not the existing T3 counter:
 Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_IGNORE_HW_ACK_WIDTH to 0
 Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_IGNORE_SW_ACK_WIDTH to 1
15.1.8 CPU Rail Gating/Ungating Sequence

CPU Rail gating/ungating is only supported on Tegra K1 devices when a cluster switch is taking place or during LP0 entry
when the PMIC turns the rail off.
15.1.8.1 CPU Rail Gating Constraints

The FCPU cluster cannot be rail-gated as a side-effect of the last FCPU core asserting WFI.
The ccplex2car_pmc_cntr_ack_fcpu{0-3} and DFT-related signals use tmc2clamp_pmc2c0nc_clamp as the clamp enable with
the effect that the clamps are not asserted when FCCPLEX is rail gated. The tmc2clamp_pmc2c0nc_clamp signal is asserted
only when the C0NC (non-CPU) partition is power gated. Since power-gating C0NC is mutually exclusive with respect to rail
gating FCCPLEX, there are two constraints:
 FCCPLEX can only be rail gated by a cluster switch sequence by programming CSR_ENABLE_EXT field to 2’b10.
FCCPLEX still needs to be rail gated during LP0 entry from FCPU, which results in an unavoidable window of time
when the level shifters may leak when SOC and CPU rails are simultaneously being turned off by the external PMIC.
 During a cluster switch from FCCPLEX to SCCPLEX, F-C0NC should be power gated only. The FCCPLEX rail can
be later turned off by software running from the SCPU:
- Set CSR_ENABLE_EXT to 0x1
- Trigger cluster switch
- Toggle the CRAIL bit of APBDEV_PMC_PWRGATE_TOGGLE_0. This step will cause the correct clamps to be
asserted.

Flow Controller
When switching back to the FCPU, the CPU rail needs to be powered up using PMC controls. Flow controller RAIL_ENABLE
cannot be used for this purpose.
15.1.8.2 Cluster0 RAM Re-Repair

At (cold or warm) boot power-up of the CPU rail, software powers up the CPU rail (by direct register writes to the PMC or the
PMIC), and triggers RAM repair by writing to the RAM_REPAIR[REQ] register of the flow controller. After that software polls
RAM_REPAIR[STS] to ensure that the repair is done.
After boot power-up of the CPU rail, whenever the CPU rail is powered up by the flow controller, the flow-controller hardware
also requests cluster0 RAM re-repair, and ensures that the repair is completed.
The re-repair request and ack signals are per segment of the CPU repair chain. The request, once asserted (high), must
remain high for as long as it does not receive the corresponding ack signal.
15.1.9 Cortex-A15 Debug Power Up/Down Requirements

The Cortex-A15 processor requires debug power up/down related support. The flow controller provides the following debug
support.
15.1.9.1 DBGPWRUPREQ
The CoreSight can initiate power-up (for a CPU which is power-gated via the flow controller) by writing to the Cortex-A15
DBGPRCR register. As a result of this register write, A15 asserts DBGPWRUPREQ signal (a per CPU active-high level). Note,
this signal can never be asserted when C0NC (or C1NC) is power-gated (since the logic generating this is inside those
partitions).
The flow controller uses this signal as a wake-event (in addition to the wake events programmed in CPUx_CSR register) to
wake the corresponding CPU-only. The flow controller qualifies this signal by corresponding PWRUPREQ_QUAL bit (of
FLOW_DBG_QUAL register). In summary, the flow controller uses the following condition to wake up a CPU.
CEx wake-condition = (CEx wake-event as programmed in CPUx_CSR) || (<ccplex2flow>_DBGPWRUPREQx &&

PWRUPREQ_QUALx)
15.1.9.2 DBGNOPWRDWN
The CoreSight can force CPU power-down to be power-down “emulation” only by writing to the Cortex-A15 DBGPRCR
register. As a result of this register write, the Cortex-A15 asserts DBGNOPPWRDWN signal (a per CPU active-high level).
Note, this signal is asserted to emulate CPU-only power-gating.
The flow controller qualifies <ccplex2flow>_DBGNOPPWRDWNx signal by corresponding NOPPWRDWN_QUALx bit (of
FLOW_DBG_QUAL register) and uses that as an indication of CPU power-gating without the pg_enable option.
Note that CPU power-gating is still triggered by CPUx_CSR write only (based on WFI). But regardless of CPUx_CSR register
configuration, if (<>_ DBGNOPPWRDWNx && NOPPWRDWN_QUALx == TRUE), then only CPUx is power-gated without the
pg_enable option.
15.1.9.3 DBGPWRDWNREQ/DBGPWRDWNACK
Cortex-A15 debug logic needs to know about power-gating requests. It also needs to make sure that power-gating starts only
after it has acknowledged (so it can flush trace buffers, etc.). For this purpose, the Cortex-A15 provides per CPU
DBGPWRDWNREQ/ DBGPWRDWNACK interface.
Logically, STANDBYWFIx (Cortex-A15 output) can be fed to DBGPWRDWNREQx (Cortex-A15 input). But STANDBYWFI can
be asserted for many reasons, so it has to be qualified when it is asserted for CPU power-gating. The flow controller provides
qualifier (PWRDWNREQ_QUALx bits of FLOW_DBQ_QUAL register) which will be set by software at the power-gating entry,
and cleared by software at CPU power-ungating.

Flow Controller
Also, if qualifier (i.e., PWRDWNREQ_QUALx) is set, then the flow controller needs to wait for DBGPWRDWNACKx (in
addition to waiting for existing STANDBYWFIx condition) before starting the CPUx power-gating.
In summary, the following is needed in each ccplex cluster:
<ccplex>_ DBGPWRDWNREQx = <ccplex>_STANDBYWFIx & <flow2ccplex>_PWRDWNREQ_QUALx
The flow controller needs to wait for <ccplex2flow>_DBGPWRDWNACKx & PWRDWNREQ_QUALx (in addition to existing
wait for STANDBYWFIx etc condition).
15.2 Flow Controller Registers

In the Flow Controller register descriptions, CPU refers to CPU0, and COP refers to the AVP coprocessor. CPU-LP (CPU4)
has its own set of control registers. This is required because there is a case (cluster1 to cluster0 switch) where both sets of
registers can be configured in parallel. Also, since CPU-LP may morph into any of the four CPUs, it is better to keep its control
register separate.
The EVENTS register is replicated per core, once for COP, four times for the cores of Cluster0.
The fields and enums have the following interpretation:
 MODE defines how the flow controller logic operates; the reset value is 0x0 for CPU0 and COP (does nothing) and
0x2 for CPU1, 2, 3 (WAITEVENT). This is related to the default behavior of the reset generator.
 Enumerated values for the field MODE are defined below.
Field Mode Enumerated Description
Value
FLOW_MODE_NONE 0 No flow control
FLOW_MODE_RUN_AND_INT 1 Keep running but generate interrupt when event
conditions met (not used)
FLOW_MODE_WAITEVENT 2 Stop running until event conditions met
FLOW_MODE_WAITEVENT_AND_INT 3 Same as FLOW_MODE_WAITEVENT but generate
an interrupt when resumed (not used)
FLOW_MODE_STOP_UNTIL_IRQ 4 Stop until an interrupt controller interrupt occurs
FLOW_MODE_STOP_UNTIL_IRQ_AND_INT 5 Same as FLOW_MODE_STOP_UNTIL_INT but
generate another interrupt when resumed (not used)
FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ 6 Stop until event conditions met AND an interrupt
controller interrupt occurs
There is no enum for 7
 Bit 31: (also known as Halt) = This bit is set to configure the wake up (of corresponding CPU) by any of the
interrupts (LIC_IRQ/FIQ, or GIC_RIQ/FIQ) corresponding to that CPU. If this bit is set, then none of the other
fields of this register need to be set for CPU wake. This bit is set by software and cleared by hardware when any
of these interrupt is received by hardware.
 Bit 30: (also known as Wait) = This bit is set to configure the wake up (of corresponding CPU) by any of the
enabled "events". The events can be enabled by setting other fields of this register (incl. *_IRQ, *_FIQ). If this bit
is set, then at least one of the events needs to be enabled to generate wake event. This bit is set by software
and cleared by hardware when wait event is observed by hardware.
 Bit 29: (also known as Sync) = This bit causes the NEXT Flow Controller register read to stall the processor until
the wake event occurs (Used for COP. Obsolete for CPUs).
The rest of the fields define which conditions will be taken into account to restart a halted processor.

Flow Controller
There are two types of events:
 Counted events: Decrement the field called ZERO. Flow controller resumes when this counter reaches 0
 Activity events: The flow controller resumes when the activity occurs, no counting
All conditions are disabled at reset:
 JTAG: Resume on JTAG activity

 SCLK : Resume on Nth SYSCLK cycle ticks
 X32K : Resume on Nth X32K clock input ticks
 uSEC: Resume on Nth uSEC clock ticks (uSEC = microsecond)
 mSEC: Resume on Nth mSEC clock ticks (mSEC = millisecond)
 SEC : Resume on Nth second RTC clock ticks
 X_RDY: Resume on Nth XIO.RDY Ext. IO Ready events
 SMP3[1,0]: Resume on Nth SMP.3[1,0] Semaphore set events
 XRQ_[D,C,B,A] : Resume on Nth XRQ.[D,C,B,A] External Trigger events
 [O,I]B[E,F]: Resume on Nth [O,I]B[E,F] [Outbox, Inbox] [Empty, Full] Events
 [LIC, GIC]_[IRQ,FIQ]: Resume on [LIC, GIC] [IRQ,FIQ].
 ZERO: Initialized then decremented
Note: If more than one event is enabled, the event counter will decrement based on an OR
condition of enabled events
15.2.1 FLOW_CTLR_HALT_CPU_EVENTS_0
MODE:
0 = FLOW_MODE_NONE
1 = FLOW_MODE_RUN_AND_INT
2 = FLOW_MODE_WAITEVENT
3 = FLOW_MODE_WAITEVENT_AND_INT
4 = FLOW_MODE_STOP_UNTIL_IRQ
31:29 0x0 5 = FLOW_MODE_STOP_UNTIL_IRQ_AND_INT
6 = FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ
2 = FLOW_MODE_STOP
3 = FLOW_MODE_STOP_AND_INT
4 = FLOW_MODE_STOP_UNTIL_INT
5 = FLOW_MODE_STOP_UNTIL_INT_AND_INT
6 = FLOW_MODE_STOP_OR_INT
28 0x0 JTAG
27 0x0 SCLK
26 0x0 X32K
25 0x0 uSEC
24 0x0 MSEC
23 0x0 SEC
22 0x0 X_RDY
21 0x0 SMP31

Flow Controller
20 0x0 SMP30
19 0x0 XRQ_D
18 0x0 XRQ_C
17 0x0 XRQ_B
16 0x0 XRQ_A
15 0x0 OBE
14 0x0 OBF
13 0x0 IBE
12 0x0 IBF
11 0x0 LIC_IRQ
10 0x0 LIC_FIQ
9 0x0 GIC_IRQ
8 0x0 GIC_FIQ
7:0 0x0 ZERO
15.2.2 FLOW_CTLR_HALT_COP_EVENTS_0
MODE:
0 = FLOW_MODE_NONE
2 = FLOW_MODE_STOP
28 0x0 JTAG
27 0x0 SCLK
26 0x0 X32K
25 0x0 uSEC
24 0x0 MSEC
23 0x0 SEC
22 0x0 X_RDY
21 0x0 SMP31
20 0x0 SMP30

Flow Controller
19 0x0 XRQ_D
18 0x0 XRQ_C
17 0x0 XRQ_B
16 0x0 XRQ_A
15 0x0 OBE
14 0x0 OBF
13 0x0 IBE
12 0x0 IBF
11 0x0 LIC_IRQ
10 0x0 LIC_FIQ
9 0x0 GIC_IRQ
8 0x0 GIC_FIQ
7:0 0x0 ZERO
15.2.3 FLOW_CTLR_CPU_CSR_0
The CPU_CSR registers are replicated for each CPU cores. They define additional characteristics of the flow controller linked
to CPU cores, especially the interaction of the flow controller with power management functions. The LP1 state is normally
entered and exited via side effects of the flow controller operation.
All fields of the CPU_CSR register have an initial value of 0. The different fields are:
 PWR_STATE : Current state of the PowerGate State Machine

 WAIT_EVENT: CPU is waiting, wake up is via an event
 HALT: CPU is halted
 P2F_ACK: pmc2flow_ack signal, this is the same signal for both CPU cores
 F2P_PWRUP: flow2pmc_pwrup, this is the same signal for both CPU cores
 F2P_REQ: flow2pmc_req valid, this is the same signal for both CPU cores
 F2C_MPCORE_RST: TRUE when requesting reset of MPCore
 PWR_OFF_STS: TRUE when CPU Power-Gated is OFF by Flow Controller
 INTR_FLAG: TRUE when Interrupt is Active -- Write-1-to-Clear
 EVENT_FLAG: TRUE when Event is Active -- Write-1-to Clear
 ENABLE_EXT: If ENABLE is TRUE, then this specifies what to power off.
o 00b: Power Gate CPU only.
o 01b: Power Gate CPU and non-CPU (note, this option must be used only when last CPU is being
power-gated).
o 10b: Reserved.
o 11b: PG Emulation. Note, this option is for CPU-only PG emulation except for cluster-switch case (i.e.
with SWITCH_CLUSTER=1) in which emulation applies to all PG steps of source cluster. In PG
emulation, PG partition is reset but not power-gated..

Flow Controller
 IMMEDIATE_WAKE: If set, CPU is powered up immediately (without waiting for an interrupt or event). Note: If
this is set then HALT_CPUx_EVENTS[MODE] should be set to 0x2 for immediate wake.
 SWITCH_CLUSTER: If set, the active cluster will be switched when all indicated CPU reach STANDBY_WFI.
This bit self clears once the cluster switch sequence is completed
 WAIT_WFI_BITMAP: All cores indicated in bitmap must be in STANDBY_WFI before switching Cluster
 EVENT_ENABLE: Generates an event when the flow controller exits the halted state
 ENABLE: PowerGate Enable - Halt or Event-wait causes CPU power-gating.
27:24 RO X PWR_STATE
23 RO X WAIT_EVENT
22 RO X HALT
21 RO X P2F_ACK
20 RO X F2P_PWRUP
19 RO X F2P_REQ
17 RO X F2C_MPCORE_RST
16 RO X PWR_OFF_STS
15 RW 0x0 INTR_FLAG
14 RW 0x0 EVENT_FLAG
ENABLE_EXT:
0 = POWERGATE_CPU_ONLY
13:12 RW 0x0 1 = POWERGATE_BOTH_CPU_NONCPU
2 = POWERGATE_CPU_TURNOFF_CPURAIL
3 = PG_EMULATION
11:8 RW 0x0 WAIT_WFI_BITMAP
7:4 RW 0x0 WAIT_WFE_BITMAP. Not used.
3 RW 0x0 IMMEDIATE_WAKE
2 RW 0x0 SWITCH_CLUSTER
1 RW 0x0 EVENT_ENABLE
0 RW 0x0 ENABLE
15.2.4 FLOW_CTLR_COP_CSR_0
COP Control/Status for Interrupts
R/W addr=6000:700c
Offset: 0xc │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxx0xxxxxxxxxxxxxxx)
15 0x0 INTR_FLAG: TRUE when Interrupt is Active -- Write-1-to-Clear

Flow Controller
15.2.5 FLOW_CTLR_XRQ_EVENTS_0
XRQ Event Detect Selector Register
XRQ_D7_XRQ_D0: Setting a bit to 1 enables event triggering for the corresponding bit in
GPIO port D. The assertion level is determined by GPIO_INT.LVL.D. If more than one
31:24 0x0
XRQ.D bit is set, the events are ORed together. The resultant event is enabled by setting the
XRQ.D bit in the HALT_CPU.EVENTS or HALT_COP.EVENTS registers.
XRQ_C7_XRQ_C0: Setting a bit to 1 enables event triggering for the corresponding bit in
GPIO port C. The assertion level is determined by GPIO_INT.LVL.C. If more than one
23:16 0x0
XRQ.C bit is set, the events are ORed together. The resultant event is enabled by setting the
XRQ.C bit in the HALT_CPU.EVENTS or HALT_COP.EVENTS registers.
XRQ_B7_XRQ_B0: Setting a bit to 1 enables event triggering for the corresponding bit in
GPIO port B. The assertion level is determined by GPIO_INT.LVL.B. If more than one XRQ.B
15:8 0x0
bit is set, the events are ORed together. The resultant event is enabled by setting the XRQ.B
bit in the HALT_CPU.EVENTS or HALT_COP.EVENTS registers.
XRQ_A7_XRQ_A0: Setting a bit to 1 enables event triggering for the corresponding bit in
GPIO port A. The assertion level is determined by GPIO_INT.LVL.A. If more than one XRQ.A
7:0 0x0
bit is set, the events are ORed together. The resultant event is enabled by setting the XRQ.A
bit in the HALT_CPU.EVENTS or HALT_COP.EVENTS registers.
15.2.6 FLOW_CTLR_HALT_CPU1_EVENTS_0
MODE:
0 = FLOW_MODE_NONE
2 = FLOW_MODE_STOP
28 0x0 JTAG
27 0x0 SCLK
26 0x0 X32K
25 0x0 uSEC
24 0x0 MSEC
23 0x0 SEC
22 0x0 X_RDY
21 0x0 SMP31
20 0x0 SMP30
19 0x0 XRQ_D

Flow Controller
18 0x0 XRQ_C
17 0x0 XRQ_B
16 0x0 XRQ_A
15 0x0 OBE
14 0x0 OBF
13 0x0 IBE
12 0x0 IBF
11 0x0 LIC_IRQ
10 0x0 LIC_FIQ
9 0x0 GIC_IRQ
8 0x0 GIC_FIQ
7:0 0x0 ZERO
15.2.7 FLOW_CTLR_CPU1_CSR_0
23 RO X WAIT_EVENT
22 RO X HALT
21 RO X P2F_ACK
20 RO X F2P_PWRUP
19 RO X F2P_REQ
16 RO X PWR_OFF_STS
15 RW 0x0 INTR_FLAG
ENABLE_EXT:
3 = PG_EMULATION

Flow Controller
0 RW 0x0 ENABLE
MODE:
0 = FLOW_MODE_NONE
2 = FLOW_MODE_STOP
28 0x0 JTAG
27 0x0 SCLK
26 0x0 X32K
25 0x0 uSEC
24 0x0 MSEC
23 0x0 SEC
22 0x0 X_RDY
21 0x0 SMP31
20 0x0 SMP30
19 0x0 XRQ_D
18 0x0 XRQ_C
17 0x0 XRQ_B
16 0x0 XRQ_A
15 0x0 OBE
14 0x0 OBF
13 0x0 IBE
12 0x0 IBF
11 0X0 LIC_IRQ
10 0X0 LIC_FIQ
9 0X0 GIC_IRQ
8 0X0 GIC_FIQ
7:0 0X0 ZERO

Flow Controller
23 RO X WAIT_EVENT
22 RO X HALT
21 RO X P2F_ACK
20 RO X F2P_PWRUP
19 RO X F2P_REQ
16 RO X PWR_OFF_STS
15 RW 0x0 INTR_FLAG
ENABLE_EXT:
3 = PG_EMULATION
0 RW 0x0 ENABLE
MODE:
0 = FLOW_MODE_NONE
2 = FLOW_MODE_STOP
28 0x0 JTAG
27 0x0 SCLK

Flow Controller
26 0x0 X32K
25 0x0 uSEC
24 0x0 MSEC
23 0x0 SEC
22 0x0 X_RDY
21 0x0 SMP31
20 0x0 SMP30
19 0x0 XRQ_D
18 0x0 XRQ_C
17 0x0 XRQ_B
16 0x0 XRQ_A
15 0x0 OBE
14 0x0 OBF
13 0x0 IBE
12 0x0 IBF
11 0X0 LIC_IRQ
10 0X0 LIC_FIQ
9 0X0 GIC_IRQ
8 0X0 GIC_FIQ
7:0 0X0 ZERO
23 RO X WAIT_EVENT
22 RO X HALT
21 RO X P2F_ACK
20 RO X F2P_PWRUP
19 RO X F2P_REQ
16 RO X PWR_OFF_STS
15 RW 0x0 INTR_FLAG

Flow Controller
ENABLE_EXT:
3 = PG_EMULATION
0 RW 0x0 ENABLE
15.2.12 FLOW_CTLR_CLUSTER_CONTROL_0
Offset: 0x2c │ Read/Write: R/W │ Reset: 0x04004000 (0b000001000000000001000000xxxxxxx0)
POST_SWITCH_DELAY: Two delays on top of the built in pipeline delay when switching
31:20 0x40
cluster, in clock cycles
19:8 0x40 PRE_SWITCH_DELAY
ACTIVE: The Active field can be written, this should only be done by the COP after making
sure all clusters are inactive. Directly writing the Active field will otherwise most probably
result in serious errors as there are no interlock in hardware as when the flow controller is
0 0x0
used to control the switch together with the use of WFI on the currently inactive cluster
0=G
1 = LP
15.2.13 FLOW_CTLR_HALT_COP1_EVENTS_0
MODE:
0 = FLOW_MODE_NONE
2 = FLOW_MODE_STOP
28 0x0 JTAG
27 0x0 SCLK
26 0x0 X32K
25 0x0 uSEC

Flow Controller
24 0x0 MSEC
23 0x0 SEC
22 0x0 X_RDY
21 0x0 SMP31
20 0x0 SMP30
19 0x0 XRQ_D
18 0x0 XRQ_C
17 0x0 XRQ_B
16 0x0 XRQ_A
15 0x0 OBE
14 0x0 OBF
13 0x0 IBE
12 0x0 IBF
11 0x0 LIC_IRQ
10 0x0 LIC_FIQ
9 0x0 GIC_IRQ
8 0x0 GIC_FIQ
7:0 0x0 ZERO
15.2.14 FLOW_CTLR_COP1_CSR_0
Offset: 0x34 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxx00xxxxx0xxx00x00)
23 RO X WAIT_EVENT
22 RO X HALT
21 RO X P2F_ACK
20 RO X F2P_PWRUP
19 RO X F2P_REQ
16 RO X PWR_OFF_STS
15 RW 0x0 INTR_FLAG
8 RW 0x0 WAIT_WFI_BITMAP
4 RW 0x0 WAIT_WFE_BITMAP. Not used.

Flow Controller
0 RW 0x0 ENABLE
15.2.15 FLOW_CTLR_CPU_PWR_CSR_0
Offset: 0x38 │ Read/Write: R/W │ Reset: 0x00000100 (0bxxxxxxxxxxxxxxxxxxxxxxx100000000)
CPU_RG_CFG: If this bit is set, then the flow controller would initiate last-CPU PG (along
with CPU RG (rail-gating) or non-CPU PG) only when other 3 CPUs are already power-
8 0x1 gated. This is primarily for debug purposes.
0 = DISABLE
1 = ENABLE
C1NC_STS: Hardware updates this register based on the current status of the C1NC
partition. Before requesting a power-off (or on) request, flow controller updates this status to
"in the process" status. Note that the flow controller requests C1NC power on/off based on
this register value or PMC pwrgate-status of C1NC depending upon the USE_FLOW_STS
7:6 0x0 register. For debug purposes, this can be written by software.
0 = PARTITION_OFF
1 = PG_IN_PROGRESS
2 = PU_IN_PROGRESS
3 = PARTITION_ON
C0NC_STS: hardware updates this register based on the current status of the C0NC
partition. Before requesting a power-off (or on) request, flow controller updates this status to
"in the process" status. Note, flow controller requests C0NC power on/off based on this
register value or PMC pwrgate-status of C0NC depending upon USE_FLOW_STS register.
5:4 0x0 For debug purposes, this can be written by software.
0 = PARTITION_OFF
1 = PG_IN_PROGRESS
2 = PU_IN_PROGRESS
3 = PARTITION_ON
USE_FLOW_STS:If this is set (=1), then the flow controller will use C0NC_STS/
C1NC_STS/RAIL_STS bits to determine whether to power-gate C0NC/C1NC/CRAIL
3 0x0 domains. If this bit is clear (=0), then the flow controller will use the PMC pwrgate-status of
C0NC/C1NC/CRAIL to determine whether to power-gate the C0NC (and C1NC) domains.
In either case, the C0NC_STS/C1NC_STS/RAIL_STS fields are updated in the same way.
RAIL_STS: Hardware updates this register based on the current status of the CPU-rail.
Before requesting a power-off (or on) request, flow controller updates this status to "in the
process" status. Note, flow controller requests CPU-RAIL power on/off based on this
register value or PMC pwrgate-status of CRAIL depending upon USE_FLOW_STS register.
2:1 0x0 For debug purposes, this can be written by software.
0 = RAIL_OFF
1 = RG_IN_PROGRESS
2 = RU_IN_PROGRESS
3 = RAIL_ON
RAIL_ENABLE: CPU rail power-on request. Software sets this to request CPU rail pwr-on
0 0x0 by flow-controller interaction. If rail is already on, writing to this is ignored. Hardware clears
this bit when CPU power rail in turned on.

Flow Controller
15.2.16 FLOW_CTLR_MPID_0
Offset: 0x3c │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00)
CPU_ID: CPU-ID of C1 CPU. Software programs this field before cluster0 -> cluster1
1:0 0x0
switch. This ID is provided to MPCore_LP which is what is read when the OS reads MPIDR.
15.2.17 FLOW_CTLR_RAM_REPAIR_0
Offset: 0x40 │ Read/Write: R/W │ Reset: 0x00000004 (0bxxxxxxxxxxxxxxxx00000000xxxx01x0)
23:16 RO X DBG_STS: Repair done (acknowledge) from repair logic.
15:8 RW 0x0 DBG_REQ: Repair request for individual segments.
DBG_EN: Debug enable to be able to repair of individual segments of the cluster0 repair
chain
3 RW 0x0
0 = DISABLE
1 = ENABLE
BYPASS_EN: RAM repair bypass enable. 0: Flow-controller requests RAM-repair at CPU

RAIL power-up. 1: Flow-controller does not request RAM-repair at CPU RAIL power-up
2 RW 0x1
0 = DISABLE
1 = ENABLE
STS: Indicates Cluster repair chain status. hardware sets this to '1' when repair of all
1 RO X
segments is done. hardware clears this to '0' when RAM repair is requested.
REQ: Cluster0 RAM repair request. Software sets this bit to '1' to initiate RAM repair
request to all segments in parallel. Hardware clears this bit when software triggered repair is
0 RW 0x0 done (i.e., STS=1)
0 = DISABLE
1 = ENABLE
15.2.18 FLOW_CTLR_FLOW_DBG_SEL_0
Offset: 0x44 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxx0000xxxx0000)
19:18 RO X RG_PWR_STATE: Current state of Rail Gate state machine
17:16 RO X RU_PWR_STATE: Current state of Rail Ungate state machine
15:14 RO X NC_PG_PWR_STATE: Current state of Non CPU Power Gate state machine
13:12 RO X NC_PU_PWR_STATE: Current state of Non CPU Power Ungate state machine

Flow Controller
CNT1_SEL: Activity selection which would be counted by CNT1.

Note power/rail activities are counted only when power/rail gating is via flow controller (and
not direct PMC register write).
0: Idle (counter holds its current value)
1: Increment by 1 every time CPU0 is power gated
5: Increment by 1 every time and of CPU0/1/2 or 3 is power-gated
6: Increment by 1 every time CPU-LP is power gated
7: Increment by 1 every time Ccluster0 non-CPU is power gated
8: Increment by 1 every time Cluster1 non-CPU is power gated
11:8 RW 0x0 9: Increment by 1 every time CPU RAIL is powered off
10: Increment by 1 every time cluser0 is switched to cluster1
0 = IDLE
1 = CPU0_PG
2 = CPU1_PG
3 = CPU2_PG
4 = CPU3_PG
5 = CPU0123_PG
6 = CPULP_PG
7 = C0NC_PG
8 = C1NC_PG
9 = CRAIL_OFF
10 = C0_TO_C1_SWITCH
CNT0_SEL: Activity selection which would be counted by CNT0.

Note: Power/rail activities are counted only when power/rail gating is via the flow controller
(and not direct PMC register write).
0: Idle (counter holds its current value)
5: Increment by 1 every time and of CPU0/1/2 or 3 is power-gated
6: Increment by 1 every time CPU-LP is power gated
7: Increment by 1 every time Ccluster0 non-CPU is power gated
8: Increment by 1 every time Cluster1 non-CPU is power gated
3:0 RW 0x0
9: Increment by 1 every time CPU RAIL is powered off
0 = IDLE
1 = CPU0_PG
2 = CPU1_PG
3 = CPU2_PG
4 = CPU3_PG
5 = CPU0123_PG
6 = CPULP_PG
7 = C0NC_PG
8 = C1NC_PG
9 = CRAIL_OFF

Flow Controller
15.2.19 FLOW_CTLR_FLOW_DBG_CNT0_0
VALUE: Activity count value (updated by hardware based on CNT0_SEL). This register can
31:0 0x0
be written by software to be able to clear it.
15.2.20 FLOW_CTLR_FLOW_DBG_CNT1_0
VALUE: Activity count value (updated by hardware based on CNT1_SEL). This register can
31:0 0x0
be written by software to be able to clear it.
15.2.21 FLOW_CTLR_FLOW_DBG_QUAL_0
Offset: 0x50 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxx0000xxx00000xxx00000xxx00000)
27:24 0x0 AXICIF_CG_DIS: CCPLEX AXICIF/MCCIF clock gating disable.
20:16 0x0 PWRUPREQ_QUAL: CPU DBGPWRUPREQ qualifier.
12:8 0x0 NOPWRDWN_QUAL: CPU DBGNOPPWRDN qualifier.
4:0 0x0 PWRDNREQ_QUAL: CPU DBGPWRDNREQ qualifier.
15.2.22 FLOW_CTLR_FLOW_CTLR_SPARE_0
Offset: 0x54 │ Read/Write: R/W │ Reset: 0xffff0000 (0b11111111111111110000000000000000)
31:16 0xffff SPARE_HI
15:0 0x0 SPARE_LO
15.2.23 FLOW_CTLR_RAM_REPAIR_CLUSTER1_0
Offset: 0x58 | Read/Write: R/W | Reset: 0x00XX000X (0bxxxxxxxxxxxxxxxx00000000xxxx0xx0)
DBG_STS: Repair done (acknowledge) from repair logic. There is one segment. Bits 23:17 are
unused. Reads to these bits will always return 0s.
23:16 RO X Bits 23:18: unused
Bit 17 - sl2
Bit 16 - scpu
DBG_REQ: Repair request for individual segments. There is one segment. Bits 15:9 are unused.
Reads to these bits will always return 0s
15:8 RW 0x0 Bits 15:10: unused
Bit 9 - sl2
Bit 8 - scpu

Flow Controller
DBG_EN: Debug enable to be able to repair of individual segments of the cluster0 repair chain
1 = ENABLE
STS: Indicates Cluster repair chain status. Hardware sets this to '1' when repair of all segments is
1 RO X
done. Hardware clears this to '0' when RAM repair is requested
REQ: Cluster1 RAM repair request. Software sets this bit to '1' to initiate RAM repair request to all
segments in parallel. Hardware clears this bit when software-triggered repair is done (i.e., STS=1)
0 RW 0x0
0 = DISABLE
1 = ENABLE

16.0 MEMORY CONTROLLER

®
Tegra K1 devices feature a hybrid 2x32-bit / 1x64-bit memory controller. These are interleaved to provide high performance
with the load shared across both channels.
The Tegra K1 memory controller (MC) handles memory requests from internal clients and arbitrates among them to allocate
memory bandwidth for DDR3L and LPDDR3 SDRAMs.
The Tegra K1 memory controller (MC) handles memory requests from internal clients and arbitrates among them to allocate
memory bandwidth for DDR3L and LPDDR3 SDRAMs. The external memory controller (EMC) communicates with external
DDR3L and LPDDR3 devices.
Key features in the Tegra K1 memory controller include:
 Enhanced arbiter design for higher memory efficiency

 System Memory Management Unit (SMMU)/Translation Unit (TU) for virtual to physical address mapping for any
device
 Support for low-voltage DDR3 and LPDDR3 SDRAMs
 8 burst transfers per transaction (BL8)
 Support for two DRAM ranks of unequal device densities
 Operates in either single x32 or single x64 configuration
 Variable transaction sizes based on the requests from the clients (one 64-byte transaction with variable dimensions,
two 32-byte transactions with variable dimensions, etc.)
 x32 sub-partitions support for x64 configuration: additional address bits allow targeting different columns of each sub-
partition
 QUSE functionality for qualification of the tristatable DQS clock in SDRAMs
The memory interface speed varies with memory type and the specific Tegra K1 SKU, so is not stated in this document.
16.1 Memory Controller Architecture

The memory controller architecturally consists of the following parts:
 Arbitration Domains (ADs), which can handle a single request or response per clock from a group of clients. Typically,
a system has a single Arbitration Domain, but an implementation may divide the client space into multiple Arbitration
Domains to increase the effective system bandwidth. Multiple Traffic Classes within a single Arbitration Domain and
Protocol Arbiter are allowed.
 Protocol Arbiters (PAs), which manage a related pool of memory devices. A system may have a single Protocol
Arbiter or multiple Protocol Arbiters.
 Memory Crossbar, which routes request and responses between Arbitration Domains and Protocol Arbiters. In the
simplest version of the system, the Memory Crossbar is just a pass through between a single Arbitration Domain and
a single Protocol Arbiter.
 Global Resources, which include entities such as configuration registers which are shared across the Memory
Subsystem.
 Write CAMs (WCAMs), which improves performance and throughput for PCIe ordered clients (PCIe, SATA, HDA, and
USB3), CPU writes, and CPU copies.
 Memory Controller Client Interface (MCCIF), which provides a standardized interface for access to the Memory
Controller.
 Translation Unit, which handles virtual-to-physical address translation, aperture decode, physical address security
checks, and protocol arbiter-specific decodes (such as external DRAM address decodes).

Memory Controller
The Tegra K1 device supports a single physical channel of memory interface, which operates in either single 1x32 or hybrid
2x32 / 1x64 configurations. There is an alternate path through the memory controller to access IRAM via AHB re-direction.
Figure 29 below is a simplified view of how memory requests are arbitrated in the Tegra K1 MSS. Memory client requests are
first arbitrated through a sequence of ring arbiters which perform a type of round-robin arbitration. There are three ring arbiters
referred to as ring0, ring1, and ring2. Ring1 arbiter clients are the ISO clients (display and camera) and the winner of the ring2
arbiter. Each ring has a rate control mechanism referred to as Priority Tier Snap Arbiter (PTSA). The client’s bandwidth
guarantee is specified by the PTSA rate (also referred to as “DDA”).
The block labelled “Row Sorter” is a pending request buffer (it sorts requests by the DRAM row that it refers to). This row
sorter is made up of many “bank queues” which hold the requests made to the same DRAM bank/row. The number of
requests pending in the row sorter can affect whether ring1 or ring2 arbiters are throttled (slowed down) based on thresholds.
Figure 29: Memory Request Arbitration
Memory Controller
Memory Requestor Ring1 and
Ring2
Memory Requestor Arbiters
SMMU
CPU Reads Ring0 Arbiter
Row Sorter
External MC
32 32
DRAM DRAM

16.2.1 DRAM Protocol Arbiter Features
 Hybrid 2x32-bit / 1x64-bit data bus
- 4 chip selects
- 4 individually controllable clock-enables
- 4 individually controllable ODTs (DDR3L)
- Operates in either single x32 or hybrid 2x32 / 1x64 configuration
- Supports per-byte data masks
 Each chip select may support different sizes and geometries
Memory Controller
- Size of Rank 0 must be larger than or equal to Rank 1

- 2 or 3 bank bits
- Column width: 9 to 12 bits
- Row width: 12 to 16 bits
 Per-byte data masks
 Support for BL8
 Data transfer minimization:
- DDR3 burst chop support
 Discrete LPDDR3 and DDR3 devices up to 933 MHz
 Support for 1T and 2T
 Support for low-power modes:
- Software controllable entry/exit from: self-refresh, power down, deep power down
- Hardware dynamic entry/exit from: power-down, self-refresh
- Support for intermittent or disabled DLL
- Disable unused address/command taps based on whether in POP or Discrete mode.
- Pads use DPD mode during idle periods
 For Tegra K1 devices, trims can be set/adjusted per-byte AND per-chip-select. The PVT-compensated value can still
be used and a PVT/frequency-compensated adjustment can be added to it (1/16, 1/8, 3/16 of a cycle) or a non-PVT-
offset can be added.
 Support for x32, x16, or x8 chips attached to the channel
- DQ/DQS swizzling: MRR_BYTESEL need to match byte swizzling.
 Deadline-based arbitration with a latency allowance that can be specified per-client, and under some circumstances,
dynamically adjusted for a given client.
16.2.2 Memory Crossbar

The Memory Crossbar (MXB) is in charge of adapting Arbitration Domains (ADs) to Protocol Arbiters (PAs). In the simplest
system with a single AD and PA running off of a single clock, the MXB is a simple pass-through or does not exist. The Tegra
K1 MXB has one AD and two PAs, one for DRAM and the other for requests redirected to the AHB. The MXB handles conflict
arbitration between responses from multiple PAs to the same AD.
16.2.3 Memory Sub-Partitions

The Tegra K1 Memory Controller implements sub-partitions. The 64B memory atom is divided into two sectors: one sector
containing bytes 0 to 31 and the other containing bytes 32 to 63. Each sector is stored in one of the two DRAM channels. With
three additional column address bits for the second sector, clients can make 64B requests of different shapes while retaining
the bandwidth and power efficiency of a 64B memory atom. This feature also allows the CPU to request that one of the two
32B sectors in a 64B atom be returned first.
The sub-partition mechanism is used by the GPU, display clients (for rotation), VIC (for rotation), MSENC (in x,y flip mode),
and the CPU (for critical-word-first). Clients that choose not to use the sub-partition feature set the extra column address bits
to the same values as the other channel. They see the DRAM as a simple 64B memory system. The sub-partition feature is
only beneficial in systems with a 64b memory. In systems with 32b memory, client addressing and request granularity are
unchanged, but the MC treats each 32B sector as an independent 32B atom.
See the “Sub-Partitions” subsection for more information.

Memory Controller
16.2.4 Global Resources

The Memory Subsystem also contains some global resources not owned by a particular AD or PA:
 A combined SMMU/TU
 Configuration registers and statistics counters
16.2.5 Supported Page Sizes

The MSS considers the following uses of pages and page size:
 DRAM page sizes from 1KB to 4KB.

 OS page: 4KB for all operating systems
 Row Sorter page: 1KB
16.3 Software Features

The majority of software interaction with the memory subsystem involves:
 Initial configuration
 Power management
 Device management
 Translation management
 ISO client bandwidth allocation
 Statistics and debugging
16.3.1 Initial Configuration

The details for configuring the Memory Subsystem (MSS) can be broken down into the following:
 Global Memory Subsystem configuration

 Arbitration Domain configuration
 Protocol Arbiter configuration
 Client configuration
Note: This configuration must be performed as part of the chip-wide boot sequence
16.3.1.1 Global Memory Subsystem Configuration

Some parts of the Memory Subsystem must be configured before any transfers are allowed into the system. The address map
must be configured to set which portions of the physical address map are allocated to which Protocol Arbiters, and what
portions of it are protected by the physical address protection mechanisms.
The Arbitration Domains operate off of a unified arbitration clock. This clock is further divided-down to produce a clock-rate
independent clock for counting latency intervals across the Memory System (also known as “ticks”). This divide-down should
be programmed to a constant interval at initialization (and any other clock-rate change). A 30 ns interval is suggested since it
is an even divide-down of many common DRAM clocks, but any convenient granularity may be chosen.
There are several global memory system tuning options that tend to shape the memory performance. Some of these can be
set statically, at initialization time, others depend on clock frequencies. For example, with SMMU configuration, the SMMU
requires software to set up and maintain page tables in memory, enable translation for clients, and assign clients to address
space identifiers.

Memory Controller
16.3.1.2 Arbitration Domain Configuration

Physical implementation decisions (such as the mapping of clients to partition clients) and default client bandwidth allocations
require configuration options in the Arbitration Domain.
16.3.1.3 Protocol Arbiter Configuration

Each Protocol Arbiter has its own requirements for initialization. Timing parameters specific to the Arbiter, the DRAM and the
current operating clock speed have to be written into Protocol Arbiter configuration registers. The type and geometry of the
attached DRAM also have to be programmed. Afterwards, the DRAM will require a set of initialization cycles to be issued.
Device/Rank Geometry
DRAM devices come in many sizes, widths, etc. The arbiter must be programmed to drive the correct combination of address
bits, data bits, and protocol.
Device Timing and Arbiter Timing

A DRAM arbiter has configuration related to timing parameters specific to the attached device. The JEDEC timing
specifications for the device have to be converted from nanoseconds to cycle counts. The controller must also be programmed
with the cycles per tick number for their particular clock domain (see also the subsection on “Global Memory Subsystem
Configuration” below).
Other Arbiter Parameters

Other parameters related to arbitration that need to be configured include:
 overall number of requests outstanding

 which clients are considered isochronous
 which clients participate in power-saving hysteresis operations
Device/Rank Initialization and Calibration Cycles

In particular, PAs need to write registers in the DRAM devices via special cycles to initialize the DRAM. In general all special
cycles to a device are done via a hardware/software handshake that looks like:
 Software writes information about the special cycle to an Arbiter-specific register

 The Controller does the special cycle out to the DRAM device(s) when timing requirements are met
 Software checks a status register to ensure the special cycle is complete; or for Mode Register Read operations, the
Controller issues an interrupt to indicate that the special cycle has been consumed
Special cycles may be emitted during normal operation as well; the Arbiter will inject them into the data stream at the
appropriate places (typically along with refresh cycles).
During device initialization, software must ensure that no client can access the memory. This can be done with per-module
flush-enable bits.
16.3.1.4 Client Configuration

The Priority Tier Snap Arbiters normally are configured dynamically to provide bandwidth guarantees to ISO clients. However,
for certain clients the PTSA settings are programmed statically (for example, when the PTSA is used as a timeout). For these
clients, the PTSA settings are part of the initial configuration.
Latency allowance may also be configured dynamically for certain clients. Latency allowance should be programmed to
default values during initial configuration.

Memory Controller
16.3.2 Power Management

The primary forms of system power management involve transition to and from low-power DRAM states and management of
clock frequency.
16.3.2.1 Low-Power States

The DRAM controller and DRAMs can operate in a number of low-power states. The controller can be programmed to
automatically enter a precharge power-down or self-refresh state after some amount of time without a request. The power-
down state can be independently entered for each individual DRAM device/rank – it is possible for one device/rank to be in
power-down while another is active. If software knows that the system will not be making further DRAM requests, it can cause
an immediate transfer to the self-refresh state by writing an override register. If multiple chip selects are available for the
DRAM controller, both the hardware and software may choose to enter low-power states on a per-chip-select basis.
Once a request is queued to the controller for that DRAM, the hardware will automatically wake from the low-power state if it
entered that state via hardware control. This can take a relatively long amount of time since the controller may be required to
issue a number of refresh cycles first. For software-initiated self-refresh, software must issue a register write to start the
transition from self-refresh back to a fully-powered state.
Deep power-down must be explicitly requested by software, since it causes DRAM data to be lost. Software must disable new
incoming requests to the MSS, wait for all outstanding in-flight requests to retire, and then write a register to transition to the
deep power-down state. To exit the state, software must reinitialize the DRAM and controller before re-enabling transfers.
Deep power-down mode may be enabled for each chip-select in a Protocol Arbiter independently and each Protocol Arbiter
independently.
Normal active bank power optimization is managed principally by the Protocol Arbiter. The arbiter will arrange to close banks
as soon as possible and to hold requests for as long as the latency timer will allow, with the intent of grouping same-page
accesses into a coherent burst.
16.3.2.2 Request Dribble

The “OSIdle” use cases (with or without display active) are important cases of active power management. Display and audio
clients can be prone to “dribbling”, that is, sending isolated requests at infrequent intervals.
There are two main causes of dribbling:
 Isochronous dribble, caused by a low periodic request rate. This can be (and should be) managed in the Display
client by using hysteresis (high and low watermarks) on the request buffer to group requests into bursts.
 Clock crossing dribble, which is caused by a large disparity between the client clock and the Arbitration Domain clock.
If the client’s clock is slow (which it often is for Display), individual requests will have several idle cycles between
each request. In general, this is unavoidable by the client.
It is difficult for the Protocol Arbiter to handle the second type of dribble when it is under load, because it cannot “see” a large
enough window of requests to group the traffic efficiently. Low-data-rate isochronous clients should have client-side request
hysteresis to handle isochronous dribble. The Protocol Arbiter can handle clock-crossing dribble when it is under load,
because the delays are smaller and it will schedule other traffic preferentially while waiting for the dribbling traffic to
accumulate. When in the OSIdle use case, the Protocol Arbiter will not have enough traffic to keep the client dribble from
becoming DRAM dribble (isolated requests that open and close the DRAM pages more often than necessary).
To manage DRAM dribble, the controller adds the concept of the “hysteresis hold-off” (also known as iso holdoff), which is a
per-controller state bit. When the hold-off is active, the controller is held off from issuing activate commands to open new
DRAM pages. Incoming requests will back up in the Protocol Arbiter’s row sorter and store buffer until the hold-off is released.
The hold-off is enabled whenever an individual device goes idle due to lack of work. It is released automatically whenever a
latency timer expires, or the Protocol Arbiter stalls due to fullness. The net effect of the hold-off is to group all requests for the
DRAM into activity bursts.

Memory Controller
The hold-off causes a delay in requests transitioning from a memory-idle state. This can affect some traffic in a negative
manner – principally requests that are low-latency like the CPU. To keep the hold-off from impacting these requests, software
has a per-module configuration bit that disables the hold-off for certain known-latency-sensitive clients. Whenever a request
with the holdoff-disable bit set enters the Protocol Arbiter, the hold-off is released. The holdoff is enabled whenever an
individual device/rank goes idle due to lack of pending requests. The holdoff is released automatically whenever a request
expires, the Protocol Arbiter stalls due to fullness, a request from a non-hysteresis client is received, or the bank-queue length
reaches a programmable threshold. The net effect of the holdoff is to group requests for the DRAM into activity bursts.
16.3.2.3 Clock Frequency Scaling

A final aspect of power management is scaling the Memory System clocks. In principle, there are two sets of clocks that can
be controlled:
 The Memory System “arbitration clock”, which is the clock used by the Arbitration Domains. Changing this clock
reduces the overall bandwidth of the system and reduces the power required by the client interfaces and cross-chip
Memory System routing.
 Individual Protocol Arbiter clocks. These reduce the bandwidth available to a particular memory pool and reduce the
power consumed by the external pins and the external DRAM. Some Protocol Arbiters may be synchronous to the
arbitration clock and not be explicitly controllable via a separate clock enable.
Tegra K1 devices have a single clock domain for the Arbitration Domain and the Protocol Arbiter: mcclk. The command
controller runs on a second clock called emcclk, which matches the frequency of the command bus on the DRAMs. Mcclk can
be configured to run at 1x, 1/2x, or 1/4x of emcclk. Mcclk and emcclk are phase-aligned.
Both clocks may be changed as part of frequency scaling. Changing the arbitration clock rate affects the Arbitration Domain’s
idea of the latency timeout. Software should change the divide-down register to keep the scale of latency timeout “ticks” to a
(relatively) constant time unit. Generally a tick time of 30 ns is used since it divides evenly into most of the common DRAM
frequencies, but any value of tick granularity may be chosen.
Both the arbitration clock and memory clock have separate divide-downs.
Changing the Protocol Arbiter clock rate affects the relative memory timing parameters. The DRAM timing parameters are
double-buffered to allow software to update the timing values for the next clock speed setting and then simultaneously switch
to using the new values by writing a trigger.
The DRAM protocol itself may require further clock-change restrictions. For example, DDR3 requires a certain number of
cycles in which to re-lock the on-DRAM DLL. To further facilitate the hardware/software handoff and reduce latency for the
clock-change operation, a hardware handshake exists between the clock controller module and the Protocol Arbiter.
The MSS maintains two copies of each configuration register that may need to change due to a clock-change, the “active” and
“assembly” copies; this is also known as a “shadowed” register. The active copy is what the MSS is currently configured to
use, and cannot be written to. The assembly copy can be written to at any time, and it can be copied onto the active via a
trigger mechanism. The clock-change handshake includes a hardware-initiated trigger for this shadow update.
To assist in full-system power analysis using silicon, the Protocol Arbiter should include enough statistics about the DRAM bus
cycles to be able to calculate the DRAM power consumed.
16.3.3 Device Management

The EMC is primarily responsible for DRAM device management (ZQCAL, thermal management, etc.).
The exception to this is that the MC schedules refresh commands to the DRAM.

Memory Controller
16.3.4 Translation Management

Surface allocation for most Tegra K1 clients is straightforward: software allocates the surface out of the device’s virtual space,
and then backs the mappings with physical pages. The mapping between virtual and physical addresses is described using
PTE and PDEs in the SMMU’s page table.
GPU surfaces have their own virtual address space that is translated by the GMMU within the GPU. The GMMU either
translates requests into physical addresses that bypass the SMMU or into a second virtual address space that is then
translated into physical addresses by the SMMU.
16.3.5 Statistics and Debugging

Statistics are used for performance monitoring and for generating usage information for guiding dynamic voltage and
frequency scaling. Hardware will provide a set of statistics counters that are used for DVFS, both for global MSS bandwidth
and for individual PA bandwidth. A separate set of counters with additional filtering support will be available for performance
monitoring and debugging.
The hardware blocks illegal transfers to memory. Some transfers are based on physical DRAM limitations (addressing outside
of the address map), permissions (addressing “secure” physical memory from a non-secure client) and from the SMMU
(accessing an unmapped page). All of these are reported via a fault interface which records the transfer information of the last
faulting address, including the following data:
 Virtual address of fault

 Module and client ID of fault
 Fault type
Faulting transfers continue through the system, but faulting reads return all-ones and faulting writes discard the write data.
Writing a fault triggers a (maskable) interrupt.
16.3.6 Coherency and Ordering

For coherence and ordering:
1. The MSS does not guarantee the coherency between different clients if the write-response tag has not been provided
back to the clients.
2. The MSS guarantees that if a write is sent with a write-response tag and that tag is returned to the client, no other
read or write issued after the response is received from anywhere in the system can pass that write.
3. The MSS guarantees that within a single client, write responses will complete in-order.
4. For PCIe ordered clients, the MSS guarantees that all writes will complete in-order.
For the most part, the memory system is fire-and-forget. Software however needs to be involved in the configuration,
translation, and power management services as described above.
16.4 Software Interfaces

The primary software interface for configuration is via the APB bus registers.
 Initial configuration
 Power management
 Device/rank management
 Translation management
 ISO client bandwidth allocation (per use case)
 Statistics and debugging

Memory Controller
16.4.1 Boot
Tegra K1 devices have a two-stage boot:
 The Boot ROM is responsible for getting the chip out of reset to where driver-level software can take over.
 The Boot Loader or the OS-recovery code is the portion of the driver responsible for completing the boot process to
the general-purpose OS.
The Boot ROM is an actual ROM built into the chip, and the Boot Loader and OS recovery section are externally loaded code.
The Boot Loader is only used for Cold boot; Warm boot utilizes operating-system recovery code.
Tegra K1 devices can “boot” in two ways: “Warm boot” or “Cold boot”. Cold boot is defined as booting from a fully powered-off
or fully reset state. Warm boot is defined as recovery from the lowest-power state (LP0), where the external DRAM has been
held in self-refresh mode while the Tegra K1 core was powered off. Warm boot use case occurs much more often; for
example, it is the use case hit whenever a SmartPhone wakes from Standby to answer a call.
16.4.1.1 IRAM Use

Tegra K1 device contain a protocol arbiter for accessing IRAM (ARC). This path is used only during boot.
The use of this path does not require the SMMU to be set as the IRAM addresses are expected to be physical addresses. The
MC redirects requests to IRAM before the SMMU translation.
This is an additional step in the boot process for these scenarios. ARC_CLK_OVR_ON must be enabled to use the ARC path.
Once all IRAM accesses are done for boot, ARC_CLK_OVR_ON should be disabled.
16.4.1.2 Cold Boot

Before Memory Subsystem boot can begin, the Boot ROM must read the Boot Configuration Tables (BCTs) from flash
memory (slow storage) into on-chip RAM. These tables include the configuration data for up to 4 initial DRAM configurations
supported. The Boot ROM then reads the strap signals assigned to the SDRAM and begins to bring up the memory
subsystem.
The Cold boot Boot ROM sequence:
1. Fetch the BCT values from the storage device and move them to IRAM using AHB redirection.
2. Configure the PLL used by the MC/EMC based on BCT values
3. Wait for PLLs to lock
4. Program necessary always-on static pad configurations in the PMC
5. Configure memory clocks based on BCT values
6. Enable the MC/EMC clocks
7. Release memory subsystem resets
8. Program other necessary pad/pad-macro configuration
9. Program initial configuration for the MC/EMC based on BCT values
10. Perform the DRAM initialization sequence. This sequence is specific to the DRAM protocol used and varies
depending on the requirements of a particular device. For example, a DDR3 sequence goes as follows:
a. Apply power to the device
b. Wait until voltage is stable
c. Assert DRAM reset
d. Wait 200 μs
e. Deassert DRAM reset
f. Apply stable clocks

Memory Controller
g. Wait 500 μs
h. Assert and hold CKE high
i. Precharge all banks
j. Send 2 Auto-refresh commands
k. Write to Mode register 0, 1, 2, 3
l. Issue ZQ Calibration command
m. Wait for ZQ calibration and DRAM DLL lock time to complete
11. Enable power-saving features such as clock stop, active power down, dynamic-self-refresh
12. Start periodic sequences such as auto refresh, ZQ calibration, auto-calibration
1
13. Release the memory-initialization hardware lock
After this, the external DRAM and Memory Subsystem are ready for use.
16.4.1.3 Warm Boot

The Warm Boot sequence is very similar to the Cold Boot sequence; many of the same steps are performed. One difference is
that instead of powering on the DRAM, it is awakened out of SelfRefresh. Another difference is the configuration data for Boot
ROM portion of MC/EMC initialization is stored in the Power Management Controller (PMC) Scratch registers.
The PMC Scratch registers are in the Always-On partition, and are powered during LP0. The power and area limitations of this
implementation restricts the number of PMC Scratch registers available; there are a smaller number of PMC Scratch Registers
than the number of bits needed to fully configure the MC and EMC. The Scratch Registers are only used to store the minimum
required configuration to get to working DRAM. The Boot ROM may not be able to Warm boot to full POR speed using only the
Scratch Register data; if this limitation is confirmed, the Boot Loader may be required to mimic DVFS software and reprogram
the MC/EMC to full-speed operation using data stored in DRAM. It is up to the LP0 Entry software code to ensure the proper
configuration gets written to the Scratch Registers.
The Warm boot code provided by the MSS includes algorithms for deriving the approximate MC arbiter performance
parameters from the EMC timing parameters. The EMC has provided generation code for the packing/unpacking calls for the
scratch registers to ease the software maintenance burden.
The Warm boot Boot ROM sequence:
1. Configure memory PLLs and memory clocks based on Scratch values

2. Wait for PLLs to lock
3. Configure memory clocks based on scratch values
4. Enable the MC/EMC clocks
5. Release memory subsystem resets. Program any necessary static pad configuration that was powered-off in LP0
6. Program any necessary static pad configuration that was powered-off in LP0.
7. Program initial configuration for the MC/EMC based on Scratch values
8. Release the DRAM from software-controlled Self Refresh. This sequence is specific to the DRAM protocol used and
may further vary depending on the requirements of a particular device. For example, a DDR3 sequence goes as
follows:
a. Apply stable clocks
b. Assert and hold CKE high
c. Issue ZQ Calibration command
1
AHB_ARBITRATION_XBAR_CTRL.MEM_INIT_DONE

Memory Controller
d. Wait for ZQ calibration and DRAM DLL lock time to complete

e. Write to Mode registers if different from LP0 entry values
f. Issue refreshes to ensure tREFI is satisfied
9. Enable power saving features such as clock stop, active power down, dynamic-self-refresh
10. Start periodic sequences such as auto refresh, ZQ calibration, auto-calibration
11. Release the memory-initialization hardware lock
After the Boot ROM sequence is complete, the operating system restore code may access DRAM and restore a different or
higher-speed operation. The operating system may also restore translation or client configuration settings before allowing any
user code to execute.
16.4.2 Security Apertures

To secure the MC registers, the CPU complex’s page table entries for the MC register space must be marked as secured.
Then to access the registers securely, the CPU must be switched into secure mode. For more details about these CPU
operations, please read the appropriate ARM Architecture Reference Manual.
To secure a region of EMEM, the page table entries for that region must be marked as secured. Then the MC registers must
be configured for the secured region, using the CPU in the secured mode:
RegWrite(MC_SECURITY_CFG0, security_aperture_base_address);
RegWrite(MC_SECURITY_CFG1, security_aperture_size_in_megabytes);
After the registers are updated, the CPU must be in secure mode to access the described region of memory:
 Video Protection region

 Security Coprocessor Secure region
For more information on handling security violations, see the subsection “MC Interrupts” below.
16.4.3 Software Client-Groupings

The Memory Subsystem inherently implements a hardware mapping of memory clients (“MCCIFs”) to super-clients, and
super-clients to the hardware modules. Additionally, the MSS implements a system of mapping modules to “software groups”
(also known as SWGROUP or SWNAME). This allows a single point of control for all clients for that hardware “engine”. Often
the list of clients in a SWGROUP is the same as the list of clients in the module that implements the hardware engine.
Each SWGROUP has registers associated with it that select an ASID (Address Space Identifier) and determine whether
SMMU translation is enabled or disabled for the client. Normally, each client is associated with one SWGROUP, thus has one
ASID associated with it. A few clients have multiple SWGROUPs associated with them, which are selectable on a transaction-
by-transaction basis via a 1- or 2-bit SWID flag provided by the client.
The mapping of SWGROUP to modules for Tegra K1 devices is listed in the following table.
SWGROUP Modules Translatable? Further Description
AFI PCIE Yes PCIExpress
AVPC AVP Cache Yes ARM7 Audio-Video Processor (AVP)

(1)
DC Display head 0 Yes Display reads, head 0, with dis2mc_swid=1’b0
Display head 0, Display reads, head 0, with dis2mc_swid=1’b1 (TZ-Display

DC1 Yes(1)
secure client window)
DCB Display head 1 Yes Display reads, head 1 (dis2mc_swid=don’t care)

(2)
GPU GPU No Kepler GPU with a[34]==0

Memory Controller
SWGROUP Modules Translatable? Further Description

(2)
GPUB GPU Yes Kepler GPU with a[34]==1
HC Host1x Yes Host interface
HDA HDA Yes High-Definition Audio engine
ISP2 ISP2 Yes Image Signal Processor
ISP2B ISP2 Yes Image Signal Processor (second instance)
MPCORE AXICIF No CPU Complex
MPCORELP AXICIF_LP No Shadow CPU Complex (Tegra K1 32-bit devices only)
MSENC MSENC Yes Multi Standard Video Encoder
AHBDMA,
PPCS No(3) Clients in the AHB cluster, with ppcs2mc_swid = 2’b00
AHBSLV
AHBDMA,
PPCS1 Yes Same as PPCS, with ppcs2mc_swid = 2’b01
AHBSLV
AHBDMA,
PPCS2 Yes(1) Same as PPCS, with ppcs2mc_swid = 2’b10
AHBSLV
PTC MC (SMMU) N/A Misses from SMMU PTC
SATA SATA Yes Serial ATA
SDMMC1A SDMMC1 Yes
SDMMC2A SDMMC2 Yes SDMMC controller. Each SDMMC controller has a unique use
case and can be run via standard (Windows/Android) or NVIDIA
SDMMC3A SDMMC3 Yes drivers, hence each controller has its own (hardcoded) SWID.
SDMMC4A SDMMC4 Yes
TSEC TSEC Yes Tegra Security coprocessor
VDE VDE Yes Video Decode Engine
VI VI Yes Video Input engine for CSI, VIP
VIC VIC Yes Video Compositor
XUSB_HOST USB3 Host Yes Although the same driver is expected to control both units, each
has its own SWNAME to maintain compatibility with the Tegra 4
XUSB_DEV USB3 device Yes device.
16. The MC defines the ASID mapping on a per software-ID (SWGROUP) basis. To support secure ASID for the SE
engine (in the AHB cluster) and TZ-Display, additional SWID signals are added to the interfaces. The additional SWID
signal allows the MC to map the client to different SWIDs, providing flexibility to use a secure ASID for the SMMU.
17. Although the GPU has one physical read client and one physical write client, it can specify one of two SWGROUPs
(GPU and GPUB) for a given request, depending on the value of address bit a[34]. LTCX maps a[34] to the MCCIF
SWID field. SMMU translation is disabled for SWGROUP GPU and enabled for GPUB. This is how the GPU indicates
whether SMMU translation is needed. The MC also performs special video protection region checks for the GPUB.
18. To support the CPU’s view of 4GB memory, part of the 0-2G memory address space is used by the CPU to address
DRAM. The devices which were previously making requests in the 0-2G address range, assuming that they would be
always mapped to other memory space by SMMU, now overlap with devices making physical address requests in the
0-2G range. An additional bit ppcs2mc_swid indicates which requests need to remain untranslated and which requests
need SMMU translation. This additional bit selects between the two SWIDs (for AHB clients). These two SWIDs map to
two separate ASIDs, where one indicates SMMU translation and the other indicates no translation.
16.4.4 Virtual Addressing: Using the SMMU

For a discussion of the virtual-address translation features provided by the SMMU, read Section 16.5.1 on “Virtual
Addressing” below.
In Tegra K1 devices, the CPU has its own MMU and issues physical addresses to the MSS. Thus it is not possible to enable
SMMU translation for the CPU.
Memory Controller
16.4.4.1 SMMU Initialization

1. For each Virtual Address Space (VAS) to be used, set up the page table in the DRAM. See the subsection on “Virtual
Addressing” below for details on the page-table formats supported.
2. For each ASID, set up the pointer to the page-table base and the ASID-wide protection bits. Since the PTB pointers
are stored in a RAM, this uses an indirect access mechanism involving two register writes:
a. Write MC_SMMU_PTB_ASID_0 with the ASID to be modified.
b. Write MC_SMMU_PTB_DATA_0 with the information for this VAS:
o Page Table Base pointer
o Whether non-secure accesses are allowed
o Whether reads are allowed
o Whether writes are allowed
3. Assign hardware engines (SWNAMES) to the ASIDs and turn on translation for those engines. This involves writes to
various MC_SMMU_<SWNAME>_ASID_0 registers.
4. If needed for Hardware Diagnostics purposes, disable or enable translation within a SWNAME on a per-client basis.
This involves writes to various bits in MC_SMMU_TRANSLATION_ENABLE_*_0 registers.
5. If desired, secure the ASIDs, which prevents untrusted code from modifying the ASID PTB pointers by enabling a
requirement for TrustZone security on register writes that modify the PTBs. This operation involves a write to
MC_SMMU_ASID_SECURITY_0. Note that this register itself is secured by TrustZone to prevent it from being
modified by untrusted sources, and in some situations writes to it must also be TrustZone secured for them to take
effect. In particular, you cannot change a module’s ASID with a non-secure write if you are trying to change it to a
secure ASID, or if it is already a secure ASID.
6. If desired, enable ASID promotion, which allows clients without security access to inherit the security status based on
the page-table translation. This operation involves a write to MC_SMMU_ASID_SECURITY_0.
7. Write PTC_FLUSH_TYPE=ALL to MC_SMMU_PTC_FLUSH_0.
8. Write TLB_FLUSH_VA_MATCH=ALL to MC_SMMU_TLB_FLUSH_0.
9. Configure reserved bits found to be necessary during chip bring-up, if any. There are reserved bits in
MC_SMMU_PTC_CONFIG_0 and MC_SMMU_TLB_CONFIG_0.
10. Enable the SMMU by writing SMMU_ENABLE=ENABLE to MC_SMMU_CONFIG_0. Note that this register is secured
by TrustZone to prevent it from being modified by untrusted sources, and writes to it must also be TrustZone secured
for them to take effect.
The following alternate initialization sequence is used when TrustZone is enabled on Win8, since the UEFI (Boot Loader) is
secure, whereas the SW memory driver (NVMEM) is not:
1. Hardware initializes the MC_SMMU_TRANSLATION_ENABLE_*_0 register to enable translation. This is done by

enabling the bits by default on cold boot (reset) or warm boot (lp0). Note that software depends on this. The
software memory driver cannot configure the MC_SMMU_TRANSLATION_ENABLE_*_0 register, since it is
TrustZone protected.
2. The UEFI sets up the display for SMMU translation: SMMU_ASID_DC = x, SMMU_ASID_DCB = x.
3. Enable the SMMU: SMMU_ENABLE=ENABLE to MC_SMMU_CONFIG_0.
4. Later the software memory driver sets up the rest of the ASIDs: SMMU_ASID_xxx = y (y is a non-secure ASID).
16.4.4.2 Page Table Modifications after Initialization

Modifications may be made to the page tables while the system is operating, however, care must be taken to avoid modifying
an entry that is in active use. Modifying an entry in active use will result in undefined operation; the most likely failure is the use
of an out-of-date cached translation. The general rules for safe modification are:

Memory Controller
 If no client is using an ASID, then that ASID and its page table can be modified.
 If no client is using any PTE in a PDE, that PDE can be modified.
 If no client is using a PTE, that PTE can be modified.
It is up to software to ensure these rules are followed when virtual address translations need changed. Once software has
updated the page-table or ASID mappings, the final step is to perform PTC and TLB invalidates on the modified entries. Note
that the granularity of invalidation is at the PTE group, which is the number of PTEs that fit in a memory atom. Software can
write:
 MC_SMMU_TLB_FLUSH_0 to flush a specific page group, 4MB section, entire ASID or the entire TLB.
 MC_SMMU_PTC_FLUSH_0 to flush a specific PTE or PDE from the PTC
16.4.4.3 Collecting Statistics on SMMU Performance

The TLB and PTC each have hit and miss statistics counters. To enable statistics collection, set
MC_SMMU_*_CONFIG_0.*_STATS_ENABLE == ENABLE, where * stands for PTC or TLB. The counters will begin collecting
information when enabled. To check the results, read the appropriate registers:
- MC_SMMU_STATS_TLB_HIT_COUNT_0
- MC_SMMU_STATS_TLB_MISS_COUNT_0
- MC_SMMU_STATS_PTC_HIT_COUNT_0
- MC_SMMU_STATS_PTC_MISS_COUNT_0
These counters do not saturate when full; instead they wrap from MAX_UINT to 0. There is no explicit reset for these counters;
the only reset-like option is to force the counter bits to all 1’s using the MC_SMMU_*_CONFIG_0.*_STATS_TEST trigger bits.
This is essentially like resetting the counters to -1.
16.4.5 Clock Frequency Management

Software programs the emcclk and mcclk frequencies to provide the required bandwidth and latency while minimizing power.
1. The performance of some devices are highly sensitive to MC clock frequency. Some drivers dynamically specify a
minimum emcclk frequency that meets their needs. Drivers make these requests on behalf of the CPU, AVP , HDMI,
the various USB controllers, GPU, MPE (MSENC), and ACTMON.
2. ISO drivers specify their ISO bandwidth requirements, which imply a minimum emcclk frequency. The ISO manager
(part of IMP) ensures that the bandwidth requested is feasible within system parameters.
3. Thermal throttling dynamically specifies the highest MC clock frequency that should be allowed.
4. The central clock code computes the new EMC/MC frequency as:
MIN( MAX(frequency_requests_from_1), ISO_MBps_to_MHz(sum(bandwidth_requests_from_2)),
frequency_request_from_3 )
16.4.6 DVFS Sequences

DVFS (Dynamic Voltage and Frequency Scaling) is a software feature for controlling system power. A key hardware feature
for supporting that is changing SDRAM frequency on the fly with minimal impact on system performance. That indicates the
following requirements:
 EMC timing parameters and their corresponding MC arbitration timing parameters need to be adjusted to the optimal
performance for the new frequency. These parameters can usually be derived from DRAM datasheet and do not
need characterization.
 All trimmer values need to be adjusted for the new frequency. These values need to be characterized across PVT
(process, voltage, temperature) and frequencies.

Memory Controller
 The pad configurations that can be turned off to save power at low frequencies should also change with frequency
change, such as pad terminations and DQS pulls.
 All registers involved in frequency change should be shadowed. That includes the reserved register fields that can
possible be turned on only in a certain frequency range. Note that any Hardware Diagnostics feature that has power
implications should be considered to be shadowed.
 No software interference should be expected from software after software pulls the trigger to change frequency and
before the clock change completes: Software runs on the CPU from SDRAM. Once the EMC blocks the requests to
SDRAM, the CPU may be frozen until the EMC finishes frequency change and unblocks the requests. Note that the
CPU can also possibly run out of the contents in cache during clock change, so we need to consider both scenarios.
 The delay caused by clock change should not cause functional failures or visible artifacts.
That results in a design as follows:
 The CAR module handshakes with the EMC on clock change. The EMC handshakes with the MC on shadow register
latching. The whole process is done by hardware and transparent to software.
 A rough estimation of clock change delay is 2-6 µs for LPDDR3.
 Supports two clock change mode: self-refresh clock change mode and power-down clock change mode. Both
LPDDR3 and DDR3 support both modes. We recommend clock change power-down mode for LPDDR3 since it takes
shorter time. We recommend self-refresh clock change mode for DDR3, since power-down clock change mode does
not allow DLL to be turned off.
 For flexibility, EMC has a 16-deep FIFO to hold register programming and release them during or immediately after
clock change. That enables us to send DRAM command or latch in unshadowed registers. Here are a few examples:
- Self-refresh clock change mode requires programming EMC_SELF_REF to put DRAM in self-refresh during
clock change.
- DDR3 precharge-power-down mode requires programming EMC_PRE to close all banks before clock change.
- Both DDR3 and LPDDR3 clock change requires writing mode registers after clock change.
- To support DLL-ON/DLL-OFF mode switching on DDR3, program mode registers before or after clock change
according to the DDR3 specification.
This is a summary of the frequency change process:
 Software turns off features like self-refresh or auto-calibration if necessary to minimize their interference with DVFS
sequence.
 Software programs MC/EMC shadow registers for the new frequency.
 Software sets up the appropriate threshold registers in the Display and VI/ISP for *_ready_for_latency_event.
 Software programs EMC clock change flow control registers, such as entering self-refresh before clock change and
programming SDRAM mode registers after clock change.
 Software programs the MC/EMC clock source register to trigger the clock change.
 The CAR sends clock change request to the EMC (clock divider and/or clock source).
 The EMC waits for the iso_ready_for_latency_event signal to be asserted. If and while this signal is deasserted, the
EMC/MC continues normal DRAM operation.
 The EMC stalls all DRAM commands including refreshes.
 The EMC handshakes with the MC to stalls incoming transactions and waits until EMC pipe is flushed
Within handshaking, EMC may enters power down state if it is in power-down clock change mode.
 The EMC executes pre-clock change sequence such as entering self-refresh and programming mode register to turn
off DLL.
 The EMC latches in shadowed registers and requests the MC to latch in shadow registers.
 The EMC acknowledges the CAR to change clock.
Memory Controller
 The CAR changes the MC/EMC clock.

 The CAR deasserts the clock change request to the EMC indicating the clock change is done.
 The EMC executes post-clock-change sequence, such as exiting self-refresh and programming SDRAM mode
registers.
 The EMC deasserts the clock change acknowledgement to the CAR.
 The EMC unstalls DRAM commands including refresh and resumes incoming MC transactions.
 Software waits 1µs before continuing.
Software programming sequence on the Tegra K1 clock change sequence:
 Before any clock change, usually at boot time

- Keep these register fields in reset values:
CLKCHANGE_REQ_ENABLE = ENABLED
CLKCHANGE_SR_ENABLE = DISABLED
- CLKCHANGE_PD_ENABLE:
ENABLED: power-down clock change mode (for LPDDR3)
DISABLED: self-refresh clock change mode (for DDR3)
 At each clock change:
- Disable DSR (dynamic-self-refresh) if it is currently enabled. There are two ways to do this (software can choose
which)
o EMC_DBG.WRITE_MUX = ACTIVE
Read-modify-write: EMC_CFG. DYN_SELF_REF = DISABLE
EMC_DBG.WRITE_MUX = ASSEMBLY
o Read-modify-write: EMC_CFG. DYN_SELF_REF = DISABLE
EMC_TIMING_CONTROL.TIMING_UPDATE = 1
poll for EMC_EMC_STATUS.TIMING_UPDATE_STALLED == 0
- Program shadow registers.
- Program STALL_THEN_EXE_BEFORE_CLKCHANGE = 1
All following EMC register programming will happen after flushing DRAM requests and stalling further DRAM
commands, including auto-refreshes. Note that EMC register reads still will not work from this point until the clock
change is complete: issuing an EMC register read in this duration will hang the system.
- (optional) Program unshadowed EMC registers that need to change with clock change
- (self-refresh clock change mode only, DLL-ON to DLL-OFF mode switching only, DDR3 only)
Program EMC_MRS to disable DLL.
- (self-refresh clock change mode only) Program SELF_REF to enter self-refresh:
SELF_REF.DISABLED = ENABLED
SELF_REF.DEV_SELECTN = depending on DRAM configuration
- Program STALL_THEN_EXE_AFTER_CLKCHANGE = 1
All following EMC register programming will happen after clock change but before unblocking DRAM requests
- (self-refresh clock change mode only) Program SELF_REF to exit self-refresh
SELF_REF.DISABLED = DISABLED
SELF_REF.DEV_SELECTN = depending on DRAM configuration
- Program DRAM mode registers by MRS/EMRS (DDR3) or MRW (LPDDR3) to change CL/WL/TWR etc.
On DLL-OFF to DLL-ON switch on DDR3, DLL is turned on with this step.
- Program UNSTALL_RW_AFTER_CLKCHANGE = 1
All following EMC register programming can happen with on-going traffic after clock change

Memory Controller
- Wait 1 µs to ensure the EMC programming goes through before programming CLK_SOURCE_EMC.
- Program CLK_SOURCE_EMC to change the clock:
EMC_2X_CLK_SRC: MC/EMC clock source
USE_PLLM_UD: use low jitter clock
MC_EMC_SAME_FREQ: drive EMC versus MC clock ratio at 1:1, otherwise 2:1
EMC_2X_CLK_DIVISOR: EMC clock divider
- Wait 1 µs, in case the next clock change starts before the current one completes, which is possible if the
software runs out of cache.
16.4.7 ZQ Calibration Sequence

ZQ calibration is a feature of LPDDR3 and DDR3 to calibrate R on (the output driver) across PVT (process, voltage,
temperature), and also ODT values on DDR3. The EMC supports periodically sending ZQ calibration commands to both
DRAMs, requiring only initial configuration after booting. The EMC also supports one time calibration commands at booting.
For cold booting, the boot ROM does a ZQ-init on LPDDR3 and a ZQ-long on DDR3, and then enables periodic ZQ-short.
For warm booting, boot ROM does ZQ-long on both LPDDR3 and DDR3, and then enables periodic ZQ-short.
Self-refresh exit:
There are three cases:
 Software-controlled self-refresh as part of LP0/LP1. The device may spend an arbitrarily long time in either of these
low-power states, thus could suffer significant drift temperature since the last ZQ calibration. Software must perform
ZQ-long at self-refresh exit.
 Hardware-controlled self-refresh after extended period of idle. The duration should not be long (if the duration were
long, software should have triggered LP1). Normal, timer-initiated ZQ-short should be sufficient.
 Hardware-controlled self-refresh as part of DVFS. The self-refresh duration deliberately is kept small since the DVFS
sequence is as short as possible. There is no need to perform a ZQ calibration within the DVFS sequence itself,
since DRAM voltage is not affected by DVFS. Normal, timer-initiated ZQ-short should be sufficient.
One time calibration:
 LPDDR3, Write MC_MRW:

- MRW_DEV_SELECTN: 2 for device 0, 1 for device 1. Or use 0 for both (not used because software must control
the delays between commands in boot ROM).
- MRW_MA: 10
- MRW_OP: 0xFF for ZQ-init. 0xAB for ZQ-long, 0x56 for ZQ-short
 DDR3: Write EMC_ZQ_CAL
- ZQ_CAL_DEV_SELECTN: 2 for device 0, 1 for device 1. Or use 0 for both (not used because software must
control the delays between commands in boot ROM)
- ZQ_CAL_LENGTH:
SHORT: issue ZQ-short command
LONG: issue ZQ-long command
- ZQ_CAL_CMD: 1
Periodic calibration:
 EMC_ZCAL_INTERVAL: Number of microseconds to wait between periodical ZQ commands. Program this register
to 0 to disable periodic ZQ calibration
 EMC_ZCAL_WAIT_CNT: Number of clocks to wait after each ZQ command before other commands
 EMC_ZCAL_MRW_CMD:
Memory Controller
- ZQ_MRW_DEV_SELECTN
2 for device 0 only, 1 for device 1 only, 0 for both devices
- ZQ_MRW_MA
LPDDR3: 10
DDR3: 0 for ZQ-short, 1 for ZQ-long
- ZQ_MRW_OP
LPDDR3: 0x56 for ZQ-short; 0xAB for ZQ-long
DDR3: 0
16.4.8 MRR Sequence

Mode Register Read (MRR) is desirable on LPDDR3 for reading the manufacturer ID to identify DRAM vendors, or reading
back from the LPDDR3 temperature sensor.
Simple sequence:
 Before any MRR, such as at booting:

- Set MRR_BYTESEL and MRR_BYTESEL_X16 corresponding to data byte sizzling, if applied on board. The
reason is that LPDDR3 always returns MRR at low byte of a data strobe, which is the only case that EMC needs
to know about swizzling.
 For each MRR
- Check EMC_STATUS.MRR_DIVLD = 0. If not true, read EMC_MRR until it becomes true
- Issue MRR:
MRR_MA: the index of the mode register to read back
MRR_DEV_SELECTN: 2 for device 0, 1 for device 1. 0 or 3 are illegal. If both devices are desired, repeat this
sequence on each device.
- Poll for EMC_STATUS.MRR_DIVLD = 1
- Read EMC_MRR. Data is in the MRR.DATA field
16.4.9 Auto-Calibration Sequence

Auto-calibration is for periodically calibrating the output driver of Tegra K1 pads. The EMC supports periodic auto-calibration
without software interference, usually initiated at booting.
To enable auto-calibration:
 Program AUTO_CAL_INTERVAL: the number of microseconds between two auto-calibrations

 Program EMC_AUTO_CAL_CONFIG:
AUTO_CAL_START = 1
AUTO_CAL_ENABLE = 1
AUTO_CAL_OVERRIDE: 1 to enable override, 0 to use normal auto-calibration
AUTO_CAL_PD_OFFSET: override value
AUTO_CAL_PU_OFFSET: override value
AUTO_CAL_E_CAL_UPDATE: number of EMC clocks E_CAL_UPDATE is asserted
AUTO_CAL_STEP: number of microseconds between each calibration step
To disable auto-calibration:
 Program AUTO_CAL_INTERVAL to 0
To re-enable auto-calibration after disabling it:
 Program AUTO_CAL_INTERVAL to the new value

Memory Controller
16.4.10 LP0/LP1 Entry/Exit

LP0 and LP1 are both power saving modes with DRAM in self-refresh mode. The only difference is that the MC and the EMC
are ON during LP1 but powered OFF during LP0.
LP0 and LP1 entry share the same sequence:
 Disable DSR (Dynamic self-refresh) by read-modify-write EMC_CFG. DYN_SELF_REF = DISABLED then program
EMC_TIMING_CONTROL.TIMING_UPDATE = 1 to latch in the shadowed register EMC_CFG
 Wait 5 µs for worst case DSR exit time
 Program EMC_REQ_CTRL to stall all transactions
STALL_ALL_WRITES = 1
STALL_ALL_READS = 1
 Wait until the EMC pipe is flushed
poll EMC_EMC_STATUS.NO_OUTSTANDING_TRANSACTIONS == 1
 Enter self-refresh
EMC_SELF_REF.SELF_REF_CMD = 1
EMC_SELF_REF.SREF_DEV_SELECTN: 2 for device/rank 0 only, 1 for device/rank 1 only, 0 for both
 (optional) Wait until the device/rank is in self-refresh
poll EMC_EMC_STATUS.DRAM_IN_SELF_REFRESH ==
1: dev0/rank0 is in self-refresh; 2: dev1/rank1 is in self-refresh; 3: both devices/ranks are in self-refresh
LP0-exit is also called warm boot. Refer to the “Warm Boot” subsection.
LP1-exit:
 Exit self-refresh
EMC_SELF_REF.SELF_REF_CMD = 0
EMC_SELF_REF.SREF_DEV_SELECTN = 2 for device/rank 0 only, 1 for device/rank 1 only, 0 for both
 poll for self-refresh completes
poll for EMC_EMC_STATUS.DRAM_IN_SELF_REFRESH == 0
 Program EMC_REQ_CTRL to unstall all transactions
STALL_ALL_WRITES = 0
STALL_ALL_READS = 0
 (optional) if it is desired to re-enable DSR (possibly turned off by LP1 entry sequence):Read-modify-write EMC_CFG.
DYN_SELF_REF = ENABLED
EMC_TIMING_CONTROL.TIMING_UPDATE = 1 to latch in shadowed EMC_CFG
16.4.11 Performance Tuning

Note: The capitalization in the below sections refers to the actual register name of the associated
setting.
16.4.11.1 Per Client Knobs

Each client of the MSS has some configuration knobs that affect the behavior of the request in the PA. These knobs are:
 ISOchronous
 HYSTeresis
Most clients set their ISO and HYST bits based on the behavior profile of the client; which is static for all systems. The default
programming should be acceptable for these bits.

Memory Controller
16.4.12 Errors (Interrupts)

Both the MC and the EMC implement a handful of interrupts to inform the software of completed events or error conditions
encountered by the hardware. Both the MC and the EMC have implemented the same style of interrupt interface, so this
section will use the MC as the example.
The interrupt interface for MC consists of two registers and a hardware output wire. The output signal is wired to the central
interrupt handling module on Tegra K1 devices; from there it can be routed to any of the CPU complexes. The first register,
INTSTATUS, contains the interrupt vector for MC. Each bit in this register is set when the hardware detects an interrupt.
Writing a 1 to the interrupt vector bit will clear the associated interrupt. The second register is INTMASK, each bit in this
register corresponds to a vector bit in INTSTATUS. If the MASK bit for an interrupt is clear (MASKED), the corresponding
interrupt will not forward the interrupt to the central interrupt handling module. If any UNMASKED interrupt vector bits are set,
the MC will assert the interrupt to the central interrupt handling module.
16.4.12.1 EMC Interrupts

The EMC generates interrupts on the following conditions:
 DLL alarm: From the EMC Digital DLL when the output delay code reaches the maximum value.
 Attempt to issue a command to a device that is in self-refresh.
 Read data from the MRR is available (to prevent software from polling for data)
 DRAM clock change sequence complete
 Refresh overflow
16.4.12.2 MC Interrupts
The MC contains two classes of interrupts: address decode errors and performance warnings.
When an address decode error occurs, the offending address is captured in the MC_ERR_ADDR register, and information
about the error is captured in one or more MC_ERR_*STATUS registers. The captured information assists developers in
debugging the error.
A single request can trigger multiple errors. There are multiple error status registers (MC_ERR_*STATUS) that capture the
status of different types of errors, as listed below:
 MC_ERR_STATUS – Multiple violations. When more than one of the following violations occurs, the highest-priority
violation is reported (listed below in descending priority order):
- ERR_TYPE = SECURITY_TRUSTZONE – TrustZone carveout violations
- ERR_TYPE = INVALID_SMMU_PAGE – Any SMMU translation violation
Decode error on PDE/PTE (reserved bits non-zero)
Request violates RW, nonsecure PTB/PDE/PTE bit values
- ERR_TYPE = DECERR_EMEM - DRAM minimum/maximum allowed memory addresses
 MC_ERR_SEC_STATUS - All SEC carveout violations
 MC_ERR_MTS_STATUS - All microcode carveout violations
 MC_ERR_VPR_STATUS - All VPR carveout violations
The capture registers record the following information about the error:
 the Virtual or Physical address of the error (depending on the type of fault)
 which type of fault the captured error corresponds to
 a read/write indicator
 the requestor client ID

Memory Controller
 the swap bit sent by the client

 if the error was an INVALID_SMMU_PAGE, then information about the page's protection status is also captured (only
in MC_ERR_STATUS):
- whether the page was marked non secure in the page-table
- whether the page was marked readable in the page-table
- whether the page was marked writeable in the page-table
- Note that SMMU page protection bits are formed by ANDing the page protection bits from the Page Table Base,
PDE, and PTEs from all three stages of the page-walk. The ANDed protection bits and the type of the provoking
transaction are both available in the status register.
Subsequent errors (of any type) will not change the status and address registers until the corresponding interrupt is cleared.
To prevent requests with address decode errors from modifying memory or accessing memory they do not have permission to,
the MC “squashes” the requests. A write request that is “squashed” has had its byte-enables forced to all-zeros, this prevents
the write data from being applied to DRAM. A read request that is “squashed” will have its read-return data forced to all-ones,
this protects the data in DRAM from being read by non-secure sources.
There is one performance warning type interrupt: ARBITRATION_EMEM. It fires when the MC detects that a request has
been pending in the Row Sorter long enough to hit the DEADLOCK_PREVENTION_SLACK_THRESHOLD. In addition to true
performance problems, this interrupt may fire in situations such as clock-change where the EMC backpressures pending traffic
for long periods of time. This interrupt helps developers identify and debug performance issues and configuration issues.
SMMU-Translated Requests and Physical Aperture Errors

All Virtual Addresses are translated through the SMMU, then run through the Physical Aperture checks. There are a number of
confusing scenarios when debugging these interactions including:
 SMMU fault followed by any physical aperture error of any sort: because the SMMU translation occurs first, the data
captured by the ERR_ADR and ERR_STATUS registers will always be the SMMU fault information. Both interrupt
bits are set.
 Decode error on a successfully translated (i.e., no SMMU fault indicated) client request: the PA checks will throw a
decode error; the data captured includes the Physical Address, not the Virtual Address. The client request is
squashed. The decode-error interrupt bit is set.
 Decode error on a Page-Table fetch (PDE or PTE): the page-table fetch will throw a decode error; the data captured
includes the Physical Address of the PDE or PTE, and the client ID corresponds to the PTC. In addition, the data
returned to the PTC is modified to turn off all access permissions, marking the page INVALID. This forces the client
request to also throw a SMMU fault when it is translated. Both the decode-error and SMMU-fault interrupt bits are set.
The PDE or PTE are then cached with those modified access permissions, so any subsequent requests to that virtual
page are also SMMU fault.
 TrustZone security violation on a translated client request: the PA checks throw a security error, the data captured
includes the Physical Address, not the Virtual Address. The security violation interrupt bit is set. The client request is
squashed. This behavior allows the Secure Aperture to stand as a “last line of defense” against SMMU page-table
modification attacks.
 Protected-region security violation on a translated client request: the PA checks throw a security error. The data
captured includes the Physical Address, not the Virtual Address. The security violation interrupt bit is set. However,
the client request is squashed.
 Video Protection-region security violation on a translated client request: the PA checks throw a security error. The
data captured includes the Physical Address, not the Virtual Address. The security violation interrupt bit is set.

Memory Controller
16.5 Functionality
16.5.1 Addressing
The 34-bit physical address space supported by the MC is 16GB. Clients may support larger (e.g. 40-bit) addresses internally,
but address msbs above those connected to the memory controller are assumed to be zero. Clients may use virtual or
physical addresses. If a client uses virtual addresses, the addresses are limited to 32-bits (the input width of the SMMU). The
SMMU outputs 34-bit physical addresses.
16.5.1.1 Address Map and Aperture

Tegra K1 device’s physical address space includes apertures for DRAM, I/O devices, and the AHB redirection region, as
defined in the address map (see the section entitled “Address Map”). The range from 0 to 2GB is designated as the MMIO
region. All non-DRAM devices (including the AHB redirection region) map (sparsely) within the MMIO region. Address
decoders above the MC decode the address ranges for the MMIO devices and intercept requests for the respective devices
before the requests reach the MC.
Requests that reach the MC map to one of the following ranges:
 AHB redirection range between IRAM_BOM and IRAM_TOM

 External memory (DRAM) between EMEM_BOM and EMEM_TOM (maximum of 8 GB)
 Not Assigned range (if the address does not fall in either of the two ranges above)
The AHB redirection path allows MC clients that need to access boot media to access IRAM during boot. See the “AHB
Redirection Region” section for details on the use and programming of the AHB redirection feature. Note that the AHB
redirection range might not map on top of the external memory range, depending on how EMEM_BOM is set.
For accesses that fall within the Not Assigned region, an error is logged, writes are acknowledged and squashed before the
WCAM, and reads return all 1s.
Four additional programmable apertures restrict which devices can access defined regions of DRAM:
 TrustZone region
 Video Protection region
 Security Coprocessor Secure region
 Microcode Carveout Protection region
Each of these may be placed anywhere in the external memory range and have programmable size. For details on these
programmable apertures, see the “TrustZone Security Region”, “Video Protection Memory Region”, and “Security Coprocessor
Secure Region” sections for more information.
In addition, a range of contiguous physical addresses may be designated as “carveout”. Virtual memory pages mapping to
carveout are required to maintain physical contiguity. Carveout is a software-defined region with no hardware aperture
detection.
The following figure shows a possible address map for a Tegra K1 system with 8GB of physical memory. For systems with 32-
bit addressing (e.g., Windows 8 systems), all memory must live below the 4 GB boundary. If 4GB of DRAM is desired, the
external memory range must be configured to map from 0 to 4GB. DRAM is then mapped in the holes in the sparsely
populated MMIO space, providing nearly 4GB of addressable DRAM memory. This is the “Swiss Cheese” approach.

Memory Controller
Figure 30: Physical Address Map Example for a System with 8 GB of DRAM
FF_FFFF_FFFF
02_8000_0000
Upper DRAM
01_0000_0000
TrustZone Secured Region
SEC Carveout Region

Lower DRAM
Video Protection Region
00_8000_0000
AHB Devices
00_7800_0000
APB Devices
00_7000_0000
External IO
00_6800_0000
PPSB devices
00_6000_0000
00_5800_0000
Graphics Host Devices
00_5400_0000
Verif Aperture
00_5300_0000
PERIPHBASE (CPU, GIC, CCI…)
00_5004_0000
Graphics Host (Host1x)
00_5000_0000
NOR
00_4800_0000
IRAM
00_4000_0000
PCIe
00_0100_0000
IROM
00_0001_0000
EVP
00_0000_0000
16.5.1.2 Client Types

The Memory Subsystem supports five types of clients:
Memory Controller
 32-bit clients with virtual addressing. These clients use the SMMU for page-based and ASID-based address
protection and translation
 32-bit clients with physical addressing. These clients either support native scatter-gather or require regions of
contiguous physical addresses. Because of the 32-bit input address width, these clients can only access the low
4GB of physical address space. These clients still have ASID protection for secure regions.
 34-bit clients with virtual addressing. These clients use the SMMU for page-based and ASID-based address
protection and translation. Because the SMMU only handles 32-bit input addresses, the upper two address bits are
ignored when operating in this mode.
 34-bit clients with physical addressing. These clients either support native scatter-gather or require regions of
contiguous physical addresses.
 34-bit CPUs. These clients have their own memory management unit and CANNOT under any circumstance use the
SMMU for address protection or translation
For Tegra K1 devices, the following list indicates the clients that support 34-bit addressing:
 CPU Complex
 GPU
 XUSB (USB3)
 AFI (PCIE)
 SATA
 SDMMC
 HDA
 VI2/ISP2 (Virtual address client, so only 32 bits are relevant)
 Display (Virtual address or physical address client. When virtual, only 32 bits are relevant)
16.5.2 Tegra K1 Granularity

The minimum burst length for DDR3 is 8. LPDDR3 supports burst lengths of 8. The Memory Subsystem only supports BL8
DRAM. Because of x64 DDR3, the minimum quantum to transfer is 64B. When using a 32-bit DRAM channel, the EMC will
construct two BL8 requests to DRAM to service the 64B request from the MC.
To match this, MC transactions carry 64B of data payload. The 64B can be contiguous or can consist of two non-contiguous
32B “sectors” that lie within the same 512B “gob”, each mapping to a different 32-bit DRAM sub-partition (see the “Memory
Sub-Partitions” section). Byte access remains possible but involves a 64B access: write accesses can use byte enables to
write a set of bytes (including a null set), and read accesses always return two full 32B sectors with potentially unneeded data
(also known as overfetch). To efficiently operate in DDR3 mode, most engines in Tegra K1 devices use 64B memory
requests.
The granularity of external access is linked to the burst size programmed for DRAM access. Bursts into each 32-bit DRAM
channel always start at a 32B aligned boundary and consist of 8 data beats. For x32 configurations, the two 32B sectors in an
MC request correspond to two transfers of 8 data beats.
DDR3 and LPDDR3 support different features to enable less data from being transferred than what the Burst Size indicates.
The resulting minimum data transfer is indicated in the following table.

Memory Controller
Table 54: LPDDR3 and DDR3 Minimum Data Transfers
LPDDR3 BL8
x32 32B
x64 64B
DDR3 BL8
x32 32B
x32 with Chop 16B
x64 64B
Tegra K1 devices support:
 BL8, LPDDR3 and DDR3

 DDR3 Burst Chop
16.5.3 Virtual Addressing

The SMMU is a centralized virtual-to-physical translation for MSS. It maps a 32 virtual address to a 34 bit physical address. If
the client address is 40b then bits 39:32 are ignored. It allows the following:
 Memory allocation for hardware pools (surfaces and buffers) could be made from non-contiguous page-sized chunks
of memory
 Areas of the hardware memory map could be marked as protected, preventing access from hardware devices
 Hardware memory access can be controlled on a per-device or per-process basis
The virtual-to-physical translation is via a two-level page table that carves up the virtual address as follows:
 Bits 31:22 choose a page directory entry (PDE). Each page directory has 1,024 PDEs, each mapping 4MB region.
 Bits 21:12 choose a page table entry (PTE) from a page table. Each page table has 1,024 PDEs, each mapping a
4kB page.
 Bits 11:0 choose a byte within a page

Memory Controller
Figure 31: Page Table and Virtual Address
VA[31:22] VA[21:12] VA[11:0]

PTB Region Page Offset
Page Directory
PDE
Page Table
PTE
Page Byte
Each PTE or PDE consume 32 bits of memory, so that each page directory or page table consumes one 4kB memory page. In
addition, the page directory lookup does an early-out either to map an entire 4MB region of the virtual space as invalid, or to
map the region to a contiguous range of physical pages.
Figure 32: Large Region Mapping
VA[31:22] VA[21:0]
PTB Region Offset
Page Directory
PDE
4MB large region mapping
Byte
The SMMU supports multiple address spaces, each with its own page-table-base register (PTB) and page table. Each
address space is tagged with an address space identifier (ASID). This allows for multiple virtual mappings to exist at the same
time. Typically, software will assign a different address space to each process that directly uses the hardware drivers, allowing
process isolation. The number of ASIDs is 128. Software is responsible for managing the assignments between processes and
ASIDs, flushing ASIDs out of the TLB as needed when they are remapped between processes.

Memory Controller
ASIDs are assigned based on the SWNAME of the incoming request. An on-chip mapping between SWNAME and the ASID is
maintained by the SMMU. For register-based devices, the driver is responsible for updating the mapping between the
SWNAME and the ASID when a device in context is swapped between processes.
Untranslated modules are also supported. The SWNAME-to-ASID mapping has a translation-enable bit to allow translation on
a per-SWNAME basis. There is also a per-client translation-enable bit for Hardware Diagnostics purposes. This can be used
by any client but is typically used by clients that generate 40-bit addresses. In addition, a global “translation enable” bit
disables all translation when cleared (cleared is the default out of reset).If translation is disabled, client address bits 33:0 are
sent directly to the output of the TU. If the client only provided a 32-bit address, the physical address bits 33:32 will be set to 0.
If translation is enabled, the lower 32 bits of the client address will be used to generate the physical address. Note that this
means that client address bits 39:32 will be ignored if a client sends a 40-bit client address and its associated ASID has
translation enabled. This is done to minimize the changes to the SMMU. It is expected that 40-bit clients will typically target
ASIDs that have translation disabled.
Both the page and directory tables are stored in DRAM. A translation look-aside buffer (TLB) will be used to cache recently-
used translations. Translations that miss in the TLB would incur potentially two additional round-trip DRAM delays, but the
latency-scheduling features of the Protocol Arbiter will be used to hide this latency behind the normal latency incurred by the
DRAM reordering policy. The TLB is backed by a page-table cache (PTC) to reduce this memory traffic further.
To further improve CPU latency, the Tegra K1 CPU low-latency read paths bypass the SMMU altogether; the hardware also
restricts the CPU write paths to untranslated-mode to prevent any configuration mishaps.
16.5.3.1 Page Table Layout

The in-memory layout of a PTE looks like
 22 bits of physical address (PA[33:12]) for the base of the page

 Protection bits which include
- A “readable” bit which allows clients to read this page
- A “writeable” bit which allows clients to write this
- A “nonsecure” bit which (when unset) restricts access of this page to “secure” TrustZone clients
The remaining bits in the 32-bit word are reserved.
Note: Wherever physical addresses are used in this document, it is assumed that the device can
address 8GB of physical memory.
The in-memory layout of a PDE looks like:
 A “next level” bit which says if this PDE maps a single 4MB region, or if it points to a page containing a table of PTEs
for the second level of translation
 If the “next level” bit is set, there are 22 bits of physical address (PA[33:12]) that point to a page containing the base
of the PTE table for this PTE. If the “next level” bit is clear, 12 bits (PA[33:22]) are used to point to the base of an
aligned 4MB physical region mapped directly by the PDE.
 The remaining bits set the permissions for the access. For 4MB large pages, these are used directly for the region.
For PDEs that point to a second-level page table, these permissions are ANDed with those of the PTE to give the
final permission
- A “readable” bit for the region
- A “writeable” bit for the region
- A “nonsecure” bit for the region

Memory Controller
The remaining bits in both interpretations are reserved. Reserved bits should be 0, otherwise they can cause an SMMU fault.
Because these are compressed in PTC before they are identified as being PDE or PTE, only the subset of reserved bits that
are common to all formats (bits [27:22]) will trigger an SMMU fault.
Figure 33: PDE and PTE Formats
PDE that maps to a 4MB large page R WS 0 Reserved 4MB page PA[33:22] Reserved
PDE that points to a page table R WS 1 Reserved Page Table PA[33:12]
PTE that maps a 4kB page R WS Reserved 4 kB page PA[33:12]
The base address of the page directory for a particular ASID is stored on-chip in the ASID table. Changes to this table may
require flushing the ASID in question from the TLB.
16.5.3.2 Page Validity and Protection

There is a need on the software side to distinguish between an invalid mapping (which has an invalid PA field) and a mapping
that is valid, but has no access. The following pseudo-code describes the recommended conventions.
// page/section/address space permission types
//
// note that INVALID implies the PA field is unused.
// PA is valid for all others, including NO_ACCESS.
enum Permission {
INVALID = NvU32(0),
NO_ACCESS = NONSECURE,
SECURE_WRITE_ONLY = WRITABLE,
WRITE_ONLY = WRITABLE | NONSECURE,
SECURE_READ_ONLY = READABLE,
READ_ONLY = READABLE | NONSECURE,
SECURE = READABLE | WRITABLE,
ANY = READABLE | WRITABLE | NONSECURE
};
For more information on handling SMMU faults, see the subsection on “MC Interrupts” above.
16.5.3.3 Flushes and Page Table Updates

Changes to the page tables require the TLB to be flushed. A software interface for selectively flushing parts of the TLB is
provided. The flush command can flush any TLB entries that match a particular subset of virtual addresses. Each address
component may be included for matching:
 Match on the ASID, or not

 Match VA[31:22], or not
 Match VA[31:16] or no VA match
Disabling all matches flushes the entire TLB. Note that the TLB is 16 entries wide, so when you match any particular VA, you
flush the entire line, which is why the VA matches are down to 16, rather than 12. 4 MB pages are still matched down to
VA[16] since they are stored in the TLB using the 4 KB page format.
In addition to the TLB, page table updates require flushing stale entries out of the PTC. This needs to be done on a slot-by-slot
basis by writing the PDE or PTE’s physical address (PA[33:4]) to the PTC flush command. Each flush flushes 16 aligned PTEs
or PDEs (one DRAM atom’s worth) out of the cache.
Memory Controller
A page table update requires three writes – one to write the PTE to memory, one to flush the stale PTE out of the PTC, and a
third to flush the stale VA mapping out of the TLB. However, since a single PTC flush flushes 16 PTEs or PDEs and a single
TLB flush can flush the entire TLB, software can reduce the flush traffic by merging flushes from multiple updates.
16.5.4 DRAM Device/Rank, Bank and Page Mapping

Tegra K1 devices support two modes of addressing; normal addressing mode and swiss-cheese mode. The EMEM_BOM
field in the MC_EMEM_CFG_0 register supports the two addressing modes.
EMEM_BOM == 1’b0 : EMEM Base is 2GB // Normal AMAP
EMEM_BOM == 1’b1 : EMEM Base is 0 // Swiss-cheese mode, EAMAP
The various address ranges for DRAM in both configurations are shown the figure below.
Figure 34: Physical DRAM Address Space for Configurations

All addresses are PA (post-SMMU)
4GB System (swiss cheese)

<= 2GB System (swiss- 3GB System no-swiss 3GB System swiss 4GB System (no swiss > 4GB System (swiss
cheese = Don’t care) cheese cheese cheese) cheese not applicable)
CPU View Device View
16GB 16GB 16GB 16GB 16GB 16GB 16GB
N GB
6GB 6GB 6GB
0 0 0 0 0 0 0
In case of any errors, MC logs the address of the violating request in the MC_ERR_STATUS_0.ERR_ADR_HI and
MC_ERR_ADR_0 registers. In case this error address is due to decerr, the logged address is the original Physical Address.
2
The EMC supports multiple devices with data widths of 8, 16, or 32 bits , all identical to form a single rank of either 32 or 64
bits . Up to two ranks are supported.
The bit mapping between the internal linear address and the device/rank, row, column and bank bits is performed as follows:
 The 2 LSBs of the linear address are ignored as the address granularity of the DRAM is 32 bits/4 bytes
 In 64-bit systems, bit 5 of the linear address determines the 32-bit subpartition (with hashing of MSBs)
 In 64-bit systems, bits[9:6,4:2] of the linear address are mapped as column bits [6:0]
 In 32-bit systems, bits[9:2] of the linear address are mapped as column bits [7:0]
 Bits [11:10] are bank bits, possibly hashed.
 Bit [12] is a bank bit if the device has more than two bank bits, possibly hashed.
 The next bits of the linear address are mapped as column bits, as many as remaining after previous mapping
 The next bits of the linear address are mapped as row bits, as many as needed for the selected device
 The next bit is a device/rank bit if device/rank bits are needed
2
A x32 device may be a single x32 chip or two x16 chips in parallel.

Memory Controller
Figure 35: Address Mapping Example

8 GB maximum device size
34 significant bits 1 GB minimum device size
Always 0
30 significant bits
3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 2 1 0 3 9 8 7 6 4 3 2 1 0 5
N Row or Dev or NM Row Row or Col Bank Col NM

M Bank or
Row or Col NM stands for Not Mapped
These bits are translated by MMU.
If BOM = 2GB, Address bit [33:31] must be greater than or equal to 001b, other
values trigger an invalid address error. This check occurs after SMMU
translation.
Example for 4 GB total external DRAM, 2 devices, 8 chips per device – DDR3
Each chip is 2 Gb, 256 Mb x8, 8 banks, JEDEC mapping: 15 row bits, 10 col bits. (64-bit IO)
3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 2 1 0 3 9 8 7 6 4 3 2 1 0 5
Col
NM Row[14:0] Bank Col[7:0] NM
[9:8]
Dev
If BOM = 0B, Address bit[33:32] must be 00b. (i.e. 0~4GB, Dev 0: 0~2GB; Dev 1: 2~4GB)
If BOM = 2GB, Address bit[33:31] must be 001b, or 010b. (i.e. 2~6GB, Dev 0: 4~6GB; Dev 1: 2~4GB)
Other values trigger an invalid address error. This check occurs after SMMU translation.
The number of sub-partition, bank, column, row, and device bits is limited by the number of address pins available:
 Sub-partition width: 1 or 0
 Bank width: 2 or 3
 Column width: 9 to 12
 Row width: 12 to 16
 Logical Devices/Ranks (also known as chip selects): 1 or 2
When two logical devices/ranks are used, the total memory mapped by the second device/rank must be less than or equal to
the first device/rank. The second device/rank also may have a different row, bank, column mapping from the first device.
16.5.5 DRAM Power Modes

The following table maps between the system power modes and DRAM power modes.
Table 55: System Power Modes and DRAM Power Modes
VDD_CORE VDD_CPU MC/EMC PLL MC/EMC Clock DRAM State

Power
LP0 (deep sleep) off off off off off self-refresh
LP1 (suspend) on off on off off self-refresh
LP2 (idle) on off on on on active
This subsection briefly describes the Tegra K1 system power modes. Refer to the PMC section for more details.
 LP0: The goal is ultra-long standby time in a cell phone. In this mode, major power rails are off and I/Os are held
constant. DRAM is commanded by the AVP to enter self-refresh. The MC and EMC are powered off. Exiting LP0 is
called warm boot, in comparison to cold boot which restarts the system. On warm boot, the MC and EMC are re-
initialized from the PMC scratch registers and then DRAM is brought out of self-refresh. The LP0 entry code is
executed from IRAM and the LP0 exit code is executed from boot ROM, both by the AVP.
 LP1: The goal is to suspend the CPU while allowing the hardware path to be externally accessible. All PLLs are
turned off, and therefore MC/EMC/DRAM clocks are frozen. The DRAM is commanded by the AVP to enter self-
refresh (it shares the same code with LP0 entry). Because the MC and EMC keep power during LP1, they do not

Memory Controller
need re-initialization. To exit LP1, simply enable the clock and exit self-refresh. Both LP1 entry and exit code are
executed by the AVP from IRAM.
 LP2: The goal is to power off the CPU while still appearing functional to users. The DRAM can still be accessed by
the display, audio, video, and other system modules, although no access comes from the CPU. The LP2 entry/exit
sequences do not involve the MC/EMC/DRAM.
For pads and DRAM, LP0 and LP1 are in the same state, and LP2 and normal running mode are in the same state.
16.5.6 Bank Hashing

To achieve a good bank interleave, Tegra K1 devices perform a hash of address MSBs into the bank bits.
16.5.7 AHB Redirection Region

During boot, USB3 and flash media (SDMMC/SATA) devices need access to IRAM. Because these clients connect to the MC
and do not have a direct path to the IRAM, The MC implements AHB redirection during boot to allow path to IRAM. In this
mode, accesses to a programmed memory address aperture are directed to the AHB bus, allowing access to the IRAM.
The AHB aperture is defined by the IRAM_BOM and IRAM_TOM registers, which are initialized to disable this aperture. If the
fuse indicates that the boot media is present in one of these clients, that Boot ROM will initialize this aperture to 0x40000000
and 0x4003f000 (1GB, 1GB+IRAM_SIZE), respectively. Once bootup is complete, the boot ROM programs the IRAM_BOM to
0xffffffff and IRAM_TOM to 0x00000000, thus disabling access to IRAM. DRAM is then potentially accessible in this address
range. These aperture register also have an access_control/lock bit. After disabling the aperture, the access_control register
should be programmed to lock the registers.
AHB routes the requests targeted to IRAM appropriately and routes all non-DRAM aperture requests (as defined by the swiss-
cheese and related configuration) back to the MC as the default DRAM region. Care must be taken to program the IRAM
aperture register to prevent a request from being stuck in a loop.
16.5.8 TrustZone Security Region

The MC can secure a region in the physical address aperture from insecure software sources. The region can be defined on
1MB boundaries in the external memory region, in multiples of 1 MB. If a non-secure request is made to the secured region or
if a secure request from the CPU is made outside of the secured region (after this mode is enabled), the MC generates an
interrupt (if enabled) and logs the details of the request (address, client ID). After the details are logged, write requests are
dropped and read requests are forced to return all 1’s, thus protecting the secured region from corruption by the insecure
source and avoiding aliasing in the CPU cache.
Only clients configured for security can make secure requests.
After the TZ aperture is established, the CPU_STRICT_TZ_APERTURE_CHECK bit in the MC_TZ_SECURITY_CTRL_0

register is set in the MC, which forces correct behavior as follows:
 Secure requests from the CPU can only access TZ secure memory space and not access the memory outside TZ
secure memory space.
 Secure requests from other clients may access the TZ secure memory space and also may access memory outside
TZ secure memory space.
 Non-secure requests from any client can only access memory outside the TZ secure memory space.
The register MC_TZ_SECURITY_CTRL_0.CPU_STRICT_TZ_APERTURE_CHECK itself is sticky and cannot be changed

once set after cold boot.

Memory Controller
16.5.9 Video Protection Memory Region

This protected memory aperture prevents the CPU (and other unauthorized clients) from accessing data within the region. The
MC secures a region in memory from access and modifications by engines that are not part of the video decode and display
process.
This aperture is defined by the VIDEO_PROTECT_BOM and VIDEO_PROTECT_SIZE_MB (reset value 0x0) registers. The
value 0 for the size register disables this aperture.
In addition to protecting the region in memory, the registers are allowed only secured access by the Boot Loader only. On cold
boot when this register is initially programmed, it is also written to the secure PMC-scratch region. On LP0 resume, the register
value is restored from this region. This eliminates need for saving this register content on LP0 entry. An additional lock bit
locks down the access to this register. On reset the lock bit is cleared. When the lock bit is cleared, the writes are allowed to
the VPR aperture registers. When the VPR registers are initialized, the lock bit is set. When the lock bit is set, all writes to the
VPR aperture registers are ignored. This lock bit is used for cold boot as well for LP0 exit.
For systems that do not implement VPR, the Boot Loader must still set the lock bit to indicate that programming is completed.
16.5.10 Security Coprocessor Secure Region

The Security Coprocessor (SEC) engine needs a secured memory space meant exclusively for use by this engine. This
memory region, SECR (SEC region) should be accessed only by the SEC engine; no other clients are allowed to read or write
to this memory region. This memory region is defined by physical memory range.
The SEC engine (also referred to as TSEC) uses this carveout region as an extension to its I-cache and D-cache. Without this
carveout, the TSEC has to encrypt the data before writing to normal DRAM.
The SECR_BOM and SECR_SIZE_MB registers (reset value 0x0) define the 1MB aligned base and size register for this
region. In addition to protecting this memory region, these aperture definition registers themselves need to be protected and
are allowed to be modified only by the Boot Loader (during cold boot) and the Boot ROM (during LP0 resume) and should be
implemented similar to the VPR aperture registers. An additional sticky/secure bit controls this register. On reset this
sticky/secure bit is cleared, thus allowing write access to the SECR aperture registers. When the Boot Loader initializes the
aperture registers, it also sets this sticky/secure register bit. When this sticky/secure bit is set, all subsequent writes to this
register are ignored. On LP0 resume, reset clears this sticky bit; it is set again when the aperture register is restored from the
PMC secure scratch space. To avoid saving this aperture register on LP0 entry, the Boot Loader (during cold boot) should
store this aperture definition to the PMC secure scratch space.
The size for this carveout region is 1MB.
Any access to this memory aperture by any other client (other than SEC) is ignored (read returns all 1s as the response and
writes are dropped) and an error is logged.
16.5.11 Microcode Carveout Protection Region (Tegra K1 64-Bit Only)

Microcode carveout is a protected region of physical memory required by the CPU architecture. Only native CPU accesses
from the CCPlex client are allowed to read or write locations in microcode carveout.
The protected region is defined to start at MTS_CARVEOUT_BOM and ends at MTS_CARVEOUT_SIZE. It can start and be
extended in multiples of 1MB . The only clients allowed to access the protected region are the CPU read and write clients:
 MPCORER
 MPCOREW
 MPCORELPR
 MPCORELPW

Memory Controller
All other clients attempting to access this region will cause the MC to issue an interrupt and log the details of the request
(address, client ID). After the details are logged, write requests are dropped and read requests are forced to return all 1s, thus
protecting the region from corruption by the insecure source.
The registers defining the aperture also need to be protected. As with the VPR aperture registers, an additional sticky/secure
bit controls these registers. On reset this sticky/secure bit is cleared, allowing write access to these registers. When this
sticky/secure bit is set, all subsequent writes to these registers are ignored.
The Microcode Carveout Protection Region should be set up and locked at or soon after the time of DRAM configuration,
before or during the micro-architectural cold boot process, before any accesses occur to the protected region by the CPU
cores. In order to minimize the boot impact, the CPU will begin using the carveout DRAM in parallel with Tegra firmware
reading the Boot Loader binary. When entering LP0, microcode will store information sufficient to reconstruct the Microcode
Carveout aperture registers into the PMC secure scratch space. On LP0 exit, reset clears the sticky bit; it is set again when
the Boot ROM initiates the LP0 DMCE exit sequence to restore the aperture registers from the PMC secure scratch space.
16.6 Memory Tiling

Tegra K1 supports the memory tiling formats described below.
Table 56: Client Shared Tiling Formats
Format Status Used for Description
Supported by some Software-compatibility, clients that

Pitch Linear Simple array ordering
clients linearly access memory
Kepler color surfaces, clients that Square DRAM page

Block linear 16Bx2 with Supported by all
access memory in blocks or arrangement (blocks) with
Tegra K1 sector ordering clients
vertically folded atoms
Legacy (Prior to Tegra 2

Not Supported
devices)
The parameters associated with each tiling format are listed below:
Table 57: Surface Descriptor Parameters
Minimum
Parameter Used by Description Values
Alignment
Layout All Surface layout PITCH, BLOCKLINEAR N/A
32-bit virtual address (40-bit virtual address within

Starting address the GPU) 64B (general)
Base
Pitch of surface, in 128B (GPU)
Address -or-
bytes 256B (MSENC, VIC)
34-bit physical address
64B (general)
Line-to-line Large enough for at least 4,096 pixels in bytes 128B (GPU)
Pitch Pitch
stride in bytes (some clients may support larger values) 256B (MSENC)
up to 256B (VIC) 3
32-bit virtual address

Starting address (40-bit virtual address within the GPU)
Base Block
of surface, in 512B (one gob)
Address Linear -or-
bytes
34-bit physical address
3
The pitch alignment restrictions for VIC depend on its cache line shape: 256Bx1: 256B, 128Bx2: 128B, otherwise: 64B.

Memory Controller
Minimum
Parameter Used by Description Values
Alignment
ONE_GOB
Block Width of block in
Block Width (this is the only setting supported on 32-bit Tegra N/A
Linear gobs
K1)
[ONE_GOB, THIRTYTWO_GOBS]
Block Block Height of block (SIXTEEN_GOBS is the normal setting, but N/A
Height Linear in gobs ONE_GOB may be needed for display surfaces
outside carveout
[ONE_GOB, THIRTYTWO_GOBS]
Block Block Depth of block
(values greater than ONE_GOB are currently only N/A
Depth Linear in gobs
supported by the GPU)
Block Width of surface [1, 4096] samples

Width 1 sample
Linear in samples (some clients may support larger values)
(x,y) to linear address translation is the responsibility of clients. The MCCIF only supports linear address inputs. Contact your
NVIDIA representative for access to libraries with translation code to simplify implementation.
16.6.1 Block Linear

The block linear formats map batches of contiguous addresses into rectangular blocks, and tile these blocks linearly. Blocking
serves two purposes: 1) it maps a DRAM page into a rectangular region, rather than into a one-pixel-tall strip, to capture
locality in a graphics geometry stream or other 2D-oriented client, such as an MPEG encoder or decoder, and 2) it makes it
possible to predictably interleave banks in x and y, minimizing bank conflicts over a large region.
Blocks themselves are arranged from GOBs (Groups of Bytes). A Kepler GOB is 512 bytes arranged as 64x8 bytes. GOBs
are stacked vertically to form a block. The number of GOBs stacked vertically in a block is controlled by an additional surface
parameter called the block height. The recommended block height for most buffers in Tegra K1 devices is 16 GOBs (128
lines). This supports 8x8 bank interleaving. For buffers for which linear display access is more important than access by GPU,
VIC, or other block-oriented engine, block height can be set to 1 GOB, providing more locality for the display client.
Blocks are arranged horizontally into a Row of Blocks (ROBs) to fill out the surface to the width value (or slightly beyond, if the
width is not a multiple of the 64B block width). Upper address bit swizzling in the bank swizzling algorithm generally makes it
unnecessary to pad the surface width further.
16.6.2 Sub-Partitions
The 64-bit DRAM channel can be divided into two sub-partitions with DQ[31:0] forming sub-partition A and DQ[63:32] forming
sub-partition B.
Each 64B atom is divided into 2 sectors of 32B. One sector contains bytes 0 – 31 while the other contains bytes 32 – 63.
16.6.3 Software Guidelines

Software should allocate surfaces respecting the minimum alignments specified in Table 57. This section gives additional
alignment restrictions for certain clients and advice on allocating surfaces for best performance.
Certain clients, such as MSENC, VDE, and VIC use 32-bit registers (left-shifted 8) to specify 40-bit base addresses of a buffer.
Base addresses for these clients must be aligned to a minimum of 256B.
Certain clients, such as MSENC and VIC, have a fixed cache line size and read all data within a cache line, even if it is beyond
the nominal height and width of the surface. For such clients, surface width and height need to be padded to at least the next
multiple of the cache line size so the unit does not read beyond the end of the buffer.

Memory Controller
Surface Type
 Block linear format generally provides best performance and should be chosen by default.
 Pitch format may be preferable if producer and consumer clients perform linear accesses and both clients support
pitch.
 Private formats are used by a few units, such as MSENC and VDE. For private formats, the client-required
allocation and padding rules must be followed.
Block Linear
 Alignment. Align surface start address as follows:
- 512B is the minimum alignment for correct behavior. Performance will be poor (no zero-bandwidth clears, poor
page locality).
- 1KB alignment is better. Zero bandwidth clears will work. Bank interleave will be suboptimal.
- 8KB alignment is best. All compression features work. Bank interleave assumes 8KB alignment. Use this
setting for large buffers.
 Block height should normally be programmed to SIXTEEN_GOBS (128 lines). For certain surfaces for which
display is the primary client, block heights of ONE_GOB or TWO_GOBS are recommended. Surfaces to be
4
accessed by the GPU texture unit may require a smaller block height under certain conditions.
 Width is typically prescribed by the application. Hardware allocates a block linear surface to be an integral number of
blocks wide, so its allocated width is width*Bpp rounded up to the next block boundary (64B), which is sufficient
5
padding in almost all circumstances.
 Height padding. Surfaces should be an integral number of blocks tall. If a client such as MSENC or VIC has a
cache line that is taller than the block height, additional row(s) of blocks may be required for padding.
Pitch
 Alignment. Align surface start address to a minimum of:
- 128B if surface is to be accessed by the GPU
- 256B if surface is to be accessed by MSENC, VDE, or VIC (due to the 8-bit left-shift issue)
- 64B otherwise
 Pitch. Surface pitch must be a multiple of:
- 128B bytes if surface is to accessed by GPU
- 128B if surface is to be read by VIC with 128x2 cache line shape
- 256B if surface is to be read by VIC with 256Bx1 cache line shape
- 64B otherwise.
 Height padding. For clients, such as MSENC and VIC, additional lines of padding might be required beyond the
nominal height of the surface. For example, when the VIC is reading a source buffer with an internal cache line
shape of 32x8, the source buffer must be a multiple of 8 lines tall.
4
For buffers that are to be accessed using the GPU texture unit, the BlockHeight parameter must match that used by the texture unit. In particular,
note that if a texture surface is smaller than the specified size in blocks, texture uses a shrunken blockHeight instead of the nominal parameter
specified in the Texture Header.
5
If VIC cacheline shapes of 128x2 or 256x1 are used (generally not recommended for block linear), width must be padded up to a multiple of the cache
line width. If this is not possible, a narrower cache line shape must be used

Memory Controller
16.7 Memory Controller Registers

16.7.1 MC Registers
USAGE NOTE: Many MC register fields are shadowed.
Writes to shadowed register fields update the shadow copy (this is default, assumes
TIMING_CONTROL_DBG.WRITE_MUX==ASSEMBLY).
Reads to shadowed register fields return the currently-active copy (this is default, assumes
TIMING_CONTROL_DBG.READ_MUX==ACTIVE).
This allows a new set of frequency-dependent timing parameters to be written to the shadow registers while memory traffic is
ongoing, then when the parameters are completely written, the MC hardware can perform a timing-safe switch.
Such switches can be triggered via two methods: TIMING_CONTROL.TIMING_UPDATE (generally used during initialization),
or the automatic CAR/EMC handshake on a clock-frequency or divider change (assuming
TIMING_CONTROL_DBG.IGNORE_EMC_TRIGGERS==DISABLED).
Registers that are shadowed are marked by a comment:
This register is shadowed: see usage note at the top of Section 16.7.1
USAGE NOTE: Many MC registers should be programmed by the Boot Loader as part of the warm boot (also known as "wake
from LP0") and cold boot (also known as "power up") sequences. Suggested actions for the Boot ROM/Boot Loader are noted
under "Boot requirements:".
USAGE NOTE: Some MC registers may only be accessed by TrustZone-secured register transactions. See the appropriate
ARM Architecture Reference Manual for information on how to handle security. Such registers are marked by a comment:
“Access to this register is restricted to TrustZone-secured requestors.”
USAGE NOTE: The MC register fields to be stored in PMC scratch registers for warm boot must have "[PMC]" in their
comments. After adding and removing such PMC flag, the tool warmboot_code_gen must be rerun to generate new boot ROM
code.
USAGE NOTE: When writing to a register, any bits that are not intended to be modified should be rewritten with their existing
values.
USAGE NOTE: Unspecified bits may not appear in tables and should be written with their Reset values.
16.7.1.1 MC_INTSTATUS_0
Interrupt Status
This register contains trigger bit fields. Bit fields not shown here are reserved.
Offset: 0x0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxx0xx000000x0xxxxxx)
DECERR_MTS_INT: This interrupt is for access violation on MTS carveout region in the MC. If a client
other than CPU read or write is trying to access the region.
16 CLEAR
0 = CLEAR
1 = SET
SECERR_SEC_INT: The request violated the SEC Carveout requirements - Only TSEC clients may
13 CLEAR access the SEC carveout.
0 = CLEAR

Memory Controller

1 = SET
DECERR_VPR_INT: The request violated the VPR requirements - in case of a read, the request address
fell in the VPR range, but the VPR attribute of the request was not set. In case of a write, the request had
12 CLEAR the VPR attribute set in the request, but the request address did not fall in the VPR range.
0 = CLEAR
1 = SET
INVALID_APB_ASID_UPDATE_INT: ASID Update through APB interface resulted in an error. APB

interface tried to update secure ASID through Non-secure interface.
11 CLEAR
0 = CLEAR
1 = SET
INVALID_SMMU_PAGE_INT: Address translation error: An access was attempted to an invalid page or a

protected page. See ERR_STATUS and ERR_ADR for more information.
10 CLEAR
0 = CLEAR
1 = SET
ARBITRATION_EMEM_INT: Warning that a pending request has reached the deadlock-prevention slack
threshold. This indicates that the MC could not meet the programmed performance goals. This interrupt
9 CLEAR is for use with assisting debug of performance-related issues.
0 = CLEAR
1 = SET
SECURITY_VIOLATION_INT: Address translation error: A nonsecure access was attempted to a

secured region. See ERR_STATUS and ERR_ADR for more information.
8 CLEAR
0 = CLEAR
1 = SET
DECERR_EMEM_INT: Address translation error: EMEM Address Decode Error. See ERR_STATUS and
ERR_ADR for more information.
6 CLEAR
0 = CLEAR
1 = SET
16.7.1.2 MC_INTMASK_0
Interrupt Masks
Boot requirements: This register should be saved to SDRAM registers and restored by the OS during warm boot. Bit fields
not shown here are reserved.
Offset: 0x4 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxx0xx000000x0xxxxxx)

Default: 0x00003540
DECERR_MTS_INTMASK:
16 MASKED _NONE_ 0 = MASKED
1 = UNMASKED
SECERR_SEC_INTMASK: Prevents SECERR_SEC_INT from triggering an interrupt to

the interrupt controller.
13 MASKED UNMASKED
0 = MASKED
1 = UNMASKED
DECERR_VPR_INTMASK: Prevents DECERR_VPR_INT from triggering an interrupt to

the interrupt controller.
12 MASKED UNMASKED
0 = MASKED
1 = UNMASKED
INVALID_APB_ASID_UPDATE_INTMASK: Prevents
INVALID_APB_ASID_UPDATE_INT from triggering an interrupt to the interrupt
11 MASKED _NONE_ controller.
0 = MASKED
1 = UNMASKED

Memory Controller
INVALID_SMMU_PAGE_INTMASK: Prevents INVALID_SMMU_PAGE_INT from

triggering an interrupt to the interrupt controller.
10 MASKED UNMASKED
0 = MASKED
1 = UNMASKED
ARBITRATION_EMEM_INTMASK: Prevents ARBITRATION_EMEM_INT from

9 MASKED _NONE_
0 = MASKED
1 = UNMASKED
SECURITY_VIOLATION_INTMASK: Prevents SECURITY_VIOLATION_INT from

8 MASKED UNMASKED
0 = MASKED
1 = UNMASKED
DECERR_EMEM_INTMASK: Prevents DECERR_EMEM_INT from triggering an

interrupt to the interrupt controller.
6 MASKED UNMASKED
0 = MASKED
1 = UNMASKED
16.7.1.3 MC_ERR_STATUS_0
Error Data Capture: Status

If a translation error is detected (for example, address-out-of-bounds, security fault, protection fault), this register records
information about this access:
 which fault the captured error corresponds to

 a read/write indicator and
 the request ID (global client ID assigned by the memory controller, see the list below).
If the error was an INVALID_SMMU_PAGE, then information about the page's protection status is also captured:
 whether the page was marked non secure in the page-table

 whether the page was marked readable in the page-table
 whether the page was marked writeable in the page-table
Note that SMMU page protection bits are formed by ANDing the page protection bits from the Page Table Base, Page
Directory Entry, and Page Table Entries from all three stages of the page-walk. The ANDed protection bits and the type of the
provoking transaction are both available in the status register.
Subsequent faults (of any type) will not change the status and address registers until the corresponding interrupt is cleared.
The global memory client IDs are defined as follows:
INBAND-
Client ID ID (hex) SWGROUP Module Partition Description
SWID
Misses from
System Memory
csr_ptcr 0 (0x00) ptc Management Unit
(SMMU) Page
Table Cache (PTC)
Display reads,
csr_display0a 1 (0x01) dc display dis
window A
Display reads,
csr_display0ab 2 (0x02) dcb displayb disb
window A
Display reads,
csr_display0b 3 (0x03) dc display dis
window B

Memory Controller
INBAND-
SWID
Display reads,
csr_display0bb 4 (0x04) dcb displayb disb
window B
Display reads,
csr_display0c 5 (0x05) dc display dis
window C
Display reads,
csr_display0cb 6 (0x06) dcb displayb disb
window C
csr_afir 14 (0x0e) afi afi pcx PCIE reads
ARM7 Audio-Video
Processor (AVP)
csr_avpcarm7r 15 (0x0f) avpc avpc avp
reads via the
avp_cache
Display reads,
csr_displayhc 16 (0x10) dc display dis
cursor
Display reads,
csr_displayhcb 17 (0x11) dcb display disb
cursor
High-definition
csr_hdar 21 (0x15) hda hda apb
audio (HDA) reads
Host channel data

csr_host1xdmar 22 (0x16) hc host1x host
reads
csr_host1xr 23 (0x17) hc host1x host Host indirect reads
csr_msencsrd 28 (0x1c) msenc msenc mse
AHB DMA engine

csr_ppcsahbdmar 29 (0x1d) ppcs ppcs ahb
reads
ppcs1
csr_ppcsahbslvr 30 (0x1e) ppcs ppcs ahb AHB bus reads
ppcs2
csr_satar 31 (0x1f) sata sata sax SATA reads
Video Decode
(VDE) video
csr_vdebsevr 34 (0x22) vde vde2x vd
bitstream engine
reads
Video Decode
csr_vdember 35 (0x23) vde vde2x vd (VDE) macroblock
engine reads
Video Decode
(VDE) motion-
csr_vdemcer 36 (0x24) vde vde2x vd
compensation
engine reads
Video Decode
csr_vdetper 37 (0x25) vde vde2x vd (VDE) transform
engine reads
Reads from
Cortex-A9 Shadow
csr_mpcorelpr 38 (0x26) mpcorelp mpcorelp stop
CPU core via the
L2 cache
Reads from
Cortex-A9 4 CPU
csr_mpcorer 39 (0x27) mpcore mpcore ftop
cores via the L2
cache
csw_msencswr 43 (0x2b) msenc msenc mse
csw_afiw 49 (0x31) afi afi pcx PCIE writes

Memory Controller
INBAND-
SWID
Arm7 Audio-Video
Processor (AVP)
csw_avpcarm7w 50 (0x32) avpc avpc avp
writes via the
avp_cache
High-definition
csw_hdaw 53 (0x35) hda hda apb
audio (HDA) writes
csw_host1xw 54 (0x36) hc host1x host Host indirect writes
Writes from
Cortex-A9 Shadow
csw_mpcorelpw 56 (0x38) mpcorelp mpcorelp stop
CPU core via the
L2 cache
Writes from
Cortex-A9 4 CPU
csw_mpcorew 57 (0x39) mpcore mpcore ftop
cores via the L2
cache
AHB DMA engine

csw_ppcsahbdmaw 59 (0x3b) ppcs ppcs ahb
writes
ppcs1
csw_ppcsahbslvw 60 (0x3c) ppcs ppcs ahb AHB bus writes
ppcs2
csw_sataw 61 (0x3d) sata sata sax SATA writes
Video Decode
(VDE) video
csw_vdebsevw 62 (0x3e) vde vde2x vd
bitstream engine
writes
Video Decode
csw_vdedbgw 63 (0x3f) vde vde2x vd (VDE) debug
writes
Video Decode
csw_vdembew 64 (0x40) vde vde2x vd (VDE) macroblock
engine writes
Video Decode
csw_vdetpmw 65 (0x41) vde vde2x vd (VDE) transform
engine writes
ISP Read client for

csr_ispra 68 (0x44) isp2 isp2 isp
Crossbar A
ISP Write client for

csw_ispwa 70 (0x46) isp2 isp2 isp
Crossbar A
ISP Write client

csw_ispwb 71 (0x47) isp2 isp2 isp
Crossbar B
csr_xusb_hostr 74 (0x4a) xusb_host xusb_host usbx XUSB reads
XUSB_HOST
csw_xusb_hostw 75 (0x4b) xusb_host xusb_host usbx
writes
csr_xusb_devr 76 (0x4c) xusb_dev xusb_dev usbd XUSB reads
csw_xusb_devw 77 (0x4d) xusb_dev xusb_dev usbd XUSB_DEV writes
ISP Read client for

csr_isprab 78 (0x4e) isp2b isp2b ve2 Crossbar A;
instance b of isp2
ISP Write client for

csw_ispwab 80 (0x50) isp2b isp2b ve2 Crossbar A;
instance b of isp2

Memory Controller
INBAND-
SWID
ISP Write client

csw_ispwbb 81 (0x51) isp2b isp2b ve2 Crossbar B;
instance b of isp2
TSEC Memory
csr_tsecsrd 84 (0x54) tsec tsec apb Return Data Client
Description
TSEC Memory
csw_tsecswr 85 (0x55) tsec tsec apb Write Client
Description
Reads from
Cortex-A9 Shadow
csr_a9avpscr 86 (0x56) a9avp a9avpsc a9avppc
CPU core via the
L2 cache
Writes from
Cortex-A9 Shadow
csw_a9avpscw 87 (0x57) a9avp a9avpsc a9avppc
CPU core via the
L2 cache
csr_gpusrd 88 (0x58) gpu gpub gpu gk 3D, ltcx reads
csw_gpuswr 89 (0x59) gpu gpub gpu gk 3D, ltcx writes
Display reads,
csr_displayt 90 (0x5a) dc dc1 display dis
Window T
sdmmca memory
csr_sdmmcra 96 (0x60) sdmmc1a sdmmca aud
read client
sdmmca memory
read client;
csr_sdmmcraa 97 (0x61) sdmmc2a sdmmcaa aud
instance a of
sdmmca
sdmmc3 memory
csr_sdmmcr 98 (0x62) sdmmc3a sdmmc aud
read client
sdmmca memory
read client;
csr_sdmmcrab 99 (0x63) sdmmc4a sdmmcab sd
instance b of
sdmmca
sdmmca memory
csw_sdmmcwa 100 (0x64) sdmmc1a sdmmca aud
write client
sdmmca memory
write client;
csw_sdmmcwaa 101 (0x65) sdmmc2a sdmmcaa aud
instance a of
sdmmca
sdmmc3 memory
csw_sdmmcw 102 (0x66) sdmmc3a sdmmc aud
write client
sdmmca memory
write client;
csw_sdmmcwab 103 (0x67) sdmmc4a sdmmcab sd
instance b of
sdmmca
csr_vicsrd 108 (0x6c) vic vic vicpc
csw_vicswr 109 (0x6d) vic vic vicpc
csw_viw 114 (0x72) vi vi2 ve VI Write client
Display reads,
csr_displayd 115 (0x73) dc display dis
Window D

Memory Controller
Offset: 0x8 | Read/Write: RO | Reset: 0xXXXXX0XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
ERR_TYPE: Type of the corresponding error:

0 = RSVD : Code 0x0 is never used.
2 = DECERR_EMEM : There is no physical DRAM attached for this address based on the value of
EMEM_SIZE_MB configuration register.
30:28 X 3 = SECURITY_TRUSTZONE : The non-secure client has attempted to access the Trustzone-secured
aperture; or a secure client has attempted to access the Trustzone-secured aperture using a non-
secure request.
4 = SECURITY_CARVEOUT : Reserved
6 = INVALID_SMMU_PAGE : The SMMU page-translation flagged an error for that access.
ERR_INVALID_SMMU_PAGE_READABLE: If INVALID_SMMU_PAGE error, set if page permission

27 X
was readable (AND of PTB/PDE/PTE). Ignore if no INVALID_SMMU_PAGE error.
ERR_INVALID_SMMU_PAGE_WRITABLE: If INVALID_SMMU_PAGE error, set if page permission

26 X
was writable (AND of PTB/PDE/PTE). Ignore if no INVALID_SMMU_PAGE error.
ERR_INVALID_SMMU_PAGE_NONSECURE: If INVALID_SMMU_PAGE error, set if page permission

25 X
was non-secure (AND of PTB/PDE/PTE). Ignore if no INVALID_SMMU_PAGE error.
ERR_ADR_HI: Higher address bits of erring address whose lower bits are available in ERR_ADR
21:20 X
register
18 X ERR_SWAP: Swap bit for transaction
ERR_SECURITY: Set if the transaction was secure.

17 X 0 = NONSECURE
1 = SECURE
ERR_RW: Direction of the access that caused the error.

16 X 0 = READ
1 = WRITE
14:12 X ERR_ADR1: Second subpartition unique address bits
6:0 X ERR_ID: Client identifier (see above list) of the access that caused the error.
16.7.1.4 MC_ERR_ADR_0
Error Data Capture: Address

If a translation error is detected, this register records the request byte address.
Subsequent faults (of any type) will not change the status and address registers until the corresponding interrupt is cleared.
Note that the decode-error, security-Trustzone, and security-carveout checks occur on the physical address (in other words,
after SMMU translation); thus those error types capture the physical address. All other errors capture the virtual address.
31:0 X ERR_ADR

Memory Controller
16.7.1.5 MC_SMMU_CONFIG_0
Used for interrupt set/clear enums. When disabled, all transactions are untranslated. When enabled, transactions may be
translated. See per-client and per-module enables in SMMU_* registers below.
This register can only be accessed by TrustZone-Secured accesses from the CPU.
Access to this register is restricted to TrustZone-secured requestors.
Boot requirements: This register should be saved to SDRAM registers and restored by the OS during warm boot.
SMMU Enable Register

Offset: 0x10 | Read/Write: R/W | Secure: Trust Zone Protected | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
SMMU_ENABLE:
1 = ENABLE
16.7.1.6 MC_SMMU_TLB_CONFIG_0
Translation Lookaside Buffer Config Register

Controls usage of the TLB.
Offset: 0x14 | Read/Write: R/W | Reset: 0x30000020 (0b0011xxxxxxxxxxxxxxxxxxxxxx100000)
TLB_STATS_ENABLE: Enable TLB Hit and Miss counters

1 = ENABLE
TLB_STATS_TEST: Set stats registers to all "1s"

1 = ENABLE
TLB_HIT_UNDER_MISS: Allow hits to pass misses in the TLB. This value may not be
changed on the fly. Ideally, this should be set before enabling the SMMU. At the very least, the
29 ENABLE TLB needs to be flushed and traffic through the SMMU stopped before changing this value.
0 = DISABLE
1 = ENABLE
TLB_ROUND_ROBIN_ARBITRATION: When enabled, forces round robin (RR) arbitration

between TLB hit and miss FIFOs.
28 ENABLE
0 = DISABLE
1 = ENABLE
TLB_ACTIVE_LINES: Set the number of active lines. Allows the TLB to be made "virtually
4:0 0x10
smaller" to save power. "Inactive" lines will never hit and never hold data.
16.7.1.7 MC_SMMU_PTC_CONFIG_0
Controls usage of the PTC

Memory Controller
Page Table Cache Config Register

Offset: 0x18 | Read/Write: R/W | Reset: 0x2800003f (0b001x1000xxxxxxxxxxxxxxxxxx111111)
PTC_STATS_ENABLE: Enable PTC Hit and Miss counters

1 = ENABLE
PTC_STATS_TEST: Set stats registers to all "1s"

1 = ENABLE
PTC_CACHE_ENABLE: Enable the PTC cache.

1 = ENABLE
PTC_REQ_LIMIT: Limit outstanding PTC fill requests to the DRAM. Minimum value is 5;
27:24 0x8
otherwise the SMMU can have functional failures.
5:0 0x3f PTC_INDEX_MAP: XOR pattern for tag generation
16.7.1.8 MC_SMMU_PTB_ASID_0
Page Table Bases (PTBs)

These pointers point to a 4KB-page aligned table of PDEs for each ASID. They also contain initial permission bits that are
ANDed with those in the PDE and PTEs to determine the final permissions of accesses through this ASID.
The PTBs are stored in a RAM that is accessed indirectly though the SMMU_PTB_ASID and SMMU_PTB_DATA registers.
Boot requirements: This RAM should be saved to SDRAM and restored by the OS during warm boot.
Page Table Base ASID Register

This register selects which PTB is modified by the SMMU_PTB_DATA register.
Offset: 0x1c | Read/Write: R/W | Reset: 0x000000XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
6:0 X CURRENT_ASID: ASID used to address SMMU_PTB register
16.7.1.9 MC_SMMU_PTB_DATA_0
Writes or reads to this register write or read the Page Table Base pointer for the ASID defined in the SMMU_PTB_ASID
register.
This register is not TrustZone secure, but only a TrustZone secure access may alter the PTB for a secure ASID.
Secure ASIDs have additional privilege over other non-secure ASIDs - they may fetch page tables from secure memory and
they can allow clients translated through them to make secure accesses if programmed to do so.
Attempts to write a secure ASID with a non-secure access will be ignored, and non-secure reads will return garbage.

Memory Controller
Page Table Base Data Register

Offset: 0x20 | Read/Write: R/W | Reset: 0xX0XXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31 X ASID_READABLE: if set, reads are allowed for this ASID
30 X ASID_WRITABLE: if set, writes are allowed for this ASID
29 X ASID_NONSECURE: if set, non-secure accesses are allowed for this ASID
21:0 X ASID_PDE_BASE: Pointer to page of PDEs, bits [33:12] for this ASID
16.7.1.10 MC_SMMU_TLB_FLUSH_0
Software can write this register to flush a specific page group, 4MB section, entire ASID or the entire TLB. There is
independent control over matching part or all of the VA and/or matching the ASID.
Note: The granularity of VA mapping here is at a page group, which is the number of PTEs that
fit in a memory atom.
Translation Lookaside Buffer Flush Register

Offset: 0x30 | Read/Write: R/W | Reset: 0xXX0XXXXX (0bxxxxxxxxxxx0xxxxxxxxxxxxxxxxxxxx)
TLB_FLUSH_ASID_MATCH: If enabled, only entries matching TLB_FLUSH_ASID are

flushed.
31 X
0 = DISABLE
1 = ENABLE
30:24 X TLB_FLUSH_ASID: ASID to match when TLB_FLUSH_ASID_MATCH is ENABLED
TLB_FLUSH_VA_GROUP: Virtual address to match for group flushes, VA[31:15]. VA[14] of

19:2 X
this field is ignored due to the TLB line size.
TLB_FLUSH_VA_MATCH: Controls flushing based on VA, one of ALL: Flush entire TLB
SECTION: Flush all entries with a VA[31:22] that match TLB_FLUSH_VA_SECTION GROUP:
Flush all entries with a VA[31:14] that match TLB_FLUSH_VA_GROUP. By default, the
1:0 X GROUP setting takes effect if this field is programmed to a value of 1.
0 = ALL
2 = SECTION
3 = GROUP
16.7.1.11 MC_SMMU_PTC_FLUSH_0
Software can use this register to flush a specific PTE or PDE from the Page Table Cache (PTC) by writing the atom-aligned
physical address of the PTE group. It can also flush the entire PTC via this register.
Note: The granularity of flushing is at the PTE group, which is the number of PTEs that fit in a
memory atom.
Page Table Cache Flush Register

Offset: 0x34 | Read/Write: R/W | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx1xxx)
31:4 X PTC_FLUSH_ADR: Physical address of PTE group to match for address flushes, PA[31:4]
PTC_NO_WAIT_IDLE_FLUSH: Set bit to immediately flush without waiting for hit FIFO to go
3 0x1
idle. Not required because it does not present an ordering hazard.

Memory Controller
PTC_FLUSH_TYPE: Controls flushing, one of ALL: Flush entire PTC ADR: Flush PTEs that
are addressed by PTC_FLUSH_ADR
0 X
0 = ALL
1 = ADR
16.7.1.12 MC_EMEM_CFG_0
Boot requirements:
 This register should be parameterized in the BCT and written by the Boot ROM during cold boot.
 This register should be saved in the scratch registers and restored by the Boot ROM during warm boot.
 During warm boot, this register may be derived from EMEM_ADR_CFG* register values.
External Memory Aperture Configuration

Offset: 0x50 | Read/Write: R/W | Reset: 0x00002000 (0b0xxxxxxxxxxxxxxxxx10000000000000) | Default: 0x00000000
EMEM_BOM: Base of DRAM memory in GBs [PMC_SECURE]. B2GB should be

used for 34b systems, while B0GB supports up to 4GB using extended mapping
31 B2GB B2GB mode
1 = B0GB
0 = B2GB
EMEM_SIZE_MB: Specify the external memory aperture size in megabytes. This

field must be set to less than or equal to the available physical memory for proper
13:0 0x7ff NONE operation. This value is used to check for decode errors; requests to addresses
greater than or equal to EMEM_BOM+EMEM_SIZE_MB will result in an EMEM
decode error.
16.7.1.13 MC_EMEM_ADR_CFG_0
The EMEM_ADR_CFG* registers are used to specify the DRAM density and geometry parameters. The MC will use these
parameters to derive device, row, bank, column addressing values to EMC.
Note: The maximum size externally supported is dependent on pinout and address-map aperture
limitations, and that it may be possible to configure the device/row/bank/column addresses
in ways that exceed these limitations.
For each device attached [1..NUMDEV], the associated per-device address configuration must also be programmed, in the
associated register EMEM_ADR_CFG_DEV{N-1}.
The maximum number of row bits carried internally is defined by NV_MC_EMEM_ROW_WIDTH.
The maximum number of address pins is defined by NV_MC_EMEM_ROWPIN_WIDTH.
If not being used to address a device, the chip-select pins may be re-used as row address pins for DDR3.
Valid settings for EMEM_ADR_CFG_DEV* registers should ensure device address width <= bank width + column width +
NV_MC_EMEM_ROW_WIDTH
Boot requirements:

Memory Controller
External Memory Address Configuration, System

EMEM_NUMDEV: [PMC] number of populated DRAM devices.

0 N1 0 = N1
1 = N2
16.7.1.14 MC_EMEM_ADR_CFG_DEV0_0
Configures the density and geometry of the first attached device.
Boot requirements:
Note: DEVSIZE is per subpartition.
External Memory Address Configuration, Device 0

Offset: 0x58 | Read/Write: R/W | Reset: 0x00040202 (0bxxxxxxxxxxxx0100xxxxxx10xxxxx010)
EMEM_DEV0_DEVSIZE: [PMC] density of the first attached DRAM device, used to generate
width of row address.
2 = D16MB
3 = D32MB
4 = D64MB
5 = D128MB
6 = D256MB
19:16 D64MB 7 = D512MB
8 = D1024MB
8 = D1GB
9 = D2048MB
9 = D2GB
10 = D4096MB
11 = D8192MB
12 = D768MB
EMEM_DEV0_BANKWIDTH: [PMC] width of bank address of the first attached DRAM device.
9:8 W2 2 = W2
3 = W3
EMEM_DEV0_COLWIDTH: [PMC] width of column address of the first attached DRAM

device. W8 maps to 1KB page size, W9 to 2KB, W10 to 4KB, etc.
1 = W8
2:0 W9 2 = W9
3 = W10
4 = W11
5 = W12
16.7.1.15 MC_EMEM_ADR_CFG_DEV1_0
Configures the density and geometry of the second attached device, if a second device is populated.
To allow for 2 devices with different column width/bank width to be used without creating holes in the system-level address
map, the DEVSIZE setting of the second device may be smaller than the others to allow for non-powers-of-2 attached memory
sizes.

Memory Controller
Boot requirements:
Note: DEVSIZE is per subpartition.
External Memory Address Configuration, Device 1

Offset: 0x5c | Read/Write: R/W | Reset: 0x00040202 (0bxxxxxxxxxxxx0100xxxxxx10xxxxx010)
EMEM_DEV1_DEVSIZE: [PMC] Density of the second attached DRAM device, used to

generate width of row address.
2 = D16MB
3 = D32MB
4 = D64MB
5 = D128MB
6 = D256MB
19:16 D64MB 7 = D512MB
8 = D1024MB
8 = D1GB
9 = D2048MB
9 = D2GB
10 = D4096MB
11 = D8192MB
12 = D768MB
EMEM_DEV1_BANKWIDTH: [PMC] width of bank address of the second attached DRAM

device.
9:8 W2
2 = W2
3 = W3
EMEM_DEV1_COLWIDTH: [PMC] width of column address of the second attached DRAM

device. W8 maps to 1KB page size, W9 to 2KB, W10 to 4KB, etc.
1 = W8
2:0 W9 2 = W9
3 = W10
4 = W11
5 = W12
16.7.1.16 MC_SECURITY_CFG0_0
Security aperture: Can be only accessed by TrustZone-Secured accesses from the secure clients. Access to this register is
restricted to TrustZone-secured requestors.
Boot requirements: This security configuration register should be saved to SDRAM and restored by the OS during warm
boot.
The global memory client IDs with TrustZone-level security are as follows:
CLIENT ID ID (hex) SWGROUP MODULE PARTITION DESCRIPTION
csr_mpcorelpr 38 (0x26) mpcorelp mpcorelp stop Reads from Cortex-A15
Shadow CPU core via the
L2 cache (Tegra K1 32-bit
only)
csr_mpcorer 39 (0x27) mpcore mpcore ftop Reads from 4 CPU cores
via the L2 cache
csw_mpcorelpw 56 (0x38) mpcorelp mpcorelp stop Writes from Cortex-A15
Shadow CPU core via the
L2 cache (Tegra K1 32-bit
only)
csw_mpcorew 57 (0x39) mpcore mpcore ftop Writes from 4 CPU cores
via the L2 cache

Memory Controller
Secure Region Configuration: Base

Offset: 0x70 | Read/Write: R/W | Secure: Trust Zone Protected | Reset: 0x80000000 (0b100000000000xxxxxxxxxxxxxxxxxxxx)
SECURITY_BOM: SECURITY_BOM is the base of the secured region, limited to MB

granularity. This must point to a region of the physical address map allocated to EMEM for it
to be effective; MC cannot secure address space it does not own. (In other words, this is an
31:20 0x800
absolute address, not an offset.) Above is the list of clients with the TrustZone-security
access. Note that AXICIF clients will adhere to the standard AXI protocol "aprot[1]==0"
indication for secure requests.
Boot requirements:
This security configuration register should be saved to SDRAM and restored by the OS during warm boot.
Secure Region Configuration: Bound

Offset: 0x74 | Read/Write: R/W | Secure: Trust Zone Protected | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxx0000000000000)
SECURITY_SIZE_MB: SECURITY_SIZE_MB is the size, in megabytes, of the secured

12:0 0x0
region. If set to 0, the security check in MC is disabled.
16.7.1.18 MC_EMEM_ARB_CFG_0
General configuration of the External Memory Arbiter.
Boot requirements:
 This arbitration configuration register should be saved to SDRAM and restored by the OS during warm boot.
 During Boot ROM warm boot, this register may be derived from the emcclk and a standard tick-value.
External Memory Arbitration Configuration

Offset: 0x90 | Read/Write: R/W | Reset: 0x00000008 (0b00000000xxx00000xxxxxxx000001000)
EXTRA_TICKS_PER_UPDATE: The number of extra ticks to add every deadline timer

update. Used to keep cycles-per-tick constant when the mcclk period is less than the chosen
wall-clock granularity for the deadline counter. If =0, then every tick increments the deadline
counter by 1; if =1, then every tick increments the deadline counter by 2, etc. Assuming a
target of 30ns-per-tick, some example programming (assumes DIV=2): 10MHz emcclk =>
20:16 0x0 5MHz mcclk => would need to increment deadline counter by 6.67 if using 1 cycle-per-tick =>
or update by 20 every 3 cycles => 3 cycles-per-tick and 19 extra ticks per update. Since
performance is not critical at such slow speeds, rounding errors may be deemed acceptable,
so the previous example may be simpler to program as 1 cycle-per-tick and 5 extra ticks per
update. Another example, the slowest supported clock speed using a 30ns tick that doesn't
distort the tick is: 1.04MHz mcclk => with 31 extra ticks per update and updating every cycle.
CYCLES_PER_UPDATE: The number of mcclk cycles per deadline timer update. The target
wall-clock granularity ("tick") for the deadline counter should be fixed for the design, then the
8:0 0x8 CYCLES_PER_UPDATE should be used to convert the wall-time value into mcclk cycles. All
client latency allowances are also expressed in units of "ticks". Of all deadline-related controls,
only the CYCLES_PER_UPDATE and EXTRA_TICKS_PER_UPDATE values need to be

Memory Controller

updated on a clock-change event. Assuming a target of 30ns per tick, some example
programming (assumes DIV=2): 667MHz emcclk => 333MHz mcclk => 10 cycles per tick;
400MHz emcclk => 200MHz mcclk => 6 cycles-per-tick. Note that value 0x0 is illegal.
16.7.1.19 MC_EMEM_ARB_OUTSTANDING_REQ_0
This register can be used to limit the number of outstanding requests in the arbiter and monitor the count.
If outstanding transaction is greater than the maximum, requests are throttled based on
MC_EMEM_ARB_RING1_THROTTLE_0 register
Boot requirements:
 During Boot ROM section of warm boot, this register may be derived from other MC settings.
External Memory Arbitration Configuration: Outstanding Request Limiter

Offset: 0x94 | Read/Write: R/W | Reset: 0x8XXX0040 (0b10xxxxxxxxxxxxxxxxxxxxx001000000)
LIMIT_OUTSTANDING: when ENABLED, the total number of requests in the arbiter is limited
to the value in ARB_MAX_OUTSTANDING
31 RW ENABLE
0 = DISABLE
1 = ENABLE
LIMIT_DURING_HOLDOFF_OVERRIDE: when DISABLED, override the limiting of

transactions during hold-off to let requests flow freely
30 RW DISABLE
0 = DISABLE
1 = ENABLE
24:16 RO X ARB_OUTSTANDING_COUNT: Current number of outstanding requests
ARB_MAX_OUTSTANDING: The maximum number of requests allowed in the arbiter when

8:0 RW 0x40
LIMIT_OUTSTANDING is set to ENABLE.
16.7.1.20 MC_EMEM_ARB_TIMING_RCD_0
Boot requirements:
 During Boot ROM section of warm boot, this register may be derived from EMC settings using the given equations.
External Memory Arbitration Configuration: DRAM Timing: tRCD

Offset: 0x98 | Read/Write: R/W | Reset: 0x0000003f (0bxxxxxxxxxxxxxxxxxxxxxxxxxx111111)
RCD: The minimum number of cycles between activate commands to the same bank.
5:0 0x3f Program to max (1,ceil(max(EMC.WR_RCD,EMC.RD_RCD)/DIV)-1-1). Note that value 0x0 is
illegal.

Memory Controller
16.7.1.21 MC_EMEM_ARB_TIMING_RP_0
Boot requirements:
External Memory Arbitration Configuration: DRAM Timing : tRP

Offset: 0x9c | Read/Write: R/W | Reset: 0x0000007f (0bxxxxxxxxxxxxxxxxxxxxxxxxx1111111)
RP: The minimum number of cycles between an internal precharge command and an activate
6:0 0x7f command to the same bank. Program to ceil (EMC.RP/DIV)-1+SFA. The combined value of
RAP2PRE+RP 0x0 is illegal; the combined value of WAP2PRE+RP 0x0 is illegal.
16.7.1.22 MC_EMEM_ARB_TIMING_RC_0
Boot requirements:
External Memory Arbitration Configuration: DRAM Timing : tRC

Offset: 0xa0 | Read/Write: R/W | Reset: 0x0000007f (0bxxxxxxxxxxxxxxxxxxxxxxxxx1111111)
RC: This is the minimum number of cycles between activate commands to the same bank.
6:0 0x7f
Program to ceil (max(EMC.RC,(EMC.RAS+EMC.RP))/DIV)-1.
16.7.1.23 MC_EMEM_ARB_TIMING_RAS_0
Boot requirements:
External Memory Arbitration Configuration: DRAM Timing: tRAS

Offset: 0xa4 | Read/Write: R/W | Reset: 0x0000003f (0bxxxxxxxxxxxxxxxxxxxxxxxxxx111111)
RAS: This is the minimum number of cycles between an activate command and a precharge
5:0 0x3f
command to the same bank. Program to ceil (EMC.RAS/DIV)-1-1.

Memory Controller
16.7.1.24 MC_EMEM_ARB_TIMING_FAW_0
Boot requirements:
External Memory Arbitration Configuration: DRAM Timing: tFAW

Offset: 0xa8 | Read/Write: R/W | Reset: 0x0000007f (0bxxxxxxxxxxxxxxxxxxxxxxxxx1111111)
FAW: For 8-bank devices: Only 4 activates may occur within this rolling window. Program to
5:0 0x3f ceil (EMC.TFAW/DIV)-1. Programming this to 0x0 or not programming a device to 4 banks will
turn off this check.
16.7.1.25 MC_EMEM_ARB_TIMING_RRD_0
Boot requirements:
External Memory Arbitration Configuration: DRAM Timing: tRRD

Offset: 0xac | Read/Write: R/W | Reset: 0x0000000f (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111)
RRD: The minimum number of cycles between an activate command and an activate
3:0 0xf
command to a different bank. Program to ceil (EMC.RRD/DIV)-1.
16.7.1.26 MC_EMEM_ARB_TIMING_RAP2PRE_0
Boot requirements:
External Memory Arbitration Configuration: DRAM Timing: tRAP2PRE

Offset: 0xb0 | Read/Write: R/W | Reset: 0x0000003f (0bxxxxxxxxxxxxxxxxxxxxxxxxxx111111)
RAP2PRE: The number of cycles between a read command with auto-precharge and the
5:0 0x3f internal precharge command generated by the DRAM. Program to ceil (EMC_R2P/DIV).
Note that: the combined value of RAP2PRE+RP 0x0 is illegal.

Memory Controller
16.7.1.27 MC_EMEM_ARB_TIMING_WAP2PRE_0
Boot requirements:
External Memory Arbitration Configuration: DRAM Timing: tWAP2PRE

Offset: 0xb4 | Read/Write: R/W | Reset: 0x0000007f (0bxxxxxxxxxxxxxxxxxxxxxxxxx1111111)
WAP2PRE: The number of cycles between a write command with auto-precharge and the
6:0 0x7f internal precharge command generated by the DRAM. Program to ceil (EMC_W2P/DIV).
Note that: the combined value of WAP2PRE+RP 0x0 is illegal.
16.7.1.28 MC_EMEM_ARB_TIMING_R2R_0
Boot requirements:
External Memory Arbitration Configuration: DRAM Timing: tR2R

Offset: 0xb8 | Read/Write: R/W | Reset: 0x0000001f (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx11111)
R2R: The number of cycles between consecutive read commands to different devices
4:0 0x1f
(different chip selects). Program to ceil (EMC.REXT/DIV)-1+OTFA+SFA.
16.7.1.29 MC_EMEM_ARB_TIMING_W2W_0
Boot requirements:
External Memory Arbitration Configuration: DRAM Timing: tW2W

Offset: 0xbc | Read/Write: R/W | Reset: 0x0000001f (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx11111)
W2W: The number of cycles between consecutive write commands to different devices
4:0 0x1f
(different chip selects). Program to ceil (EMC.WEXT/DIV)-1+SFA.

Memory Controller
16.7.1.30 MC_EMEM_ARB_TIMING_R2W_0
Boot requirements:
External Memory Arbitration Configuration: DRAM Timing: tR2W

Offset: 0xc0 | Read/Write: R/W | Reset: 0x0000003f (0bxxxxxxxxxxxxxxxxxxxxxxxxxx111111)
R2W: The number of cycles to turn the bus from reads to writes. Program to ceil
5:0 0x3f
(EMC.R2W/DIV)-1+OTFA+SFA.
16.7.1.31 MC_EMEM_ARB_TIMING_W2R_0
Boot requirements:
External Memory Arbitration Configuration: DRAM Timing: tW2R

Offset: 0xc4 | Read/Write: R/W | Reset: 0x0000003f (0bxxxxxxxxxxxxxxxxxxxxxxxxxx111111)
W2R: The number of cycles to turn the bus from reads to writes. Program to ceil
5:0 0x3f
(EMC.W2R/DIV)-1+SFA.
16.7.1.32 MC_EMEM_ARB_DA_TURNS_0
The direction arbiter attempts to choose the highest efficiency (i.e., lowest bubbles) direction to open pages next. While
programming this register incorrectly may lower performance, it should never cause chip-hangs since the EMC always controls
the final DRAM timing decisions. This register should be reprogrammed after clock-change events to bring the computed
values back in alignment with EMC's register values. These turn costs are deliberately not computed in hardware to provide
better flexibility to tweak arbiter performance.
The configuration registers for turns for DA are separate from the timing registers to allow for flexibility in the programming.
Boot requirements:
 During Boot ROM section of warm boot, this register may be derived from MC settings using the given equations.
External Memory Arbitration Configuration: Direction Arbiter: Turns

Offset: 0xd0 | Read/Write: R/W | Reset: 0x0f0f0205 (0b00001111000011110000001000000101)

Memory Controller
W2R_TURN: Bubbles produced by a write to read bus turn. Approximately

31:24 0xf
MC_EMEM_ARB_TIMING_W2R.
R2W_TURN: Bubbles produced by a read to write bus turn. Approximately

23:16 0xf
MC_EMEM_ARB_TIMING_R2W.
W2W_TURN: Bubbles produced by a write to write (other device) bus turn. Approximately
15:8 0x2
MC_EMEM_ARB_TIMING_W2W.
R2R_TURN: Bubbles produced by a read to read (other device) bus turn. Approximately
7:0 0x5
MC_EMEM_ARB_TIMING_R2R.
16.7.1.33 MC_EMEM_ARB_DA_COVERS_0
The direction arbiter attempts to choose the highest efficiency (i.e., lowest bubbles) direction to open pages next. While
programming this register incorrectly may lower performance, it should never cause chip-hangs since the EMC always controls
the final DRAM timing decisions. This register should be reprogrammed after clock-change events to bring the computed
values back in alignment with EMC's register values. These cover costs are deliberately not computed in hardware to provide
better flexibility to tweak arbiter performance.
Boot requirements:
 During Boot ROM section of warm boot, this register may be derived from MC settings using the given equations.
External Memory Arbitration Configuration: Direction Arbiter: Covers

Offset: 0xd4 | Read/Write: R/W | Reset: 0x000f0f0f (0bxxxxxxxx000011110000111100001111)
RCD_W_COVER: Cost to cover the activate-to-write delay. Approximately ceil ((EMC.RTP +

23:16 0xf
EMC.RP + EMC.RD_RCD)/DIV)-1.
RCD_R_COVER: Cost to cover the activate-to-read delay. Approximately ceil ((EMC.WTP +

15:8 0xf
EMC.RP + EMC.WR_RCD)/DIV)-1.
RC_COVER: Cost to cover the activate-to-activate delay. Approximately

7:0 0xf
MC_EMEM_ARB_TIMING_RC.
16.7.1.34 MC_EMEM_ARB_MISC0_0
BC2AA_HOLDOFF: In the case where the currently-open pages have more work pending than the time it would take to open
another page, it is better to hold off opening that page until it is truly needed. The Best-bank Cache computes the pending
work and compares it to this threshold and advises the Activation Arbiter to hold-off.
Priority Inversion: In general, if the arbiter is working on a lower-priority request that blocks a higher-priority request, these
thresholds are used to limit the number of low-priority requests we will service before the arbiter will interrupt the lower-priority
traffic to start servicing the higher-priority traffic.
The priority classes are (in increasing priority order): Low (! expired), High (expired), HighIso.
There are three ways priority can be inverted: Bank Activation, Bus Direction, and Refresh:
Bank Activation: If an unexpired request to bank A, row R currently holds the page open, and a request to bank A, row S
expires, the Transaction Arbiter must make a decision whether to finish out the work for row R or to interrupt that transfer to
immediately service row S. The TA makes this decision based on the remaining work for row R and whether row S is for an
isochronous client, and the two PRIORITY_INVERSION thresholds.

Memory Controller
Bus Direction: If the Transaction Arbiter is currently working on expired requests in direction P, and requests are also expired
(or expired-iso) in direction Q, the Transaction Arbiter must make a decision whether to continue working in direction P or
switch the bus to direction Q. The Transaction Arbiter will service at maximum PRIORITY_INVERSION_THRESHOLD (or
_INVERSION_ISO_THRESHOLD) requests in direction P before switching to direction Q.
Refresh: If the Transaction Arbiter is currently working on requests, and EMC asks to inject a refresh, the Transaction Arbiter
must decide whether it is more efficient (overall) to close the pages immediately or to finish the pages and then close them.
Depending on the setting of the REFRESH_ACK_THRESHOLD_USAGE configuration bit (in EMEM_ARB_MISC1 register,
below), the Transaction Arbiter will either choose to close the page immediately (NONE), close the page immediately if its
length is over the iso threshold (ISO), or close the page immediately if its length is over the normal threshold (NORMAL). If the
length is less than the chosen threshold, the Transaction Arbiter will service all remaining requests to the page before
acknowledging the EMC refresh request.
When in DDR3 coalesce-for-performance mode, the arbiters will monitor the traffic patterns and might halve the priority
inversion thresholds if they detect the current traffic is not coalescing efficiently. When in MC_EMC_SAME_FREQ mode, the
priority inversion thresholds should be set to half of their non-same-frequency values.
Boot requirements:
 The MC_EMC_SAME_FREQ field should be saved to scratch registers and restored by the Boot ROM during warm
boot.
 The other fields of this register should be saved to SDRAM and restored by the OS during warm boot.
 During Boot ROM section of warm boot, this register may be derived from other settings.
External Memory Arbitration Configuration: Miscellaneous Thresholds (0)

Offset: 0xd8 | Read/Write: R/W | Reset: 0x720a4010 (0bx1110010000010100100000000010000)
ATOMS_PER_DVFS_PULSE: [PMC] ATOMS_PER_DVFS_PULSE is used to control the rate

at which the MC updates the sys_stats_mon outputs. The MC will toggle the sys_stats_mon
outputs for every 2^(ATOMS_PER_DVFS_PULSE+1) atoms of traffic, where an atom is
30:28 0x7 defined as any transaction. Note that 16B, 32B, and 64B requests consume the same amount
of memory bus resources. So, in this context, an atom is defined as any request and not
cumulative 64B sized transactions. The maximum ATOMS_PER_DVFS_PULSEsetting
supported is the reset value, also known as NV_MC_EMEM_DVFS_CNTR_CFG_RESET.
MC_EMC_SAME_FREQ: [PMC] Used in conjunction with

EMEM_ARB_MISC1.COALESCE_FOR_PERFORMANCE to configure how often the MC can
send EMC a data request, should be configured to mirror CAR's
CLK_SOURCE_EMC.MC_EMC_SAME_FREQ.
If configured to DIV=2 BL=4, then the MC can send a data request every cycle.
If configured to DIV=1 BL=4, then the MC can send a data request every other cycle.
27 DISABLE
If configured to DIV=2 BL!=4, then MC can send a data request every other cycle.
If configured to DIV=1 BL!=4, then the MC can send a data request once every four cycles.
0 = MC is 1/2 the frequency of EMC (DIV=2).
1 = MC is the same frequency of EMC (DIV=1).
0 = DISABLE
1 = ENABLE
EXPIRING_SOON_SLACK_THRESHOLD: Slack threshold below which an isochronous

request is considered to be expiring "soon". Used to de-assert mc2emc_idle signal early to
wake EMC out of power-down or self-refresh. If using EMC's Dynamic Self Refresh features,
26:21 0x10
set this to the ticks needed to cover exit self-refresh delay; otherwise, if using EMC's ACPD
feature, set to the ticks needed to cover exit power-down delay; if neither power-saving feature
is being used, the programming of this threshold should have no effect.

Memory Controller
PRIORITY_INVERSION_ISO_THRESHOLD: Bank Activation: maximum number of unexpired

or expired-but-not-isochronous requests that can be serviced before switching to expired
isochronous traffic. Bus Direction: maximum number of requests in direction P that can be
20:16 0xa
serviced before switching to expired-isochronous traffic in direction Q. Refresh: maximum
number of requests that can be serviced before refresh is sent. Values <= 0x2 disable the
feature. Values < 0x6 should be avoided if coalescing for performance.
EMC_REQ_B2B_XFER: When enabled, the MC allows EMC transactions on back-to-back

clocks regardless of EMC consumption bandwidth
15 DISABLE
0 = DISABLE
1 = ENABLE
PRIORITY_INVERSION_THRESHOLD: Bank Activation: maximum number of unexpired

requests that can be serviced before switching to expired traffic. Bus Direction: maximum
number of requests in direction P that can be serviced before switching to expired traffic in
14:8 0x40
direction Q. Refresh: maximum number of requests that can be serviced before refresh is
sent. Values <= 0x2 disable the feature. Values < 0x6 should be avoided if coalescing for
performance.
BC2AA_HOLDOFF_THRESHOLD: If the pending work is greater than this value, hold off on
7:0 0x10 activations. Generally should be set to match the page-opening cost:
MC_EMEM_ARB_TIMING_RC+1.
16.7.1.35 MC_EMEM_ARB_MISC1_0
Two DVFS counters exist in the "NV_MC_ARB_EMEM_stats.v" module: one for all requests and another for CPU-only
transactions. Both of these are down counters which decrement for each transaction atom on mcclk.
When these counters reach zero, a single mcclk pulse is generated, and the counters reinitialize to a value of
((2^(ATOMS_PER_DVFS_PULSE+1))-1). The single mcclk pulse that is generated (when the counters reach zero) gets
synchronized to sclk (system clock) through a cross-clock domain FIFO control module, which has a minimum response time
requirement of (4 * sclk_period + 4 * mcclk_period). Therefore, ATOMS_PER_DVFS_PULSE should never be set such that
((2^(ATOMS_PER_DVFS_PULSE+1)) * mcclk_period) is less than (4 * sclk_period + 4 * mcclk_period).
This translates to the following rule for setting the minimum value of ATOMS_PER_DVFS_PULSE:
ATOMS_PER_DVFS_PULSE >= log2((4 * sclk_period/mcclk_period) + 4) - 1
Boot requirements:
 The COALESCE_FOR_PERFORMANCE field should be saved to scratch registers and restored by the Boot ROM
during warm boot. It may also be derived from EMC settings.
 The other fields of this register should be saved to SDRAM and restored by the OS during warm boot.

Memory Controller
External Memory Arbitration Configuration: Miscellaneous Thresholds

Offset: 0xdc | Read/Write: R/W | Reset: 0x80a00002 (0b1000xx00101xxxxxxxx000000000xx10) | Default: 0x00000000
DEADLOCK_PREVENTION_SLACK_THRESHOLD: If the
slack at the head of any bank-queue, or any of the slacks in
the hit-under-miss FIFO is less than -(2^threshold),
backpressure the input to the arbiter until the violating slack
values have been arbitrated. This is intended to: (a) avoid
deadline-wrapping in heavily backpressured corner-cases and
31:28 0x8 NONE
(b) quickly get such cases back into high-efficiency arbitration.
Value of 0x0 disables the feature. The reset value is
NV_MC_EMEM_DL_WIDTH-1. Behavior with values greater
than or equal to NV_MC_EMEM_DL_WIDTH is UNDEFINED.
If the threshold is reached, ARBITRATION_EMEM_INT will
fire.
REFRESH_ACK_THRESHOLD_USAGE: Determines which

thresholds (if any) the refresh-acknowledge signal will use to
determine how to close all pages after EMC has requested a
25:24 NORMAL NONE refresh.
0 = NORMAL : Use priority-inversion threshold
1 = ISO : Use priority-inversion-ISO threshold
2 = NONE : Force a precharge immediately to close the page
EXPIRING_SOON_SLACK_THRESHOLD_PD: [PMC] Slack

threshold below which an isochronous request is considered
to be expiring "soon". Used to deassert the mc2emc_idle_pd
signal early to wake the EMC out of power-down.
(EXPIRING_SOON_SLACK_THRESHOLD controls exit from
self-refresh.) This register should be set to the ticks needed to
cover the exit power-down delay. If the available choices are
not sufficient, the value should be set in
EXPIRING_SOON_SLACK_THRESHOLD and this register
23:21 USE_EXPIRING_SOON_SLACK_THRESHOLD NONE should be set to
USE_EXPIRING_SOON_SLACK_THRESHOLD
0 = ZERO_TICKS : 0 tick threshold for PD expiring soon
1 = ONE_TICK: 1 tick threshold for PD expiring soon
2 = TWO_TICKS: 2 tick threshold for PD expiring soon
3 = FOUR_TICKS: 4 tick threshold for PD expiring soon
4 = EIGHT_TICKS: 8 tick threshold for PD expiring soon
5 = USE_EXPIRING_SOON_SLACK_THRESHOLD: Use the
setting in EXPIRING_SOON_SLACK_THRESHOLD to control
mc2emc_idle_pd
ALT_DEADLOCK_PREVENTION_SLACK_THRESHOLD:
[PMC] Use the absolute value of deadlock prevention slack
12:4 0x0 0x0 threshold instead of 2^n format. Note that the
DEADLOCK_PREVENTION_SLACK_THRESHOLD field still
needs to be programmed along with this one (for example, 7).
ALLOW_BCA_HOLDOFF_WHEN_EXP: [PMC] When

enabled, allows BCA holdoff to occur even when expired
1 ENABLE NONE requests are present.
0 = DISABLE
1 = ENABLE
BLOCK_LP_CPU_RD_IF_SMMU_INP_HP: [PMC] When

enabled, low priority (due to DDA) CPU reads get blocked
when the SMMU output is high priority and a request is
0 DISABLE 0x0
present at the input to the SMMU.
0 = DISABLE
1 = ENABLE

Memory Controller
16.7.1.36 MC_EMEM_ARB_RING1_THROTTLE_0
External Memory Arbitration Configuration: Snap Arbiter Throttle

Ring1 Snap Arbiter Throttle - Inserts some number of stall cycles at Ring1 after every request.
Throttle cycle count varies whether outstanding_request count is below (LOW) or above (HIGH) the max_outstanding
threshold.
Boot requirements: During Boot ROM section of warm boot, this register may be derived from other settings.
Offset: 0xe0 | Read/Write: R/W | Reset: 0x001f0000 (0bxxxxxxxxxxx11111xxxxxxxxxxx00000)
RING1_THROTTLE_CYCLES_HIGH: Cycles of throttle after each request when outstanding

20:16 0x1f
transaction count is greater than or equal to threshold.
RING1_THROTTLE_CYCLES_LOW: Cycles of throttle after each request when outstanding

4:0 0x0
transaction count is below threshold. Suggested programming: (DIV==1)? 1 : 0.
16.7.1.37 MC_EMEM_ARB_RING3_THROTTLE_0

Highest Ring Snap Arbiter Throttle - Although called ring3, this register works on the highest ring.
Boot requirements: This register should be saved in the SDRAM and restored by the OS during warm boot.
Offset: 0xe4 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxx00000xxxxxxxxxxx00000)
4:0 0x0 RING3_THROTTLE_CYCLES: Cycles of throttle after each request.
16.7.1.38 MC_EMEM_ARB_OVERRIDE_0
External Memory Arbitration Configuration: Feature Overrides

Boot requirements:
 Some fields of this register should be saved in the scratch registers and restored by the Boot ROM during warm boot.
 This register should be saved in the SDRAM and restored by the OS during warm boot.
Offset: 0xe8 | Read/Write: R/W | Reset: 0x10000000 (0b0xx100xx0000000000000000xxx0xxxx)
31 DISABLE ARB_HUM_FIFO_DEADLOCK_CHECK_OVERRIDE
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
28 ENABLE ARB_EMEM_SPO_OVERRIDE
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
27 DISABLE ARB_EMEM_AP_OVERRIDE
0 = DISABLE
1 = ENABLE

Memory Controller

1 = OVERRIDE
26 DISABLE ARB_HUM_FIFO_OVERRIDE
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
23 DISABLE ISO_TA_OVERRIDE
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
22 DISABLE ISO_DA_OVERRIDE
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
21 DISABLE ISO_BC_INHERIT_ON_PRIINV_OVERRIDE
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
20 DISABLE ISO_BC_CAUSE_PRIINV_OVERRIDE
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
19 DISABLE ISO_BA_OVERRIDE
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
18 DISABLE ISO_AA_OVERRIDE
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
17 DISABLE ARB_EMEM_BUBBLECALC_OVERRIDE:
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
16 DISABLE ALLOC_ONE_BQ_PER_CLIENT:
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
15 DISABLE PRIORITY_INVERSION_ISO_THRESHOLD_BUS_OVERRIDE:
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
14 DISABLE PRIORITY_INVERSION_ISO_THRESHOLD_BANK_OVERRIDE:
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
13 DISABLE PRIORITY_INVERSION_THRESHOLD_BUS_OVERRIDE:
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
12 DISABLE PRIORITY_INVERSION_THRESHOLD_BANK_OVERRIDE:
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
11 DISABLE PRIORITY_INVERSION_EQ_PRI_LEN_LIMIT_OVERRIDE:
0 = DISABLE
1 = ENABLE
1 = OVERRIDE

Memory Controller
10 DISABLE OBSERVED_DIRECTION_OVERRIDE:
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
9 DISABLE BC2AA_HOLDOFF_OVERRIDE:
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
8 DISABLE TS2AA_HOLDOFF_OVERRIDE:
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
4 DISABLE EXPIRE_UPDATE_OVERRIDE:
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
16.7.1.39 MC_EMEM_ARB_RSV_0
EMEM Arbiter Reserved

Boot requirements:
 Some fields of this register should be saved in the scratch registers and restored by the Boot ROM during warm boot.
Offset: 0xec | Read/Write: R/W | Reset: 0xff00ff00 (0b11111111000000001111111100000000)
31:24 0xff EMEM_ARB_RESERVED_BYTE3
23:16 0x0 EMEM_ARB_RESERVED_BYTE2
15:8 0xff EMEM_ARB_RESERVED_BYTE1
7:0 0x0 EMEM_ARB_RESERVED_BYTE0
16.7.1.40 MC_CLKEN_OVERRIDE_0
Second-Level Clock Enable Overrides

Boot requirements: This register should be saved in the SDRAM and restored by the OS during warm boot.
Offset: 0xf4 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxx00000x00x0)
9 CLK_GATED WCAM_CLKEN_OVR :
0 = CLK_GATED
1 = CLK_ALWAYS_ON
0 = DISABLE
1 = ENABLE
0 = DISABLED
1 = ENABLED
8 CLK_GATED PTC_CACHE_CLKEN_OVR :
0 = CLK_GATED
1 = CLK_ALWAYS_ON
0 = DISABLE

Memory Controller

1 = ENABLE
0 = DISABLED
1 = ENABLED
7 CLK_GATED PTC_CLKEN_OVR :
0 = CLK_GATED
1 = CLK_ALWAYS_ON
0 = DISABLE
1 = ENABLE
0 = DISABLED
1 = ENABLED
6 CLK_GATED TLB_CLKEN_OVR :
0 = CLK_GATED
1 = CLK_ALWAYS_ON
0 = DISABLE
1 = ENABLE
0 = DISABLED
1 = ENABLED
5 CLK_GATED WB_CLKEN_OVR :
0 = CLK_GATED
1 = CLK_ALWAYS_ON
0 = DISABLE
1 = ENABLE
0 = DISABLED
1 = ENABLED
3 CLK_GATED REGS_CLKEN_OVR :
0 = CLK_GATED
1 = CLK_ALWAYS_ON
0 = DISABLE
1 = ENABLE
0 = DISABLED
1 = ENABLED
2 CLK_GATED EARB_CLKEN_OVR :
0 = CLK_GATED
1 = CLK_ALWAYS_ON
0 = DISABLE
1 = ENABLE
0 = DISABLED
1 = ENABLED
0 CLK_GATED CIF_CLKEN_OVR :
0 = CLK_GATED
1 = CLK_ALWAYS_ON
0 = DISABLE
1 = ENABLE
0 = DISABLED
1 = ENABLED
16.7.1.41 MC_TIMING_CONTROL_0
Shadowed Registers: Update Trigger

Boot requirements: Writing this register with 0x1 will trigger a timing update event, which should be used in both warm boot
and cold boot sequences.
Offset: 0xfc | Read/Write: R/W | Reset: 0x0000000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
0 X TIMING_UPDATE

Memory Controller
16.7.1.42 MC_STAT_CONTROL_0
Statistics: Control
3 DISABLE EMC_PM_STOP_TRIGGER:
0 = DISABLE
1 = ENABLE
2 DISABLE EMC_PM_START_TRIGGER:
0 = DISABLE
1 = ENABLE
1:0 RST EMC_GATHER:

0 = RST
2 = DISABLE
3 = ENABLE
16.7.1.43 MC_CLIENT_HOTRESET_CTRL_0
Writing FLUSH_ENABLE to a bit in this register causes a flush to be performed on all of the clients for the selected swname.
The status of the flush (done/in progress) can be monitored in the CLIENT_HOTRESET_STATUS register.
A proper client reset sequence is as follows:
1. Set the appropriate FLUSH_ENABLE bit in the CLIENT_HOTRESET_CTRL register to block further access by the
client, and start the flush process.
2. Poll the CLIENT_HOTRESET_STATUS register until the appropriate bit returns FLUSH_DONE.
3. Clear module bit in the CLK_RST_CONTROLLER_RST_DEVICES_* register to reset the module.
4. Set module bit in the CLK_RST_CONTROLLER_RST_DEVICES_* register to release the module reset.
5. Clear the appropriate FLUSH_ENABLE bit in the CLIENT_HOTRESET_CTRL register to allow transactions to flow.
Memory Client Hot Reset Control Register

Offset: 0x200 | Read/Write: R/W | Reset: 0x00000000 (0b000xxxxxx000000000xx000000xx0000
SDMMC3A_FLUSH_ENABLE:
0 = DISABLE
31 DISABLE 1 = ENABLE
0 = DISABLED
1 = ENABLED
0 = DISABLE
0 = DISABLED
1 = ENABLED
0 = DISABLE
0 = DISABLED
1 = ENABLED
TSEC_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED

Memory Controller
XUSB_DEV_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
XUSB_HOST_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
VIC_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
VI_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
VDE_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
SATA_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
PPCS_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
MSENC _FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
MPCORELP_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
MPCORE_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
ISP2_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
HDA_FLUSH_ENABLE:
1 = ENABLE
0 = DISABLED

Memory Controller

1 = ENABLED
HC_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
DCB_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
DC_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
AVPC_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
AFI_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
16.7.1.44 MC_CLIENT_HOTRESET_STATUS_0
Contains one bit for each swname, indicating the status of any flush that has been requested in the
CLIENT_HOTRESET_CTRL register.
Note: If no flush has been requested, this register returns FLUSH_DONE.
Memory Client Hot Reset Status Register

Offset: 0x204 | Read/Write: RO | Reset: 0xX0XXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
SDMMC3A_HOTRESET_STATUS:
31 X 1 = FLUSH_DONE
0 = FLUSH_IN_PROGRESS
30 X 1 = FLUSH_DONE
29 X 1 = FLUSH_DONE
TSEC_HOTRESET_STATUS:
22 X 1 = FLUSH_DONE
XUSB_DEV_HOTRESET_STATUS:
20 X 1 = FLUSH_DONE
19 X XUSB_HOST_HOTRESET_STATUS:
1 = FLUSH_DONE

Memory Controller

VIC_HOTRESET_STATUS:
18 X 1 = FLUSH_DONE
VI_HOTRESET_STATUS:
17 X 1 = FLUSH_DONE
VDE_HOTRESET_STATUS:
16 X 1 = FLUSH_DONE
SATA_HOTRESET_STATUS:
15 X 1 = FLUSH_DONE
PPCS_HOTRESET_STATUS:
14 X 1 = FLUSH_DONE
MSENC_HOTRESET_STATUS:
11 X 1 = FLUSH_DONE
MPCORELP_HOTRESET_STATUS:
10 X 1 = FLUSH_DONE
MPCORE_HOTRESET_STATUS:
9 X 1 = FLUSH_DONE
ISP2_HOTRESET_STATUS:
8 X 1 = FLUSH_DONE
HDA_HOTRESET_STATUS:
7 X 1 = FLUSH_DONE
HC_HOTRESET_STATUS:
6 X 1 = FLUSH_DONE
DCB_HOTRESET_STATUS:
3 X 1 = FLUSH_DONE
DC_HOTRESET_STATUS:
2 X 1 = FLUSH_DONE
AVPC_HOTRESET_STATUS:
1 X 1 = FLUSH_DONE
AFI_HOTRESET_STATUS:
0 X 1 = FLUSH_DONE
16.7.1.45 MC_EMEM_ARB_ISOCHRONOUS_0_0
Controls whether a client is considered to be an isochronous client for EMEM arbitration. If a client is configured to be
isochronous, the arbiter will favor expired isochronous requests over requests of any other type. This applies to arbitration for:
best-bank arbiter (BA), activation arbiter (AA), direction arbiter (DA), and transaction arbiter (TA).

Memory Controller
Boot requirements:
Per-Client Isochronous Settings

Offset: 0x208 | Read/Write: R/W | Reset: 0x0023007e (0b0000xxxx001xxx1100xxxxxxx1111110
ISO_SATAR: client satar is treated as an isochronous client

1 = ENABLE
ISO_PPCSAHBSLVR: client ppcsahbslvr is treated as an isochronous client

1 = ENABLE
ISO_PPCSAHBDMAR: client ppcsahbdmar is treated as an isochronous client

1 = ENABLE
ISO_MSENCSRD: client msencsrd is treated as an isochronous client

1 = ENABLE
ISO_HOST1XR: client host1xr is treated as an isochronous client

1 = ENABLE
ISO_HOST1XDMAR: client host1xdmar is treated as an isochronous client

1 = ENABLE
ISO_HDAR: client hdar is treated as an isochronous client

1 = ENABLE
ISO_DISPLAYHCB: client displayhcb is treated as an isochronous client

17 0x1 0 = DISABLE
1 = ENABLE
ISO_DISPLAYHC: client displayhc is treated as an isochronous client

16 0x1 0 = DISABLE
1 = ENABLE
ISO_AVPCARM7R: client avpcarm7r is treated as an isochronous client

1 = ENABLE
ISO_AFIR: client afir is treated as an isochronous client

1 = ENABLE
ISO_DISPLAY0CB: client display0cb is treated as an isochronous client

6 0x1 0 = DISABLE
1 = ENABLE
ISO_DISPLAY0C: client display0c is treated as an isochronous client

5 0x1 0 = DISABLE
1 = ENABLE
ISO_DISPLAY0BB: client display0bb is treated as an isochronous client

4 0x1 0 = DISABLE
1 = ENABLE
ISO_DISPLAY0B: client display0b is treated as an isochronous client

3 0x1 0 = DISABLE
1 = ENABLE
2 0x1 ISO_DISPLAY0AB: client display0ab is treated as an isochronous client

0 = DISABLE

Memory Controller

1 = ENABLE
ISO_DISPLAY0A: client display0a is treated as an isochronous client

1 0x1 0 = DISABLE
1 = ENABLE
ISO_PTCR: client ptcr is treated as an isochronous client

0 0x1 0 = DISABLE
1 = ENABLE
isochronous, the arbiter will favor expired isochronous requests over requests of any other type.
This applies to arbitration for: best-bank arbiter (BA), activation arbiter (AA), direction arbiter (DA), and transaction arbiter (TA).
Boot requirements:
Per-client isochronous settings

Offset: 0x20c | Read/Write: R/W | Reset: 0x00000000 (0b00000x00x00xx00xxxxx0xxx000000xx
ISO_VDEDBGW: client vdedbgw is treated as an isochronous client

1 = ENABLE
ISO_VDEBSEVW: client vdebsevw is treated as an isochronous client

1 = ENABLE
ISO_SATAW: client sataw is treated as an isochronous client

1 = ENABLE
ISO_PPCSAHBSLVW: client ppcsahbslvw is treated as an isochronous client

1 = ENABLE
ISO_PPCSAHBDMAW: client ppcsahbdmaw is treated as an isochronous client

1 = ENABLE
ISO_MPCOREW: client mpcorew is treated as an isochronous client

1 = ENABLE
ISO_MPCORELPW: client mpcorelpw is treated as an isochronous client

1 = ENABLE
ISO_HOST1XW: client host1xw is treated as an isochronous client

1 = ENABLE
ISO_HDAW: client hdaw is treated as an isochronous client

1 = ENABLE
ISO_AVPCARM7W: client avpcarm7w is treated as an isochronous client

1 = ENABLE
17 DISABLE ISO_AFIW: client afiw is treated as an isochronous client

Memory Controller

0 = DISABLE
1 = ENABLE
ISO_MSENCSWR: client msencswr is treated as an isochronous client

1 = ENABLE
ISO_MPCORER: client mpcorer is treated as an isochronous client

1 = ENABLE
ISO_MPCORELPR: client mpcorelpr is treated as an isochronous client

1 = ENABLE
ISO_VDETPER: client vdetper is treated as an isochronous client

1 = ENABLE
ISO_VDEMCER: client vdemcer is treated as an isochronous client

1 = ENABLE
ISO_VDEMBER: client vdember is treated as an isochronous client

1 = ENABLE
ISO_VDEBSEVR: client vdebsevr is treated as an isochronous client

1 = ENABLE
isochronous, the arbiter will favor expired isochronous requests over requests of any other type.
This applies to arbitration for: best-bank arbiter (BA), activation arbiter (AA), direction arbiter (DA), and transaction arbiter (TA).
Boot requirements:

Offset: 0x210 | Read/Write: R/W | Reset: 0x04000000 (0bxxxxx1000000xx00x00000xx00x0xx00
ISO_DISPLAYT: Client displayt is treated as an isochronous client

26 0x1 0 = DISABLE
1 = ENABLE
ISO_GPUSWR: Client gpuswr is treated as an isochronous client

1 = ENABLE
ISO_GPUSRD: Client gpusrd is treated as an isochronous client

1 = ENABLE
ISO_TSECSWR: Client tsecswr is treated as an isochronous client

1 = ENABLE
ISO_TSECSRD: Client tsecsrd is treated as an isochronous client

20 DISABLE
0 = DISABLE

Memory Controller

1 = ENABLE
ISO_ISPWBB: Client emucifwispwbb is treated as an isochronous client

1 = ENABLE
ISO_ISPWAB: Client ispwab is treated as an isochronous client

1 = ENABLE
ISO_ISPRAB: Client isprab is treated as an isochronous client

1 = ENABLE
ISO_XUSB_DEVW: Client xusb_devw is treated as an isochronous client

1 = ENABLE
ISO_XUSB_DEVR: Client xusb_devr is treated as an isochronous client

1 = ENABLE
ISO_XUSB_HOSTW: Client xusb_hostw is treated as an isochronous client

1 = ENABLE
ISO_XUSB_HOSTR: Client xusb_hostr is treated as an isochronous client

1 = ENABLE
ISO_ISPWB: Client ispwb is treated as an isochronous client

1 = ENABLE
ISO_ISPWA: Client ispwa is treated as an isochronous client

1 = ENABLE
ISO_ISPRA: Client ispra is treated as an isochronous client

1 = ENABLE
ISO_VDETPMW: client vdetpmw is treated as an isochronous client

1 = ENABLE
ISO_VDEMBEW: client vdembew is treated as an isochronous client

1 = ENABLE
isochronous, the arbiter will favor expired isochronous requests over requests of any other type. This applies to arbitration for:
best-bank arbiter (BA), activation arbiter (AA), direction arbiter (DA), and transaction arbiter (TA).
Boot requirements:

Offset: 0x214 | Read/Write: R/W | Reset: 0x00080000 (0bxxxxxxxxxxxx10xxxx00xxxx00000000)
19 0x1 ISO_DISPLAYD: Client displayd is treated as an isochronous client

0 = DISABLE

Memory Controller

1 = ENABLE
ISO_VIW: Client viw is treated as an isochronous client

1 = ENABLE
ISO_VICSWR: Client vicswr is treated as an isochronous client

1 = ENABLE
ISO_VICSRD: Client vicsrd is treated as an isochronous client

1 = ENABLE
ISO_SDMMCWAB: Client sdmmcwab is treated as an isochronous client

1 = ENABLE
ISO_SDMMCW: Client sdmmcw is treated as an isochronous client

1 = ENABLE
ISO_SDMMCWAA: Client sdmmcwaa is treated as an isochronous client

1 = ENABLE
ISO_SDMMCWA: Client sdmmcwa is treated as an isochronous client

1 = ENABLE
ISO_SDMMCRAB: Client sdmmcrab is treated as an isochronous client

1 = ENABLE
ISO_SDMMCR: Client sdmmcr is treated as an isochronous client

1 = ENABLE
ISO_SDMMCRAA: Client sdmmcraa is treated as an isochronous client

1 = ENABLE
ISO_SDMMCRA: Client sdmmcra is treated as an isochronous client

1 = ENABLE
16.7.1.49 MC_EMEM_ARB_HYSTERESIS_0_0
Controls whether a client is considered to be a hysteresis client for EMEM arbitration. If a client is NOT marked hysteresis, it
will immediately cause the arbiter to turn off ts2aa_holdoff (see the comments for EMEM_ARB_OVERRIDE for further
description of ts2aa_holdoff functionality).
Boot requirements:
Per-Client Hysteresis Settings

Offset: 0x218 | Read/Write: R/W | Reset: 0x0003007e (0b0000xxxx000xxx1100xxxxxxx1111110)
HYST_SATAR: client satar is treated as a hysteresis client

1 = ENABLE
30 DISABLE HYST_PPCSAHBSLVR: client ppcsahbslvr is treated as a hysteresis client

0 = DISABLE

Memory Controller

1 = ENABLE
HYST_PPCSAHBDMAR: client ppcsahbdmar is treated as a hysteresis client

1 = ENABLE
HYST_MSENCSRD: client msencsrd is treated as a hysteresis client

1 = ENABLE
HYST_HOST1XR: client host1xr is treated as a hysteresis client

1 = ENABLE
HYST_HOST1XDMAR: client host1xdmar is treated as a hysteresis client

1 = ENABLE
HYST_HDAR: client hdar is treated as a hysteresis client

1 = ENABLE
HYST_DISPLAYHCB: client displayhcb is treated as a hysteresis client

17 0x1 0 = DISABLE
1 = ENABLE
HYST_DISPLAYHC: client displayhc is treated as a hysteresis client

16 0x1 0 = DISABLE
1 = ENABLE
HYST_AVPCARM7R: client avpcarm7r is treated as a hysteresis client

1 = ENABLE
HYST_AFIR: client afir is treated as a hysteresis client

1 = ENABLE
HYST_DISPLAY0CB: client display0cb is treated as a hysteresis client

6 0x1 0 = DISABLE
1 = ENABLE
HYST_DISPLAY0C: client display0c is treated as a hysteresis client

5 0x1 0 = DISABLE
1 = ENABLE
HYST_DISPLAY0BB: client display0bb is treated as a hysteresis client

4 0x1 0 = DISABLE
1 = ENABLE
HYST_DISPLAY0B: client display0b is treated as a hysteresis client

3 0x1 0 = DISABLE
1 = ENABLE
HYST_DISPLAY0AB: client display0ab is treated as a hysteresis client

2 0x1 0 = DISABLE
1 = ENABLE
HYST_DISPLAY0A: client display0a is treated as a hysteresis client

1 0x1 0 = DISABLE
1 = ENABLE
HYST_PTCR: client ptcr is treated as a hysteresis client

1 = ENABLE

Memory Controller
Controls whether a client is considered to be an hysteresis client for EMEM arbitration. If a client is NOT marked hysteresis, it
Boot requirements:
Per-Client Hysteresis Settings

Offset: 0x21c | Read/Write: R/W | Reset: 0x00000000 (0b00000x00x00xx00xxxxx0xxx000000xx
HYST_VDEDBGW: client vdedbgw is treated as a hysteresis client

1 = ENABLE
HYST_VDEBSEVW: client vdebsevw is treated as a hysteresis client

1 = ENABLE
HYST_SATAW: client sataw is treated as a hysteresis client

1 = ENABLE
HYST_PPCSAHBSLVW: client ppcsahbslvw is treated as a hysteresis client

1 = ENABLE
HYST_PPCSAHBDMAW: client ppcsahbdmaw is treated as a hysteresis client

1 = ENABLE
HYST_MPCOREW: client mpcorew is treated as a hysteresis client

1 = ENABLE
HYST_MPCORELPW: client mpcorelpw is treated as a hysteresis client

1 = ENABLE
HYST_HOST1XW: client host1xw is treated as a hysteresis client

1 = ENABLE
HYST_HDAW: client hdaw is treated as a hysteresis client

1 = ENABLE
HYST_AVPCARM7W: client avpcarm7w is treated as a hysteresis client

1 = ENABLE
HYST_AFIW: client afiw is treated as a hysteresis client

1 = ENABLE
HYST_ MSENCSWR: client msencswr is treated as a hysteresis client

1 = ENABLE
HYST_MPCORER: client mpcorer is treated as a hysteresis client

1 = ENABLE
HYST_MPCORELPR: client mpcorelpr is treated as a hysteresis client

1 = ENABLE

Memory Controller
HYST_VDETPER: client vdetper is treated as a hysteresis client

1 = ENABLE
HYST_VDEMCER: client vdemcer is treated as a hysteresis client

1 = ENABLE
HYST_VDEMBER: client vdember is treated as a hysteresis client

1 = ENABLE
HYST_VDEBSEVR: client vdebsevr is treated as a hysteresis client

1 = ENABLE
Controls whether a client is considered to be a hysteresis client for EMEM arbitration. If a client is NOT marked hysteresis, it
Boot requirements:
Per-client hysteresis settings

Offset: 0x220 | Read/Write: R/W | Reset: 0x04000000 (0bxxxxx1000000xx00x00000xx00x0xx00)
HYST_DISPLAYT: client displayt is treated as a hysteresis client

26 0x1 0 = DISABLE
1 = ENABLE
HYST_GPUSWR: client gpuswr is treated as a hysteresis client

1 = ENABLE
HYST_GPUSRD: client gpusrd is treated as a hysteresis client

1 = ENABLE
HYST_TSECSWR: client tsecswr is treated as a hysteresis client

1 = ENABLE
HYST_TSECSRD: client tsecsrd is treated as a hysteresis client

1 = ENABLE
HYST_ISPWBB: client ispwbb is treated as a hysteresis client

1 = ENABLE
HYST_ISPWAB: client ispwab is treated as a hysteresis client

1 = ENABLE
HYST_ISPRAB: client isprab is treated as a hysteresis client

1 = ENABLE
HYST_XUSB_DEVW: client xusb_devw is treated as a hysteresis client

1 = ENABLE

Memory Controller
HYST_XUSB_DEVR: client xusb_devr is treated as a hysteresis client

1 = ENABLE
HYST_XUSB_HOSTW: client xusb_hostw is treated as a hysteresis client

1 = ENABLE
HYST_XUSB_HOSTR: client xusb_hostr is treated as a hysteresis client

1 = ENABLE
HYST_ISPWB: client ispwb is treated as a hysteresis client

1 = ENABLE
HYST_ISPWA: client ispwa is treated as a hysteresis client

1 = ENABLE
HYST_ISPRA: client ispra is treated as a hysteresis client

1 = ENABLE
HYST_VDETPMW: client vdetpmw is treated as a hysteresis client

1 = ENABLE
HYST_VDEMBEW: client vdembew is treated as a hysteresis client

1 = ENABLE
Controls whether a client is considered to be an hysteresis client for EMEM arbitration. If a client is NOT marked hysteresis, it
Boot requirements:
Per-client hysteresis settings

Offset: 0x224 | Read/Write: R/W | Reset: 0x00080000 (0bxxxxxxxxxxxx10xxxx00xxxx00000000)
HYST_DISPLAYD: client displayd is treated as a hysteresis client

19 0x1 0 = DISABLE
1 = ENABLE
HYST_VIW: client viw is treated as a hysteresis client

1 = ENABLE
HYST_VICSWR: client vicswr is treated as a hysteresis client

1 = ENABLE
HYST_VICSRD: client vicsrd is treated as a hysteresis client

1 = ENABLE
HYST_SDMMCWAB: client sdmmcwab is treated as a hysteresis client

1 = ENABLE

Memory Controller
HYST_SDMMCW: client sdmmcw is treated as a hysteresis client

1 = ENABLE
HYST_SDMMCWAA: client sdmmcwaa is treated as a hysteresis client

1 = ENABLE
HYST_SDMMCWA: client sdmmcwa is treated as a hysteresis client

1 = ENABLE
HYST_SDMMCRAB: client sdmmcrab is treated as a hysteresis client

1 = ENABLE
HYST_SDMMCR: client sdmmcr is treated as a hysteresis client

1 = ENABLE
HYST_SDMMCRAA: client sdmmcraa is treated as a hysteresis client

1 = ENABLE
HYST_SDMMCRA: client sdmmcra is treated as a hysteresis client

1 = ENABLE
16.7.1.53 MC_SMMU_TRANSLATION_ENABLE_0_0
Used in addition to the global (MC_SMMU_CONFIG.SMMU_ENABLE) and per-module
(MC_SMMU_*_ASID.*_SMMU_ENABLE) enables.
Boot requirements:
Per-client SMMU translation enables

Offset: 0x228 | Read/Write: R/W | Secure: Trust Zone Protected | Reset: 0xf0e3c07e
(0b1111xxxx111xxx1111xxxxxxx111111x)
SMMU_SATAR_ENABLE: enable client satar to be translated by SMMU

1 = ENABLE
SMMU_PPCSAHBSLVR_ENABLE: enable client ppcsahbslvr to be translated by SMMU

1 = ENABLE
SMMU_PPCSAHBDMAR_ENABLE: enable client ppcsahbdmar to be translated by SMMU

1 = ENABLE
SMMU_MSENCSRD_ENABLE: enable client msencsrd to be translated by SMMU

1 = ENABLE
SMMU_HOST1XR_ENABLE: enable client host1xr to be translated by SMMU

1 = ENABLE
22 ENABLE SMMU_HOST1XDMAR_ENABLE: enable client host1xdmar to be translated by SMMU

Memory Controller

0 = DISABLE
1 = ENABLE
SMMU_HDAR_ENABLE: enable client hdar to be translated by SMMU

1 = ENABLE
SMMU_DISPLAYHCB_ENABLE: enable client displayhcb to be translated by SMMU

1 = ENABLE
SMMU_DISPLAYHC_ENABLE: enable client displayhc to be translated by SMMU

1 = ENABLE
SMMU_AVPCARM7R_ENABLE: enable client avpcarm7r to be translated by SMMU

1 = ENABLE
SMMU_AFIR_ENABLE: enable client afir to be translated by SMMU

1 = ENABLE
SMMU_DISPLAY0CB_ENABLE: enable client display0cb to be translated by SMMU

1 = ENABLE
SMMU_DISPLAY0C_ENABLE: enable client display0c to be translated by SMMU

1 = ENABLE
SMMU_DISPLAY0BB_ENABLE: enable client display0bb to be translated by SMMU

1 = ENABLE
SMMU_DISPLAY0B_ENABLE: enable client display0b to be translated by SMMU

1 = ENABLE
SMMU_DISPLAY0AB_ENABLE: enable client display0ab to be translated by SMMU

1 = ENABLE
SMMU_DISPLAY0A_ENABLE: enable client display0a to be translated by SMMU

1 = ENABLE
Boot requirements:

Offset: 0x22c | Read/Write: R/W | Secure: Trust Zone Protected | Reset: 0xf866083c (0b11111xxxx11xx11xxxxx1xxxxx1111xx
SMMU_VDEDBGW_ENABLE: enable client vdedbgw to be translated by SMMU

1 = ENABLE

Memory Controller
SMMU_VDEBSEVW_ENABLE: enable client vdebsevw to be translated by SMMU

1 = ENABLE
SMMU_SATAW_ENABLE: enable client sataw to be translated by SMMU

1 = ENABLE
SMMU_PPCSAHBSLVW_ENABLE: enable client ppcsahbslvw to be translated by SMMU

1 = ENABLE
SMMU_PPCSAHBDMAW_ENABLE: enable client ppcsahbdmaw to be translated by SMMU

1 = ENABLE
SMMU_HOST1XW_ENABLE: enable client host1xw to be translated by SMMU

1 = ENABLE
SMMU_HDAW_ENABLE: enable client hdaw to be translated by SMMU

1 = ENABLE
SMMU_AVPCARM7W_ENABLE: enable client avpcarm7w to be translated by SMMU

1 = ENABLE
SMMU_AFIW_ENABLE: enable client afiw to be translated by SMMU

1 = ENABLE
SMMU_MSENCSWR _ENABLE: enable client msencswr to be translated by SMMU

1 = ENABLE
SMMU_VDETPER_ENABLE: enable client vdetper to be translated by SMMU

1 = ENABLE
SMMU_VDEMCER_ENABLE: enable client vdemcer to be translated by SMMU

1 = ENABLE
SMMU_VDEMBER_ENABLE: enable client vdember to be translated by SMMU

1 = ENABLE
SMMU_VDEBSEVR_ENABLE: enable client vdebsevr to be translated by SMMU

1 = ENABLE
Boot requirements:

Offset: 0x230 | Read/Write: R/W | Secure: Trust Zone Protected | Reset: 0x0Xf37cd3
(0bxxxxx1xx1111xx11x11111xx11x1xx11)

Memory Controller
SMMU_DISPLAYT_ENABLE: enable client displayt to be translated by the SMMU

1 = ENABLE
SMMU_GPUSWR_ENABLE: GPU translation is handled by swid, so this is required to be

enabled
25 RO X
0 = DISABLE
1 = ENABLE
SMMU_GPUSRD_ENABLE: GPU translation is handled by swid, so this is required to be

enabled
24 RO X
0 = DISABLE
1 = ENABLE
SMMU_TSECSWR_ENABLE: enable client tsecswr to be translated by the SMMU

1 = ENABLE
MMU_TSECSRD_ENABLE: enable client tsecsrd to be translated by the SMMU.

1 = ENABLE
SMMU_ISPWBB_ENABLE: enable client ispwbb to be translated by the SMMU.

1 = ENABLE
SMMU_ISPWAB_ENABLE: enable client ispwab to be translated by the SMMU.

1 = ENABLE
SMMU_ISPRAB_ENABLE: enable client isprab to be translated by the SMMU.

1 = ENABLE
SMMU_XUSB_DEVW_ENABLE: enable client xusb_devw to be translated by the SMMU.

1 = ENABLE
SMMU_XUSB_DEVR_ENABLE: enable client xusb_devr to be translated by the SMMU.

1 = ENABLE
SMMU_XUSB_HOSTW_ENABLE: enable client xusb_hostw to be translated by the SMMU.

1 = ENABLE
SMMU_XUSB_HOSTR_ENABLE: enable client xusb_hostr to be translated by the SMMU.

1 = ENABLE
SMMU_ISPWB_ENABLE: enable client ispwb to be translated by the SMMU.

1 = ENABLE
SMMU_ISPWA_ENABLE: enable client ispwa to be translated by the SMMU.

1 = ENABLE
SMMU_ISPRA_ENABLE: enable client ispra to be translated by the SMMU.

1 = ENABLE
SMMU_VDETPMW_ENABLE: enable client vdetpmw to be translated by SMMU

1 = ENABLE
SMMU_VDEMBEW_ENABLE: enable client vdembew to be translated by SMMU

1 = ENABLE

Memory Controller
Boot requirements:
Per-Client SMMU Translation Enables

Offset: 0x234 | Read/Write: R/W | Secure: Trust Zone Protected | Reset: 0x000c30ff (0bxxxxxxxxxxxx11xxxx11xxxx11111111)
SMMU_DISPLAYD_ENABLE: enable client displayd to be translated by the SMMU.

1 = ENABLE
SMMU_VIW_ENABLE: enable client viw to be translated by the SMMU.

1 = ENABLE
SMMU_VICSRD_ENABLE: enable client vicsrd to be translated by the SMMU.

1 = ENABLE
SMMU_VICSRD_ENABLE: enable client vicsrd to be translated by the SMMU.

1 = ENABLE
SMMU_SDMMCWAB_ENABLE: enable client sdmmcwab to be translated by the SMMU.

1 = ENABLE
SMMU_SDMMCW_ENABLE: enable client sdmmcw to be translated by the SMMU.

1 = ENABLE
SMMU_SDMMCWAA_ENABLE: enable client sdmmcwaa to be translated by the SMMU.

1 = ENABLE
SMMU_SDMMCWA_ENABLE: enable client sdmmcwa to be translated by the SMMU.

1 = ENABLE
SMMU_SDMMCRAB_ENABLE: enable client sdmmcrab to be translated by the SMMU.

1 = ENABLE
SMMU_SDMMCR_ENABLE: enable client sdmmcr to be translated by the SMMU.

1 = ENABLE
SMMU_SDMMCRAA_ENABLE: enable client sdmmcraa to be translated by the SMMU.

1 = ENABLE
SMMU_SDMMCRA_ENABLE: enable client sdmmcra to be translated by the SMMU.

0 0x0 0 = DISABLE
1 = ENABLE
16.7.1.57 MC_SMMU_AFI_ASID_0
Enables or disables SMMU translation for the module and if enabled sets the ASID for translation.

Memory Controller
This register is not TrustZone secure, but non-secure writes to this register will be dropped if either the current or new value of
the ASID field is for a secure ASID (regardless of the current or new value of the SMMU_ENABLE field).
Boot requirements:
SMMU AFI ASID Assignment Register

Offset: 0x238 | Read/Write: R/W | Reset: 0x00000000 (0b0xxxxxxxxxxxxxxxxxxxxxxxx0000000)
AFI_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
6:0 0x0 AFI_ASID: ASID to use for translation, if enabled
16.7.1.58 MC_SMMU_AVPC_ASID_0
Boot requirements:
SMMU AVPC ASID Assignment Register

Offset: 0x23c | Read/Write: R/W | Reset: 0x00000000 (0b0xxxxxxxxxxxxxxxxxxxxxxxx0000000)
AVPC_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
6:0 0x0 AVPC_ASID: ASID to use for translation, if enabled
16.7.1.59 MC_SMMU_DC_ASID_0
Boot requirements:
SMMU DC ASID Assignment Register

DC_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
6:0 0x0 DC_ASID: ASID to use for translation, if enabled

Memory Controller
16.7.1.60 MC_SMMU_DCB_ASID_0
Boot requirements:
SMMU DCB ASID Assignment Register

DCB_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
6:0 0x0 DCB_ASID: ASID to use for translation, if enabled
16.7.1.61 MC_SMMU_HC_ASID_0
Boot requirements:
SMMU HC ASID Assignment Register

HC_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
6:0 0x0 HC_ASID: ASID to use for translation, if enabled
16.7.1.62 MC_SMMU_HDA_ASID_0
Boot requirements:

Memory Controller
SMMU HDA ASID Assignment Register

HDA_SMMU_ENABLE: if set, translation is enabled for this module

1 = ENABLE
6:0 0x0 HDA_ASID: ASID to use for translation, if enabled
16.7.1.63 MC_SMMU_ISP2_ASID_0
Boot requirements:
SMMU ISP2 ASID Assignment Register

ISP2_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
6:0 0x0 ISP2_ASID: ASID to use for translation, if enabled
16.7.1.64 MC_SMMU_MSENC_ASID_0
Boot requirements:
SMMU MSENC ASID Assignment Register

MSENC_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
6:0 0x0 MSENC_ASID: ASID to use for translation, if enabled
16.7.1.65 MC_SMMU_NV_ASID_0
the ASID field is for a secure ASID (regardless of the current or new value of the SMMU_ENABLE field.

Memory Controller
SMMU NV ASID Assignment Register

Offset: 0x268 | Read/Write: R/W | Reset: 0b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxx00
NV_SMMU_ENABLE: if set, translation is enabled for this module

1 = ENABLE
1:0 0x0 NV_ASID: ASID to use for translation, if enabled
16.7.1.66 MC_SMMU_NV2_ASID_0
the ASID field is for a secure ASID (regardless of the current or new value of the SMMU_ENABLE field.
SMMU NV2 ASID Assignment Register

Offset: 0x26c | Read/Write: R/W | Reset: 0b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxx00
NV2_SMMU_ENABLE: if set, translation is enabled for this module

1 = ENABLE
1:0 0x0 NV2_ASID: ASID to use for translation, if enabled
16.7.1.67 MC_SMMU_PPCS_ASID_0
Boot requirements:
SMMU PPCS ASID Assignment Register

PPCS_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
6:0 0x0 PPCS_ASID: ASID to use for translation, if enabled
16.7.1.68 MC_SMMU_SATA_ASID_0
Boot requirements:

Memory Controller
SMMU SATA ASID Assignment Register

SATA_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
6:0 0x0 SATA_ASID: ASID to use for translation, if enabled
16.7.1.69 MC_SMMU_VDE_ASID_0
Boot requirements:
SMMU VDE ASID Assignment Register

VDE_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
1:0 0x0 VDE_ASID: ASID to use for translation, if enabled
16.7.1.70 MC_SMMU_VI_ASID_0
Boot requirements:
SMMU VI ASID Assignment Register

VI_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
6:0 0x0 VI_ASID: ASID to use for translation, if enabled
16.7.1.71 MC_SMMU_VIC_ASID_0

Memory Controller
Boot requirements:
SMMU VIC ASID Assignment Register

VIC_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
6:0 0x0 VIC_ASID: ASID to use for translation, if enabled
16.7.1.72 MC_SMMU_XUSB_HOST_ASID_0
Boot requirements:
SMMU XUSB_HOST ASID Assignment Register

XUSB_HOST_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
6:0 0x0 XUSB_HOST_ASID: ASID to use for translation, if enabled
16.7.1.73 MC_SMMU_XUSB_DEV_ASID_0
Boot requirements:
SMMU XUSB_DEV ASID Assignment Register

XUSB_DEV_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
6:0 0x0 XUSB_DEV_ASID: ASID to use for translation, if enabled

Memory Controller
16.7.1.74 MC_SMMU_TSEC_ASID_0
Boot requirements:
SMMU TSEC ASID Assignment Register

TSEC_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
6:0 0x0 TSEC_ASID: ASID to use for translation, if enabled
16.7.1.75 MC_SMMU_PPCS1_ASID_0
Boot requirements:
SMMU PPCS1ASID Assignment Register

PPCS1_SMMU_ENABLE: if set, translation is enabled for this client

1 = ENABLE
6:0 0x0 PPCS1_ASID: ASID to use for translation, if enabled
16.7.1.76 MC_VIDEO_PROTECT_VPR_OVERRIDE_0
MC VPR OVERRIDE Register

Offset: 0x418 | Read/Write: R/W | Reset: 0xe4bac743 (0b111xx1xx1011101011xx011101xx0011)
31 ENABLE SDMMC3A_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE

Memory Controller
26 ENABLE DC1_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
23 ENABLE PPCS1_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
22 DISABLE TSEC_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
20 ENABLE XUSB_DEV_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
19 ENABLE XUSB_HOST_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
18 DISABLE VIC_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
17 ENABLE VI_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
16 DISABLE VDE_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
15 ENABLE SATA_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
14 ENABLE PPCS_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
11 DISABLE MSENC_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
10 ENABLE MPCORELP_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
9 ENABLE MPCORE_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
8 ENABLE ISP2_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
7 DISABLE HDA_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
6 ENABLE HC_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
3 DISABLE DCB_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
2 DISABLE DC_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE

Memory Controller
1 ENABLE AVPC_VPR_OVERRIDE
0 = DISABLE
1 = ENABLE
0 ENABLE AFI_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
16.7.1.77 MC_VIDEO_PROTECT_VPR_OVERRIDE1_0
MC VPR OVERRIDE Register

4 ENABLE PPCS2_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
3 DISABLE GPUB_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
2 DISABLE GPU_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
1 ENABLE ISP2B_VPR_OVERRIDE:
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
16.7.1.78 MC_SMMU_TLB_SET_SELECTION_MASK_0_0
TLB Set Selection Mask (Bit 0)

Mask is ANDed with the Virtual Address, and the resulting value is XORed to a single bit. That bit selects either set0 or set1.
Boot requirements:
Offset: 0x600 | Read/Write: R/W | Reset: 0x00008000 (0bxxxxxxxx000000001xxxxxxxxxxxxxxx)
23:15 0x1 TLB_SET_SELECTION_MASK_0

Memory Controller
16.7.1.79 MC_DISPLAY_SNAP_RING_0
Display Arbiter Ring Selection

Boot requirements:
Offset: 0x608 | Read/Write: R/W | Reset: 0x00000003 (0b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxx11)
31 ENABLED DISPLAY_SNAP_RING_WRITE_ACCESS :
0 = ENABLED
1 = DISABLED
1 RING1 DISB_SNAP_RING :
0 = RING0
1 = RING1
0 RING1 DIS_SNAP_RING :
0 = RING0
1 = RING1
16.7.1.80 MC_ERR_VPR_STATUS_0
Offset: 0x654 | Read/Write: RO | Reset: 0x00XXX0XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
ERR_VPR_ADR_HI: Higher address bits of erring address whose lower bits are available in the
21:20 X
ERR_VPR_ADR register
18 X ERR_VPR_SWAP
ERR_VPR_SECURITY: Set if transaction was secure.

17 X 0 = NONSECURE
1 = SECURE
ERR_VPR_RW: Direction of the access that caused the error.

16 X 0 = READ
1 = WRITE
14:12 X ERR_VPR_ADR1: Second subpartition unique address bits
6:0 X ERR_VPR_ID: Client identifier (see above list) of the access that caused the error.
16.7.1.81 MC_ERR_VPR_ADR_0
31:0 X ERR_VPR_ADR
16.7.1.82 MC_EMEM_CFG_ACCESS_CTRL_0
Access Control Bit for EMEM_CFG Registers

This bit is "sticky." Registers are writeable by default. Once write access is disabled, it cannot be re-enabled without a system
reset.
The following registers are controlled by this register:
 EMEM_CFG
 EMEM_ADR_CFG
Memory Controller
 EMEM_ADR_CFG_DEV0
 EMEM_ADR_CFG_DEV1
 EMEM_ADR_CFG_CHANNEL_MASK
 EMEM_ADR_CFG_BANK_MASK_0
 EMEM_BANK_SWIZZLE_CFG0
EMEM_CFG_WRITE_ACCESS:
0 ENABLED 0 = ENABLED
1 = DISABLED
16.7.1.83 MC_TZ_SECURITY_CTRL_0
Trustzone Security Control Register

Controls "Strict"ness of TrustZone security check.
This register is "sticky" - once the strict check is enabled, it cannot be disabled without a reset.
CPU_STRICT_TZ_APERTURE_CHECK: When this bit is set to ENABLED, the TrustZone security

check requires that the CPU's security state bit exactly match the aperture. That is, when the CPU
sets the NS bit to 0, it can ONLY access the TrustZone secured aperture. When the NS bit is 1, the
CPU may NOT access the TrustZone secured aperture. Any violation causes a security violation to
be flagged.
0 DISABLED When this bit is set to DISABLED, the security check is relaxed. In this mode, the CPU can access
memory outside of the TrustZone secured aperture even though the NS bit is set to 0 (that is, even
though the CPU is in secure mode). The above description only applies to the CPU complex clients
(read and write). Other clients operate in the relaxed mode.
0 = DISABLED
1 = ENABLED
16.7.1.84 MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0
External Memory Arbitration Configuration: Highest Ring Outstanding Request Limiter
Note: Although called ring3, this register works on the highest ring.
This register is used to limit the number of outstanding requests in the arbiter and monitor the count. If the outstanding
transactions are greater than the maximum, the highest ring requests are throttled based on the
MC_EMEM_ARB_RING3_THROTTLE_0 register.
Boot requirements:

Memory Controller
 During the Boot ROM section of warm boot, this register can be derived from other MC settings.
Offset: 0x66c | Read/Write: R/W | Reset: 0x8XXX0080 (0b10xxxxxxxxxxxxxxxxxxxxx010000000)
LIMIT_OUTSTANDING_RING3: When ENABLED, requests into ring3 are throttled after the
request count reaches ARB_MAX_OUTSTANDING_RING3.
31 RW ENABLE
0 = DISABLE
1 = ENABLE
LIMIT_DURING_HOLDOFF_OVERRIDE_RING3: When DISABLED, overrides the limiting of

ring3 transactions during holdoff to let requests flow freely.
30 RW DISABLE
0 = DISABLE
1 = ENABLE
24:16 RO X ARB_OUTSTANDING_COUNT_RING3: Current number of outstanding requests
ARB_MAX_OUTSTANDING_RING3: The maximum number of requests allowed in the arbiter

8:0 RW 0x80
when LIMIT_OUTSTANDING is set to ENABLE
16.7.1.85 MC_SEC_CARVEOUT_BOM_0
Offset: 0x670 | Read/Write: R/W | Reset: 0xfff00000 (0b111111111111xxxxxxxxxxxxxxxxxxxx)
31:20 0xfff SEC_CARVEOUT_BOM: [PMC_SECURE] Base address for the SEC carveout address space.
16.7.1.86 MC_SEC_CARVEOUT_SIZE_MB_0
Offset: 0x674 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxx000000000000)
SEC_CARVEOUT_SIZE_MB: [PMC_SECURE] SEC_CARVEOUT_SIZE_MB is the size, in megabytes,

11:0 0x0
of the SEC carveout region. If set to 0, the security check in MC is disabled.
16.7.1.87 MC_SEC_CARVEOUT_REG_CTRL_0
SEC_CARVEOUT_WRITE_ACCESS: [PMC_SECURE] Sticky bit to control the writes to the other Sec
Carveout aperture registers.
0 ENABLED
0 = ENABLED
1 = DISABLED
16.7.1.88 MC_ERR_SEC_STATUS_0
Offset: 0x67c | Read/Write: RO | Reset: 0x00XXX0XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
ERR_SEC_ADR_HI: Higher address bits of erring address whose lower bits are available in the
21:20 X
ERR_ADR register
18 X ERR_SEC_SWAP
ERR_SEC_SECURITY: Set if the transaction was secure.

17 X 0 = NONSECURE
1 = SECURE

Memory Controller
ERR_SEC_RW: Direction of the access that caused the error.

16 X 0 = READ
1 = WRITE
14:12 X ERR_SEC_ADR1: Second subpartition unique address bits.
6:0 X ERR_SEC_ID: Client identifier (see above list) of the access that caused the error.
16.7.1.89 MC_ERR_SEC_ADR_0
31:0 X ERR_SEC_ADR
16.7.1.90 MC_PC_IDLE_CLOCK_GATE_CONFIG_0
Partition Idle Clock Gate Config

Boot requirements:
This register should be saved in the SDRAM and restored by the OS during warm boot.
Offset: 0x684 | Read/Write: R/W | Reset: 0x0000001f (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx11111)
4:0 0x1f CLOCK_GATE_IDLE_TICKS: Number of idle "ticks" before a partition client is clock-gated
16.7.1.91 MC_STUTTER_CONTROL_0
SLOW_EMCCLK_DURING_DSR: When ENABLED, the clock to the EMC will be slowed during dynamic
self refresh.
0 0x0
0 = DISABLED
1 = ENABLED
16.7.1.92 MC_EMEM_ARB_NISO_THROTTLE_0

Highest Ring Snap Arbiter Input Throttle - This register applies to the inputs of the highest ring. Refer to the
EMEM_ARB_NISO_THROTTLE_MASK register to see how partition clients are configured into the "NISO meta-client" group
for the purpose of NISO client throttling.
Boot requirements:
Offset: 0x6b0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxx00000xxxxxxxxxxx00000)
NISO_THROTTLE_CYCLES_HIGH: Cycles of throttle after each request when the

20:16 0x0
outstanding transaction count is greater than or equal to the threshold.

Memory Controller
4:0 0x0 NISO_THROTTLE_CYCLES: Cycles of throttle after each request.
16.7.1.93 MC_EMEM_ARB_OUTSTANDING_REQ_NISO_0
External Memory Arbitration Configuration: Highest Ring Input NISO Outstanding Request Limiter
Although called NISO, this register applies to the inputs of the highest snap-arbiter ring. Refer to the
EMEM_ARB_NISO_THROTTLE_MASK register to see how partition clients are configured into the "NISO meta-client" group
for the purpose of NISO client throttling.
This register can be used to limit the number of outstanding requests in the arbiter and monitor the count. If the outstanding
transactions are greater than the maximum, the highest ring requests are throttled based on the
MC_EMEM_ARB_NISO_THROTTLE register.
Boot requirements:
 During the Boot ROM section of warm boot, this register may be derived from other MC settings.
Offset: 0x6b4 | Read/Write: R/W | Reset: 0x8XXX0080 (0b10xxxxxxxxxxxxxxxxxxxxx010000000)
LIMIT_OUTSTANDING_NISO: When ENABLED, requests into NISO are throttled after the
request count reaches ARB_MAX_OUTSTANDING_NISO.
31 RW ENABLE
0 = DISABLE
1 = ENABLE
LIMIT_DURING_HOLDOFF_OVERRIDE_NISO: When DISABLED, overrides the limiting of

NISO transactions during holdoff to let requests flow freely.
30 RW DISABLE
0 = DISABLE
1 = ENABLE
24:16 RO X ARB_OUTSTANDING_COUNT_NISO: Current number of outstanding requests.
ARB_MAX_OUTSTANDING_NISO: The maximum number of requests allowed in the arbiter

8:0 RW 0x80
when LIMIT_OUTSTANDING is set to ENABLE.
16.7.1.94 MC_EMEM_ARB_NISO_THROTTLE_MASK_0
External Memory Arbitration Configuration: Highest Ring Input NISO Throttle Mask
This register is used to group partition clients in the highest level snap-arbiter ring into a "NISO meta-client" group for the
purpose of throttling. This allows soft-ISO clients in this ring to meet their bandwidth needs.
To prevent non-ISO (NISO) clients from filling the MC row-sorter (which could prevent soft-ISO clients from getting bandwidth),
selective throttling is implemented at the input of ring2. To do this, the EMEM_ARB_NISO_THROTTLE_MASK register is
used to specify which partition clients get included into a "NISO meta-client" group. To implement throttling, a total number of
outstanding transactions counter (for example, only one counter exists in the whole "NV_MC_cif" to track this, and is shared
by all throttling circuits) gets compared to a programmable maximum limit for this NISO meta-client group. If the number is
greater than the maximum limit, all clients included in the "NISO meta-client" group get throttled based on the
EMEM_ARB_NISO_THROTTLE register. This NISO_THROTTLE register is used to specify a number of stall cycles that get
inserted at the input to the ring after every request from any of the clients included in the NISO group.

Memory Controller
Boot requirements:
 This register should be saved to SDRAM and restored by the OS during warm boot.
Offset: 0x6b8 | Read/Write: R/W | Reset: 0x00000000 (0bxx0000xx00xx0x0xx0xxxx000xxx000x)
NISO_THROTTLE_MASK_VICPC: If enabled, include VICPC in the NISO meta-client group for

throttling.
29 DISABLED
0 = DISABLED
1 = ENABLED
NISO_THROTTLE_MASK_USBD: If enabled, include USBD in the NISO meta-client group for

throttling.
28 DISABLED
0 = DISABLED
1 = ENABLED
NISO_THROTTLE_MASK_HOST: If enabled, include HOST in the NISO meta-client group for

throttling.
27 DISABLED
0 = DISABLED
1 = ENABLED
NISO_THROTTLE_MASK_AUD: If enabled, include AUD in the NISO meta-client group for throttling.
26 DISABLED 0 = DISABLED
1 = ENABLED
NISO_THROTTLE_MASK_SD: If enabled, include SD in the NISO meta-client group for throttling.

1 = ENABLED
NISO_THROTTLE_MASK_GK: If enabled, include GK in the NISO meta-client group for throttling.

1 = ENABLED
NISO_THROTTLE_MASK_MSE: If enabled, include MSE in the NISO meta-client group for throttling.
1 = ENABLED
NISO_THROTTLE_MASK_USBX: If enabled, include USBX in the NISO meta-client group for

throttling.
17 DISABLED
0 = DISABLED
1 = ENABLED
NISO_THROTTLE_MASK_VD: If enabled, include VD in the NISO meta-client group for throttling.

1 = ENABLED
NISO_THROTTLE_MASK_SAX: If enabled, include SAX in the NISO meta-client group for throttling.
1 = ENABLED
NISO_THROTTLE_MASK_FTOP: If enabled, include FTOP in the NISO meta-client group for

throttling.
8 DISABLED
0 = DISABLED
1 = ENABLED
NISO_THROTTLE_MASK_PCX: If enabled, include PCX in the NISO meta-client group for throttling.
1 = ENABLED
NISO_THROTTLE_MASK_AVP: If enabled, include AVP in the NISO meta-client group for throttling.
1 = ENABLED
NISO_THROTTLE_MASK_APB: If enabled, include APB in the NISO meta-client group for throttling.
1 = ENABLED
NISO_THROTTLE_MASK_AHB: If enabled, include AHB in the NISO meta-client group for throttling.
1 = ENABLED

Memory Controller
16.7.1.95 MC_EMEM_ARB_RING0_THROTTLE_MASK_0
External Memory Arbitration Configuration: Ring0 Input Throttle Mask

This register is used to group partition clients at the input to snaparb ring0 into a single "meta-client" group for throttling. This
allows clients in this ring to meet their bandwidth needs.
Boot requirements:
 This register should be saved to SDRAM registers and restored by the OS during warm boot.
 This register is shadowed: see usage note at the top of Section 16.7.1
Offset: 0x6bc | Read/Write: R/W | Reset: 0x80008031 (0b1xxxxxxxxxxxxxxx1xxxxxxxxx110001)
ARB_OUTSTANDING_COUNT_ABOVE_SMMU: If enabled, arb_outstanding count includes requests

in SMMU. If disabled, only count requests downstream of ring0.
31 ENABLE
0 = DISABLE
1 = ENABLE
RING0_THROTTLE_MASK_RING1_OUTPUT: If enabled, include the ring1 output (that is, all ring1
requests) in the ring0 meta-client group for throttling.
15 ENABLE
0 = DISABLE
1 = ENABLE
RING0_THROTTLE_MASK_R0_DISB: If enabled, include r0_disb in the ring0 meta-client group for

throttling.
5 ENABLE
0 = DISABLE
1 = ENABLE
RING0_THROTTLE_MASK_R0_DIS: If enabled, include r0_dis in the ring0 meta-client group for

throttling.
4 ENABLE
0 = DISABLE
1 = ENABLE
RING0_THROTTLE_MASK_MEM: If enabled, include mem in the ring0 meta-client group for throttling.
1 = ENABLE
RING0_THROTTLE_MASK_PTC: If enabled, include ptc in the ring0 meta-client group for throttling.
1 = ENABLE
RING0_THROTTLE_MASK_MMU: If enabled, include mmu in the ring0 meta-client group for throttling.
1 = ENABLE
RING0_THROTTLE_MASK_MPCORER: If enabled, include mpcorer in the ring0 meta-client group for

throttling.
0 ENABLE
0 = DISABLE
1 = ENABLE
16.7.1.96 MC_PC_IDLE_CLOCK_GATE_0
Partition Idle Clock Gate

Setting the control bit to NOT_GATED for a given partition will ensure that the mcclk, when the override is set to
GATED_ON_IDLE, can be gated if that partition is idle.
Boot requirements:
This register should be saved in the SDRAM and restored by the OS during warm boot.

Memory Controller
Offset: 0x954 | Read/Write: R/W | Reset: 0x3dfec29e (0bxx1111x11111111x11xxxx101xx1111x)
VICPC_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the vicpc partition

29 GATED_ON_IDLE 0 = NOT_GATED
1 = GATED_ON_IDLE
USBD_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the usbd partition

1 = GATED_ON_IDLE
HOST_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the host partition

1 = GATED_ON_IDLE
AUD_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the aud partition

1 = GATED_ON_IDLE
ISP_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the isp partition

1 = GATED_ON_IDLE
SD_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the sd partition

1 = GATED_ON_IDLE
GK_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the gk partition

1 = GATED_ON_IDLE
VE2_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the ve2 partition

1 = GATED_ON_IDLE
MSE_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the mse partition

1 = GATED_ON_IDLE
DISB_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the disb partition

1 = GATED_ON_IDLE
USBX_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the usbx partition

1 = GATED_ON_IDLE
VE_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the ve partition

1 = GATED_ON_IDLE
VD_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the vd partition

1 = GATED_ON_IDLE
SAX_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the sax partition

1 = GATED_ON_IDLE
FTOP_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the ftop partition

8 NOT_GATED 0 = NOT_GATED
1 = GATED_ON_IDLE
PCX_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the pcx partition

1 = GATED_ON_IDLE
DIS_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the dis partition

1 = GATED_ON_IDLE

Memory Controller
AVP_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the avp partition

1 = GATED_ON_IDLE
APB_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the apb partition

1 = GATED_ON_IDLE
AHB_IDLE_CLOCK_GATE_ENABLE: Idle clock gate control for the ahb partition

1 = GATED_ON_IDLE
16.7.1.97 MC_EMEM_ARB_OVERRIDE_1_0
Boot requirements:
 Some fields of register should be saved in the scratch registers and restored by the Boot ROM during warm boot.
 This security configuration register should be saved to SDRAM and restored by the OS during warm boot.
31:7 0x0 EMEM_ARB_OVERRIDE_RESERVED
5 DISABLE EXPIRE_UPDATE_DEADLOCK_OVERRIDE:
0 = DISABLE
1 = ENABLE
1 = OVERRIDE
4:2 DISABLE CPU_READ_PAGE_OPEN_POLICY:

0 = DISABLE
1 = ENABLE_ALL
2 = ENABLE_EACK_ACTIVE
3 = ENABLE_EARLY_ACK_ENABLE
4 = ENABLE_PO_HINT
1:0 DISABLE CPU_WRITE_PAGE_OPEN_POLICY :

0 = DISABLE
1 = ENABLE_ALL
2 = ENABLE_EACK_HINT
16.7.1.98 MC_CLIENT_HOTRESET_CTRL_1_0
Memory Client Hot Reset Control Register

Writing FLUSH_ENABLE to a bit in this register causes a flush to be performed on all clients for the selected swname. The
status of the flush (done/in progress) can be monitored in the CLIENT_HOTRESET_STATUS register.
A proper client reset sequence is as follows:
 Set the appropriate FLUSH_ENABLE bit in the CLIENT_HOTRESET_CTRL register to block further access by the
client, and start the flush process.
 Poll the CLIENT_HOTRESET_STATUS register until the appropriate bit returns FLUSH_DONE.
 Clear module bit in the CLK_RST_CONTROLLER_RST_DEVICES_* register to reset the module.
 Set module bit in the CLK_RST_CONTROLLER_RST_DEVICES_* register to release the module reset.
 Clear the appropriate FLUSH_ENABLE bit in the CLIENT_HOTRESET_CTRL register to allow transactions to flow.

Memory Controller
GPU_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
ISP2B_FLUSH_ENABLE:
0 = DISABLE
0 = DISABLED
1 = ENABLED
0 = DISABLE
0 = DISABLED
1 = ENABLED
16.7.1.99 MC_CLIENT_HOTRESET_STATUS_1_0
Memory Client Hot Reset Status Register

Contains one bit for each swname indicating the status of any flush that has been requested in the
CLIENT_HOTRESET_CTRL register.
Note: If no flush has been requested, this register returns FLUSH_DONE.
Offset: 0x974 | Read/Write: RO | Reset: 0x0000000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
GPU_HOTRESET_STATUS:
2 X 1 = FLUSH_DONE
ISP2B_HOTRESET_STATUS:
1 X 1 = FLUSH_DONE
0 X 1 = FLUSH_DONE
16.7.1.100 MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0
31:0 0x0 VIDEO_PROTECT_GPU_OVERRIDE_0
16.7.1.101 MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0
15:0 0x0 VIDEO_PROTECT_GPU_OVERRIDE_1

Memory Controller
16.7.1.102 MC_MTS_CARVEOUT_BOM_0
Offset: 0x9a0 | Read/Write: R/W | Reset: 0xfff00000 (0b111111111111xxxxxxxxxxxxxxxxxxxx)
31:20 0xfff MTS_CARVEOUT_BOM
16.7.1.103 MC_MTS_CARVEOUT_SIZE_MB_0
Offset: 0x9a4 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxx000000000000)
11:0 0x0 MTS_CARVEOUT_SIZE_MB
16.7.1.104 MC_MTS_CARVEOUT_ADR_HI_0
Offset: 0x9a8 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00)
1:0 0x0 MTS_CARVEOUT_BOM_HI
16.7.1.105 MC_MTS_CARVEOUT_REG_CTRL_0
Offset: 0x9ac | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
0 ENABLED MTS_CARVEOUT_WRITE_ACCESS
0 = ENABLED
1 = DISABLED
16.7.1.106 MC_SMMU_PTC_FLUSH_1_0
Program the higher address bits above PTC_FLUSH_ADR[31] in this field to flush a PDE or PTE group at a certain physical
address.
Note: Only a 10 GB physical address is supported.
Page Table Cache Flush Address (Upper) Register

Offset: 0x9b8 | Read/Write: R/W | Reset: 0x0000000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
PTC_FLUSH_ADR_HI: Physical address of PTE group to match for address flushes,

1:0 X
PA[39:32]
Secure/Carveout Region Configuration: Base Address Higher Bits

Security Base:
 Can be only accessed by TrustZone-secured accesses from the secure clients.

 Access to this register is restricted to TrustZone-secured requestors.

Memory Controller
Boot requirements:
 This security configuration register should be saved to SDRAM and restored by the OS during warm boot.
Offset: 0x9bc | Read/Write: R/W | Secure Trust Zone Protected | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00)
SECURITY_BOM_HI: SECURITY_BOM_HI has the higher address bits beyond 32 bits of the
1:0 0x0
base of the secured region, limited to MB granularity.
16.7.1.108 MC_EMEM_BANK_SWIZZLE_CFG0_0
Bank Swizzling Register

Offset: 0x9c0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxx0000000000000000)
15:0 0x0 EMEM_BANK_MASK0



Offset: 0x9cc | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000)
2:0 COL_NONE EMEM_BANK_SWIZCOL

0 = COL_NONE
1 = COL_1KB
2 = COL_2KB
3 = COL_2KB_OFFSET_2
4 = COL_2KB_OFFSET_4

Memory Controller
16.7.1.112 MC_SEC_CARVEOUT_ADR_HI_0
Offset: 0x9d4 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00)
SEC_CARVEOUT_BOM_HI: [PMC_SECURE] Higher address bits beyond 32 bits of byte-aligned address

1:0 0x0
of the base address of the SEC carveout space.
16.7.1.113 MC_SMMU_DC1_ASID_0
SMMU DC1 ASID Assignment Register

Boot requirements:
Offset: 0xa88 | Read/Write: R/W | Secure Trust Zone Protected | Reset: 0x00000000 (0b0xxxxxxxxxxxxxxxxxxxxxxxx0000000)
DC1_SMMU_ENABLE: If set, translation is enabled for this client.

1 = ENABLE
6:0 0x0 DC1_ASID: ASID to use for translation, if enabled.
16.7.1.114 MC_SMMU_SDMMC1A_ASID_0
Boot requirements:
SMMU SDMMC1A ASID Assignment Register

Offset: 0xa94 | Read/Write: R/W | Reset: 0x00000000 (0b0xxxxxxxxxxxxxxxxxxxxxxxx0000000)
SDMMC1A_SMMU_ENABLE: If set, translation is enabled for this client.

1 = ENABLE
6:0 0x0 SDMMC1A_ASID: ASID to use for translation, if enabled.

Memory Controller
Boot requirements:

Offset: 0xa98 | Read/Write: R/W | Reset: 0x00000000 (0b0xxxxxxxxxxxxxxxxxxxxxxxx0000000)

1 = ENABLE
Boot requirements:

Offset: 0xa9c | Read/Write: R/W | Reset: 0x00000000 (0b0xxxxxxxxxxxxxxxxxxxxxxxx0000000)

1 = ENABLE
Boot requirements:

Offset: 0xaa0 | Read/Write: R/W | Reset: 0x00000000 (0b0xxxxxxxxxxxxxxxxxxxxxxxx0000000)

1 = ENABLE

Memory Controller
16.7.1.118 MC_SMMU_ISP2B_ASID_0
Boot requirements:
SMMU ISP2B ASID Assignment Register

ISP2B_SMMU_ENABLE: If set, translation is enabled for this client.

1 = ENABLE
6:0 0x0 ISP2B_ASID: ASID to use for translation, if enabled.
16.7.1.119 MC_SMMU_GPU_ASID_0
Boot requirements:
SMMU GPU ASID Assignment Register

GPU_SMMU_ENABLE: Hardcoded for GPU to DISABLE.

1 = ENABLE
6:0 0x0 GPU_ASID: ASID to use for translation, if enabled.
16.7.1.120 MC_SMMU_GPUB_ASID_0
Boot requirements:

Memory Controller
SMMU GPUB ASID Assignment Register

Offset: 0xaac | Read/Write: R/W | Reset: 0x80000000 (0b1xxxxxxxxxxxxxxxxxxxxxxxx0000000)
GPUB_SMMU_ENABLE: Hardcoded for GPUB to ENABLE.

1 = ENABLE
6:0 0x0 GPUB_ASID: ASID to use for translation, if enabled.
16.7.1.121 MC_SMMU_PPCS2_ASID_0
Boot requirements:
SMMU PPCS2 ASID Assignment Register

Offset: 0xab0 | Read/Write: R/W | Reset: 0x00000000 (0b0xxxxxxxxxxxxxxxxxxxxxxxx0000000)
PPCS2_SMMU_ENABLE: If set, translation is enabled for this client.

1 = ENABLE
6:0 0x0 PPCS2_ASID: ASID to use for translation, if enabled.
16.7.2 EMC Registers

USAGE NOTE: Many EMC register fields are shadowed:
 Writes to shadowed register fields update the shadow copy (this is default, assumes
DBG.WRITE_MUX==ASSEMBLY).
 Reads to shadowed register fields return the currently-active copy (this is default, assumes
DBG.READ_MUX==ACTIVE).
This allows a new set of frequency-dependent timing parameters to be written to the shadow registers while memory traffic is
ongoing, then when the parameters are completely written, the EMC hardware can perform a timing-safe switch.
Such switches can be triggered via two methods: TIMING_CONTROL.TIMING_UPDATE (generally used during initialization),
or the automatic CAR/EMC handshake on a clock-frequency or divider change (assuming
CFG_2.CLKCHANGE_REQ_ENABLE==ENABLED).
Registers that are shadowed are marked by a comment:
Occasionally, only certain fields in the register will be shadowed; if so they are noted after the above comment.
USAGE NOTE: Many EMC registers play crucial roles in warm boot (also known as "wake from LP0") and cold boot (also
known as "power up") sequences. Suggested actions for the Boot ROM/Boot Loader are noted after "Boot requirements:”.

Memory Controller
USAGE NOTE: The EMC register fields to be stored in the PMC must have "[PMC]", "[PMC2]", or "[PMC3]".in their comments.
([PMC2] registers are packed/unpacked after [PMC] register group in software code. [PMC3] is even later.) The fields that
need to be stored in PMC Secure Scratch registers must have [PMC_SECURE] in their comments.
USAGE NOTE: When writing to a register, any bits that are not intended to be modified should be rewritten with their existing
values.
USAGE NOTE: Unspecified bits may not appear in tables and should be written with their Reset values.
16.7.2.1 EMC_INTSTATUS_0
Interrupt Status Register

Clear on 1-write. Init value is clear. This register is “sticky”.
Offset: 0x0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxx0000000xxx)
9 CLEAR DLL_LOCK_TIMEOUT_INT: Indicates a DLL lock timeout has occurred.

0 = CLEAR
1 = SET
8 CLEAR CCFIFO_OVERFLOW_INT: Clock change FIFO overflow.

0 = CLEAR
1 = SET
DLL_ALARM_INT: Indicates a DLL alarm has been set

7 CLEAR 0 = CLEAR
1 = SET
ACCESS_TO_SR_DPD_DEV_INT: Indicates a system attempt to access a self-refresh/deep-

powered-down device.
6 CLEAR
0 = CLEAR
1 = SET
MRR_DIVLD_INT: LPDDR3 MRR data is available to be read.

5 CLEAR 0 = CLEAR
1 = SET
CLKCHANGE_COMPLETE_INT: CAR/EMC clock-change handshake complete.

4 CLEAR 0 = CLEAR
1 = SET
REFRESH_OVERFLOW_INT: Refresh request overflow timeout.

3 CLEAR 0 = CLEAR
1 = SET
16.7.2.2 EMC_INTMASK_0
Interrupt Mask Register

Init value is masked.
Offset: 0x4 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxx0000000xxx)
9 MASKED DLL_LOCK_TIMEOUT_INTMASK: Mask for DLL lock timeout interrupt.

0 = MASKED
1 = UNMASKED
8 MASKED CCFIFO_OVERFLOW_INTMASK: Mask for clock change FIFO overflow.

0 = MASKED
1 = UNMASKED

Memory Controller
DLL_ALARM_INTMASK: Mask for DLL alarm

7 MASKED 0 = MASKED
1 = UNMASKED
ACCESS_TO_SR_DPD_DEV_INTMASK: Mask for access a self-refresh/deep-powered-down

device interrupt.
6 MASKED
0 = MASKED
1 = UNMASKED
MRR_DIVLD_INTMASK: Mask for MRR data available.

5 MASKED 0 = MASKED
1 = UNMASKED
CLKCHANGE_COMPLETE_INTMASK: Mask for CAR/EMC clock-change handshake

complete.
4 MASKED
0 = MASKED
1 = UNMASKED
REFRESH_OVERFLOW_INTMASK: Mask for refresh request overflow timeout.

3 MASKED 0 = MASKED
1 = UNMASKED
16.7.2.3 EMC_CFG_0
Configuration Register
The CFG register is used to configure the external memory interface.
Boot requirements:
Offset: 0xc | Read/Write: R/W | Reset: 0x03c0000e (0b0000x01111000000xxxxxx000000111x)
DRAM_CLKSTOP_PD: [PMC] clock stop is only allowed to happen if the DRAM is in

active/precharge powerdown (for all CKE bits associated with clock)
31 DISABLED
0 = DISABLED
1 = ENABLED
DRAM_CLKSTOP_SR: [PMC] clockstop is only allowed to happen if the DRAM is in

self-refresh (for all CKE bits associated with clock)
30 DISABLED
0 = DISABLED
1 = ENABLED
DRAM_ACPD: [PMC] Allows the DRAM controller to perform opportunistic active

powerdown control using the CKE pin on the DRAM. The behavior of the powerdown
control logic is controlled by the PDEX2* and *2PDEN registers. The value of
29 NO_POWERDOWN DRAM_ACPD should only be changed when CKE is low, e.g., during software-
controlled self-refresh or before DRAM initialization.
0 = NO_POWERDOWN
1 = ACTIVE_POWERDOWN
DYN_SELF_REF: [PMC]
1 = ENABLED
REQACT_ASYNC: [PMC] Allows independent transfers of activates and transactions

from the MC to the EMC. Disabled to preserve the order of requests selected by
26 DISABLED mc_arb logic.
0 = DISABLED
1 = ENABLED

Memory Controller
AUTO_PRE_WR: [PMC] enable using MC auto-precharge indication for writes. This

bits, when set to DISABLE, will override the settings in the MC register (EMC ignore
the auto-precharge indication from MC). Otherwise, they permit clients to make either
25 ENABLED
auto or explicit precharge requests depend on the state of MAN_PRE_WR.
0 = DISABLED
1 = ENABLED
AUTO_PRE_RD: [PMC] enable using MC auto-precharge indication for reads. This

bits, when set to DISABLE, will override the settings in the MC register (EMC ignores
the auto-precharge indication from MC). Otherwise, they permit clients to make either
24 ENABLED
auto or explicit precharge requests depend on the state of MAN_PRE_RD.
0 = DISABLED
1 = ENABLED
MAN_PRE_WR: [PMC] enable explicit-precharge in the EMC for writes. When this bit
is enabled (and AUTO_PRE_WR=enable), EMC will issue an explicit precharge
command after the memory write command. If this bit is disabled (and
23 ENABLED AUTO_PRE_WR=enable), the EMC will issue an auto-precharge with the memory
write command.
0 = DISABLED
1 = ENABLED
MAN_PRE_RD: [PMC] enable explicit-precharge in the EMC for reads. When this bit
is enabled (and AUTO_PRE_RD=enable), EMC will issue an explicit precharge
command after the memory read command. If this bit is disabled (and
22 ENABLED AUTO_PRE_RD=enable), the EMC will issue an auto-precharge with the memory
read command.
0 = DISABLED
1 = ENABLED
PERIODIC_QRST: [PMC] specifies whether or not to periodic reset the FBIO read-
data FIFO during normal operation. The periodic resets can be used for graceful
recovery from an intermittent failure condition; only the initial reset is absolutely
21 DISABLED required.
Note: For LPDDRx and MRR (if ever used), this bit should be set to enable.
0 = DISABLED
1 = ENABLED
20 DISABLED EN_DYNAMIC_PUTERM: [PMC] enable dynamic puterm.

0 = DISABLED
1 = ENABLED
19 DISABLED DLY_WR_DQ_HALF_CLOCK: [PMC]

1 = delay write data by 1/2 clock.
0 = DISABLED
1 = ENABLED
18 DISABLED DSR_VTTGEN_DRV_EN: [PMC] enable VTTGEN controls (via

DSR_VTTGEN_DRV/TXDSRVTTGEN registers) during DSR.
0 = DISABLED
1 = ENABLED
EMC2MC_CLK_RATIO: [PMC] EMC to MC clock ratio.

0 = TWOX
17:16 TWOX 1 = ONEX
2 = FOURX
3 = RESERVED
WAIT_FOR_ISP2B_READY_B4_CC: [PMC]
9 0x0
1 = wait for isp2b ready event to be asserted before acknowledge clock change.
WAIT_FOR_VI2_READY_B4_CC: [PMC]
8 0x0
1 = wait for vi2 ready event to be asserted before acknowledge clock change.
WAIT_FOR_ISP2_READY_B4_CC: [PMC]
7 0x0
1 = wait for isp2 ready event to be asserted before acknowledge clock change.
6 0x0 INVERT_DQM: [PMC]

1 = invert DQM polarity.

Memory Controller
5 0x0 WAIT_FOR_DISPLAYB_READY_B4_CC: [PMC]

1 = wait for displayb ready event to be asserted before acknowledging clock change.
4 0x0 WAIT_FOR_DISPLAY_READY_B4_CC: [PMC]

1 = wait for display ready event to be asserted before acknowledging clock change.
3 0x1 EMC2PMACRO_CFG_BYPASS_DATAPIPE2: [PMC]

1 = bypass data pipeline stage2 (closer to I/O) between EMC and data pad-macro.
2 0x1 EMC2PMACRO_CFG_BYPASS_DATAPIPE1: [PMC]

1 = bypass data pipeline stage1 (closer to core) between EMC and data pad-macro.
1 0x1 EMC2PMACRO_CFG_BYPASS_ADDRPIPE: [PMC]

1 = bypass address pipeline stage between EMC and address pad-macro.
16.7.2.4 EMC_ADR_CFG_0
External Memory Address Configuration, System

The ADR_CFG register is used to specify the number of DRAM devices. DRAM density and geometry parameters are
specified by the EMEM_ADR_CFG* registers in MC.
Boot requirements:
EMEM_NUMDEV: [PMC SECURE] Number of populated DRAM devices.

0 N2 0 = N1
1 = N2
16.7.2.5 EMC_REFCTRL_0
Refresh Control Register

The REFCTRL register allows software to enable or disable the refresh controller.
REF_VALID should be enabled after the initialization sequence is completed.
Boot requirements:
 If per-device DPD is used, the DEVICE_REFRESH_DISABLE field should be parameterized in the BCT and written
by the Boot ROM during cold boot.
 If per-device DPD is used, the DEVICE_REFRESH_DISABLE field should be parameterized the scratch registers
and restored by the Boot ROM during warm boot.
 REF_VALID field should always be set to ENABLED for normal use, no need to parameterize in BCT/scratch.
Offset: 0x20 | Read/Write: R/W | Reset: 0x00000000 (0b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxx00)
REF_VALID: Enable refresh controller.

1 = ENABLED
DEVICE_REFRESH_DISABLE: Disables refresh to individual attached device (1 bit per

1:0 0x0
DRAM chip select).

Memory Controller
16.7.2.6 EMC_PIN_0
Controls State of Selected DRAM Pins

The PIN register allows software to control the state of the selected external DRAM pins.
Boot requirements:
 Both fields in this register should be set to NORMAL during cold boot.
 Both fields in this register should be set to NORMAL during warm boot.
Offset: 0x24 | Read/Write: R/W | Reset: 0x00000100 (0bxxxxxxxxxxxxxxxxxxxxxxx1xxx0xxx0)
PIN_RESET: Selects the level of the DDR3 RESET# pin.

8 INACTIVE 0 = ACTIVE
1 = INACTIVE
PIN_DQM: Is used to always mask DRAM writes. This pin should only be used for
initialization. Certain DRAM vendors require the DQM to be high during initialization. The
4 NORMAL register value should be set to NORMAL after the initialization sequence.
0 = NORMAL
1 = INACTIVE
PIN_CKE: Selects the level of the CKE pin. This can be used to place the DRAM in power
down state. PIN_CKE value is applied all CKE pins.
0 POWERDOWN
0 = POWERDOWN
1 = NORMAL
16.7.2.7 EMC_TIMING_CONTROL_0
Triggers an Update of the Timing-Related Registers

The TIMING_CONTROL register is used by software to trigger parameter updates for timing parameter registers,
RDQS/QUSE delay controls, and some DLL controls. Writing the TIMING_UPDATE field updates the active state of these
registers with the programmed assembly state. The active state is updated during a safe interval determined by the EMC. If
CLKCHANGE_REQ_ENABLE is enabled, the active value will automatically be updated on completion of the clock change.
Note: Programming of this register does not trigger the shadow register update event
immediately. To prevent shadow register programming issued after programming this
register from being latched accidentally, always poll for TIMING_UPDATE_STALLED==0
after programming this register.
Boot requirements:
 Writing this register with 0x1 will trigger a timing update event, which should be used in both warm boot and cold boot
sequences.
Offset: 0x28 | Read/Write: R/W | Reset: 0x0000000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
0 X TIMING_UPDATE

Memory Controller
16.7.2.8 EMC_RC_0
DRAM Timing Parameter

Boot requirements:
Offset: 0x2c | Read/Write: R/W | Reset: 0x0000007f (0bxxxxxxxxxxxxxxxxxxxxxxxxx1111111)
RC: [PMC] Specifies the row cycle time. This is the minimum number of cycles between
activate commands to the same bank.
6:0 0x7f
LPDDR3 : ceil((tRASmin+tRPpb)/tCK) – 1
DDR3: max(0, ceil(tRC/tCK) - (CMD_2T_TIMING == 1 ? 2 : 1))
16.7.2.9 EMC_RFC_0

This register is shadowed: see usage note at the top of Section 16.7.2 .
Boot requirements:
Offset: 0x30 | Read/Write: R/W | Reset: 0x0000003f (0bxxxxxxxxxxxxxxxxxxxxxxx000111111)
RFC: [PMC] specifies the auto refresh cycle time. This is the minimum number of cycles
between an auto refresh command and a subsequent auto refresh or activate command.
8:0 0x3f LPDDR3: ceil(tRFCab/tCK) – 1
DDR2 : ceil(tRFC/tCK) - 1
DDR3: max(0, ceil(tRFC/tCK) - (CMD_2T_TIMING == 1 ? 2 : 1))
16.7.2.10 EMC_RAS_0

Boot requirements:
RAS: [PMC] specifies the row active time. This is the minimum number of cycles between an
activate command and a precharge command to the same bank.
5:0 0x3f
DDR3: max(0, ceil(tRASmin/tCK) - (CMD_2T_TIMING == 1 ? 2 : 1))
LPDDR3: max(3, ceil(tRASmin/tCK)) - 1

Memory Controller
16.7.2.11 EMC_RP_0

Boot requirements:
RP: [PMC] specifies the row precharge time. This is the minimum number of cycles between a
precharge command and an activate command to the same bank.
5:0 0x3f
DDR3: max(0, ceil(tRP/tCK) - (CMD_2T_TIMING == 1 ? 2 : 1))
LPDDR3: max(3, ceil(tRP/tCK)) - 1
16.7.2.12 EMC_R2W_0
R2something and W2something registers are independent of burst length, and are relative to the last virtual CAS_ of a
command. Counting starts from the last data transfer as related to where CAS_ would be if BL = 4.
DRAM timing parameter

Boot requirements:
Offset: 0x3c | Read/Write: R/W | Reset: 0x0000001f (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx11111)
R2W: [PMC] specifies the minimum number of cycles from any read command to any write
command, irrespective of bank. This parameter guarantees the read->write turnaround time on
the bus.
DDR3: RL - WL + 2 - (CMD_2T_TIMING == 1 ? 1 : 0) + (CTT_TERMINATION == 1 ? max(0,
CTT + CTT_DURATION - RDV - 2) : (EMC2PMACRO_CFG_XM2DQS_E_STRPULL_DQS ?
4:0 0x1f
1 : 0)) + (EMC2PMACRO_CFG_QUSE_MODE == ALWAYS_ON ? 1 : 0)
LPDDR3: RL - WL + 1 + ceil(tDQSCKmax/tCK) +
(EMC2PMACRO_CFG_XM2DQS_E_STRPULL_DQS ? 1 : 0) +
(EMC2PMACRO_CFG_QUSE_MODE == ALWAYS_ON ? 1 : 0)
Largest programming value is 29
16.7.2.13 EMC_W2R_0

Boot requirements:
Memory Controller
W2R: [PMC] specifies the minimum number of cycles from a write command to a read
command, irrespective of bank.
4:0 0x1f DDR3 : WL + max(4, ceil(tWTR/tCK)) - (CMD_2T_TIMING == 1 ? 1 : 0)
LPDDR3 : WL + 1 + ceil(tWTR/tCK)
Largest programming value is 29.
16.7.2.14 EMC_R2P_0

Boot requirements:
R2P: [PMC] specifies the minimum number of cycles from a read command to a precharge
command for the same bank.
4:0 0x1f
DDR3 : max(4, ceil(tRTP/tCK)) - (CMD_2T_TIMING == 1 ? 2 : 1)
LPDDR3: BL/2 + max(2, ceil(tRTP/tCK)) 4 .
16.7.2.15 EMC_W2P_0

Boot requirements:
W2P: [PMC] Specifies the minimum number of cycles from a write command to a precharge
command for the same bank.
5:0 0x3f
DDR3 : WL + max(2, ceil(tWR/tCK)) - (CMD_2T_TIMING == 1 ? 1 : 0)
LPDDR3: WL + max(3, TWR)
16.7.2.16 EMC_RD_RCD_0


Memory Controller
Boot requirements:
Offset: 0x4c | Read/Write: R/W | Reset: 0x0000001f (0bxxxxxxxxxxxxxxxxxxxxxxxxxx011111)
RD_RCD: [PMC] Specifies the RAS to CAS delay. RD_RCD is the minimum number of cycles
between an activate command and a read command to the same bank.
5:0 0x1f
DDR3 : ceil(tRCD/tCK) - (CMD_2T_TIMING == 1 ? 2 : 1)
LPDDR3: max(3, ceil(tRCD/tCK)) - 1
16.7.2.17 EMC_WR_RCD_0

Boot requirements:
WR_RCD: [PMC] Minimum number of cycles between an activate command and a write
command to the same bank.
5:0 0x1f
DDR3 : ceil(tRCD/tCK) - (CMD_2T_TIMING == 1 ? 2 : 1)
LPDDR3: max(3, ceil(tRCD/tCK)) - 1
16.7.2.18 EMC_RRD_0

Boot requirements:
Offset: 0x54 | Read/Write: R/W | Reset: 0x0000000f (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111)
RRD: [PMC] specifies the Bank X Act to Bank Y Act command delay.
3:0 0xf DDR3 : max(4, ceil(tRRD/tCK)) - (CMD_2T_TIMING == 1 ? 2 : 1)
LPDDR3: max(2, ceil(tRRD/tCK)) - 1
16.7.2.19 EMC_REXT_0

Boot requirements:
Memory Controller
REXT: [PMC] specifies the read to read delay for reads when multiple physical devices are
present.
3:0 0x1
DDR3: USE_PER_DEVICE_DLY_TRIM_IB == 1 ? 2 : 1
LPDDR3: ceil(3/tCK + 0.5) + USE_PER_DEVICE_DLY_TRIM_IB ? 1 : 0
16.7.2.20 EMC_WDV_0

Boot requirements:
Offset: 0x5c | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000)
WDV: [PMC] The number of cycles to post (delay) write data from being asserted to the
RAMs.
3:0 0x0 DDR3 : WL - 1
LPDDR3 : WL
15 = MAX
16.7.2.21 EMC_QUSE_0

The QRST, QUSE, and RDV fields specify the delays from read to internal timing signals. These fields should be set as
follows:
QUSE = CAS_LATENCY - 1 non-mobile SDRAM

= CAS_LATENCY - 2 for mobile SDRAM
QRST = CAS_LATENCY - 2
QSAFE >= RDV - QRST
RDV = CAS_LATENCY + 5
EINPUT = RDV - 7
Because SDRAM uses a tristating clock (the DQS), a method is needed to deal with the ambiguity of when DQS is tristated.
Only one such method is supported: QUSE.
Boot requirements:

Memory Controller
Offset: 0x60 | Read/Write: R/W | Reset: 0x00000002 (0bxxxxxxxxxxxxxxxxxxxxxxxxxx000010)
QUSE: [PMC] Tells the chip when to look for read return data.
5:0 0x2
LPDDR3/DDR3: obtained from characterization
16.7.2.22 EMC_QRST_0

Boot requirements:
QRST: [PMC] time from expiration of QSAFE until reset is issued.

5:0 0x1 DDR3 : CL - 2
LPDDR3: RL - 2
16.7.2.23 EMC_QSAFE_0

When PERIODIC_QRST is enabled, the QSAFE parameter is intended to guarantee that the QRSTs will not interfere with
pending reads (for example, the queue is empty). This field must be set to at least (RDV - QRST).
Boot requirements:
QSAFE: [PMC] Time from a read command to when it is safe to issue a QRST (delayed by the
4:0 0x7 QRST parameter).
LPDDR3/DDR3 QSAFE >= RDV - QRST
16.7.2.24 EMC_RDV_0

RDV is the read latency register. This register value is not negotiable; it will work with the right value and will not with the
wrong value. It uses sequential timing, not combinational (i.e., maybe the silicon is fast enough type) timing.
Boot requirements:
Memory Controller
Offset: 0x6c | Read/Write: R/W | Reset: 0x00000008 (0bxxxxxxxxxxxxxxxxxxxxxxxxxx001000)
RDV: [PMC] Time from read command to latching the read data from the pad macros.
DDR3 : RL + 6 + f_ceil(fly-by-time/tCK) - (dram-dll-is-off ? 1 : 0)
LPDDR3: RL + 6 + ceil((tDQSCKmax + fly-by-time)/tCK)
5:0 0x8
Fly-by-time is board routing dependent, which usually should be less than 1.5ns.
dram-dll-is-off is true below 150 MHz where DRAM DLL has to be turned off
45 = MAX
16.7.2.25 EMC_REFRESH_0

The value of REFRESH is calculated using the following formula:
{REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64,
(tREF/#_of_rows) / (emc_clk_period) * 97%]
For example, if the clock frequency is 133 MHz, and the refresh requirement is 64 ms per 4096 rows. The programming value
is 0x7e3.
Boot requirements:
Offset: 0x70 | Read/Write: R/W | Reset: 0x0000001f (0bxxxxxxxxxxxxxxxx0000000000011111)
15:6 0x0 REFRESH: [PMC] Specifies the interval between refresh requests.
5:0 0x1f REFRESH_LO: [PMC]
16.7.2.26 EMC_BURST_REFRESH_NUM_0

BURST_REFRESH_NUM is used to specify the refresh burst count. The refresh controller will wait until
BURST_REFRESH_NUM refreshes have been scheduled, then issue them all at once. This can result in a performance
improvement in many cases.
Note: If tRAS(max) is less than the refresh interval (tREF/#_of_rows), tRAS(max) must be used
instead of the refresh interval in the formula above. This is because refresh is used to
satisfy tRAS(max) timing. Accordingly, BURST_REFRESH_NUM must be programmed in
such a way that queuing up multiple refreshes does not violate tRAS(max) timing. Burst
length = 2^BURST_REFRESH_NUM. Refreshes will be throttled to meet TREFBW
limitation (8/window) if TREFBW > 0.
Note: Do not program this register to value non-zero unless for testing.
Boot requirements:

Memory Controller
BURST_REFRESH_NUM: [PMC] Specify the refresh burst count.

0 = BR1
1 = BR2
2 = BR4
3 = BR8
4 = BR16
3:0 BR1
5 = BR32
6 = BR64
7 = BR128
8 = BR256
9 = BR512
9 = MAX
16.7.2.27 EMC_PDEX2WR_0

Boot requirements:
Offset: 0x78 | Read/Write: R/W | Reset: 0x0000003e (0bxxxxxxxxxxxxxxxxxxxxxxxxxx111110)
PDEX2WR: Specify the timing delay from exit of powerdown mode to a write command.
DDR3 : max(3, ceil(tXP/tCK)) - (CMD_2T_TIMING == 1 ? 2 : 1)
LPDDR3 : ceil(tXP/tCK) - 1
5:0 0x3e
Note: on DDR3, if slow power down exit mode is used and ODT is enabled, use max(10,
ceil(tXPDLL/tCK)) instead of max(3, ceil(tXP/tCK)) in the formula. The largest allowed value
is 62.
16.7.2.28 EMC_PDEX2RD_0

Boot requirements:
Offset: 0x7c | Read/Write: R/W | Reset: 0x0000003e (0bxxxxxxxxxxxxxxxxxxxxxxxxxx111110)
PDEX2RD: Specify the timing delay from exit of powerdown mode to a read command.
DDR3: (use-slow-pd-exit-mode ? max(10, ceil(tXPDLL/tCK)) : max(3, ceil(tXP/tCK))) -
(CMD_2T_TIMING == 1 ? 2 : 1)
5:0 0x3e
LPDDR3: ceil(tXP/tCK) - 1
use-slow-pd-exit-mode is 1 if slow power down exit mode is used (MR0 bit 12 is 0). The
largest allowed value is 62.

Memory Controller
16.7.2.29 EMC_PCHG2PDEN_0

Boot requirements:
PCHG2PDEN: [PMC] Specify the timing delay from a precharge command to powerdown
entry.
5:0 0x1f
DDR3: 1
LPDDR3: f_ceil(tRP]/tCK) - (CMD_2T_TIMING == 1 ? 1 : 0)
16.7.2.30 EMC_ACT2PDEN_0
[PMC] DRAM timing parameter

Boot requirements:
ACT2PDEN: Specify the timing delay from an activate, MRS or EMRS command to power-
5:0 0x1f down entry.
DDR3/ LPDDR3: 0
16.7.2.31 EMC_AR2PDEN_0

Boot requirements:
Offset: 0x88 | Read/Write: R/W | Reset: 0x0000001f (0bxxxxxxxxxxxxxxxxxxxxxxx000011111)
AR2PDEN: [PMC] Specify the timing delay from an autorefresh command to powerdown
entry.
8:0 0x1f
DDR3: max(7, ceil((tXPDLL - tXP)/tCK))
LPDDR3: 1

Memory Controller
16.7.2.32 EMC_RW2PDEN_0

Boot requirements:
Offset: 0x8c | Read/Write: R/W | Reset: 0x0000001f (0bxxxxxxxxxxxxxxxxxxxxxxxxxx011111)
RW2PDEN: [PMC] Specify the timing delay from a read/write command to powerdown entry.
Auto-precharge timing must be taken into account when programming this field
5:0 0x1f
DDR3: max(RL+5, WL+4+TWR) - 1
LPDDR3: max(RL+BL/2+ceil((tDQSCKmax+1)/tCK)+1, WL+BL/2+1+ceil((tWR+1)/tCCK)) - 1
16.7.2.33 EMC_TXSR_0

Boot requirements:
Offset: 0x90 | Read/Write: R/W | Reset: 0x000003fe (0bxxxxxxxxxxxxxxxxxxxxxx1111111110)
TXSR: [PMC] Cycles between self-refresh exit & first DRAM command that does not require
a locked DLL. Largest allowed value is 0x3fe.
9:0 0x3fe
DDR3: max(5, ceil(tXSR/tCK))
LPDDR3: max(2, ceil(tXSR/tCK))
16.7.2.34 EMC_TCKE_0

Boot requirements:
TCKE: Specify the minimum CKE high pulse width.

DDR3: Use-slow-pd-exit-mode ? max(10, ceil(max(tCKESR, uXPDLL)/tCK)) : max(4,
5:0 0x3e ceil(max(tXP,tXP)/tCK))
LPDDR3: max(3, tCKE, ceil(tXP/tCK))
use-slow-pd-exit-mode is 1 if slow power down exit mode is used (MR0 bit 12 is 0).

Memory Controller
16.7.2.35 EMC_TFAW_0

Boot requirements:
TFAW: [PMC] specify the width of the FAW (four-activate window) for 8-bank devices. Set to
6:0 0x0 0 to disable this timing check. Only 4 activates may occur within the rolling window. .
DDR3/LPDDR3: ceil(tFAW/tCK)
16.7.2.36 EMC_TRPAB_0

Boot requirements:
TRPAB: [PMC] Specify precharge-all tRP allowance for 8-bank devices. Setting this field to 0
will cause EMC to use TRP.TRP for precharge-all.
5:0 0x0
DDR3: ceil(tRP/tCK) + 1
LPDDR3: max(3, ceil((tRPpb+3)/tCK
16.7.2.37 EMC_TCLKSTABLE_0

Boot requirements:
Offset: 0xa0 | Read/Write: R/W | Reset: 0x0000000f (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx01111)
TCLKSTABLE: [PMC] Specify minimum number of cycles of a stable clock period prior to
exiting powerdown or self-refresh modes.
4:0 0xf
DDR3: max(5, ceil(tCKSRX/tCK)) - 1
LPDDR3: 2

Memory Controller
16.7.2.38 EMC_TCLKSTOP_0

Boot requirements:
Offset: 0xa4 | Read/Write: R/W | Reset: 0x0000000f (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx01111)
TCLKSTOP: [PMC] Delay from last command to stopping the external clock to DRAM
devices.
4:0 0xf
DDR3: max(5, ceil(tCKSRE/tCK)) - 1
LPDDR3: 2
16.7.2.39 EMC_TREFBW_0

Boot requirements:
Offset: 0xa8 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxx00000000000000)
TREFBW: [PMC] specify the width of the burst-refresh window. If set to a non-zero value,
only 8 refreshes will occur in this rolling window. Set to 0 to disable this timing check.
13:0 0x0
DDR3: ceil(tREFI/tCK)
LPDDR3: ceil(tREFBW/tCK)
16.7.2.40 EMC_ODT_WRITE_0
For DDR3, ODT may be enabled during writes and disabled during reads via control of ODT pin.
Boot requirements:
Offset: 0xb0 | Read/Write: R/W | Reset: 0x00000000 (0b00xxxxxxxxxxxxxxxxxx0000xx000000)
ENABLE_ODT_DURING_WRITE: enables ODT to be turned on prior to issuing write to

31 0x0 DRAM. [PMC] If ENABLE_ODT_DURING_WRITE = 1 and DISABLE_ODT_DURING_READ
= 0, ODT will always be enabled after the first write.
ODT_B4_WRITE: [PMC] If this field == 1, ODT is turned on ODT_WR_DELAY cycles prior to

DRAM WRITE command. If this field == 0, ODT is turned on ODT_WR_DELAY cycles after
30 0x0
DRAM WRITE command. Set ODT_B4_WRITE to 1 if ( WL - ceiling(tAOND) - 2 ) < 0. This
field is not used for DDR3.

Memory Controller
11:8 0x0 ODT_WR_DURATION: [PMC] for LPDDR3, indicate how long to assert ODT by.
5 0x0 SHARE_ONE_ODT: [PMC] For LPDDR3 only. When enabled, ODT[1] is not used. The ODT
for both ranks will be sharing the same ODT[0]. When disabled, ODT[0] is controlling rank0,
ODT[1] is controlling rank1.
DRIVE_BOTH_ODT: [PMC] If this field = 0, only the ODT for the requested device will be
4 0x0
asserted during write. If this field = 1, ODTs for both devices will be asserted during write.
ODT_WR_DELAY: [PMC] Set this field = ABS ( WL - ceiling(tAOND) - 2 ).

The valid programming range is:
3:0 0x0 0 <= ODT_WR_DELAY <= 2, if ODT_B4_WRITE=0
0 <= ODT_WR_DELAY <= 1, if ODT_B4_WRITE=1.
For DDR3, this field = (WL - 3). For LPDDR3, this field = (WL - 2).
16.7.2.41 EMC_ODT_READ_0
This register is not used. Please keep its reset value.
Boot requirements:
Offset: 0xb4 | Read/Write: R/W | Reset: 0x00000000 (0b00xxxxxxxxxxxxxxxxxxxxxxxxxxx000)
DISABLE_ODT_DURING_READ: enables ODT to be turned off prior to issuing read to

DRAM.
If this field == 0, the ODT state is not changed for reads.
31 0x0
If this field == 1, turn off ODT prior to READ command (has no effect if ODT
ENABLE_ODT_DURING_WRITE == 0, as ODT will always be disabled).
This field is not used for DDR3.
ODT_B4_READ: If this field == 1, ODT is turned off ODT_RD_DELAY cycles prior to DRAM
READ command.
30 0x0 If this field == 0, ODT is turned off ODT_RD_DELAY cycles after a DRAM READ command.
Set ODT_B4_READ to 1 if ( RL - ceiling(tAOFD) - 2 ) < 0.
ODT_RD_DELAY: Set this field = ABS ( RL - ceiling(tAOFD) - 2 ). The valid programming

range is:
2:0 0x0 0 <= ODT_RD_DELAY <= 2 if ODT_B4_READ=0
0 <= ODT_RD_DELAY <= 1 if ODT_B4_READ=1
16.7.2.42 EMC_WEXT_0

Boot requirements:
Offset: 0xb8 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000)

Memory Controller
WEXT: [PMC] specifies the write to write delay for writes when multiple physical devices are
present.
3:0 0x0 DDR3: max(0, (USE_PER_DEVICE_DLY_TRIM_OB == 1 ? 5 : 0) - (CMD_2T_TIMING ==
1 ? 1 : 0))
LPDDR3: USE_PER_DEVICE_DLY_TRIM_OB == 1 ? 5 : 0
16.7.2.43 EMC_CTT_0

CTT controls timing of internal read terminations. Based on read latency (CTT must frame read data). Adding non-RDV linked
timing control for flexibility. Has no effect unless CTT_TERMINATION == ENABLED || E_PUTERM_DQ == ENABLED It is
sequential timing, not combinational (i.e., maybe the silicon is fast enough type) timing.
Boot requirements:
Offset: 0xbc | Read/Write: R/W | Reset: 0x00000008 (0bxxxxxxxxxxxxxxxxxxxxxxxxxx001000)
CTT: [PMC] time from read command to CTT turn-on.

DDR3 ? (CTT_TERMINATION == 1) ? CL + 7 : 0
5:0 0x8
LPDDR3: 0
45 = MAX
16.7.2.44 EMC_RFC_SLR_0

Boot requirements:
Offset: 0xc0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxx000000000)
8:0 0x0 RFC_SLR: [PMC] Specifies the stagger refresh cycle time between ranks. This is the
minimum number of cycles between an auto refresh command to one rank and a subsequent
auto refresh to another rank. A zero value indicates stagger refresh is disabled.
16.7.2.45 EMC_MRS_WAIT_CNT2_0
This register allows the delay between an MRS/EMRS/MRW/MRR command and the following DRAM command
Boot requirements:
Offset: 0xc4 | Read/Write: R/W | Reset: 0x0208000f (0bxxxxxx1000001000xxxxxx0000001111) | Default: 0x03ff03ff
25:16 0x208 0x3ff MRS_EXT2_WAIT_CNT: [PMC] Number of EMC clocks to wait before issuing

Memory Controller

any commands after sending an MRS ext2 command.
MRS_EXT1_WAIT_CNT: [PMC] Number of EMC clocks to wait before issuing

9:0 0xf 0x3ff
any commands after sending an MRS ext1 command.
16.7.2.46 EMC_MRS_WAIT_CNT_0
This register allows the delay between an MRS/EMRS/MRW/MRR command and the following DRAM command.
Boot requirements:
Offset: 0xc8 | Read/Write: R/W | Reset: 0x0208000f (0bxxxxxx1000001000xxxxxx0000001111)
MRS_LONG_WAIT_CNT: [PMC] Number of EMC clocks to wait before issuing

25:16 0x208 0x3ff
any commands after sending an MRS long command.
MRS_SHORT_WAIT_CNT: [PMC] Number of EMC clocks to wait before issuing

9:0 0xf 0x3ff
any commands after sending an MRS short command.
16.7.2.47 EMC_MRS_0
Command Trigger: MRS

The MRS register allows software to issue an MRS command.
BA0, BA1 are used to address MRS or EMRS registers in DRAM. Although this register can also program EMRS, use the
EMRS register so that the hardware registers can shadow what is in the DRAM.
Boot requirements:
Offset: 0xcc | Read/Write: R/W | Reset: 0x00000000 (0b00xx00xxxx00xxxxxx00000000000000)
MRS_DEV_SELECTN: [PMC] Active low chip-select, 0x0 applies command to both devices,
31:30 0x0
0x2 to for only dev0, 0x1 for only dev1.
USE_MRS_EXT_CNT: [PMC]
27 0x0 0 =USE_MRS_LONG_CNT will select between SHORT(0)/LONG(1),
1=USE_MRS_LONG_CNT will select between EXT1(0)/EXT2(1).
USE_MRS_LONG_CNT: [PMC] Indicate to use long or short MRS wait count.

26 SHORT 0 = SHORT
1 = LONG
21:20 0x0 MRS_BA: [PMC] Set to 0x0 for MRS.
13:0 0x0 MRS_ADR: [PMC] Mode-register data to be written.
16.7.2.48 EMC_EMRS_0
Command trigger: EMRS

The EMRS register allows software to issue an EMRS command.
Boot requirements:
Memory Controller
Offset: 0xd0 | Read/Write: R/W | Reset: 0x00000000 (0b00xxx0xxxx00xxxxxx00000000000000)
EMRS_DEV_SELECTN: [PMC] Active low chip-select, 0x0 applies command to both

31:30 0x0
devices, 0x2 to for only dev0, 0x1 for only dev1.
USE_EMRS_EXT_CNT: [PMC]
27 0x0 0 = USE_MRS_LONG_CNT will select between SHORT(0)/LONG(1),
1 = USE_MRS_LONG_CNT will select between EXT1(0)/EXT2(1).
USE_EMRS_LONG_CNT: [PMC] Indicate to use long or short MRS wait count.

26 SHORT 0 = SHORT
1 = LONG
EMRS_BA: [PMC] Set to 0x1 for EMRS (and where applicable, 0x2 for EMRS2, and 0x3 for
21:20 0x0
EMRS3).
13:0 0x0 EMRS_ADR: [PMC] Mode-register data to be written.
16.7.2.49 EMC_REF_0
Command Trigger: Refresh
Note: The REF register allows software to issue refresh commands. This is done to ensure
proper DRAM initialization.
Boot requirements:
 This register triggers a refresh command. REF_CMD should be written with 0x1 during cold boot to trigger refresh
commands during DRAM initialization.
Offset: 0xd4 | Read/Write: R/W | Reset: 0x00000000 (0b00xxxxxxxxxxxxxx00000000xxxxxx00)
REF_DEV_SELECTN: active low chip-select, 0x0 applies command to both devices, 0x2 to
31:30 0x0
for only dev0, 0x1 for only dev1.
15:8 0x0 REF_NUM: perform (REF_NUM + 1) refresh cycles.
REF_NORMAL:
0 = execute first refresh immediately (this is use during DRAM initialization).
1 0x0
1 = execute refresh through normal refresh mechanism (this should be used in normal
operation).
0 0x0 REF_CMD: causes the hardware to perform a REFRESH to all DRAM banks.
16.7.2.50 EMC_PRE_0
Command Trigger: Precharge-All

The PRE register allows software to issue a precharge all command. This command may be used to ensure proper DRAM
initialization.
Boot requirements:
 This register triggers a precharge-all command. PRE_CMD should be written with 0x1 during cold boot to trigger
refresh commands during DRAM initialization.
 If per-device DPD is used, the PRE_DEV_SELECTN field should be parameterized in the BCT and written by the
Boot ROM during cold boot.

Memory Controller
Offset: 0xd8 | Read/Write: R/W | Reset: 0x00000000 (0b00xxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
PRE_DEV_SELECTN: active low chip-select, 0x0 applies command to both devices, 0x2 to
31:30 0x0
0 0x0 PRE_CMD: causes the hardware to perform a PRECHARGE to all DRAM banks.
16.7.2.51 EMC_NOP_0
Command Trigger: NOP

The NOP register allows software to issue an explicit NOP command. This command may be used to ensure proper DRAM
initialization.
Boot requirements:
 This register triggers a no-operation command. NOP_CMD should be written with 0x1 during cold boot to trigger no-
op commands during DRAM initialization.
Offset: 0xdc | Read/Write: R/W | Reset: 0b00xxxxxxxxxxxxxxxxxxxxxxxxxxxxx0
NOP_DEV_SELECTN: active low chip-select, 0x0 applies command to both devices, 0x2 to
31:30 0x0
0 0x0 NOP_CMD: causes the hardware to perform a NOP to all DRAM banks.
16.7.2.52 EMC_SELF_REF_0
Command Trigger: SELF REFRESH

The SELF_REF register allows software to issue self-refresh commands.
Do not program this register when a clock change sequence is on-going. Check the CLKCHANGE_COMPLETE_INT value if
not sure.
Offset: 0xe0 | Read/Write: R/W | Reset: 0x00000000 (0b00xxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
SREF_DEV_SELECTN: active low chip-select, 0x0 applies command to both devices, 0x2 to
31:30 0x0
for only dev0, 0x1 for only dev1, 0x3 for neither device.
SELF_REF_CMD: causes the hardware to issue a SELF_REFRESH command. While

CMD:ENABLED, the CKE pin is held deasserted. The CMD:ENABLED state will override the
0 DISABLED PIN:CKE setting. The DRAM will ignore all accesses until CMD:DISABLED.
0 = DISABLED
1 = ENABLED
16.7.2.53 EMC_DPD_0
Command Trigger: Deep Power Down

The DPD register allows software to issue a deep power down command.
Offset: 0xe4 | Read/Write: R/W | Reset: 0x00000000 (0b00xxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
DPD_DEV_SELECTN: active low chip-select, 0x0 applies command to both devices, 0x2 to
31:30 0x0

Memory Controller
DPD_CMD: causes the hardware to issue the deep power down command (Burst Terminate
with CKE low). While in DPD mode, the DRAM will not maintain data integrity. While
CMD:ENABLED, the CKE pin is held deasserted. The CMD:ENABLED state will override the
0 DISABLED
PIN:CKE setting. The DRAM will ignore all accesses until CMD:DISABLED.
0 = DISABLED
1 = ENABLED
16.7.2.54 EMC_MRW_0
Command Trigger: MRW

Mode Register Write: LPDDR3-only version of MRS/EMRS
Boot requirements:
 This register triggers a mode register write command. Multiple mode-register writes may be required by the cold boot
sequence. Such commands should be parameterized in the BCT and written by the Boot ROM during cold boot.
Offset: 0xe8 | Read/Write: R/W | Reset: 0x00000000 (0b00xx00xx00000000xxxxxxxx00000000
MRW_DEV_SELECTN: [PMC] Active-low chip-select, 0x0 applies command to both devices,

31:30 0x0
0x2 to for only dev0, 0x1 for dev1.
27 0x0 USE_MRW_EXT_CNT: [PMC]

0 = USE_MRS_LONG_CNT will select between SHORT(0)/LONG(1),
26 SHORT USE_MRW_LONG_CNT: [PMC] Indicate to use long or short MRS wait count.
23:16 0x0 MRW_MA: [PMC] Register address
7:0 0x0 MRW_OP: [PMC] Data to be written
16.7.2.55 EMC_MRR_0
Command Trigger: MRR

Mode Register Read: LPDDR3 only
Sequence
1. Read MRR until EMC_STATUS.MRR_DIVLD=0 (ok to skip if it is sure there are no pending MRR reads)
2. Write this register with the desired addr (MA) and device (DEV_SELECTN), device needs to be either DEV0 or DEV1:
writing to both is illegal
3. Poll EMC_STATUS.MRR_DIVLD=1, or if using interrupt, wait for MRR_DIVLD_INT
4. Read back MRR. The value is in MRR_DATA field.
Note: It is okay to issue new MRR requests while there are on-going requests. For example, to issue 3 MRR requests, follow
these steps: 1,2,2,2,3,4,3,4,3,4. Data read back in step 4 is in the same order requested in step 2.
To make sure the EMC is available for new MRR requests, poll for EMC_STATUS.MRR_FIFO_SPACE > 0 before step 2.
If using 2 x16 DRAM, MRR_DATA[15:8] can be used to store MRR from the second DRAM on the same CS (configured via
CFG_3.MRR_BYTESEL_X16)

Memory Controller
Offset: 0xec | Read/Write: R/W | Reset: 0x0000XXXX (0b00xx00xx00000000xxxxxxxxxxxxxxxx)
MRR_DEV_SELECTN: active-low chip-select, choose which device to send the command to.
(enum for safety).
0 = ILLEGAL
31:30 RW 0x0
1 = DEV1
2 = DEV0
3 = RESERVED
USE_MRR_EXT_CNT:
27 RW 0x0 0 = USE_MRS_LONG_CNT will select between SHORT(0)/LONG(1),
USE_MRR_LONG_CNT: Indicate to use long or short MRS wait count.

26 RW SHORT 0 = SHORT
1 = LONG
23:16 RW 0x0 MRR_MA: register address
15:0 RO X MRR_DATA: data returned
16.7.2.56 EMC_CMDQ_0
Command Queue Depth Register

Boot requirements:
 This arbitration configuration register should be parameterized in the BCT and written by the OS during cold boot and
warm boot.
Offset: 0xf0 | Read/Write: R/W | Reset: 0x10004408 (0bxxx10000xxxxxxxxx100x100xxx01000)
28:24 0x10 RW_WD_DEPTH
14:12 0x4 PRE_DEPTH
10:8 0x4 ACT_DEPTH
4:0 0x8 RW_DEPTH
16.7.2.57 EMC_MC2EMCQ_0
Command Queue Depth Register

Boot requirements:
 This arbitration configuration register should be parameterized in the BCT and written by the OS during cold boot and
warm boot.
Offset: 0xf4 | Read/Write: R/W | Reset: 0x06000404 (0bxxxx0110xxxxxxxxxxxxx100xxxxx100)
27:24 0x6 MCWD_DEPTH
10:8 0x4 MCACT_DEPTH
2:0 0x4 MCREQ_DEPTH

Memory Controller
16.7.2.58 EMC_XM2DQSPADCTRL3_0
Offset: 0xf8 | Read/Write: R/W | Reset: 0x20820800 (0bx01000x01000x01000x01000xx0xxxx0)
30:26 0x8 EMC2PMACRO_CFG_XM2DQS_BYTE3_VREF_DQS: [PMC]
5 0x0 EMC2PMACRO_CFG_XM2DQS_E_VREF_DQS: [PMC]
0 0x0 EMC2PMACRO_CFG_XM2DQS_E_STRPULL_DQS: [PMC]
16.7.2.59 EMC_FBIO_SPARE_0
FBIO Spare Register

Note: CFG_FBIO_SPARE_0[1] = FBIO_SPARE[1] = lock further change to ADDR_SWIZZLE_STACK* and ADR_CFG.
registers.
Boot requirements:
 CFG_FBIO_SPARE_3 should be saved in the scratch registers and restored by the Boot ROM during warm boot.
31:24 0x0 CFG_FBIO_SPARE_3
16.7.2.60 EMC_FBIO_CFG5_0
FBIO Configuration Register

The trimmer value may be overridden by setting using MULT==0 and OFFS = value << 4.
The FBIO_CFG5 register controls the FBIO I/O cells.
The following fields are shadowed: DIFFERENTIAL_DQS, CTT_TERMINATION, DQS_PULLD, CMD_2T_TIMING.
Writes to these fields will not take effect until the active value is updated via TIMING_UPDATE or (if enabled)
CLKCHANGE_REQ.
Boot requirements:
 This register (except for field DISABLE_CONCURRENT_AUTOPRE) should be parameterized in the BCT and written
 This register (except for field DISABLE_CONCURRENT_AUTOPRE) should be saved in the scratch registers and
restored by the Boot ROM during warm boot.
Memory Controller
Offset: 0x104 | Read/Write: R/W | Reset: 0x10400815 (0bxxx1x000010000000000100000010101) | Default: 0x00400010
MASK_PUTERM_N_DQS_PULLD_DURING_ZQCAL:
[PMC] When this bit is enabled; it deasserts DQ/DQS puterm
28 ENABLED NONE and DQS pulld during ZQ calibration in hardware.
0 = DISABLED
1 = ENABLED
CMD_BUS_RETURN_TO_ONE: [PMC] this bit drives the

cmd bus back to a one as a resting stage (legacy Tegra
device behavior). Power is saved if this is not done (Tegra
26 DISABLED NONE
K1 behavior). Shadowed
0 = DISABLED
1 = ENABLED
LPDDR3_DRAM: [PMC] Enables differentiation between

lpddr3 DRAM protocol. Should only be set if LPDDR3 is
25 DISABLED NONE selected with DRAM_TYPE.
0 = DISABLED
1 = ENABLED
LPDDR3_WR_PREAMBLE_TOGGLE: [PMC] enable

LPDDR3 write preamble toggle.
24 DISABLED NONE
0 = DISABLED
1 = ENABLED
ERR_RD_BUBBLE: [PMC] Number of bubbles to be

inserted in CMDQ after every error-Read. A dummy read is
placed in CMDQ for each error read. This field controls the
number of emcclk bubbles inserted for each dummy read. It
23:20 0x4 0x4
is expected that this should be set to BL/2. Without this,
ret_stat_fifo will build up and block non-error reads. This
could cause ret_data_fifo to overflow as it is only 8 deep
(area savings) where as ret_stat_fifo is 20 deep. Shadowed
CMD_MAPPING:[PMC_SECURE] Shadowed. The

command mapping is locked from any additional updates
once fbio_spare[1] is set. The
MID_DDR3L_4X16_96_2T2B_SWONLY is a placeholder for
a software-based cmd mapping based on
MID_DDR3L_4X16_96_4TOP. The hardware register should
always be programmed to MID_DDR3L_4X16_96_4TOP.
0 = DDR3L_4X16
1 = DSC_LPDDR3_1X64_253
2 = DSC_LPDDR2_2X32_134
19:16 DDR3L_4X16 NONE 3 = DSC_LPDDR3_2X32_178
4 = DSC_DDR3L_2X32_136
5 = DSC_DDR3L_4X16_96_2X2H
6 = DSC_DDR3L_4X16_96_2X2V
7 = DSC_DDR3L_4X16_96_2TBV
8 = DSC_DDR3L_4X16_96_2TBH
9 = DSC_DDR3L_4X16_96_1X4_2LYR
10 = MID_DDR3L_4X16_96_4TOP
11 = MID_DDR3L_2X32_136
12 = MID_DDR3L_8X8_78_8TOP
13 = MID_DDR3L_4X16_96_4BOT
14 = MID_DDR3L_4X16_96_2T2B_SWONLY
EMC2PMACRO_CFG_QUSE_MODE: [PMC] Select QUSE

mode. Shadowed.
(NORMAL = off-chip)
(ALWAYS_ON = requires DQS PULL)
15:13 NORMAL NONE (INTERNAL_LPBK selects on-chip loopback)
(DIRECT_QUSE = directly controlled QUSE).
0 = NORMAL
1 = ALWAYS_ON
2 = INTERNAL_LPBK
3 = PULSE_INT

Memory Controller

4 = RESERVED
5 = DIRECT_QUSE
6 = RESERVED1
CMD_2T_TIMING: [PMC] Enable 2T command timing

(RAS/CAS/WE/ROW/A/BA). Shadowed.
12 DISABLED NONE
0 = DISABLED
1 = ENABLED
CFG_QUSE_EXTEND_HALF_CLK: [PMC] Extend the

QUSE window by half clk in DIRECT_QUSE mode.
11 ENABLED NONE Shadowed.
0 = DISABLED
1 = ENABLED
DISABLE_CONCURRENT_AUTOPRE: [PMC] Disables

reads/writes to a device until the precharge command has
10 DISABLED NONE been issued by the DRAM internally.
0 = DISABLED
1 = ENABLED
DQS_PULLD: [PMC] Enables pull-downs on DQS lines (and

pull-ups on DQS_N if DIFFERENTIAL_DQS). Shadowed.
9 DISABLED NONE
0 = DISABLED
1 = ENABLED
CTT_TERMINATION: [PMC] Enables CTT_TERMINATION

mode in pads (DDR2 support). Shadowed.
8 DISABLED NONE
0 = DISABLED
1 = ENABLED
DIFFERENTIAL_DQS: [PMC] Enables differential signaling

on DQS strobes. Shadowed.
7 DISABLED NONE
0 = DISABLED
1 = ENABLED
CFG_E_PUTERM_DQ: [PMC] Enables E_PUTERM_DQ

mode in pads (DDR3 support). In the IOBRICK, the
E_PUTERM_DQ mode overrides CTT_TERMINATION
6 DISABLED NONE mode. Shadowed.
0 = DISABLED
1 = ENABLED
DRAM_DATA_SWZL: [PMC] Specifies which half of the data

bytes are used in X32 mode.
LOWER:B0-B3
5 LOWER LOWER
UPPER:B4-B7
0 = LOWER
1 = UPPER
DRAM_WIDTH: [PMC] Specifies DRAM width. Platform

specific.
4 X64 X64
0 = X32
1 = X64
DRAM_BURST: [PMC] Specifies the burst length to use for

the attached device(s). ON_THE_FLY BC4/BL8 is only use
for DDR3. Shadowed.
3:2 BURST8 NONE 0 = BURST4
1 = BURST8
2 = ON_THE_FLY
3 = RESERVED
DRAM_TYPE: [PMC] Specifies which DRAM protocol to use

for the attached device(s).
0 = DDR3
1:0 DDR1 NONE
1 = DDR1
2 = LPDDR3
3 = DDR2

Memory Controller
16.7.2.61 EMC_FBIO_CFG6_0
FBIO Configuration Register

QUSE_LATE determines how much added delay FBIO should add to the QUSE path. QUSE needs to align (approximately)
with the incoming DQS in order to qualify it, since the incoming DQS/feedback clock is not always valid.
DRAMC can position QUSE with m2clk granularity (2 bit times). QUSE_LATE provides finer granularity of 1/2 an M2CLK
cycle (1/2 bit time). The amount of delay added is primarily a function of the round trip wire delay to/from the DRAM. Other
portions of the delay (driver and receiver delay) are compensated for by delay through a non-bonded QUSE pad cell.
Additional delay can be added to QUSE vi XFORM_QUSEx_MULT and XFORM_QUSEx_OFFS (applied to DLL offset).
Boot requirements:
2:0 0x2 CFG_QUSE_LATE: [PMC]
16.7.2.62 EMC_CFG_RSV_0
EMC Configuration Reserved

Offset: 0x120 | Read/Write: R/W | Reset: 0xff00ff00 (0b11111111000000001111111100000000)
31:24 0xff CFG_RESERVED_BYTE3
23:16 0x0 CFG_RESERVED_BYTE2
15:8 0xff CFG_RESERVED_BYTE1
7:0 0x0 CFG_RESERVED_BYTE0
16.7.2.63 EMC_ACPD_CONTROL_0
Threshold for ACPD

15:0 0x0 ACPD_THRESHOLD: [PMC] number of idle cycles to wait before allowing power-down entry
16.7.2.64 EMC_EMRS2_0
Command Trigger: EMRS2

The EMRS2 register allows software to issue an EMRS2 command.

Memory Controller
Boot requirements:
Offset: 0x12c | Read/Write: R/W | Reset: 0x00000000 (0b00xx00xxxx00xxxxxx00000000000000)
31:30 0x0 EMRS2_DEV_SELECTN: [PMC] active low chip-select, 0x0 applies command to both devices, 0x2 to
27 0x0 USE_EMRS2_EXT_CNT: [PMC] 0=>USE_MRS_LONG_CNT will select between

SHORT(0)/LONG(1), 1=>USE_MRS_LONG_CNT will select between EXT1(0)/EXT2(1).
26 SHORT USE_EMRS2_LONG_CNT: [PMC] Indicate to use long or short MRS wait count.
0 = SHORT
1 = LONG
21:20 0x0 EMRS2_BA: [PMC] Set to 0x1 for EMRS (and where applicable, 0x2 for EMRS2, and 0x3 for
EMRS3).
13:0 0x0 EMRS2_ADR: [PMC] mode-register data to be written.
16.7.2.65 EMC_EMRS3_0
Command Trigger: EMRS2

The EMRS3 register allows software to issue an EMRS3 command.
Boot requirements:
Offset: 0x130 | Read/Write: R/W | Reset: 0x00000000 (0b00xx00xxxx00xxxxxx00000000000000)
31:30 0x0 EMRS3_DEV_SELECTN: [PMC] active low chip-select, 0x0 applies command to both devices, 0x2 to
27 0x0 USE_EMRS3_EXT_CNT: [PMC] 0=>USE_MRS_LONG_CNT will select between

SHORT(0)/LONG(1), 1=>USE_MRS_LONG_CNT will select between EXT1(0)/EXT2(1).
26 SHORT USE_EMRS3_LONG_CNT: [PMC] Indicate to use long or short MRS wait count.
0 = SHORT
1 = LONG
21:20 0x0 EMRS3_BA: [PMC] Set to 0x1 for EMRS (and where applicable, 0x2 for EMRS2, and 0x3 for
EMRS3).
13:0 0x0 EMRS3_ADR: [PMC] mode-register data to be written.
16.7.2.66 EMC_MRW2_0
Command Trigger: MRW2

Mode Register Write: LPDDR3 -only version of MRS/EMRS
Boot requirements:
This register triggers a mode register write command. Multiple mode-register writes may be required by the cold boot
Offset: 0x134 | Read/Write: R/W | Reset: 0x00000000 (0b00xx00xx00000000xxxxxxxx00000000)

Memory Controller
31:30 0x0 MRW2_DEV_SELECTN: [PMC] active-low chip-select, 0x0 applies command to both devices, 0x2 to
for only dev0, 0x1 for dev1.
27 0x0 USE_MRW2_EXT_CNT: [PMC] 0=>USE_MRS_LONG_CNT will select between SHORT(0)/LONG(1),

1=>USE_MRS_LONG_CNT will select between EXT1(0)/EXT2(1).
26 SHORT USE_MRW2_LONG_CNT: [PMC] Indicate to use long or short MRS wait count.
0 = SHORT
1 = LONG
23:16 0x0 MRW2_MA: [PMC] register address
7:0 0x0 MRW2_OP: [PMC] data to be written
16.7.2.67 EMC_MRW3_0

Boot requirements:
Offset: 0x138 | Read/Write: R/W | Reset: 0x00000000 (0b00xx00xx00000000xxxxxxxx00000000)

0 = SHORT
1 = LONG
16.7.2.68 EMC_MRW4_0

Boot requirements:
Offset: 0x13c | Read/Write: R/W | Reset: 0x00000000 (0b00xx00xx00000000xxxxxxxx00000000)

0 = SHORT

Memory Controller

1 = LONG
16.7.2.69 EMC_CLKEN_OVERRIDE_0
Second-Level Clock Enable Override Register

Offset: 0x140 | Read/Write: R/W | Reset: 0x00000000 (0b0xxxxxxxxxxxxxxxxxxxxxxxx0xx000x)
31 DISABLED OBS_BUS_CLKEN:
0 = DISABLED
1 = ENABLED
6 CLK_GATED STATS_CLKEN_OVR:
0 = CLK_GATED
1 = CLK_ALWAYS_ON
0 = DISABLE
1 = ENABLE
0 = DISABLED
1 = ENABLED
3 CLK_GATED RR_CLKEN_OVR:
0 = CLK_GATED
1 = CLK_ALWAYS_ON
0 = DISABLE
1 = ENABLE
0 = DISABLED
1 = ENABLED
2 CLK_GATED DRAMC_CLKEN_OVR:
0 = CLK_GATED
1 = CLK_ALWAYS_ON
0 = DISABLE
1 = ENABLE
0 = DISABLED
1 = ENABLED
1 CLK_GATED CMDQ_CLKEN_OVR:
0 = CLK_GATED
1 = CLK_ALWAYS_ON
0 = DISABLE
1 = ENABLE
0 = DISABLED
1 = ENABLED
16.7.2.70 EMC_R2R_0

Boot requirements:

Memory Controller
3:0 0x0 R2R:
16.7.2.71 EMC_W2W_0

Boot requirements:
3:0 0x0 W2W:
16.7.2.72 EMC_EINPUT_0

Boot requirements:
5:0 0x0 EINPUT: [PMC] specifies when to assert EINPUT for a read, should normally be the same as QUSE.
16.7.2.73 EMC_EINPUT_DURATION_0

The minimum for EINPUT_DURATION is 4.
Boot requirements:
4:0 0x4 EINPUT_DURATION: [PMC] Specifies how long the EINPUT should be asserted.

Memory Controller
16.7.2.74 EMC_PUTERM_EXTRA_0

Boot requirements:
Offset: 0x154 | Read/Write: R/W | Reset: 0x00010000 (0bxxxxxxxxxx000001xxxxxxxxxxxxxxxx)
21:16 0x1 PUTERM: [PMC] tells the chip when to assert dynamic PUTERM for read return data.
16.7.2.75 EMC_TCKESR_0

Boot requirements:
5:0 0x3e TCKESR: [PMC] Specify minimum low CKE pulse width for self-refresh mode.
16.7.2.76 EMC_TPD_0

Boot requirements:
Offset: 0x15c | Read/Write: R/W | Reset: 0x0000003e (0bxxxxxxxxxxxxxxxxxxxxxxxxxx111110)
5:0 0x3e TPD: [PMC] specify minimum low CKE pulse width for power-down mode.

Memory Controller
16.7.2.77 EMC_AUTO_CAL_CONFIG_0
Auto-Calibration Settings for EMC Pads

Boot requirements:
 This register (except for AUTOCAL_SLW_OVERRIDE and AUTO_CAL_START(trigger)) should be parameterized in

the BCT and written by the Boot ROM during cold boot.
 This register (except for AUTOCAL_SLW_OVERRIDE and AUTO_CAL_START(trigger)) should be saved in the
scratch registers and restored by the Boot ROM during warm boot.
Offset: 0x2a4 | Read/Write: R/W | Reset: 0x00f10000 (0b0000xx001111x001xxx00000xxx00000)
AUTO_CAL_START: [PMC] Writing a one to this bit starts the calibration state machine.
31 RO 0x0
This bit must be set even if the override is set in order to latch in the override value.
AUTO_CAL_OVERRIDE: [PMC] 0 (normal operation): use AUTO_CAL_PU/PD_OFFSET as

30 RW 0x0 an offset to the calibration state machine setting 1 (override) : use
AUTO_CAL_PU/PD_OFFSET register values directly
AUTO_CAL_ENABLE: [PMC] 1 (normal operation): use EMC generated pullup/down

(override or autocal) 0 (disabled): use emc2tmc_cfg* register settings for pullup/down
29 RW DISABLED
0 = DISABLED
1 = ENABLED
AUTOCAL_SLW_OVERRIDE: [PMC] 0 (Normal operation) pad DRVDN/UP_SLWR/F tied to

28 RW 0x0 AUTO_CAL output DRDVDN/UP_SLWR/F[3:0] = AUTO_CAL_PULLDOWN/UP[4:1] 1
(override) use EMC2TMC_CFG*_DRVDN/UP_SLWR/F pins to control pad slew inputs
AUTO_CAL_E_CAL_UPDATE: [PMC] wait time in EMC clocks between clk cal code
25:20 RW 0xf change, and E_CAL_UPDATE assertion is AUTO_CAL_E_CAL_UPDATE - 4. Maximum
value is 31.
18:16 RW 0x1 AUTO_CAL_STEP: [PMC] calibration step interval (in microseconds)
12:8 RW 0x0 AUTO_CAL_PD_OFFSET: [PMC] 2's complement offset for the pull-down value
4:0 RW 0x0 AUTO_CAL_PU_OFFSET: [PMC] 2's complement offset for the DQ/DQS pull-up value
16.7.2.78 EMC_AUTO_CAL_INTERVAL_0
EMC Pad Calibration Interval

Boot requirements:
Offset: 0x2a8 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxx000000000000000000000)
AUTO_CAL_INTERVAL: [PMC] 0: Calibrate once. Otherwise, auto-calibration occurs at

20:0 0x0
intervals equivalent to the programmed number of microseconds.

Memory Controller
16.7.2.79 EMC_AUTO_CAL_STATUS_0
EMC Pad Calibration Status

Offset: 0x2ac | Read/Write: RO | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
AUTO_CAL_ACTIVE: One when auto calibrate is active - valid only after auto calibrate
31 X
sequence has completed (EMC_CAL_ACTIVE == 0)
28:24 X AUTO_CAL_PULLDOWN_ADJ: Pull-down code sent to pads
20:16 X AUTO_CAL_PULLUP_ADJ: Pull-up code sent to pads
12:8 X AUTO_CAL_PULLDOWN: Pull-down code generated by auto-calibration
4:0 X AUTO_CAL_PULLUP: Pull-up code generated by auto-calibration
16.7.2.80 EMC_REQ_CTRL_0
Request Status/Control
When either STALL_ALL_READS and/or STALL_ALL_WRITES is asserted, the stalling of read and/or write requests will not
take effect until the status bit from EMC_STATUS register's NO_OUTSTANDING_TRANSACTIONS field is asserted.
Offset: 0x2b0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00)
1 0x0 STALL_ALL_WRITES: Stall incoming write transactions
0 0x0 STALL_ALL_READS: Stall incoming read transactions
16.7.2.81 EMC_EMC_STATUS_0
EMC State-Machine Status

DRAM_IN_POWERDOWN, DRAM_IN_SELF_REFRESH, DRAM_IN_DPD: active high signal indicating current DRAM status
for each of these modes, with 1 status bit per device, bit[0] = dev0 status, bit[1] = dev1 status.
Example: DRAM_IN_SELF_REFRESH = 0x3, both devices are in self-refresh, DRAM_IN_DPD= 0x2 would indicate only dev1
is in deep-power-down mode.
Note: If EMC is reset or powered down, the actual DRAM state could be different than indicated by these status
bits. These bits do not reflect manually entered/exited powerdown or self-refresh (via use of PIN_CKE).
Offset: 0x2b4 | Read/Write: RO | Reset: 0x0XXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
27:26 X ACPD_FSM_IDLE: Indicate dev[n] power-down FSM is idle.
25:24 X DSR_FSM_IDLE: Indicate dev[n] dynamic self refresh FSM is idle.
TIMING_UPDATE_STALLED: Indicates timing update triggered by

23 X
TIMING_CONTROL.TIMING_UPDATE is not yet completed.
22 X ZQ_FSM_IDLE: Indicates auto ZQ state machine is idle.
21 X CFG_ZQ_ACTIVE: Indicates ZQ configuration access is active.
20 X MRR_DIVLD: MRR data available for reading
19:16 X MRR_FIFO_SPACE: MRR FIFO space available

Memory Controller
13:12 X DRAM_IN_DPD: dev[n] has been put into deep powerdown state
DRAM_IN_SELF_REFRESH: dev[n] has been put into self-refresh (will remain until SR exit
9:8 X
cmd).
DRAM_IN_POWERDOWN: dev[n] has entered powerdown state (incoming req's will awaken
5:4 X
if not stalled)
2 X NO_OUTSTANDING_TRANSACTIONS: All non-stalled requests have completed
0 X EMC_REQ_FIFO_EMPTY: Request FIFO is empty
16.7.2.82 EMC_CFG_2_0
EMC Configuration
Clock change sequencing: Once the divider is reprogrammed, CAR signals to EMC that a clock change is pending. If
enabled, EMC stalls incoming requests, drains outstanding requests, and, if CLKCHANGE_(PD|SR)_ENABLE is enabled, puts
DRAM into power-down (or self-refresh) before signalling to CAR that it is idle and ready for the change to happen. CAR will
then change the divider/pll reprogramming. Once complete, EMC updates its shadow registers (assuming they may have
been reprogrammed for new clock setting), unstalls requests, and resumes operation with new clock settings.
Some fields of this register are shadowed: see usage note at the top of Section 16.7.2
Boot requirements:
 This register (except for fields DRAMC_PRE_B4_ACT, MRR_BYTESEL_X16, MRR_BYTESEL) should be

parameterized in the BCT and written by the Boot ROM during cold boot.
Offset: 0x2b8 | Read/Write: R/W | Reset: 0x00008057 (0b0000000000xxxxxx1000000001010111)
DRAMC_PRE_B4_ACT: [PMC] Diagnostic bit, gives priority to activates over precharges,

determining which (precharge/activate) is processed first if both are pending and unblocked.
31 DISABLED
0 = DISABLED
1 = ENABLED
USE_PER_DEVICE_DLY_TRIM_OB: [PMC] Diagnostic bit. Shadowed. Allows using different

outbound delay trim values per device. When enabled, WDV must be programmed to >= 2
13 DISABLED and WEXT >=5.
0 = DISABLED
1 = ENABLED
USE_PER_DEVICE_DLY_TRIM_IB: [PMC] Diagnostic bit. Shadowed. Allows using different

inbound delay trim values per device. When enabled, REXT/RDV/QUSE must be
12 DISABLED programmed to >= 2.
0 = DISABLED
1 = ENABLED
DIS_CNTR_WITH_CFG_TIMING_UPDATE: [PMC] Diagnostic bit. 1 = Disable reset of timing

11 0x0
parameter counters with TIMING_CONTROL.TIMING_UPDATE.
9:8 0x0 Reserved
EARLY_TRFC_8_CLK: [PMC] Diagnostic bit. Shadowed.

7 0x0 1 = 8 clocks early
0 = 16 clocks early.
6 0x1 DIS_STP_OB_CLK_DURING_NON_WR: [PMC] 1 = Disables stopping outbound data clock

to I/O during non-write transactions.
5:3 0x2 ZQ_EXTRA_DELAY: [PMC] Additional delay to push out ZQCMD based on tODToff
(maximum) & frequency.
2 0x1 REF_AFTER_SREF: [PMC] 1 = Enables trigger of refresh after exiting self-refresh.

Memory Controller
CLKCHANGE_PD_ENABLE: [PMC] Forces DRAM into power-down during CLKCHANGE.

1 ENABLED 0 = DISABLED
1 = ENABLED
CLKCHANGE_REQ_ENABLE: [PMC] Allows the EMC and CAR to handshake on PLL

divider/source changes.
0 ENABLED
0 = DISABLED
1 = ENABLED
16.7.2.83 EMC_CFG_DIG_DLL_0
Configure Digital DLL

Controls for digital DLL's, which used to measure and maintain 1/4 cycle phase adjustment for RDQS strobes.
Boot requirements:
 This register (except for field CFG_DLL_ALARM_DISABLE and DLL_RESET (trigger) and
CFG_DLL_USE_OVERRIDE_UNTIL_LOCK(trigger)) should be parameterized in the BCT and written by the Boot
ROM during cold boot.
 This register (except for field CFG_DLL_ALARM_DISABLE and DLL_RESET (trigger) and
CFG_DLL_USE_OVERRIDE_UNTIL_LOCK(trigger)) should be saved in the scratch registers and restored by the
Boot ROM during warm boot.
Offset: 0x2bc | Read/Write: R/W | Reset: 0xXX0000Xd (0bx0000x000000000000000000011x11x1)
CFG_DLL_USE_OVERRIDE_UNTIL_LOCK: [PMC] Writing 1 to this register causes

31 RO X override_val to be used in place of DLL output until DLL_LOCK/DLL_LOCK_TIMEOUT
is obtained. Takes effect on next shadow update.
DLL_RESET: [PMC] Writing 1 to this register will send reset pulse to DLL's on next
30 RO 0x0 shadow update. Must reset DLLs when changing clock frequency by factor >= 2. Reset
occurs at next shadow update.
CFG_DLL_LOCK_LIMIT: [PMC] Diagnostic in case DLL has problems locking.

Shadowed. DLL will be treated as locked after LIMIT µs. Counter is reset with
DLL_RESET (from above) or with each periodic update (if using RUN_PERIODIC).
Settings are:
29:28 RW 0x0
00: LIMIT = 16 µs
01: LIMIT = 64 µs
10: LIMIT = 128 µs
11: LIMIT = 512 µs
CFG_DLL_ALARM_DISABLE: [PMC] Diagnostic bit. Shadowed. Disable override of

27 RW 0x0
DLL logic when DLL_ALM is set (otherwise overrides DLI to 0x3FF).
CFG_DLL_UPDATE_AT_NXT_REFRESH: Writing 1 to this register causes the

DLCELL update to occur at the next REFRESH interval. Ordinarily, updates are only
26 RO X
performed if the DLL value is updated. This mechanism allows updates to the
XFORM_MULT/OFF to be taken at the next REFRESH.
CFG_DLL_OVERRIDE_VAL: [PMC] Value to use in place of DLI output if

25:16 RW 0x0 CFG_DLL_OVERRIDE_EN is set or prior to lock in RUN_TIL_LOCK mode.
Shadowed.
15 RW 0x0 CFG_DLL_TESTEN: [PMC] Enable DLL test mode
14 RW 0x0 CFG_DLL_QUSE_TESTOUT: [PMC] Enable DLL TESTOUT on QUSE pads
13:12 RW 0x0 CFG_DLL_TESTSEL: [PMC] Select DLL test output

Memory Controller
11:8 RW 0x0 CFG_DLL_UDSET: [PMC] DLL Loop filter control (2^(udset+3)). Shadowed.
CFG_DLL_MODE: [PMC] Controls how frequently DLL runs. Shadowed.

0 = RUN_CONTINUOUS: DLL will run continuously. This option will consume the most
power. Once LOCK/TIMEOUT occurs, trimmers will be updated at REFRESH or
shadow update.
7:6 RW RUN_TIL_LOCK 1 = RUN_TIL_LOCK: after DLL_RESET is set, DLL will run until it has locked/timed
out, then be disabled. Trimmers updated at following REFRESH/shadow update.
2 = RUN_PERIODIC: after DLL_LOCK/TIMEOUT, DLL will be disabled and re-enabled
after CFG_DLL_RUN_PERIOD µs to track delay changes (temperature/voltage).
3 = RESERVED
CFG_DLL_LOWSPEED: [PMC] Enable DLL for use with low-speed EMCCLK

5 RW 0x1 operation (< 200 MHz). Shadowed. The DLL does power optimization by itself. This
control should stay at 1.
CFG_DLL_STALL_RW_UNTIL_LOCK: [PMC] Writing 1 to this register will cause the

4 RO X
EMC to stall all RW traffic until the DLL locks. Takes effect on the next shadow update.
CFG_DLL_STALL_ALL_TRAFFIC: [PMC] Enables stalling of all DRAM traffic while

3 RW 0x1 undergoing dll_stall condition;otherwise only block reads/writes are stalled during
dll_stall. Shadowed.
CFG_DLL_OVERRIDE_EN: [PMC] Override DLL's DLI output with OVERRIDE_VAL

(still uses mult/offset). Shadowed.
2 RW ENABLED
0 = DISABLED
1 = ENABLED
CFG_DLL_EN: [PMC] Enables digital DLL. Shadowed.

0 RW ENABLED 0 = DISABLED
1 = ENABLED
16.7.2.84 EMC_CFG_DIG_DLL_PERIOD_0
CFG_DLL_RUN_PERIOD: [PMC] If CFG_DLL_MODE == RUN_PERIODIC, this specifies the

15:0 0x8000
interval between runs in microseconds.
16.7.2.85 EMC_DIG_DLL_STATUS_0
Digital DLL Status

Digital DLL Status bits directly from the DLL
Offset: 0x2c8 | Read/Write: RO | Reset: 0x0000XXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
15 X DLL_LOCK
14 X DLL_ALARM
13 X DLL_LOCK_TIMEOUT
9:0 X DLL_OUT

Memory Controller
16.7.2.86 EMC_RDV_MASK_0

Boot requirements:
Offset: 0x2cc | Read/Write: R/W | Reset: 0x0000003f (0bxxxxxxxxxxxxxxxxxxxxxxxxxx111111)
5:0 0x3f RDV_MASK: [PMC] This should be programmed to RDV.
16.7.2.87 EMC_WDV_MASK_0

Boot requirements:
Offset: 0x2d0 | Read/Write: R/W | Reset: 0x0000000f (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111)
3:0 0xf WDV_MASK: [PMC] This should be programmed to WDV.
16.7.2.88 EMC_CTT_DURATION_0

CTT_DURATION controls how long CTT remains enabled. If CTT + CTT_DURATION - RDV - 2 > 0, R2W must be
increased by that amount.
Offset: 0x2d8 | Read/Write: R/W | Reset: 0x00000003 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx0011)
CTT_DURATION: [PMC] Determines how long CTT remains enabled during reads. CTT
determines when it will be enabled.
3:0 0x3
DDR3: CTT_TERMINATION == 1 ? 4 : 0
LPDDR3: 0
16.7.2.89 EMC_CTT_TERM_CTRL_0
Configure CTT Termination Output Drive Strength

If CTT_TERMINATION is enabled, this controls the strength of the output drivers.
TERM_OVERRIDE forces use of EMC2TMC_CFG*_DRVDN_TERM, EMC2TMC_CFG*_DRVUP_TERM instead of using of

AUTO_CAL DRVDN/DRVUP values with the following equation applied:

Memory Controller
TERM_DRDN = (AUTO_CAL_DRVDN * TERM_SLOPE) / 4 + TERM_OFFSET

TERM_DRUP = (AUTO_CAL_DRVUP * TERM_SLOPE) / 4 + TERM_OFFSET
Recommended values for SLOPE/OFFSET
100ohm CTT: TERM_SLOPE = 0x1, TERM_OFFSET = 0x4

50ohm CTT: TERM_SLOPE = 0x2, TERM_OFFSET = 0x8
Note: setting slope = 0 allows TERM_DRDN/DRVUP = TERM_OFFSET
setting slope > 2 is not supported
Boot requirements:
 This register (except for fields TERM_DRVDN and TERM_DRVUP) should be parameterized in the BCT and written
 This register (except for fields TERM_DRVDN and TERM_DRVUP) should be saved in the scratch registers and
restored by the Boot ROM during warm boot.
Offset: 0x2dc | Read/Write: R/W | Reset: 0xXX0XX802 (0b0xxxxxxxxxxxxxxxxxx01000xxxxx010)
TERM_OVERRIDE: [PMC]
31 RW DISABLED 0 = DISABLED
1 = ENABLED
28:24 RO X TERM_DRVUP
19:15 RO X TERM_DRVDN
12:8 RW 0x8 TERM_OFFSET: [PMC]
2:0 RW 0x2 TERM_SLOPE: [PMC]
ZQ Calibration Registers -- LPDDR3/DDR3

1. Periodic mode
Allows a ZQ calibration command to be sent periodically to DRAM. After ZCAL_INTERVAL, ZCAL_MRW_CMD will be sent to
each DRAM, 1 at a time, followed by ZCAL_WAIT_CNT interval in which no other commands will be allowed to be sent to
either DRAM. So if ZQ_MRW_DEV_SELECTN == 2'b00, it would send the MRW command to dev0, wait ZCAL_WAIT_CNT,
send the command to dev1, wait ZCAL_WAIT_CNT, resume normal operation. It will then wait ZCAL_INTERVAL
microseconds before repeating the procedure. The ZQ calibration command will not be sent to devices that are 1)
unpopulated and 2) either in or about to enter self-refresh or DPD.
To enable periodic ZQ calibration, program ZCAL_INTERVAL and ZCAL_WAIT_CNT to be non-zero, as well as

ZCAL_MRW_CMD to contain the command and device selection, followed by TIMING_CONTROL to latch those three
registers.
Note that ZCAL_WAIT_CNT will be used instead of MRS_WAIT_CNT for delaying the subsequent DRAM commands after the
ZQ calibration commands, even though in LPDDR3 a ZQ calibration command is also an MRW command.
Disable this feature by setting ZCAL_INTERVAL.ZCAL_REF_INTERVAL = 0, followed by TIMING_CONTROL to latch it.
2. One-shot mode
Allows ZQ calibration command to be sent to DRAM.
To send a one-shot command, keep ZCAL_INTERVAL and ZCAL_WAIT_CNT equal to zero, program ZCAL_MRW_CMD with
only one device selected, then program TIMING_CONTROL to latch in those registers, and finally program

Memory Controller
ZCAL_ONE_SHOT to 1 to trigger the one-shot command. If more than one device needs to be calibrated, wait the ZQ
calibration time and repeat the steps above with the other device selection bit enabled in ZCAL_MRW_CMD.
Do not send a one-shot ZQ calibration command when periodic mode is enabled.
16.7.2.90 EMC_ZCAL_INTERVAL_0
Configure ZQ Calibration
Boot requirements:
Offset: 0x2e0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxx000000000000000000000000)
ZCAL_INTERVAL_HI: [PMC] Combined with ZCAL_INTERVAL_LO specifies the number of

23:10 0x0 microseconds to wait between issuance of ZCAL_MRW_CMD. If 0, ZCAL is disabled and
internal counter will be reset.
9:0 0x0 ZCAL_INTERVAL_LO [PMC]
16.7.2.91 EMC_ZCAL_WAIT_CNT_0
Boot requirements:
Offset: 0x2e4 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxx0000000000)
ZCAL_WAIT_CNT: [PMC] Number of EMC clocks to wait before issuing any commands after
9:0 0x0
sending ZCAL_MRW_CMD.
16.7.2.92 EMC_ZCAL_MRW_CMD_0
(However, it does not obey READ_MUX/WRITE_MUX non-default values.)
Boot requirements:
Offset: 0x2e8 | Read/Write: R/W | Reset: 0xc0000000 (0b11xxxxxx00000000xxxxxxxx00000000)
31:30 0x3 ZQ_MRW_DEV_SELECTN: [PMC] Active-low chip-select, 0x0 applies command to both

Memory Controller

devices (will happen 1 at a time), 0x2 to for only dev0, 0x1 for dev1.
23:16 0x0 ZQ_MRW_MA: [PMC] MRW MA field to be sent after ZCAL_INTERVAL
7:0 0x0 ZQ_MRW_OP: [PMC] MRW OP field to be sent after ZCAL_INTERVAL
16.7.2.93 EMC_ZQ_CAL_0
Trigger a Single ZQ Calibration

This register issues a ZQ calibration command for DDR3.
Offset: 0x2ec | Read/Write: R/W | Reset: 0x00000010 (0b00xxxxxxxxxxxxxxxxxxxxxxxxx1xxx0)
ZQ_CAL_DEV_SELECTN: Active low chip-select, 0x0 applies command to both devices, 0x2
31:30 0x0 to for only dev0, 0x1 for only dev1, 0x3 for neither device (0x0, for both devices, is not allowed
if the ZQ resister is shared between devices).
ZQ_CAL_LENGTH: Indicate short or long ZQ calibration.

4 LONG 0 = SHORT
1 = LONG
0 0x0 ZQ_CAL_CMD: Issues a ZQ calibration command (DDR3 only).
16.7.2.94 EMC_XM2CMDPADCTRL_0
Pad configuration registers from APB_MISC:
XM2CMD Pad Control Register

Boot requirements:
Offset: 0x2f0 | Read/Write: R/W | Reset: 0x10000200 (0bxxx1xxxxxxxxxxxxxxxxx01000000xxx)
EMC2TMC_CFG_XM2RESET_E_PULLUP: [PMC] Select pullup mode on reset pad

1 = ENABLE
CFG_XM2CMD_CAL_SELECT: [PMC] Choose VREF/NORMAL (DQ/DQS) calibration for

CMD pads.
10 NORMAL
0 = NORMAL
1 = VREF
EMC2TMC_CFG_XM2RESET_E_DDR3: [PMC] Select pad mode

1 = ENABLE
EMC2PMACRO_CFG_XM2CMD_PHASESHIFT: [PMC] Shift cmd outputs by 1/2 cycle (useful

for DDR3 in place of DIGTRIM)
8 DISABLE
0 = DISABLE
1 = ENABLE
EMC2TMC_CFG_XM2CMD_E_DDR3: [PMC] Select pad mode

1 = ENABLE

Memory Controller
EMC2TMC_CFG_XM2CMD_CLK_SEL: [PMC] pad clk_sel (ma bits get this value inverted in
6 0x0
LPDDR3 mode)
EMC2TMC_CFG_XM2CMD_E_PREEMP: [PMC] XM2CMD data pins pre-emp enable

5 0x0 0 = DISABLE
1 = ENABLE
EMC2TMC_CFG_XM2CMD_E_BYPASS: [PMC] XM2CMD pins bypass outbound flop enable

4 0x0 0 = DISABLE
1 = ENABLE
EMC2TMC_CFG_XM2CMD_E_PWRD: [PMC] XM2CMD pins pad power-down signal

3 0x0 0 = DISABLE
1 = ENABLE
16.7.2.95 EMC_XM2CMDPADCTRL2_0
Offset: 0x2f4 | Read/Write: R/W | Reset: 0x050c0000 (0b000001010000110000xxxxxxxxxxxxxx) | Default: 0x858c0000
31:28 0x0 0x8 EMC2PMACRO_CFG_XM2CMD_DRVUP_SLWF [PMC]
27:24 0x5 0x5 EMC2PMACRO_CFG_XM2CMD_DRVDN_SLWR [PMC]
23:19 0x1 0x11 EMC2PMACRO_CFG_XM2CMD_DRVUP [PMC]
18:14 0x10 0x10 EMC2PMACRO_CFG_XM2CMD_DRVDN [PMC]
16.7.2.96 EMC_XM2DQSPADCTRL_0
XM2DQS Pad Control Register

Boot requirements:
Offset: 0x2f8 | Read/Write: R/W | Reset: 0x490c1414 (0b010010010000110000x10100xxx10100) | Default: 0x888c1414
31:28 0x4 0x8 EMC2PMACRO_CFG_XM2DQS_DRVUP_SLWF [PMC]
27:24 0x9 0x8 EMC2PMACRO_CFG_XM2DQS_DRVDN_SLWR [PMC]
23:19 0x1 0x11 EMC2PMACRO_CFG_XM2DQS_DRVUP [PMC]
18:14 0x10 0x10 EMC2PMACRO_CFG_XM2DQS_DRVDN [PMC]
12:8 0x14 0x14 EMC2PMACRO_CFG_XM2DQS_DRVUP_TERM [PMC]
4:0 0x14 0x14 EMC2PMACRO_CFG_XM2DQS_DRVDN_TERM [PMC]
XM2DQS Pad Control Register

Boot requirements:
Memory Controller
Offset: 0x2fc | Read/Write: R/W | Reset: 0x0000be18 (0bxxxxxxx0xx0000001011111000011000)
24 0x0 EMC2TMC_CFG_XM2DQS_QUSE_DLL_BYP: [PMC]

0 = DISABLE
1 = ENABLE
21:20 0x0 EMC2TMC_CFG_XM2DQS_CONFIG: [PMC] IOBRICK rfu pins
19:18 0x0 EMC2TMC_CFG_XM2DQS_RX_DQS_SEL: [PMC] IOBRICK rfu pins
EMC2TMC_CFG_XM2DQS_RX_DQ_SEL: [PMC] [0] = select between legacy mode (0) or

17:16 0x0
LSSA mode (1) DQ RX. [1]=RFU
15 0x1 EMC2TMC_CFG_XM2DQS_E_SCHMT_DQ: [PMC] XM2DQ DQ pins Schmitt enable

0 = DISABLE
1 = ENABLE
EMC2TMC_CFG_XM2DQS_E_PWRD: [PMC] XM2DQS pins pad power-down signal

14 0x0 0 = DISABLE
1 = ENABLE
EMC2TMC_CFG_XM2DQS_E_SCHMT_DQS: [PMC] XM2DQS DQS pins Schmitt enable

13 0x1 0 = DISABLE
1 = ENABLE
EMC2TMC_CFG_XM2DQS_QUSE_DLI_EN: [PMC] Active low

1 = DISABLE
EMC2TMC_CFG_XM2DQS_TXDQS_DLI_EN: [PMC] Active low

1 = DISABLE
EMC2TMC_CFG_XM2DQS_TXDQ_DLI_EN: [PMC] Active low

1 = DISABLE
EMC2TMC_CFG_XM2DQS_RX_DLI_EN: [PMC] Active low

1 = DISABLE
EMC2TMC_CFG_XM2DQS_E_DDR3: [PMC] Select pad mode

1 = ENABLE
7 0x0 EMC2TMC_CFG_XM2DQS_CLKSEL_DQS: [PMC]
6 0x0 EMC2TMC_CFG_XM2DQS_CLKSEL_DQ: [PMC]
EMC2TMC_CFG_XM2DQS_E_VREF_DQ: [PMC]
5 0x0 0 = DISABLE
1 = ENABLE
EMC2TMC_CFG_XM2DQS_E_CTT_HIZ_DQS: [PMC]
1 = ENABLE
EMC2TMC_CFG_XM2DQS_E_CTT_HIZ_DQ: [PMC]
1 = ENABLE
EMC2TMC_CFG_XM2DQS_E_PREEMP: [PMC] CFG_XM2DQ data pins pre-emp enable

2 0x0 0 = DISABLE
1 = ENABLE
EMC2TMC_CFG_XM2DQS_E_BYPASS: [PMC] CFG_XM2DQ data pins bypass outbound

flop enable
1 0x0
0 = DISABLE
1 = ENABLE

Memory Controller
EMC2TMC_CFG_XM2DQS_E_RX_FT_REC: [PMC]
0 0x0 0 = DISABLE
1 = ENABLE
16.7.2.98 EMC_XM2DQPADCTRL_0
CFG_XM2DQ Pad Control Register

These values only used if autocal is disabled
Offset: 0x300 | Read/Write: R/W | Reset: 0x490c2990 (0b0100100100001100001010011001xxxx) | Default: 0x888c2990
31:28 0x4 0x8 EMC2PMACRO_CFG_XM2DQ_DRVUP_SLWF [PMC]
27:24 0x9 0x8 EMC2PMACRO_CFG_XM2DQ_DRVDN_SLWR [PMC]
23:19 0x1 0x11 EMC2PMACRO_CFG_XM2DQ_DRVUP [PMC]
18:14 0x10 0x10 EMC2PMACRO_CFG_XM2DQ_DRVDN [PMC]
13:9 0x14 0x14 EMC2PMACRO_CFG_XM2DQ_DRVUP_TERM [PMC]
8:4 0x19 0x19 EMC2PMACRO_CFG_XM2DQ_DRVDN_TERM [PMC]
16.7.2.99 EMC_XM2DQPADCTRL2_0
Boot requirements:
Offset: 0x304 | Read/Write: R/W | Reset: 0x00000000 (0bx000x000x000x000xxxxxxxxxxxxxxxx)
30:28 0x0 EMC2TMC_CFG_XM2DQ3_DLYIN_TRM: [PMC3] delay trim for byte 3
16.7.2.100 EMC_XM2CLKPADCTRL_0
XM2CLK Pad Control Register

Boot requirements:
Offset: 0x308 | Read/Write: R/W | Reset: 0xffffc000 (0b1111111111111111110000000xx000x0)
31:28 0xf EMC2PMACRO_CFG_XM2CLK_DRVUP_SLWF [PMC]

Memory Controller
27:24 0xf EMC2PMACRO_CFG_XM2CLK_DRVDN_SLWR [PMC]
23:19 0x1f EMC2PMACRO_CFG_XM2CLK_DRVUP: [PMC]
18:14 0x1f EMC2PMACRO_CFG_XM2CLK_DRVDN: [PMC]
EMC2TMC_CFG_XM2CLK_E_DDR3: [PMC] Select pad mode

1 = ENABLE
EMC2TMC_CFG_XM2CLK_E_PWRD: [PMC] XM2CLK pins pad power-down signal

1 = ENABLE
EMC2TMC_CFG_XM2CLK_E_CAL_BYPASS: [PMC] XM2CLK bypass drvdown/up

calibration
3 DISABLE
0 = DISABLE
1 = ENABLE
EMC2TMC_CFG_XM2CLK_E_PREEMP: [PMC] pre-emphasis enable

1 = ENABLE
EMC2PMACRO_CFG_DYN_PULLS_ON_CLKDIS: [PMC] Enable pull-up on CLKP and pull-

down on CLKN when disabling clock. Reserved in case clock startup ramp is too slow
0 DISABLE (DDR3).
0 = DISABLE
1 = ENABLE
16.7.2.101 EMC_XM2COMPPADCTRL_0
MEM_COMP Pad Control Register

Boot requirements:
Offset: 0x30c | Read/Write: R/W | Reset: 0x81f1f008 (0b10000xx11111xxx11111000000001000)
31:28 0x8 EMC2TMC_CFG_XM2COMP_PU_VREF_SEL: [PMC]
27 0x0 EMC2TMC_CFG_XM2COMP_PU_VREF_SEL4: [PMC] bit 4 of the PU_VREF_SEL
24:20 0x1f CFG_XM2COMP_DRVUP: [PMC] used if AUTOCAL is disabled
16:12 0x1f CFG_XM2COMP_DRVDN: [PMC] used if AUTOCAL is disabled
EMC2TMC_CFG_XM2COMP_E_TESTOUT: [PMC]
1 = ENABLE
CFG_XM2COMP_VREF_CAL_EN: [PMC] When enabled (=1), generate MCLK calibration

cycle.
10 DISABLE
0 = DISABLE
1 = ENABLE
EMC2TMC_CFG_XM2COMP_E_PWRD: [PMC] XM2CLK pins pad power-down signal

1 = ENABLE
EMC2TMC_CFG_XM2COMP_E_DDR3: [PMC] Select pad mode

1 = ENABLE

Memory Controller
7:5 0x0 EMC2TMC_CFG_XM2COMP_BIAS_SEL: [PMC]
4:0 0x8 EMC2TMC_CFG_XM2COMP_PD_VREF_SEL: [PMC] VREF_SEL for CK
16.7.2.102 EMC_XM2VTTGENPADCTRL_0
XM2 MISC/VTTGEN Pad Control Register

Boot requirements:
Offset: 0x310 | Read/Write: R/W | Reset: 0x07070000 (0bxxxxx111xxxxx111xxxxxxxxxxxxx0x0)
26:24 0x7 EMC2TMC_CFG_XM2VTTGEN_DRVUP: [PMC]
18:16 0x7 EMC2TMC_CFG_XM2VTTGEN_DRVDN: [PMC]
2 0x0 EMC2TMC_CFG_XM2VTTGEN_E_DDR3: [PMC] Select pad mode
0 0x0 EMC2TMC_CFG_XM2VTTGEN_SHORT: [PMC]
16.7.2.103 EMC_XM2VTTGENPADCTRL2_0
 E_WEAK_BIAS: enables low current bias mode on VTTGEN cell
 E_NO_VTTGEN: disables VTTGEN altogether. One VTTGEN pad in each MEM section is always enabled (DDR3-
only)
Offset: 0x314 | Read/Write: R/W | Reset: 0x00000000 (0b0000xxxxxxxxxxxxxxxxxxxxxx000000)
EMC2TMC_CFG_XM2VTTGEN_MEMEXCLK_WEAK_BIAS: [PMC] Enable BIAS mode

current mode during DPD -- MEM group excluding CLK
31:30 DISABLE 0 = DISABLE
1 = ENABLE
2 = RESERVED
EMC2TMC_CFG_XM2VTTGEN_MEMCLK_WEAK_BIAS: [PMC] Enable BIAS mode current

mode during DPD -- MEMCLK pad group
29:28 DISABLE 0 = DISABLE
1 = ENABLE
2 = RESERVED
EMC2TMC_CFG_XM2VTTGEN_E_NO_VTTGEN: [PMC] Disable optional VTTGEN pads (1

bit per pad)
[0]--ADDR0
[1]--ADDR1
5:0 0x0
[2]--ADDR2
[3]--DATA1
[4]--DATA2
[5]--DATA3

Memory Controller
16.7.2.104 EMC_XM2VTTGENPADCTRL3_0
Offset: 0x318 | Read/Write: R/W | Reset: 0x013bbbbb (0bxxxxxxx1x01110111011101110111011)
24 0x1 EMC2TMC_CFG_XM2VTTGEN_VAUXP_BACKUP_BYTE: [PMC]
22:20 0x3 EMC2TMC_CFG_XM2VTTGEN_VAUXP_LEVEL_BYTE: [PMC]
19 0x1 EMC2TMC_CFG_XM2VTTGEN_VCLAMP_BACKUP_BYTE: [PMC]
18:16 0x3 EMC2TMC_CFG_XM2VTTGEN_VCLAMP_LEVEL_BYTE: [PMC]
15 0x1 EMC2TMC_CFG_XM2VTTGEN_VAUXP_BACKUP_CMD: [PMC]
14:12 0x3 EMC2TMC_CFG_XM2VTTGEN_VAUXP_LEVEL_CMD: [PMC]
11 0x1 EMC2TMC_CFG_XM2VTTGEN_VCLAMP_BACKUP_CMD: [PMC]
10:8 0x3 EMC2TMC_CFG_XM2VTTGEN_VCLAMP_LEVEL_CMD: [PMC]
7 0x1 EMC2TMC_CFG_XM2VTTGEN_VAUXP_BACKUP_CLK: [PMC]
6:4 0x3 EMC2TMC_CFG_XM2VTTGEN_VAUXP_LEVEL_CLK: [PMC]
3 0x1 EMC2TMC_CFG_XM2VTTGEN_VCLAMP_BACKUP_CLK: [PMC]
2:0 0x3 EMC2TMC_CFG_XM2VTTGEN_VCLAMP_LEVEL_CLK: [PMC]
16.7.2.105 EMC_EMCPADEN_0
EMC pad enable register

Writing 0 will disable listed direction
Offset: 0x31c | Read/Write: R/W | Reset: 0x00000003 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11)
EMC2PMACRO_CFG_PAD_INPUT_EN: Inputs enable for EMC pads

1 0x1 0 = DISABLE
1 = ENABLE
EMC2PMACRO_CFG_PAD_OUTPUT_EN: Outputs enable for EMC pads

0 0x1 0 = DISABLE
1 = ENABLE
Offset: 0x320 | Read/Write: R/W | Reset: 0x00208208 (0bxxxxxxxxx01000x01000x01000x01000)
22:18 0x8 EMC2TMC_CFG_XM2DQS_BYTE3_VREF_DQ: [PMC]

Memory Controller
16.7.2.107 EMC_SCRATCH0_0
This is a scratch register for general use.
31:0 0x0 SCRATCH:
16.7.2.108 EMC_DLL_XFORM_DQS0_0

XFORM_DQSx_MULT and XFORM_DQSx_OFFS are a multiplier and offset, respectively, that can be used to modify the DLL
output. Final products may be read out in DQS_TRIMMER_RD register. The default is multiply by 1 to keep the DLL's 1/4
cycle delay. Integer + fractional formats for multiplier and offset:
OFFS is 2's complement format, with bit [0] representing integer
The output of the XFORM is xform_out = (xform_in * MULT + OFFS*16)/ 16
Largest allowed MULT = 0x17
In the case of overflow, output is clamped according to these rules:
 out >= 0x600, xform_out = 0x000

 0x600 > out >= 0x400, xform_out = 0x3ff
That means clamping works within 50% above the maximum (0x3ff) DLL output or 50% below the minimum (0) DLL output.
To make sure that is always satisfied, conservatively program OFFS so that 0x600 < OFFS < (0x5ff – ((MULT * 0x3ff) >> 4)).
The DLL output is effectively overridden by setting XFORM_*_MULT to 0 and programming XFORM_*_OFFS[8:1] to override
value.
Boot requirements:
The DQS_CURRENT_TRIM_VAL_BYTE_x registers provide a way to observe the values being used by the trimmers
Offset: 0x328 | Read/Write: R/W | Reset: 0x007ff010 (0bxxxxxxxxx11111111111xxxxxxx10000)
22:12 0x7ff XFORM_DQS0_OFFS: [PMC]
4:0 0x10 XFORM_DQS0_MULT: [PMC]

Memory Controller

Offset: 0x32c | Read/Write: R/W | Reset: 0x007ff010 (0bxxxxxxxxx11111111111xxxxxxx10000)




Memory Controller

Offset: 0x33c | Read/Write: R/W | Reset: 0x007ff010 (0bxxxxxxxxx11111111111xxxxxxx10000)


16.7.2.116 EMC_DLL_XFORM_QUSE0_0

XFORM_QUSEx_MULT and XFORM_QUSEx_OFFS are a multiplier and offset, respectively, that can be used to modify the
DLL output. Final product may be read out in DQS_TRIMMER_RD register. The default is multiply by 1/2, to give 1/8 cycle
delay.
OFFS is 2's complement format, with bit [0] representing integer. The output of the XFORM is xform_out = (xform_in * MULT
+ OFFS*16)/ 16
 out >= 0x600, xform_out = 0x000

That means clamping works within 50% above the maximum (0x3ff) DLL output or 50% below the minimum (0) DLL output. To
make sure that is always satisfied, conservatively program OFFS so that 0x600 < OFFS < (0x5ff – ((MULT * 0x3ff) >> 4)). The
Memory Controller
DLL output is effectively overridden by setting XFORM_*_MULT to 0 and programming XFORM_*_OFFS[8:1] to override
value.
Boot requirements:
Offset: 0x348 | Read/Write: R/W | Reset: 0x0000000c (0bxxxxxxxxx00000000000xxxxxxx01100)
22:12 0x0 XFORM_QUSE0_OFFS: [PMC]
4:0 0xc XFORM_QUSE0_MULT: [PMC]

Offset: 0x34c | Read/Write: R/W | Reset: 0x0000000c (0bxxxxxxxxx00000000000xxxxxxx01100)



Memory Controller


Offset: 0x35c | Read/Write: R/W | Reset: 0x0000000c (0bxxxxxxxxx00000000000xxxxxxx01100)


16.7.2.124 EMC_DLL_XFORM_DQ0_0

XFORM_DQx_MULT and XFORM_DQx_OFFS are a multiplier and offset, respectively, that can be used to modify the DLL
output. XFORM_DQx_* applies to all DQ/DM bits in each byte x. Final products may be read out in the DQ_TRIMMER_RD

Memory Controller
register. The default is multiply by 1, providing 1/4 cycle skew to DQS to keep DLL's 1/4 cycle delay. Integer + fractional
formats for multiplier & offset:
OFFS is 2's complement format, with bit [0] representing integer. The output of the XFORM is xform_out = (xform_in * MULT
+ OFFS*16)/ 16
 out >= 0x600, xform_out = 0x000

That means clamping works within 50% above the maximum (0x3ff) DLL output or 50% below the minimum (0) DLL output. To
make sure that is always satisfied, conservatively program OFFS so that 0x600 < OFFS < (0x5ff – ((MULT * 0x3ff) >> 4)).
Boot requirements:
Offset: 0x368 | Read/Write: R/W | Reset: 0x00000010 (0bxxxxxxxxx00000000000xxxxxxx10000)
22:12 0x0 XFORM_TXDQ0_OFFS: [PMC]
4:0 0x10 XFORM_TXDQ0_MULT: [PMC]

Offset: 0x36c | Read/Write: R/W | Reset: 0x00000010 (0bxxxxxxxxx00000000000xxxxxxx10000)


Memory Controller

16.7.2.128 EMC_DLI_RX_TRIM0_0

Offset: 0x378 | Read/Write: RO | Reset: 0x0XXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
24:15 X QUSE_CURRENT_TRIM_VAL_BYTE_0
9:0 X DQS_CURRENT_TRIM_VAL_BYTE_0

Offset: 0x37c | Read/Write: RO | Reset: 0x0XXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)



Memory Controller




16.7.2.136 EMC_DLI_TX_TRIM0_0

9:0 X TXDQ_CURRENT_TRIM_VAL_BYTE_0

Memory Controller

Offset: 0x39c | Read/Write: RO | Reset: 0x00000XXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)

Offset: 0x3a0 | Read/Write: RO | Reset: 0x00000XXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)

Offset: 0x3a4 | Read/Write: RO | Reset: 0x00000XXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
16.7.2.140 EMC_DLI_TRIM_TXDQS0_0
Set DLI TRIM

DLI_TRIM_TXDQSx
Controls trimmer used to skew data byte DQS/DQ output relative to MCK. 0-7 apply to rank 0, 8-15 apply to rank 1 (if dual-
rank enabled)
Boot requirements:
Offset: 0x3a8 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxx0000000)
6:0 0x0 EMC2PMACRO_CFG_TXDQS0_DLI: [PMC]

Memory Controller
Set DLI TRIM

Offset: 0x3ac | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxx0000000)
Set DLI TRIM

Offset: 0x3b0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxx0000000)
Set DLI TRIM

Set DLI TRIM

Set DLI TRIM

Offset: 0x3bc | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxx0000000)

Memory Controller
Set DLI TRIM

Offset: 0x3c0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxx0000000)
Set DLI TRIM

Offset: 0x3c4 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxx0000000)
16.7.2.148 EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0
Scheme to change controller timing parameters + SDRAM mode timing atomically.
1. Program the EMC controller timing registers (shadowed).

2. Pre-program the SDRAM mode registers.
a. Write 1 to the STALL_THEN_EXE_BEFORE_CLKCHANGE field, which will prevent further cfg execution
until a clock change request has been detected.
Note: After this step, no register read should happen on the EMC before the clock change (C)
happens, otherwise the system will hang. Disable the EMC interrupt before this step if the
interrupt handler reads EMC registers.
b. Write to whatever EMC registers you want to be execute after clock change request has been detected but
before the actual clock change happens. For example, if you want to disable DLL in DDR3 mode, you can,
i. Issue a write to SDRAM's MR1 register via EMC MRS register to disable DLL.
ii. Issue a Self-refresh entry via EMC SELF_REF register.
Note: If there is no need to execute any register access before clock change, simply skip step
(b); step (a) is still required.
c. Write 1 to STALL_THEN_EXE_AFTER_CLKCHANGE field which will prevent further config execution until
after the actual clock change has happened.
d. Write to whatever EMC registers you want to be executed after the clock change. Using the same example
as (b), you will,
i. Issue a Self-refresh exit via EMC SELF_REF register.
ii. Issue writes to SDRAM's MRx register(s) to change read/write latencies and/or enable DLL
iii. Issue burst refreshes via EMC REF register.
Note: If there is no need to execute any register access after clock change, simply skip step (d);
step (c) is still required.

Memory Controller
3. Program the CAR to change either clock source and/or clock divider.
Note: In both sequences above, DYN_SELF_REF must be disabled off before the first step, then
it can be restored after the last step.
The interval between two clock change sequences are recommended to be at least 20 µs
apart
Writes to this register will stall the register read/write path until a clock change request is detected. Once detected, whatever
register access follows this register write will be executed until a STALL_THEN_EXE_AFTER_CKLCHANGE is encountered.
At that point, EMC timing registers will be updated and the clock change request will be acknowledged.
Offset: 0x3c8 | Read/Write: RO | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
STALL_THEN_EXE_BEFORE_CLKCHANGE: Writing a one to this bit will stall subsequent

0 0x0
register accesses.
16.7.2.149 EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0
Writes to this register will stall the register read/write path until after EMC timing registers are updated and that clock change
has been completed. Once that happens, whatever register access follows this register write will be executed until
UNSTALL_RW_AFTER_CLKCHANGE is encountered. At that point, normal memory read/write will be allowed to resume.
Offset: 0x3cc | Read/Write: RO | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
STALL_THEN_EXE_AFTER_CLKCHANGE: Writing a one to this bit will stall subsequent

0 0x0
register accesses.
16.7.2.150 EMC_UNSTALL_RW_AFTER_CLKCHANGE_0
Writing to this register will unstall memory reads/writes after a clock change. Use in conjunction with
STALL_THEN_EXE_AFTER_CLKCHANGE.
Offset: 0x3d0 | Read/Write: RO | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0)
UNSTALL_RW_AFTER_CLKCHANGE: Writing a one to this bit will unstall memory reads/writes after a
0 0x0
clock change.
16.7.2.151 EMC_AUTO_CAL_CLK_STATUS_0

Offset: 0x3d4 | Read/Write: RO | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
28:24 X AUTO_CAL_CLK_PULLDOWN_ADJ: Pull-down code sent to pads for MCLK pad.
20:16 X AUTO_CAL_CLK_PULLUP_ADJ: Pull-up code sent to pads for MCLK pad.
12:8 X AUTO_CAL_CLK_PULLDOWN: Pull-down code generated by auto-calibration for MCLK pad.
4:0 X AUTO_CAL_CLK_PULLUP: Pull-up code generated by auto-calibration for MCLK pad.

Memory Controller
16.7.2.152 EMC_SEL_DPD_CTRL_0
Configures Functional SEL_DPD Modes

Offset: 0x3d8 | Read/Write: R/W | Reset: 0x00040000 (0bxxxxxxxxxxxxx100xxxxxxx0xx0000xx)
18:16 0x4 SEL_DPD_DLY: [PMC] number of cycles to wait before asserting SEL_DPD
DATA_SEL_DPD_EN: [PMC] allow SEL_DPD assertion for data pads

1 = ENABLED
ODT_SEL_DPD_EN: [PMC] tie SEL_DPD for ODT pads to ENABLE_ODT_DURING_WRITE

1 = ENABLED
RESET_SEL_DPD_EN: [PMC] assert SEL_DPD for reset pad

1 = ENABLED
CA_SEL_DPD_EN: [PMC] allow SEL_DPD assertion for discrete command/address pads

1 = ENABLED
CLK_SEL_DPD_EN: [PMC] allow SEL_DPD assertion for discrete clock pad

1 = ENABLED
16.7.2.153 EMC_PRE_REFRESH_REQ_CNT_0
Offset: 0x3dc | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxx0000000000000000)
PRE_REF_REQ_CNT: [PMC] When the refresh counter reach this pre-refresh request count
just before a burst refresh will be issued when it reach the {REFRESH,REFRESH_LO}, a pre-
15:0 0x0
refresh request will be asserted to MC to close the banks/pages and flush its pipeline. A 0
value will disable this feature.
16.7.2.154 EMC_DYN_SELF_REF_CONTROL_0
Threshold for Dynamic Self-Refresh Entry

This register controls how dynamic self-refresh entry/exit is handled.
If ODT is enabled, the DSR_PER_DEVICE field must be set to DISABLED.
It is recommended to change the values of ODT_WRITE and DSR_PER_DEVICE with a clock change
To do it outside of a clock change sequence, one has to be aware that DSR enable/disable takes time to take effect. This is
the sequence for disabling DSR_PER_DEVICE and enabling ODT outside of clock change:
1. DYN_SELF_REF <= DISABLED (DSR exit)
2. TIMING_UPDATE <= 1 (latch in the shadow value)
3. Read back and discard any EMC register such as INTSTATUS (ensure 1 and 2 have gone through)
4. Wait 2 µs for the last possible self-refresh entry
5. Poll for SDRAM_IN_SELF_REFRESH == 0 (ensure that self-refresh exits)

Memory Controller
6. ODT_WRITE <= new value to turn on ODT
DSR_PER_DEVICE <= DISABLED (turn off per-device DSR)
DYN_SELF_REF <= ENABLED (re-enable DSR)
7. TIMING_UPDATE <= 1 (latch in the shadow values)
Offset: 0x3e0 | Read/Write: R/W | Reset: 0x00000000 (0b0xxxxxxxxxxxxxxx0000000000000000)
DSR_PER_DEVICE: [PMC] controls whether dynamic self-refresh is done on a per-device

basis.
31 DISABLED
0 = DISABLED
1 = ENABLED
DSR_THRESHOLD: [PMC] number of idle cycles to wait before allowing dynamic self-refresh
15:0 0x0
entry
16.7.2.155 EMC_TXSRDLL_0

Boot requirements:
Note: If operating in non-DLL mode, this register needs to be updated with the non-DLL timing requirement.
Offset: 0x3e4 | Read/Write: R/W | Reset: 0x000007ff (0bxxxxxxxxxxxxxxxxxxxx011111111111)
TXSRDLL: [PMC] Cycles between self-refresh exit and first DRAM command requiring a
locked DLL. For DDR3 only: READ (and RAP) and synchronous ODT commands.
11:0 0x7ff DDR3: 512.
LPDDR3: TXSR (not used).
Largest allowed value is 0xffe
16.7.2.156 EMC_CCFIFO_ADDR_0
CCFIFO_ADDR: This register contains the address offset of the EMC register that is intended to be executed during the clock
change sequence.
Note: Before triggering a clock change sequence from the CAR, you must configure the pre-
/post- clock change sequence by writing, multiple times, to the
CCFIFO_DATA/CCFIFO_ADDR register pair. After the CCFIFO_ADDR register is written,
Hardware will write the register offset and corresponding data into the 32-deep clock
change FIFO (CCFIFO).
Offset: 0x3e8 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxx0000000000000000)
15:0 0x0 CCFIFO_ADDR: clock change FIFO address register.

Memory Controller
16.7.2.157 EMC_CCFIFO_DATA_0
CCFIFO_DATA: This register contains the 32-bit data of the EMC register that is intended to be written to or pointed at by
CCFIFO_ADDR.
Offset: 0x3ec | Read/Write: R/W | Reset: 0x00000000 (0b00000000000000000000000000000000)
31:0 0x0 CCFIFO_DATA: clock change FIFO data register.
16.7.2.158 EMC_CCFIFO_STATUS_0
Offset: 0x3f0 | Read/Write: RO | Reset: 0x000000XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
5:0 X CCFIFO_COUNT
16.7.2.159 EMC_CDB_CNTL_1_0
CDB Control Register

The following table lists the mapping for the SEL_PI_TAP bits in CDB Control Register 1.
Table 58: SEL_PI_TAP Mapping
CDB SEL_PI_TAP# EMC Signal Comment
CDB SEL_PI_TAP15 EMC2PMACRO_SEL_PI_TAP15 data brick 7
CDB SEL_PI_TAP11 EMC2PMACRO_SEL_PI_TAP11 CLKBUF 5 controls

channel 1 sdr pins:
cke_b0, cke_b1,
odt_b0, odt_b1,
cs_b0_, cs_b1_

channel 1 ddr/2T pins:
ba0, ba1, ba2, a10,
a12, a13, a15, a_b3,
a_b4

a_b5,a11,a14
CDB SEL_PI_TAP8 EMC2PMACRO_SEL_PI_TAP8 MCLK_B
CDB SEL_PI_TAP7 EMC2PMACRO_SEL_PI_TAP7 MCLK

channel 0 sdr pins:
cs1_ cs0_, odt1, odt0,
cke0, cke1

ras_,cas_,we_,rst,a2,a
3,a4,a6,a8

Memory Controller
CDB SEL_PI_TAP# EMC Signal Comment

a0,a1,a5,a7,a9
CDB SEL_PI_TAP3 EMC2PMACRO_SEL_PI_TAP3 data byte 3
Offset: 0x3f4 | Read/Write: R/W | Reset: 0x00000000 (0bxx000000000000000000000000000000)
29:27 0x0 EMC2PMACRO_SEL_PI_TAP9: [PMC]
16.7.2.160 EMC_CDB_CNTL_2_0
Offset: 0x3f8 | Read/Write: R/W | Reset: 0x00000000 (0b00000000000000000000000000000000)
31 0x0 EMC2PMACRO_CLKNIGATE_TAP15: [PMC]

Memory Controller
15 0x0 EMC2PMACRO_CLKPIGATE_TAP15: [PMC]
16.7.2.161 EMC_XM2CLKPADCTRL2_0
XM2CLK Pad Control Register

Boot requirements:
Offset: 0x3fc | Read/Write: R/W | Reset: 0x00000000 (0b0xx000000xx00000xx000000xx000000)
31 0x0 EMC2PMACRO_CFG_FLIP_CKB_SENSE: [PMC] Flip the m2clk_b pad sense
EMC2PMACRO_CFG_PI_CLKB_TRIM: [PMC] pi_clk_trim to control the 32-tap trimmer on the ckb pad
28:24 0x0
macro (pi clock domain)
23 0x0 EMC2PMACRO_CFG_FLIP_CK_SENSE: [PMC] Flip the m2clk pad sense
EMC2PMACRO_CFG_PI_CLK_TRIM: [PMC] pi_clk_trim to control the 32-tap trimmer on the ck pad-

20:16 0x0
macro (pi clk domain)
13:8 0x0 EMC2TMC_CFG_XM2CLKB_DLY_TRM_P: [PMC]
5:0 0x0 EMC2TMC_CFG_XM2CLK_DLY_TRM_P: [PMC]

Memory Controller
16.7.2.162 EMC_SWIZZLE_RANK0_BYTE_CFG_0
For byte swizzling, each SWZ_RANK*_BYTE*_SEL field indicates which SDRAM byte is mapped/connected to the
corresponding byte of the chip.
The SWZ_RANK*_BYTE*_BIT*_SEL fields indicate which SDRAM data bit (0-7) within each byte is mapped/connected to the
corresponding bit of the chip.
The Tegra K1 device has 8 bytes per partition without a per rank differentiation for swizzling. The RANK1 register set controls
swizzling for the upper 4 byte of data.
Offset: 0x400 | Read/Write: R/W | Reset: 0x00003210 (0bxxxxxxxxxxxxxxxxxx11xx10xx01xx00)
13:12 0x3 SWZ_RANK0_BYTE3_SEL: [PMC]
16.7.2.163 EMC_SWIZZLE_RANK0_BYTE0_0
Offset: 0x404 | Read/Write: R/W | Reset: 0x76543210 (0bx111x110x101x100x011x010x001x000)
30:28 0x7 SWZ_RANK0_BYTE0_BIT7_SEL: (encoded)
22:20 0x5 SWZ_RANK0_BYTE0_BIT5_SEL: [PMC]

Memory Controller
Offset: 0x40c | Read/Write: R/W | Reset: 0x76543210 (0bx111x110x101x100x011x010x001x000)
16.7.2.167 EMC_SWIZZLE_RANK1_BYTE_CFG_0
Offset: 0x414 | Read/Write: R/W | Reset: 0x00003210 (0bxxxxxxxxxxxxxxxxxx11xx10xx01xx00)

Memory Controller
Offset: 0x41c | Read/Write: R/W | Reset: 0x76543210 (0bx111x110x101x100x011x010x001x000)



Memory Controller
16.7.2.172 EMC_CA_TRAINING_START_0
Procedure for LPDDR3 CA Training

(1a) Configure data swizzling (if needed) through the DATA_SWIZZLE_RANK[0,1]_[0:7] registers.
(1b) Enable EMC2PMACRO_CFG_BYPASS_ADDRPIPE if needed. There's no need to enable

EMC2PMACRO_CFG_BYPASS_DATAPIPE* for CA training purposes.
(1c) Follow the procedure on optimal trim setting into the CA bus clock trimmer below.
(2) Configure the CA training engine through the CA_TRAINING_[TIMING_CNTL1,TIMING_CNTL2, CA_LEAD_IN, CA,
and CA_LEAD_OUT] registers.
(3) Software configures the CA training engine to use MR41 mode (through the CA_TRAINING_CFG register).
(4) Software starts the CA training engine (in the CA_TRAINING_START register) and waits for the CA training to finish
(CA_TRAINING_BUSY).
(5) Software saves the result from the CA_TRAINING_RESULT* registers.
(6) Software repeats steps 3-5 but configures for MR48 mode.
(7) Software combines the results from MR41/MR48 modes to come up with a single trim setting and programs the
EMC2PMACRO_CFG_XM2CMD_DIGTRIM field.
(8) Software issues MR42 to rank0.
(9) If desired, software can repeat steps 3-8 for rank1.
(10) Software combines the results from MR41/MR48 modes (if desired, results for rank1 as well) to come up with a
single trim setting and programs the EMC2PMACRO_CFG_XM2CMD_DIGTRIM field
(A) Put CLKBUF0/CLKBUF2 into trimmer mode by setting EMC2TMC_CFG_XM2CMD_CLKBUF[0,2]_CONFIG = 001.
(B) Put XFORM_ADDR[0,2]_MULT field to 5'b0.
(C) Program bits [7:2] in the XFORM_ADDR[0,2]_OFFS field (11 bits) with the optimal trim result. The other
XFORM_ADDR[0,2]_OFFS bits should remain at 0.
(D) Write a 1 into the TIMING_UPDATE field to load the above fields from shadow to active.
Below is what should be programmed into the CA_TRAINING_TIMING_CONTROL* registers.
CACKEL = tCACKEL + 15 clks
CAENT = tCAENT + 3 clks
CACD = tCACD + 5 clks
CACKEH = tCACKEH – 1 clk
CAEXT = tCAEXT – 1 clk
CA_DQ_RDV = CACD
Offset: 0x428 | Read/Write: R/W | Reset: 0x00000000 (0b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31 0x0 CA_TRAIN_START: 1 = start training.

Memory Controller
16.7.2.173 EMC_CA_TRAINING_BUSY_0
Offset: 0x42c | Read/Write: RO | Reset: 0x0000000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
0 X CA_TRAIN_BUSY: 1 = training is in progress.
16.7.2.174 EMC_CA_TRAINING_CFG_0
Offset: 0x430 | Read/Write: R/W | Reset: 0x0000001f (0bx000xx0000000000x0000000x0011111)

30 RANK0 CA_RANK: Indicates which rank to do training on.
0 = RANK0
1 = RANK1
29 0x0 CA_DRAM_X32: 1 = Using x32 DRAM, 0 = using x16 DRAM.
28 MR41 CA_MR48:
0 = training with MR41 mode
1 = training with MR48 mode.
0 = MR41
1 = MR48
25:16 0x0 CA_MRW_CA: MR41 = 0x290, MR48 = 0x300.
14:8 0x0 CA_START_TRIM_VAL: Indicates the starting delay trim value to use for CA training.
6:0 0x1f CA_END_TRIM_VAL: Indicates the ending delay trim value to use for CA training.
16.7.2.175 EMC_CA_TRAINING_TIMING_CNTL1_0
Offset: 0x434 | Read/Write: R/W | Reset: 0x1f7df7df (0bxxx11111x11111x11111x11111x11111)

28:24 0x1f CAEXT: tCAEXT parameter.
22:18 0x1f CACKEH: tCACKEH parameter.
16:12 0x1f CACD: tCACD parameter.
10:6 0x1f CAENT: tCAENT parameter.
4:0 0x1f CACKEL: tCACKEL parameter.
16.7.2.176 EMC_CA_TRAINING_TIMING_CNTL2_0
5:0 0x1f CA_DQ_RDV: number of clocks to delay after CS is asserted before comparing CA/DQ. Minimum is 5.
40 = MAX
16.7.2.177 EMC_CA_TRAINING_CA_LEAD_IN_0
Offset: 0x43c | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxx0000000000xxxxxx0000000000)
25:16 0x0 CA_LEAD_IN_RISE: CA rise value for the clock before CS is active.
9:0 0x0 CA_LEAD_IN_FALL: CA fall value for the clock before CS is active.

Memory Controller
16.7.2.178 EMC_CA_TRAINING_CA_0
Offset: 0x440 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxx0000000000xxxxxx0000000000)
25:16 0x0 CA_RISE: CA rise value for the clock CS is active.
9:0 0x0 CA_FALL: CA fall value for the clock CS is active.
16.7.2.179 EMC_CA_TRAINING_CA_LEAD_OUT_0
Offset: 0x444 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxx0000000000xxxxxx0000000000)
25:16 0x0 CA_LEAD_OUT_RISE: CA rise value for the clock after CS is active.
9:0 0x0 CA_LEAD_OUT_FALL: CA fall value for the clock after CS is active.
16.7.2.180 EMC_CA_TRAINING_RESULT1_0
31:0 X CA_TRIM_RESULT_31_0: Indicates which trim setting(s) pass the CA-to-DQ comparison.
16.7.2.184 EMC_AUTO_CAL_CONFIG2_0

Boot requirements:

Memory Controller
Offset: 0x458 | Read/Write: R/W | Reset: 0x00000000 (0bxxx00000xxx00000xxx00000xxx00000)

28:24 0x0 AUTO_CAL_CNTL_PD_OFFSET: [PMC] 2's complement offset for CS/ODT/CKE pull-down value
20:16 0x0 AUTO_CAL_CNTL_PU_OFFSET: [PMC] 2's complement offset for CS/ODT/CKE pull-up value
12:8 0x0 AUTO_CAL_CMD_PD_OFFSET: [PMC] 2's complement offset for ADDR/RAS/CAS/WE pull-down
value
4:0 0x0 AUTO_CAL_CMD_PU_OFFSET: [PMC] 2's complement offset for ADDR/RAS/CAS/WE pull-up value
16.7.2.185 EMC_AUTO_CAL_CONFIG3_0

Boot requirements:
Offset: 0x45c | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxx00000xxx00000)
12:8 0x0 AUTO_CAL_CLK_PD_OFFSET: [PMC] 2's complement offset for CLK pull-down value
4:0 0x0 AUTO_CAL_CLK_PU_OFFSET: [PMC] 2's complement offset for CLK pull-up value
16.7.2.186 EMC_AUTO_CAL_STATUS2_0


28:24 X AUTO_CAL_CNTL_PULLDOWN_ADJ: Pullup/down code sent to pads
20:16 X AUTO_CAL_CNTL_PULLUP_ADJ: Pullup/down code sent to pads
12:8 X AUTO_CAL_CMD_PULLDOWN_ADJ: Pullup/down code sent to pads.
4:0 X AUTO_CAL_CMD_PULLUP_ADJ: Pullup/down code sent to pads
16.7.2.187 EMC_IBDLY_0

4:0 0x1 IBDLY: [PMC] tells the chip when to change IBDLY for DQ/DQS.
16.7.2.188 EMC_DLL_XFORM_ADDR0_0
Configure Digital DLL for CMD/ADDR Group 0

XFORM_ADDRx_MULT and XFORM_ADDRx_OFFS are a multiplier and offset, respectively, that can be used to modify the
DLL output. Final products may be read out in the ADDR_TRIMMER_RD register. The default is multiply by 1, to keep the
DLL's 1/4 cycle delay. Integer + fractional formats for multiplier and offset:
Memory Controller
OFFS is 2's complement format, with bit [0] representing integer
The output of the XFORM is xform_out = (xform_in * MULT + OFFS*16)/16
The largest allowed MULT = 0x17
In the case of overflow, the output is clamped according to these rules:
out >= 0x600, xform_out = 0x000
0x600 > out >= 0x400, xform_out = 0x3ff
That means clamping works within 50% above the maximum (0x3ff) DLL output or 50% below the minimum (0) DLL output.
To make sure that is always satisfied, conservatively program OFFS so that 0x600 < OFFS < (0x5ff - ((MULT * 0x3ff) >> 4))
The DLL output is effectively overridden by setting XFORM_*_MULT to 0 and programming XFORM_*_OFFS[8:1] to override
the value
Boot requirements:
The ADDR(0|1|2)_CURRENT_TRIM_VAL registers provide a way to observe the values being used by the trimmers.
CLKBUF assignments for XFORM_ADDR as well as DLI_DDR_TRIM are:
 XFORM_ADDR5 controls channel 1 sdr pins: cke_b0, cke_b1, odt_b0, odt_b1, cs_b0_, cs_b1_
 XFORM_ADDR4 controls channel 1 ddr/2T pins: ba0, ba1, ba2, a10, a12, a13, a15, a_b3, a_b4
 XFORM_ADDR3 controls channel 1 ddr/2T pins: a_b5, a11, a14
 XFORM_ADDR2 controls channel 0 sdr pins: cs1_ cs0_, odt1, odt0, cke0, cke1
 XFORM_ADDR1 controls channel 0 ddr/2T pins: ras_,cas_,we_,rst,a2,a3, a4, a6, a8
 XFORM_ADDR0 controls channel 0 ddr/2T pins: a0, a1, a5, a7, a9
Offset: 0x46c | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxx00000000000xxxxxxx00000)
22:12 0x0 XFORM_ADDR0_OFFS: [PMC]
4:0 0x0 XFORM_ADDR0_MULT: [PMC]


Memory Controller

16.7.2.191 EMC_DLI_ADDR_TRIM_0

29:20 X ADDR2_CURRENT_TRIM_VAL
16.7.2.192 EMC_DSR_VTTGEN_DRV_0
Offset: 0x47c | Read/Write: R/W | Reset: 0x0707003f (0bxxxxx111xxxxx111xxxxxxxxxx111111)
26:24 0x7 DSR_VTTGEN_DRVUP: [PMC] Indicates the VTTGEN VCLAMP regulator impedance to use during
DSR.
18:16 0x7 DSR_VTTGEN_DRVDN: [PMC] Indicates the VTTGEN VAUXP regulator impedance to use during
DSR.
5:0 0x3f DSR_VTTGEN_E_NO_VTTGEN: [PMC] Disables optional VTTGEN pads (1 bit per pad) [0]--ADDR0,
[1]--ADDR1, [2]--ADDR2, [3]--DATA1, [4]--DATA2, [5]--DATA3
16.7.2.193 EMC_TXDSRVTTGEN_0

11:0 0x0 TXDSRVTTGEN: [PMC] Cycles to wait from DSR exit (VTTGEN drive normal), to when a DRAM
transaction is allow to start.

Memory Controller
XM2CMD Pad Control Register 4

Controls related to NI-PI handoff in pad macros.
Boot requirements:
Offset: 0x484 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxx0x0x0x0x0x0)

10 0x0 EMC2PMACRO_CFG_2T_PM_PHASE_SHIFT: [PMC] when set to 1, enables 1/2 clocks of delay on OB
2T signals
8 0x0 EMC2PMACRO_CFG_2T_PM2PAD_FLOP_BYPASS: [PMC] when set to 1, enables flop between NI-PI
handoff structure and pad for OB 2T
6 0x0 EMC2PMACRO_CFG_1T_PM_PHASE_SHIFT: [PMC] when set to 1, enables 1/2 clocks of delay on OB
1T signals
4 0x0 EMC2PMACRO_CFG_1T_PM2PAD_FLOP_BYPASS: [PMC] when set to 1, enables flop between NI-PI
handoff structure and pad for OB 1T
2 0x0 EMC2PMACRO_CFG_DAT_PM_PHASE_SHIFT: [PMC] when set to 1, enables 1/2 clocks of delay on OB
data signals
0 0x0 EMC2PMACRO_CFG_DAT_PM2PAD_FLOP_BYPASS: [PMC] when set to 1, enables flop between
DQ/DQS NI-PI handoff structure and pad
Boot requirements:
Offset: 0x488 | Read/Write: R/W | Reset: 0x00111111 (0bxxxxxxxxx001x001x001x001x001x001)

22:20 0x1 EMC2TMC_CFG_XM2CMD_CLKBUF5_CONFIG: [PMC] CONFIG bit setting of CLKBUF5 pad (000 ==
DLCELL mode, 001 == TRIM/PDL mode)
16.7.2.196 EMC_CFG_3_0
EMC Configuration
Boot requirements:

Memory Controller
 This register (except for fields DRAMC_PRE_B4_ACT, MRR_BYTESEL_X16, MRR_BYTESEL) should be saved in
the scratch registers and restored by the Boot ROM during warm boot.
 If the OS needs the MRR_BYTESEL* fields set to non-default values to perform a mode-register read, it needs to
correctly program these values before performing the MRR.
Offset: 0x49c | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxx000x000)

MRR_BYTESEL_X16: If using 2 x16 DRAM on a single CS to form 32-bit wide data, indicates to which
6:4 0x0
byte lane the second DRAM's byte 0 is connected.
MRR_BYTESEL: Indicates which AP byte lane is connected to DRAM byte 0 (over which MRR data is
2:0 0x0
returned).

Offset: 0x4a0 | Read/Write: R/W | Reset: 0x007ff010 (0bxxxxxxxxx11111111111xxxxxxx10000)






Memory Controller
Offset: 0x4ac | Read/Write: R/W | Reset: 0x007ff010 (0bxxxxxxxxx11111111111xxxxxxx10000)

Offset: 0x4b0 | Read/Write: R/W | Reset: 0x007ff010 (0bxxxxxxxxx11111111111xxxxxxx10000)



Offset: 0x4bc | Read/Write: R/W | Reset: 0x007ff010 (0bxxxxxxxxx11111111111xxxxxxx10000)

Memory Controller

Offset: 0x4c0 | Read/Write: R/W | Reset: 0x0000000c (0bxxxxxxxxx000000000000000xxx01100)
22:8 0x0 XFORM_QUSE8_OFFS:[PMC]
4:0 0xc XFORM_QUSE8_MULT:[PMC]



Offset: 0x4cc | Read/Write: R/W | Reset: 0x0000000c (0bxxxxxxxxx000000000000000xxx01100)

Offset: 0x4d0 | Read/Write: R/W | Reset: 0x0000000c (0bxxxxxxxxx000000000000000xxx01100)

Memory Controller



Offset: 0x4dc | Read/Write: R/W | Reset: 0x0000000c (0bxxxxxxxxx000000000000000xxx01100)

Offset: 0x4e0 | Read/Write: R/W | Reset: 0x00000010 (0bxxxxxxxxx000000000000000xxx10000)
22:8 0x0 XFORM_TXDQ4_OFFS:[PMC]
4:0 0x10 XFORM_TXDQ4_MULT:[PMC]

Memory Controller



Offset: 0x4ec | Read/Write: R/W | Reset: 0x00000010 (0bxxxxxxxxx000000000000000xxx10000)

Offset: 0x4f0 | Read/Write: RO | Reset: 0x0XXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)


Memory Controller


Offset: 0x4fc | Read/Write: RO | Reset: 0x0XXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)




Memory Controller





Offset: 0x51c | Read/Write: RO | Reset: 0x00000XXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)

Memory Controller
Set DLI TRIM

6:0 0x0 EMC2PMACRO_CFG_TXDQS8_DLI:[PMC]
Set DLI TRIM

Set DLI TRIM

Set DLI TRIM

Offset: 0x52c | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxx0000000)
Set DLI TRIM


Memory Controller
Set DLI TRIM

Set DLI TRIM

Set DLI TRIM

Offset: 0x53c | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxx0000000)
16.7.2.237 EMC_CDB_CNTL_3_0
Offset: 0x540 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxx000000000000000000)

Offset: 0x544 | Read/Write: R/W | Reset: 0x00208208 (0bxxxxxxxxx01000x01000x01000x01000)

Memory Controller

Offset: 0x548 | Read/Write: R/W | Reset: 0x20820800 (0bx01000x01000x01000x01000xxxxxxxx)

16.7.2.240 EMC_XM2DQPADCTRL3_0
Offset: 0x54c | Read/Write: R/W | Reset: 0x00000000 (0bx000x000x000x000xxxxxxxxxxxxxxxx)

30:28 0x0 EMC2TMC_CFG_XM2DQ7_DLYIN_TRM: [PMC] delay trim for byte 3
Configure Digital DLL for CMD/ADDR group 3



Memory Controller

16.7.2.244 EMC_DLI_ADDR_TRIM2_0

16.7.2.245 EMC_CFG_PIPE_0
Datapipe Configuration Register

Offset: 0x560 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxx0000xx000000xx00)
EMC2PMACRO_CFG_BYPASS_OB_DATAPIPE4: [PMC] 1 = bypass data pipeline stage2 (closer to I/O)

15 0x0
between E
14 0x0
between E
13 0x0
between E
EMC2PMACRO_CFG_BYPASS_OB_DATAPIPE1: [PMC] 1 = bypass data pipeline stage1 (closer to core)
12 0x0
between EMC and data pad-macro.
EMC2PMACRO_CFG_BYPASS_OB_ADDRPIPE2: [PMC] 1 = bypass address pipeline stage between
9 0x0
EMC and address pad-macro.
EMC2PMACRO_CFG_BYPASS_OB_ADDRPIPE1: [PMC] 1 = bypass address pipeline stage between
8 0x0
EMC2PMACRO_CFG_BYPASS_IB_DATAPIPE4: [PMC] 1 = bypass data pipeline stage2 (closer to I/O)
7 0x0
between E
6 0x0
between E
5 0x0
between E
EMC2PMACRO_CFG_BYPASS_IB_DATAPIPE1: [PMC] 1 = bypass data pipeline stage1 (closer to core)
4 0x0
between EMC and data pad-macro.
EMC2PMACRO_CFG_BYPASS_IB_ADDRPIPE2: [PMC] 1 = bypass address pipeline stage between
1 0x0

Memory Controller
EMC2PMACRO_CFG_BYPASS_IB_ADDRPIPE1: [PMC] 1 = bypass address pipeline stage between

0 0x0
16.7.2.246 EMC_QPOP_0

Boot requirements:
QPOP: [PMC] time from read command to pop data from the pad macro FIFO.
5:0 0x6
45 = MAX
16.7.2.247 EMC_QUSE_WIDTH_0

3:0 0x3 QUSE_DURATION: [PMC] Additional QUSE duration apart from default BL/2
16.7.2.248 EMC_PUTERM_WIDTH_0

Offset: 0x56c | Read/Write: R/W | Reset: 0x00000005 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx0101)
3:0 0x5 PUTERM_DURATION: [PMC] Additional PUTERM duration apart from default BL/2
16.7.2.249 EMC_BGBIAS_CTL0_0
BGBIAS Pad controls

3 0x0 BIAS0_DSC_E_PWRD_IBIAS_RX: [PMC] Bias current going out to brick receiver

BIAS0_DSC_E_PWRD_IBIAS_VTTGEN: [PMC] Active High. Disables biasing current going out to
2 0x0
VTTGEN cells
1 0x0 BIAS0_DSC_E_PWRD: [PMC] Active High. Disables all DC current paths within entire cell.

Memory Controller
0 0x0 BIAS0_DSC_BG_SEL_N: [PMC] Active low; 0= select BandGap reference current;
16.7.2.250 EMC_PUTERM_ADJ_0
PUTERM controls
Offset: 0x574 | Read/Write: R/W | Reset: 0x00000081 (0bxxxxxxxxxxxxxxxxxxxxxxxx1xxxxx01)
CFG_PUTERM_EXTEND_HALF_CLK: [PMC] extend the PUTERM window by half a clock

7 ENABLED 0 = DISABLED
1 = ENABLED
1:0 0x1 CFG_PUTERM_LATE: [PMC] Half-cycle increments
16.7.2.251 EMC_CA_TRAINING_SP1_RESULT1_0
Offset: 0x5f0 | Read/Write: RO | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X CA_TRIM_RESULT_SP1_31_0: Indicates which trim setting(s) pass the CA-to-DQ comparison.
Offset: 0x5fc | Read/Write: RO | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)

Memory Controller

17.0 AHB
17.1 AHB Bus

The AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced High-performance Bus (AHB) architecture as
published by ARM.
®
AHB is a 32-bit multi-master bus. Despite what its name implies, it is a second tier bus in the Tegra K1 processor, slower and
less flexible than the AXI bus used by the CPU, or the memory client interface used by the high-speed devices.
The Master clients on the AHB are:
 The AHB memory controller slave, which is the interface between the AHB bus and the Memory Controller
 The AVP crossbar, both as a master and as a slave. This is the path to IRAM from AHB devices, and also the AVP
and CPU path to AHB devices. Neither the CPU complex nor the AVP can access DRAM through this path.
 The APB DMA controller, used to provide data transfer between APB devices and memory
 The USB-OTG controller
 MIPI HSI controller
 ARC controller
 The security engine (SE), both as a master and as a slave
 BSEA and BSEV bitstream engines
 The CoreSight™ debug controller
 The deprecated AHB DMA controller master
 SNOR AHB master
 DDS
 USB2 and USB3 controllers
The Slave clients on the AHB are:
 XBAR
 DRAM
 USB-OTG, USB2, USB3
 SNOR
 TZRAM
AHB in the Tegra K1 processor supports secure access to memory, using the same secure bit mechanism used by the CPU
TrustZone security mechanism. This is supported by the SE, which can make secure accesses to memory.
17.2 AHB Bus Arbiter

The AHB Arbiter controls AHB bus master arbitration. This effectively forms a second level of arbitration for access to the
memory controller through the AHB Slave Memory device, although AHB masters in some circumstances can use other AHB
slaves, in particular they can access IRAM.
The controls presented here are largely for diagnostic purposes only. For suspect AHB performance problems, try disabling
the other masters for the device with performance issues. In normal operation bus parking is usually enabled, and all the
masters are enabled.
Also see the AHB slave interface registers, where the AHB pre-fetch logic can be configured to enhance performance for
devices doing sequential read access from DRAM.
AHB
Each AHB master is assigned to either the high or low priority bin.
17.2.1 Arbitration Scheme

In every AHB Arbitration cycle, it is first decided whether a request from the high or low priority bin will be served. If there are
only requests active for one of the bins, then that bin is served. When there are active requests from both bins, then the value
from the AHB_PRIORITY_WEIGHT field is considered. There is a counter that is loaded with the AHB_PRIORITY_WEIGHT
whenever the current count is 0 and someone wins an AHB arbitration. This counter is decremented anytime the count is
nonzero and the winner of AHB arbitration was from the high-priority bin. Whenever this counter is nonzero, then a high-
priority bin request will win over any low-priority bin request. In a system where both high- and low- priority bin requests are
constantly active, the AHB_PRIORITY_WEIGHT says how many high-priority requests will be served for every one low-priority
request.
Within each bin, the arbitration algorithm is round robin. For example, after AHB Master 2 wins an arbitration, then Master 3
has precedence for winning the next (followed by Master 4, etc. while Master 2 is last). AHB Master ID’s can be seen in the
enumeration of AHB_MEM_PREFETCH_CFG* registers’ “AHB_MST_ID” field.
17.2.2 AHB Arbiter Registers

In prior generation Tegra processors, this location used to hold a configuration register for COP_CACHE, but COP_CACHE
has been replaced with AVP_CACHE, which has a region in a different section. For software compatibility, this location is
reserved.
17.2.2.1 AHB_ARBITRATION_DISABLE_0
The AHB arbitration control register allows user to tweak arbitration behavior of the AHB arbiter.
 Enable bus parking. This keeps the last serviced AHB master on the bus granted so that it can start another
transaction faster. If bus parking is disabled, no AHB master will be able to start a new transaction until the arbitration
is done and the master is granted the bus.
 Allows the user to specifically disable an AHB master from arbitrating on the AHB bus.
AHB Arbitration Controller

Offset: 0x4 │ Read/Write: R/W │ Reset: 0x00000000 (0b00xxxxxxxx0xx000000x0xxx00000000)
31 0x0 DIS_BUS_PARK: 1 = Disable bus parking.

0 = ENABLE
1 = DISABLE
30 0x0 DIS_PENULTIMATE_ARB:
1 = Disable arbitration on the second to last transfer.
21 0x0 MIPIHSI: 1 = Disable MIPIHSI from arbitration.

0 = ENABLE
1 = DISABLE
18 0x0 USB2: 1 = Disable USB2 from arbitration.

0 = ENABLE
1 = DISABLE

AHB
17 0x0 USB3: 1 = Disable USB3 from arbitration.

0 = ENABLE
1 = DISABLE
16 0x0 BSEA: 1 = Disable BSEA from arbitration.

0 = ENABLE
1 = DISABLE
15 0x0 DDS: 1 = Disable DDS from arbitration.

0 = ENABLE
1 = DISABLE
14 0x0 SE: 1 = Disable SE from arbitration.

0 = ENABLE
1 = DISABLE
13 0x0 BSEV: 1 = Disable BSEV from arbitration.

0 = ENABLE
1 = DISABLE
11 0x0 SNOR: 1 = Disable SNOR from arbitration.

0 = ENABLE
1 = DISABLE
7 0x0 APBDMA: 1 = Disable APB-DMA from arbitration.

0 = ENABLE
1 = DISABLE
6 0x0 USB: 1 = Disable USB from arbitration.

0 = ENABLE
1 = DISABLE
5 0x0 AHBDMA: 1 = Disable AHB-DMA from arbitration.

0 = ENABLE
1 = DISABLE
4 0x0 ARC: 1 = Disable ARC from arbitration.

0 = ENABLE
1 = DISABLE
3 0x0 CSITE: 1 = Disable CoreSight from arbitration.

0 = ENABLE
1 = DISABLE
2 0x0 VCP: 1 = Disable VCP from arbitration.

0 = ENABLE
1 = DISABLE
1 0x0 COP: 1 = Disable COP from arbitration.

0 = ENABLE
1 = DISABLE
0 0x0 CPU: 1 = Disable CPU from arbitration.

0 = ENABLE
1 = DISABLE
17.2.2.2 AHB_ARBITRATION_PRIORITY_CTRL_0
The AHB arbiter implements a 2-level priority scheme. In the first level, arbitration is determined between the high and low
priority group according to the priority weight; the higher the weight, the higher the winning rate of the high priority group.

AHB
In the second level, within each of the high/low priority group, arbitration is determined in a round-robin fashion.
AHB Arbitration Priority Control Register

Offset: 0x8 │ Read/Write: R/W │ Reset: 0x00000000 (0b00000000000000000000000000000000) | Default: 0xe0000000
SW
Default
AHB_PRIORITY_WEIGHT: AHB priority weight count. This 3-bit field is used to control
31:29 0x0 0x7 the amount of attention (weight) given to the high priority group before switching to the
low priority group.
28:0 0x0 NONE AHB_PRIORITY_SELECT: 0 = low priority group.
17.2.2.3 AHB_ARBITRATION_USR_PROTECT_0
USR Protection Register

Offset: 0xc │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxx0000x0000)
CACHE: Abort on USR mode access to Cache memory space

8 0x0 0 = ABT_DIS
1 = ABT_EN
ROM: Abort on USR mode access to internal ROM memory space

7 0x0 0 = ABT_DIS
1 = ABT_EN
APB: Abort on USR mode access to APB memory space

6 0x0 0 = ABT_DIS
1 = ABT_EN
AHB: Abort on USR mode access to AHB memory space

5 0x0 0 = ABT_DIS
1 = ABT_EN
IRAMD: Abort on USR mode access to iRAMd memory space

3 0x0 0 = ABT_DIS
1 = ABT_EN
IRAMC: Abort on USR mode access to iRAMc memory space

2 0x0 0 = ABT_DIS
1 = ABT_EN
IRAMB: Abort on USR mode access to iRAMb memory space

1 0x0 0 = ABT_DIS
1 = ABT_EN
IRAMA: Abort on USR mode access to iRAMa memory space

0 0x0 0 = ABT_DIS
1 = ABT_EN
17.3 AHB “Gizmo”

AHB master/slave gizmos are essentially hardware layers used by many of the master/slave logic which need to connect to
the AHB bus.
These hardware layers handle all the AHB bus protocols and convert the more complex AHB protocol into a much simpler IP
interface/handshake.

AHB
Because the AHB master/slave gizmos interface with many IP logic with different characteristics varying in speed, latency,
etc., the gizmos accept a number of static configuration bits. Depending on system speed, latency requirement, transfer
direction, burst characteristic, etc., these static configuration bits can be pre-configured to give extra performance or improve
bus efficiency.
17.3.1 AHB Gizmo Registers

17.3.1.1 AHB_GIZMO_AHB_MEM_0
AHB Master/Slave Gizmo Register

Given below is a description of each configuration field, what they are used for and the pros and cons of using them.
Note: These configuration bits are meant to be changed only when the particular gizmo you want
to change is idle (not being used). Changing the configuration bits on-the-fly while that
gizmo is active can hang the system.
AHB gizmo configuration bit definition:
(1) AHB Master Gizmo

1. MAX_AHB_BURSTSIZE: Controls the maximum burst size that this gizmo can generate on the AHB bus. For the
current system, this field should be set to burst-of-8.
2. IMMEDIATE: Controls how quickly an AHB write request on the bus can start.
- If 1, the gizmo will start an AHB write request once the IP side provides one beat of data of a burst. For IP that
can provide quick continuous burst data, this setting provides parallelism between AHB request and IP data
transfer. However, for IP that cannot provide quick burst data, this setting will force this gizmo to hold the AHB
bus longer, reducing bus efficiency.
- If 0, gizmo will wait until all beats of data of a burst are provided before starting an AHB write request. With this
setting, AHB bus efficiency is realized but IP latency and efficiency may be reduced.
3. RD_DATA: Controls how read data will be returned from the gizmo to the IP side.
- If 1, all beats of data of a burst have to be available before it indicates to the IP logic that read data is ready. This
setting ensures there is no wait-state (bubble) between read data burst, but it will increase latency.
- If 0, each beat of data of a burst will be sent from gizmo to the IP logic immediately. This setting will reduce
latency, but can create non-consecutive data burst or bubble between data.
4. REQ_NEG_CNT: Provides a way to limit (in terms of number of AHB bus clock) how fast/often this master can
request the AHB bus. The bigger the number, the slower the rate of AHB request.
(2) AHB Slave Gizmo

1. ENABLE_SPLIT: Controls enabling the split feature of the AHB bus.
- If 1, the gizmo will always generate split response for a read. If 'DONT_SPLIT_AHB_WR' is set to 0, gizmo also
generates split response if it can no longer accept a write request from the AHB master. This setting can
increase AHB bus utilization since it allows other AHB masters to talk to other AHB slaves while this original AHB
slave is fetching read data. However, the flip side is that it takes longer time for the original AHB master to get
the read data, because the original AHB master has to re-arbitrate for the AHB bus again to get to the data it
asked for.

AHB
- If 0, the gizmo will not generate split response. Instead, it will hold on to the AHB bus until all the requested read
data is returned back to the AHB master. This setting will reduce read latency to the master, but decrease AHB
bus utilization.
2. FORCE_TO_AHB_SINGLE: Controls how the gizmo treats the AHB master's burst request.
- If 1, the gizmo will break up the burst request internally into individual single word requests.
- If 0, the gizmo will burst request internally as burst request.
3. ENB_FAST_REARBITRATE: Controls when the gizmo can allow the original read requested AHB master to re-
arbitrate for the AHB bus again so the AHB master can retrieve the originally requested read data.
- If 1, once first read data of a burst is in the slave gizmo's FIFO, it will allow the original AHB master to re-
arbitrate, thus, allowing arbitration to happen in parallel with subsequent read data of a burst. However, if the
data burst has wait-states or bubbles, then this setting will decrease AHB bus utilization because the slave gizmo
will hold on to the AHB bus longer.
- If 0, all read data of a burst must be in the slave gizmo's FIFO before it allows the original AHB master to re-
arbitrate to retrieve the read data. This increases read data latency, and also increase AHB bus utilization.
4. IP_WR_REQ_IMMEDIATE: Controls when the gizmo will start write data request to the IP logic.
- If 1, the gizmo will start write request to the IP logic once it gets one write data of a burst from the AHB side. This
setting will create non-consecutive/bubbles in a write data burst.
- If 0, the gizmo will start write request to the IP logic only when it gets all write data of a burst from the AHB side.
This setting will create consecutive data burst (no bubbles or wait-states).
5. MAX_IP_BURSTSIZE: Controls the maximum burst size that this gizmo can generate to the IP logic.
6. ACCEPT_AHB_WR_ALWAYS: Controls how the slave gizmo will treat AHB write request.
- If 1, the gizmo will always accept a write request without checking whether it's FIFOs can accept the write or not.
This setting can reduce bus utilization, but can reduce the rate of AHB retry.
- If 0, the gizmo will check its FIFOs to make sure they have room before accepting the AHB write request. This
setting increase bus utilization, but can create a lot of AHB retry.
7. DONT_SPLIT_AHB_WR: Controls whether to split AHB write request when the slave gizmo determines it cannot
accept the write request.
- If 1 and when ENABLE_SPLIT=1, the gizmo will generate split for write if its FIFOs are not ready to accept the
AHB write request or data. This setting can improve AHB bus utilization as there are no continuous AHB master
retries on the bus.
- If 0, the gizmo will generate retry response for write if its FIFOs are not ready to accept the AHB write request.
Software should leave this bit at 0 since this feature has not been proven.
AHB Gizmo AHB-DMA/Memory Control Register

Offset: 0x10 │ Read/Write: R/W │ Reset: 0x00020081 (0b00000000xxxxx010xxxxxx0010xxx001) | Default: 0x00000304
SW
Default
REQ_NEG_CNT: AHB master request negate count. This is an 8-bit counter

31:24 0x0 NONE used to indicate the minimum number of clock counts between requests from
this AHB master.
IMMEDIATE: AHB master gizmo (AHB-DMA) – Start AHB write request

immediately
1 = Start the AHB write request immediately as soon as the device has put
18 0x0 NONE
one write data in the AHB gizmos queue.
0 = Start the AHB write request only when all the write data has transferred
from the device to the AHB gizmos queue.

AHB
SW
Default
0 = DISABLE
1 = ENABLE
MAX_AHB_BURSTSIZE: AHB master gizmo (AHB-DMA) – Maximum allowed

AHB burst size.
00 = Single transfer
01 = Burst-of-4
10 = Burst-of-8
17:16 0x2 NONE
11 = Burst-of-16
0 = DMA_BURST_1WORDS
EN_USB_WAIT_COMMIT_ON_1K_STALL: Enabling this register and

enabling WR_WAIT_COMMIT_ON_1K causes MC requests to be stalled
when the current request from the USB is in a different 4KB block with respect
9 0x0 ENABLE to the previous USB request. The register field name indicates 1K but the
actual implementation is 4K.
0 = DISABLE
1 = ENABLE
WR_WAIT_COMMIT_ON_1K: writes to ahbslv will only be issued to the MC

when all prior writes in different 4KB pages have reached the point of
coherency. This is needed because the MC allows re-ordering of transactions.
If this is not set, an entity which polls memory for a descriptor or flag to
8 0x0 ENABLE indicate some other memory has been written, may think something is
available in memory when it is not. The register field name indicates 1K but
the actual implementation is 4K.
0 = DISABLE
1 = ENABLE
DONT_SPLIT_AHB_WR: AHB slave gizmo (memory controller) – Do not split

AHB write transaction
1 = Do not split AHB write transaction ever.
7 0x1 NONE
0 (and enable_split=1) = Allow AHB write transaction to be split.
0 = ENABLE
1 = DISABLE
ACCEPT_AHB_WR_ALWAYS: AHB slave gizmo (memory controller) -

Accept AHB write request always.
1= Always accept AHB write request without checking whether there is room
in the queue to store the write data. Bypass Memory Controller AHB slave
gizmo write queue.
6 0x0 NONE
0 = Accept AHB write request only when there is enough room in the queue to
store all the write data. Memory controller AHB slave gizmos write queue is
used in this case.
0 = ACCEPT_ON_CHECK
1 = ACCEPT_ON_NOCHECK
ENB_FAST_REARBITRATE: AHB slave gizmo - Enable fast re-arbitration.

1 = Allow AHB master re-arbitration as soon as the device returns one read
data into the gizmos queue.
2 0x0 ENABLE 0 = Allow AHB master re-arbitration only when the device returns all read data
into the gizmos queue.
0 = DISABLE
1 = ENABLE

AHB
SW
Default
FORCE_TO_AHB_SINGLE: AHB slave gizmo (memory controller) - Force all

AHB transaction to single data request transaction
1 = Force to single data transaction always.
1 0x0 NONE 0 = Do not force to single data transaction.
0 = NOT_SINGLE_DATA
1 = SINGLE_DATA
ENABLE_SPLIT: AHB slave gizmo (memory controller) - Enable splitting AHB

transaction.
0 0x1 NONE
0 = DISABLE
1 = ENABLE
17.3.1.2 AHB_GIZMO_APB_DMA_0
AHB Gizmo APB-DMA Control Register

Offset: 0x14 │ Read/Write: R/W │ Reset: 0x00020000 (0b00000000xxxxx010xxxxxxxxxxxxxxxx )
31:24 0x0 REQ_NEG_CNT: AHB master request negate count. This is an 8-bit counter used to
indicate the minimum number of clock counts between requests from this AHB master.
18 0x0 IMMEDIATE: AHB master gizmo (AHB-DMA) - Start AHB write request immediately.
1 = Start the AHB write request immediately as soon as the device has put one write
data in the AHB gizmos queue.
0 = Start the AHB write request only when all the write data has transferred from the
device to the AHB gizmos queue.
0 = DISABLE
1 = ENABLE
17:16 0x2 MAX_AHB_BURSTSIZE: AHB master gizmo - Maximum allowed AHB burst size.
00 = single transfer
01 = burst-of-4
10 = burst-of-8
11 = burst-of-16
17.3.1.3 AHB_MASTER_SWID_0
AHB Master SWID[0] Register

Writes are secure.
Offset: 0x18 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxx0xx000000x0xxxx0000000)
21 0x0 MIPIHSI: SWID[0] for MIPIHSI
18 0x0 USB2:SWID[0] for USB2
17 0x0 USB3: SWID[0] for USB3
16 0x0 BSEA:SWID[0] for BSEA

AHB
15 0x0 DDS:SWID[0] for DDS
14 0x0 SE:SWID[0] for SE
13 0x0 BSEV:SWID[0] for BSEV
11 0x0 NOR: SWID[0] for NOR
5 0x0 AHBDMA:SWID[0] for AHBDMA
4 0x0 ARC: SWID[0] for ARC
3 0x0 CORESIGHT:SWID[0] for CORESIGHT
2 0x0 VCP:SWID[0] for VCP
1 0x0 COP:SWID[0] for COP
0 0x0 CPU:SWID[0] for CPU
17.3.1.4 AHB_GIZMO_USB_0
AHB Gizmo USB Control Register

Offset: 0x20 │ Read/Write: R/W │ Reset: 0x00020087 (0b00000000xxxxx010xxxxxxxx10xxx111)
0 = DISABLE
1 = ENABLE
01 = burst-of-4
10 = burst-of-8
11 = burst-of-16.
7 0x1 DONT_SPLIT_AHB_WR: AHB slave gizmo – do not split AHB write transaction.
0 = ENABLE
1 = DISABLE

AHB
6 0x0 ACCEPT_AHB_WR_ALWAYS: AHB slave gizmo - Accept AHB write request always.
1 = Always accept AHB write request without checking whether there is room in the
queue to store the write data.
0 = Accept AHB write request only when there is enough room in the queue to store all
the write data.
0 = ACCEPT_ON_CHECK
2 0x1 ENB_FAST_REARBITRATE: AHB slave gizmo - Enable fast re-arbitration.

1 = Allow AHB master re-arbitration as soon as the device returns one read data into the
gizmos queue.
0 = Allow AHB master re-arbitration only when the device returns all read data into the
gizmos queue.
0 = DISABLE
1 = ENABLE
1 0x1 FORCE_TO_AHB_SINGLE: AHB slave gizmo - Force all AHB transaction to single data
request transaction.
0 = Do not force to single data transaction.
0 = NOT_SINGLE_DATA
1 = SINGLE_DATA
0 0x1 ENABLE_SPLIT: AHB slave gizmo - Enable splitting AHB transactions.

0 = DISABLE
1 = ENABLE
17.3.1.5 AHB_GIZMO_AHB_XBAR_BRIDGE_0
AHB Gizmo AHB XBAR Bridge Control Register

Offset: 0x24 │ Read/Write: R/W │ Reset: 0x0000008d (0bxxxxxxxxxxxxxxxxxxxxxxxx10001101)
7 0x1 DONT_SPLIT_AHB_WR: AHB slave gizmo – do not split AHB write transaction.
0 = ENABLE
1 = DISABLE
6 0x0 ACCEPT_AHB_WR_ALWAYS: AHB slave gizmo - Accept AHB write request always.
0 = Accept AHB write request only when there is enough room in the queue to store all
the write data.
0 = ACCEPT_ON_CHECK

AHB
5:4 0x0 MAX_IP_BURSTSIZE: AHB slave gizmo - Maximum allowed IP burst size.
01 = burst-of-4
10 = burst-of-8
11 = burst-of-16.
3 0x1 IMMEDIATE: AHB slave gizmo - Start write request to device immediately.
1 = Start write request on the device side as soon as the AHB master puts data into the
gizmos queue.
0 = Start the device write request only when the AHB master has placed all write data
0 = DISABLE
1 = ENABLE
2 0x1 ENB_FAST_REARBITRATE: AHB slave gizmo - Enable fast re-arbitration.

gizmos queue.
0 = Allow AHB master re-arbitration only when the device returns all read data into the
gizmos queue.
0 = DISABLE
1 = ENABLE
1 0x0 FORCE_TO_AHB_SINGLE: AHB slave gizmo - Force all AHB transaction to single data
0 = NOT_SINGLE_DATA
1 = SINGLE_DATA
0 0x1 ENABLE_SPLIT: AHB slave gizmo - Enable splitting AHB transactions.

0 = DISABLE
1 = ENABLE
17.3.1.6 AHB_GIZMO_CPU_AHB_BRIDGE_0
AHB Gizmo CPU AHB Bridge Control Register

Offset: 0x28 │ Read/Write: R/W │ Reset: 0x00060000 (0b00000000xxxxx110xxxxxxxxxxxxxxxx)
indicate the minimum number of clock counts between requests from this AHB master

AHB
0 = DISABLE
1 = ENABLE
01 = burst-of-4
10 = burst-of-8
11 = burst-of-16.
17.3.1.7 AHB_GIZMO_COP_AHB_BRIDGE_0
AHB Gizmo COP AHB Bridge Control Register

Offset: 0x2c │ Read/Write: R/W │ Reset: 0x00060000 (0b00000000xxxxx110xxxxxxxxxxxxxxxx)
indicate the minimum number of clock counts between requests from this AHB master
0 = DISABLE
1 = ENABLE
01 = burst-of-4
10 = burst-of-8
11 = burst-of-16.

AHB
17.3.1.8 AHB_GIZMO_XBAR_APB_CTLR_0
AHB Gizmo XBAR APB Control Register

Offset: 0x30 │ Read/Write: R/W │ Reset: 0x00000008 (0bxxxxxxxxxxxxxxxxxxxxxxxxxx001xxx)
5:4 0x0 MAX_IP_BURSTSIZE: AHB slave gizmo - Maximum allowed IP burst size.
01 = burst-of-4
10 = burst-of-8
11 = burst-of-16.
3 0x1 IMMEDIATE: AHB slave gizmo - Start write request to device immediately.
1 = Start write request on the device side as soon as the AHB master puts data into the
gizmos queue.
0 = Start the device write request only when the AHB master has placed all write data
0 = DISABLE
1 = ENABLE
17.3.1.9 AHB_GIZMO_VCP_AHB_BRIDGE_0
AHB Gizmo VCP AHB Bridge Control Register

REQ_NEG_CNT: AHB master request negate count. This is an 8-bit counter used to
31:24 0x0
IMMEDIATE: AHB master gizmo (AHB-DMA) - Start AHB write request immediately.
18 0x1 0 = Start the AHB write request only when all the write data has transferred from the
0 = DISABLE
1 = ENABLE
MAX_AHB_BURSTSIZE: AHB master gizmo - Maximum allowed AHB burst size.

01 = burst-of-4
10 = burst-of-8
17:16 0x2 11 = burst-of-16.

AHB
17.3.1.10 AHB_MASTER_SWID_1
AHB Master SWID[1] Register

Writes are secure.
Offset: 0x38 │ Read/Write: R/W│ Reset: 0x00000000 (0bxxxxxxxxxx0xx000000x0xxxx0000000)
20 0x0 MIPIHSI: SWID[1] for MIPIHSI
17 0x0 USB3: SWID[1] for USB3
16 0x0 BSEA:SWID[1] for BSEA
15 0x0 DDS:SWID[1] for DDS
14 0x0 SE:SWID[1] for SE
13 0x0 BSEV:SWID[1] for BSEV
11 0x0 NOR:SWID[1] for NOR
5 0x0 AHBDMA:SWID[1] for AHBDMA
4 0x0 ARC: SWID[1] for ARC
3 0x0 CORESIGHT:SWID[1] for CORESIGHT
2 0x0 VCP:SWID[1] for VCP
1 0x0 COP:SWID[1] for COP
0 0x0 CPU:SWID[1] for CPU
17.3.1.11 AHB_GIZMO_SE_0
AHB Gizmo SE Control Register

Offset: 0x50 │ Read/Write: R/W │ Reset: 0x00020000 (0b00000000xxxxx010xxxxxxxxxxxxxxxx) | Default: 0x00000000
REQ_NEG_CNT: AHB master request negate count. This is an 8-bit counter used
31:24 0x0 NONE to indicate the minimum number of clock counts between requests from this AHB
master.
1 = Start the AHB write request immediately as soon as the device has put one
write data in the AHB gizmos queue
18 DISABLE DISABLE 0 = Start the AHB write request only when all the write data has transferred from the
0 = DISABLE
1 = ENABLE

17:16 DMA_BURST_8WORDS NONE 01 = burst-of-4
10 = burst-of-8
11 = burst-of-16

AHB

17.3.1.12 AHB_GIZMO_TZRAM_0
AHB Gizmo AHB TZRAM Control Register

Offset: 0x54 │ Read/Write: R/W │ Reset: 0x00000081 (0bxxxxxxxxxxxxxxxxxxxxxxxx10xxx001)
DONT_SPLIT_AHB_WR: AHB slave gizmo – Do not split AHB write transaction.

7 0x1 0 (and enable_split=1) = Allow AHB write transaction to be split.
0 = ENABLE
1 = DISABLE
ACCEPT_AHB_WR_ALWAYS: AHB slave gizmo - Accept AHB write request always.

1 = Always accept AHB write request without checking whether there is room in the queue to
store the write data.
6 0x0 0 = Accept AHB write request only when there is enough room in the queue to store all the
write data.
0 = ACCEPT_ON_CHECK

gizmos queue.
2 0x0 0 = Allow AHB master re-arbitration only when the device returns all read data into the gizmos
queue.
0 = DISABLE
1 = ENABLE
FORCE_TO_AHB_SINGLE: AHB slave gizmo - Force all AHB transaction to single data
1 0x0
0 = NOT_SINGLE_DATA
1 = SINGLE_DATA
ENABLE_SPLIT: AHB slave gizmo - Enable splitting AHB transactions.

0 0x1 0 = DISABLE
1 = ENABLE
17.3.1.13 AHB_GIZMO_BSEV_0
This is the VDE's BSEV master gizmo configuration.
AHB Gizmo BSE Control Register

Offset: 0x64 │ Read/Write: R/W │ Reset: 0x00020000 (0b00000000xxx0x010xxxxxxxxxxxxxxxx)
20 0x0 RESERVED_GIZMO_BSEV: Reserved for future use

AHB
NOTE: THIS SHOULD NEVER BE SET TO ENABLE (BSEV requires this bit to be 0).
0 = DISABLE
1 = ENABLE
01 = burst-of-4
10 = burst-of-8
11 = burst-of-16.
17.3.1.14 AHB_GIZMO_BSEA_0
VDE's BSEA master gizmo configuration
AHB Gizmo SCE Control Register

18 0x0 IMMEDIATE: AHB master gizmo - Start AHB write request immediately.
1 = Start the AHB write request immediately as soon as the device puts data in the AHB
gizmos queue.
NOTE: THIS SHOULD NEVER BE SET TO ENABLE (BSEV requires this bit to be 0)
0 = DISABLE
1 = ENABLE
01 = burst-of-4
10 = burst-of-8
11 = burst-of-16.
17.3.1.15 AHB_GIZMO_NOR_0
AHB Gizmo AHB NOR Flash Control Register

Offset: 0x78 | Read/Write: R/W | Reset: 0x00020081 (0b00000000xxxxx010xxxxxxxx10xxx001)
AHB
REQ_NEG_CNT: AHB master request negate count. This 8-bit counter is used to
31:24 0x0 indicate the minimum number of clock counts between requests from this AHB
master.
data in the AHB gizmos queue
18 DISABLE 0 = Start the AHB write request only when all the write data has transferred from the
0 = DISABLE
1 = ENABLE

00 = Single transfer.
01 = Burst-of-4.
10 = Burst-of-8.
17:16 DMA_BURST_8WORDS 11 = Burst-of-16.

1 = Do not ever split AHB write transaction.
7 0x1 0 (and enable_split=1) = Allow AHB write transactions to be split.
0 = ENABLE
1 = DISABLE
ACCEPT_AHB_WR_ALWAYS: AHB slave gizmo – Always accept AHB write

requests.
1 = Always accept AHB write requests without checking whether there is room in the
6 0x0 0 = Accept AHB write requests only when there is enough room in the queue to store
all the write data.
0 = ACCEPT_ON_CHECK

1 = Allow AHB master re-arbitration as soon as the device returns one read data into
the gizmo’s queue.
2 0x0 0 = Allow AHB master re-arbitration only when the device returns all read data into
the gizmo’s queue.
0 = DISABLE
1 = ENABLE
FORCE_TO_AHB_SINGLE: AHB slave gizmo - Force all AHB transactions to single

data request transaction.
1 0x0
0 = NOT_SINGLE_DATA
1 = SINGLE_DATA

0 0x1 0 = DISABLE
1 = ENABLE
17.3.1.16 AHB_GIZMO_USB2_0
USB2 master gizmo configuration.
AHB Gizmo USB2 Control Register

Offset: 0x7c │ Read/Write: R/W │ Reset: 0x00020087 (0b00000000xxxxx010xxxxxxxx10xxx111)

AHB
31:24 0x0
IMMEDIATE: AHB master gizmo - Start AHB write request immediately.

gizmos queue.
0 = DISABLE
1 = ENABLE

01 = burst-of-4
10 = burst-of-8
17:16 0x2 11 = burst-of-16.

0 = ENABLE
1 = DISABLE

6 0x0 0 = Accept AHB write request only when there is enough room in the queue to store all
the write data.
0 = ACCEPT_ON_CHECK

gizmos queue.
2 0x1 0 = Allow AHB master re-arbitration only when the device returns all read data into the
gizmos queue.
0 = DISABLE
1 = ENABLE
1 0x1 0 = Do not force to single data transaction.
0 = NOT_SINGLE_DATA
1 = SINGLE_DATA

0 0x1 0 = DISABLE
1 = ENABLE

AHB
17.3.1.17 AHB_GIZMO_USB3_0
USB3 master gizmo configuration.
AHB Gizmo USB3 Control Register

Offset: 0x80 │ Read/Write: R/W │ Reset: 0x00020087 (0b00000000xxxxx010xxxxxxxx10xxx111)
31:24 0x0
IMMEDIATE: AHB master gizmo - Start AHB write request immediately.

gizmos queue.
0 = DISABLE
1 = ENABLE

01 = burst-of-4
17:16 0x2 10 = burst-of-8. 11 = burst-of-16.

0 = ENABLE
1 = DISABLE

6 0x0 0 = Accept AHB write request only when there is enough room in the queue to store all
the write data.
0 = ACCEPT_ON_CHECK

1 = Allow AHB master re-arbitration as soon as the device returns one read data into
the gizmos queue.
2 0x1 0 = Allow AHB master re-arbitration only when the device returns all read data into the
gizmos queue.
0 = DISABLE
1 = ENABLE
1 0x1 0 = Do not force to single data transaction.
0 = NOT_SINGLE_DATA
1 = SINGLE_DATA

0 0x1 0 = DISABLE
1 = ENABLE

AHB
17.3.1.18 AHB_GIZMO_DDS_0
AHB Gizmo DDS Control Register

31:24 0x0 to indicate the minimum number of clock counts between requests from this AHB
master.
IMMEDIATE: AHB master gizmo (AHB-DMA) - Start AHB write request

immediately.
18 DISABLE 0 = Start the AHB write request only when all the write data has transferred from
the device to the AHB gizmos queue.
0 = DISABLE
1 = ENABLE

00 = single transfer.
01 = burst-of-4.
10 = burst-of-8.
17:16 DMA_BURST_8WORDS 11 = burst-of-16.
17.3.1.19 AHB_GIZMO_MIPIHSI_0
AHB Gizmo MIPIHSI Control Register

master.

immediately.
0 = DISABLE
1 = ENABLE

01 = burst-of-4.
10 = burst-of-8.

AHB
17.3.1.20 AHB_GIZMO_ARC_0
AHB Gizmo ARC Control Register

MC Master Gizmo Configuration
master.

immediately.
0 = DISABLE
1 = ENABLE

01 = burst-of-4.
10 = burst-of-8.
17.3.1.21 AHB_AHB_WRQ_EMPTY_0
Offset: 0xc4 │ Read/Write: RO │ Reset: 0x0000000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
1 X COP_AHB_WRQ_EMPTY
0 X CPU_AHB_WRQ_EMPTY
17.4 AHB Memory Controller Slave

The AHB memory controller slave is the path used by AHB bus masters to access the Memory Controller. It provides access
to DRAM from the AHB bus and can pre-fetch data.
17.4.1 AHB Memory Pre-Fetcher

The AHB memory controller slave contains a pre-fetcher block. This is intended to improve performance for AHB masters
performing sequential reads from DRAM. Performance can be a problem because the AHB bus protocol only allows a single
outstanding read request from a master, so the round trip latency limits bandwidth. As there are two level of arbitration, firstly
on AHB and secondly within the memory controller, this latency can become large on a busy system.
There are eight such pre-fetchers, allowing this function to be active for up to eight AHB masters.
When the pre-fetcher is enabled, the first read request initiates a speculative read of up to 128 bytes, and subsequent linear
reads will return the data directly to the AHB master without going through the memory controller to DRAM.

AHB
17.4.1.1 Pre-Fetch Invalidate

The pre-fetch buffer’s contents are invalidated under any of the following conditions, in all cases a read refers to a DRAM read
by the assigned AHB master:
 The programmed time-out value is reached since the last read

 A read occurs which is not sequential with the previous read
 A read occurs which is not the same size as the previous read, unless the corresponding
DISABLE_CHECK_SIZE_MASTERx bit is set.
 A read occurs which is past the end of the pre-fetch buffer (this will trigger a new fill of the buffer).
 The pre-fetcher is disabled. A momentary disable and then re-enable can be used to invalidate the buffer.
17.4.1.2 Pre-Fetch Buffer Coherency

As the pre-fetch buffer contains a copy of data in DRAM, there is an inherent coherency risk if the DRAM data is updated. The
hardware invalidation mechanisms provide some protection here, but there remains risk of subtle problems arising from this
hardware. If an AHB master shows errors that appear to arise from stale data then a reasonable experiment is to disable the
pre-fetcher to see if that cures the problem. If so, the following guidelines may help.
Problems have been seen for control structures such as USB Transfer Descriptors.
Two approaches can resolve this problem:
1. Pad the data
As the pre-fetcher invalidates the buffer for any non-sequential read, placing some padding will prevent pre-fetch issues. A
problem can be triggered by using something like this:
struct dtd { unsigned HW_descriptor[K] ; } ; struct dtd dtd_array[N] ;
This makes the hardware descriptors structures as read by the USB DMA sequential, and so pre-fetchable.
If the definition is modified as:
struct dtd { unsigned HW_descriptor[K] ; unsigned Padding ; } ; struct dtd dtd_array[N] ;
Then reads by USB DMA of consecutive hardware descriptors become not sequential and so there is no coherency issue as
the pre-fetch buffer will be invalidated.
2. Invalidate the pre-fetch buffer
After updating a memory structure, the pre-fetch buffer can be invalidated by disabling the pre-fetcher and then immediately
re-enabling it.
17.4.2 AHB Memory Controller Slave Registers

17.4.2.1 AHB_AHB_MEM_PREFETCH_CFG5_0
0x6000_C0CC: ahbslv prefetch cfg5 --> reset value = 0x1883.0800.
Offset: 0xcc │ Read/Write: R/W │ Reset: 0x14800800 (0b00010100100xxxxx0000100000000000)
31 0x0 ENABLE: 1=enable, 0=disable
30:26 0x5 AHB_MST_ID:

0 = CPU

AHB

1 = COP
2 = VCP
3 = CSITE
4 = IDE
5 = AHBDMA
6 = USB
7 = APBDMA
8 = UNUSED_08
9 = SDIO1
10 = NAND_FLASH
11 = SNOR
12 = HSMMC
13 = BSEV
14 = SE
15 = UNUSED_0F
16 = BSEA
17 = USB3
18 = USB2
19 = SDIO2
20 = UNUSED_14
21 = UNUSED_15
22 = UNUSED_16
23 = UNUSED_17
24 = UNUSED_18
25 = UNUSED_19
26 = UNUSED_1A
27 = UNUSED_1B
28 = UNUSED_1C
29 = UNUSED_1D
30 = UNUSED_1E
31 = UNUSED_1F
25:21 0x4 ADDR_BNDRY: 2^(n+6) byte boundary. Any value greater than 16 will use n=16.
15:0 0x800 INACTIVITY_TIMEOUT
0x6000_C0D0: ahbslv prefetch cfg6 --> reset value = 0x1883.0800.
Offset: 0xd0 │ Read/Write: R/W │ Reset: 0x18800800 (0b00011000100xxxxx0000100000000000)
AHB_MST_ID: USB
0 = CPU
1 = COP
2 = VCP
3 = CSITE
4 = IDE
5 = AHBDMA
6 = USB
7 = APBDMA
8 = UNUSED_08
30:26 0x6 9 = SDIO1
10 = NAND_FLASH
11 = SNOR
12 = HSMMC
13 = BSEV
14 = SE
15 = UNUSED_0F
16 = BSEA
17 = USB3
18 = USB2
19 = SDIO2

AHB

20 = UNUSED_14
21 = UNUSED_15
22 = UNUSED_16
23 = UNUSED_17
24 = UNUSED_18
25 = UNUSED_19
26 = UNUSED_1A
27 = UNUSED_1B
28 = UNUSED_1C
29 = UNUSED_1D
30 = UNUSED_1E
31 = UNUSED_1F
Offset: 0xd4 │ Read/Write: R/W │ Reset: 0x1c800800 (0b00011100100xxxxx0000100000000000)
AHB_MST_ID: USB
0 = CPU
1 = COP
2 = VCP
3 = CSITE
4 = IDE
5 = AHBDMA
6 = USB
7 = APBDMA
8 = UNUSED_08
9 = SDIO1
10 = NAND_FLASH
11 = SNOR
12 = HSMMC
13 = BSEV
14 = SE
30:26 0x7 15 = UNUSED_0F
16 = BSEA
17 = USB3
18 = USB2
19 = SDIO2
20 = UNUSED_14
21 = UNUSED_15
22 = UNUSED_16
23 = UNUSED_17
24 = UNUSED_18
25 = UNUSED_19
26 = UNUSED_1A
27 = UNUSED_1B
28 = UNUSED_1C
29 = UNUSED_1D
30 = UNUSED_1E
31 = UNUSED_1F

AHB
Offset: 0xd8 │ Read/Write: R/W │ Reset: 0x20800800 (0b00100000100xxxxx0000100000000000)
AHB_MST_ID: USB
0 = CPU
1 = COP
2 = VCP
3 = CSITE
4 = IDE
5 = AHBDMA
6 = USB
7 = APBDMA
8 = UNUSED_08
9 = SDIO1
10 = NAND_FLASH
11 = SNOR
12 = HSMMC
13 = BSEV
14 = SE
30:26 0x8 15 = UNUSED_0F
16 = BSEA
17 = USB3
18 = USB2
19 = SDIO2
20 = UNUSED_14
21 = UNUSED_15
22 = UNUSED_16
23 = UNUSED_17
24 = UNUSED_18
25 = UNUSED_19
26 = UNUSED_1A
27 = UNUSED_1B
28 = UNUSED_1C
29 = UNUSED_1D
30 = UNUSED_1E
31 = UNUSED_1F
17.4.2.5 AHB_AHB_MEM_PREFETCH_CFG_X_0
If DISABLE_CHECK_SIZE is 0, then only read requests that have the exact same size as the original read request that kick-
started the prefetch process will cause a "hit". In addition, the address must be the exact next one in the sequence.
For instance, if the first request on a prefetch-enabled AHB Master arrives with SIZE=ONE_BYTE and ADDR[31:0]=0x3, then
the next access must have SIZE=ONE_BYTE and ADDR[31:0]=0x4 in order to be considered a hit.
If DISABLE_CHECK_SIZE is 1, then a read request will hit as long as the incoming ADDR[31:4]matches the
expected_ADDR[31:4]. expected_ADDR[31:4] is always either "last ADDR[31:4]" or "last ADDR[31:4] + 1", where last ADDR is
the prior read request actually issued by the AHB Master(as opposed to the last request to the CIF, which could have been a
speculative read).
expected_ADDR[31:4] is always "last ADDR[31:4]" unless "SIZE" field in the last request uses the last byte in the 16-byte CIF
word.
Offset: 0xdc │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxxxx0000000000000000)

AHB
15 0x0 DISABLE_ADDR_BNDY_CHK_MST8:
8 0x0 DISABLE_ADDR_BNDY_CHK_MST1
7 0x0 DISABLE_CHECK_SIZE_MASTER8:
17.4.2.6 AHB_ARBITRATION_XBAR_CTRL_0
XBAR Control Register

Offset: 0xe0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxxxxx00xxxxxxxxxxxxxx00)
MEM_INIT_DONE: Software should set this bit when memory has been initialized
16 0x0 0 = NOT_DONE
1 = DONE
HOLD_DIS: By default CPU accesses to IRAMs will be held if there are any pending
requests from the AHB to the IRAMs. This is done to avoid data coherency issues. If
software handles coherency then this can be turned off to improve performance.
1 0x0
Software writes to modify.
0 = ENABLE
1 = DISABLE
POST_DIS: Software writes to modify

0 0x0 0 = ENABLE
1 = DISABLE

AHB
See the description of the pre-fetcher above. 6000:C0E4: ahbslv prefetch cfg3 --> reset value = 0x1483.0800.
Offset: 0xe4 │ Read/Write: R/W │ Reset: 0x0c800800 (0b00001100100xxxxx0000100000000000)
31 0x0 ENABLE: 1=enable. 0=disable
AHB_MST_ID: AHBDMA master

0 = CPU
1 = COP
2 = VCP
3 = CSITE
4 = IDE
5 = AHBDMA
6 = USB
7 = APBDMA
8 = UNUSED_08
9 = UNUSED_09
10 = UNUSED_0A
11 = SNOR
12 = HSMMC
13 = BSEV
14 = SE
30:26 0x3 15 = UNUSED_0F
16 = BSEA
17 = USB3
18 = USB2
19 = UNUSED_13
20 = UNISED_14
21 = UNUSED_15
22 = UNUSED_16
23 = UNUSED_17
24 = UNUSED_18
25 = UNUSED_19
26 = UNUSED_1A
27 = UNUSED_1B
28 = UNUSED_1C
29 = UNUSED_1D
30 = UNUSED_1E
31 = UNUSED_1F
15:0 0x800 INACTIVITY_TIMEOUT: 2048 cycles
See the description of the pre-fetcher above. 6000:C0E8: ahbslv prefetch cfg4 --> reset value = 0x1483.0800.
Offset: 0xe8 │ Read/Write: R/W │ Reset: 0x10800800 (0b00010000100xxxxx0000100000000000)
31 0x0 ENABLE: 1=enable. 0=disable
AHB_MST_ID: AHBDMA master

0 = CPU
1 = COP
2 = VCP
30:26 0x4 3 = CSITE
4 = IDE
5 = AHBDMA
6 = USB
7 = APBDMA
8 = UNUSED_08

AHB

9 = UNUSED_09
10 = UNUSED_0A
11 = SNOR
12 = HSMMC
13 = BSEV
14 = SE
15 = UNUSED_0F
16 = BSEA
17 = USB3
18 = USB2
19 = UNUSED_13
20 = UNUSED_14
21 = UNUSED_15
22 = UNUSED_16
23 = UNUSED_17
24 = UNUSED_18
25 = UNUSED_19
26 = UNUSED_1A
27 = UNUSED_1B
28 = UNUSED_1C
29 = UNUSED_1D
30 = UNUSED_1E
31 = UNUSED_1F
17.4.2.9 AHB_AVP_PPCS_RD_COH_STATUS_0
0x6000_C0EC: ARM7 outstanding rd/wr
Offset: 0xec │ Read/Write: RO │ Reset: 0x000X000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
16 X RDS_OUTSTANDING
0 X WRS_OUTSTANDING
NV_ahbslvmem prefetch
The NV_ahbslvmem prefetch feature reduces latency and improves overall bandwidth for AHB Masters doing reads to
SDRAM. AHB only allows one outstanding read transaction at a time. When enabled, and kick-started by a first read request
(which will "miss" since there would be nothing in the prefetch FIFO) the prefetcher makes speculative read requests to the
memory controller in consecutive progression of linear address. Without this feature, an AHB Master will suffer roundtrip
latency through the gizmo, PPCS, CIF, MC arbitration, and all the read data passing for every AHB transaction.
Address Boundaries for prefetching will stop the sequential prefetch process from making additional speculations. This is
useful to help prevent coherency issues -- software needs ways to stop the prefetcher from prefetching data before the data
has been written in memory. If an AHB master can be known to make 256 byte transfers that are aligned accesses,
ADDR_BNDRY should be set to a value of 4.
INACTIVITY_TIMEOUT is intended to prevent coherency problems. If no read request from the prefetch-enabled master is
observed after the number of cycles specified in the inactivity timeout counter, then any speculatively prefetched read data is
invalidated.
There are eight AHB masters that can be enabled for prefetching. Each prefetch buffer can hold up to 8 entries (of 128 bits
each entry) of prefetched data.
AHB
0x6000_C0F0: ahbslv prefetch cfg1 --> reset value = 0x1483.0800.
Offset: 0xf0 │ Read/Write: R/W │ Reset: 0x04800800 (0b00000100100xxxxx0000100000000000)
30:26 0x1 AHB_MST_ID: AHBDMA master

0 = CPU
1 = COP
2 = VCP
3 = CSITE
4 = IDE
5 = AHBDMA
6 = USB
7 = APBDMA
8 = UNUSED_08
9 = UNUSED_09
10 = UNUSED_0A
11 = SNOR
12 = HSMMC
13 = BSEV
14 = SE
15 = UNUSED_0F
16 = BSEA
17 = USB3
18 = USB2
19 = UNUSED_13
20 = UNUSED_14
21 = UNUSED_15
22 = UNUSED_16
23 = UNUSED_17
24 = UNUSED_18
25 = UNUSED_19
26 = UNUSED_1A
27 = UNUSED_1B
28 = UNUSED_1C
29 = UNUSED_1D
30 = UNUSED_1E
31 = UNUSED_1F
25:21 0x4 ADDR_BNDRY: 2^(n+6) byte boundary. Any value greater than 26 will
use n=26.
See the description of the pre-fetcher above. 0x6000_C0F4: ahbslv prefetch cfg2 --> reset value = 0x1883.0800.
Offset: 0xf4 │ Read/Write: R/W │ Reset: 0x08800800 (0b00001000100xxxxx0000100000000000)

AHB
30:26 0x2 AHB_MST_ID: AHBDMA master

0 = CPU
1 = COP
2 = VCP
3 = CSITE
4 = IDE
5 = AHBDMA
6 = USB
7 = APBDMA
8 = UNUSED_08
9 = UNUSED_09
10 = UNUSED_0A
11 = SNOR
12 = HSMMC
13 = BSEV
14 = SE
15 = UNUSED_0F
16 = BSEA
17 = USB3
18 = USB2
19 = UNUSED_13
20 = UNUSED_14
21 = UNUSED_15
22 = UNUSED_16
23 = UNUSED_17
24 = UNUSED_18
25 = UNUSED_19
26 = UNUSED_1A
27 = UNUSED_1B
28 = UNUSED_1C
29 = UNUSED_1D
30 = UNUSED_1E
31 = UNUSED_1F
25:21 0x4 ADDR_BNDRY: 2^(n+6) byte boundary. Any value greater than 26 will
use n=26.
17.4.2.12 AHB_AHBSLVMEM_STATUS_0
0x6000_C0F8: ahbslv outstanding rd, rdque_empty status
Offset: 0xf8 │ Read/Write: RO │ Reset: 0x0000000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
1 X PPCS_RDS_OUTSTANDING
0 X GIZMO_IP_RDQUE_EMPTY
17.4.2.13 AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0
0x6000_C0FC: AHB Memory Write Queue AHB Master ID Register

Offset: 0xfc │ Read/Write: RO │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X AHB_MASTER_ID: 0 = There is no write data in the write queue from that AHB master.

AHB
17.4.2.14 AHB_ARBITRATION_CPU_ABORT_ADDR_0
0x6000_C100: CPU Abort Address Register

Offset: 0x100 │ Read/Write: RO │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X ADDR: Instruction Address which caused the abort.
17.4.2.15 AHB_ARBITRATION_CPU_ABORT_INFO_0
0x6000_C104: CPU Abort Info Register

Offset: 0x104 │ Read/Write: RO │ Reset: 0x0000XXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
15 X IRAMA: Abort occurred due to an iRAMa protection violation

0 = ABT_DIS
1 = ABT_EN
14 X IRAMB: Abort occurred due to an iRAMb protection violation

0 = ABT_DIS
1 = ABT_EN
13 X IRAMC: Abort occurred due to an iRAMc protection violation

0 = ABT_DIS
1 = ABT_EN
12 X IRAMD: Abort occurred due to an iRAMd protection violation

0 = ABT_DIS
1 = ABT_EN
11 X INV_IRAM: Abort occurred due to an access to invalid iRAM address space

0 = ABT_DIS
1 = ABT_EN
10 X PPSB: Abort occurred due to a PPSB protection violation

0 = ABT_DIS
1 = ABT_EN
9 X APB: Abort occurred due to an APB protection violation

0 = ABT_DIS
1 = ABT_EN
8 X AHB: Abort occurred due to an AHB protection violation

0 = ABT_DIS
1 = ABT_EN
7 X CACHE: Abort occurred due to a Cache protection violation

0 = ABT_DIS
1 = ABT_EN
6 X PROTECTION: TRUE for any protection violation

0 = ABT_DIS
1 = ABT_EN

AHB
5 X ALIGN: TRUE for abort caused by Misalignment (i.e., word access at odd byte address)
0 = ABT_DIS
1 = ABT_EN
4 X BADSIZE: TRUE for abort caused by Bad Size (i.e., word access at odd byte address)
0 = ABT_DIS
1 = ABT_EN
3 X WRITE: Aborted transaction was a Write

0 = ABT_DIS
1 = ABT_EN
2 X DATA: Aborted transaction was a Data access

0 = ABT_DIS
1 = ABT_EN
1:0 X SIZE: Aborted transaction Request Size

00=byte
01=halfword
10=word
0 = BYTE_ABT
1 = HWORD_ABT
2 = WORD_ABT
17.4.2.16 AHB_ARBITRATION_COP_ABORT_ADDR_0
0x6000_C108: CPU Abort Address Register

31:0 X ADDR: Instruction Address which caused the abort
17.4.2.17 AHB_ARBITRATION_COP_ABORT_INFO_0
0x6000_C10C: COP Abort Info Register

Offset: 0x10c │ Read/Write: RO │ Reset: 0x0000XXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
15 X IRAMA: Abort occurred due to an iRAMa protection violation

0 = ABT_DIS
1 = ABT_EN
14 X IRAMB: Abort occurred due to an iRAMb protection violation

0 = ABT_DIS
1 = ABT_EN
13 X IRAMC: Abort occurred due to an iRAMc protection violation

0 = ABT_DIS
1 = ABT_EN

AHB
10 X PPSB: Abort occurred due to a PPSB protection violation

0 = ABT_DIS
1 = ABT_EN
9 X APB: Abort occurred due to an APB protection violation

0 = ABT_DIS
1 = ABT_EN
8 X AHB: Abort occurred due to an AHB protection violation

0 = ABT_DIS
1 = ABT_EN
7 X CACHE: Abort occurred due to a Cache protection violation

0 = ABT_DIS
1 = ABT_EN
6 X PROTECTION: TRUE for any protection violation

0 = ABT_DIS
1 = ABT_EN
5 X ALIGN: TRUE for abort caused by Misalignment (i.e., word access at odd byte address)
0 = ABT_DIS
1 = ABT_EN
4 X BADSIZE: TRUE for abort caused by Bad Size (i.e., word access at odd byte address)
0 = ABT_DIS
1 = ABT_EN
3 X WRITE: Aborted transaction was a Write

0 = ABT_DIS
1 = ABT_EN
2 X DATA: Aborted transaction was a Data access

0 = ABT_DIS
1 = ABT_EN
1:0 X SIZE: Aborted transaction Request Size

00=byte
01=halfword
10=word
0 = BYTE_ABT
1 = HWORD_ABT
2 = WORD_ABT
17.4.2.18 AHB_AHB_SPARE_REG_0
0x6000_C110: AHB Spare Register Bits

Offset: 0x110 │ Read/Write: R/W │ Reset: 0x00000060 (0b00000000000000000000xxxxx1100000)
AHB_SPARE_REG: AHB Spare Register

31:12 0x0 Note: For Tegra K1 64-bit processors, bit 31 is used for Microcode-Boot ROM
handshaking. See the Boot Process chapter in the Tegra K1 64-Bit Processor TRM for
more information.
4:0 0x0 CSITE_PADMACRO_TRIM_SEL: Trimmer select register for CoreSight clock pad macro.

AHB
17.4.2.19 AHB_XBAR_SPARE_REG_0
0x6000_C114: XBAR Spare Register Bits

31:11 0x0 UNUSED: XBAR Diagnostic Register Spare Bits
10 0x0 DISABLE_COP_BYTE_WR: XBAR Diagnostic Register to disable COP byte writes
DISABLE_XUSB_DEV_BYTE_WR: XBAR Diagnostic Register to disable XUSB dev byte

9 0x0
writes
DISABLE_XUSB_HOST_BYTE_WR: XBAR Diagnostic Register to disable XUSB host

8 0x0
byte writes
DISABLE_SDMMC_BYTE_WR: XBAR Diagnostic Register to disable SDMMC byte

7 0x0
writes
DISABLE_XBAR_APB_BYTE_WR: XBAR Diagnostic Register to disable byte writes to

6 0x0
APB slaves
MASK_PEND_IRAM_REQ: XBAR Diagnostic Register to mask pending IRAM request

5 0x0
while arbitration
KILL_NEXT_REQ_ON_ABORT_UCQ: XBAR Diagnostic Register to kill next request on

4 0x0
ABORT from UCQ
KILL_NEXT_REQ_ON_ABORT_AHB: XBAR Diagnostic Register to kill next request on

3 0x0
ABORT from AHB Bridge
KILL_NEXT_REQ_ON_ABORT_VCP2: XBAR Diagnostic Register to kill next request on

2 0x0
ABORT from VCP2
KILL_NEXT_REQ_ON_ABORT_COP: XBAR Diagnostic Register to kill next request on

1 0x0
ABORT from COP
KILL_NEXT_REQ_ON_ABORT_APC: XBAR Diagnostic Register to kill next request on

0 0x0
ABORT from APC
17.4.2.20 AHB_AVPC_MCCIF_FIFOCTRL_0
Note: The FIFO timing aspects of this register are no longer supported, but are retained for
software compatibility.
The clock override/ovr_mode fields of this register control the second-level clock gating for the client and MC sides of the
MCCIF. All clock gating is enabled by default.
A '1' written to the rclk/wclk override field will result in one of the following:
 With wclk/rclk override mode = LEGACY, the clock reverts to legacy mode of operation where the clock is on
 With wclk/rclk override mode = ON, the clock is always on inside the MCCIF and PC
A '1' written to the CCLK override field keeps the client's clock always on inside the MCCIF.

AHB
Offset: 0x120 │ Byte Offset: 0x480 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxx00000xxxxxxxxxxxx0000)
AVPC_RCLK_OVR_MODE:
1 = ON
AVPC_WCLK_OVR_MODE:
1 = ON
18 0x0 AVPC_CCLK_OVERRIDE
17 0x0 AVPC_RCLK_OVERRIDE
16 0x0 AVPC_WCLK_OVERRIDE
AVPC_MCCIF_RDCL_RDFAST:
1 = ENABLE
AVPC_MCCIF_WRMC_CLLE2X:
1 = ENABLE
AVPC_MCCIF_RDMC_RDFAST:
1 = ENABLE
AVPC_MCCIF_WRCL_MCLE2X:
1 = ENABLE
17.4.2.21 AHB_TIMEOUT_WCOAL_AVPC_0
Note: Write coalescing is no longer supported by the MCCIF clients. Registers are retained for
software compatibility but are not used by the hardware.
Write Coalescing Time-Out Register

Offset: 0x124 │ Byte Offset: 0x490 │ Read/Write: R/W │ Reset: 0x00000032 (0bxxxxxxxxxxxxxxxxxxxxxxxx00110010)
7:0 0x32 AVPCARM7W_WCOAL_TMVAL
17.4.2.22 AHB_MPCORELP_MCCIF_FIFOCTRL_0
software compatibility
 With wclk/rclk override mode = LEGACY, the clock reverts to legacy mode of operation, where the clock is on

AHB
 With wclk/rclk override mode = ON, the clock is always on inside MCCIF and PC.
Offset: 0x128 │ Byte Offset: 0x4a0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxx00000xxxxxxxxxxxxxxxx)
SYS_REGS_MPCORELP_RCLK_OVR_MODE:
1 = ON
SYS_REGS_MPCORELP_WCLK_OVR_MODE:
1 = ON
18 0x0 SYS_REGS_MPCORELP_CCLK_OVERRIDE
17 0x0 SYS_REGS_MPCORELP_RCLK_OVERRIDE
16 0x0 SYS_REGS_MPCORELP_WCLK_OVERRIDE
17.4.2.23 AHB_MPCORE_MCCIF_FIFOCTRL_0
software compatibility
 With wclk/rclk override mode = LEGACY, the clock reverts to legacy mode of operation, where the clock is on
 With wclk/rclk override mode = ON, the clock is always on inside MCCIF and PC.
Offset: 0x12c │ Byte Offset: 0x4b0 │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxxxxxx00000xxxxxxxxxxxxxxxx)
SYS_REGS_MPCORE_RCLK_OVR_MODE:
1 = ON
SYS_REGS_MPCORE_WCLK_OVR_MODE:
1 = ON
18 0x0 SYS_REGS_MPCORE_CCLK_OVERRIDE
17 0x0 SYS_REGS_MPCORE_RCLK_OVERRIDE
16 0x0 SYS_REGS_MPCORE_WCLK_OVERRIDE

18.0 APB
18.1 APB Miscellaneous Registers

This section describes a number of system control registers that are grouped together in the aptly named miscellaneous
registers section. These registers are all present on the APB bus.
18.1.1 JTAG Configuration Register
18.1.1.1 APB_MISC_PP_CONFIG_CTL_0
Configuration Control Register

The use of the SO bits below has been deprecated. Keep these bits disabled at all times.
Offset: 0x24 │ Read/Write: R/W │ Reset: 0x00000040 (0bxxxxxxxxxxxxxxxxxxxxxxxx01xxxx00)
TBE: 0 = Disable ; 1 = Enable RTCK Daisy chaining

1 = ENABLE
JTAG: 0 = Disable Debug ; 1 = Enable JTAG DBGEN

1 = ENABLE
XBAR_SO_DEFAULT: Deprecated -- keep disabled -- default SO bit for non-CPU XBAR clients
1 = ENABLE
CPU_XBAR_SO_ENABLE: Deprecated -- keep disabled --Enable CPU SO bit to propagate to

XBAR
0 DISABLE
0 = DISABLE
1 = ENABLE
18.1.1.2 APB_MISC_PP_PINMUX_GLOBAL_0_0
Global Pinmux Control Register

When both CLAMP_INPUTS_WHEN_TRISTATED is set to ENABLE and the TRISTATE field is set to TRISTATE (1b1), the
inputs to the core are clamped to zero. Software must set this bit before taking any controller using a pinmuxed pin out of
reset.
CLAMP_INPUTS_WHEN_TRISTATED: 0 = Do not clamp inputs when tristated; 1 = Clamp

inputs when tristated
0 DISABLE
0 = DISABLE
1 = ENABLE

APB
18.1.2 PULL_UP/PULL_DOWN Control Register

Controls the pull_up/pull_down inputs of the pads. Used to eliminate external components on interfaces that need
pullup/pulldown. Those are weak internal pullup/pulldowns
 NORMAL setting means pad is neither pulled up (driving weak 1) or pulled down (driving weak 0)
 PULL_DOWN selection means pad is driving weak 0
 PULL_UP selection means pad is driving weak 1
WARNING! Driving an internal pull-up when the pad has an external pull-down and vice
versa will cause a significant increase in power consumption.
Table 59: Cross Reference of Fields with Real Ball Names
Field Name Controls Balls

XM2D_PU_PD DDR_DQ0,DDR_DQ1,...,DDR_DQ31
XM2C_PU_PD MIO_IORDY,DDR_DM0,..,DDR_DM3,DDR_DQS0,...,DDR_DQS3,DDR_A0,..,DDR_A13,DDR_
BA0,DDR_BA1,DDR_CS0_,DDR_CS1_,DDR_CKE,DDR_RAS_,DDR_CAS_,DDR_WE_
DDRC_PU_PD DDR_COMP_PU, DDR_COMP_PD
18.1.2.1 APB_MISC_PP_PULLUPDOWN_REG_C_0
Offset: 0xa8 │ Read/Write: R/W │ Reset: 0x00000000 (0b000000xxxxxxxxxxxxxxxxxxxxxxxxxx)
XM2C_PU_PD:
0 = NORMAL
31:30 NORMAL 1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
XM2D_PU_PD:
0 = NORMAL
2 = PULL_UP
3 = RSVD
DDRC_PU_PD:
0 = NORMAL
2 = PULL_UP
3 = RSVD
18.1.2.2 APB_MISC_SC1X_PADS_VIP_VCLKCTRL_0
VCLK Control Register

Enable VCLK pad to get external clock for VI.
INVERSION: VCLK invert enable

1 0x0 0 = DISABLE
1 = ENABLE
IE: VCLK input enable

0 0x0 0 = DISABLE
1 = ENABLE

APB
18.1.2.3 APB_MISC_GP_HIDREV_0
Chip ID Revision Register

Offset: 0x804 │ Read/Write: RO │ Reset: 0x000XXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
19:16 X MINORREV: Chip ID minor revision
15:8 X CHIPID: Chip ID
MAJORREV: Chip ID major revision (0: Emulation, 1-15: Silicon)

7:4 X 0 = EMULATION
1 = A01
HIDFAM: Chip ID family register.

0 = GPU
1 = HANDHELD
2 = BR_CHIPS
3:0 X 3 = CRUSH
4 = MCP
5 = CK
6 = VAIO
7 = HANDHELD_SOC
18.1.3 Pad Control Registers

The registers below control pad behavior. For each digital pad, the following controls can be used to tune pad performance,
functionality, and power consumption. The pads controlled by each pad group register can be found in the Pinmux section of
this document.
 HSM_EN - High speed mode - active high, enables high speed mode for driver and receiver for better matching of the
rise/fall delay in outbound and inbound paths. Use it for clocks and the high speed signaling where the matching
timings are of importance.
 SCHMT_EN - Schmitt enable - active high, enables the Schmitt Trigger Type of I/P receiver. Default is Inverter Type
of receiver.
 LPMD - Low power mode - select low power modes (different impedance and current value). The table depicts the
function of low power mode
Table 60: Low Power Mode Functions
LPMD1 LPMD0 Power Mode Selected
0 0 X/8 Current Setting. Lowest Power or Current ( 8*Z ohm)
0 1 X/4 Current Setting ( 4*Z ohm)
1 0 X/2 Current Setting ( 2*Z ohm)
1 1 X Current Setting (Z ohm = 50 ohm ). Highest Power or Current.
 CAL_DRVDN - drive down (falling edge) - Driver Output Pull-Down drive strength code.
 CAL_DRVUP - drive up (rising edge) - Driver Output Pull-Up drive strength code. Works with combination of LMPD
bits. For lower power modes, higher drive strength are masked. See table below:

APB
LPMD1 LPMD0 CAL_DRV*4 CAL_DRV*3 CAL_DRV*2 CAL_DRV*1 CAL_DRV*0
0 0 Masked to 0 Masked to 0 Masked to 0 Pass Code Pass Code
0 1 Masked to 0 Masked to 0 Pass Code Pass Code Pass Code
1 0 Masked to 0 Pass Code Pass Code Pass Code Pass Code
1 1 Pass Code Pass Code Pass Code Pass Code Pass Code
 DRVDN_SLWR - Driver Output Rising Edge Slew 2-bit control code.

Code 11 is least slewing of signal, code 00 is highest slewing of the signal.
 DRVUP_SLWF -Driver Output Falling Edge Slew 2-bit control code.
Code 11 is least slewing of signal, code 00 is highest slewing of the signal.
18.1.3.1 APB_MISC_GP_MIPI_PAD_CTRL_0
Offset: 0x820 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0x)
DSIB_MODE:
1 CSI 0 = CSI
1 = DSI
18.1.3.2 APB_MISC_GP_AOCFG1PADCTRL_0
AOCFG1 Pad Control Register

Offset: 0x868 │ Read/Write: R/W │ Reset: 0xf0e09000 (0b1111xxx01110xxx01001xxxxxxxx00xx)
31:30 0x3 CFG2TMC_AOCFG1_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_AOCFG1_CAL_DRVDN_SLWR
24:20 0xe CFG2TMC_AOCFG1_CAL_DRVUP
16:12 0x9 CFG2TMC_AOCFG1_CAL_DRVDN
CFG2TMC_AOCFG1_SCHMT_EN: AOCFG1 data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_AOCFG1_HSM_EN: AOCFG1 data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE

Offset: 0x86c │ Read/Write: R/W │ Reset: 0xf0e09000 (0b1111xxx01110xxx01001xxxxxxxx00xx)

APB

3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.4 APB_MISC_GP_ATCFG1PADCTRL_0
ATCFG1 Pad Control Register

Offset: 0x870 │ Read/Write: R/W │ Reset: 0x01318000 (0b0000x0010011x0011000xxxx00xx00xx)
31:30 0x0 CFG2TMC_ATCFG1_CAL_DRVUP_SLWF
29:28 0x0 CFG2TMC_ATCFG1_CAL_DRVDN_SLWR
26:20 0x13 CFG2TMC_ATCFG1_CAL_DRVUP
18:12 0x18 CFG2TMC_ATCFG1_CAL_DRVDN
7:6 0x0 CFG2TMC_ATCFG1_DRV_TYPE
CFG2TMC_ATCFG1_SCHMT_EN: ATCFG1 data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_ATCFG1_HSM_EN: ATCFG1 data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE


3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE

APB


3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE

Offset: 0x87c │ Read/Write: R/W │ Reset: 0x01318000 (0b0000x0010011x0011000xxxx00xx00xx)

3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE

Offset: 0x880 │ Read/Write: R/W │ Reset: 0xf0b48000 (0b1111xxxx1011010010xxxxxxxxxx00xx)

APB

3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.9 APB_MISC_GP_CDEV1CFGPADCTRL_0
CDEV1CFG Pad Control Register

31:30 0x3 CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR
24:20 0xe CFG2TMC_CDEV1CFG_CAL_DRVUP
16:12 0x9 CFG2TMC_CDEV1CFG_CAL_DRVDN
CFG2TMC_CDEV1CFG_SCHMT_EN: CDEV1CFG data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_CDEV1CFG_HSM_EN: CDEV1CFG data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.10 APB_MISC_GP_CDEV2CFGPADCTRL_0
CDEV2CFG Pad Control Register

31:30 0x3 CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR
24:20 0xe CFG2TMC_CDEV2CFG_CAL_DRVUP
16:12 0x9 CFG2TMC_CDEV2CFG_CAL_DRVDN
CFG2TMC_CDEV2CFG_SCHMT_EN: CDEV2CFG data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_CDEV2CFG_HSM_EN: CDEV2CFG data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE

APB
18.1.3.11 APB_MISC_GP_DAP1CFGPADCTRL_0
DAP1CFG Pad Control Register

31:30 0x3 CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR
24:20 0xe CFG2TMC_DAP1CFG_CAL_DRVUP
16:12 0x9 CFG2TMC_DAP1CFG_CAL_DRVDN
CFG2TMC_DAP1CFG_SCHMT_EN: DAP1CFG data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_DAP1CFG_HSM_EN: DAP1CFG data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE


3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE


APB

3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE


3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.15 APB_MISC_GP_DBGCFGPADCTRL_0
DBGCFG Pad Control Register

Offset: 0x8a0 │ Read/Write: R/W │ Reset: 0xf0e09000 (0b1111xxx01110xxx01001xxxxxxxx00xx)
31:30 0x3 CFG2TMC_DBGCFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_DBGCFG_CAL_DRVDN_SLWR
24:20 0xe CFG2TMC_DBGCFG_CAL_DRVUP
16:12 0x9 CFG2TMC_DBGCFG_CAL_DRVDN
CFG2TMC_DBGCFG_SCHMT_EN: DBGCFG data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_DBGCFG_HSM_EN: DBGCFG data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE

APB
18.1.3.16 APB_MISC_GP_SDIO3CFGPADCTRL_0
SDIO3CFG Pad Control Register

Controls for BDSDMEM pads of SDMMC3
The following calibration codes need to be used for the pad under default condition. In general, the calibration pad will provide
the code for the pad. To bypass calibration and provide the default code for the required impedance, these values (in decimal)
should be used.
Table 61: DRV Codes
33 ohms 50 ohms 66 ohms 100 ohms

Supply
Up DN Up DN Up DN Up DN
1.8V 70 54 42 32 34 23 19
3.3V 36 20

Offset: 0x8b0 │ Read/Write: R/W │ Reset: 0x12414000 (0b0001x0100100x0010100xxxxxxxx00xx)
31:30 0x0 CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF. Maps to MSB of DRVDN[18:17].
29:28 0x1 CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR. Maps to MSB of DRVUP[26:25].
26:20 0x24 CFG2TMC_SDIO3CFG_CAL_DRVUP. 3.3V 50 ohm driver for removable SD card.
18:12 0x14 CFG2TMC_SDIO3CFG_CAL_DRVDN. 3.3V 50 ohm driver for removable SD card.
CFG2TMC_SDIO3CFG_SCHMT_EN: SDIO3CFG data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_SDIO3CFG_HSM_EN: SDIO3CFG data pins high speed mode enable. Software

should set this if I/O is running at greater than or equal to 100 MHz.
2 0x0
0 = DISABLE
1 = ENABLE
18.1.3.17 APB_MISC_GP_SPICFGPADCTRL_0
SPICFG Pad Control Register

Offset: 0x8b4 │ Read/Write: R/W │ Reset: 0xf0e09000 (0b1111xxx01110xxx01001xxxxxxxx00xx)
31:30 0x3 CFG2TMC_SPICFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_SPICFG_CAL_DRVDN_SLWR
24:20 0xe CFG2TMC_SPICFG_CAL_DRVUP
16:12 0x9 CFG2TMC_SPICFG_CAL_DRVDN
CFG2TMC_SPICFG_SCHMT_EN: SPICFG data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE

APB
CFG2TMC_SPICFG_HSM_EN: SPICFG data pins high-speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.18 APB_MISC_GP_UAACFGPADCTRL_0
UAACFG Pad Control Register

31:30 0x3 CFG2TMC_UAACFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_UAACFG_CAL_DRVDN_SLWR
24:20 0xe CFG2TMC_UAACFG_CAL_DRVUP
16:12 0x9 CFG2TMC_UAACFG_CAL_DRVDN
CFG2TMC_UAACFG_SCHMT_EN: UAACFG data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_UAACFG_HSM_EN: UAACFG data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.19 APB_MISC_GP_UABCFGPADCTRL_0
UABCFG Pad Control Register

Offset: 0x8bc │ Read/Write: R/W │ Reset: 0xf0e09000 (0b1111xxx01110xxx01001xxxxxxxx00xx)
31:30 0x3 CFG2TMC_UABCFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_UABCFG_CAL_DRVDN_SLWR
24:20 0xe CFG2TMC_UABCFG_CAL_DRVUP
16:12 0x9 CFG2TMC_UABCFG_CAL_DRVDN
CFG2TMC_UABCFG_SCHMT_EN: UABCFG data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_UABCFG_HSM_EN: UABCFG data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.20 APB_MISC_GP_UART2CFGPADCTRL_0
UART2CFG Pad Control Register

Offset: 0x8c0 │ Read/Write: R/W │ Reset: 0xf0e09000 (0b1111xxx01110xxx01001xxxxxxxx00xx)

APB
31:30 0x3 CFG2TMC_UART2CFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_UART2CFG_CAL_DRVDN_SLWR
24:20 0xe CFG2TMC_UART2CFG_CAL_DRVUP
16:12 0x9 CFG2TMC_UART2CFG_CAL_DRVDN
CFG2TMC_UART2CFG_SCHMT_EN: UART2CFG data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_UART2CFG_HSM_EN: UART2CFG data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.21 APB_MISC_GP_UART3CFGPADCTRL_0
UART3CFG Pad Control Register

Offset: 0x8c4 │ Read/Write: R/W │ Reset: 0xf0e09000 (0b1111xxx01110xxx01001xxxxxxxx00xx)
31:30 0x3 CFG2TMC_UART3CFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_UART3CFG_CAL_DRVDN_SLWR
24:20 0xe CFG2TMC_UART3CFG_CAL_DRVUP
16:12 0x9 CFG2TMC_UART3CFG_CAL_DRVDN
CFG2TMC_UART3CFG_SCHMT_EN: UART3CFG data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_UART3CFG_HSM_EN: UART3CFG data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE
Controls for BDSDMEM pads of SDMMC1
the code for the pad. To bypass calibration and provide the default code for the required impedance, these values (in decimal)
should be used.
Table 62: DRV Codes
33 ohms 50 ohms 66 ohms 100 ohms

Supply
Up DN Up DN Up DN Up DN
1.8V 70 54 42 32 34 23 19
3.3V 36 20

APB

Offset: 0x8ec │ Read/Write: R/W │ Reset: 0x52a20000 (0b0101x0101010x0100000xxxxxxxx00xx)
31:30 0x1 CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF. Maps to MSB of DRVDN[18:17]
29:28 0x1 CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR. Maps to MSB of DRVUP[26:25]
26:20 0x2a CFG2TMC_SDIO1CFG_CAL_DRVUP. 1.8V 50 ohm driver for wifi SDIO card.
18:12 0x20 CFG2TMC_SDIO1CFG_CAL_DRVDN. 1.8V 50 ohm driver for wifi SDIO card

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_SDIO1CFG_HSM_EN: SDIO1CFG data pins high speed mode enable. Software

should set this if I/O is running at greater than or equal to 100 MHz.
2 0x0
0 = DISABLE
1 = ENABLE
18.1.3.23 APB_MISC_GP_DDCCFGPADCTRL_0
CRTCFG and DDCCFG Pad Control Registers

Offset: 0x8fc │ Read/Write: R/W │ Reset: 0xc160000c (0b1100xxx10110xxx00000xxxxxxxx11xx)
31:30 0x3 CFG2TMC_DDCCFG_CAL_DRVUP_SLWF
29:28 0x0 CFG2TMC_DDCCFG_CAL_DRVDN_SLWR
24:20 0x16 CFG2TMC_DDCCFG_CAL_DRVUP
16:12 0x0 CFG2TMC_DDCCFG_CAL_DRVDN
CFG2TMC_DDCCFG_SCHMT_EN: Data pins Schmitt enable

3 0x1 0 = DISABLE
1 = ENABLE
CFG2TMC_DDCCFG_HSM_EN: Data pins high speed mode enable

2 0x1 0 = DISABLE
1 = ENABLE
18.1.3.24 APB_MISC_GP_GMACFGPADCTRL_0
Controls for BDSDMEMLV pads of SDMMC4
the code for the pad. To bypass calibration and provide the default code for the required impedance, these values (in
hexadecimal) should be used.
Table 63: DRV Codes (5-bit Code)
33 ohms 50 ohms
Supply
Up DN Up DN
1.8V 0x7 0x7 0x2 0x1

APB
Supply 33 ohms 50 ohms
1.2V 0xE 0xE 0x5 0x5
GMACFG Pad Control Register

Offset: 0x900 │ Read/Write: R/W │ Reset: 0x00204040 (0b0000xxx00010x00001xxxxxx01xx00x0)
31:30 0x0 CFG2TMC_GMACFG_CAL_DRVUP_SLWF. Maps to MSB of DRVDN[18:17].
29:28 0x0 CFG2TMC_GMACFG_CAL_DRVDN_SLWR. Maps to MSB of DRVUP[24:23].
24:20 0x2 CFG2TMC_GMACFG_CAL_DRVUP. 1.8V 50 ohm driver for eMMC.
18:14 0x1 CFG2TMC_GMACFG_CAL_DRVDN. 1.8V 50 ohm driver for eMMC.
CFG2TMC_GMACFG_DRV_TYPE.
7:6 0x1 0x1: 33-50 ohm driver
0x0: 66-100 ohm driver
CFG2TMC_GMACFG_SCHMT_EN: Data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_GMACFG_HSM_EN: Data pins high speed mode enable. Software should set
this when I/O is running at greater than or equal to 100 MHz.
2 0x0
0 = DISABLE
1 = ENABLE
CFG2TMC_GMACFG_E_PREEMP:pre-emphasis enable
0 0x0 0 = DISABLE
1 = ENABLE
18.1.3.25 APB_MISC_GP_GMECFGPADCTRL_0
GMECFG Pad Control Register

Offset: 0x910 │ Read/Write: R/W │ Reset: 0xf0724000 (0b1111xxxx0111001001xxxxxxxxxx00xx)
31:30 0x3 CFG2TMC_GMECFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_GMECFG_CAL_DRVDN_SLWR
23:19 0xe CFG2TMC_GMECFG_CAL_DRVUP
18:14 0x9 CFG2TMC_GMECFG_CAL_DRVDN
CFG2TMC_GMECFG_SCHMT_EN: Data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_GMECFG_HSM_EN: Data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.26 APB_MISC_GP_GMFCFGPADCTRL_0
GMFCFG Pad Control Register

APB
31:30 0x3 CFG2TMC_GMFCFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_GMFCFG_CAL_DRVDN_SLWR
23:19 0xe CFG2TMC_GMFCFG_CAL_DRVUP
18:14 0x9 CFG2TMC_GMFCFG_CAL_DRVDN
CFG2TMC_GMFCFG_SCHMT_EN: Data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_GMFCFG_HSM_EN: Data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.27 APB_MISC_GP_GMGCFGPADCTRL_0
GMGCFG Pad Control Register

31:30 0x3 CFG2TMC_GMGCFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_GMGCFG_CAL_DRVDN_SLWR
23:19 0xe CFG2TMC_GMGCFG_CAL_DRVUP
18:14 0x9 CFG2TMC_GMGCFG_CAL_DRVDN
CFG2TMC_GMGCFG_SCHMT_EN: Data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_GMGCFG_HSM_EN: Data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.28 APB_MISC_GP_GMHCFGPADCTRL_0
GMHCFG Pad Control Register

Offset: 0x91c │ Read/Write: R/W │ Reset: 0xf0724000 (0b1111xxxx0111001001xxxxxxxxxx00xx)
31:30 0x3 CFG2TMC_GMHCFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_GMHCFG_CAL_DRVDN_SLWR
23:19 0xe CFG2TMC_GMHCFG_CAL_DRVUP
18:14 0x9 CFG2TMC_GMHCFG_CAL_DRVDN
CFG2TMC_GMHCFG_SCHMT_EN: Data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_GMHCFG_HSM_EN: Data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE

APB
18.1.3.29 APB_MISC_GP_OWRCFGPADCTRL_0
OWRCFG Pad Control Register

Offset: 0x920 │ Read/Write: R/W │ Reset: 0xc160000c (0b1100xxx10110xxx00000xxxxxxxx11xx)
31:30 0x3 CFG2TMC_OWRCFG_CAL_DRVUP_SLWF
29:28 0x0 CFG2TMC_OWRCFG_CAL_DRVDN_SLWR
24:20 0x16 CFG2TMC_OWRCFG_CAL_DRVUP
16:12 0x0 CFG2TMC_OWRCFG_CAL_DRVDN
CFG2TMC_OWRCFG_SCHMT_EN: Data pins Schmitt enable

3 0x1 0 = DISABLE
1 = ENABLE
CFG2TMC_OWRCFG_HSM_EN: Data pins high speed mode enable

2 0x1 0 = DISABLE
1 = ENABLE
18.1.3.30 APB_MISC_GP_UADCFGPADCTRL_0
UDACFG Pad Control Register

31:30 0x3 CFG2TMC_UDACFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_UDACFG_CAL_DRVDN_SLWR
24:20 0xe CFG2TMC_UDACFG_CAL_DRVUP
16:12 0x9 CFG2TMC_UDACFG_CAL_DRVDN
CFG2TMC_UDACFG_SCHMT_EN: Data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_UDACFG_HSM_EN: Data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.31 APB_MISC_GP_GPVCFGPADCTRL_0
GPV Pad Control Register

Offset: 0x928 | Read/Write: R/W | Reset: 0xf0e09000 (0b1111xxx01110xxx01001xxxxxxxx00xx)
31:30 0x3 CFG2TMC_GPVCFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_GPVCFG_CAL_DRVDN_SLWR
24:20 0xe CFG2TMC_GPVCFG_CAL_DRVUP
16:12 0x9 CFG2TMC_GPVCFG_CAL_DRVDN

APB
CFG2TMC_GPVCFG_SCHMT_EN:
3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_GPVCFG_HSM_EN:
2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.32 APB_MISC_GP_DEV3CFGPADCTRL_0
DEV3CFG Pad Control Register

31:30 0x3 CFG2TMC_DEV3CFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_DEV3CFG_CAL_DRVDN_SLWR
24:20 0xe CFG2TMC_DEV3CFG_CAL_DRVUP
16:12 0x9 CFG2TMC_DEV3CFG_CAL_DRVDN
CFG2TMC_DEV3CFG_SCHMT_EN: DEV3CFG data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_DEV3CFG_HSM_EN: DEV3CFG data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.33 APB_MISC_GP_CECCFGPADCTRL_0
CECCFG Pad Control Register

Offset: 0x938 │ Read/Write: R/W │ Reset: 0xf1612000 (0b1111xxx10110xxx10010xxxxxxxx00xx)
31:30 0x3 CFG2TMC_CECCFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_CECCFG_CAL_DRVDN_SLWR
24:20 0x16 CFG2TMC_CECCFG_CAL_DRVUP
16:12 0x12 CFG2TMC_CECCFG_CAL_DRVDN
CFG2TMC_CECCFG_SCHMT_EN: Data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
CFG2TMC_CECCFG_HSM_EN: Data pins high speed mode enable

2 0x0 0 = DISABLE
1 = ENABLE


APB

3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE

Offset: 0x998 │ Read/Write: R/W │ Reset: 0xf0503000 (0b1111xxx00101xxx00011xxxxxxxx00xx)
24:20 0x5 CFG2TMC_DAP5CFG_CAL_DRVUP

3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.36 APB_MISC_GP_USB_VBUS_EN_CFGPADCTRL_0
USB_VBUS_EN_CFG Pad Control Register

Offset: 0x99c │ Read/Write: R/W │ Reset: 0xf1612000 (0b1111xxx10110xxx10010xxxxxxxx00xx)
31:30 0x3 CFG2TMC_USB_VBUS_EN_CFG_CAL_DRVUP_SLWF
29:28 0x3 CFG2TMC_USB_VBUS_EN_CFG_CAL_DRVDN_SLWR
24:20 0x16 CFG2TMC_USB_VBUS_EN_CFG_CAL_DRVUP
16:12 0x12 CFG2TMC_USB_VBUS_EN_CFG_CAL_DRVDN
CFG2TMC_USB_VBUS_EN_CFG_SCHMT_EN: data pins Schmitt enable

3 0x0 0 = DISABLE
1 = ENABLE
2 0x0 CFG2TMC_USB_VBUS_EN_CFG_HSM_EN: Data pins high speed mode enable

APB

0 = DISABLE
1 = ENABLE

Offset: 0x9a8 │ Read/Write: R/W │ Reset: 0x0000000c (0bxx00xxxxxxxxxxx00000xxxxxxxx11xx)

3 0x1 0 = DISABLE
1 = ENABLE

2 0x1 0 = DISABLE
1 = ENABLE


3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE
18.1.3.39 APB_MISC_GP_HVCFG0PADCTRL_0
HVCFG0 Pad Control Register

Offset: 0x9b4 │ Read/Write: R/W │ Reset: 0x0000000c (0bxx00xxxxxxxxxxx00000xxxxxxxx11xx)
29:28 0x0 CFG2TMC_HVCFG0_CAL_DRVDN_SLWR
16:12 0x0 CFG2TMC_HVCFG0_CAL_DRVDN
3 0x1 CFG2TMC_HVCFG0_SCHMT_EN: HVCFG0 data pins Schmitt enable

0 = DISABLE

APB

1 = ENABLE
CFG2TMC_HVCFG0_HSM_EN: HVCFG0 data pins high speed mode enable

2 0x1 0 = DISABLE
1 = ENABLE

Offset: 0x9c4 │ Read/Write: R/W │ Reset: 0xc0e0000c (0b1100xxx01110xxx00000xxxxxxxx11xx)
31:30 0x3 CFG2TMC_SDIO4CFG_CAL_DRVUP_SLWF
29:28 0x0 CFG2TMC_SDIO4CFG_CAL_DRVDN_SLWR
24:20 0xe CFG2TMC_SDIO4CFG_CAL_DRVUP
16:12 0x0 CFG2TMC_SDIO4CFG_CAL_DRVDN

3 0x1 0 = DISABLE
1 = ENABLE
CFG2TMC_SDIO4CFG_HSM_EN: SDIO4CFG data pins high speed mode enable

2 0x1 0 = DISABLE
1 = ENABLE
Offset: 0x9c8 | Read/Write: R/W | Reset: 0xf0e09000 (0b1111x0001110x0001001xxxx00xx00xx)
7:6 0x0 CFG2TMC_AOCFG4_DRV_TYPE

3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE
18.1.4 DAC/DAP Registers
18.1.4.1 APB_MISC_DAS_DAP_CTRL_SEL_0
DAP Control Register


APB
Offset: 0xc00..0xc13 | Read/Write: R/W | Reset: 0x00000000 (0b000xxxxxxxxxxxxxxxxxxxxxxxx00000)
DAP_MS_SEL: This bit is programmed to put a particular DAP in either master or slave mode when two or
more DAPs are in bypass mode.
31 0x0
0 = SLAVE
1 = MASTER
DAP_SDATA1_TX_RX: Programs sdata1 in either tx or rx mode when two or more DAPs are in bypass
mode.
30 0x0
0 = TX
1 = RX
DAP_SDATA2_RX_TX: Programs sdata2 in either tx or rx mode when two or more DAPs are in bypass
mode.
29 0x0
0 = RX
1 = TX
DAP_CTRL_SEL: DAP selection bits to select one of the three DACs or one of the five DAPs.
0 = DAC1
1 = DAC2
2 = DAC3
4:0 0x0 16 = DAP1
17 = DAP2
18 = DAP3
19 = DAP4
20 = DAP5
18.1.4.2 APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0
DAC Input Data Selections

Offset: 0xc40..0xc4b | Read/Write: R/W | Reset: 0x00000000 (0b00000000xxxxxxxxxxxxxxxxxxxx0000)
DAC_SDATA2_SEL: These bits control the sdata2 input selection for DACs.
0 = DAP1
1 = DAP2
31:28 0x0
2 = DAP3
3 = DAP4
4 = DAP5
DAC_SDATA1_SEL: These bits control the sdata1 input selection for DACs.
0 = DAP1
1 = DAP2
27:24 0x0
2 = DAP3
3 = DAP4
4 = DAP5
DAC_CLK_SEL: These bits control the bit clock and fsync selection for DACs.
0 = DAP1
1 = DAP2
3:0 0x0
2 = DAP3
3 = DAP4
4 = DAP5

APB
18.1.5 AP Control Registers
Secure Registers
18.1.5.1 APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0
APB Slave Security Enable Register 0

These registers are used to enable and disable secure access of corresponding APB slaves. If set, the corresponding APB
slave is accessed only via secure transactions.
Offset: 0xc00 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxx00000x00000000000x000000x)
24 0x0 CEC_SECURITY_EN: CEC
23 0x0 ATOMICS_SECURITY_EN: Atomics
22 0x0 LA_SECURITY_EN: LA
21 0x0 HDA_SECURITY_EN: HDA
20 0x0 SATA_SECURITY_EN: SATA
18 0x0 OWR_SECURITY_EN: OWR
17 0x0 SNOR_SECURITY_EN: SNOR
16 0x0 KFUSE_SECURITY_EN: kfuse
15 0x0 FUSE_SECURITY_EN: Fuse
14 0x0 SE_SECURITY_EN: Security Engine
13 0x0 PMC_SECURITY_EN: PMC
12 0x0 KBC_SECURITY_EN: Reserved
11 0x0 RTC_SECURITY_EN: RTC
10 0x0 CSITE_SECURITY_EN: Core Site
9 0x0 MHS_SECURITY_EN: MIPI HSI
8 0x0 PWM_SECURITY_EN: PWFM
6 0x0 DTV_SECURITY_EN: DTV
5 0x0 VFIR_SECURITY_EN: VFIR
4 0x0 AUDIO_SECURITY_EN: Audio Cluster registers
3 0x0 PINMUX_AUX_SECURITY_EN: Pinmux aux registers
2 0x0 SATA_AUX_SECURITY_EN: SATA aux registers
1 0x0 MISC_REGS_SECURITY_EN: PP, SC1x pads and GP registers

Offset: 0xc04 | Read/Write: R/W | Reset: 0x00000000 (0b000000000000xxxx0000xxxx00xxxxxx)

APB
31 0x0 I2C6_SECURITY_EN: I2C6
30 0x0 DVC_SECURITY_EN: DVC - I2C5
25 0x0 SPI6_SECURITY_EN: SPI6
15 0x0 UART_D_SECURITY_EN: UARTD
14 0x0 UART_C_SECURITY_EN: UARTC
13 0x0 UART_B_SECURITY_EN: UARTB
12 0x0 UART_A_SECURITY_EN: UARTA
7 0x0 EMC_SECURITY_EN: EMC
6 0x0 MC_SECURITY_EN: MC

Offset: 0xc08 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxx000000000xxxx0000)
16 0x0 DVFS_SECURITY_EN: DVFS
15 0x0 MIPI_CAL_SECURITY_EN: MIPI cal
14 0x0 XUSB_PADCTL_SECURITY_EN: XUSB_PADCTL
13 0x0 XUSB_DEV_SECURITY_EN: XUSB_dev
12 0x0 XUSB_HOST_SECURITY_EN: XUSB_host
11 0x0 APB2JTAG_SECURITY_EN: APB2JTAG
10 0x0 SOC_THERM_SECURITY_EN: SOC_THERM
9 0x0 DP2_SECURITY_EN: DP2
8 0x0 DDS_SECURITY_EN: DDS
3 0x0 SDMMC4_SECURITY_EN: SDMMC4

APB
18.1.6 Pin Mux Selects

Refer to the Multi-Purpose I/O Pins and Pin Multiplexing (Pinmuxing) section in this document for details on the Pinmux_aux
registers.

18.2 APB DMA Controller

The APB DMA Controller is placed between the AHB Bus and the APB Bus and is a master on both buses.
The APB DMA Controller is used for block data transfers from a source location to the destination location. The source may be
DRAM or IRAM, and the destination location could be devices placed on APB Bus; or vice versa. DMA transfers are done
without any processor intervention other than register writes needed to program the parameters for a particular transfer, and
accesses needed to handle any interrupts.
The APB DMA Controller has 32 fully programmable channels, which can all transfer data concurrently.
18.2.1 Features
 DMA master for transfers between external/internal memory and peripheral devices on the APB Bus
 Two modes of operation: single transfer (once) or continuous
 Programmable burst sizes of 1, 4, or 8 words
 Maximum transfer size is 1 GB per channel, with the minimum size being one word
 Programmable APB bus widths of 8, 16, and 32 bits
 Separate AHB and APB start addresses
 Per channel trigger and flow control mechanism support
 Channel to channel trigger support, i.e., ability to link up channels to start at the end of another channel’s transfer,
allowing scattering/gathering of physical memory.
 Interrupt generation at the completion of channel transfer
 Interrupts per channel can be routed to the CPU or AVP
 Ability to hold processor until transfer is done
 Wrap mode supported for all channels in Once mode
 Ping-Pong feature supported in continuous mode
 Weighted round robin arbitration among channels at burst granularity. The weights for each channel can be set.
 Runs on APB clock. The APB clock generally runs at 1:2:2 or 1:2:3 clock ratios (sclk : hclk : pclk).
 APB DMA secure access feature allows configuration of secure and non-secure areas
 Address wraparound
 Global or individual channel pausing
18.2.2 Functionality
There are 32 channels in APB DMA. An APB DMA channel can transfer specified portions of data from an AHB address space
(can be iRAMs or DRAMs on the MC) to an APB address space. APB DMA follows a simple round robin arbitration scheme,
starting with channel 0.
Each channel can have independent burst transfer sizes programmed to one word, four words, or eight words.
Each DMA channel supports:
 Enable bit: one for each channel and one global enable bit.
 Interrupt Enable at the end of transfer with ability to mask or route to desired processor.
 Ability to hold off a processor. The Processor that writes into this bit will be held until transfer is completed.
 Direction bit to determine the direction of transfer--AHB to APB or APB to AHB.

APB DMA Controller
 Trigger and Flow selects. These are addition controls apart from channel enable, on which the transfer depends.
Trigger is used to start a channel on some event to start the transfer and flow is used to proceed with every new
burst transfer. These events are under either Software or Hardware control.
 Wrap feature wraps the LS nibble of the address back to ‘b0000 instead of incrementing to the next address if
the required number of words has been transmitted.
 APB bus width is configurable whereas the AHB bus width is fixed to 32 bits. The APB bus can be 8, 16, or 32
bits wide. For an AHB burst of 8 (burst is always with regard to words) and an APB bus size of 16, there are: 8
words transferred to the APB side, or 16 halfwords transferred.
 Double Buffering Mode makes the APB DMA Burst Address reset to AHB Base Address after every even (2nd,
4th, 6th, etc.) APB DMA Transfer. This mode is used only along with continuous mode (once bit 0).
 Separate AHB start address and APB start address.
 Ability to delay the burst rate with the help of a global counter which can be programmed to desired value, which
equals number of clocks delay required between each burst.
Figure 36: APB-DMA Block Diagram
AHB_BUS
AHB_MST-GIZMO
P
P
S
APB_DMA
B Interrupt
U
S
APB Bridge
APB_BUS
AUDIO SPI I2C UART ….
18.2.3 APB DMA Secure Access

APB DMA secure access is determined by the channel security enable bits in the APB DMA Security register. A particular
channel is secured by enabling the respective bit field . Whether through the CPU or APB DMA, accesses are blocked if the
SECURITY_EN bit of that region is enabled and the incoming access is non-secured.
The APBDMA_SECURITY_REG register contains the fields CH_<0-31>_SECURITY_EN, which indicate which channel is
secure. Write and read transactions to this register must always be secure.
If a channel is designated as secure, its registers must be written and read out in a secure manner. A non-secure write
attempt will not affect any of the secure channel’s registers and a non-secure read attempt will not generate any read data.
APB DMA Controller
If a channel is non-secure, its registers can be written or read either in a secure or a non-secure manner.
The following figure shows the security flow.
Figure 37: Security Flow Diagram
CPU COP
APB Slave Region Security Enable

XBAR Register
APB Slave I2C1
APB Bridge APB Slave I2C2
APB DMA
Secure Channel
Enable Register APB Slave
18.2.4 Programming Guidelines

Follow these guidelines when programming the APB DMA Controller:
The DMA transfer size should be in multiples of 4 bytes only.
The APB burst size and the FIFO trigger levels (in the modules) need to be programmed such that they do not lead to an
overflow/underflow of the FIFO in the APB client.
All registers of a channel should be programmed before the Channel Enable bit in the channel’s control register is set as
follows:
1. Program the AHB Starting Address and APB Starting address in the *AHB_PTR and *APB_PTR registers.
2. Program the required AHB BURST size, WRAP word window size, and AHB_DATA_SWAP (byte swapping) option in
the *AHB_SWQ register. The AHB BUS WIDTH is fixed to a 32-bit bus.
3. Program the required APB_BUS_WIDTH (as the peripheral), APB_DATA_SWAP (byte swapping) option, and WRAP
word window size in the *APB_SEQ register.
4. Program the number of words to be transferred in the *WCOUNT register.
5. Program the trigger in the CHANNEL_*_CSRE register.
6. Program the Interrupt option, Hold Processor option, DMA transfer direction, Transfer Mode, and Flow Enable in the
CHANNEL_*_CSR register.

APB DMA Controller
7. Program the Global Enable (GEN) bit in the APB_DMA Command Register. The GEN bit can also be programmed
before programming the channel registers.
8. Whenever the channel’s ENB bit is enabled, the DMA starts the data transfer.
9. Each channel’s status is observed by polling the APB_DMA Status Register. The number of words remaining to be
transferred will be in the WORD_TRANSFER register.
10. The Tx/Rx Flow/Trigger requestors are programmed in the APB-DMA Requestor Assignments Registers.
11. The busy (BSY) bit is set as soon as a DMA channel is enabled and is cleared after the transfer is completed.
Pausing and Ending of Data Transfers

 Clearing the Global Enable (GEN) bit causes the transfers that are in progress to be paused. Setting the GEN bit
resumes the transfers. A channel should never be disabled when the DMA is in global pause.
 Setting the CHANNEL_PAUSE bit in the CSRE register pauses data transfers on that channel. If the
CHANNEL_PAUSE bit of a particular channel is enabled during a data transfer, the data transfer is paused only on
this channel after the completion of the current burst. It can be resumed by setting this bit to 0.
 If a channel’s ENB is disabled independently while a transfer is in progress, the transfer ends after completing any
burst sequence that is in progress.
Interrupts
 Interrupts are write-1-to-clear, i.e., an interrupt bit is cleared when the value of write data corresponding to the bit
position of the interrupt bit is 1.
 An interrupt is generated when the last data is accepted by the AHB slave while writing on the AHB bus and once the
last data is placed on APB bus while reading from AHB bus. Note that completion of an AHB write does not
guarantee the data is written to DRAM. Refer to the AHB section of this document for how data is flushed from AHB
to the MC for this master.
Wraparound
Wraparound does not occur in between bursts; it is only after completing a burst that the address wraps around. Wraparound
is possible for both AHB and APB addresses.
The programming of the AHB wraparound needs to account for the address that is programmed in the AHB start address and
the burst size.
Usually, APB clients have a buffer of a fixed size. If the APB addresses are incremented after each word transfer, it is likely
that the address would cross the address limit of that client and go into the address range of another client. To avoid this, the
wrap feature is used. The default wraparound on the APB side is wrapping on 1 word. It prevents unnecessary address
switching on the APB.
With the address wrap feature enabled, the LS nibble of the address wraps back to 0 after completion of the programmed
number of words instead of incrementing the address.
Example: AHB burst size = 4 words, AHB start address = 0x4000_0000, AHB wrap on 32 words
In this case, the AHB addresses would be:
0x4000_0000, 0x4000_0004, 0x4000_0008, 0x4000_000C
……….
0x4000_0070, 0x4000_0074, 0x4000_0078, 0x4000_007C
When the address wrap feature is disabled, the addresses are incremented after each word transfer. This helps transfer data
from/to contiguous locations.

APB DMA Controller
Flow Control
When flow control is enabled, the number of words to be transferred must always be a multiple of the burst size/APB trigger
level. Without flow control the following are possible:
 If a burst of 8 is requested with an address that is not aligned to an 8-word boundary, the DMA will do a single burst
until it aligns itself to the 8-word boundary and then starts issuing burst requests.
 If a burst of 8 is requested and at any point of time the transfer size goes below 8, the DMA completes the remaining
transfers with a burst of 4 or 1, whichever is possible.
 If a burst of 4 is requested with an address that is not aligned to a 4-word boundary, the DMA transfers a single burst
until it aligns itself to the 4-word boundary.
 If a burst of 4 is requested and at any point of time the transfer size goes below 4, the DMA completes the remaining
transfers with a burst of 1.
Continuous Mode
In continuous mode, when a transfer is in progress, the APB and AHB addresses and the WCOUNT fields can be
reprogrammed in the middle of a data transfer. When the current transfer completes and a new transfer starts, it picks up the
newly programmed values. All new programming must complete before the channel completes the data transfer. To be sure
about this, CHANNEL_PAUSE can be used.
2x Mode
In 2x mode, the reprogramming can be done only on the second half of the data transfer.
18.2.5 APB DMA Registers

18.2.5.1 APBDMA_COMMAND_0
APB-DMA Command Register

The Global Enable (GEN) bit in the command register enables the APB DMA. Clearing this bit causes active DMA transfers to
be paused. Pending bus transactions (on going burst) will be completed, and no new transactions will be initiated. Setting this
bit again resumes the transfers. Disabling this bit will disable the channel register access.
Note that the power on reset value for the APB DMA Global Enable is 0. This bit must be written to 1 before any APB DMA
transactions can begin.
Offset: 0x0 │Read/Write: R/W │ Reset: 0x00000000 (0b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
GEN: Enables Global APB-DMA

31 0x0 0 = DISABLE
1 = ENABLE
18.2.5.2 APBDMA_STATUS_0
APB-DMA Status Register

The Busy bits in the Status Register indicate which (if any) of the APB DMA channels have active pending APB DMA
transfers. Note that Busy bits remain active in APB DMA transfers that are started in continuous (repetitive) mode until the
enable bit for the APB DMA channel is cleared to 0 (by the software). Read-only flags are set/cleared by hardware.

APB DMA Controller
BSY_31: DMA channel 31 status

31 X 0 = NOT_BUSY
1 = BUSY

30 X 0 = NOT_BUSY
1 = BUSY

29 X 0 = NOT_BUSY
1 = BUSY

28 X 0 = NOT_BUSY
1 = BUSY

27 X 0 = NOT_BUSY
1 = BUSY

26 X 0 = NOT_BUSY
1 = BUSY

25 X 0 = NOT_BUSY
1 = BUSY

24 X 0 = NOT_BUSY
1 = BUSY

23 X 0 = NOT_BUSY
1 = BUSY

22 X 0 = NOT_BUSY
1 = BUSY

21 X 0 = NOT_BUSY
1 = BUSY

20 X 0 = NOT_BUSY
1 = BUSY

19 X 0 = NOT_BUSY
1 = BUSY

18 X 0 = NOT_BUSY
1 = BUSY

17 X 0 = NOT_BUSY
1 = BUSY

16 X 0 = NOT_BUSY
1 = BUSY

15 X 0 = NOT_BUSY
1 = BUSY

APB DMA Controller

14 X 0 = NOT_BUSY
1 = BUSY

13 X 0 = NOT_BUSY
1 = BUSY

12 X 0 = NOT_BUSY
1 = BUSY

11 X 0 = NOT_BUSY
1 = BUSY

10 X 0 = NOT_BUSY
1 = BUSY

9 X 0 = NOT_BUSY
1 = BUSY

8 X 0 = NOT_BUSY
1 = BUSY

7 X 0 = NOT_BUSY
1 = BUSY

6 X 0 = NOT_BUSY
1 = BUSY

5 X 0 = NOT_BUSY
1 = BUSY

4 X 0 = NOT_BUSY
1 = BUSY

3 X 0 = NOT_BUSY
1 = BUSY

2 X 0 = NOT_BUSY
1 = BUSY

1 X 0 = NOT_BUSY
1 = BUSY

0 X 0 = NOT_BUSY
1 = BUSY

APB DMA Controller
18.2.5.3 APBDMA_CNTRL_REG_0
APB-DMA Counter Register

The APB DMA Counter is used to slow down the request rates on some APB DMA channels. The APB DMA Channel Counter
Enable register stores bits that configure which (if any) channel(s) should be throttled (bits [31:0] of channel counter enable
register correspond to the 32 APB DMA channels).
The APB DMA Counter initial/reload count value is programmed in the APB DMA Counter Register (bits[15:0]).The APB DMA
Counter is loaded with this initial/reload count value whenever the APB DMA Counter Register is written, and is re-loaded to
this saved initial count value on a burst complete (programmable). The APB DMA Counter value will decrement whenever an
APB DMA burst complete, and the current count value is non-zero, and any of the bits [31:16] are set.
15:0 0x0 COUNT_VALUE: DMA COUNT Value.
18.2.5.4 APBDMA_IRQ_STA_CPU_0
APB-DMA CPU IRQ STATUS Register

Gathers all the after-masking CPU directed IRQ status bits
CH31: Gathers all the after-masking CPU directed IRQ status bits from channel 31
0 = No IRQ pending
31 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE

APB DMA Controller
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
14 X CH14: Gathers all the after-masking CPU directed IRQ status bits from channel 14
0 = No IRQ pending

APB DMA Controller

1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
9 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
8 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
7 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
6 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
5 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
4 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
3 X
1 = IRQ pending
0 = DISABLE

APB DMA Controller

1 = ENABLE
0 = No IRQ pending
2 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
1 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
18.2.5.5 APBDMA_IRQ_STA_COP_0
APB-DMA COP IRQ STATUS Register

Gathers all the after-masking COP directed IRQ status bits
CH31: Gathers all the after-masking COP directed IRQ status bits from channel 31
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE

APB DMA Controller
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
14 X CH14: Gathers all the after-masking COP directed IRQ status bits from channel 14
0 = No IRQ pending

APB DMA Controller

1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
9 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
8 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
7 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
6 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
5 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
4 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
3 X
1 = IRQ pending
0 = DISABLE

APB DMA Controller

1 = ENABLE
0 = No IRQ pending
2 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
1 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
0 = No IRQ pending
0 X 1 = IRQ pending
0 = DISABLE
1 = ENABLE
18.2.5.6 APBDMA_IRQ_MASK_0
APB-DMA IRQ MASK Register

Allows the IRQ to propagate when enabled, this is the ANDed result of set and clear.
Offset: 0x1c │ Read/Write: RO │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
CH31: Each bit allows the associated channel31 IRQ to propagate when '1'
31 X 0 = DISABLE
1 = ENABLE
30 X 0 = DISABLE
1 = ENABLE
29 X 0 = DISABLE
1 = ENABLE
28 X 0 = DISABLE
1 = ENABLE
27 X 0 = DISABLE
1 = ENABLE
26 X 0 = DISABLE
1 = ENABLE
25 X 0 = DISABLE
1 = ENABLE
24 X 0 = DISABLE
1 = ENABLE
23 X 0 = DISABLE
1 = ENABLE
22 X CH22: Each bit allows the associated channel22 IRQ to propagate when '1'
0 = DISABLE

APB DMA Controller

1 = ENABLE
21 X 0 = DISABLE
1 = ENABLE
20 X 0 = DISABLE
1 = ENABLE
19 X 0 = DISABLE
1 = ENABLE
18 X 0 = DISABLE
1 = ENABLE
17 X 0 = DISABLE
1 = ENABLE
16 X 0 = DISABLE
1 = ENABLE
15 X 0 = DISABLE
1 = ENABLE
14 X 0 = DISABLE
1 = ENABLE
13 X 0 = DISABLE
1 = ENABLE
12 X 0 = DISABLE
1 = ENABLE
11 X 0 = DISABLE
1 = ENABLE
10 X 0 = DISABLE
1 = ENABLE
9 X 0 = DISABLE
1 = ENABLE
8 X 0 = DISABLE
1 = ENABLE
7 X 0 = DISABLE
1 = ENABLE
6 X 0 = DISABLE
1 = ENABLE
5 X 0 = DISABLE
1 = ENABLE
4 X CH4: Each bit allows the associated channel4 IRQ to propagate when '1'
0 = DISABLE

APB DMA Controller

1 = ENABLE
3 X 0 = DISABLE
1 = ENABLE
2 X 0 = DISABLE
1 = ENABLE
1 X 0 = DISABLE
1 = ENABLE
0 X 0 = DISABLE
1 = ENABLE
18.2.5.7 APBDMA_IRQ_MASK_SET_0
APB-DMA IRQ MASK SET Register

Offset: 0x20 │ Read/Write: WO │ Reset: 0x00000000 (0b00000000000000000000000000000000)
CH31: Sets the Mask Register

0 = Disable the IRQ
31 0x0 1 = Enable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

APB DMA Controller

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE
13 0x0 CH13: Sets the Mask Register

0 = Disable the IRQ

APB DMA Controller

1 = Enable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
2 0x0
1 = Enable the IRQ
0 = DISABLE

APB DMA Controller

1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE

0 = Disable the IRQ
0 = DISABLE
1 = ENABLE
18.2.5.8 APBDMA_IRQ_MASK_CLR_0
APB-DMA IRQ MASK CLEAR Register

Offset: 0x24 │ Read/Write: WO │ Reset: 0x00000000 (0b00000000000000000000000000000000)
CH31: Clears the Mask Register

31 0x0 0 = DISABLE
1 = ENABLE

30 0x0 0 = DISABLE
1 = ENABLE

29 0x0 0 = DISABLE
1 = ENABLE

28 0x0 0 = DISABLE
1 = ENABLE

27 0x0 0 = DISABLE
1 = ENABLE

26 0x0 0 = DISABLE
1 = ENABLE

25 0x0 0 = DISABLE
1 = ENABLE

24 0x0 0 = DISABLE
1 = ENABLE

23 0x0 0 = DISABLE
1 = ENABLE

22 0x0 0 = DISABLE
1 = ENABLE

21 0x0 0 = DISABLE
1 = ENABLE

APB DMA Controller

20 0x0 0 = DISABLE
1 = ENABLE

19 0x0 0 = DISABLE
1 = ENABLE

18 0x0 0 = DISABLE
1 = ENABLE

17 0x0 0 = DISABLE
1 = ENABLE

16 0x0 0 = DISABLE
1 = ENABLE

15 0x0 0 = DISABLE
1 = ENABLE

14 0x0 0 = DISABLE
1 = ENABLE

13 0x0 0 = DISABLE
1 = ENABLE

12 0x0 0 = DISABLE
1 = ENABLE

11 0x0 0 = DISABLE
1 = ENABLE

10 0x0 0 = DISABLE
1 = ENABLE

9 0x0 0 = DISABLE
1 = ENABLE

8 0x0 0 = DISABLE
1 = ENABLE

7 0x0 0 = DISABLE
1 = ENABLE

6 0x0 0 = DISABLE
1 = ENABLE

5 0x0 0 = DISABLE
1 = ENABLE

4 0x0 0 = DISABLE
1 = ENABLE

3 0x0 0 = DISABLE
1 = ENABLE

APB DMA Controller

2 0x0 0 = DISABLE
1 = ENABLE

1 0x0 0 = DISABLE
1 = ENABLE

0 0x0 0 = DISABLE
1 = ENABLE
18.2.5.9 APBDMA_TRIG_REG_0
APB-DMA Trigger Register

Offset: 0x28 │ Read/Write: RO │ Reset: 0x00000XXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
TMR2: Trigger select from Timer (Hardware initiated DMA request)

8 X 0 = NOT_ACTIVE
1 = ACTIVE
TMR1: Trigger select from Timer (Hardware initiated DMA request)

7 X 0 = NOT_ACTIVE
1 = ACTIVE
XRQ_B: XRQ.B (GPIOB) (Hardware initiated DMA request)

6 X 0 = NOT_ACTIVE
1 = ACTIVE
XRQ_A: XRQ.A (GPIOA) (Hardware initiated DMA request)

5 X 0 = NOT_ACTIVE
1 = ACTIVE
SMP_27: Semaphore requests software-initiated DMA request

4 X 0 = NOT_ACTIVE
1 = ACTIVE

3 X 0 = NOT_ACTIVE
1 = ACTIVE

2 X 0 = NOT_ACTIVE
1 = ACTIVE

1 X 0 = NOT_ACTIVE
1 = ACTIVE
18.2.5.10 APBDMA_CHANNEL_TRIG_REG_0
APB-DMA Channel Trigger Registers

Offset: 0x2c │ Read/Write: RO │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
APB_31: EOC-31 Initiated DMA Request after transfer completion

31 X 0 = NOT_ACTIVE
1 = ACTIVE

APB DMA Controller

30 X 0 = NOT_ACTIVE
1 = ACTIVE

29 X 0 = NOT_ACTIVE
1 = ACTIVE

28 X 0 = NOT_ACTIVE
1 = ACTIVE

27 X 0 = NOT_ACTIVE
1 = ACTIVE

26 X 0 = NOT_ACTIVE
1 = ACTIVE

25 X 0 = NOT_ACTIVE
1 = ACTIVE

24 X 0 = NOT_ACTIVE
1 = ACTIVE

23 X 0 = NOT_ACTIVE
1 = ACTIVE

22 X 0 = NOT_ACTIVE
1 = ACTIVE

21 X 0 = NOT_ACTIVE
1 = ACTIVE

20 X 0 = NOT_ACTIVE
1 = ACTIVE

19 X 0 = NOT_ACTIVE
1 = ACTIVE

18 X 0 = NOT_ACTIVE
1 = ACTIVE

17 X 0 = NOT_ACTIVE
1 = ACTIVE

16 X 0 = NOT_ACTIVE
1 = ACTIVE

15 X 0 = NOT_ACTIVE
1 = ACTIVE

14 X 0 = NOT_ACTIVE
1 = ACTIVE

13 X 0 = NOT_ACTIVE
1 = ACTIVE

APB DMA Controller

12 X 0 = NOT_ACTIVE
1 = ACTIVE

11 X 0 = NOT_ACTIVE
1 = ACTIVE

10 X 0 = NOT_ACTIVE
1 = ACTIVE

9 X 0 = NOT_ACTIVE
1 = ACTIVE

8 X 0 = NOT_ACTIVE
1 = ACTIVE

7 X 0 = NOT_ACTIVE
1 = ACTIVE

6 X 0 = NOT_ACTIVE
1 = ACTIVE

5 X 0 = NOT_ACTIVE
1 = ACTIVE

4 X 0 = NOT_ACTIVE
1 = ACTIVE

3 X 0 = NOT_ACTIVE
1 = ACTIVE

2 X 0 = NOT_ACTIVE
1 = ACTIVE

1 X 0 = NOT_ACTIVE
1 = ACTIVE

0 X 0 = NOT_ACTIVE
1 = ACTIVE
18.2.5.11 APBDMA_DMA_STATUS_0
APB-DMA Interrupt Status

ISE_EOC_31: DMA Channel31 Interrupt Status

31 X 0 = NOT_ACTIVE
1 = ACTIVE

30 X 0 = NOT_ACTIVE
1 = ACTIVE

APB DMA Controller

29 X 0 = NOT_ACTIVE
1 = ACTIVE

28 X 0 = NOT_ACTIVE
1 = ACTIVE

27 X 0 = NOT_ACTIVE
1 = ACTIVE

26 X 0 = NOT_ACTIVE
1 = ACTIVE

25 X 0 = NOT_ACTIVE
1 = ACTIVE

24 X 0 = NOT_ACTIVE
1 = ACTIVE

23 X 0 = NOT_ACTIVE
1 = ACTIVE

22 X 0 = NOT_ACTIVE
1 = ACTIVE

21 X 0 = NOT_ACTIVE
1 = ACTIVE

20 X 0 = NOT_ACTIVE
1 = ACTIVE

19 X 0 = NOT_ACTIVE
1 = ACTIVE

18 X 0 = NOT_ACTIVE
1 = ACTIVE

17 X 0 = NOT_ACTIVE
1 = ACTIVE

16 X 0 = NOT_ACTIVE
1 = ACTIVE

15 X 0 = NOT_ACTIVE
1 = ACTIVE

14 X 0 = NOT_ACTIVE
1 = ACTIVE

13 X 0 = NOT_ACTIVE
1 = ACTIVE

12 X 0 = NOT_ACTIVE
1 = ACTIVE

APB DMA Controller

11 X 0 = NOT_ACTIVE
1 = ACTIVE

10 X 0 = NOT_ACTIVE
1 = ACTIVE

9 X 0 = NOT_ACTIVE
1 = ACTIVE

8 X 0 = NOT_ACTIVE
1 = ACTIVE

7 X 0 = NOT_ACTIVE
1 = ACTIVE

6 X 0 = NOT_ACTIVE
1 = ACTIVE

5 X 0 = NOT_ACTIVE
1 = ACTIVE

4 X 0 = NOT_ACTIVE
1 = ACTIVE

3 X 0 = NOT_ACTIVE
1 = ACTIVE

2 X 0 = NOT_ACTIVE
1 = ACTIVE

1 X 0 = NOT_ACTIVE
1 = ACTIVE

0 X 0 = NOT_ACTIVE
1 = ACTIVE
18.2.5.12 APBDMA_CHANNEL_EN_REG_0
APB-DMA Channel Counter Enable Registers

CH31_CNT_EN: Enable the Channel31 count

31 0x0 0 = DISABLE
1 = ENABLE

30 0x0 0 = DISABLE
1 = ENABLE

29 0x0 0 = DISABLE
1 = ENABLE

APB DMA Controller

28 0x0 0 = DISABLE
1 = ENABLE

27 0x0 0 = DISABLE
1 = ENABLE

26 0x0 0 = DISABLE
1 = ENABLE

25 0x0 0 = DISABLE
1 = ENABLE

24 0x0 0 = DISABLE
1 = ENABLE

23 0x0 0 = DISABLE
1 = ENABLE

22 0x0 0 = DISABLE
1 = ENABLE

21 0x0 0 = DISABLE
1 = ENABLE

20 0x0 0 = DISABLE
1 = ENABLE

19 0x0 0 = DISABLE
1 = ENABLE

18 0x0 0 = DISABLE
1 = ENABLE

17 0x0 0 = DISABLE
1 = ENABLE

16 0x0 0 = DISABLE
1 = ENABLE

15 0x0 0 = DISABLE
1 = ENABLE

14 0x0 0 = DISABLE
1 = ENABLE

13 0x0 0 = DISABLE
1 = ENABLE

12 0x0 0 = DISABLE
1 = ENABLE

11 0x0 0 = DISABLE
1 = ENABLE

APB DMA Controller

10 0x0 0 = DISABLE
1 = ENABLE

9 0x0 0 = DISABLE
1 = ENABLE

8 0x0 0 = DISABLE
1 = ENABLE

7 0x0 0 = DISABLE
1 = ENABLE

6 0x0 0 = DISABLE
1 = ENABLE

5 0x0 0 = DISABLE
1 = ENABLE

4 0x0 0 = DISABLE
1 = ENABLE

3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE

1 0x0 0 = DISABLE
1 = ENABLE

0 0x0 0 = DISABLE
1 = ENABLE
18.2.5.13 APBDMA_SECURITY_REG_0
Security enables for each channel.
Secure: TrustZone Protected
CH_31_SECURITY_EN: Enables secure channel

31 0x0 0 = DISABLE
1 = ENABLE

30 0x0 0 = DISABLE
1 = ENABLE

29 0x0 0 = DISABLE
1 = ENABLE

28 0x0 0 = DISABLE
1 = ENABLE

APB DMA Controller

27 0x0 0 = DISABLE
1 = ENABLE

26 0x0 0 = DISABLE
1 = ENABLE

25 0x0 0 = DISABLE
1 = ENABLE

24 0x0 0 = DISABLE
1 = ENABLE

23 0x0 0 = DISABLE
1 = ENABLE

22 0x0 0 = DISABLE
1 = ENABLE

21 0x0 0 = DISABLE
1 = ENABLE

20 0x0 0 = DISABLE
1 = ENABLE

19 0x0 0 = DISABLE
1 = ENABLE

18 0x0 0 = DISABLE
1 = ENABLE

17 0x0 0 = DISABLE
1 = ENABLE

16 0x0 0 = DISABLE
1 = ENABLE

15 0x0 0 = DISABLE
1 = ENABLE

14 0x0 0 = DISABLE
1 = ENABLE

13 0x0 0 = DISABLE
1 = ENABLE

12 0x0 0 = DISABLE
1 = ENABLE

11 0x0 0 = DISABLE
1 = ENABLE

10 0x0 0 = DISABLE
1 = ENABLE

APB DMA Controller

9 0x0 0 = DISABLE
1 = ENABLE

8 0x0 0 = DISABLE
1 = ENABLE

7 0x0 0 = DISABLE
1 = ENABLE

6 0x0 0 = DISABLE
1 = ENABLE

5 0x0 0 = DISABLE
1 = ENABLE

4 0x0 0 = DISABLE
1 = ENABLE

3 0x0 0 = DISABLE
1 = ENABLE

2 0x0 0 = DISABLE
1 = ENABLE

1 0x0 0 = DISABLE
1 = ENABLE

0 0x0 0 = DISABLE
1 = ENABLE
18.2.5.14 APBDMA_CHANNEL_SWID_0
SWID[0] for each APBDMA channel. Supports secure writes.
31 0x0 CH_31_SWID:SWID for Channel 31

APB DMA Controller
18.2.5.15 APBDMA_CHAN_WT_REG0_0
Channel weights for weighted-round-robin arbitration
31:28 0x1 WT_CH31: Weight of channel

APB DMA Controller
18.2.5.19 APBDMA_CHANNEL_SWID1_0
SWID[1] indicating secure ASID. Supports secure writes.

APB DMA Controller
31 0x0 CH_31_SWID_1: SWID for Channel 31
18.2.6 APB DMA Channel Registers

Each of the 32 APB DMA channels has its own set of 10 APB DMA registers. Each channel has 64 bytes of address space.
This subsection defines one complete set of APB DMA channel registers. The register spaces per APB DMA channel are
listed in the table below.

APB DMA Controller
Table 64: APB DMA Channel Register Mapping
Register Space Channel Registers
0x0 – 0x3f Channel 0 APB DMA Channel Registers
0x80 – 0xbf Channel 2 APB DMA Channel Registers
0xc0 – 0xff Channel 3 APB DMA Channel Registers
0x180 – 0x1bf Channel 6 APB DMA Channel Registers
0x1c0 – 0x1ff Channel 7 APB DMA Channel Registers

APB DMA Controller
18.2.6.1 APBDMACHAN_CHANNEL_n_CSR_0
APB-DMA-n Control Register

There are 32 APB DMA Channel Control Registers, one per channel (n = 0 through 31).
Writing a 1 to bit [31] of an APB DMA Channel Control Register will initiate the APB DMA transfer. Because this action will
depend on some values programmed in the other registers, it is recommended that the registers in the address space in the
required APB DMA channel be programmed before writing into control register.
In "Once" mode, the channel is disabled after the APB DMA transfer has completed. When the channel's transfer completes,
an interrupt will be sent if the IE.EOC bit is set. If the transfer requires a trigger or flow, then the corresponding trigger selected
by the "TRIG_SEL" or "REQ_SEL" field must become active respectively before the channel can starts its transfer. If both
Trigger and Flow bits are set, both conditions must be met before the channel starts each DMA burst.
Offset: 0x0+ (n * 0x40) │ Read/Write: R/W │ Reset: 0x00000000 (0b00000xxxxx000000xxxxxxxxxxxxxxxx)
ENB: Enables DMA channel transfer

31 0x0 0 = DISABLE
1 = ENABLE
IE_EOC: Generates interrupts when DMA block transfer completes

30 0x0 0 = DISABLE
1 = ENABLE
HOLD: Holds this Processor until DMA block transfer completes

29 0x0 0 = DISABLE
1 = ENABLE
DIR: DMA Transfer Direction.

0 = APB read to AHB write
28 0x0 1 = AHB read to APB write.
0 = AHB_WRITE
1 = AHB_READ
ONCE: Run Once or Run Multiple Mode (Allow Retriggering of this Channel).
0 = Run for Multiple Block Transfers
27 0x0 1 = Run for One Block Transfer.
0 = MULTIPLE_BLOCK
1 = SINGLE_BLOCK
FLOW: Flow Control Enable (Synchronize Burst Transfers).

0 = Independent of DRQ request
21 0x0 1 = Link to DRQ source.
0 = DISABLE
1 = ENABLE
REQ_SEL:
0 = CNTR_REQ
1 = APBIF_CH0
2 = APBIF_CH1
3 = APBIF_CH2
4 = APBIF_CH3
5 = HSI
6 = APBIF_CH4
7 = APBIF_CH5
20:16 0x0 8 = UART_A
9 = UART_B
10 = UART_C
11 = DTV
12 = APBIF_CH6
13 = APBIF_CH7
14 = APBIF_CH8
15 = SL2B1
16 = SL2B2
17 = SL2B3

APB DMA Controller

18 = SL2B4
19 = UART_D
20 = Reserved
21 = I2C
22 = I2C2
23 = I2C3
24 = DVC_I2C
25 = OWR
26 = I2C4
27 = SL2B5
28 = SL2B6
29 = APBIF_CH9
30 = I2C6
31 = NA31
18.2.6.2 APBDMACHAN_CHANNEL_n_STA_0
APB-DMA-n Status Register

There are 32 APB DMA Status Registers, one per channel (n = 0 through 31).
Offset: 0x4 + (n * 0x40) │ Read/Write: R/W │ Reset: 0xXX000000 (0bx0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
BSY: Indicates whether DMA Channel Status is active or not

0 = Inactive
31 RO X 1 = Active
0 = WAIT
1 = ACTIVE
ISE_EOC: Write '1' to clear the flag

30 RW 0x0 0 = NO_INTR
1 = INTR
HALT: Holding Status of Processor

29 RO X 0 = NO_HALT
1 = HALT
PING_PONG_STA:
• If dir = AHB_WRITE:
0 - Ping buffer transfer completed; 1 - Pong buffer transfer completed.
28 RO X • If dir = AHB_READ:
0 - Pong buffer transfer completed ; 1 - Ping buffer transfer completed ;
0 = PING_INTR_STA
1 = PONG_INTR_STA
DMA_ACTIVITY: Indicates current DMA channel is transferring data

27 RO X 0 = IDLE
1 = BUSY
26 RO X CHANNEL_PAUSE: Indicates the status of channel pause.
18.2.6.3 APBDMACHAN_CHANNEL_n_DMA_BYTE_STA_0
APB-DMA-n DMA Byte Status Register

There are 32 APB DMA Byte Status Registers, one per channel (n = 0 through 31).
Offset: 0x8+ (n * 0x40) │ Read/Write: RO │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:0 X DMA_COUNT: Indicates the actual DMA Data Transfer Count in bytes

APB DMA Controller
18.2.6.4 APBDMACHAN_CHANNEL_n_CSRE_0
APB-DMA-n Control-Extended Register

There are 32 APB DMA Control Extended Registers, one per channel (n = 0 through 31).
Offset: 0xc+ (n * 0x40) │ Read/Write: R/W │ Reset: 0x00000000 (0b0xxxxxxxxxxx000000xxxxxxxxxxxxxx)
31 0x0 CHANNEL_PAUSE: When enabled, pauses data transfers on the channel

0 = RESUME
1 = PAUSE
19:14 0x0 TRIG_SEL: Enable on Non-Zero Value

0 = NA1
1 = SMP24
2 = SMP25
3 = SMP26
4 = SMP27
5 = XRQ_A
6 = XRQ_B
7 = TMR1
8 = TMR2
9 = APB_0
10 = APB_1
11 = APB_2
12 = APB_3
13 = APB_4
14 = APB_5
15 = APB_6
16 = APB_7
17 = APB_8
18 = APB_9
19 = APB_10
20 = APB_11
21 = APB_12
22 = APB_13
23 = APB_14
24 = APB_15
25 = APB_16
26 = APB_17
27 = APB_18
28 = APB_19
29 = APB_20
30 = APB_21
31 = APB_22
32 = APB_23
33 = APB_24
34 = APB_25
35 = APB_26
36 = APB_27
37 = APB_28
38 = APB_29
39 = APB_30
40 = APB_31
18.2.6.5 APBDMACHAN_CHANNEL_n_AHB_PTR_0
APB-DMA-n AHB Starting Address Pointer Register

There are 32 APB Starting Address Pointer Registers, one per channel (n = 0 through 31).
Offset: 0x10 + (n * 0x40) │ Read/Write: R/W │ Reset: 0x00000000 (0b000000000000000000000000000000xx)
31:2 0x0 AHB_BASE: APB-DMA Starting Address for AHB Bus: Software writes to modify

APB DMA Controller
18.2.6.6 APBDMACHAN_CHANNEL_n_AHB_SEQ_0
APB-DMA-n AHB Address Sequencer Register

There are 32 APB DMA AHB Address Sequencer Registers, one per channel (n = 0 through 31).
Offset: 0x14 + (x * 0x40) │ Read/Write: R/W │ Reset: 0x26000000 (0b00100110xxxx0000xxxxxxxxxxxxxxxx)
INTR_ENB: 0 = Send interrupt to COP

31 0x0 1 = CPU
0 = COP
AHB_BUS_WIDTH: AHB Bus Width.

0 = 8-bit bus (RSVD).
1 = 16-bit bus (RSVD).
2 = 32-bit bus (default).
3 = 64 bit-Bus (RSVD).
4 = 128-bit Bus (RSVD)
30:28 0x2
0 = BUS_WIDTH_8
1 = BUS_WIDTH_16
2 = BUS_WIDTH_32
3 = BUS_WIDTH_64
4 = BUS_WIDTH_128
AHB_DATA_SWAP: When enabled, the data going to AHB gets swapped as [31:0] -->
{[7:0], [15:8], [23:16], [31:24] }.
27 0x0
0 = DISABLE
1 = ENABLE
AHB_BURST: AHB Burst Size DMA Burst Length (encoded).

4 = 1 Word (1x32bits).
5 = 4 Words (4x32 bits).
6 = 8 Words (8x32bits), default
26:24 0x6
DBL_BUF: 2X Double Buffering Mode (for Run-Multiple Mode with No Wrap Operations).
1 = Reload Base Address for 2X blocks (reload every other time).
0 = Reload Base Address for 1X blocks (default) (reload each time)
19 0x0
0 = RELOAD_FOR_1X_BLOCKS
1 = RELOAD_FOR_2X_BLOCKS
WRAP: AHB Address Wrap: AHB Address wrap-around window. 0=No Wrap (default).
5=Wrap on 512 word window. 1=Wrap on 32 word window. 6=Wrap on 1024 word window.
2=Wrap on 64 word window. 7=Wrap on 2048 word window. 3=Wrap on 128 word window.
4=Wrap on 256 word window
0 = NO_WRAP
1 = WRAP_0N_32WORDS
18:16 0x0
2 = WRAP_ON_64WORDS
3 = WRAP_ON_128WORDS

APB DMA Controller
18.2.6.7 APBDMACHAN_CHANNEL_n_APB_PTR_0
APB-DMA-n APB Starting Address Pointer Register

There are 32 APB DMA APB Starting Address Pointer Registers, one per channel (n = 0 through 31).
Offset: 0x18 + (n * 0x40) │ Read/Write: R/W │ Reset: 0x00000000 (0b000000000000000000000000000000xx)
31:2 0x0 APB_BASE: APB-DMA Starting address for APB Bus
18.2.6.8 APBDMACHAN_CHANNEL_n_APB_SEQ_0
APB-DMA-n APB Address Sequencer Assignments

There are 32 APB DMA APB Address Sequencer Registers, one per channel (n = 0 through 31).
Offset: 0x1c + (n * 0x40) │ Read/Write: R/W │ Reset: 0x20010000 (0bx0100xxxxxxxx001xxxxxxxxxxxxxxxx)
APB_BUS_WIDTH:
0 = 8-bit bus.
1 = 16-bit bus.
2 = 32-bit bus (default)
3 = 64-bit bus. (RSVD).
4 = 128-bit bus (RSVD)
30:28 0x2
0 = BUS_WIDTH_8
1 = BUS_WIDTH_16
2 = BUS_WIDTH_32
3 = BUS_WIDTH_64
4 = BUS_WIDTH_128
APB_DATA_SWAP: When enabled, the data going to the APB gets swapped as [31:0] -->
{[7:0], [15:8], [23:16], [31:24] }.
27 0x0
0 = DISABLE
1 = ENABLE
APB_ADDR_WRAP: APB Address Wrap-around Window. 0 = No Wrap. 1 = Wrap on 1

Word Window (default). 2 = Wrap on 2 Word Window. 3 = Wrap on 4 Word Window. 4 =
Wrap on 8 Word Window. 5 = Wrap on 16 Word Window. 6 = Wrap on 32 Word Window. 7
= Wrap on 64 Word Windows (rsvd).
0 = NO_WRAP
1 = WRAP_0N_1WORDS
18:16 0x1
2 = WRAP_ON_2WORDS
3 = WRAP_ON_4WORDS
4 = WRAP_ON_8WORDS
5 = WRAP_ON_16WORDS
6 = WRAP_ON_32WORDS
7 = WRAP_ON_64WORDS
18.2.6.9 APBDMACHAN_CHANNEL_n_WCOUNT_0
APB-DMA-n Word Count Register

There are 32 APB DMA Word Count Registers, one per channel (n = 0 through 31).
Offset: 0x20 + (n * 0x40) │ Read/Write: R/W │ Reset: 0x00000000 (0bxx0000000000000000000000000000xx)
29:2 0x0 WCOUNT: Number of 32-bit word cycles.

APB DMA Controller
18.2.6.10 APBDMACHAN_CHANNEL_n_WORD_TRANSFER_0
APB-DMA-n Word Transfer Register

There are 32 APB DMA Word Transfer Registers, one per channel (n = 0 through 31).
Offset: 0x24 + (n * 0x40) │ Read/Write: RO │ Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
29:2 X COUNT: APB-Current 32-bit Word Cycles. Flags set/cleared by hardware.

APB DMA Controller

19.0 USB COMPLEX

®
Note: The ULPI and XUSB device mode functionalities described in this section have been deprecated from Tegra K1
devices, and are not supported by NVIDIA.
19.1 USB Overview

The Tegra K1 device has three USB 2.0 (EHCI) controllers (named USB_OTG, USB2, and USB3) and one USB 3.0 (xHCI)
controller (named XUSB), controlling a total of five exposed ports shared among them (named UTMIP, HSIC0, UTMIP1,
HSIC1, and UTMIP2). The following diagram shows the relationship between the different USB controllers and interfaces.
Note that some USB ports are shared between the USB 2.0 and USB 3.0 controllers.
Figure 38: Tegra K1 USB Controllers and Interfaces
TEGRA PCB
PLLE PLLU
USB connector
SS
(SS0)
100 MHz
USB connector
USB 3.0 SS
Controller (SS1)
(XUSB) 100 MHz
USB connector
UTMIP
USB 2.0 (USB0)
Controller #1 12 MHz
(USB_OTG)
12 MHz USB connector
UTMIP1
(USB1)
USB 2.0
Controller #2 480 MHz
(USB2) UHSIC HSIC
(HSIC0) Peripheral/Host
12 MHz
USB connector
UTMIP2
(USB2)
USB 2.0
Controller #3
(USB3) 480 MHz
UHSIC1 HSIC
(HSIC1) Peripheral/Host

USB Complex
Below is a summary of the key components in the USB complex:
§ USB_OTG and UTMIP: This is the primary USB port that supports OTG. USB recovery is also supported on this
interface.
§ USB2 and UHSIC: This interface allows connection of an HSIC peripheral/host on the PCB board.
§ USB2 and UTMIP1: This interface allows an additional USB port. It supports host mode of operation.
§ USB3 and UHSIC1: This interface allows connection of an HSIC peripheral/host on the PCB board.
§ USB3 and UTMIP2: This interface allows an additional USB port. It supports host mode of operation.
§ XUSB and UTMIP2. XUSB can support multiple interfaces at the same time.
§ XUSB and UTMIP1. XUSB can support multiple interfaces at the same time.
§ XUSB and UTMIP. XUSB can support multiple interfaces at the same time.
§ XUSB and SS. XUSB can support multiple interfaces at the same time.
On power-on-reset, USB2 and USB3 default to UTMI mode.
USB_OTG supports 16 bidirectional endpoints in device mode, where USB2 and USB3 should never be advised or
programmed to support device mode. Endpoint 0 of USB_OTG is always a bidirectional control endpoint. All other endpoints
can be programmed as one of Bulk, Interrupt, Isochronous, or Control type in either direction. Control endpoints are always
bidirectional and hence to program an endpoint as control type, both IN and OUT directions need to be programmed to control
type. Conversely, if an endpoint has either IN or OUT direction programmed to be non-control type, the other direction also
needs to be programmed to be non-control type. The maximum packet size supported on any endpoint is 1024 bytes in high-
speed mode, for both device and host modes.
19.2 USB 2.0 Controllers and Interfaces

The USB 2.0 controllers in the Tegra K1 mobile processors provide mechanisms for the processor to communicate with a PC
as a peripheral or to communicate with USB 2.0 peripherals, such as keyboards, mouse devices, cameras, or storage devices,
as a host using regular USB 2.0 ports. The USB 2.0 controllers also provide mechanisms for Tegra K1 devices to
communicate with an on-board baseband controller with HSIC or regular UTMIP interfaces. Each Tegra K1 device provides
three USB 2.0 controllers with five USB interfaces: three regular USB ports and two HSICs (see Figure 38).
The Tegra K1 device supports peripheral functionalities with USB 2.0 controller #1, which implements VBUS and ID sensing
capabilities and associated interrupt mechanisms to support for device and host OTG operations with the regular USB 2.0
port. Tegra K1 devices support battery charging charger detection capabilities and associated interrupt mechanisms that are
compliant with USB Battery Charging specification version 1.2 with USB 2.0 controller #1. For battery charging, software
programming sequences are required to support the operations in response to hardware notifications from USB 2.0 controller
#1.
All 3 USB 2.0 controllers support the EHCI programming model for scheduling transactions and interface managements as
hosts. Each USB 2.0 controller contains an integrated transaction translator hub to support USB 1.1 transactions when
connected to a USB 1.0 peripheral. USB 2.0 controller #1 supports EHCI-like programming models for scheduling responses
to host requests.
Tegra K1 USB 2.0 controllers support L1 and L2 (suspend) link power managements. Tegra K1 USB 2.0 controllers support
remote wakeup, wake on connect, wake on disconnect, and wake on overcurrent in all Tegra K1 power states, including deep
sleep mode.

USB Complex
19.2.1 USB 2.0 Controller #1 (USB_OTG)

USB 2.0 Controller #1 only connects to USB 2.0 Port #1, which is the primary USB 2.0 port on Tegra K1 devices. USB 2.0
Controller #1 shares the same USB 2.0 Port #1 pins with the USB 3.0 xHCI controller. The pinmux must be programmed prior
to USB 2.0 Controller #1 using USB 2.0 Port #1.
USB 2.0 Controller #1 supports both USB 2.0 device and USB 2.0 host operations. USB recovery is supported only with USB
2.0 Controller #1 and USB 2.0 Port #1.
Wake-up from deep sleep mode is also supported on VBUS and accessory detect (ACCx_DETECT) pins. Power and Ground
pins for USB1 and USB3 are shared.
19.2.2 USB 2.0 Controller #2

USB 2.0 Controller #2 must always be configured to Host mode, and it can be configured to connect to USB2.0 Port #2 or
HSIC Port #1.
USB 2.0 Port

USB 2.0 Controller #2 can be configured to use a regular USB 2.0 port. This is the second regular USB 2.0 port on Tegra K1
devices. USB 2.0 Controller #2 shares the same USB 2.0 Port #2 pins with the USB 3.0 controller. The pinmux must be
programmed prior to USB 2.0 Controller #2 using USB 2.0 Port #2.
This USB 2.0 port only supports Host mode operations.
HSIC
USB 2.0 Controller #2 can be configured to use HSIC interface #1 that allows connection of an on-board peripheral supporting
an HSIC interface to the Tegra K1 device. HSIC can be used to support baseband controllers that support an HSIC interface.
19.2.3 USB 2.0 Controller #3

USB 2.0 Controller #3 must always be configured to Host mode, and it can be configured to connect to USB2.0 Port #2or
HSIC Port #2.
USB 2.0 Port

USB 2.0 Controller #3 can be configured to use a regular USB 2.0 port. This is the second regular USB 2.0 port on Tegra K1
devices. USB 2.0 Controller #3 shares the same USB 2.0 Port #3 pins with the USB 3.0 controller. The pinmux must be
programmed prior to USB 2.0 Controller #3 using USB 2.0 Port #3.
This USB 2.0 port only supports Host mode operations.
HSIC
USB 2.0 Controller #3 can be configured to use the HSIC #2 interface that allows connection of an on-board peripheral
supporting an HSIC interface to the Tegra K1 device. HSIC can be used to support baseband controllers that support an HSIC
interface.
19.2.4 Interface Restrictions

Regular 2.0 port and HSIC are mutually exclusive for USB 2.0 controller #2 and #3, where only one of the interfaces can be
used with a given board design.
On power-on-reset, the default interface for USB 2.0 controller #2 is the UTMIP interface, and the default interface of USB 2.0
controller #3 is the UTMIP interface.

USB Complex
19.2.5 AHB Interface

All 3 USB 2.0 controllers adapt the AHB interface as masters and slaves for communicating with the other Tegra K1 devices.
The following table lists the AHB interface numbers for each controller.
Table 65: AHB Master and Slave Numbers

Controller AHB Master Number AHB Slave Number
USB 2.0 Controller #1 6 6
19.3 USB 2.0 Programming Interfaces

All 3 USB 2.0 controllers offer the same functionalities and may be configured to either host or device. However, due to
interface restrictions, only USB 2.0 controller #1 should be configured to device mode, while USB 2.0 controller #2 and #3
must always be configured to host mode.
§ Host controller registers and data structures are implemented as standard EHCI programming interface.
§ Host controller supports USB 1.1 Full and Low speed devices via integrated transaction translator hub through
EHCI standard data structures, instead of utilizing companion USB 1.1 host controller.
§ Device controller registers and data structures are implemented as extensions to the EHCI programmers
interface.
Figure 39 illustrates the control and datapaths block diagram of USB 2.0 controllers.
Figure 39: USB 2.0 Controller Block Diagram
Microprocessor Slave Interface

System Bus
Slave Interface
• Bus Interface
• Control and Status Registers
• Interrupt Generation
System Bus DMA Engine Dual Port RAM

Protocol Engine Port Controllers
Master Controller
§ Bus Interface § Single Channel (for host)
Interface § Virtual FIFO Channel (for § Interval Timers § Port Status and Control USB 2.0
§ Host: Transversal State
device) § Error Handling § Asynchronous Clock
Machine
§ DMA Contexts § CRC Handling
Physical Layer
§ Device: Endpoint Priming Domain Crossing
§ Bus Handshake § Transceiver Interface Interface
State Machine
On-Chip Dual Port Generation Logic
§ Data Movement
Synchronous SRAM
19.3.1 Endpoint Capabilities

USB 2.0 controller #1 supports 16 IN and 16 OUT endpoints in device mode. Endpoint 0 is always a bidirectional control
endpoint. All other endpoints can be configured as Bulk, Interrupt, Isochronous or Control endpoints in either direction. Control
endpoints are always bidirectional. Hence for a control endpoint, the endpoints in both directions must be configured to be
control endpoint. Conversely, if a particular endpoint number has either IN or OUT direction programmed to be a non-control
endpoint, the other direction must also be configured as a non-control endpoint.
The maximum packet size supported on any endpoint is 1024 bytes in high-speed mode.

USB Complex
19.4 USB 3.0 Controller

The Tegra K1 device provides 1 USB 3.0 controller that can support up to 2 regular USB 3.0 ports and their companion regular
USB 2.0 ports, or up to 3 standalone USB 2.0 ports. The USB 3.0 controller in Tegra K1 devices provides mechanisms to
communicate with USB 2.0 peripherals, such as keyboards, mouse devices, and card readers. The USB 3.0 controller also
provides mechanisms to communicate with USB 3.0 peripherals, such as cameras and storage devices, as a host using
regular USB 3.0 ports.
The following figure illustrates the connection between USB 3.0 controllers and USB interfaces in Tegra K1 devices, where
each USB 3.0 receptacle must encompass 1 USB 3.0 port and 1 USB 2.0 port from the USB 3.0 controller. USB 3.0 Controller
shares the same USB 2.0 Port #1, #2, and #3 pins with USB 2.0 controllers #1, #2, and #3. The pinmux must be programmed
prior to USB 3.0 Controller using USB 2.0 Port #1, #2, or #3.
Figure 40: Tegra K1 USB 3.0 Controller and Interfaces

MUX
HSIC
PAD
MUX
AHB
MUX USB2
PAD
USB 3.0 (XUSB) Controller
xHCI MUX USB2

IPFS Controller
(w/ debug
PAD
capability) USB2 P0
USB2 P1
USB2 P2 MUX USB2
APB
Device
USB2 P0 PAD
IPFS Controller SS P0
SS P1
MCCIF
MUX USB3/
SATA
PAD
MUX USB3/
PCIE
PAD
AXI
The USB 3.0 controllers support the xHCI programming model for scheduling transactions and interface managements as a
host that natively supports USB 3.0, USB 2.0, and USB 1.1 transactions with its USB 3.0 and USB 2.0 interfaces.
The Tegra K1 USB 3.0 controller supports USB 2.0 L1 and L2 (suspend) link power management and USB 3.0 U1, U2, and
U3 (suspend) link power managements. The Tegra K1 USB 3.0 controller supports remote wakeup, wake on connect, wake
on disconnect, and wake on overcurrent in all Tegra K1 power states, including deep sleep mode.
USB 2.0 Ports

Each USB 2.0 port operates in USB 2.0 High Speed mode when connecting directly to a USB 2.0 peripheral. Each USB 2.0
port operates in USB 1.1 Full and Low Speed modes when connecting directly to a USB 1.1 peripheral.
All USB 2.0 ports operating in High Speed mode share one High Speed Bus Instance, which means 480 Mb/s theoretical
bandwidth is distributed across these ports. All USB 2.0 ports operating in Full or Low Speed modes share one Full/Low
Speed Bus Instance, which means 12 Mb/s theoretical bandwidth is distributed across these ports.
USB Complex
USB 2.0 ports of the USB 3.0 controller support software initiated L1 and L2 (suspend) link power management. USB 2.0 ports
of the USB 3.0 controller do not support hardware initiated L1 link power management.
USB 3.0 Ports

USB 3.0 ports only operate in USB 3.0 Super Speed mode. All USB 3.0 ports share one Super Speed Bus Instance, which
means 5 Gb/s theoretical bandwidth is distributed across these ports.
USB 3.0 ports of the USB 3.0 controller support hardware initiated U1 and U2 link power management as well as software
initiate U3 (suspend) link power management.
Falcon Microcontroller
The Tegra K1 USB 3.0 controller integrated an NVIDIA Falcon microcontroller to perform the following tasks:
§ Command ring processing
§ Event ring management
§ Endpoint scheduling
§ Context save and restore
19.4.1 Interface Restrictions

A USB3.0 connector includes both USB2.0 and USB3.0 interface signals. The USB2.0 interface signals of a USB3.0 connector
must be assigned to the USB3.0 controller for xHCI specification compliance.
Similarly, if the USB3.0 interface signals are used to connect to a peripheral on the system board, such as a USB3.0 hub, the
USB2.0 signals connecting to that peripheral must be assigned to the USB3.0 controller.
19.4.2 Host and Memory Access Interfaces

USB 3.0 controller adapts the APB interface as its host interface for configuration and memory-mapped I/O register accesses.
USB 3.0 controller adapts direct memory as its memory interface for direct memory accesses.
19.5 USB 3.0 Programming Interface

The USB 3.0 Controller supports host functionality with host controller registers and data structures implemented as standard
xHCI programming interface. Figure 41 illustrates the control and datapaths block diagram of the USB 3.0 controller.

USB Complex
Figure 41: USB 3.0 Controller Block Diagram
Microprocessor Slave Interface

System Bus
Slave Interface
• Bus Interface
• Control and Status Registers
Micro-Controller
§ Command handlings
§ Event generations
§ Endpoint scheduling
DMA Engines Protocol Engines Port Controllers

§ Bus Interface § Interval Timers
§ Host: Transversal State § Error Handling § Port Status and Control
USB 2.0
Machine § Bus Handshake § CRC Handling Physical Layer
System Bus § Device: Endpoint Priming Generation § Transceiver Interface Interfaces
Master State Machine § Asynchronous Clock Logic
§ Data Movement Domain Crossing
Interface
DMA Engines Protocol Engines Port Controllers

§ Bus Interface § Interval Timers
§ Host: Transversal State § Error Handling § Port Status and Control USB 3.0
Machine § Bus Handshake § Flow Control Physical Layer
§ Device: Endpoint Priming Generation § CRC Handling
§ Transceiver Interface Interfaces
State Machine § Asynchronous Clock
§ Data Movement Domain Crossing Logic
19.6 USB PADCTL

The USB PADCTL in Tegra K1 devices provides the programming interface to assign the USB 2.0 ports to either USB 2.0
controllers or the USB 3.0 controller. The USB PADCTL provides VBUS control and overcurrent mapping for all USB 2.0
controllers and the USB 3.0 controller.
The USB PADCTL also provides the programming interface to configure the pad parameters for the USB 3.0 pad and the USB
2.0 pad for the USB 2.0 port that is assigned to USB 3.0 controller.
The following figure illustrates the connection between USB PADCTL and USB interfaces in a Tegra K1 device.

USB Complex
Figure 42: Tegra K1 USB PADCTL and Interfaces

USB 2.0 Controller #1 (OTG) MUX
HSIC
USB Controller USB2 P0 PAD
MUX
USB 2.0 Controller #2
AHB HSIC P0
USB Controller USB2 P1
USB 2.0 Controller #3

HSIC P1
USB Controller
USB2 P2 MUX USB2
PAD
USB 3.0 (XUSB) Controller
xHCI MUX USB2

IPFS Controller
(w/ debug
PAD
capability) USB2 P0
USB2 P1
USB2 P2 MUX USB2
APB
Device
USB2 P0 PAD
IPFS Controller SS P0
SS P1
MCCIF
MUX USB3/
SATA SATA
x1
PAD
IPFS AHCI
Controller SATA Ch0
MUX USB3/
PCIE PCIE
PCIE Lane 0 x5
TMS0 PCIE Lane 1 PAD
AXI
AFI PCIE Lane 2

TMS1 PCIE Lane 3
PCIE Lane 4
USB PADCTL
19.6.1 APB Interface

USB PADCTL adapts the APB interface as its host interface for configuration and memory-mapped I/O register accesses.

USB Complex
19.7 Programming Guidelines
19.7.1 USB_OTG Programming Guidelines
19.7.1.1 USB_OTG Programming
Clock Initialization
After power-on-reset, the USB clocks are disabled. Software can enable the USB clocks by setting CLK_ENB_USBD in the
CLK_OUT_ENB_L register to ENABLE. Also, the USB controller stays in reset. Software should bring it out of reset by first
setting SWR_USBD_RST in the RST_DEVICES_L register to ENABLE and then setting it to DISABLE.
Some parameters in UTMIP need to be programmed before the UTMIP can be brought out of reset. These parameters need
to be programmed every time the USB controller is reset: the SWR_USBD_RST in RST_DEVICES_L register and RST in the
USB2D_USBCMD register.
After UTMIP is reset, the PHY clock takes some time to come up, so software must wait until the USB_PHY_CLK_VALID bit in
the USB_SUSP_CTRL register becomes valid. This bit, when set to 1, also generates an interrupt if RSM_IE is set in the
USB_SUSP_CTRL register.
OTG_ID and VBUS Connection

Tegra K1 devices can use OTG_ID supported by the UTMIP/USB hardware, or a GPIO can be used for OTG_ID functions. If
using OTG_ID as a GPIO, the GPIO can be sampled to detect the presence of a micro-A or micro-B plug and the sampled
value can be written to the SW_ID bit in the PHY_VBUS_WAKEUP_ID_0 register. It is recommended that board design
connects OTG_ID on the Tegra K1 device to the ID pin on the micro-AB connector even if OTG_ID is connected to a GPIO.
Tegra K1 devices have a VBUS pin connected to the UTMIP, and VBUS pin from the connector should be connected to this
pin even though VBUS from the connector is connected to a GPIO. It is not required that VBUS from the connector directly
connect to the VBUS pin. It is required that its voltage is above 3V when VBUS is on.
Both VBUS and ID are available as a wake-up event during DPD/LP0 state. USB bus D+/D- line wake events are also
available as a DPD/LP0 state. Refer to the PMC section for more information.
Detection of USB Cable Insertion (General Use Cases)

The USB cable insertion event can be detected by a change in the ID or VBUS pin on the micro-AB connector. Initially, when
the cable is not attached, the ID pin on the micro-AB connector is floating and is detected as 1 by the Tegra K1 device
because of the weak pull-up on this pin. This makes the Tegra K1 start-up as a B-device, even though a cable is not
connected (when the ID pin is seen as a 1 by the Tegra K1 device, there can be no-cable or micro-B connected).
When a user attaches the USB cable, one of the following two events occur:
1. The user connects the micro-A end of the cable to the Tegra K1 device. This changes the ID pin to 0. Hence software
can detect the ID change and go to A-device mode. Software can then supply power to the USB and place the Tegra
K1 device in host mode.
2. The user connects micro-B (or mini-B) end of the cable to the Tegra K1 device. The other end of the cable can be
either micro-A or standard-A and is connected to an OTG host or a standard host, respectively. For both cases, the
Host starts driving power on VBUS and software can detect the cable insertion event by checking that the voltage on
VBUS has gone above the A_Sess_Vld level by reading the A_VBUS_VLD_STS bit in the
USB_PHY_VBUS_SENSORS register. Once this is seen, it can place the Tegra K1 device in the device mode.
Notes:
1. ID change can be detected by enabling the GPIO interrupt.

USB Complex
2. VBUS change can be detected by enabling the interrupt A_VBUS_VLD_INT_EN in the USB_PHY_VBUS_SENSORS
register.
3. The USB controller and PHY clocks need not be turned on for this detection.
4. To detect these events during DPD/LP0 modes, use VBUS/ID wakeup events in the PMC.
PHY Clock Control

The PHY clock can be turned off using the SUSP_SET bit in the USB_SUSP_CTRL register. This bit must be pulsed by first
writing a 1 and then writing a 0 to the bit.
To turn on the PHY clock, software should write to SUSP_CLR in the USB_SUSP_CTRL register. This bit must be pulsed by
first writing a 1 and then writing a 0 to the bit.
The current suspend status of the PHY can be checked by the USB_PHY_CLK_VALID bit of the USB_SUSP_CTRL register.
If this bit is 1, the PHY clock is turned on; otherwise it is off.
The PHY clock can be turned on automatically on the events mentioned below. Set only the required wakeup enable bits
based on the state of the USB as mentioned below. Do not set unnecessary wakeup enable bits. When the PHY clock wakes
up under any such event, make sure that the wakeup enable bits are turned off as soon as possible.
There is an interrupt generated whenever the PHY clock is turned on which can be checked by checking that the value of
USB_PHY_CLK_VALID in the USB_SUSP_CTRL register is 1. The interrupt can be enabled/disabled by setting the RSM_IE
bit in USB_SUSP_CTRL to 1/0.
Notes:
1. The PLLU_ENABLE bit in the PLLU_BASE register should be always set to ENABLE. All parameters for PLLU in the
PLLU_BASE and PLLU_MISC registers should be set according to the oscillator frequency used. Not doing that will
put the USB PHY PLL in a free-running mode, and can result in undesirable side effects.
2. When the USB PHY is suspended, the PCLK should not be stopped. It can be reduced to 32 KHz, however. If the
system clock is stopped, then it might not be possible to bring up the system on a wakeup event described below.
There are two cases to consider for controlling the PHY clocks depending on whether the Tegra K1 processor is in device or
host mode.
Device Mode
The PHY clock can be turned off in two cases:
§ When the USB cable is not connected, the VBUS signal is 0. In this case, software needs to turn on the PHY
clock on cable insertion. Follow the procedure described above in “Detection of USB Cable Insertion”.
§ When the USB cable is connected, the PHY clock can only be turned off when the SLI bit in the
USB2D_USBSTS register is set to 1 when the USB Host puts the USB bus in suspend mode. This bit can be
used to generate an interrupt if the SLE bit in the USB2D_USBINTR register is set to 1.
In this case, software needs to set two bits in the USB_SUSP_CTRL register to turn on the PHY clock on a USB
resume or a USB reset event from USB Host: WAKE_ON_DISCON_EN (Wake on Disconnect enable) and
WK_RSM_EN (Wake on Resume enable).
If WK_RSM_EN (bit 8) in the USB_SUSP_CTRL register is set to 1, the PHY clock can be turned on
automatically on receiving a USB resume event from the USB Host. If WAKE_ON_DISCON_EN in the
USB_SUSP_CTRL register is set to 1, the PHY clock can be turned on automatically on receiving a USB reset
event from the USB Host or if the USB cable is disconnected. These bits should only be turned on after the PHY
clock is turned off. The method described above can be used to interrupt the processor when the PHY clock is
turned on. Also, turn off these bits when coming out of the suspend state.

USB Complex
Host Mode
When a device is not connected, software can set the WKCN bit in USB2D_PORTSC1 register. Make sure that VBUS is also
turned on. After this, it can stop the PHY clock by using the method described above. The PHY clock resumes automatically
when a device is connected. The method described above can be used to interrupt the processor when the PHY clock is
turned on.
With a device connected, software needs to put the USB system in the suspend state by setting the SUSP bit in the
USB2D_PORTSC1 register. It needs to wait until this bit is set to 1 by the controller to make sure that the USB system actually
went into the suspend state. It can enable the WK_RSM_EN bit in the USB_SUSP_CTRL register and the WK_DS bit in the
USB2D_PORTSC1 register. Then it can stop the PHY clock as described above. The PHY clock is turned on automatically if
the USB device disconnects or it does a remote wakeup signaling. There is an interrupt associated with this as described
above.
If the software wants to wake up the USB system, then it needs to turn on the PHY clock as described above.
Charger Detection 1 (Non-compliant Chargers)

There are four conditions for the different kind of non-compliant chargers: SE1, FS-PU, LS-PU, SE0. Any kind of non-
compliant charger can be supported by following the generic procedure below:
1. VBUS detection (by whatever means software does it)
2. Enable USB controller and PHY power and clocks
3. Wait until PHY_CLKVALID = 1.
4. Wait for 10 microseconds more to give time for any filtering to pass through so software does not read the wrong
values.
5. Set the DIV_DET_EN bit in the IF_USB_PHY_VBUS_WAKEUP_ID_0 register to 1.
6. Wait for about 10 microseconds to allow the divider detector to settle.
7. Read the {VOP_DIV2P7_DET, VOP_DIV2P0_DET, VON_DIV2P7_DET, VON_DIV2P0_DET} register bits in the

IF_USB_PHY_VBUS_WAKEUP_ID_0 register.
{VOP_DIV2P7_DET, VON_DIV2P7_DET } = 2'b11: Connected to charger_A1.
8. Set the DIV_DET_EN bit in the IF_USB_PHY_VBUS_WAKEUP_ID_0 register to 0.
9. For A1, A2, A3, or A4, enable charging current per the connected charger’s requirement (A1, A2, A3, or A4).
10. Read the LS bits [11:10] in the PORTSC register.
Case 1: LS = 2'b11: Connected to charger_1.
Case 4: LS = 2'b00: Connected to either charger_4, a compliant charger, or a PC host.
11. For case 1, 2, or 3, enable charging current as per that charger’s requirement. This can vary for every
implementation.

USB Complex
12. For case 4, the connection is to either a PC host or charger_4 (which could be a USB compliant charger as well). Go
to step 15.
13. Set the USB circuit to low-power mode now. Make sure the charger circuit does not change state.
14. VBUS disconnect. Return to step 1.
15. Check for connection to a USB compliant charger by doing the charger detection from VBAT register. If yes, go back
to step 8. If not, continue to the next step.
16. Set the USB controller to device mode and enable it by setting it to RUN mode. Wait for SOF.
17. If an SOF is not seen after timeout, then the connection is to charger_4. Set the current limit as required for that
charger. Go to step 7.
Charger Detection 2 (Compliant Chargers)

This replaces step 10 in the above.
1. Make sure the UTMIP_PD_CHRG bit in the UTMIP_BAT_CHRG_CFG0_0 register is set to 0, so that charger
detection circuit is on.
2. Set the UTMIP_OP_I_SRC_EN bit in the UTMIP_BAT_CHRG_CFG0_0 register to 1.
3. Wait for about 10 microseconds to allow the battery charger detector to settle.
4. Now check that the VDCD_DET_CHG_DET bit is 1, and the VDCD_DET_STS bit is 0 in the
USB_PHY_VBUS_WAKEUP_ID register. This ensures that the data pins have made contact.
5. Set the UTMIP_OP_I_SRC_EN bit to 0 in the UTMIP_BAT_CHRG_CFG0_0 register.
6. Set the following register bits in the UTMIP_BAT_CHRG_CFG0_0 register to:
UTMIP_OP_SRC_EN = 1
UTMIP_ON_SINK_EN = 1
UTMIP_OP_SINK_EN = 0
UTMIP_ON_SRC_EN = 0
8. Now check that the VDAT_DET_CHG_DET and VDAT_DET_STS bits in the USB_PHY_VBUS_WAKEUP_ID
register are set to 1. This indicates connection to a USB compliant dedicated charger that supports up to 1.5A
current. If these bits are not set, then the connection is to a PC host, where the downstream port may support
charging.
9. Set the following bits in the UTMIP_BAT_CHRG_CFG0_0 register to:
UTMIP_OP_SRC_EN = 0
UTMIP_ON_SRC_EN = 1
11. Now check that the VDAT_DET_CHG_DET and VDAT_DET_STS bits in the USB_PHY_VBUS_WAKEUP_ID
register are both set to 1. This indicates connection to a USB compliant dedicated charger that supports up to 1.5A
current. If these bits are not set, then the connection is to a PC host, where the downstream port supports a standard
500mA current when the high power device is enumerated.
USB Complex
12. Set the following bits in the UTMIP_BAT_CHRG_CFG0_0 register to:
UTMIP_OP_SRC_EN = 0
UTMIP_ON_SRC_EN = 0
13. Now normal USB operation can continue if connected to PC host.
19.7.1.2 LPM Support

Software should program the following register to set the duration that the host keeps generating resume signaling when the
host initiated an exit from L1 based on system and device specific requirements:
CONTROLLER_USB2D_USBCMD_0.HIRD
The following software walk-around is required to extend the resume signaling if required.
1. Move PAD out of Suspend
IF_USB_SUSP_CTRL_0.USB_SUSP_CLR = SET (1)
2. Fake resume signaling
UTMIP_MISC_CFG0_0.UTMIP_DPDM_OBSERVE = 1
UTMIP_MISC_CFG0_0.UTMIP_DPDM_OBSERVE_SEL = 0xE
3. Wait the required time following the encoding of the HIRD value
4. Enable hardware to drive the resume signaling
CONTROLLER_USB2D_PORTSC1_0.FPR = Resume driven on port (1)
5. Disable fake resume signaling as hardware takes over
UTMIP_MISC_CFG0_0.UTMIP_DPDM_OBSERVE = 0
6. Wait for hardware to finish driving resume signaling by checking the following bit:
CONTROLLER_USB2D_PORTSC1_0.FPR = No resume driven on port (0)
7. Wait 50 µs
8. Enable hardware to start sending SOF and executing schedule:
CONTROLLER_USB2D_USBCMD_0.RS = RUN (1)
Software Initiated L1 Support

Software puts the bus into the L1 or Suspend (L2) state by setting the same SUSP bit in PORTSC1 register. The difference is
to put the link to L1, software should first program the following registers:
CONTROLLER_USB2D_PORTSC1_0.DA = N, Device Address of the attached device
CONTROLLER_USB2D_HOSTPC1_DEVLC_0. EPLPM = 0
CONTROLLER_USB2D_PORTSC1_0.SLP = Suspend using L1 (1)
Software should then set the following register bit to initiate L1 entry:
CONTROLLER_USB2D_PORTSC1_0.SUSP = 1
Software can check the following registers to ensure the link has entered L1:
USB Complex
CONTROLLER_USB2D_PORTSC1_0.SUSP = Port in suspend state (1)
CONTROLLER_USB2D_PORTSC1_0.SSTS = L1STATE_ENTERED (0)
If L1 cannot be entered successfully, the bus stays in the L0 state. Hardware will generate a port change interrupt when L1
entry fails. So software can check the following registers for the reason of the failed entry. Software can retry the L1 entry later
if the reason is NYET_PERIPH, where the peripheral indicates it is not ready to put the bus into L1.
CONTROLLER_USB2D_PORTSC1_0.SUSP = Port not in suspend state (0)
CONTROLLER_USB2D_PORTSC1_0.SSTS = NYET_PERIPH (1), or
= L1STATE_NOT_SUPPORTED (2),
= PERIPH_NORESP_ERR (3),
When the bus is in the L1, software can set the following register at any time to bring the link back to the L0 state.
CONTROLLER_USB2D_PORTSC1_0.FPR = Resume driven on port (1)
Hardware Initiated L1 Support

Software can enable hardware to put the bus to L1 automatically. Software should first program the following registers, where
X is the system specific idle threshold measured in number of SOFs with no activities in between:
CONTROLLER_USB2D_PORTSC1_0.DA = N, device address of the attached device
CONTROLLER_USB2D_HOSTPC1_DEVLC_0. EPLPM = 0
CONTROLLER_USB2D_HOSTPC1_DEVLC_0. LPMFRM = X
Software should then set the following register bit to enabled hardware initiated L1 entry:
CONTROLLER_USB2D_HOSTPC1_DEVLC_0. LPMX = 1
19.7.1.3 Streaming Mode

The USB controller supports streaming, where it starts sending DATA packets for OUT transactions when the controller has
not finished fetching the entire data packet from system memory to its TX buffer. For IN transactions, the streaming mode
allows data to be written to system memory before the entire data packet is received in its RX buffer. Streaming mode can be
disabled with the following bit:
CONTROLLER_USB2D_USBMODE_0.SDIS
Enabling streaming mode allows lower latency and higher bandwidth of USB transfers but requires lower system memory
latency.
Long system memory latency might cause TX buffer underrun/RX buffer overrun when streaming mode is enabled. Streaming
mode should be kept enabled when USB controller is initialized and streaming mode should only be disabled if it is determined
the system latency does cause the buffer overrun/underrun issues.
19.7.2 USB2 Programming Guidelines

The USB2 controller supports a UHSIC interface. All of these interfaces are directly controlled through USB2 register space.
19.7.2.1 Clock Initialization

After power-on-reset, the USB clocks are disabled. Software can enable the USB clocks by setting CLK_ENB_USBD in
CLK_OUT_ENB_L register to ENABLE.
Also, USB stays in reset. So software should bring it out of reset by first setting the SWR_USBD_RST in RST_DEVICES_L
register to ENABLE and then setting it to DISABLE.
USB Complex
After the clocks for USB2 are up, software can program any register for USB2 required for proper configuration.
PLLU outputs a 480 MHz clock (FO_UHSIC) for the UHSIC interface. If using any of these interfaces, PLLU should be
programmed appropriately.
Any time after USB2 is reset, or the UHSIC PHY comes out of suspend, software needs to wait until ULPI/UHSIC PHY clock
comes up. It can do that by checking for USB_PHY_CLK_VALID bit in USB2_IF_USB_SUSP_CTRL register. If this bit is 1,
PHY clocks are up; otherwise, they are not. There are interrupts associated with this bit: if USB_PHY_CLK_VALID_INT_ENB
is set to ENABLE, USB_PHY_CLK_VALID_INT_STS will be set to SET whenever the PHY clock becomes valid. Software can
write a 1 to USB_PHY_CLK_VALID_INT_STS to clear the interrupt status.
Before doing anything useful on USB2, one of its interfaces needs to be selected and configured.
19.7.2.2 Selection of UTMIP2 Interface

The UTMIP1 I/O pads are in power-down state at power-on. Bring them out of power-down mode by writing 0 to the following
fields (unless writing 1 is indicated):
1. FORCE_PD_POWERDOWN, FORCE_PD2_POWERDOWN, and FORCE_PDZI_POWERDOWN fields in the

UTMIP_XCVR_CFG0 register.
2. OTGPD and BIASPD fields in the UTMIP_BIAS_CFG0 register.
3. FORCE_PDDISC_POWERDOWEN, FORCE_PDCHRP_POWERDOWN, and FORCE_PDDR_POWERDOWN fields

in the UTMIP_XCVR_CFG1 register.
4. Hold UTMIP2 PHY in reset by writing a 1 to the UTMIP_RESET bit in the IF_USB_SUSP_CTRL register.
5. Program the PLLU parameters to enable the UTMIP2 PLLU clock.
6. Enable UTMIP2 interface by setting UTMIP_PHY_ENB in IF_USB_SUSP_CTRL register to 1.
7. Program the configuration parameters for UTMIP1.
8. Release reset to UTMIP2 by writing 0 to the UTMIP_RESET field in the IF_USB_SUSP_CTRL register.
9. Wait until the PHY clock comes up by checking the USB_PHY_CLK_VALID bit in the IF_USB_SUSP_CTRL register.
An interrupt can be generated as explained above.
10. Set the CM field in the USB2D_USBMODE register to HOST mode.
11. Program the USB2 controller to use UTMIP2 PHY by setting the PTS field in the
CONTROLLER_2_USB2D_HOSTPC1_DEVLC register to UTMIP (2’b00).
Selection of UHSIC Interface

1. UHSIC I/O pad is in power-down state at power-on. Bring it out of power-down mode by setting the PD_BG, PD_TX,
PD_RX, PD_ZI and RPD_DATA, RPD_STROBE fields in the UHSIC_PADS_CFG1 register to 0.
2. Bring the tracking circuit out of power-down mode by clearing the PD_TRK bit.
3. Add 25 µs delay to allow calibration to complete.
4. Tracking circuit can be powered down now by setting PD_TRK=1.
5. Hold UHSIC in reset by writing 1 to the UHSIC_RESET field in the IF_USB_SUSP_CTRL register.
6. Program the PLLU parameters to enable the UHSIC PLLU clock.
7. Select the UHSIC interface by writing 1 to the UHSIC_PHY_ENB field in the IF_USB_SUSP_CTRL register.
8. Program the configuration parameters for UHSIC.

USB Complex
9. Release reset to the UHSIC by writing 0 to the UHSIC_RESET field in the IF_USB_SUSP_CTRL register.
11. Program the USB2 controller to use the UHSIC PHY by writing 0 to the PTS field in the
CONTROLLER_1_USB2D_HOSTPC1_DEVLC register.
12. Program the UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE field in the UHSIC_TX_CFG0 register to “1”.
19.7.2.3 PHY Clock Control

The PHY clock can be turned off using the PHCD bit in the USB_PORTSC1 register. Note: This bit does not need to be
pulsed.
To turn on the PHY clock, software should write to USB_SUSP_CLR in USB2_IF_USB_SUSP_CTRL register. This bit must
be pulsed by first writing a 1 and then writing a 0 to the bit.
Whenever the PHY is placed in the suspend mode, the PHY clock is turned off and USB_PHY_CLK_VALID in the
USB2_IF_USB_SUSP_CTRL register is set to 0. Software should make sure that the PHY clock shuts down by polling this bit
whenever it places the PHY into suspend mode.
To prevent the PHY clock from waking up on unnecessary glitches on the USB pins, software can set the
USB_WAKEUP_DEBOUNCE_COUNT field in the USB_SUSP_CTRL register to a non-zero value (between 1-7). This will
allow the wakeup event to be debounced by the equivalent number of HCLK cycles.
An interrupt is generated whenever the PHY clock is turned on, which can be checked by checking the value of
USB_PHY_CLK_VALID in the USB_SUSP_CTRL register to be 1. The interrupt can be enabled/disabled by setting the
USB_PHY_CLK_VALID_INT_ENB bit in the USB_SUSP_CTRL register to 1/0.
To clear the USB_WAKEUP_INT_STS and USB_PHY_CLK_VALID_INT_STS interrupts, software can write a 1 to

corresponding bits.
Generally, whenever the PHY is woken up from the suspend mode, first a wakeup event is generated
(USB_WAKEUP_INT_STS = 1) followed by a PHY clock valid interrupt (USB_PHY_CLK_VALID_INT_STS = 1) when PHY
clock starts up.
19.7.2.4 Bus Signaling Procedure Changes for the UHSIC Interface

To support the UHSIC interface, some changes are required in the bus signaling procedure for USB2 controller (connect and
bus reset sequences) as described in the subsections below:
Host Mode - Bus Connect Sequence

The normal connect sequence assumes that port power has been enabled on a downstream port and the device has signaled
a “Connect” on the bus. This will generate a port change interrupt and the software takes action from here. Standard EHCI
connect interrupt can be used to detect the device connect.

USB Complex
Host Mode: Bus Reset Sequence

This is a reconnect procedure without physically detaching the USB cable. This operation is demanded by software whenever
necessary as it is the case when an unrecoverable anomaly takes place. It would then bring the bus, the port, and the device
into a well-known state.
1. Check if PortReset (the PR bit in the USB2D_PORTSC1 register) is NOT active. If by any means a bus reset is
already taking place, it must be stopped before proceeding. This is done by clearing the bit and polling until it goes
LOW.
2. Enable the “PortReset” bit - Start the HSIC bus reset on a downstream port by activating the PR bit of the
USB2D_PORTSC1 register.
3. Wait until the end of the reset. This wait time is defined by the USB 2.0 specification and has the effect of holding the
reset signaling on the HSIC bus.
4. Clear the PR bit.Stop the reset signaling by clearing the respective port reset bit.
5. Poll until the reset bit goes LOW to guarantee that the reset bit is effectively cleared;
6. Poll until LineState is DPlus.This confirms that the reset signaling has really finished on the HSIC bus and that the
USB2 controller is ready to connect again.
7. Proceed with the “HOST Bus Connect Sequence” as described above. From here on, the procedure is the same as
with an initial connect, instructing the USB2 controller to enter HS directly, skipping speed negotiation.
8. Standard EHCI reset interrupt can be used in Tegra K1 HSIC because native HSIC support is built-in.
19.7.3 USB3 Programming Guidelines

The USB3 controller supports ICUSB and UTMIP3 interfaces. All of these interfaces are directly controlled through USB3
register space.
19.7.3.1 Clock Initialization

After power-on-reset, USB3 clocks are disabled. Software can enable USB3 clocks by setting CLK_ENB_USB3 in
ARCLK_RST_CLK_OUT_ENB_H register to ENABLE.
Also, USB3 stays in reset at power-on and software should bring it out of reset by first setting SWR_USB3_RST in
RST_DEVICES_H register to ENABLE and then set it to DISABLE.
After the clocks for USB3 are up, software can program any registers for USB3 required for proper configuration.
PLLU outputs a 60 MHz clock FO_ICUSB for ICUSB interface and a 12 MHz clock FO_USB for UTMIP3 interface. If any of
these interfaces are used, PLLU should be programmed appropriately.
Any time after USB3 is reset or ICUSB/UTMIP3 PHY comes out of suspend, software needs to wait until ICUSB/UTMIP3 PHY
clock comes up. It can do that by checking the USB_PHY_CLK_VALID bit in the USB3_IF_USB_SUSP_CTRL register. If this
bit is 1, the PHY clocks are up; otherwise they are not. There are interrupts associated with this bit: if
USB_PHY_CLK_VALID_INT_ENB is set to ENABLE, USB_PHY_CLK_VALID_INT_STS will be set to SET whenever PHY
clock becomes valid. Software can write a 1 to USB_PHY_CLK_VALID_INT_STS to clear the interrupt status.
Before doing anything useful on USB2, one of its interfaces needs to be selected and configured.
19.7.3.2 Selection of the UTMIP3 Interface

1. UTMIP3 I/O pads are in power-down state at power-on. Bring them out of power-down mode by writing the following
fields to 0:

USB Complex
§ FORCE_PD_POWERDOWN, FORCE_PD2_POWERDOWN, FORCE_PDZI_POWERDOWN fields in

UTMIP_XCVR_CFG0 register.
§ OTGPD and BIASPD fields in UTMIP_BIAS_CFG0 register.
§ FORCE_PDDISC_POWERDOWN , FORCE_PDCHRP_POWERDOWN, FORCE_PDDR_POWERDOWN fields

in UTMIP_XCVR_CFG1 register.
2. Hold UTMIP3 PHY in reset by writing the UTMIP_RESET bit in the IF_USB_SUSP_CTRL register to 1.
3. Program the PLLU parameters to enable UTMIP3 PLLU clock.
4. Enable the UTMIP3 interface by setting UTMIP_PHY_ENB in the IF_USB_SUSP_CTRL register to 1.
5. Program the configuration parameters for UTMIP3.
6. Release the reset to UTMIP3 by writing 0 to the UTMIP_RESET field in the IF_USB_SUSP_CTRL register.
9. Program the USB3 controller to use UTMIP3 PHY by setting the PTS field in
CONTROLLER_2_USB2D_HOSTPC1_DEVLC register to UTMIP (2’b00).
19.7.3.3 Selection of UHSIC Interface

1. UHSIC I/O pad is in power-down state at power-on. Bring it out of power-down mode by setting the PD_BG, PD_TX,
PD_RX, PD_ZI, RPD_DATA, and RPD_STROBE fields in the UHSIC_PADS_CFG1 register to 0.
2. Bring the tracking circuit out of power-down mode by clearing the PD_TRK bit.
3. Add 25 µs delay to allow calibration to complete.
4. The tracking circuit can be powered down now by setting PD_TRK=1.
5. Hold UHSIC in reset by writing 1 to the UHSIC_RESET field in the IF_USB_SUSP_CTRL register.
6. Program the PLLU parameters to enable the UHSIC PLLU clock.
7. Select the UHSIC interface by writing 1 to the UHSIC_PHY_ENB field in the IF_USB_SUSP_CTRL register.
8. Program the configuration parameters for UHSIC.
9. Release reset to the UHSIC by writing 0 to the UHSIC_RESET field in the IF_USB_SUSP_CTRL register.
11. Program the USB3 controller to use the UHSIC PHY by writing 0 to the PTS field in the
CONTROLLER_1_USB2D_HOSTPC1_DEVLC register.
12. Program the UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE field in the UHSIC_TX_CFG0 register to “1”.
19.7.3.4 Detection of USB Cable Insertion

The USB cable insertion event can be detected by a change in the ID or VBUS pin on the micro-AB connector. Initially, when
the cable is not attached, the ID pin on the micro-AB connector is floating and is detected as 1 by Tegra K1 devices because
of the weak pull-up on this pin. This makes a Tegra K1 device start up as a B-device, even though a cable is not connected
(when the ID pin is seen as a 1 by a Tegra K1 device, there can be no cable or micro-B connected).

USB Complex
When a user attaches the USB cable, one of the following two events occur:
§ User connects micro-A end of the cable to the Tegra K1 device. This changes the ID pin to 0. Hence the
software can detect the ID change and go to A-device mode. Software can then supply power to the USB and
place the Tegra K1 device in host mode.
§ User connects micro-B (or mini-B) end of the cable to the Tegra K1 device. The other end of the cable can be
either micro-A or standard-A and will be connected to a standard host, respectively.
For both cases, the Host will start driving power on VBUS and software can detect the cable insertion event by checking the
VBUS status on corresponding GPIO. Once this is seen, it can place the Tegra K1 device in the device mode.
Note: Both ID and VBUS changes can be detected by enabling the corresponding GPIO
interrupts.
USB controller/PHY clocks do not need to be turned on for this detection as this is done
using GPIOs.
To detect these events during DPD/LP0 modes, use VBUS/ID wakeup events in the PMC.
19.7.3.5 PHY Clock Control

The PHY clock can be turned off by writing 1 to the PHCD bit in the USB2D_PORTSC1 register. Note: There is no need to
pulse this bit.
To turn on the PHY clock, software should write to SUSP_CLR in the USB3_IF_USB_SUSP_CTRL register. This bit must be
pulsed by first writing a 1 and then writing a 0 to it.
The current suspend status of the PHY and thereby whether the PHY clock is running can be checked by reading the bit
USB_PHY_CLK_VALID in USB_SUSP_CTRL register. If the PHY is placed in suspend, then this bit will be set to 0, else it will
be set to 1. Software should make sure that PHY clock shuts down by polling this bit whenever it places the PHY into suspend.
To prevent the PHY clock from waking up on unnecessary glitches on the USB pins, software can set the
USB_WAKEUP_DEBOUNCE_COUNT field in USB_SUSP_CTRL register to a non-zero value (between 1-7). This will allow
the wakeup event to be debounced by the equivalent number of HCLK cycles.
An interrupt is generated whenever the PHY is woken up from suspend, which can be verified by checking that the value of
USB_WAKEUP_INT_STS in USB_SUSP_CTRL register is 1. The interrupt can be enabled/disabled by setting the bit
USB_WAKEUP_INT_ENB in USB_SUSP_CTRL to 1/0.
An interrupt is generated whenever the PHY clock is turned on, which can be verified by checking that the value of
USB_PHY_CLK_VALID_INT_STS in the USB_SUSP_CTRL register is 1. The interrupt can be enabled/disabled by setting the
USB_PHY_CLK_VALID_INT_ENB bit in the USB_SUSP_CTRL register to 1/0.
To clear the USB_WAKEUP_INT_STS and USB_PHY_CLK_VALID_INT_STS interrupts, software can write a 1 to the
corresponding bits.
Generally, whenever PHY is woken up from suspend, first a wakeup event is generated (USB_WAKEUP_INT_STS = 1)
followed by a PHY clock valid interrupt (USB_PHY_CLK_VALID_INT_STS = 1) when the PHY clock starts up.
Note: The PLLU_ENABLE bit in PLLU_BASE register should be always set to ENABLE. All the
parameters for PLLU in PLLU_BASE and PLLU_MISC register should be set according to
the oscillator frequency used. Not doing that will put the USB PHY PLL in a free-running
mode, and can result in undesirable side-effects.
When the USB PHY is suspended, the USB3 clock should not be stopped. It can be
reduced to 32 KHz, however. If the system clock is stopped, then it may not be possible to
bring up the system on a wakeup event described below.

USB Complex
When USB3 is in suspend, AHB clocks to USB3 controller are turned off, and hence there
should be no register access to USB2_CONTROLLER_2_* registers. All registers marked
as ARUSB3_IF_* are accessible, and can be used to resume the UTMIP3 PHY clocks.
When a device is not connected, software can set the WKCN bit in USB2D_PORTSC1 register. Make sure that VBUS is also
turned on. After this, it can stop the PHY clock by using the method described above. The PHY clock will resume automatically
when a device is connected. The method described above can be used to interrupt the processor when the PHY clock is
turned on.
With a device connected, software needs to put the USB system under suspend by setting the bit SUSP in USB2D_PORTSC1
register. It needs to wait until this bit is set to 1 by the controller to make sure that the USB system actually went into suspend.
It can enable the bits USB_WAKE_ON_RESUME_EN in USB_SUSP_CTRL register and WK_DS in USB2D_PORTSC1
register. Then it can stop the PHY clock as described above. The PHY clock will be turned on automatically if the USB device
disconnects or it does a remote wakeup signaling. There will be an interrupt associated with this as described above.
If the software wants to wake up the USB system, it needs to turn on the PHY clock as described above.
19.7.3.6 USB3 Controller Power Gating
Initialization and Shutdown Procedure for USB

1. Bring up USB3 clocks by writing 1 to CLK_ENB_USB3 in ARCLK_RST_CLK_OUT_ENB_H register.
2. Set and clear the SWR_USB3_RST bit in the RST_DEVICES_H register to bring the USB block out of reset.
3. Set the UTMIP_RESET bit in the USB_SUSP_CTRL register to 1 to keep UTMIP3 PHY in reset.
4. Program the UTMIP and PLLU parameters.
§ Set the UTMIP_SUSPEND_EXIT_ON_EDGE bit (bit 22) in the UTMIP_MISC_CFG0 register to 0.
§ Set PLLU_ENABLE to 1, and never deassert it.
5. Set the UTMIP_RESET bit in the USB_SUSP_CTRL register to 0 to bring UTMIP3 out of reset.
§ Wait until PHY_CLKVALID is set to 1.
6. Set USB controller and PHY to suspend by writing 1 to PHCD in USB2D_PORTSC1 register. This will reduce the
power consumption on USB3 controller and UTMIP3 PHY.
7. Set all PD bits required to bring USB pads to low power mode.
§ UTMIP_OTGPD in UTMIP_BIAS_CFG0 is needed for VBUS detection, and so it should be set to 0.
§ If using VBUS_WAKEUP for VBUS detection, then UTMIP_BIASPD in UTMIP_BIAS_CFG0 can be set to 1 to
save power. But if using A_SESS_VLD or any other VBUS sensor for VBUS detection, then this bit should be set
to 0.
§ ID_PU in USB_PHY_VBUS_WAKEUP_ID should be set to 1 to enable ID detection.
§ UTMIP_IDPD_SEL in UTMIP_BIAS_CFG0 should be set to 0.
8. To interrupt the processor on VBUS or ID detection, software can set the following:
§ Enable appropriate VBUS interrupt enable, for example, I using A_SESS_VLD sensor for VBUS detection, set
A_SESS_VLD_INT_EN in the USB_PHY_VBUS_SENSORS register to 1.
§ Enable ID detection interrupt by setting ID_INT_EN in the USB_PHY_VBUS_WAKEUP_ID register.
9. When (VBUS=1) or (ID=0) is detected, do the following:

USB Complex
§ Bring the USB3 controller and PHY out of suspend mode by pulsing the SUSP_CLR in USB_SUSP_CTRL
register by first writing 1 and then writing 0.
§ Clear the PD bits that are required for the normal operation.
10. From this point on, the driver can run normal operations.
§ UTMIP should only be suspended by writing 1 to PHCD in the USB2D_PORTSC1 register when the USB cable
is connected and only after the USB bus is suspended, for both device and host modes.
11. If a cable disconnect is detected (VBUS = 0) or (ID = 1), then go back to step 4.
19.7.4 UTMIP Programming Guidelines

A Tegra K1 device has a total of 3 UTMI+ interfaces. This results in three cabled USB ports. These ports are not part of a
multiport host configuration. They are completely independent ports and can be configured in any combination of device or
host. Internally, these ports correspond to USB controllers 1, 2, and 3, where controller 1 is often implicitly numbered.
Externally, these are USB ports 0, 1, and 2. All UTMI+ PHY interfaces are identical instances of the same design. All three
controllers use latest edition of USB core controller.
19.7.4.1 Holding USB in Reset

It is important that most static configuration of the UTMIP (and USB) be done while the unit is held in reset. For example,
holding reset ensures that PLL_U is disabled and can be reconfigured. It also ensures that transactions are not occurring on
the USB interface. Holding reset in both a controller and its corresponding PHY can be achieved by using the RST bit of the
USB2D_USBCMD register.
19.7.4.2 PLL_U Programming

The USB ports use a cascaded PLL scheme to guarantee a high clock quality. First there is a PLL_U, which is the source
clock for both the USB PLLs that are dedicated to ports. PLL_U (of type CLKPLL960_USB) produces reference clocks for all
forms of USB (UTMIP, UHSIC). Table 66 describes the parameter settings that are dependent on the crystal clock reference
frequency. The parameters are specified in decimal notation.
Table 66: 480 MHz PLL_U Output Frequency Fo = (Fi·N)÷(M· 2) With VCO_FREQ=0
Fi (MHz) 12.0MHz 13.0MHz 16.8MHz 19.2MHz 26.0MHz 38.4 MHz 48.0MHz
N (PLLU_DIVN) 960 960 400 200 960 200 960
M (PLLU_DIVM) 12 13 7 4 26 4 12
These parameters can be found in the PLLU_BASE register. The PLLU_OVERRIDE bit should be set to 0. PLLU_VCO_FREQ
parameter must also be set to 0.
Note: PLL_U must be properly configured in the Boot ROM. DO NOT change the parameters of
PLL_U while the unit is running. The same applies to the USB_PHY_PLL.
19.7.4.3 PLL_U and USB_PHY_PLL Automatic Startup Times

The PLL_U and USB_PHY_PLL automatic startup times are used in reset and suspend modes to kick start the PLLs. Software
should not manually force the PLL up and down because it cannot do so rapidly enough to meet the protocol. The following
table lists the start times, which must be set up in the Boot ROM.

USB Complex
Table 67: PLL Automated Start Times (Must be Set Up in the Boot ROM)
Crystal Frequency 12.0 MHz 13.0 MHz 16.8 MHz 19.2 MHz 26.0 MHz 38.4 MHz 48.0 MHz
PLLU_ENABLE_DELAY_COUNT 2 2 3 3 4 5 6
PLLU_STABLE_COUNT 47 51 66 75 102 150 188
PLL_ACTIVE_DLY_COUNT 8 9 11 12 9 24 31
XTAL_FREQ_COUNT 118 127 165 188 254 375 469
PLLU_ENABLE_DLY_COUNT should be set for at least 1 microsecond, PLLU_STABLE_COUNT should be set for at least
1 ms, the PLL_ACTIVE_DLY_COUNT should be at least 10 ms, and the XTAL_FREQ_COUNT set for about 2.5 ms.
19.7.4.4 Fuse Programming

The Tegra K1 device incorporates fuses to account for process variation in high speed data eye swing. The high speed data
eye is controlled through the SETUP[6:0] transceiver pad parameter of the USB control registers. To set this parameter via the
fuses, set the UTMIP_SPARE_CFG0[3] bit on all USB ports. This must be done in the Boot ROM. The default is to maintain
backward compatibility, which implies no fuses are used by default. The objective is to get the data eye swing as close as
possible to 400mV without falling below the mark under typical operating conditions.
19.7.4.5 Programming the Tracking Length Time

The PD_TRK signal is used to power down the bias cell. After 25 microseconds of bias cell operation, the PD_TRK signal can
be turned high to save power. This can be automated by programming a timing interval as given in the following table.
Table 68: 25 µs Timer on Bias Cell Tracking (for Set Up in the Boot ROM)
Crystal Frequency 12.0 MHz 13.0 MHz 16.8 MHZ 19.2 MHz 26.0 MHz 38.4 MHz 48.0 MHz
UTMIP_BIAS_PAD_TRK_COUNT 5 6 7 8 11 15 19
(UTMIP_BIAS_CFG1[7:3])
All values in the table are decimal. This parameter must be set in the Boot ROM while the crystal clock is stopped. To stop the
crystal clock, disable the UTMIP_PHY_XTAL_CLOCKEN bit of register UTMIP_MISC_CFG1 and then re-enable it when done.
Because there is more than one UTMIP sharing the same bias cell, power down is done through a daisy chain, requiring
power down across all ports.
19.7.4.6 Powering Down a USB Port Outside of Deep Power Down (DPD)
When a port is known to be disabled, there needs to be a mechanism to stop its power consumption for situations outside of
DPD. This section addresses disabling a port while powered up.
Powering down of USB at times other than deep power down should be done by setting all specialized PLL and pad power
down pins instead of using the global E_DPD pins of the USB analog components. It is safer to power down the cells through
the traditional power down pins when the 3.3V and 1.2V supplies might still be on. This is achieved by setting the following pad
controls from UTMIP register space. Before setting the power down bits; save previous registers values so that they may be
restored. This type of power down should not be done in the Boot ROM.
Table 69: UTMIP Pad Controls

Pad Control Analog Register Bit Settings
Cell
PD Transceiver UTMIP_FORCE_PD_POWER_DOWN=1
PD2 Transceiver UTMIP_FORCE_PD2_POWER_DOWN=1
PD_ZI Transceiver UTMIP_FORCE_PDZI_POWER_DOWN=1
PD_DR Transceiver UTMIP_FORCE_PDDR_POWER_DOWN=1

USB Complex
Pad Control Analog Register Bit Settings

Cell
PD_CHRP Transceiver UTMIP_FORCE_PDCHRP_POWER_DOWN=1
PD_DISC Transceiver UTMIP_FORCE_PDDISC_POWER_DOWN=1
PD_CHG Transceiver UTMIP_PD_CHG=1
PD Bias UTMIP_BIASPD=1
PD_TRK Bias UTMIP_FORCE_PDTRK_POWER_DOWN=1
OTG_PD Bias UTMIP_OTGPD=1
ID_PD Bias UTMIP_IDPD_SEL=1, UTMIP_IDPD_VAL=1
VBUS_WAKEUP_PD Bias UTMIP_VBUS_WAKEUP_POWER_DOWN=1
ENABLE PHY PLL UTMIP_FORCE_PLL_ENABLE_POWERDOWN=1
ACTIVE PHY PLL UTMIP_FORCE_PLL_ACTIVE_POWERDOWN=1
PD_SAMP_A/C PHY_PLL UTMIP_FORCE_PD_SAMP_A/C_POWERDOWN=1
ENABLE PLL U UTMIP_FORCE_PLLU_POWERDOWN=1
UTMIP PHY UTMIP_PHY_XTAL_CLOCKEN=0
19.7.4.7 Extending Debouncer Period Length

USB debouncers provide a programmable debounce to alleviate the software burden. This is done with the
UTMIP_DEBOUNCE_TIME_SCALE parameter located at UTMIP_BIAS_CFG1[13:8]. The default implies a timescale factor of
1. The timescale should not be programmed at Boot ROM time. The timescale register field incremented by 1 multiplies the
debounce duration for all debouncers.
In the Boot ROM, the A debounce period should be set to 10 ms. This is dependent on the crystal frequency scale. The
following table shows how it is programmed.
Table 70: 10 ms Timer on the A Debounce Period

Crystal Frequency 12.0 MHz 13.0 MHz 16.8 MHZ 19.2 MHz 26.0 MHz 38.4 MHz 48.0 MHz
UTMIP_BIAS_DEBOUNCE_A 30000 32500 42000 48000 65000 96000 120000
To program values of 96000 and 120000 for crystal clock frequencies of 38.4 and 48 MHz, respectively, these steps must be
followed:
1. In the debounce register, program 48000 for a 38.4 MHz crystal clock or 60000 for a 60 MHz clock.
2. Set UTMIP_BIAS_DEBOUNCE_TIMESCALE to 1 by writing into the USB2_UTMIP_BIAS_CFG1[1] register field.
19.7.4.8 Deep Power Down Behavior

Tegra K1 devices’ deep power down behavior for USB wake-up events is controlled in the PMC via registers
USB_DEBOUNCE_DLY, USB_AO and the WAKE_MASK (USB_EVENT field) of the PMC unit. These control the wake-up
events, their debounce duration, and their debounce length while powered down. USB port 0 has a possible event on ID or
VBUS detection. These can be configured at startup time. These registers take over from the UTMIP registers when the chip is
powered down. The programming depends on the context of the chip. For example, if USB port 0 is a dedicated host port then
the VBUS wake-up event should be kept powered down. Conversely, a dedicated device mode port may not want to wake-up
on the detection of an ID connector and can chose to power down ID.
19.7.4.9 Miscellaneous Boot ROM Fields

The UTMIP fields in the following table must be programmed at Boot ROM time. These should be set when the USB device is
held in reset.

USB Complex
Field Value
UTMIP_FS_PREAMBLE_J (UTMIP_TX_CFG0) 1
UTMIP_PD_CHG (UTMIP_BAT_CHRG_CFG0) 1
UTMIP_XCVR_LSBIAS_SEL (UTMIP_XCVR_CFG0) 0
UTMIP_SPARE_CFG0[3] 1
UTMIP_IDLE_WAIT (UTMIP_HSRX_CFG0) 17
UTMIP_ELASTIC_LIMIT (UTMIP_HSRX_CFG0) 16
UTMIP_HS_SYNC_START_DLY (UTMIP_HSRX_CFG1) 9
19.7.4.10 PHY Resets

Additional controls have been provided to stop the USB PHY (and its clocks) by issuing a reset to the PHY only (as opposed to
a reset encompassing the controller and the PHY). This is akin to the Reset found in the UTMI+ standard. This is done in both
controllers. See the UTMIP_RESET field of the USB_SUSP_CTRL register for more information.
19.7.4.11 Static Boot ROM Configuration for UTMIP

The boot ROM configuration for UTMIP should be done while the unit is held in Reset. For correct behavior, the following
sequence MUST be followed:
1. Apply Reset to the USB controller (and UTMIP).
2. Run the crystal clock for approximately 5 microseconds while the UTMIP is in reset.
3. Stop the crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN Low. This only stops the crystal clocks in the UTMIP
units.
4. Program PLL_U as described in the “PLL_U Programming” section.
5. Program automatic PLL start times as described in the “PLL_U and USB_PHY_PLL Automatic Startup Times”
section.
6. Remove power downs from USB_PHY_PLL ACTIVE/ENABLE/PD_SAMP_A/C and PLL_U.
7. Program the tracking duration as described in “Programming the Tracking Length Time.” Remove the power downs
from PD (Bias) and disable PD_TRK. After 25 µs (tracking time), enable PD_TRK by writing 0 into
UTMIP_FORCE_PDTRK_POWER_DOWN.
8. Once PD (Bias) is disabled, disable OTG_PD after 1 µs.
9. Remove powerdowns from ID_PD and VBUS_WAKEUP_PD. This can be removed earlier, as there is no timing or
sequential relation with other signals.
10. Once the PLL_U, USB_PHY_PLL, and Bias pad are ready, remove PD (Transceiver). After 400 ns, the USB pad is
ready for HS/FS/LS operation.
11. There are other powerdowns which can be removed if needed (as such not needed for Boot ROM). These are PD /
PD_ZI / PD_DR / PD_CHRP / PD_DISC / PD_CHG.
12. Program the debouncer length time as described in ”Extending Debouncer Period Length.”
13. Program various static parameters of the UTMIP as described in “Miscellaneous Boot ROM Fields.”
14. Restart the crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN.

USB Complex
15. Resume any previous USB programming work that falls outside of UTMIP and release reset.From the UTMIP
perspective it does not matter when reset is released, as long as it is after step 8. It will take about 3.5 ms before the
60 MHz clock appears once reset is released.
From a UTMIP perspective, ensure that all the cabled USB port PHYs are configured similarly in the Boot ROM.
19.7.4.12 EHCI Deviations

§ Embedded Transaction Translator – Allows direct attachment of FS and LS devices in host mode without the
need for a companion controller.
§ Embedded design interface – This core does not have a PCI Interface and therefore the PCI configuration
registers described in the EHCI specification are not applicable.
Programmable Physical Interface Behavior

This design supports multiple Physical interfaces which can operate in differing modes when the core is configured with
software programmable Physical Interface Modes. Software programmability allows the selection of the Physical interface part
during the board design phase instead of during the chip design phase. The control bits for selecting the Physical Interface
operating mode have been added to the HOSTPCx register providing a capability that is not defined by EHCI.
Port Reset
The port connect methods specified by EHCI require setting the port reset bit in the PORTSCx register for a minimum duration
of 10ms. Due to the complexity required to support the attachment of devices that are not high speed, there are counter
already present in the design that can count the 10ms reset pulse to alleviate the requirement of the software to measure this
duration. The basic connection is then summarized as the following:
§ [Port Change Interrupt] Port connect change occurs to notify the host controller driver that a device has
attached.
§ Software shall write a ‘1’ to the reset the device.
§ Software shall write a ‘0’ to the reset the device after 10 ms.
§ Driver needs to wait until port change interrupt is asserted and port reset is cleared
Note: Should the EHCI host controller driver attempt to write a ‘0’ to the reset bit while a reset is in progress the
write will be ignored and the reset will continue until completion.
§ [Port Change Interrupt] Port enable change occurs to notify the host controller that the device is now operational
and at this point the port speed has been determined.
Port Speed Detection

After the port change interrupt indicates that a port is enabled, the EHCI stack should determine the port speed. Unlike the
EHCI implementation which will re-assign the port owner for any device that does not connect at High-Speed, this host
controller supports direct attach of non High-Speed devices. Therefore, the following differences are important regarding port
speed detection:
§ Port Owner is read-only and always reads 0.
§ A 2-bit Port Speed indicator (PSPD) has been added to HOSTPCx to provide the current operating speed of the
port to the host controller driver.
Port Reset duration is 55 ms instead of 50 ms.

USB Complex
Port Suspend (PORTSC.Suspend) bit is set immediately after setting the bit. As per EHCI a 4 ms delay is expected for this bit
to be set.
Tegra K1 devices also have the following cases that are not directly compliant to EHCI:
§ USB controller/PHY interface initialization
§ PHY Clock shutdown/wakeup procedure during suspend/resume/connect/disconnect
§ PMC logic use for special low power modes during suspend/LP0
19.7.5 Cold Boot

Step 1
The Boot ROM enables USB2.0 related PLLs with software override.
The Boot ROM deasserts reset to the XUSB PADCTL block.
Step 2
The PAD driver switches USB 2.0 related PLLs to under hardware control after the PAD driver is loaded.
§ Program the following CAR registers to set up hardware control of UTMIPLL:
- CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0[UTMIPLL_USE_LOCKDET] to ‘1’
- CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0[UTMIPLL_CLK_ENABLE_SWCTL] to ‘0’
- CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0[UTMIPLL_SEQ_START_STATE] to ‘1’
- CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0[UTMIP_FORCE_PLL_ENABLE_POWERUP] to ‘0’
- CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0[UTMIP_FORCE_PLL_ENABLE_POWERDOWN] to ‘0’
§ Program the following CAR registers to set up software override of UTMIPLL’s IDDQ control.
- CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0[UTMIPLL_IDDQ_SWCTL] to ‘1’
- CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0[UTMIPLL_IDDQ_OVERRIDE_VALUE] to ‘0’
§ Program the following CAR register to enable hardware control to UTMIPLL:
- Wait 1 µs then set CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0[UTMIPLL_SEQ_ENABLE]

to ‘1’
§ Program the following CAR registers to set up hardware control of PLLU:
- CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_0[PLLU_USE_LOCKDET] to ‘1’
- CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_0[PLLU_CLK_ENABLE_SWCTL] to ‘0’
- CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_0[PLLU_CLK_SWITCH_SWCTL] to ‘0’
- CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_0[PLLU_SEQ_START_STATE] to ‘1’
§ Program the following CAR register to set up hardware control of PLLU when all non-HSIC USB2.0 ports are
assigned to XUSB:
- CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_0[PLLU_SEQ_IN_SWCTL] to ‘0’
§ Program the following CAR register to enable hardware control of PLLU:
- Wait 1 µs then set CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_0[PLLU_SEQ_ENABLE] to ‘1’
§ Program the following CAR register bits to disable the override to PLLU:
- CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0[UTMIP_FORCE_PLLU_POWERUP] to ‘0’

USB Complex
- CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0[UTMIP_FORCE_PLLU_POWERDOWN] to ‘0’
- CLK_RST_CONTROLLER_PLLU_BASE_0[PLLU_OVERRIDE] to ‘0’
The PAD driver enables USB3.0 related PLLs.
§ Program the following CAR register bits to ‘0’ to move the REFPLLE and PLLE out of IDDQ:
- CLK_RST_CONTROLLER_PLLREFE_MISC_0[PLLREFE_IDDQ]
- CLK_RST_CONTROLLER_PLLE_MISC_0[PLLE_IDDQ_OVERRIDE_VALUE]
§ Program the following CAR register bits to configure the REFPLLE:
- CLK_RST_CONTROLLER_PLLREFE_BASE_0[PLLREFE_MDIV]
- CLK_RST_CONTROLLER_PLLREFE_BASE_0[PLLREFE_NDIV]
- CLK_RST_CONTROLLER_PLLREFE_BASE_0[PLLREFE_PLDIV]
- CLK_RST_CONTROLLER_PLLREFE_BASE_0[PLLREFE_KVCO]
- CLK_RST_CONTROLLER_PLLREFE_BASE_0[PLLREFE_KCP]
§ Set the following CAR register bit to ‘1’ to enable the PLL:
- CLK_RST_CONTROLLER_PLLREFE_BASE_0[PLLREFE_ENABLE]
§ Program the following CAR register to enable REFPLLE LOCK output
- CLK_RST_CONTROLLER_PLLREFE_MISC_0[PLLREFE_LOCK_ENABLE] to ‘1’
§ Poll the following CAR register to ensure REFPLLE is locked:
- CLK_RST_CONTROLLER_PLLREFE_MISC_0[PLLREFE_LOCK] equals ‘1’
§ Program the following CAR register bits to configure the PLLE according to the frequency of osc_clk:
- CLK_RST_CONTROLLER_PLLE_BASE_0[PLLE_MDIV]
- CLK_RST_CONTROLLER_PLLE_BASE_0[PLLE_NDIV]
- CLK_RST_CONTROLLER_PLLE_BASE_0[PLLE_FDIV4B]
- CLK_RST_CONTROLLER_PLLE_BASE_0[PLLE_PLDIV_CML]
§ Set the following CAR register bit to ‘1’ to enable the PLL:
- CLK_RST_CONTROLLER_PLLE_BASE_0[PLLE_ENABLE]
§ Program the following CAR register to enable PLL LOCK output:
- CLK_RST_CONTROLLER_PLLE_MISC_0[PLLE_LOCK_ENABLE] to 1’b1
§ Poll the following CAR register to ensure PLLE is locked:
- CLK_RST_CONTROLLER_PLLE_MISC_0[PLLE_LOCK] equals ‘1’
The PAD driver switches USB 3.0 related PLLs to under hardware control.
§ Program the following CAR registers to set up hardware control of PLLE
- CLK_RST_CONTROLLER_PLLE_AUX_0[PLLE_USE_LOCKDET] to ‘1’
- CLK_RST_CONTROLLER_PLLE_AUX_0[PLLE_ENABLE_SWCTL] to ‘0’
- CLK_RST_CONTROLLER_PLLE_AUX_0[PLLE_SS_SWCTL] to ‘0’
- CLK_RST_CONTROLLER_PLLE_AUX_0[PLLE_SEQ_START_STATE] to ‘1’
- CLK_RST_CONTROLLER_PLLE_MISC_0[PLLE_IDDQ_SWCTL] to ‘0’

USB Complex
§ Program the following CAR register to enable hardware control of PLLE:
- Wait 1 µs then set CLK_RST_CONTROLLER_PLLE_AUX_0[PLLE_SEQ_ENABLE] to ‘1’
§ Program the following CAR registers to set up hardware control of XUSB Brick’s PLL, where XUSBIO_PLL is
used by either or both XUSB and PCIE and SATA_PLL is used by either XUSB or SATA:
- CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0[XUSBIO_PADPLL_USE_LOCKDET] to ‘1’
- CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0[XUSBIO_CLK_ENABLE_SWCTL] to ‘0’
- CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0[XUSBIO_PADPLL_RESET_SWCTL] to ‘0’
- CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0[XUSBIO_SEQ_START_STATE] to ‘1’
- CLK_RST_CONTROLLER_SATA_PLL_CFG0_0[SATA_PADPLL_USE_LOCKDET] to ‘1’
- CLK_RST_CONTROLLER_SATA_PLL_CFG0_0[SATA_PADPLL_RESET_SWCTL] to ‘0’
- CLK_RST_CONTROLLER_SATA_PLL_CFG0_0[SATA_SEQ_START_STATE] to ‘1’
§ Wait 1 µs
§ Program the following CAR registers to enable hardware control of the XUSB Brick’s PLL:
- CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0[XUSBIO_SEQ_ENABLE] to ‘1’
- CLK_RST_CONTROLLER_SATA_PLL_CFG0_0[SATA_SEQ_ENABLE] to ‘1’
Step 3
The PAD driver enables platform specific regulators enable power rails to the pads, VBUS, and pull-up voltage to the VBUS
control PMIC’s EN input.
The PAD driver assigns the USB ports to the controllers, then programs the port capabilities and pad parameters of ports
assigned to XUSB after booting to OS.
§ Program the following XUSB PADCTL registers to assign the USB2.0 ports to XUSB, according to the platform-
specific configuration:
- XUSB_PADCTL_USB2_PAD_MUX_0[USB2_HSIC_PAD_PORT1]
- XUSB_PADCTL_USB2_PAD_MUX_0[USB2_HSIC_PAD_PORT0]
- XUSB_PADCTL_USB2_PAD_MUX_0[USB2_OTG_PAD_PORT2]
§ Program the following XUSB PADCTL registers to assign the port capabilities for USB2.0 ports owned by XUSB,
according to the platform specific configuration:
- XUSB_PADCTL_USB2_PORT_CAP_0[PORT2_CAP] for host/disabled

- XUSB_PADCTL_USB2_PORT_CAP_0[PORT2_INTERNAL] for whether its internal port
§ Program the following XUSB PADCTL registers to ‘0x7’ to disable the overcurrent signal mapping for USB 2.0
ports owned by XUSB:
- XUSB_PADCTL_SNPS_OC_MAP_0[CONTROLLER1_OC_PIN]

USB Complex
- XUSB_PADCTL_USB2_OC_MAP_0[PORT2_OC_PIN]
- XUSB_PADCTL_OC_DET_0[VBUS_ENABLE0_OC_MAP]
§ Program the following XUSB PADCTL registers to assign the SuperSpeed port mapping to USB2.0 ports owned
by XUSB, where the SuperSpeed ports inherit their port capabilities from the USB2.0 ports they mapped to,
according to the platform specific configuration:
- XUSB_PADCTL_SS_PORT_MAP_0[PORT1_MAP]
- XUSB_PADCTL_SS_PORT_MAP_0[PORT0_MAP]
§ Program the following XUSB PADCTL registers to assign the IOPHY lanes to XUSB, PCIE, or SATA, according
to the platform-specific configuration
- XUSB_PADCTL_USB3_PAD_MUX_0[PCIE_PAD_LANE0]
- XUSB_PADCTL_USB3_PAD_MUX_0[SATA_PAD_LANE0]
§ Program the following XUSB PADCTL registers to assign the PAD and PLL parameters of ports owned by
XUSB, according to the platform-specific configuration:
- XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0
- XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0
- XUSB_PADCTL_IOPHY_USB3_PAD0_CTL_1_0
USB Complex
- XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL_1_0
- XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_1_0
- XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0
USB Complex
- XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0
- XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
- XUSB_PADCTL_HSIC_PAD0_CTL_0_0
- XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0
§ Program the following XUSB PADCTL register bits to ‘0’ to disable power down of the PAD:
- XUSB_PADCTL_USB2_BATTERY_CHRG_BIASPAD_0[PD_OTG]
- XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0[PD]
- XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0[PD2]
- XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0[PD_ZI]
- XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0[PD_DR]
- XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0[PD]
- XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0[PD_TRK]
- XUSB_PADCTL_HSIC_PAD0_CTL_1_0[PD_TX]
- XUSB_PADCTL_HSIC_PAD0_CTL_1_0[PD_TRX]
- XUSB_PADCTL_HSIC_PAD1_CTL_1_0[PD_TRX]
- XUSB_PADCTL_HSIC_PAD0_CTL_1_0[PD_RX]
- XUSB_PADCTL_HSIC_PAD1_CTL_1_0[PD_RX]
- XUSB_PADCTL_HSIC_PAD0_CTL_1_0[PD_ZI]
- XUSB_PADCTL_HSIC_PAD1_CTL_1_0[PD_ZI]
§ Program the following XUSB PADCTL register bits to ‘0’ to release the XUSB SS wake logic state latching:
- XUSB_PADCTL_ELPG_PROGRAM_0[SSP0_ELPG_CLAMP_EN]

USB Complex
- XUSB_PADCTL_ELPG_PROGRAM_0[SSP0_ELPG_CLAMP_EN_EARLY]
- XUSB_PADCTL_ELPG_PROGRAM_0[SSP0_ELPG_VCORE_DOWN]
§ Program the following XUSB PADCTL register fields to enable the pad override to put the pad of the lanes
assigned to XUSB in low power mode. These pads should be brought out of low power mode during SS clock
frequency increasing sequence.
- XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL_3_0[RX_IDLE_MODE] to ‘0’
- XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL_3_0[RX_IDLE_MODE_OVRD] to ‘1’
- XUSB_PADCTL_IOPHY_MISC_PAD_P1_CTL_3_0[RX_IDLE_MODE] to ‘0’
- XUSB_PADCTL_IOPHY_MISC_PAD_P1_CTL_3_0[RX_IDLE_MODE_OVRD] to ‘1’
- XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_3_0[RX_IDLE_MODE] to ‘0’
- XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_3_0[RX_IDLE_MODE_OVRD] to ‘1’
Note: To avoid conflict or ambiguity, the XUSB controller should be under reset when updating the port
assignments.
Step 4
The PAD driver programs the clocks and deasserts the resets to the controllers
§ Set the following CAR register bit to ‘1’ to enable the clocks to XUSB:
- CLK_RST_CONTROLLER_CLK_ENB_W_SET_0[SET_CLK_ENB_XUSB]
§ Set the following CAR register bits to ‘1’ to enable the clocks to individual XUSB partitions:
- CLK_RST_CONTROLLER_CLK_ENB_U_SET_0[SET_CLK_ENB_XUSB_HOST]
- CLK_RST_CONTROLLER_CLK_ENB_W_SET_0[SET_CLK_ENB_XUSB_SS]
§ Program the following CAR register bits to set the source of XUSB clocks, where PLLP_OUT0 runs at 408 MHz.
- CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0[XUSB_CORE_HOST_CLK_SRC] to
‘PLLP_OUT0’
- CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0[XUSB_CORE_HOST_CLK_DIVISOR]
to ‘0x6’
- CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0[XUSB_FALCON_CLK_SRC] to
‘PLLP_OUT0’
- CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0[XUSB_FALCON_CLK_DIVISOR] to ‘0x2’
- CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0[XUSB_FS_CLK_SRC] to ‘FO_48M’
- CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0[XUSB_FS_CLK_DIVISOR] to ‘0x0’
- CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0[XUSB_SS_CLK_SRC] to ‘HSIC_480’
- CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0[XUSB_SS_CLK_DIVISOR] to ‘0x6’
§ Set the following CAR register bits to ‘0’ to deassert reset to XUSB:
- CLK_RST_CONTROLLER_RST_DEVICES_U_0[SWR_XUSB_HOST_RST]
- CLK_RST_CONTROLLER_RST_DEVICES_W_0[SWR_XUSB_SS_RST]

USB Complex
Step 5
The PAD driver brings the IOPHY out of IDDQ.
§ Program the following XUSB PADCTL registers to ‘1’ to bring specific lanes of IOPHY out of IDDQ. Only lanes
that are used in the platform are required to be bring out of IDDQ:
- XUSB_PADCTL_USB3_PAD_MUX_0[FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0]
- XUSB_PADCTL_USB3_PAD_MUX_0[FORCE_SATA_PAD_IDDQ_DISABLE_MASK0]
§ Alternatively, program the following XUSB PADCTL register to ‘0’ to bring all lanes of IOPHY out of IDDQ:
- XUSB_PADCTL_USB3_PAD_MUX_0[FORCE_PCIE_PAD_IDDQ_DISABLE]
The PAD driver releases the always on PAD muxing logic state latching.
§ Program the following XUSB PADCTL register bits:
§ Wait 1 µs
- XUSB_PADCTL_ELPG_PROGRAM_0[AUX_MUX_LP0_CLAMP_EN] to ‘0’
§ Wait 100 µs
- XUSB_PADCTL_ELPG_PROGRAM_0[AUX_MUX_LP0_CLAMP_EN_EARLY] to ‘0’
§ Wait 100 µs
- XUSB_PADCTL_ELPG_PROGRAM_0[AUX_MUX_LP0_VCORE_DOWN] to ‘0’
The PAD driver enables the VBUS to the USB ports.
§ Program the following XUSB PADCTL registers to assign the over current signal mapping for USB 2.0 ports
owned by XUSB, according to the platform-specific configuration:
§ Write ‘1’ to the following XUSB PADCTL register bits to clear possible false reporting of overcurrent events
before the over current signal mappings are properly programmed:
- XUSB_PADCTL_OC_DET_0[OC_DETECTED0]

USB Complex
- XUSB_PADCTL_OC_DET_0[OC_DETECTED_VBUS_PAD0]
§ Set the following XUSB PADCTL register bits to ‘1’ to enable the VBUS of the host ports
- XUSB_PADCTL_OC_DET_0[VBUS_ENABLE0]
Step 6
The xHCI PEP driver initializes IPFS registers.
§ Program the following XUSB IPFS registers to allow software accesses to XUSB’s MMIO registers:
- XUSB_HOST_AXI_BAR0_START_0[AXI_BAR0_START] to ‘0x70090’
- XUSB_HOST_AXI_BAR0_SZ_0[AXI_BAR0_SIZE] to ‘0x00008’
- XUSB_HOST_FPCI_BAR0_0[FPCI_BAR0_START] to ‘0x0010000’
- XUSB_HOST_FPCI_BAR0_0[FPCI_BAR0_ACCESS_TYPE] to ‘0’
§ Program the following XUSB IPFS register to enable the XUSB host:
- XUSB_HOST_CONFIGURATION_0[EN_FPCI] to ‘1’
Note: XUSB configuration address mapping is hardcoded in IPFS.
The xHCI PEP driver initializes XUSB’s configuration registers.
§ Program the following XUSB configuration registers to initialize XUSB:
- NV_PROJ__XUSB_CFG_1_BUS_MASTER to ‘1’
- NV_PROJ__XUSB_CFG_1_MEMORY_SPACE to ‘1’
- NV_PROJ__XUSB_CFG_4_BASE_ADDRESS to ‘0x02000’
Step 6
The xHCI PEP driver loads XUSB firmware.
The xHCI driver initializes the host controller.
19.7.6 LP0
19.7.6.1 LP0 Entry

Step 1
The xHCI driver performs a context save operation as described in section 4.23.2 of the xHCI specification.
The xHCI PEP driver performs an XUSB specific context save operation.
The xHCI PEP driver performs an XUSB IPFS specific context save operation.
§ Read and store the value of the following registers
- XUSB_HOST_MSI_BAR_SZ_0
- XUSB_HOST_MSI_AXI_BAR_ST_0
USB Complex
- XUSB_HOST_MSI_FPCI_BAR_ST_0
- XUSB_HOST_MSI_VEC0_0
- XUSB_HOST_MSI_EN_VEC0_0
- XUSB_HOST_FPCI_ERROR_MASKS_0
- XUSB_HOST_INTR_MASK_0
- XUSB_HOST_IPFS_INTR_ENABLE_0
- XUSB_HOST_UFPCI_CONFIG_0
- XUSB_HOST_CLKGATE_HYSTERESIS_0
- XUSB_HOST_XUSB_HOST_MCCIF_FIFOCTRL_0
Step 2
The System Power Management driver programs the PMC USB2.0 sleepwalk logic as described in the “PMC Programming”
section.
The System Power Management driver should enable the wake events according to the port states and Wake-on-Connect,
Wake-on-Disconnect, and Wake-on-Over-Current settings of the XUSB registers ports accordingly.
The System Power Management driver enables wake events from USB ports.
§ Set the following PMC register bits to ‘1’ to set the wake signal active level to ‘HIGH’
- APBDEV_PMC_WAKE2_LVL_0[5] for VBUS wakeup

- APBDEV_PMC_WAKE2_LVL_0[6] for ID wakeup
- APBDEV_PMC_WAKE2_LVL_0[7] for USB2.0 port 0 wakeup
- APBDEV_PMC_WAKE2_LVL_0[10] for HSIC port 0 wakeup
- APBDEV_PMC_WAKE2_LVL_0[11] for HSIC port 1 wakeup
- APBDEV_PMC_WAKE2_LVL_0[26] for USB3.0 ports wakeup
§ Set the following PMC register bits to ‘1’ to enable USB wake events
- APBDEV_PMC_WAKE2_MASK_0[5] for VBUS wakeup

- APBDEV_PMC_WAKE2_MASK_0[6] for ID wakeup
- APBDEV_PMC_WAKE2_MASK_0[7] for USB2.0 port 0 wakeup
- APBDEV_PMC_WAKE2_MASK_0[10] for HSIC port 0 wakeup
- APBDEV_PMC_WAKE2_MASK_0[11] for HSIC port 1 wakeup
- APBDEV_PMC_WAKE2_MASK_0[26] for USB3.0 ports wakeup
Step 3
The system software puts the system in LP0.

USB Complex
19.7.6.2 LP0 Exit

After exiting LP0, the PMC will restore the partition power gating to the state before LP0 entry. This means if a partition was
power gated before entering LP0, that partition would stay power gated after exiting LP0, and only partitions that were
powered before entering LP0 would have their power restored after exiting LP0.
Step 1
The Boot ROM enables USB related PLLs with software override.
The Boot ROM deasserts reset to XUSB PADCTL block.
The system software puts the system in LP0.
Step 2
The PAD driver switches USB related PLLs to under hardware control.
Refer to Step 2 of “Cold Boot”for the programming sequence.
Step 3
The PAD driver assigns the USB port to the controllers, then programs the port capabilities and pad parameters of ports
assigned to XUSB according to the platform specific configuration.
Step 4
The PAD driver programs the clocks and deasserts the resets to the controllers.
§ Wait 1 µs
§ Program the following XUSB PADCTL register bits to ‘0’ to release the XUSB SS wake logic state latching
§ Wait 100 µs.
§ Wait 100 µs
Note: If XUSB was in ELPG before entering LP0 and the LP0 exit is not due to wake event from ports belong to
XUSB, the PAD driver should keep XUSB in the ELPG state and only bring XUSB out of ELPG when wake
events are detected for the ports owned by XUSB.
Step 5
The PAD driver enables the VBUS to the USB ports if VBUS was disabled during LP0.

USB Complex
Step 6
The xHCI PEP driver performs XUSB specific IOPHY context restore for the following registers for the lanes assigned to XUSB
based on the SS port mappings.
§ Program the following XUSB PADCTL register bits with the context stored during the last time the port entered
U0.
- XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL_4_0[DFE_CNTL[28:24]]
- XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL_2_0[RX_EQ[13:8]]
- XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_4_0[DFE_CNTL[28:24]]
- XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_4_0[DFE_CNTL[22:16]]
- XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_2_0[RX_EQ[13:8]]
- XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_2_0[RX_EQ[5:0]]
The xHCI PEP driver performs XUSB specific context restore operation
The xHCI PEP driver performs XUSB IPFS and XUSB register initialization as described in Step 6 of “Cold Boot”.
Step 7
The xHCI PEP Driver loads XUSB firmware.
Step 8
The xHCI driver performs context restore operation as described in section 4.23.2 of the xHCI specification,
Step 9
The System Power Management driver disables the PMC USB2.0 sleepwalk logic as described in the “PMC Programming”
section.

USB Complex
19.7.7 XUSB Controller Power Gating

The following figure illustrates the signal sequences from the PMC that are used by XUSB SS Wake logic to enable its wake
event detection.
XUSB SS Port
Link State XUSB SS
U3/Rx.Detect/SS.Disable/SS.Invalid
master_en1
clamp_en_early2
clamp_en2
vcore_down2
PMC
sys_clken2
pwrreq2
wakeup_rstn2
clamp_en_early3
clamp_en4
XUSB APB Slave
5
vcore_down
reset_
clocks
Clock/Reset/Power
Vaux_core

USB Complex
The following figure illustrates the signal sequences from the XUSB PADCTL block that are required to follow the same
sequence as from the PMC so XUSB SS Wake logic can enable its wake event detection.
XUSB SS Port
Link State XUSB SS
U3/Rx.Detect/SS.Disable/SS.Invalid
master_en1
PMC
wake_int_en5
XUSB APB Slave

clamp_en_early6
clamp_en7
vcore_down8
CAR
xusb_ce3
swr_xusb_rst4
xusb_clamp2
PMC
reset_
clocks
Clock/Reset/Power
Vxusb
The XUSB host controller has two partitions that can be selectively power gated with the following use cases, where unlisted
combinations are not supported:
XUSBC XUSBA Use Case Descriptions

(Host/USB2.0) (SuperSpeed)
Powered Powered Host controller in normal operations, with SuperSpeed links

operational.
Powered Power Gated Host controller in normal operations, with SuperSpeed links
in low power states.
SuperSpeed link wake events report through XUSB
PADCTL.
Power Gated Power Gated Host controllers power gated, with SuperSpeed links in low
power states.
All Host link wake events report through XUSB PADCTL.
19.7.7.1 All Partitions ELPG Entry

Step 1
The xHCI driver performs context save operation as described in section 4.23.2 of the xHCI specification.
The xHCI PEP driver performs XUSB_HOST specific context save operation.
The xHCI PEP driver performs XUSB IPFS specific context save operation.
§ Read and store the value of the following registers
- XUSB_HOST_MSI_BAR_SZ_0
USB Complex
- XUSB_HOST_MSI_AXI_BAR_ST_0
- XUSB_HOST_MSI_FPCI_BAR_ST_0
- XUSB_HOST_MSI_VEC0_0
- XUSB_HOST_MSI_EN_VEC0_0
- XUSB_HOST_FPCI_ERROR_MASKS_0
- XUSB_HOST_INTR_MASK_0
- XUSB_HOST_IPFS_INTR_ENABLE_0
- XUSB_HOST_UFPCI_CONFIG_0
- XUSB_HOST_CLKGATE_HYSTERESIS_0
- XUSB_HOST_XUSB_HOST_MCCIF_FIFOCTRL_0
Step 2
section.
Wake-on-Disconnect, and Wake-on-Over-Current settings of the USB2 ports accordingly.
Step 3
The xHCI PEP driver enables the XUSB wakeup interrupts for the SuperSpeed and USB2.0 ports.
§ Write ‘1’ to the following XUSB PADCTL register bits to clear the interrupt status.
- XUSB_PADCTL_ELPG_PROGRAM_0[SS_PORT0_WAKEUP_EVENT]
- XUSB_PADCTL_ELPG_PROGRAM_0[SS_PORT1_WAKEUP_EVENT]
- XUSB_PADCTL_ELPG_PROGRAM_0[USB2_PORT0_WAKEUP_EVENT]
- XUSB_PADCTL_ELPG_PROGRAM_0[USB2_HSIC_PORT0_WAKEUP_EVENT]
- XUSB_PADCTL_ELPG_PROGRAM_0[USB2_HSIC_PORT1_WAKEUP_EVENT]
§ Set the following XUSB PADCTL register bits to ‘1’ to enable the interrupt.
- XUSB_PADCTL_ELPG_PROGRAM_0[SS_PORT0_WAKE_INTERRUPT_ENABLE]
- XUSB_PADCTL_ELPG_PROGRAM_0[USB2_PORT0_WAKE_INTERRUPT_ENABLE]
- XUSB_PADCTL_ELPG_PROGRAM_0[USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE]
§ Set the following XUSB PADCTL register bits to ‘1’ to disable the output driver of the HSIC pad.

USB Complex
Step 4
The xHCI PEP driver initiates the signal sequence to enable the XUSB SSwake detection logic for the SuperSpeed ports.
§ Write ‘1’ to the following XUSB PADCTL register bits to assert the clamp_en_early signal.
§ Write ‘1’ to the following XUSB PADCTL register bits to assert the clamp_en signal.
§ Wait 250 µs
Note: These two writes must not be combined.
Step 5
System Power Management driver flushes MCCIF and partition clients.
§ Set the following MC register bit to ‘1’ to enable flush to XUSB
- MC_CLIENT_HOTRESET_CTRL_0[XUSB_HOST_FLUSH_ENABLE] for host mode
§ Read the following MC register bit to be ‘1’ to ensure flush to XUSB is enabled
- MC_CLIENT_HOTRESET_STATUS_0[XUSB_HOST_HOTRESET_STATUS] for host mode
Step 6
The System Power Management driver asserts reset to XUSB then disables its clocks.
§ Set the following CAR register bits to ‘1’ to assert reset to XUSB
- CLK_RST_CONTROLLER_RST_DEVICES_U_0[SWR_XUSB_HOST_RST] for host mode

- CLK_RST_CONTROLLER_RST_DEVICES_W_0[SWR_XUSB_SS_RST] for SuperSpeed ports
§ Set the following CAR register bits to ‘1’ to disable the clocks to individual XUSB partitions.
- CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0[CLR_CLK_ENB_XUSB_HOST] for host mode

- CLK_RST_CONTROLLER_CLK_ENB_W_CLR_0[CLR_CLK_ENB_XUSB_SS] for SS ports
Step 7
The System Power Management driver disables the XUSB power rails.
§ Program the following PMC register bits in a single write to disable the power rail to XUSB host:
- APBDEV_PMC_PWRGATE_TOGGLE_0[START] to ‘enable’
- APBDEV_PMC_PWRGATE_TOGGLE_0[PARTID] to ‘XUSBC’
§ Read the following PMC register bit to confirm the power gating status of XUSB host
- APBDEV_PMC_PWRGATE_STATUS_0[XUSBC] equals ‘OFF’
§ Program the following PMC register bits in a single write to disable the power rail to XUSB SuperSpeed:
- APBDEV_PMC_PWRGATE_TOGGLE_0[PARTID] to ‘XUSBA’
§ Read the following PMC register bit to confirm the power gating status of XUSB SuperSpeed:

USB Complex
- APBDEV_PMC_PWRGATE_STATUS_0[XUSBA] equals ‘OFF’
Note: Only one partition can be power gated at a time
Step 8
The xHCI PEP driver initiates the signal sequence to enable the XUSB SS wake detection logic for the SuperSpeed ports
assigned to host.
§ Write ‘1’ to the following XUSB PADCTL register bits to assert the vcore_off signal:
19.7.7.2 Host Mode Partition ELPG Entry

Step 1
The xHCI driver performs context save operation as described in section 4.23.2 of the xHCI specification.
The xHCI PEP driver performs XUSB_HOST specific context save operation.
The xHCI PEP driver performs XUSB IPFS specific context save operation.
Step 2
section.
Wake-on-Disconnect, and Wake-on-Over-Current settings of the USB2 ports accordingly.
Step 3
The xHCI PEP driver enables the XUSB wakeup interrupts for the SuperSpeed and USB2.0 ports.
Step 4
The System Power Management driver flushes MCCIF and partition clients.
§ Set the following MC register bit to ‘1’ to enable flush to XUSB:
§ Read the following MC register bit to be ‘1’ to ensure flush to XUSB is enabled:
- MC_CLIENT_HOTRESET_STATUS_0[XUSB_HOST_HOTRESET_STATUS] for host mode
Step 5
The System Power Management driver asserts reset to XUSB then disables its clocks.
§ Set the following CAR register bit to ‘1’ to assert reset to XUSB
§ Set the following CAR register bits to ‘1’ to disable the clocks to individual XUSB partitions.
- CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0[CLR_CLK_ENB_XUSB_HOST] for host mode
Step 6
The System Power Management driver disables the XUSB power rails.
§ Program the following PMC register bits in a single write to disable the power rail to XUSB host:

USB Complex
§ Read the following PMC register bit to confirm the power gating status of XUSB host:
- APBDEV_PMC_PWRGATE_STATUS_0[XUSBC] equals ‘OFF’
Step 7
The xHCI PEP driver moves the port to be under USB2 controllers as a workaround to use USB2 controller outputs to put the
USB2.0 PADs in low power mode.
§ Program ‘SNPS’ to the following XUSB PADCTL register bits for ports assigned to XUSB:
19.7.7.3 SuperSpeed Partition ELPG Entry

Step 1
The xHCI PEP driver communicates SuperSpeed partition ELPG entry with the System Power Management driver.
Step 2
The xHCI PEP driver enables the XUSB wakeup interrupts for the SuperSpeed ports.
Step 3
The xHCI PEP driver initiates the signal sequence to enable the XUSB SSwake detection logic for the SuperSpeed ports as
described in Step 4 of the “All Partitions ELPG Entry” section.
Step 4
The System Power Management driver asserts reset to XUSB SuperSpeed partition then disables its clocks.
§ Set the following CAR register bit to ‘1’ to assert reset to XUSB:
§ Set the following CAR register bit to ‘1’ to disable the clocks to individual XUSB partitions:
- CLK_RST_CONTROLLER_CLK_ENB_W_CLR_0[CLR_CLK_ENB_XUSB_SS] for SS ports
Step 5
The System Power Management driver disables the XUSB SuperSpeed partition power rails.
§ Read the following PMC register bit to confirm the power gating status of the partitions:
- APBDEV_PMC_PWRGATE_STATUS_0[XUSBA] equals ‘OFF’
Note: Only one partition can be power gated at a time.

USB Complex
Step 6
The xHCI PEP driver initiates the signal sequence to enable the XUSB SS wake detection logic for the SuperSpeed ports as
described in Step 7 of the “All Partitions ELPG Entry” section.
19.7.7.4 All Partitions ELPG Exit

In the case the wake event is not generated by SuperSpeed ports, the SuperSpeed related programming should be skipped,
where the SuperSpeed partition should exit ELPG due to wake events detected by SuperSpeed ports.
Step 1
The xHCI PEP driver moves the USB2.0 port back to XUSB.
§ Program the following XUSB PADCTL registers to assign the USB2.0 ports to XUSB, according to the platform
Step 2
The System Power Management driver enables the XUSB power rails.
§ Program the following PMC register bits in a single write to enable the power rail to XUSB host:
- APBDEV_PMC_PWRGATE_STATUS_0[XUSBC] equals ‘ON’
§ Read the following PMC register bit to confirm the power gating status of XUSB SuperSpeed:
- APBDEV_PMC_PWRGATE_STATUS_0[XUSBA] equals ‘ON’
Note: Only one partition can be un-power gated at a time.
Step 3
The System Power Management driver enables XUSB clocks.
§ Set the following CAR register bits to ‘1’ to enable the clocks to individual XUSB partitions.
- CLK_RST_CONTROLLER_CLK_ENB_U_SET_0[SET_CLK_ENB_XUSB_HOST] for host mode

- CLK_RST_CONTROLLER_CLK_ENB_W_SET_0[SET_CLK_ENB_XUSB_SS] for SS ports
Step 4
The System Power Management driver removes power clamps to XUSB partitions.
§ Set the following PMC register bits to ‘1’ to remove the power clamps to individual XUSB partitions.
- APBDEV_PMC_REMOVE_CLAMPING_CMD_0 [XUSBC] for host mode

USB Complex
- APBDEV_PMC_REMOVE_CLAMPING_CMD_0 [XUSBA] for SS ports
§ Read the following PMC register bits to confirm the power clamps to individual XUSB partitions are removed.
- APBDEV_PMC_REMOVE_CLAMPING_CMD_0 [XUSBC] equals ‘0’

- APBDEV_PMC_REMOVE_CLAMPING_CMD_0 [XUSBA] equals ‘0’
Step 5
The System Power Management driver deasserts reset to XUSB.
§ Set the following CAR register bits to ‘0’ to deassert reset to XUSB:

§ Wait 1 µs
Step 6
The System Power Management driver disables flushes of MCCIF and partition clients.
§ Set the following MC register bits to ‘0’ to enable flush to XUSB:
Step 7
The xHCI PEP driver disables the XUSB wakeup interrupts.
§ Set the following XUSB PADCTL register bits to ‘0’ to disable the interrupts.
Step 8
The xHCI PEP driver initiates the signal sequence to disable the XUSB SS wake detection logic.
§ Write ‘0’ to the following XUSB PADCTL register bits to deassert the vcore_off signal.
§ Wait 100 µs.
§ Write ‘0’ to the following XUSB PADCTL register bits to deassert the clamp_en_early signals.
§ Wait 100 µs.
§ Write ‘0’ to the following XUSB PADCTL register bits to deassert the clamp_en signals.
USB Complex
Note: The write to clear vcore_off cannot be combined with the write to clear clamp_en and clamp_en_early.
Step 9
The xHCI PEP driver performs XUSB register initialization.
The xHCI PEP driver performs XUSB context restore operation.
Step 10
The xHCI PEP driver loads XUSB firmware.
The xHCI PEP driver notifies XUSB firmware whether context of SuperSpeed Partition should be restored.
Step 11
The xHCI driver performs context restore operation as described in section 4.23.2 of the xHCI specification.
Step 12
The System Power Management driver programs the PMC USB2.0 sleepwalk logic to disable the sleepwalk logic as described
in the “PMC Programming” section.
The xHCI PEP driver clears the XUSB wakeup events.
§ Write ‘1’ to the following XUSB PADCTL register bits to clear the events.
- XUSB_PADCTL_ELPG_PROGRAM_0[SS_PORT0_WAKE_EVENT]
- XUSB_PADCTL_ELPG_PROGRAM_0[USB2_PORT0_WAKE_EVENT]
- XUSB_PADCTL_ELPG_PROGRAM_0[USB2_HSIC_PORT0_WAKE_EVENT]
19.7.7.5 Host Mode ELPG Exit

Step 1
The xHCI PEP driver driver moves the USB2.0 port back to XUSB.
§ Program the following XUSB PADCTL registers to assign the USB2.0 ports to XUSB, according to the platform
Step 2
§ Program the following PMC register bits in a single write to enable the power rail to XUSB host:

USB Complex
- APBDEV_PMC_PWRGATE_STATUS_0[XUSBC] equals ‘ON’
Step 3
§ Set the following CAR register bit to ‘1’ to enable the clocks to individual XUSB partitions:
- CLK_RST_CONTROLLER_CLK_ENB_U_SET_0[SET_CLK_ENB_XUSB_HOST] for host mode
Step 4
§ Set the following PMC register bit to ‘1’ to remove the power clamps to individual XUSB partitions:
- APBDEV_PMC_REMOVE_CLAMPING_CMD_0 [XUSBC] for host mode
§ Read the following PMC register bits to confirm the power clamps to individual XUSB partitions are removed.
- APBDEV_PMC_REMOVE_CLAMPING_CMD_0 [XUSBC] equals ‘0’
Step 5
§ Set the following CAR register bit to ‘0’ to deassert reset to XUSB
§ Wait 1 µs
Step 6
The System Power Management driver disables flushes of MCCIF and partition clients.
§ Set the following MC register bits to ‘0’ to enable flush to XUSB
Step 7
The xHCI PEP driver disables the USB2.0wakeup interrupts for ports assigned to XUSB.
Step 8
The xHCI PEP driver performs XUSB register initialization.
The xHCI PEP driver performs XUSB specific context restore operation.

USB Complex
Step 9
The xHCI PEP Driver loads XUSB firmware.
The xHCI PEP Driver notifies XUSB firmware whether context of SuperSpeed Partition should be restored.
Step 10
The xHCI driver performs context restore operation as described in section 4.23.2 of the xHCI specification.
Step 11
The System Power Management driver programs the PMC USB2.0 sleepwalk logic to disable the sleepwalk logic as described
in the “PMC Programming” section.
19.7.7.6 SuperSpeed Partition ELPG Exit

Step 1
The xHCI PEP driver communicates SuperSpeed partition ELPG exit with System Power Management driver.
Step 2
§ Program the following PMC register bits in a single write to disable the power rail to XUSB SuperSpeed
§ Read the following PMC register bits to confirm the power gating status of XUSB SuperSpeed
- APBDEV_PMC_PWRGATE_STATUS_0[XUSBA] equals ‘ON’
Note: Only one partition can be un-power gated at a time
Step 3
§ Set the following CAR register bits to ‘1’ to enable the clocks to individual XUSB partitions.
- CLK_RST_CONTROLLER_CLK_ENB_W_SET_0[SET_CLK_ENB_XUSB_SS] for SS ports
Step 4
The xHCI PEP driver initiates the signal sequence to disable the XUSB SS wake detection logic for the SuperSpeed ports as
described in Step 3 of the “All Partitions ELPG Exit” section.
Step 5
The xHCI PEP driver disable the XUSB SS wakeup interrupts.

USB Complex
Step 6
§ Set the following PMC register bit to ‘1’ to remove the power clamp to XUSB SS:
- APBDEV_PMC_REMOVE_CLAMPING_CMD_0 [XUSBA]
§ Read the following PMC register bits to confirm the power clamp to XUSB SS is removed.
- APBDEV_PMC_REMOVE_CLAMPING_CMD_0 [XUSBA] equals ‘0’
Step 7
§ Set the following CAR register bit to ‘0’ to deassert reset to XUSB:
Step 8
19.7.8 PMC Programming

Sleepwalk logic in the PMC is used for wake event detection of USB2.0 ports, including wake on connect, wake on disconnect,
and remote wakeup.
19.7.8.1 Initialize PMC Sleepwalk Logic

Step 1
The xHCI PEP driver initializes the sleepwalk logic:
§ Set the following registers to ‘0’ to ensure sleepwalk logic is disabled:
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG_0[UTMIP_MASTER_ENABLE_P0]
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG1_0[UTMIP_MASTER_ENABLE_P3]
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG_0[UHSIC_MASTER_ENABLE_P0]
§ Set the following registers to ‘1’ to ensure sleepwalk logic is in low power mode:
- APBDEV_PMC_UTMIP_MASTER_CONFIG_0[UTMIP_PWR_P0]

USB Complex
- APBDEV_PMC_UTMIP_MASTER_CONFIG_0[UHSIC_PWR_P0]
§ Program the following registers to set debounce time:
- APBDEV_PMC_USB_DEBOUNCE_DEL_0[UTMIP_LINE_DEB_CNT]
- APBDEV_PMC_USB_DEBOUNCE_DEL_0[UHSIC_LINE_DEB_CNT]
§ Set the following registers to ‘0’ to ensure fake events of sleepwalk logic are disabled:
- APBDEV_PMC_UTMIP_UHSIC_FAKE_0[UTMIP_FAKE_USBOP_EN_P0]
- APBDEV_PMC_UTMIP_UHSIC_FAKE_0[UTMIP_FAKE_USBON_EN_P0]
- APBDEV_PMC_UTMIP_UHSIC_FAKE_0[UTMIP_FAKE_USBOP_VAL_P0]
- APBDEV_PMC_UTMIP_UHSIC_FAKE_0[UTMIP_FAKE_USBON_VAL_P0]
- APBDEV_PMC_UTMIP_UHSIC2_FAKE_0[UTMIP_FAKE_USBOP_EN_P3]
- APBDEV_PMC_UTMIP_UHSIC2_FAKE_0[UTMIP_FAKE_USBON_EN_P3]
- APBDEV_PMC_UTMIP_UHSIC2_FAKE_0[UTMIP_FAKE_USBOP_VAL_P3]
- APBDEV_PMC_UTMIP_UHSIC2_FAKE_0[UTMIP_FAKE_USBON_VAL_P3]
- APBDEV_PMC_UTMIP_UHSIC_FAKE_0[UHSIC_FAKE_DATA_EN_P0]
- APBDEV_PMC_UTMIP_UHSIC_FAKE_0[UHSIC_FAKE_STROBE_EN_P0]
- APBDEV_PMC_UTMIP_UHSIC_FAKE_0[UHSIC_FAKE_DATA_VAL_P0]
- APBDEV_PMC_UTMIP_UHSIC_FAKE_0[UHSIC_FAKE_STROBE_VAL_P0]
§ Set the following registers to ‘0’ to ensure wake events of sleepwalk logic are not latched:
- APBDEV_PMC_UTMIP_UHSIC_LINE_WAKEUP_0[UTMIP_LINE_WAKEUP_EN_P0]
- APBDEV_PMC_UTMIP_UHSIC_LINE_WAKEUP_0[UHSIC_LINE_WAKEUP_EN_P0]
§ Program the following registers to ‘NONE’ to disable wake event triggers of sleepwalk logic:
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG_0[UTMIP_WAKE_VAL_P0]
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG1_0[UTMIP_WAKE_VAL_P3]
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG_0[UHSIC_WAKE_VAL_P0]

USB Complex
§ Set the following registers to ‘0’ to power down the line state detectors of the pad:
- APBDEV_PMC_USB_AO_0[USBOP_VAL_PD_P0]
- APBDEV_PMC_USB_AO_0[USBON_VAL_PD_P0]
- APBDEV_PMC_USB_AO_0[DATA0_VAL_PD_P0]
- APBDEV_PMC_USB_AO_0[STROBE_VAL_PD_P0]
19.7.8.2 Enable PMC Sleepwalk Logic

Step 1
The xHCI PEP driver re-initializes the sleepwalk logic as described in the “Initialize PMC Sleepwalk Logic” section.
Step 2
The xHCI PEP driver sets up the sleepwalk logic.
§ Program the following registers to match the speed of the port:
- APBDEV_PMC_UTMIP_UHSIC_SAVED_STATE_0[UTMIP_SPEED_P0]
- APBDEV_PMC_UTMIP_UHSIC2_SAVED_STATE_0[UTMIP_SPEED_P3]
- APBDEV_PMC_UTMIP_UHSIC_SAVED_STATE_0[UHSIC_SPEED_P0]
§ Set the following registers to ‘1’ to enable the trigger of the sleepwalk logic:
- APBDEV_PMC_UTMIP_UHSIC_SLEEPWALK_CFG_0[UTMIP_WAKE_WALK_EN_P0]
- APBDEV_PMC_UTMIP_UHSIC_SLEEPWALK_CFG_0[UTMIP_LINEVAL_WALK_EN_P0]
- APBDEV_PMC_UTMIP_UHSIC2_SLEEPWALK_CFG_0[UTMIP_WAKE_WALK_EN_P3]
- APBDEV_PMC_UTMIP_UHSIC2_SLEEPWALK_CFG_0[UTMIP_LINEVAL_WALK_EN_P3]
- APBDEV_PMC_UTMIP_UHSIC_SLEEPWALK_CFG_0[UHSIC_WAKE_WALK_EN_P0]
- APBDEV_PMC_UTMIP_UHSIC_SLEEPWALK_CFG_0[UHSIC_LINEVAL_WALK_EN_P0]
§ Write ‘1’ to the following registers to reset the walk pointer and clear the alarm of the sleepwalk logic, as well as
capture the configuration of the USB2.0 pad:
- APBDEV_PMC_UTMIP_UHSIC_TRIGGERS_0[UTMIP_CLR_WALK_PTR_P0]

USB Complex
- APBDEV_PMC_UTMIP_UHSIC_TRIGGERS_0[UTMIP_CLR_WAKE_ALARM_P0]
- APBDEV_PMC_UTMIP_UHSIC_TRIGGERS_0[UTMIP_CAP_CFG_P0]
- APBDEV_PMC_UTMIP_UHSIC_TRIGGERS_0[UHSIC_CLR_WALK_PTR_P0]
- APBDEV_PMC_UTMIP_UHSIC_TRIGGERS_0[UHSIC_CLR_WAKE_ALARM_P0]
§ Program the following registers with electrical parameters read from XUSB PADCTL:
- APBDEV_PMC_UTMIP_TERM_PAD_CFG_0[TCTRL_VAL] to
XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0[TCTRL]
- APBDEV_PMC_UTMIP_UHSIC_TRIGGERS_0[PCTRL_VAL] to
XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0[PCTRL]
§ Program the following registers to set up the pull-ups and pull-downs of the signals during the four stages of
sleepwalk:
- APBDEV_PMC_UTMIP_SLEEPWALK_P0_0[USBOP_RPD_{A/B/C/D}] to ‘1’
- APBDEV_PMC_UTMIP_SLEEPWALK_P0_0[USBON_RPD_{A/B/C/D}] to ‘1’
- APBDEV_PMC_UTMIP_SLEEPWALK_P0_0[USBOP_RPU_{A/B/C/D}] to ‘0’
- APBDEV_PMC_UTMIP_SLEEPWALK_P0_0[USBON_RPU_{A/B/C/D}] to ‘0’
- APBDEV_PMC_UHSIC_SLEEPWALK_P0_0[STROBE_RPD_A] to ‘0’
- APBDEV_PMC_UHSIC_SLEEPWALK_P0_0[DATA0_RPD_A] to ‘1’
- APBDEV_PMC_UHSIC_SLEEPWALK_P0_0[DATA1_RPD_A] to ‘1’
USB Complex
- APBDEV_PMC_UHSIC_SLEEPWALK_P0_0[STROBE_RPU_A] to ‘1’
- APBDEV_PMC_UHSIC_SLEEPWALK_P0_0[DATA0_RPU_A] to ‘0’
- APBDEV_PMC_UHSIC_SLEEPWALK_P0_0[DATA1_RPU_A] to ‘0’
- APBDEV_PMC_UHSIC_SLEEPWALK_P0_0[STROBE_RPD_{B/C/D}] to ‘1’
- APBDEV_PMC_UHSIC_SLEEPWALK_P0_0[DATA0_RPD_{B/C/D}] to ‘0’
- APBDEV_PMC_UHSIC_SLEEPWALK_P0_0[DATA1_RPD_{B/C/D}] to ‘1’
- APBDEV_PMC_UHSIC_SLEEPWALK_P0_0[STROBE_RPU_{B/C/D}] to ‘0’
- APBDEV_PMC_UHSIC_SLEEPWALK_P0_0[DATA0_RPU_{B/C/D}] to ‘1’
- APBDEV_PMC_UHSIC_SLEEPWALK_P0_0[DATA1_RPU_{B/C/D}] to ‘0’
§ Program the following registers to set up the driving values of the signals during the four stages of sleepwalk:
- APBDEV_PMC_UTMIP_SLEEPWALK_P0_0[AP_A] to ‘0’
- APBDEV_PMC_UTMIP_SLEEPWALK_P0_0[AN_A] to ‘0’
- APBDEV_PMC_UTMIP_SLEEPWALK_P0_0[HIGNZ_A] to ‘0’
- APBDEV_PMC_UTMIP_SLEEPWALK_P0_0[AP_{B/C/D}] to ‘0’ for HS/FS and ‘1’ for LS
- APBDEV_PMC_UTMIP_SLEEPWALK_P0_0[AN_{B/C/D}] to ‘1’ for HS/FS and ‘0’ for LS
- APBDEV_PMC_UTMIP_SLEEPWALK_P0_0[HIGHZ_{B/C/D}] to ‘1’
Note: For HSIC and HSIS+, DATA1 is not used for signaling wake.
Step 3
The xHCI driver puts the ports in the U3 suspend state.

USB Complex
Step 4
The xHCI PEP driver enables the wake event detections.
§ Set the following registers to ‘1’ to power up the line state detectors of the pad
§ Wait 1 µs
§ Set the following registers to ‘1’ to switch the electric control of the USB2.0 pad to PMC
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG_0[UTMIP_FSLS_USE_PMC_P0]
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG_0[UTMIP_PCTRL_USE_PMC_P0]
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG_0[UTMIP_TCTRL_USE_PMC_P0]
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG1_0[UTMIP_FSLS_USE_PMC_P3]
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG1_0[UTMIP_PCTRL_USE_PMC_P3]
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG1_0[UTMIP_TCTRL_USE_PMC_P3]
§ Program the following registers to set the wake signaling trigger events
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG_0[UTMIP_WAKE_VAL_P0] to ‘ANY’
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG1_0[UTMIP_WAKE_VAL_P3] to ‘ANY’
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG_0[UHSIC_WAKE_VAL_P0] to ‘SD10’
§ Set the following registers to ‘1’ to enable the wake detection

USB Complex
Note: For USB2 ports, set wake value to ANY means any line state change would trigger wake.
Note: For HSIC and HSIS+, DATA1 is not used for wake detection.
19.7.8.3 Disable PMC Sleepwalk Logic

Step 1
The xHCI PEP driver disables the wake event detections.
§ Set the following registers to ‘0’ to disable the wake detection:
§ Set the following registers to ‘0’ to switch the electric control of the USB2.0 pad to XUSB or USB2:
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG1_0[UTMIP_FSLS_USE_PMC_P3]
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG1_0[UTMIP_PCTRL_USE_PMC_P3]
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG1_0[UTMIP_TCTRL_USE_PMC_P3]

USB Complex
§ Program the following registers to ‘NONE’ to disable wake event triggers of sleepwalk logic:
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG1_0[UTMIP_WAKE_VAL_P3]
- APBDEV_PMC_UTMIP_UHSIC_SLEEP_CFG_0[UHSIC_WAKE_VAL_P0]
§ Set the following registers to ‘0’ to power down the line state detectors of the pad:
§ Write ‘1’ to the following registers to clear alarm of the sleepwalk logic:
- APBDEV_PMC_UTMIP_UHSIC_TRIGGERS_0[UHSIC_CLR_WAKE_ALARM_P0]
19.8 Recommended PHY Settings

Contact your local NVIDIA representative for PHY settings specific to your design.
19.9 BIAS PAD Configuration

The UTMIP BIAS pad is shared across USB_OTG and USB3 controllers and the below common bias pad settings need to be
configured from the USB1 controller only.
USB1_UTMIP_BIAS_CFG0_0:
§ UTMIP_BIASPD
§ UTMIP_HSCHIRP_LEVEL
§ UTMIP_HSSQUELCH_LEVEL
§ UTMIP_HSDISCON_LEVEL_MSB
§ UTMIP_HSDISCON_LEVEL

USB Complex
§ UTMIP_ACTIVE_TERM_OFFSET
§ UTMIP_ACTIVE_PULLUP_OFFSET
§ UTMIP_VBUS_LEVEL_LEVEL
§ UTMIP_SESS_LEVEL_LEVEL
USB1_UTMIP_BIAS_CFG1_0:
§ UTMIP_FORCE_PDTRK_POWERUP
§ UTMIP_FORCE_PDTRK_POWERDOWN
Following is the sequence to configure above parameters of the BIAS pad:
1. Enable the clock to the USB1 controller
2. Set any of above parameters as required.
3. Disable the clock to the USB1 controller if it is not used.
19.10 BOOT ROM Initialization Sequence for USB Recovery

1. Program PLL_U.
§ Set the PLLU_BASE register fields, PLLU_DIVM, PLLU_DIVN, PLLU_VCO_FREQ, PLLU_BYPASS and
PLLU_ENABLE fields as described in this document.
2. Configure USB_OTG
3. Bring up USB_OTG clocks by writing 1 to CLK_ENB_USBD in the CLK_OUT_ENB_L register.
4. Assert and deassert the master USBD reset in the CAR block (SWR_USBD_RST in the RST_DEVICES_L register)
to bring USB_OTG out of reset.
5. Stop the crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN in the UTMIP_MISC_CFG1 register to 0. This only
stops the crystal clocks in the UTMIP units.
o The default value of USB1_UTMIP_PHY_XTAL_CLOCKEN (= 1) now changes to 0.
o To use the A Session Valid for cable detection logic, set the USB1_VBUS_SENSE_CTL field in the
USB1_LEGACY_CTRL register to A_SESS_VLD (2’b11).
6. Program the automatic PLL start times.
Set USB1_IF_UTMIP_PLLU_ENABLE_DLY_COUNT, UTMIP_PLLU_STABLE_COUNT,

UTMIP_PLL_ACTIVE_DLY_COUNT and UTMIP_XTAL_FREQ_COUNT as per the values given in this
document.
7. Program the tracking duration.
Set USB1_IF_UTMIP_BIAS_CFG1.UTMIP_BIAS_PDTRK_COUNT as per the values given in this document.
8. Program the debouncer length times.
Set UTMIP_DEBOUNCE_CFG0.UTMIP_BIAS_DEBOUNCE_A field.
9. Program various static parameters of the USB_OTG UTMIP1.
o Set UTMIP_TX_CFG0.UTMIP_FS_PREAMBLE_J to 0x1.
o Set UTMIP_BAT_CHRG_CFG0.UTMIP_PD_CHRG to 1.
o Set UTMIP_XCVR_CFG0.UTMIP_XCVR_LSBIAS_SEL to 0.

USB Complex
o Set the third bit of UTMIP_SPARE_CFG0 to 1. i.e., UTMIP_SPARE_CFG0[3] to 1.
o Set UTMIP_HSRX_CFG0. UTMIP_IDLE_WAIT as per the values given in this document.
o Set UTMIP_HSRX_CFG0.UTMIP_ELASTIC_LIMIT to 16.
o Set UTMIP_HSRX_CFG1.UTMIP_HS_SYNC_START_DLY to 9
10. Restart the crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN in the UTMIP_MISC_CFG1 register to 1 for
USB_OTG.
11. Wait for cable connect on the USB_OTG UTMIP1 port. When cable is connected on USB_OTG UTMIP1 port,
continue to the next step.
12. Bring UTMIP1 out of reset by writing 0 to the UTMIP_RESET bit of the USB1_IF_SUSP_CTRL register.
13. Wait until USB1_IF_USB_SUSP_CTRL.PHY_CLK_VALID is set to 1.
14. Then perform USB controller initialization.

a. Reset the bus.
15. Wait until the bus comes out of reset.
16. Set the controller in device mode.
17. Perform USB operations.
19.11 Performance Settings for USB Controllers

To meet USB’s strict bandwidth/latency requirements, some AHB programming needs to be done. The following gives a
guideline on the programming requirements to achieve maximum performance from USB:
§ The burst size for the USB controller should be programmed to 8 in the USB2D_BURSTSIZE register. Both
TXPBURST and RXPBURST fields should be programmed to the same value of 8.
§ The ENB_FAST_REARBITRATE field for AHB_MEM gizmo should be set to 1 in the AHB_GIZMO_AHB_MEM
register.
§ The IMMEDIATE field for USB gizmos should be set to 1 in the AHB_GIZMO_USB, AHB_GIZMO_USB2, or
AHB_GIZMO_USB3 register, depending on the controller in use.
§ USB controllers should be set as high-priority masters on AHB by setting the bits corresponding to each USB
controller to 1 in AHB_PRIORITY_SELECT field in the register AHB_ARBITRATION_PRIORITY_CTRL and
setting the priority weight to 7 by setting the AHB_PRIORITY_WEIGHT field in the same register. USB master
numbers are 6 for USB_OTG, 18 for USB2, and 17 for USB3. The priority weight could be relaxed depending on
requirements from other AHB masters in the system as required for different use cases.
§ The prefetch engine needs to be set up correctly to enable prefetching of transmit data packets for USB masters.
Each USB master needs one channel on the prefetch engine. There are 4 channels on the prefetch engine. If all
3 USB masters enable one channel at the same time, it would leave one more channel for another AHB master.
Each prefetch channel is controlled by the AHB_AHB_MEM_PREFETCH_CFG[NO] register, where NO=1,2,3,4.
To enable prefetch for a USB controller on a channel, program AHB_MST_ID_USB, AHB_MST_ID_USB2, or
AHB_MST_ID_USB3 in the AHB_MST_ID field for the AHB_AHB_MEM_PREFETCH_CFG[NO] register. The
ADDR_BNDRY field should be set to log2 (buffer size) according to the buffer size required for the
corresponding USB master. The SPEC_THROTTLE field should be set to 0, and the INACTIVITY_TIMEOUT
field should be set to 0x800.
§ When a particular USB controller is in Host mode, the TXFIFOTHRES field in the USB2D_TXFILLTUNING
register (offset 0x154) should be set to 0x10.

USB Complex
All this programming needs to be done before the RS bit in USB2D_USBCMD is set to RUN (1) for the corresponding USB
controller.
19.12 USB Controller Handling of USB Resume Sequence

Following are the steps for how the USB controller handles a USB resume while the port is under PMC control:
1. The PMC maintains suspend mode on the bus.
2. When auto resume happens, the system starts restoring the USB controller.
3. Set the RUN bit from the USB controller to start SOFs.
4. The USB controller is brought back to suspend state.
5. Switch the USB bus from the PMC to the USB controller.
6. Wait until a resume complete notification from the USB controller. This is handled by the EHCI driver.
7. Further USB communication can start from here.
19.13 USB Registers

19.13.1 USB 1 Controller Registers
19.13.1.1 USB2_CONTROLLER_USB2D_ID_0
USB2D Identification Register

Offset: 0x0 | Read/Write: RO |Reset: 0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
31:29 X CIVERSION: Identifies the CI version
28:25 X VERSION: Identifies the version of the core
24:21 X REVISION: Revision number of the USB controller. This is set to 0x0.
20:16 X TAG: Identifies the tag of the core
15:8 X NID: One’s complement version of ID. This field is set to 0xF9.
7:0 X ID: Configuration number. This field is set to 0x06
19.13.1.2 USB2_CONTROLLER_USB2D_HW_HOST_0
USB2D Hardware Host Register

Offset: 0x8 | Read/Write: RO | Reset: 0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
3:1 X NPORT: VUSB_HS_NUM_PORT-1: This host controller has only 1 port. So this field will always be 0.
0 X HC: VUSB_HS_HOST: Indicates support for host mode. Set to 1.

USB Complex
19.13.1.3 USB2_CONTROLLER_USB2D_HW_DEVICE_0
USB2D Hardware Device Register

Offset: 0xc | Read/Write: RO | Reset: 0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
DEVEP: VUSB_HS_DV_EP: Number of endpoints supported by this device controller. Set to 16. This
5:1 X
includes control endpoint 0.
0 X DC: Device capable: Set to 1 indicating support for device mode.
19.13.1.4 USB2_CONTROLLER_USB2D_HW_TXBUF_0
USB2D Hardware TX Buffer Register

TXCHANADD: VUSB_HS_TX_CHAN_ADD: Total number of address bits for the transmit buffer of each
23:16 X
transmit endpoint. Set to 7. Each transmit buffer is 128 words deep.
TXADD: VUSB_HS_TX_ADD: Total number of address bits for the transmit buffer. Set to 11. The total
15:8 X
depth of the transmit buffer is 2048 words.
TCBURST: VUSB_HS_TX_BURST: Maximum burst size supported by the transmit endpoints for data
7:0 X
transfers. Set to 8.
19.13.1.5 USB2_CONTROLLER_USB2D_HW_RXBUF_0
USB2D RX Buffer HW Parameters Register

RXADD: VUSB_HS_RX_ADD: Total number of address bits for the receive buffer. Set to 7. The total
15:8 X
depth of the receive buffer is 128 words
RXBURST: VUSB_HS_RX_BURST: Maximum burst size supported by the receive endpoints for data
7:0 X
19.13.1.6 USB2_CONTROLLER_USB2D_GPTIMER0LD_0
The host/device controller drivers can measure time-related activities using these timer registers. These registers are not part
of the standard EHCI controller.
GPTIMER0LD: This field is the value to be loaded into the GPTCNT countdown timer on a reset action.
23:0 0x0
The value in this register represents the time in microseconds minus 1 for the timer duration .
19.13.1.7 USB2_CONTROLLER_USB2D_GPTIMER0CTRL_0
Offset: 0x84 | Read/Write: R/W | Reset: 0x00XXXXXX (0b00xxxxx0xxxxxxxxxxxxxxxxxxxxxxxx)
31 RW 0x0 GTPRUN: This bit enables the general-purpose timer to run. Setting or clearing this bit will not

USB Complex

have an effect on the GPTCNT counter value.
30 WO 0x0 GPTRST: Writing a one to this bit will reload the GPTCNT with the value in GPTLD.
GPTMODE: This bit selects between a single timer countdown and a looped countdown. In one-
shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is
24 RW 0x0
reset by software. In repeat mode, the timer will count down to zero, generate an interrupt, and
automatically reload the counter to begin again.
23:0 RO X GPTCNT: This field is the value of the running timer.
19.13.1.8 USB2_CONTROLLER_USB2D_GPTIMER1LD_0
GPTIMER1LD: This field is the value to be loaded into the GPTCNT countdown timer on a reset action.
23:0 0x0
19.13.1.9 USB2_CONTROLLER_USB2D_GPTIMER1CTRL_0
Offset: 0x8c | Read/Write: R/W | Reset: 0x00XXXXXX (0b00xxxxx0xxxxxxxxxxxxxxxxxxxxxxxx)
GTPRUN: This bit enables the general-purpose timer to run. Setting or clearing this bit will not
31 RW 0x0
30 WO 0x0 GPTRST: Writing a one to this bit will reload the GPTCNT with the value in GPTLD.
shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is
24 RW 0x0
reset by software. In repeat mode, the timer will count down to zero, generate an interrupt, and
automatically reload the counter to begin again.
23:0 RO X GPTCNT: This field is the value of the running timer.
19.13.1.10 USB2_CONTROLLER_USB2D_CAPLENGTH_0
USB2D Capability Register Length Register

CAPLENGTH: Indicates which offset to add to the register base address at the beginning of the
7:0 X
Operational Register. Set to 0x30.
19.13.1.11 USB2_CONTROLLER_USB2D_HCIVERSON_0
USB2D Host Interface Version Number Register

HCIVERSION: Contains a BCD encoding of the EHCI revision number supported by this host controller.
15:0 X The most significant byte of this register represents a major revision and the least significant byte is the
minor revision. This host controller supports EHCI revision 1.00.

USB Complex
19.13.1.12 USB2_CONTROLLER_USB2D_HCSPARAMS_0
USB2D Host Control Structural Parameters Register

N_TT: Number of Transaction Translators: Indicates the number of embedded transaction translators
27:24 X associated with the USB2.0 host controller. This field is always set to 1 indicating only 1 embedded TT
is implemented in this implementation. This is a non-EHCI field to support embedded TT.
N_PTT: Number of Ports per Transaction Translator: Indicates the number of ports assigned to each
23:20 X transaction translator within the USB2.0 host controller. Field always equals N_PORTS. This is a non-
EHCI field to support embedded TT.
N_CC: Number of Companion Controller: Indicates the number of companion controllers. This field is
15:12 X
set to 0.
N_PCC: Number of Ports per Companion Controller: Indicates the number of ports supported per
11:8 X
internal companion controller. This field is set to 0.
PPC: Port Power Control: Indicates whether the host controller implementation includes port power
control.
1 = Ports have port power switches
4 X
0= Ports do not have port power switches.
This field affects the functionality of the port Power field in each port status and control register. This
field is set to 1.
N_PORTS: Number of downstream ports. This field specifies the number of physical downstream ports
3:0 X
implemented on this host controller. This field is fixed to 1, since this host controller only supports 1 port.
19.13.1.13 USB2_CONTROLLER_USB2D_HCCPARAMS_0
USB2D Host Control Capability Parameters Register

PPC: Per-Port Change Event Capability - RO. Default = 1b. This field indicates the support for per-port
18 X change events. This field is related to the USBCMD PPE field, USBSTS PPCI field, and USBINTR PPCE
field.
LEN: Link Power Management Capability - RO. Default = 1b. This field indicates the support for LPM L1
17 X state. This field is related to USBCMD HIRD field, POSTSCx SSTS and DA fields and HOSTPCx LEN,
BA, and EPLPM fields.
EECP: EHCI Extended Capabilities Pointer: Indicates a capabilities list exists. A value of 00h indicates no
15:8 X
extended capabilities are implemented. For this implementation this field is always "0".
IST: Isochronous Scheduling Threshold. This field indicates, relative to the current position of the
executing host controller, where software can reliably update the isochronous schedule. When bit [7] is
zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can
7:4 X
hold a set of isochronous data structures (one or more) before flushing the state. When bit [7] is a one,
then host software assumes the host controller may cache an isochronous data structure for an entire
frame. This field will always be "0".
ASP: Asynchronous Schedule Park Capability. 1 = (Default) the host controller supports the park feature
for high-speed queue heads in the Asynchronous Schedule. The feature can be disabled or enabled and
2 X
set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous
Schedule Park Mode Count fields in the USBCMD register. This field is always 1.
PFL: Programmable Frame List Flag. 0 = System software must use a frame list length of 1024 elements
with this host controller. The USBCMD register Frame List Size field is a read-only register and must be
set to zero. 1 = System software can specify and use a smaller frame list and configure the host
1 X
controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-
page boundary. This requirement ensures that the frame list is always physically contiguous. This field
will always be "1".

USB Complex
19.13.1.14 USB2_CONTROLLER_USB2D_DCIVERSION_0
USB2D Device Interface Version Number Register

DCIVERSION: The device controller interface conforms to the two-byte BCD encoding of the interface
15:0 X
version number contained in this register.
19.13.1.15 USB2_CONTROLLER_USB2D_DCCPARAMS_0
USB2D Device Control Capabilities Register

HC: Host Capable: 1 = This controller can operate as an EHCI compatible USB 2 0 host controller. This
8 X
field is set to 1.
7 X DC: Device Capable: 1 = Controller can operate as a USB 2.0 device. This field is set to 1.
5 X
state. This field is related to the DEVLCx ASUS, STL, BA, and NYT fields.
4:0 X DEN: Device Endpoint Number: Number of endpoints built into the device controller. This is set to 16.
19.13.1.16 USB2_CONTROLLER_USB2D_EXTSTS_0
USB2D EXTSTS Register

Offset: 0x128 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxxxxxxxxxxxxxxx0000x
TI1: General Purpose Timer Interrupt 1 - RWC. Default = 0b. This bit is set when the counter in the
4 RW 0x0
GPTIMER1CTRL register transitions to zero. Writing a one to this bit will clear it.
3 RW 0x0
UPA: USB Host Periodic Interrupt (USBHSTPERINT) R/WC. This bit is set by the Host Controller
when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor
(TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit
is also set by the Host Controller when a short packet is detected AND the packet is on the periodic
2 RW 0x0
schedule. A short packet is when the actual number of bytes received was less than the expected
number of bytes. This bit is not used by the device controller and will always be zero.
0 = DISABLE
1 = ENABLE
UAI: USB Host Asynchronous Interrupt (USBHSTASYNCINT) R/WC. This bit is set by the Host
Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer
Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous
schedule. This bit is also set by the Host when a short packet is detected AND the packet is on the
1 RW 0x0
asynchronous schedule. A short packet is when the actual number of bytes received was less than
the expected number of bytes. This bit is not used by the device controller and will always be zero.
0 = DISABLE
1 = ENABLE
NAKI: NAK Interrupt Bit Read Only. This bit is read only. It is set by hardware when for a particular
endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit
are set. This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK
0 RO X
bits are cleared.
0 = DISABLE
1 = ENABLE

USB Complex
19.13.1.17 USB2_CONTROLLER_USB2D_USBEXTINTR_0
USB2D EXTINTR Register

Offset: 0x12c | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxxxxxxxxxxxxxxx00000
TIE1: General Purpose Timer Interrupt Enable 1 - RWC. Default = 0b. When this bit is a one, and the TI1
4 0x0 bit in the EXTSTS register is a one, the controller will issue an interrupt. The interrupt is acknowledged by
software clearing the TI1 bit.
UPIE: UPIE Interrupt Enable. 1 = USB controller issues an interrupt if the UPA bit in USBSTS register
transitions.
2 0x0
0 = DISABLE
1 = ENABLE
UAIE: UAIE Interrupt Enable. 1 = USB controller issues an interrupt if the UAI bit in USBSTS register
transitions.
1 0x0
0 = DISABLE
1 = ENABLE
NAKE: NAK Interrupt Enable. 1 = USB controller issues an interrupt if the NAKI bit in USBSTS register
transitions.
0 0x0
0 = DISABLE
1 = ENABLE
19.13.1.18 USB2_CONTROLLER_USB2D_USBCMD_0
USB2D USB Command Register

Offset: 0x130 | Read/Write: R/W | Reset: 0bxxxx000000001000000x1x11x0000000
HIRD: Host Initiated Resume Duration RW. Default = 0000b. This has the same behavior as bits
7:4 of the BA field of the HOSTPCx register. When writing to this field all BA[7:4] fields of all
HOSTPCx registers will be set to this value. This field is used by system software to specify the
minimum amount of time the host controller will drive the K-state during a host-initiated resume
from an LPM state (e.g., L1), and is conveyed to each LPM-enabled device (via the HIRD bits
within an LPM Tokens bmAttributes field) upon entry into a low-power state. Note the host
27:24 RW 0x0
controller is required to drive resume signaling for at least the amount of time specified in the
HIRD value conveyed to the device during any proceeding host-initiated resume. Also note that
the host controller is not required to observe this requirement during device-initiated resumes.
Encoding for this field is identical to the definition for the similarly named HIRD field within an
LPM Token, specifically: a value 0000b equals 50 µs and each additional increment adds 75 µs.
For example, the value 0001b equals 125 µs, and the value 1111b equals 1,175 µs (~1.2 ms).
ITC: Interrupt Threshold Control .Read/Write. Default 08h. The system software uses this field to
set the maximum rate at which the host/device controller will issue interrupts. ITC contains the
maximum interrupt interval measured in micro-frames. Valid values are shown below. Value
Maximum Interrupt Interval.
00h: Immediate (no threshold).
01h: 1 micro-frame.
02h: 2 micro-frames.
23:16 RW 0x8 08h: 8 micro-frames.
40h: 64 micro-frames
0 = IMMEDIATE
2 = ONE_MF
4 = TWO_MF
8 = EIGHT_MF
16 = SIXTEEN_MF

USB Complex

32 = THIRTY_TWO_MF
64 = SIXTY_FOUR_MF
15 RW 0x0 FS2: Bit 2 of Frame List Size.
ATDTW: Add DTD Tripwire. This bit is used as a semaphore when a DTD is added to an active
(primed) endpoint. This bit is set and cleared by software and will be cleared by hardware when a
14 RW 0x0 hazard exists such that adding a dTD to a primed endpoint may go unnoticed.
0 = CLEAR
1 = SET
SUTW: Setup Tripwire. This bit is used as a semaphore when the 8 bytes of setup data read
extracted by the firmware. If the setup lockout mode is off, then there exists a hazard when new
setup data arrives and firmware is copying setup data from the queue head (QH) for a previous
13 RW 0x0 setup packet. This bit is set and cleared by software and will be cleared by hardware when a
hazard exists.
0 = CLEAR
1 = SET
ASPE: Asynchronous Schedule Park mode Enable. Software uses this bit to enable or disable
Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is
11 RW 0x1 disabled. This field is set to "1" in this implementation.
0 = DISABLE
1 = ENABLE
ASP1_ASP0: Asynchronous Schedule Park Mode Count (OPTIONAL) Read/Write. If the

Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to
3h and is R/W. Otherwise it defaults to zero and is RO. It contains a count of the number of
successive transactions the host controller is allowed to execute from a high-speed queue head
9:8 RW 0x3
on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid
values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as
this will result in undefined behavior. This field is set to 3h in this implementation and is
Read/Write capable.
LR: Light Host/Device Controller Reset (OPTIONAL). Read Only. Not Implemented. This field will
7 RO X
always be "0".
IAA: Interrupt on Async Advance Doorbell. When the host controller has evicted all appropriate
cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register.
If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host
controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to
zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one.
6 RW 0x0
Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so
will yield undefined results. This bit is only used in host mode. Writing a one to this bit when
device mode is selected will have undefined results.
0 = CLEAR
1 = SET
ASE: Asynchronous Schedule Enable. This bit controls whether the host controller skips
processing the Asynchronous Schedule. 0 = Do not process the Asynchronous Schedule. 1 =
Use the ASYNCLISTADDR register to access the Asynchronous Schedule. Only the host
5 RW 0x0
controller uses this bit.
0 = DISABLE
1 = ENABLE
PSE: Periodic Schedule Enable. This bit controls whether the host controller skips processing the
Periodic Schedule. 0 = Do not process the Periodic Schedule 1 = Use the PERIODICLISTBASE
4 RW 0x0 register to access the Periodic Schedule. Only the host controller uses this bit.
0 = DISABLE
1 = ENABLE
FS1_FS0: Frame List Size. (Read/Write). 000 = (Default). This field is Read/Write only if the
Programmable Frame List Flag in the HCCPARAMS registers is set to one. Hence this field is
Read/Write for this implementation. This field specifies the size of the frame list that controls
which bits in the Frame Index Register should be used for the Frame List Current index. Note that
3:2 RW 0x0 this field is made up from USBCMD bits 15, 3, and 2.
000 = 1024 elements (4096 bytes) Default value
001 = 512 elements (2048 bytes)

USB Complex

Only the host controller uses this field.
RST: Controller Reset. Software uses this bit to reset the controller. This bit is set to zero by the
Host/Device Controller when the reset process is complete. Software cannot terminate the reset
process early by writing a zero to this register.
Host Controller: When software writes a one to this bit, the Host Controller resets its internal
pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in
progress on USB is immediately terminated. A USB reset is not driven on downstream ports.
Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero.
1 RW 0x0
Attempting to reset an actively running host controller results in undefined behavior.
Device Controller: When software writes a one to this bit, the Device Controller resets its internal
pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in
progress on USB is immediately terminated. Writing a one to this bit in device mode is not
recommended.
0 = CLEAR
1 = SET
RS: Run/Stop: Host Controller: When set to a 1, the Host Controller proceeds with the execution
of the schedule. The Host Controller continues execution as long as this bit is set to a one. When
this bit is set to 0, the Host Controller completes the current transaction on the USB and then
halts. The HCHalted bit in the status register indicates when the Host Controller has finished the
transaction and has entered the stopped state. Software should not write a one to this field unless
the host controller is in the Halted state (i.e., HCHalted in the USBSTS register is a one).
0 RW 0x0 Device Controller: Writing a one to this bit will cause the device controller to enable a pull-up on
D+ and initiate an attach event. This control bit is not directly connected to the pull-up enable, as
the pull-up will become disabled upon transitioning into high-speed mode. Software should use
this bit to prevent an attach event before the device controller has been properly initialized.
Writing a 0 to this will cause a detach event.
0 = STOP
1 = RUN
19.13.1.19 USB2_CONTROLLER_USB2D_USBSTS_0
USB2D USB Status Register

Offset: 0x134 | Read/Write: R/W | Reset: 0b000000000000000000x100x0000x0000
PPCI: Port-n Change Detect - RW. Default = 0000h. The definition for each bit is identical to the
Port Change Detect field (bit 2 of this register) except these bits are specific to a given port,
31:16 RW 0x0 where bit 16 = Port 1, 17 = Port 2, etc. For example, if bit 17 is set to a one then a port change
event was detected on Port 2. The N_PORTS field in HCSPARAMS specifies how many ports
are exposed by the host controller and thus how many bits in this field are valid.
AS: Asynchronous Schedule Status. This bit reports the current real status of the Asynchronous
Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the
status is enabled. The Host Controller is not required to immediately disable or enable the
Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the
15 RW 0x0
USBCMD register. If AS = ASE: 1= Enable Asynchronous Schedule. 0= Disable Asynchronous
Schedule. Only used by the host controller.
0 = DISABLE
1 = ENABLE
PS: Periodic Schedule Status. This bit reports the current real status of the Periodic Schedule.
When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The
Host Controller is not required to immediately disable or enable the Periodic Schedule when
software transitions the Periodic Schedule Enable bit in the USBCMD register. If PS = PSE then:
14 RW 0x0
1 = Periodic Schedule is enabled or 0 = Periodic Schedule is disabled. Only used by the host
controller.
0 = DISABLE
1 = ENABLE

USB Complex
RCL: Reclamation. This is a read-only status bit used to detect an empty asynchronous schedule.
Only used by the host controller.
13 RO X
0 = DISABLE
1 = ENABLE
HCH: HCHalted. 1 = Default. This bit is a zero whenever the Run/Stop bit is a one. The Host
Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set
to 0, either by software or by the Host Controller hardware (e.g., internal error). Only used by the
12 RW 0x1
host controller.
0 = UNHALTED
1 = HALTED
UALT_INT: ULPI alt_int Interrupt. 0 = Default. This interrupt bit is set when an RXCMD is
received through the ULPI interface with bit 7 set (alt_int).The alt_int itself is set when an
unmasked event occurs on any bit in the Carkit Interrupt Latch Register, in the ULPI PHY The
software should read the Carkit Interrupt Latch Register (Read to Clear) through the ULPI
11 RW 0x0 Viewport to check the source of the interrupt. Only present in designs where configuration
constant VUSB_HS_PHY_ULPI = 1.
0 = NOT_ULPI_ALT_INT
1 = ULPI_ALT_INT
ULPI_INT: ULPI Interrupt. This bit is set whenever an interrupt is received from ULPI PHY.
Software writes 1 to clear it.
10 RW 0x0
0 = NOT_ULPI_INT
1 = ULPI_INT
SLI: DCSuspend. When a device controller enters a suspend state from an active state, this bit
will be set to a 1. The device controller clears the bit upon exiting from a suspend state. Only
8 RW 0x0 used by the device controller.
0 = NOTSUSPEND
1 = SUSPENDED
SRI: SOF Received. When the device controller detects a Start Of (micro) Frame, this bit will be
set to a one. When an SOF is extremely late, the device controller will automatically set this bit to
indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS
mode and every 125 µs in HS mode and will be synchronized to the actual SOF that is received.
Since the device controller is initialized to FS before connect, this bit will be set at an interval of
7 RW 0x0
1 ms during the prelude to the connect and chirp. In host mode, this bit will be set every 125 µs
and can be used by the host controller driver as a time base. Software writes a 1 to this bit to
clear it. This is a non-EHCI status bit.
0 = SOF_NOT_RCVD
1 = SOF_RCVD
URI: USB Reset Received. When the device controller detects a USB Reset and enters the
default state, this bit is set to a 1. Software can write a 1 to this bit to clear the USB Reset
6 RW 0x0 Received status bit. Only used by the device controller.
0 = NO_USB_RESET
1 = USB_RESET
AAI: Interrupt and Asynchronous Advance. System software can force the host controller to issue
an interrupt the next time the host controller advances the asynchronous schedule by writing a
one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit
5 RW 0x0
indicates the assertion of that interrupt source. Only used by the host controller
0 = NOT_ADVANCED
1 = ADVANCED
SEI: System Error. This bit is not used in this implementation and will always be set to "0".
4 RO X 0 = NO_ERROR
1 = ERROR
FRI: Frame List Rollover. The Host Controller sets this bit to a 1 when the Frame List Index rolls
over from its maximum value to 0. The exact value at which the rollover occurs depends on the
frame list size. For example. If the frame list size (as programmed in the Frame List Size field of
the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [1 3]
3 RW 0x0
toggles. Similarly, if the size is 512, the Host Controller sets this bit to a 1 every time FHINDEX
[12] toggles. Only used by the host controller.
0 = NO_ROLLOVER
1 = ROLLOVER

USB Complex
PCI: Port Change Detect. The Host Controller sets this bit to a 1 when on any port a Connect
Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the
result of a J-K transition on the suspended port. The Device Controller sets this bit to a one when
the port controller enters the full or high-speed operational state. When the port controller exits
2 RW 0x0 the full or high-speed operational states due to Reset or Suspend events, the notification
mechanisms are the USB Reset Received bit and the DCSuspend bits, respectively. This bit is
not EHCI compatible.
0 = NO_PORT_CHANGE
1 = PORT_CHANGE
UEI: USB Error Interrupt. This bit gets set by the Host/Device controller when completion of a
USB transaction results in an error condition. This bit is set along with the USBINT bit, if the TD
1 RW 0x0 on which the error interrupt occurred also had its interrupt on complete (IOC) bit set.
0 = NO_ERROR
1 = ERROR
UI: USB Interrupt. This bit is set by the Host/Device Controller when the cause of an interrupt is a
completion of a USB transaction where the Transfer Descriptor (TD) as an interrupt on complete
(IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A
0 RW 0x0 short packet is when the actual number of bytes received was less than the expected number of
bytes.
0 = NO_INT
1 = INT
19.13.1.20 USB2_CONTROLLER_USB2D_USBINTR_0
USB2D USB Interrupt Enable Register

Offset: 0x138 | Read/Write: R/W | Reset: 0b0000000000000000xxxx00x000000000
PPCE: Port-n Change Detect Enable - RW. Default = 0000h. The definition for each bit in this field is
identical to bit 2 of this register (Port Change Interrupt Enable) except these bits are specific to a given
port, where bit 16 = Port 1, 17 = Port 2, etc. For example, if bit 17 is set (1b) then a port change event
31:16 0x0
was detected on Port 2. When a bit in this field is a one, and the corresponding Port-n Change Detect
bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is
acknowledged by software clearing the Port-n Change Detect bit.
UALTIE: ULPI alt_int Interrupt Enable. 1 = USB controller issues an interrupt if the ULPI_ALT_INT bit in
the USBSTS register transitions. The interrupt is acknowledged by software by writing a 1 to the
11 0x0 ULPI_ALT_INT bit.
0 = DISABLE
1 = ENABLE
ULPIE: ULPI Interrupt Enable. 1 = USB controller issues an interrupt if ULPI_INT bit in USBSTS register
transitions. The interrupt is acknowledged by software by writing a 1 to the ULPI_INT bit.
10 0x0
0 = DISABLE
1 = ENABLE
SLE: Sleep Enable. 1 = Device controller issues an interrupt if DCSuspend bit in USBSTS register
transitions. The interrupt is acknowledged by software by writing a 1 to the DCSuspend bit. Only used
8 0x0 by the device controller.
0 = DISABLE
1 = ENABLE
SRE: SOF Received Enable. 1 = Device controller issues an interrupt if SOF Received bit in USBSTS
register = 1. The interrupt is acknowledged by software clearing the SOF Received bit.
7 0x0
0 = DISABLE
1 = ENABLE
URE: USB Reset Enable.1 = Device controller issues an interrupt if USB Reset Received bit in USBSTS
register = 1. The interrupt is acknowledged by software clearing the USB Reset Received bit. Only used
0 = DISABLE
1 = ENABLE

USB Complex
AAE: Interrupt on Asynchronous Advance Enable. 1 = The host controller issues an interrupt at the next
interrupt threshold if Interrupt on Async Advance bit in USBSTS register = 1. The interrupt is
5 0x0 acknowledged by software clearing the Interrupt on Async Advance bit. Only used by the host controller.
0 = DISABLE
1 = ENABLE
SEE: System Error Enable. 1 = Host/device controller issues an interrupt if the System Error bit in
USBSTS register = 1. The interrupt is acknowledged by software clearing the System Error bit.
4 0x0
0 = DISABLE
1 = ENABLE
FRE: Frame List Rollover Enable. 1 = Host controller issues an interrupt if Frame List Rollover bit in the
USBSTS register = 1. The interrupt is acknowledged by software clearing the Frame List Rollover bit.
3 0x0 Only used by the host controller.
0 = DISABLE
1 = ENABLE
PCE: Port Change Detect Enable. 1 = Host/device controller issues an interrupt if Port Change Detect
bit in USBSTS register = 1. The interrupt is acknowledged by software clearing the Port Change Detect
2 0x0 bit.
0 = DISABLE
1 = ENABLE
UEE: USB Error Interrupt Enable. 1 = Host controller issues an interrupt at the next interrupt threshold if
the USBERRINT bit in USBSTS = 1. The interrupt is acknowledged by software clearing the
1 0x0 USBERRINT bit in the USBSTS register.
0 = DISABLE
1 = ENABLE
UE: USB Interrupt Enable. 1 = Host/device issues an interrupt at the next interrupt threshold if the
USBINT bit in USBSTS = 1. The interrupt is acknowledged by software clearing the USBINT bit.
0 0x0
0 = DISABLE
1 = ENABLE
19.13.1.21 USB2_CONTROLLER_USB2D_FRINDEX_0
USB2D USB Frame Index Register

Offset: 0x13c | Read/Write: RO | Reset: 0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
FRINDEX: Frame Index. The value in this register increments at the end of each time frame (micro-
frame). Bits [N: 3] are used for the Frame List current index. Each location of the frame list is accessed 8
times (frames or micro-frames) before moving to the next index. The following illustrates values of N
based on the value of the Frame List Size field in the USBCMD register, when used in host
mode. USBCMD [Frame List Size] Number Elements N
000b (1024) 12
001b (512) 11
13:0 X 010b (256) 10
011b (128) 9
100b (64) 8
101b (32) 7
110b (16) 6
111b (8) 5
In device mode, the value is the current frame number of the last frame transmitted. It is not used as an
index. In either mode bits 2:0 indicate the current micro-frame.

USB Complex
19.13.1.22 USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0
USB2D Host Controller Frame List Base Address Register

Offset: 0x144 | Read/Write: R/W | Reset: 0b00000000000000000000xxxxxxxxxxxx
USBADR: Device mode. The upper seven bits of this register represent the device address. After any
controller reset or a USB reset, the device address is set to the default address (0). The default address
31:25 0x0
will match all incoming addresses. Software shall reprogram the address after receiving a
SET_ADDRESS request.
USBADRA: Device Address Advance. Default=0. When this bit is 0, any writes to USBADR are
instantaneous. When this bit is written to a 1 at the same time or before USBADR is written, the write to
the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is
ACKed, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on
the following conditions:
1) IN is ACKed to endpoint 0. (USBADR is updated from staging register).
24 0x0 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated).
3) Device Reset occurs (USBADR is reset to 0).
Note: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the
USBADR field. This mechanism will ensure this specification is met when the DCD cannot write of the
device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with
USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the
USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement.
BASEADR: Host mode: This 32-bit register contains the beginning address of the Periodic Frame List in
the system memory. The HCD loads this register prior to starting the schedule execution by the Host
Controller. The memory structure referenced by this physical memory pointer is assumed to be 4-Kbyte
31:12 0x0
aligned. The contents of this register are combined with the Frame Index Register (FRINDEX) to enable
the Host Controller to step through the Periodic Frame List in sequence. Base Address (Low). These
bits correspond to memory address signals [31:12], respectively. Only used by the host controller.
19.13.1.23 USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0
USB2D Next Asynchronous List Address Register

Offset: 0x148 | Read/Write: R/W | Reset: 0b000000000000000000000000000xxxxx
EPBASE: Device mode. This register contains the address of the top of the endpoint list in system
31:11 0x0 memory. These bits correspond to memory address signals [31:11], respectively. This field will
reference a list of up to 32 Queue Heads (QHs). Only used by the device controller.
ASYBASE: Host mode. This 32-bit register contains the address of the next asynchronous queue head
31:5 0x0 to be executed by the host. Link Pointer Low (LPL). These bits correspond to memory address signals
[31:5], respectively. This field may only reference a Queue Head (OH). Only used by the host controller.
19.13.1.24 USB2_CONTROLLER_USB2D_ASYNCTTSTS_0
USB2D Asynchronous Buffer Status for Embedded TT Register

Offset: 0x14c | Read/Write: R/W | Reset: 0bx0000000xxxxxxxxxxxxxxxxxxxxxx0x
30:24 RW 0x0 TTHA: Internal TT Hub Address representation. This field is used to match the Hub Address field
in Queue Head (QH) and split isochronous transaction descriptor (siTD) to determine if the packet
is routed to the internal transaction translator (TT) for directly attached FS/LS devices. If the Hub
Address in the QH or siTD does not match this address then the packet will be broadcast on the
High Speed ports destined for a downstream High Speed hub with the address in QH/siTD.
1 RW 0x0 TTAC: Embedded TT Async Buffers Clear. (Read/Write to set). This field will clear all pending
transactions in the embedded TT Async Buffer(s). The clear will take as much time as necessary

USB Complex

to clear buffer without interfering with a transaction in progress. TTAC will return to zero after
being set by software only after the actual clear occurs.
TTAS: Embedded TT Async Buffers Status. (Read Only). This read only bit will be 1 if one or
0 RO X more transactions are being held in the embedded TT Async. Buffers. When this bit is a zero,
then all outstanding transactions in the embedded TT have been flushed.
19.13.1.25 USB2_CONTROLLER_USB2D_BURSTSIZE_0
USB2D Burst Size Register

Offset: 0x150 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxxxx0000100000001000
TXPBURST: Programmable TX Burst Length. (Read/Write). This register represents the maximum length
15:8 0x8
of a burst in 32-bit words while moving data from system memory to the USB bus.
RXPBURST: Programmable RX Burst Length. (Read/Write). This register represents the maximum
7:0 0x8
length of a burst in 32-bit words while moving data from the USB bus to system memory.
19.13.1.26 USB2_CONTROLLER_USB2D_TXFILLTUNING_0
USB2D Transmit Fill Tuning Register

Offset: 0x154 | Read/Write: R/W | Reset: 0bxxxxxxxxxx000010xxx0000000000000
TXFIFOTHRES: FIFO Burst Threshold. (Read/Write). This register controls the number of data bursts
that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The
minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher
21:16 0x2 value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO
may underrun because the data transferred from the latency FIFO to USB occurs before it can be
replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register
is set.
TXSCHHEALTH: Scheduler Health Counter. (Read/Write To Clear) [Default = 0] This register

increments when the host controller fails to fill the TX latency FIFO to the level programmed by
12:8 0x0 TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This
health counter measures the number of times this occurs to provide feedback to selecting a proper
TXSCHOH. Writing to this register will clear the counter and this counter will max out at 31.
TXSCHOH: Scheduler Overhead. (Read/Write) [Default = 0] This register adds an additional fixed offset
to the schedule time estimator described above as Tff. As an approximation, the value chosen for this
register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per
7:0 0x0 second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can
needlessly reduce USB utilization. The time unit represented in this register is 1.267 µs when a device
is connected in High-Speed Mode. The time unit represented in this register is 6.333 µs when a device
is connected in Low/Full Speed Mode
19.13.1.27 USB2_CONTROLLER_USB2D_ICUSB_CTRL_0
This register enables and controls the ICUSB FS/LS transceiver.
USB2D ICUSB control register

Offset: 0x15c | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000
IC_ENB1: ICUSB transceiver enable. This bit enables the ICUSB transceiver. To enable the interface, the
3 0x0 bits PTS must be set to 11 in the PORTSCx. Writing a '1' to this bit selects the IC_USB interface.
0 = DISABLE

USB Complex

1 = ENABLE
IC_VDD1: ICUSB voltage select. It selects which voltage is being supplied to the ICUSB peripheral.
000 = No voltage
001 = 1.0V - reserved
2:0 0x0 100 = 1.8V
101 = 3.0V
110 = reserved
111 = reserved
The Voltage negotiation should happen between enabling port power (PP) and asserting the run/stop bit in
register.
19.13.1.28 USB2_CONTROLLER_USB2D_ULPI_VIEWPORT_0
This register provides indirect access to the ULPI PHY register set. Although the USB controller performs access to the ULPI
PHY register set, there may be extraordinary circumstances where software may need direct access.
Note: WRITES TO THE ULPI THROUGH THE VIEWPORT CAN SUBSTANTIALLY HARM STANDARD USB
OPERATIONS. CURRENTLY NO USAGE MODEL HAS BEEN DEFINED WHERE SOFTWARE SHOULD
NEED TO EXECUTE WRITES DIRECTLY TO THE ULPI PHY. SEE EXCEPTION REGARDING
OPTIONAL FEATURES BELOW.
Note: Executing read operations through the ULPI Viewport should have no harmful side effects to standard USB
operations.
There are two operations that can be performed with the ULPI Viewport: wakeup and read /write operations.
The wakeup operation is used to put the ULPI interface into normal operation mode and reenable the clock if necessary. A
wakeup operation is required before accessing the registers when the ULPI interface is operating in low power mode, serial
mode, or carkit mode.
The ULPI state can be determined by reading the sync state bit (ULPI_SYNC_STATE). If this bit is a one, then ULPI interface
is running in normal operation mode and can accept read/write operations. If the ULPI_SYNC_STATE indicates a 0 then then
read/write operations will not be able to execute. Undefined behavior will result if ULPI_SYNC_STATE = 0 and a read or write
operation is performed.
To execute a wakeup operation, write all 32-bits of the ULPI Viewport where ULPI_PORT is constructed appropriately and the
ULPI_WAKEUP bit is a 1 and ULPI_RUN bit is a 0. Poll the ULPI Viewport until ULPI_WAKEUP is zero for the operation to
complete.
To execute a read or write operation, write all 32 bits of the ULPI Viewport where ULPI_DATA_WR, ULPI_REG_ADDR,
ULPI_PORT, ULPI_RD_WR are constructed appropriately and the ULPI_RUN bit is a 1. Poll the ULPI Viewport until
ULPI_RUN is zero for the operation to complete. Once ULPI_RUN is zero, the ULPI_DATA_RD will be valid if the operation
was a read.
The polling method above can be changed to interrupt driven using the ULPI interrupt defined in the USBSTS and USBINTR
registers. When a wakeup or read/write operation is complete, the ULPI_INT interrupt will be set.
There are several optional features that may need to be enabled or disabled by system software as part of system
configuration. These bits are contained in the Interface and OTG Control registers of the ULPI PHY register set. These
registers also contain bits which are controlled by the link dynamically and therefore should be only modified by system
software using the Set/Clear access method. Direct writes to these registers could have harmful side effects to the standard
USB operations. The optional bits are as follows: Bits 3 through 7 in the Interface Control register and Bits 6 and 7 in the OTG
Control register.
Please refer to the ULPI Specification Revision 1.1 for further information on the use of the optional features.

USB Complex
USB2D ULPI Viewport Register

Offset: 0x160 | Read/Write: R/W | Reset: 0b000xx00000000000xxxxxxxx00000000
ULPI_WAKEUP: ULPI Wakeup. Writing the 1 to this bit will begin the wakeup operation. The bit
will automatically transition to 0 after the wakeup is complete. Once this bit is set, the driver
cannot set it back to 0. Note: The driver must never execute a wakeup and a read/write operation
31 RW 0x0
at the same time.
0 = CLEAR
1 = SET
ULPI_RUN: ULPI read/write Run. Writing the 1 to this bit will begin the read/write operation. The
bit will automatically transition to 0 after the read/write is complete. Once this bit is set, the driver
30 RW 0x0
at the same time.
0 = CLEAR
1 = SET
ULPI_RD_WR: ULPI read/write control. (0) Read; (1) Write. This bit selects between running a
read or write operation.
29 RW 0x0
0 = READ
1 = WRITE
ULPI_SYNC_STATE: ULPI sync state. (1) Normal Sync. State. (0) In another state (i.e., carkit,
serial, low power). This bit represents the state of the ULPI interface.
27 RO X
0 = NOT_NORMAL
1 = NORMAL
26:24 RW 0x0 ULPI_PORT: ULPI PHY port number. This field should be always written as 0.
ULPI_REG_ADDR: ULPI PHY register address. When doing a read or write operation to the ULPI
23:16 RW 0x0
PHY, the address of the ULPI PHY register being accessed is written to this field.
ULPI_DATA_RD: ULPI PHY data read. The data from the ULPI PHY register can be read from
15:8 RO X
here after the read operation completes.
ULPI_DATA_WR: ULPI PHY data write. The data to write to the ULPI PHY register is written
7:0 RW 0x0
here.
19.13.1.29 USB2_CONTROLLER_USB2D_PORTSC1_0
USB2D Port Status/Control 1 Register

Offset: 0x174 | Read/Write: R/W | Reset: 0b0000000xx0000000xxx1xx00x0xx010x
DA: Device Address - RW. Default = 0000000b. The 7-bit USB device address for the device
attached to an immediately downstream of the associated root port. A value of zero indicates no
31:25 RW 0x0 device is present or software support for this feature is not present. This is used by the Controller
when sending the LPM token. This field is only valid when the core is operating in host mode. If in
device mode it will be read only and always equal to 0000000b.
SSTS: Suspend Status - RO. Default = 00b. These two bits are used by software to determine
whether an L1-based suspend request was successful, specifically:
00b - L1 state entered with success. ACK received from peripheral.
01b - NYET received from peripheral. It was not able to enter L1 state this time.
10b - L1 state not supported by peripheral. STALL received.
11b - Peripheral did not respond or an error occurred.
The value of this field is only valid when the port resides in the L0 state - that is, the meaning of
24:23 RO X these bits is invalid whenever bit 7 of this register (SUSP) is one. Ideally, the Controller driver
should read this register if it receives an interrupt after issuing a suspend using L1 support. In
case of a non-success a port change interrupt will be fired and this field should be checked for a
possible L1 failure. This field is only valid when the core is operating in host mode. If in device
mode, it will be always equal to 00b.
0 = L1STATE_ENTERED
1 = NYET_PERIPH
2 = L1STATE_NOT_SUPPORTED

USB Complex

3 = PERIPH_NORESP_ERR
WKOC: Default = 0b. Wake on Over-current Enable: Writing this bit to a one enables the port to
be sensitive to over-current conditions as wake-up events. This field is zero if Port Power (PP) is
zero. This bit should only be used when operating in Host mode. Writing this bit to 1 while the
22 RW 0x0
controller is working in device mode can result in undefined behavior.
0 = DISABLE
1 = ENABLE
WKDS: Wake on Disconnect Enable: Writing this bit to a one enables the port to be sensitive to
device disconnects as wake-up events. This field is zero if Port Power (PP) is zero or in device
mode. This bit should only be used when operating in Host mode. Writing this bit to 1 while the
controller is working in device mode can result in undefined behavior. This bit should not be
21 RW 0x0
written to 1 if there is no device connected. After the device disconnect is detected, this bit should
be cleared to 0.
0 = DISABLE
1 = ENABLE
WKCN: Wake on Connect Enable: Writing this bit to a one enables the port to be sensitive to
device connects as wake-up events. This field is zero if Port Power (PP) is zero or in device
20 RW 0x0
written to 1 while the device is connected. After the device connection is detected, this bit should
be cleared to 0.
0 = DISABLE
1 = ENABLE
PTC: Port Test Control: Any value other than zero indicates that the port is operating in test
mode. Value Specific Test.
0000b: Not enabled.
0001b: J_ STATE.
0010b: K_STATE.
0011b: SEQ_NAK.
0100b: Packet.
0101b: FORCE_ENABLE.
19:16 RW 0x0 0110b to 1111b: Reserved. | Refer to Chapter 7 of the USB Specification Revision 2.0 for details
on each test mode.
0 = NORMAL_OP
1 = TEST_J
2 = TEST_K
3 = TEST_SE0_NAK
4 = TEST_PKT
5 = TEST_FORCE_ENABLE
PIC: Port Indicator Control: This field is not supported in the current implementation. Please use a
15:14 RO X
GPIO if you wish to use Port Indicators.
PO: Port Owner. Port owner handoff is not implemented in this design, therefore this bit will
13 RO X
always be 0.
PP: Port Power: The function of this bit depends on the value of the Port Power Switching (PPC)
field in the HCSPARAMS register. The behavior is as follows:
PPC PP Operation
0b 0b Read Only. A device controller with no OTG capability does not have port
power control switches.
1b 1b/0b RW. Host/OTG controller requires port power control switches.
12 RW 0x1
This bit represents the current setting of the switch (0=off, 1=on). When power is not available on
a port (i.e., PP equals a 0), the port is non-functional and will not report attaches, detaches, etc.
When an over-current condition is detected on a powered port and PPC is a one, the PP bit in
each affected port may be transitioned by the host controller driver from a one to a zero
(removing power from the port).
0 = NOT_POWERED
1 = POWERED

USB Complex
LS: These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. The
encoding of the bits is:
00b = SE0.
01b = K-state.
10b = L-state.
11b = Undefined.
11:10 RO X The value of this field is undefined if Port Power (PP) is zero in host mode. In host mode, the use
of line-state by the host controller driver is not necessary (unlike EHCI), because the port
controller state machine and the port routing manage the connection of LS and FS. In device
mode, the use of line-state by the device controller driver is not necessary.
0 = SE0
1 = K_STATE
2 = J_STATE
3 = UNDEFINED
SLP: Suspend using L1 - RW. Default = 0b. When this bit is set to '1' and a non-zero Device
Address (DA) is specified, the Controller will instigate L1 entry during suspend (bit 7) and L1 exit
during resume (bit 6). When this bit is set to zero, the Controller will use the legacy (L2)
9 RW 0x0 mechanism. Software should only set this bit when the device attached immediately downstream
supports L1 transitions. When acting as device, this bit is read-only and set to '1' by the hardware
when the Controller enters is L1 state (LPM token received and accepted). Note: HSP is
redundant with PSPD[27:26]. This bit is not defined in the EHCI specification.
PR: This field is zero if Port Power (PP) is zero. In Host Mode: Read/Write. 1=Port is in Reset.
0=Port is not in Reset. When software writes a one to this bit the bus-reset sequence as defined
in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after
the reset sequence is complete. This behavior is different from EHCI where the host controller
8 RW 0x0 driver is required to set this bit to a zero after the reset duration is timed in the driver. In Device
Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the
USBSTS register.
0 = NOT_USB_RESET
1 = USB_RESET
SUSP: Port suspend. 1=Port in suspend state. 0=Port not in suspend state. In Host Mode:
Read/Write. Port Enabled Bit and Suspend bit of this register define the port states as follows:
Bits [Port Enabled, Suspend] Port State
0x Disable
10 Enable
11 Suspend.
When in the suspend state, downstream propagation of data is blocked on this port, except for
port reset. The blocking occurs at the end of the current transaction if a transaction was in
7 RO X progress when this bit was written to 1. In the suspend state, the port is sensitive to resume
detection. Note that the bit status does not change until the port is suspended and that there may
be a delay in suspending a port if there is a transaction currently in progress on the USB. The
host controller will unconditionally set this bit to zero when software sets the Force Port Resume
bit to zero. A write of zero to this bit is ignored by the host controller. If host software sets this bit
to a one when the port is not enabled (i.e., Port enabled bit is a zero), the results are undefined.
This field is zero if Port Power (PP) is zero in host mode.
In Device Mode: Read Only. This bit is a read only status bit.
0 = NOT_SUSPEND
1 = SUSPEND

USB Complex
FPR: Force Port Resume. 1= Resume detected/driven on port. 0=No resume (K state)
detected/driven on port.
In Host Mode: Software sets this bit to one to drive resume signaling. The Host Controller sets
this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit
transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the
USBSTS register is also set to one. This bit will automatically change to zero after the resume
sequence is complete. This behavior is different from EHCI where the host controller driver is
required to set this bit to a zero after the resume duration is timed in the driver. Note that when
the Host controller owns the port, the resume sequence follows the defined sequence
documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is
driven on the port as long as this bit remains a one. This bit remains a one until the port has
6 RW 0x0 switched to the high-speed idle. Writing a zero has no effect because the port controller will time
the resume operation to clear the bit when the port control state switches to HS or FS idle. This
field is zero if Port Power (PP) is zero in host mode. This bit is not-EHCI compatible.
In Device mode: After the device has been in Suspend State for 5ms or more, software must set
this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to
one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared
when the device returns to normal operation. Also, when this bit transitions to a one because a J-
to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one.
Software should ensure that the PHY clock is operational before writing a 1 to this bit to start the
resume sequence. This is true for both Device and Host modes.
0 = NO_RESUME
1 = RESUME
OCC: Over-current Change: Not supported

5 RO X 0 = NO_CHANGE
1 = CHANGE
OCA: Over-current Active: Not supported

4 RO X 0 = NO_OVER_CURRENT
1 = OVER_CURRENT
PEC: Port Enable/Disable Change: 1=Port enabled/disabled status has changed. 0=No change.
In Host Mode: For the root hub, this bit gets set to a one only when a port is disabled due to
disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See
Chapter 11 of the USB Specification). Software clears this by writing a one to it. This field is zero
3 RW 0x0
if Port Power (PP) is zero.
In Device mode: The device port is always enabled. (This bit will be zero.)
0 = NO_CHANGE
1 = CHANGE
PE: Port Enabled/Disabled: 1=Enable. 0=Disable (default).

In Host Mode: Ports can only be enabled by the host controller as a part of the reset and enable.
Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault
condition (disconnect event or other fault condition) or by the host software. Note that the bit
status does not change until the port state actually changes. There may be a delay in disabling or
2 RW 0x1 enabling a port due to other host controller and bus events. When the port is disabled, (0b)
downstream propagation of data is blocked except for reset. This field is zero if Port Power (PP)
is zero in host mode.
In Device Mode: The device port is always enabled. (This bit will be one)
0 = PORT_DISABLED
1 = PORT_ENABLED
CSC: Connect Status Change: 1 =Change in Current Connect Status. 0=No change (default)
In Host Mode: Indicates a change has occurred in the port's Current Connect Status. The
host/device controller sets this bit for all changes to the port device connect status, even if system
software has not cleared an existing connect status change. For example, the insertion status
changes twice before system software has cleared the changed condition, hub hardware will be
1 RW 0x0
'setting' an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to
it. This field is zero if Port Power (PP) is zero in host mode.
This bit is undefined in device controller mode.
0 = NO_CHANGE
1 = CHANGE

USB Complex
CCS: Current Connect Status.

In Host Mode: 1=Device is present on port. 0=No device is present (default). This value reflects
the current state of the port, and may not correspond directly to the event that caused the
Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power (PP) is zero in host
mode.
0 RO X In Device Mode: 1=Attached 0=Not Attached (default) A one indicates that the device
successfully attached and is operating in either high speed or full speed as indicated by the High
Speed Port bit in this register. A zero indicates that the device did not attach successfully or was
forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It
does not state the device being disconnected or suspended.
0 = NOT_CONNECTED
1 = CONNECTED
19.13.1.30 USB2_CONTROLLER_USB2D_HOSTPC1_DEVLC_0
USB2D Device Mode LPM Behavior and Control Register

This register controls the LPM behavior and controls the behavior of each USB port. Only available in device mode. This
register shares the same address with the HOSTPC1 register (which is used only in host mode).
USB2D Host Mode LPM Behavior and Control Register

This register controls the LPM behavior and controls the behavior of each USB port. Only available in host mode. This register
shares the same address with the DEVLC register (which is used only in device mode).
Offset: 0x1b4 | Read/Write: R/W | Reset: 0b0000xxx0000000000000xxxxxxxxxxx0
PTS: Parallel transceiver select. This bit is not defined in the EHCI specification.
0 = UTMI
1 = RESERVED
31:29 RW 0x0 2 = ULPI
3 = ICUSB_SER
4 = HSIC
STS: Serial transceiver not selected. This is the only value supported. This bit is not defined in
the EHCI specification.
28 RW 0x0
0 = PARALLEL_IF
1 = SERIAL_IF
PTW: Parallel Transceiver Width. Fixed to 0. This bit is not defined in the EHCI specification.
27 RO X 0 = EIGHT_BIT
1 = RESERVED
PSPD: This register field indicates the speed at which the port is operating. 00 = Full Speed 01 =
Low Speed 10 = High Speed. This bit is not defined in the EHCI specification.
0 = FULL_SPEED
26:25 RO X
1 = LOW_SPEED
2 = HIGH_SPEED
3 = RESERVED
ALPD: Auto Low Power While Disconnect - RW. Default = 0b. If set, this feature will be enabled,
and every time the port enters the disconnect state it will also enter low power state,disabling the
transceiver clock. The behavior will be same as if the PHCD bit was enabled (in fact this bit will
be set to 1 as soon as low power mode is enabled).When this field is set the WKCN field of
PORTSCx register (Wake on Connect Enable) will also be set. This way the core will wake up in
24 RW 0x0 case a connect is detected. There will be a delay between the detection of a disconnect and
actually enter in low power mode. This delay can be controlled by writing to the ALPDD field in
the register USBMODE.
0 = DONT_AUTO_LOW_POWER_WHILE_DISCONNECT
1 = AUTO_LOW_POWER_WHILE_DISCONNECT

USB Complex
PFSC: Port Force Full Speed Connect - RW. Default = 0b. Writing this bit to a '1b' will force the
port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify
itself as High Speed. This is useful for testing FS configurations with an HS host, hub or device.
23 RW 0x0
This bit is not defined in the EHCI specification.
0 = DONT_FORCE_FULL_SPEED
1 = FORCE_FULL_SPEED
PHCD: PHY Low Power Suspend - Clock disable: Writing this bit to a 1 will disable the PHY
clock. Write a 0 enables it. Reading this bit will indicate the status of the PHY clock.
NOTE: The PHY clock cannot be disabled if it is being used as the system clock. In device mode,
the PHY can be put into Low Power Clock Disable when the device is not running (USBCMD
RS=0b) or the host has signaled suspend (PORTSCx SUSP=1b). Low Power Clock Disable will
22 RW 0x0 be cleared automatically when the host has signaled resume. Before forcing a resume from the
device, the Controller driver must clear this bit. In host mode, the PHY can be put into Low Power
Suspend Clock Disable when the downstream device has been put into suspend mode or when
no downstream device is connected. Low Power Clock Disable is completely under the control of
software.
0 = DISABLE
1 = ENABLE
LPMX: Auto LPM set - RW. Default = 00b. This bit field is valid during Host Mode Only. For
Device Mode, this bit is reserved.
Value Meaning
00b Disables auto LPM.
01b If there is no activity for a certain number of SOFs the controller will send an LPM
21:20 RW 0x0 token, enter in suspend and issue a port change interrupt.
10b Same as above but without issuing an interrupt.
11b Reserved for futures LPM enhancements.
The detection of no activity is based on the absence of response from the downstream device.
Because of this limitation this feature should not be used if ISO OUT endpoints are being used
(as no handshake is expected).
ASUS: Auto Low Power - RW. Default = 0b. This bit field is valid during Device Mode Only. In
Host Mode, it is part of the ELPM field. This bit is used to control the auto low power feature. If
set, the auto low power feature will be enabled and every time the port enters in suspend state it
will also enter in low power state, disabling the transceiver clock. The behavior will be the same
17 RW 0x0
as if the PHCD bit was enabled (in fact this bit will be set to '1' as soon as low power mode is
enabled).
0 = DISABLE
1 = ENABLE
EPLPM: Endpoint for LPM token - RW. Default = 0000b. This bit field is valid during Host Mode
Only. For Device Mode, bits [19:18] are reserved and bit 17 is ASUS, while bit 16 is STL. This
19:16 RW 0x0
sets the endpoint number to which the LPM token will be sent. It will be directly mapped to the
ENDP field in the LPM token with the EXT PID.
STL: STALL reply to LPM token - RW. Default = 0b. This bit field is valid during Device Mode
Only. In Host Mode, it is part of the ELPM field. When this bit is set to '1', the Controller will reply
16 RW 0x0 always with STALL to all incoming LPM tokens. This bit overrides the LPM NYET bit (NYT).
0 = DISABLE
1 = ENABLE
LPMFRM: Auto LPM SOF Threshold - RW. Default = 0000b. This bit field is valid during Host
Mode Only. For Device Mode, this field is reserved. This holds the SOF counter threshold. When
15:12 RW 0x0 the number of SOFs with no activity in between reaches this threshold and the auto LPM is
enabled, an LPM token will be sent and the port will enter in suspend state. The SOF counter for
this threshold is incremented each 125 µs, even if the port is not in HS operation.
BA: bmAttributes - RO. Default = 00000000000b. This holds the bmAttributes field of the LPM
11:1 RO X
sub-token received, after the EXT PID token.

USB Complex
NYT_ASUS: NYET reply to LPM token - RW. Default = 0b. This bit is NYT during Device Mode.
Details follow: When this bit is to '1', the device controller will NYET all the LPM tokens. When this
bit is set to '0', the Controller will ACK all the LPM tokens if the STALL bit (STL) is also set to '0'.
This bit is ASUS in Host Mode. Details follow: This bit is used to control the auto low power
feature. If set, the auto low power feature will be enabled and every time the port enters in
0 RW 0x0
suspend state it will also enter in low power state, disabling the transceiver clock. The behavior
will be the same as if the PHCD bit was enabled (in fact this bit will be set to '1' as soon as low
power mode is enabled).
0 = DISABLE
1 = ENABLE
19.13.1.31 USB2_CONTROLLER_USB2D_OTGSC_0
USB2D On-The-Go (OTG) Status and Control Register

Offset: 0x1f4 | Read/Write: R/W | Reset: 0bx0000000x0000000xxxxxxxxxx100x00
DPIE: Data Pulse Interrupt Enable. Setting this bit enables the Data pulse interrupt.
1 = ENABLE
ONEMSE: 1 millisecond timer Interrupt enable. Setting this bit enables the 1 millisecond timer
interrupt.
29 RW 0x0
0 = DISABLE
1 = ENABLE
BSEIE: B Session End Interrupt Enable. Setting this bit enables the B session end interrupt
1 = ENABLE
BSVIE: B Session Valid Interrupt Enable. Setting this bit enables the B session valid interrupt
1 = ENABLE
ASVIE: A Session Valid Interrupt Enable. Setting this bit enables the A session valid interrupt
1 = ENABLE
AVVIE: A VBus Valid Interrupt Enable. Setting this bit enables the A VBus valid interrupt
1 = ENABLE
IDIE: USB ID Interrupt Enable. Setting this bit enables the USB ID interrupt
1 = ENABLE
DPIS: Data Pulse Interrupt Status. This bit is set when data bus pulsing occurs on DP or DM. Data
bus pulsing is only detected when USBMODE.CM = Host (11) and PORTSC(0). PortPower = Off
22 RW 0x0 (0). Software writes a 1 to clear this bit.
0 = INT_CLEAR
1 = INT_SET
ONEMSS: 1 millisecond timer Interrupt Status: This bit is set once every millisecond. Software
writes a 1 to clear it.
21 RW 0x0
0 = INT_CLEAR
1 = INT_SET
BSEIS: B Session End Interrupt Status. This bit is set when VBus has fallen below the B session
end threshold. Software writes a 1 to clear this bit .
20 RW 0x0
0 = INT_CLEAR
1 = INT_SET
BSVIS: B Session Valid Interrupt Status. This bit is set when VBus has either risen above or fallen
below the B session valid threshold (0.8 VDC). Software writes a 1 to clear this bit.
19 RW 0x0
0 = INT_CLEAR
1 = INT_SET

USB Complex
ASVIS: A Session Valid Interrupt Status. This bit is set when VBus has either risen above or fallen
below the A session valid threshold (0.8 VDC). Software writes a one to clear this bit.
18 RW 0x0
0 = INT_CLEAR
1 = INT_SET
AVVIS: A VBus Valid Interrupt Status. This bit is set when VBus has either risen above or fallen
below the VBus valid threshold (4.4 VDC) on an A device. Software writes a 1 to clear this bit.
17 RW 0x0
0 = INT_CLEAR
1 = INT_SET
IDIS: USB ID Interrupt Status. This bit is set when a change on the ID input has been detected.
Software writes a 1 to clear this bit.
16 RW 0x0
0 = INT_CLEAR
1 = INT_SET
DPS: Data Bus Pulsing Status. A 1 indicates data bus pulsing is being detected on the port.
14 RO X 0 = STS_CLEAR
1 = STS_SET
ONEMST: 1 millisecond timer toggle. This bit toggles once per millisecond
1 = STS_SET
BSE: B session End. Indicates VBus is below the B session end threshold
1 = STS_SET
BSV: B Session Valid. Indicates VBus is above the B session valid threshold
1 = STS_SET
ASV: A Session Valid. Indicates VBus is above the A session valid threshold
1 = STS_SET
AVV: A VBus Valid. Indicates VBus is above the A VBus valid threshold
1 = STS_SET
ID: USB ID: 0 = A-device 1 = B-device

8 RO X 0 = A_DEV
1 = B_DEV
IDPU: USB ID Pullup

5 RW 0x1 0 = CLEAR
1 = SET
DP: Data Pulsing. Setting this bit causes the pull-up on DP to be asserted for data pulsing during
SRP.
4 RW 0x0
0 = NO_DATA_PULSE
1 = DATA_PULSE
OT: OTG Termination. This bit must be set when the OTG device is in device mode, this controls
the pulldown on DM.
3 RW 0x0
0 = NO_OTG_TERM
1 = OTG_TERM
VC: VBUS Charge. Setting this bit causes the VBus line to be charged. This is used for VBus
pulsing during SRP.
1 RW 0x0
0 = NO_VBUS_CHRG
1 = VBUS_CHRG
VD: VBUS_Discharge. Read/write. Setting this bit causes Vbus to discharge through a resistor.
0 RW 0x0 0 = NO_VBUS_DISCHRG
1 = VBUS_DISCHRG

USB Complex
19.13.1.32 USB2_CONTROLLER_USB2D_USBMODE_0
USB2D USB Device Mode Register

Offset: 0x1f8 | Read/Write: R/W | Reset: 0b00000000000000000xxxxxxxxx0xxxxx
ALPDD: Auto Low Power While Disconnect Delay, Used when the ALPD field of the HOSTPCx
register is set. Defines the delay between disconnect detection and entering in low power mode.
31:16 RW 0x0
The delay is <this register value>*64*100/3 in milliseconds. The maximum value is
65535*64*100/3 = 139,808 ms. The minimum value is 0. Only used in host mode.
15 RW 0x0 SRT: Shorten USB Reset Time. Software should never set this to 1.
VBPS: VBUS Power Select This can be used by logic that selects between an on-chip Vbus
power source (charge pump) and an off-chip source in systems when both are available. Only to
5 RW 0x0
be used in Host Mode. No functionality is implemented for this, so software should not use this
bit.
SDIS: Stream disable: 1: Streaming is disabled - helpful to avoid overruns/underruns when the
system load is too high.
4 RO X
0 = STREAM_ENABLE
1 = STREAM_DISABLE
SLOM: Setup Lockout Mode: In device mode, this bit controls the behavior of the setup lockout
mechanism. 0: Setup lockout is ON (default). 1: Setup lockout is OFF. Firmware requires the use
3 RO X of setup tripwire semaphore in USB2D_USBCMD register.
0 = LOCKOUT_ON
1 = LOCKOUT_OFF
ES: Endian Select: Note: For this implementation, this bit should be always set to 0 (little endian).
2 RO X 0 = LITTLE_ENDIAN
1 = RESERVED
CM: Controller Mode: The controller mode will default to an idle state and will need to be
initialized to the desired operating mode after reset. This register can only be written once after
reset. If it is necessary to switch modes, software must reset the controller by writing to the
RESET bit in the USBCMD register before reprogramming this register. 00 = Idle [Default]. 01 =
1:0 RO X Reserved. 10 = Device Controller. 11 = Host Controller.
0 = IDLE
1 = RESERVED
2 = DEVICE_MODE
3 = HOST_MODE
19.13.1.33 USB2_CONTROLLER_USB2D_ENDPTNAK_0
USB2D Endpoint NAK register

Offset: 0x200 | Read/Write: R/W | Reset: 0b00000000000000000000000000000000
EPTN: TX Endpoint NAK R/WC. Each TX endpoint has 1 bit in this field. The bit is set when the device
sends a NAK handshake on a received IN token for the corresponding endpoint.
31:16 0x0
0 = CLEAR
1 = SET
EPRN: RX Endpoint NAK R/WC. Each RX endpoint has 1 bit in this field. The bit is set when the device
sends a NAK handshake on a received OUT or PING token for the corresponding endpoint.
15:0 0x0
0 = CLEAR
1 = SET

USB Complex
19.13.1.34 USB2_CONTROLLER_USB2D_ENDPTNAK_ENABLE_0
USB2D Endpoint NAK Enable register

EPTNE: TX Endpoint NAK Enable R/W. Each bit is an enable bit for the corresponding TX Endpoint
NAK bit. If this bit is set and the corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set.
31:16 0x0
0 = DISABLE
1 = ENABLE
EPRNE: RX Endpoint NAK Enable R/W. Each bit is an enable bit for the corresponding RX Endpoint
NAK bit. If this bit is set and the corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set.
15:0 0x0
0 = DISABLE
1 = ENABLE
19.13.1.35 USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0
USB2D Endpoint Setup Status Register

ENDPTSETUPSTAT15: Endpoint 15 Setup Status: For every setup transaction that is received, this bit is
set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the
setup data from Queue head. The response to a setup packet (as in the order of operations and total
15 0x0 response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. This
register is only used in device mode.
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD

USB Complex
0 = NOT_RCVD
1 = SETUP_RCVD
ENDPTSETUPSTAT9: Endpoint 9 Setup Status: For every setup transaction that is received, this bit is set
to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup
data from Queue head. The response to a setup packet (as in the order of operations and total response
9 0x0 time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. This register is only
used in device mode.
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD

USB Complex
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
19.13.1.36 USB2_CONTROLLER_USB2D_ENDPTPRIME_0
USB2D Endpoint Initialization Register

Offset: 0x20c | Read/Write: R/W | Reset: 0b00000000000000000000000000000000
PETB15: Prime Endpoint Transmit Buffer: This bit is used to request that a buffer prepared for a transmit
operation in order to respond to a USB IN/INTERRUPT transaction on this endpoint. Software should write
a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use
31 0x0 this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer.
Hardware will clear this bit when this endpoint is successfully primed. This is only used in device mode.
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME

USB Complex
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME

USB Complex
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
PERB15: Prime Endpoint Receive Buffer: This bit is used to request that a buffer prepared for a receive
operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one
to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this
15 0x0 bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer.
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME

USB Complex
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME

USB Complex
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
19.13.1.37 USB2_CONTROLLER_USB2D_ENDPTFLUSH_0
USB2D Endpoint De-Initialization Register

FETB15: Flush Endpoint Transmit Buffer: Writing a one to this bit causes the associated endpoint to clear
any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until
completion. Hardware clears this register after the endpoint flush operation is successful. This is only used
31 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
30 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
29 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
28 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH

USB Complex
27 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
26 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
25 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
24 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
23 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
22 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
21 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
20 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
19 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
18 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH

USB Complex
FETB1: Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is
in progress for the associated endpoint that transfer will continue until completion. Hardware clears this
17 0x0 register after the endpoint flush operation is successful. This is only used in device mode.
0 = DONT_FLUSH
1 = FLUSH
0 = DONT_FLUSH
1 = FLUSH
FERB15: Flush Endpoint Receive Buffer: Writing a one to this bit causes the associated endpoint to clear
15 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
14 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
13 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
12 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
11 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
10 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
9 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
8 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH

USB Complex
7 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
6 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
5 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
4 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
3 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
2 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
1 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
0 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH

USB Complex
19.13.1.38 USB2_CONTROLLER_USB2D_ENDPTSTATUS_0
USB2D Endpoint Status Register

ETBR15: Endpoint Transmit Buffer Ready: One bit for each endpoint indicates status of the respective
endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a
corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the
ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB
31 X
traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by
the USB DMA system, or through the ENDPTFLUSH register. This is only used in device mode.
0 = NOT_READY
1 = READY
30 X
0 = NOT_READY
1 = READY
29 X
0 = NOT_READY
1 = READY
28 X
0 = NOT_READY
1 = READY
27 X
0 = NOT_READY
1 = READY
26 X
0 = NOT_READY
1 = READY
25 X
0 = NOT_READY
1 = READY

USB Complex
24 X
0 = NOT_READY
1 = READY
23 X
0 = NOT_READY
1 = READY
22 X
0 = NOT_READY
1 = READY
21 X
0 = NOT_READY
1 = READY
20 X
0 = NOT_READY
1 = READY
19 X
0 = NOT_READY
1 = READY
18 X
0 = NOT_READY
1 = READY

USB Complex
17 X
0 = NOT_READY
1 = READY
16 X
0 = NOT_READY
1 = READY
ERBR15: Endpoint Receive Buffer Ready: One bit for each endpoint indicates status of the respective
15 X
0 = NOT_READY
1 = READY
14 X
0 = NOT_READY
1 = READY
13 X
0 = NOT_READY
1 = READY
12 X
0 = NOT_READY
1 = READY
11 X
0 = NOT_READY
1 = READY

USB Complex
10 X
0 = NOT_READY
1 = READY
9 X
0 = NOT_READY
1 = READY
8 X
0 = NOT_READY
1 = READY
7 X
0 = NOT_READY
1 = READY
6 X
0 = NOT_READY
1 = READY
5 X
0 = NOT_READY
1 = READY
4 X
0 = NOT_READY
1 = READY

USB Complex
3 X
0 = NOT_READY
1 = READY
2 X
0 = NOT_READY
1 = READY
1 X
0 = NOT_READY
1 = READY
0 X
0 = NOT_READY
1 = READY
19.13.1.39 USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0
USB2D Endpoint Complete Register

ETCE15: Endpoint Transmit Complete Event: Each bit indicates a transmit event (IN/INTERRUPT)
occurred and software should read the corresponding endpoint queue to determine the endpoint status. If
the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the
31 0x0
USBINT. Writing a one clears the corresponding bit in this register. This is only used in device mode.
0 = NOT_COMPLETE
1 = COMPLETE
30 0x0
0 = NOT_COMPLETE
1 = COMPLETE
29 0x0
0 = NOT_COMPLETE
1 = COMPLETE

USB Complex
28 0x0
0 = NOT_COMPLETE
1 = COMPLETE
27 0x0
0 = NOT_COMPLETE
1 = COMPLETE
26 0x0
0 = NOT_COMPLETE
1 = COMPLETE
ETCE9: Endpoint Transmit Complete Event: Each bit indicates a transmit event (IN/INTERRUPT) occurred
and software should read the corresponding endpoint queue to determine the endpoint status. If the
corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the
25 0x0
0 = NOT_COMPLETE
1 = COMPLETE
24 0x0
0 = NOT_COMPLETE
1 = COMPLETE
23 0x0
0 = NOT_COMPLETE
1 = COMPLETE
22 0x0
0 = NOT_COMPLETE
1 = COMPLETE
21 0x0
0 = NOT_COMPLETE
1 = COMPLETE
20 0x0
0 = NOT_COMPLETE
1 = COMPLETE
19 0x0
0 = NOT_COMPLETE
1 = COMPLETE

USB Complex
18 0x0
0 = NOT_COMPLETE
1 = COMPLETE
17 0x0
0 = NOT_COMPLETE
1 = COMPLETE
16 0x0
0 = NOT_COMPLETE
1 = COMPLETE
ERCE15: Endpoint Receive Complete Event: Each bit indicates a received event (OUT/SETUP) occurred
and software should read the corresponding endpoint queue to determine the transfer status. If the
15 0x0
0 = NOT_COMPLETE
1 = COMPLETE
14 0x0
0 = NOT_COMPLETE
1 = COMPLETE
13 0x0
0 = NOT_COMPLETE
1 = COMPLETE
12 0x0
0 = NOT_COMPLETE
1 = COMPLETE
11 0x0
0 = NOT_COMPLETE
1 = COMPLETE
10 0x0
0 = NOT_COMPLETE
1 = COMPLETE
9 0x0
0 = NOT_COMPLETE
1 = COMPLETE

USB Complex
8 0x0
0 = NOT_COMPLETE
1 = COMPLETE
7 0x0
0 = NOT_COMPLETE
1 = COMPLETE
6 0x0
0 = NOT_COMPLETE
1 = COMPLETE
5 0x0
0 = NOT_COMPLETE
1 = COMPLETE
4 0x0
0 = NOT_COMPLETE
1 = COMPLETE
3 0x0
0 = NOT_COMPLETE
1 = COMPLETE
2 0x0
0 = NOT_COMPLETE
1 = COMPLETE
1 0x0
0 = NOT_COMPLETE
1 = COMPLETE
0 0x0
0 = NOT_COMPLETE
1 = COMPLETE

USB Complex
19.13.1.40 USB2_CONTROLLER_USB2D_ENDPTCTRL0_0
USB2D Endpoint Control 0 Register

TXE: TX Endpoint Enable. Endpoint 0 is always enabled.

23 X 0 = DISABLE
1 = ENABLE
TXT: TX Endpoint Type. Endpoint 0 is fixed as a Control Endpoint.

0 = CTRL
19:18 X 1 = ISO
2 = BULK
3 = INTR
TXS: TX Endpoint Stall: Software can write a one to this bit to force the endpoint to return a STALL
handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will
16 X automatically be cleared upon receipt of a new SETUP request.
0 = EP_OK
1 = EP_STALL
RXE: RX Endpoint Enable. Endpoint 0 is always enabled.

7 X 0 = DISABLE
1 = ENABLE
RXT: RX Endpoint Type. Endpoint 0 is fixed as a Control Endpoint.

0 = CTRL
3:2 X 1 = ISO
2 = BULK
3 = INTR
RXS: RX Endpoint Stall: Software can write a one to this bit to force the endpoint to return a STALL
0 = EP_OK
1 = EP_STALL
19.13.1.41 USB2_CONTROLLER_USB2D_ENDPTCTRLn_0
USB2D Endpoint Control 1 through 15 registers have the same field definitions and reset value. In the register offset, the value
n is the register number (1 through 15).
USB2D Endpoint Control n Register

Offset: 0x220 + (n – 1) * 0x04 | Read/Write: R/W | Reset: 0bxxxxxxxx000x00x0xxxxxxxx000x00x0
TXE: TX Endpoint Enable. An Endpoint should be enabled only after it has been configured.
1 = ENABLE
TXR: TX Data Toggle Reset: Whenever a configuration event is received for this Endpoint,
software must write a one to this bit in order to synchronize the data PIDs between the Host and
22 RW 0x0 device.
0 = KEEP_GOING
1 = RESET_PID_SEQ
TXI: TX Data Toggle Inhibit: This bit is only used for test and should always be written as zero.
Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always
21 RW 0x0 transmit DATA0 for a data packet.
0 = DIS_PID_SEQ
1 = ENB_PID_SEQ
19:18 RW 0x0 TXT: TX Endpoint Type: 00 = Control. 01 = Isochronous. 10 = Bulk. 11 = Interrupt.

0 = CTRL

USB Complex

1 = ISO
2 = BULK
3 = INTR
17 RO X TXD: This bit is fixed to 0.
TXS: TX Endpoint Stall: This bit will be set automatically upon receipt of a SETUP request if this
Endpoint is not configured as a Control Endpoint. It will be cleared automatically upon receipt of a
SETUP request if this Endpoint is configured as a Control Endpoint. Software can write a one to
16 RW 0x0 this bit to force the endpoint to return a STALL handshake to the Host. It will continue to returning
STALL until this bit is either cleared by software or automatically cleared as above.
0 = EP_OK
1 = EP_STALL
RXE: RX Endpoint Enable. An Endpoint should be enabled only after it has been configured.
1 = ENABLE
RXR: RX Data Toggle Reset: Whenever a configuration event is received for this Endpoint,
software must write a one to this bit in order to synchronize the data PIDs between the host and
6 RW 0x0 device.
0 = KEEP_GOING
1 = RESET_PID_SEQ
RXI: RX Data Toggle Inhibit: This bit is only used for test and should always be written as zero.
5 RW 0x0 accept data packet regardless of their data PID.
0 = DIS_PID_SEQ
1 = ENB_PID_SEQ
RXT: RX Endpoint Type: 00 = Control. 01 = Isochronous. 10 = Bulk. 11 = Interrupt.

0 = CTRL
3:2 RW 0x0 1 = ISO
2 = BULK
3 = INTR
1 RO X RXD: This bit is fixed to 0.
RXS: RX Endpoint Stall: This bit will be set automatically upon receipt of a SETUP request if this
Endpoint is not configured as a Control Endpoint. It will be cleared automatically upon receipt a
0 = EP_OK
1 = EP_STALL
19.13.2 USB1 Controller Interface Registers

These are used to generate the actual RTL registers for USB1 controller interface.
19.13.2.1 USB1_IF_USB_SUSP_CTRL_0
This register controls the suspend and resume behavior of USB controller/PHY.
USB Suspend Control Register

Offset: 0x400 | Read/Write: R/W | Reset: 0bxxxxx00xxxxxx000xxx01000xx000000
FAST_WAKEUP_RESP: Enable Fast Response from UTMIP PHY for a Remote Wakeup request
from device. This is used only for cases where wakeup response needs to be within 1 ms of spec.
26 RW 0x0 Used for Host mode ONLY.
0 = DISABLE
1 = ENABLE
25 RW 0x0 UTMIP_SUSPL1_SET: Enable SuspendL1 for UTMIP PHY. Enabling this will only cut off clocks
to the UTMIP logic. The USB PLLs, PllU and UTMIP PLL will still be running.

USB Complex

0 = DISABLE
1 = ENABLE
USB_WAKEUP_DEBOUNCE_COUNT: USB PHY wakeup debounce counter. USB will debounce

18:16 RW 0x0 any wakeup event by the number of clocks programmed in this counter. A value of 0 results in no
debounce.
UTMIP_PHY_ENB: Enable UTMIP PHY mode. Set this to 1 if using UTMIP PHY. Otherwise set
this to 0.
12 RW 0x0
0 = DISABLE
1 = ENABLE
UTMIP_RESET: Reset going to UTMIP PHY (active high). This should be set to 1 whenever
programming the UTMIP config registers. It should be cleared to 0 after the programming of
UTMIP config registers is done. UTMIP config registers should be programmed only once before
11 RW 0x1 doing any transactions on USB. The UTMIP PHY registers should be programmed while UTMIP
is in reset.
0 = DISABLE
1 = ENABLE
USB_SUSP_POL: Polarity of the suspend signal going to USB PHY. 0 = Active low (default). 1 =
Active high. This should not be changed by software.
10 RW 0x0
0 = ACTIVE_LOW
1 = ACTIVE_HIGH
USB_PHY_CLK_VALID_INT_ENB: USB PHY clock valid interrupt enable. If this bit is enabled,
interrupt is generated whenever USB clocks are resumed from a suspend.
9 RW 0x0
0 = DISABLE
1 = ENABLE
USB_PHY_CLK_VALID_INT_STS: USB PHY clock valid interrupt status. This bit is set whenever
the USB PHY clock is woken up from suspend. Software must write a 1 to clear this bit.
8 RO 0x0
0 = UNSET
1 = SET
USB_PHY_CLK_VALID: USB PHY clock valid status. This bit indicates whether the USB PHY is
generating a valid clock to the USB controller. If USB PHY clock is running, this bit is set to 1,
7 RO X else it is set to 0.
0 = UNSET
1 = SET
USB_CLKEN: USB AHB clock enable status. Indicates whether the AHB clock to the USB
controller is enabled or not. If AHB clock to USB controller is enabled, this bit is set to 1, else it is
set to 0. NOTE: even when this is set to 0, all essential blocks that are required to resume USB
6 RO X
clocks from suspend will be active and their AHB clock will not be suspended.
0 = UNSET
1 = SET
USB_SUSP_CLR: Suspend Clear. Software must write a 1 to this bit to bring the PHY out of
suspend mode. This is used when the software stops the PHY clock during suspend and then
wants to initiate a resume. Software should also write 0 to clear it. NOTE: It is required that
5 RW 0x0
software generate a positive pulse on this bit to guarantee proper operation.
0 = UNSET
1 = SET
USB_WAKE_ON_DISCON_EN_DEV: Wake on Disconnect Enable (device mode). When

enabled (1), the USB device will wake up from suspend on a disconnect event. This is only valid
4 RW 0x0 when USB controller is in device mode, it is not applicable when USB controller is in host mode.
0 = DISABLE
1 = ENABLE
USB_WAKE_ON_CNNT_EN_DEV: Wake on Connect Enable (device mode). When enabled (1),

USB device will wake up from suspend on a connect event. This is only valid when USB
3 RW 0x0 controller is in device mode, it is not applicable when USB controller is in host mode.
0 = DISABLE
1 = ENABLE
USB_WAKE_ON_RESUME_EN: Wake on resume enable. If this bit is enabled, USB will wake up
2 RW 0x0 from suspend whenever a resume event is detected on USB. This is valid for both USB device
and USB host modes.
0 = DISABLE

USB Complex

1 = ENABLE
USB_WAKEUP_INT_ENB: USB wakeup interrupt enable. If this bit is enabled, interrupt is

generated whenever USB wakeup event is generated.
1 RW 0x0
0 = DISABLE
1 = ENABLE
USB_WAKEUP_INT_STS: USB wakeup interrupt status. This bit is set whenever USB wakes up
from suspend (a wakeup event is generated). Software must write a 1 to clear this bit. Note that
during the wakeup sequence, PHY clocks will be resumed from suspend. Software can check
when the PHY clocks are resumed by reading the bit USB_PHY_CLK_VALID. There is also a
0 RO 0x0 separate interrupt generated when PHY clock is resumed if USB_PHY_CLK_VALID_INT_EN is
set. During the wakeup sequence, first USB_WAKEUP_INT_STS will be set, and it will take some
time for the PHY clock to resume, which can be detected by checking USB_PHY_CLK_VALID.
0 = UNSET
1 = SET
19.13.2.2 USB1_IF_USB_PHY_VBUS_SENSORS_0
This register controls the OTG VBUS sensors in the USB PHY. There are 4 VBUS sensors:
§ A_VBUS_VLD
§ A_SESS_VLD
§ B_SESS_VLD
§ B_SESS_END
The debounced status of each sensor can be read from the corresponding _STS bit field of the sensor in this register. The
_CHG_DET field is set to 1 whenever a change is detected in the value of the _STS bit field of the corresponding sensor. If
_INT_EN is set, then an interrupt is generated to the processor. This interrupt can be routed to CPU/AVP by appropriately
writing the USBD bits in the interrupt controller registers.
In case software wants to override the value for a sensor, it can set the corresponding _SW_EN to 1, and set the
corresponding sensor _SW_VALUE to 1 or 0 as per the requirement.
There are two debouncers for each sensor - DEBOUNCE_A and DEBOUNCE_B. The debounce values for them are
controlled by the register UTMIP_DEBOUNCE_CFG0, fields UTMIP_BIAS_DEBOUNCE_A and
UTMIP_BIAS_DEBOUNCE_B. For each sensor, we can select whether to use DEBOUNCE_A or DEBOUNCE_B by setting
the field _DEB_SEL_B to the appropriate value (SEL_A or SEL_B).
Note: Do not set either UTMIP_BIAS_DEBOUNCE_A or UTMIP_BIAS_DEBOUNCE_B to 0x0. If not using one
of the debouncers, keep it at the default value of 0xFFFF.
USB PHY VBUS SENSORS Control Register

Offset: 0x404 | Read/Write: R/W | Reset: 0bx0000x00x0000x00x0000x00x0000x00
A_VBUS_VLD_WAKEUP_EN: A_VBUS_VLD wakeup enable. If this bit is enabled, USB will wake
up from suspend whenever a change is detected on A_VBUS_VLD.
30 RW 0x0
0 = DISABLE
1 = ENABLE
A_VBUS_VLD_DEB_SEL_B: A_VBUS_VLD debounce A/B select. Selects between the two

debounce values UTMIP_BIAS_DEBOUNCE_A or UTMIP_BIAS_DEBOUNCE_B from the register
29 RW 0x0 UTMIP_DEBOUNCE_CFG0.
0 = SEL_A
1 = SEL_B
28 RW 0x0 A_VBUS_VLD_SW_VALUE: A_VBUS_VLD software value. Software should write the appropriate
value (1/0) to set/unset the A_VBUS_VLD status. This is only valid when A_VBUS_VLD_SW_EN is

USB Complex

set.
0 = UNSET
1 = SET
A_VBUS_VLD_SW_EN: A_VBUS_VLD software enable. Enable Software Controlled

A_VBUS_VLD. Software sets this bit to drive the value in A_VBUS_VLD_SW_VALUE to the USB
27 RW 0x0 controller.
0 = DISABLE
1 = ENABLE
A_VBUS_VLD_STS: A_VBUS_VLD status. This is set to 1 whenever A_VBUS_VLD sensor output

is 1.
26 RO X
0 = UNSET
1 = SET
A_VBUS_VLD_CHG_DET: A_VBUS_VLD change detect. This field is set by hardware whenever a

change is detected in the value of A_VBUS_VLD. software writes a 1 to clear it
25 RO 0x0
0 = UNSET
1 = SET
A_VBUS_VLD_INT_EN: A_VBUS_VLD interrupt enable. If this field is set to 1, an interrupt is

generated whenever A_VBUS_VLD_CHG_DET is set to 1.
24 RW 0x0
0 = DISABLE
1 = ENABLE
A_SESS_VLD_WAKEUP_EN: A_SESS_VLD wakeup enable. If this bit is enabled, USB will wake
up from suspend whenever a change is detected on A_SESS_VLD.
22 RW 0x0
0 = DISABLE
1 = ENABLE
A_SESS_VLD_DEB_SEL_B: A_SESS_VLD debounce A/B select. Selects between the two

0 = SEL_A
1 = SEL_B
A_SESS_VLD_SW_VALUE: A_SESS_VLD software value. Software should write the appropriate

value (1/0) to set/unset the A_SESS_VLD status. This is only valid when A_SESS_VLD_SW_EN is
20 RW 0x0 set.
0 = UNSET
1 = SET
A_SESS_VLD_SW_EN: A_SESS_VLD software enable. Enable Software Controlled

A_SESS_VLD. Software sets this bit to drive the value in A_SESS_VLD_SW_VALUE to the USB
0 = DISABLE
1 = ENABLE
A_SESS_VLD_STS: A_SESS_VLD status. This is set to 1 whenever A_SESS_VLD sensor output

is 1.
18 RO X
0 = UNSET
1 = SET
A_SESS_VLD_CHG_DET: A_SESS_VLD change detect. This field is set by hardware whenever a

change is detected in the value of A_SESS_VLD. software writes a 1 to clear it
17 RO 0x0
0 = UNSET
1 = SET
A_SESS_VLD_INT_EN: A_SESS_VLD interrupt enable. If this field is set to 1, an interrupt is

generated whenever A_SESS_VLD_CHG_DET is set to 1.
16 RW 0x0
0 = DISABLE
1 = ENABLE
B_SESS_VLD_WAKEUP_EN: B_SESS_VLD wakeup enable. If this bit is enabled, USB will wake
up from suspend whenever a change is detected on B_SESS_VLD.
14 RW 0x0
0 = DISABLE
1 = ENABLE
B_SESS_VLD_DEB_SEL_B: B_SESS_VLD debounce A/B select. Selects between the two

13 RW 0x0 debounce values UTMIP_BIAS_DEBOUNCE_A or UTMIP_BIAS_DEBOUNCE_B from the register
UTMIP_DEBOUNCE_CFG0.
0 = SEL_A
USB Complex

1 = SEL_B
B_SESS_VLD_SW_VALUE: B_SESS_VLD software value. Software should write the appropriate

value (1/0) to set/unset the B_SESS_VLD status. This is only valid when B_SESS_VLD_SW_EN is
12 RW 0x0 set.
0 = UNSET
1 = SET
B_SESS_VLD_SW_EN: B_SESS_VLD software enable. Enable Software Controlled

B_SESS_VLD. Software sets this bit to drive the value in B_SESS_VLD_SW_VALUE to the USB
0 = DISABLE
1 = ENABLE
B_SESS_VLD_STS: B_SESS_VLD status. This is set to 1 whenever B_SESS_VLD sensor output

is 1.
10 RO X
0 = UNSET
1 = SET
B_SESS_VLD_CHG_DET: B_SESS_VLD change detect. This field is set by hardware whenever a

change is detected in the value of B_SESS_VLD. software writes a 1 to clear it
9 RO 0x0
0 = UNSET
1 = SET
B_SESS_VLD_INT_EN: B_SESS_VLD interrupt enable. If this field is set to 1, an interrupt is

generated whenever B_SESS_VLD_CHG_DET is set to 1.
8 RW 0x0
0 = DISABLE
1 = ENABLE
B_SESS_END_WAKEUP_EN: B_SESS_END wakeup enable. If this bit is enabled, USB will wake
up from suspend whenever a change is detected on B_SESS_END.
6 RW 0x0
0 = DISABLE
1 = ENABLE
B_SESS_END_DEB_SEL_B: B_SESS_END debounce A/B select. Selects between the two

0 = SEL_A
1 = SEL_B
B_SESS_END_SW_VALUE: B_SESS_END software value. Software should write the appropriate

value (1/0) to set/unset the B_SESS_END status. This is only valid when B_SESS_END_SW_EN is
4 RW 0x0 set.
0 = UNSET
1 = SET
B_SESS_END_SW_EN: B_SESS_END software enable. Enable Software Controlled

B_SESS_END Software sets this bit to drive the value in B_SESS_END_SW_VALUE to the USB
0 = DISABLE
1 = ENABLE
B_SESS_END_STS: B_SESS_END status. This is set to 1 whenever B_SESS_END sensor output

is 1.
2 RO X
0 = UNSET
1 = SET
B_SESS_END_CHG_DET: B_SESS_END change detect. This field is set by hardware whenever a

change is detected in the value of B_SESS_END. software writes a 1 to clear it
1 RO 0x0
0 = UNSET
1 = SET
B_SESS_END_INT_EN: B_SESS_END interrupt enable. If this field is set to 1, an interrupt is

generated whenever B_SESS_END_CHG_DET is set to 1.
0 RW 0x0
0 = DISABLE
1 = ENABLE

USB Complex
19.13.2.3 USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0
This register controls the battery charger (VDCD_DET, VDAT_DET), VBUS_WAKEUP and ID sensors. The following sensors
are in this register:
§ VBUS_WAKEUP
§ ID
§ VDAT_DET
§ VDCD_DET
There are debouncers for VDAT_DET and VDCD_DET. These use separate debouncers -CHRG_DEBOUNCE_PERIOD_A
and CHRG_DEBOUNCE_PERIOD_B. The debounce values for them are controlled by the register
UTMIP_CHRG_DEB_CFG0, fields UTMIP_CHRG_DEBOUNCE_PERIOD_A and UTMIP_CHRG_DEBOUNCE_PERIOD_B.
For each sensor, we can select whether to use CHRG_DEBOUNCE_PERIOD_A or CHRG_DEBOUNCE_PERIOD_B by
setting the field _DEB_SEL_B to the appropriate value (SEL_A or SEL_B).
Note: Do not set either UTMIP_CHRG_DEBOUNCE_PERIOD_A or UTMIP_CHRG_DEBOUNCE_PERIOD_B to

0x0. If not using one of the debouncers, keep it at the default value of 0xFFFF.
USB PHY VBUS Wakeup and ID Control Register

Offset: 0x408 | Read/Write: R/W | Reset: 0b00000x00xx000x00xx000x00x1000x00
DIV_DET_EN: Battery charger divider detection enable. This goes to the USB2OTG pad.
1 = ENABLE
VBUS_WAKEUP_WAKEUP_EN: VBUS_WAKEUP wakeup enable. If this bit is enabled, USB will

wake up from suspend whenever a change is detected on VBUS_WAKEUP.
30 RW 0x0
0 = DISABLE
1 = ENABLE
VDCD_DET_DEB_SEL_B: VCDT_DET debounce A/B select. Selects the debounce value from
UTMIP_CHRG_DEBOUNCE_PERIOD_A or UTMIP_CHRG_DEBOUNCE_PERIOD_B from the
29 RW 0x0 register UTMIP_CHRG_DEB_CFG0.
0 = SEL_A
1 = SEL_B
VDCD_DET_SW_VALUE: VDCD_DET software value. Software should write the appropriate value
(1/0) to set/unset the VDCD_DET status. This is only valid when VDCD_DET_SW_EN is set.
28 RW 0x0
0 = UNSET
1 = SET

USB Complex
VDCD_DET_SW_EN: VDCD_DET software enable. Enable Software Controlled VDCD_DET.

Software sets this bit to drive the value in VDCD_DET_SW_VALUE to the USB controller
27 RW 0x0
0 = DISABLE
1 = ENABLE
VDCD_DET_STS: VDCD_DET status. This is set to 1 whenever VDCD_DET sensor output is 1.

26 RO X 0 = UNSET
1 = SET
VDCD_DET_CHG_DET: VDCD_DET change detect. This field is set by hardware whenever a

change is detected in the value of VDCD_DET. software writes a 1 to clear it
25 RO 0x0
0 = UNSET
1 = SET
VDCD_DET_INT_EN: VDCD_DET interrupt enable. If this field is set to 1, an interrupt is generated

whenever VDCD_DET_CHG_DET is set to 1.
24 RW 0x0
0 = DISABLE
1 = ENABLE
VOP_DIV2P7_DET: This read-only status bit is from the battery charging divider circuit of the
USB2OTG pad
23 RO X
0 = UNSET
1 = SET
VOP_DIV2P0_DET:This read-only status bit is from the battery charging divider circuit of the
USB2OTG pad
22 RO X
0 = UNSET
1 = SET
VDAT_DET_DEB_SEL_B: VDAT_DET debounce A/B select. Selects between the two debounce
values UTMIP_CHRG_DEBOUNCE_PERIOD_A or UTMIP_CHRG_DEBOUNCE_PERIOD_B from
21 RW 0x0 the register UTMIP_DEBOUNCE_CFG0.
0 = SEL_A
1 = SEL_B
VDAT_DET_SW_VALUE: VDAT_DET software value. Software should write the appropriate value
(1/0) to set/unset the VDAT_DET status. This is only valid when VDAT_DET_SW_EN is set.
20 RW 0x0
0 = UNSET
1 = SET
VDAT_DET_SW_EN: VDAT_DET software enable. Enable Software Controlled VDAT_DET.

Software sets this bit to drive the value in VDAT_DET_SW_VALUE to the USB controller
19 RW 0x0
0 = DISABLE
1 = ENABLE
VDAT_DET_STS: VDAT_DET status. This is set to 1 whenever the VDAT_DET sensor output is 1.
18 RO X 0 = UNSET
1 = SET
VDAT_DET_CHG_DET: VDAT_DET change detect. This field is set by hardware whenever a

change is detected in the value of VDAT_DET. software writes a 1 to clear it
17 RO 0x0
0 = UNSET
1 = SET
VDAT_DET_INT_EN: VDAT_DET interrupt enable. If this field is set to 1, an interrupt is generated

whenever VDAT_DET_CHG_DET is set to 1.
16 RW 0x0
0 = DISABLE
1 = ENABLE
VON_DIV2P7_DET: This read-only status bit is from the battery charging divider circuit of the
USB2OTG pad
15 RO X
0 = UNSET
1 = SET
VON_DIV2P0_DET: This read-only status bit is from the battery charging divider circuit of the
USB2OTG pad
14 RO X
0 = UNSET
1 = SET
VBUS_WAKEUP_DEB_SEL_B: VBUS_WAKEUP debounce A/B select. Selects between the two

13 RW 0x0 debounce values UTMIP_BIAS_DEBOUNCE_A or UTMIP_BIAS_DEBOUNCE_B from the register
UTMIP_DEBOUNCE_CFG0.
USB Complex

0 = SEL_A
1 = SEL_B
VBUS_WAKEUP_SW_VALUE: VBUS wakeup software value. Software should write the

appropriate value (1/0) to set/unset the VBUS_WAKEUP status. This is only valid when
12 RW 0x0 VBUS_WAKEUP_SW_EN is set.
0 = UNSET
1 = SET
VBUS_WAKEUP_SW_EN: VBUS wakeup software enable. Enable Software Controlled

VBUS_WAKEUP. Software sets this bit to drive the value in VBUS_WAKEUP_SW_VALUE to the
11 RW 0x0 USB controller.
0 = DISABLE
1 = ENABLE
VBUS_WAKEUP_STS: VBUS wakeup status. This is set to 1 whenever VBUS_WAKEUP sensor

output is 1.
10 RO X
0 = UNSET
1 = SET
VBUS_WAKEUP_CHG_DET: VBUS wakeup change detect. This field is set by hardware whenever
a change is detected in the value of VBUS_WAKEUP. software writes a 1 to clear it
9 RO 0x0
0 = UNSET
1 = SET
VBUS_WAKEUP_INT_EN: VBUS wakeup interrupt enable. If this field is set to 1, an interrupt is

generated whenever VBUS_WAKEUP_CHG_DET is set to 1.
8 RW 0x0
0 = DISABLE
1 = ENABLE
STATIC_GPI: Static GPI status

7 RO X 0 = UNSET
1 = SET
ID_PU: ID pullup enable. Set to 1.

1 = ENABLE
ID_DEB_SEL_B: ID debounce A/B select. Selects between the two debounce values
UTMIP_BIAS_DEBOUNCE_A or UTMIP_BIAS_DEBOUNCE_B from the register
0 = SEL_A
1 = SEL_B
ID_SW_VALUE: ID software value. Software should write the appropriate value (1/0) to set/unset
the ID status. This is only valid when ID_SW_EN is set.
4 RW 0x0
0 = UNSET
1 = SET
ID_SW_EN: ID software enable. Enable Software Controlled ID. Software sets this bit to drive the
value in ID_SW_VALUE to the USB controller
3 RW 0x0
0 = DISABLE
1 = ENABLE
ID_STS: ID status. This is set to 1 whenever ID sensor output is 1.

2 RO X 0 = UNSET
1 = SET
ID_CHG_DET: ID change detect. This field is set by hardware whenever a change is detected in the
value of ID. software writes a 1 to clear it
1 RO 0x0
0 = UNSET
1 = SET
ID_INT_EN: ID interrupt enable. If this field is set to 1, an interrupt is generated whenever

ID_CHG_DET is set to 1.
0 RW 0x0
0 = DISABLE
1 = ENABLE

USB Complex
19.13.2.4 USB1_IF_USB_PHY_ALT_VBUS_STS_0
USB PHY Alternate VBUS/ID Status Register

ID_DIG_C_ALT: IDDIG_C alternate status

14 X 0 = UNSET
1 = SET
ID_DIG_C: IDDIG_C status

13 X 0 = UNSET
1 = SET
ID_DIG_B_ALT: IDDIG_B alternate status

12 X 0 = UNSET
1 = SET
ID_DIG_B: IDDIG_B status

11 X 0 = UNSET
1 = SET
ID_DIG_A_ALT: IDDIG_A alternate status

10 X 0 = UNSET
1 = SET
ID_DIG_A: IDDIG_A status

9 X 0 = UNSET
1 = SET
VDCD_DET_ALT: VDCD_DET alternate status

8 X 0 = UNSET
1 = SET
VDAT_DET_ALT: VDAT_DET alternate status

7 X 0 = UNSET
1 = SET
A_SESS_VLD_ALT: A_SESS_VLD alternate status

6 X 0 = UNSET
1 = SET
B_SESS_VLD_ALT: B_SESS_VLD alternate status

5 X 0 = UNSET
1 = SET
ID_DIG_ALT: ID alternate status

4 X 0 = UNSET
1 = SET
B_SESS_END_ALT: B_SESS_END alternate status

3 X 0 = UNSET
1 = SET
STATIC_GPI_ALT: Static GPI alternate status

2 X 0 = UNSET
1 = SET
A_VBUS_VLD_ALT: A_VBUS_VLD alternate status

1 X 0 = UNSET
1 = SET
VBUS_WAKEUP_ALT: Vbus wakeup alternate status

0 X 0 = UNSET
1 = SET

USB Complex
19.13.2.5 USB1_IF_USB_INTER_PKT_DELAY_CTRL_0
This controls the interpacket delay between two consecutive transmit packets in HS mode. This only applies to host mode as
device never transmits two packets in a row.
Inter Packet Delay Control

Offset: 0x420 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxxxxxxxxxxxxx0010010
6:0 0x12 IP_DELAY_TX2TX_HS: HS Tx to Tx inter-packet delay. Software should not change this.
19.13.2.6 USB1_IF_USB_RSM_DLY_0
USB Controller Resume Signaling Delay

TIME_TO_RESUME: Send the resume back in number of 60 MHz cycles. Default gives 900 µs delay.
15:0 0x6978
Only applicable in host mode.
19.13.2.7 USB1_IF_SPARE_0
For ICUSB PADCTLS. Spare Register
SPARE_HI: Spare register bits, defaulted to 1.

31:16 0xffff
SPARE_HI[0] - usb_port_reset_fix_en. Enable port-reset fix.
SPARE_LO: Spare register bits, defaulted to 0.

15:0 0x0 SPARE_LO[4] - usb_hs_rsm_eop_fix_en, Enable HS_RESUME EOP fix.
SPARE_LO[5] - usb_port_suspend_fix_en.
19.13.2.8 USB1_IF_USB1_NEW_CONTROL_0
USB Coherency and Memory Alignment Controls

Offset: 0x4c0 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxxxx00001111xxxxxx00
15:8 0xf REQUEST_EXPIRY_COUNTER: Time to wait for coalescing the request
MEM_ALIGNMENT_MUX_EN: Mux to select between Tegra 3 style (0) and Tegra K1 style (1) DMA
request generation mechanism
1 0x0
0 = DISABLE
1 = ENABLE
COHERENCY_EN: Enable fence mechanism.

0 0x0 0 = DISABLE
1 = ENABLE.
19.13.3 USB1 UTMIP Configuration Registers

Note: Current UTMIP configuration registers use settings that support NV software drivers and should NOT be
modified. If designing custom drivers, consult your NV representative prior to modifying these registers

USB Complex
19.13.3.1 UTMIP REGISTER: PLL_CFG0

This register was used to configure PLL inside UTMIP block prior to Tegra K1 devices. This has been de-featured from UTMIP
space and moved to CAR space. This register is used to configure the PHY PLL contained in the UTMIP module. Refer to the
Clock and Reset Controller section for details on this register.
Note: This register has been moved to the Clock and Reset section of this document. PROGRAMMING THIS
REGISTER HERE WILL HAVE NO EFFECT!
19.13.3.2 USB1_UTMIP_PLL_CFG1_0
This register was used to configure the PLL inside the UTMIP block prior to Tegra K1 devices. This register has been
defeatured from UTMIP space and moved to CAR space. Refer to the Clock and Reset Controller section for details on this
register.
19.13.3.3 USB1_UTMIP_XCVR_CFG0_0
UTMIP Transceiver Cell Configuration Register 0

31:25 0x10 UTMIP_XCVR_HSSLEW_MSB: Most significant bits of HS_SLEW.
24:22 0x0 UTMIP_XCVR_SETUP_MSB: Most significant bits of SETUP.
21 0x1 UTMIP_XCVR_LSBIAS_SEL: Low speed bias selection method for USB transceiver pad
20 0x0 UTMIP_XCVR_DISCON_METHOD: Disconnect method on the USB transceiver pad
19 0x0 UTMIP_FORCE_PDZI_POWERUP: Force PDZI input into power up.
UTMIP_FORCE_PDZI_POWERDOWN: Force PDZI input into power down. (Overrides

18 0x1
FORCE_PDZI_POWERUP.)
17 0x0 UTMIP_FORCE_PD2_POWERUP: Force PD2 input into power up.
UTMIP_FORCE_PD2_POWERDOWN: Force PD2 input into power down. (Overrides

16 0x1
FORCE_PD2_POWERUP.)
15 0x0 UTMIP_FORCE_PD_POWERUP: Force PD input into power up.
UTMIP_FORCE_PD_POWERDOWN: Force PD input into power down. (Overrides

14 0x1
FORCE_PD_POWERUP.)
13 0x1 UTMIP_XCVR_TERMEN: Enable HS termination.
12 0x0 UTMIP_XCVR_HSLOOPBACK: Internal loopback inside XCVR cell. Used for IOBIST.
11:10 0x1 UTMIP_XCVR_LSFSLEW: LS falling slew rate control.
9:8 0x1 UTMIP_XCVR_LSRSLEW: LS rising slew rate control.
7:6 0x0 UTMIP_XCVR_FSSLEW: FS slew rate control.
5:4 0x0 UTMIP_XCVR_HSSLEW: HS slew rate control. The two LSBs.
3:0 0x0 UTMIP_XCVR_SETUP: SETUP[3:0] input of XCVR cell. HS driver output control. 4 LSBs.

USB Complex
19.13.3.4 USB1_UTMIP_BIAS_CFG0_0
UTMIP Bias Cell Configuration Register 0

Offset: 0x80c | Read/Write: R/W | Reset: 0bx0000000110000000000110000000000
30 0x0 UTMIP_IDDIG_C_VAL: See IDDIG_C_SEL.
29 0x0 UTMIP_IDDIG_C_SEL: 0: IdDig_c = IdDig_c. 1: IdDig_c = IDDIG_C_VAL.
28 0x0 UTMIP_IDDIG_B_VAL: See IDDIG_B_SEL.
27 0x0 UTMIP_IDDIG_B_SEL: 0: IdDig_b = IdDig_b. 1: IdDig_b = IDDIG_B_VAL.
26 0x0 UTMIP_IDDIG_A_VAL: See IDDIG_A_SEL.
25 0x0 UTMIP_IDDIG_A_SEL: 0: IdDig_a = IdDig_a. 1: IdDig_a = IDDIG_A_VAL.
24 0x0 UTMIP_HSDISCON_LEVEL_MSB: Most significant bit of UTMIP_HSDISCON_LEVEL, bit 2
23 0x1 UTMIP_IDPD_VAL: See IDPD_SEL.
22 0x1 UTMIP_IDPD_SEL: 0: Reserved. Refer to the PMC registers for this feature.
21 0x0 UTMIP_IDDIG_VAL: See IDDIG_SEL.
20 0x0 UTMIP_IDDIG_SEL: 0: IdDig = IdDig. 1: IdDig = IDDIG_VAL.
19 0x0 UTMIP_GPI_VAL: See GPI_SEL.
18 0x0 UTMIP_GPI_SEL: 0: StaticGpi = IdDig. 1: StaticGpi = GPI_VAL.
17:15 0x0 UTMIP_ACTIVE_TERM_OFFSET: Active termination control offset.
14:12 0x0 UTMIP_ACTIVE_PULLUP_OFFSET: Active 1.5K pullup control offset.
11 0x1 UTMIP_OTGPD: Power down OTG circuit.
10 0x1 UTMIP_BIASPD: Power down bias circuit.
9:8 0x0 UTMIP_VBUS_LEVEL_LEVEL: Vbus detector level.
7:6 0x0 UTMIP_SESS_LEVEL_LEVEL: SessionEnd detector level.
5:4 0x0 UTMIP_HSCHIRP_LEVEL: HS chirp detector level.
3:2 0x0 UTMIP_HSDISCON_LEVEL: HS disconnect detector level.
1:0 0x0 UTMIP_HSSQUELCH_LEVEL: HS squelch detector level.
19.13.3.5 USB1_UTMIP_HSRX_CFG0_0
UTMIP High Speed Receive Config 0

31:30 0x2 UTMIP_KEEP_PATT_ON_ACTIVE: Keep the stay alive pattern on active
29 0x0 UTMIP_ALLOW_CONSEC_UPDN: Allow consecutive ups and downs on the bits, debug only, set to 0.
28 0x1 UTMIP_REALIGN_ON_NEW_PKT: Realign the inertia counters on a new packet
27:24 0x1 UTMIP_PCOUNT_UPDN_DIV: The number of (edges-1) needed to move the sampling point
23:21 0x3 UTMIP_SQUELCH_EOP_DLY: Limit the delay of the squelch at EOP time
20 0x0 UTMIP_NO_STRIPPING: Do not strip incoming data
19:15 0xa UTMIP_IDLE_WAIT: Number of idle cycles to declare IDLE.

USB Complex
14:10 0xd UTMIP_ELASTIC_LIMIT: Depth of elastic input store
9 0x0 UTMIP_ELASTIC_OVERRUN_DISABLE: Do not declare overrun errors until overflow of FIFO
8 0x0 UTMIP_ELASTIC_UNDERRUN_DISABLE: Do not declare underrun errors
7 0x0 UTMIP_PASS_CHIRP: When in Chirp Mode, allow chirp RX data through
6 0x0 UTMIP_PASS_FEEDBACK: Pass through the feedback, do not block it.
5:4 0x0 UTMIP_PCOUNT_INERTIA: Retime the path.
3:2 0x0 UTMIP_PHASE_ADJUST: Based on incoming edges and current sampling position, adjust phase
1 0x0 UTMIP_THREE_SYNCBITS: Sync pattern detection needs 3 consecutive samples instead of 4
0 0x0 UTMIP_USE4SYNC_TRAN: Require 4 sync pattern transitions (01) instead of 3

Offset: 0x814 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxxxxxxxxxxxxxx010011
5:1 0x9 UTMIP_HS_SYNC_START_DLY: How long to wait before start of sync launches RxActive
0 0x1 UTMIP_HS_ALLOW_KEEP_ALIVE: Allow Keep Alive packets
19.13.3.7 USB1_UTMIP_FSLSRX_CFG0_0
UTMIP Full and Low Speed Receive Config 0

31 0x1 UTMIP_FSLS_SE1_DRIBBLE_FILTER: One SE1, do not allow dribble
30 0x1 UTMIP_FSLS_SE1_FILTER: Filter SE1
29 0x1 UTMIP_FSLS_SERIAL_SE0_RCV
28:26 0x7 UTMIP_FSLS_UPR_DRIBBLE_SIZE: Do not allow <= dribble bits
25:23 0x2 UTMIP_FSLS_LWR_DRIBBLE_SIZE: Do not allow >= dribble bits
22 0x1 UTMIP_FSLS_EOP_ENDS_AT_SE0: Only look for transitioning out of EOP
21:16 0x14 UTMIP_FSLS_KCOUNT_MAX: Number of K bits in question
15 0x1 UTMIP_FSLS_KCOUNT_LIMIT: Limit the number of bit times a K can last
14 0x0 UTMIP_FSLS_ACTIVE_ON_FULL_SYNC: Require a full sync pattern to declare the data received
13:8 0x4 UTMIP_FSLS_IDLE_WAIT_MAX: 4 bits of SEO should exceed the time limit
7 0x0 UTMIP_FSLS_IDLE_WAIT_LIMIT: Enable the reset of the state machine on extended SE0
6:1 0x14 UTMIP_FSLS_IDLE_COUNT_MAX: 20 bits of idle should end the packet if FsLsIdleCountLimitCfg=1.
0 0x1 UTMIP_FSLS_IDLE_COUNT_LIMIT: Give up on packet if a long sequence of J

USB Complex

Offset: 0x81c | Read/Write: R/W | Reset: 0bxxxxx010001001100111010000000000
26 0x0 UTMIP_EARLY_LINE_STATE_FILTER: Assumes line state filtering table is inclusive, not exclusive
25:23 0x4 UTMIP_LS_BOUNCE_LENGTH: Number of clock cycle of LS stable
22:17 0x13 UTMIP_LS_EXTRACTION_COUNT: Phase count on which LS bits are extracted
16:11 0xe UTMIP_LS_EOP_START_COUNT: Number of SEO clock cycles to block bit extraction
10:5 0x20 UTMIP_LS_SE0_COUNT: Only for this number of 60MHz of SEO and Idle to end packet
4 0x0 UTMIP_LS_LENIENT_DRIBBLE: Allow for large dribble in low speed mode
3 0x0 UTMIP_FS_LENIENT_DRIBBLE: Allow for large dribble in full speed mode
2 0x0 UTMIP_FS_WEAK_SYNC: Only look for a KK pattern, instead of KJKK
1 0x0 UTMIP_FS_DEBOUNCE: Whether full speed uses debouncing
0 0x0 UTMIP_FS_EOP_LENGTH: Whether full speed EOP is determined within 3(0) or 4(1) 60MHz cycles
19.13.3.9 USB1_UTMIP_TX_CFG0_0
UTMIP Transmit Config Signals

Offset: 0x820 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxx00010000001000000000
19 0x0 UTMIP_FS_PREAMBLE_J: Output enable sends an initial J before sync pattern
18 0x0 UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE: Output enable turns off 1/2 cycle after
17 0x0 UTMIP_FS_PREAMBLE_OUTPUT_ENABLE: Output enable turns on 1/2 cycle before
16 0x1 UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR: Allow SOP to be source of transmit error stuffing
15 0x0 UTMIP_HS_READY_WAIT_FOR_VALID
14:10 0x0 UTMIP_HS_TX_IPG_DLY
9 0x1 UTMIP_HS_DISCON_EOP_ONLY: Only check during EOP
8 0x0 UTMIP_HS_DISCON_DISABLE: Disable high speed disconnect
7 0x0 UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE: Output enable turns off 1 cycle after
6 0x0 UTMIP_HS_PREAMBLE_OUTPUT_ENABLE: Output enable turns on 1 cycle before
5 0x0 UTMIP_SIE_RESUME_ON_LINESTATE: SIE, not macrocell, detects LineState change to resume
UTMIP_SOF_ON_NO_STUFF: SOF when OpMode 3 -- perhaps, when sending controller made

4 0x0
packets
3 0x0 UTMIP_SOF_ON_NO_ENCODE: SOF when OpMode 2 -- not likely, for Chirp
2 0x0 UTMIP_NO_STUFFING: No bit stuffing, static programming
1 0x0 UTMIP_NO_ENCODING: No encoding, static programming
0 0x0 UTMIP_NO_SYNC_NO_EOP: Do not send SYNC or EOP

USB Complex
19.13.3.10 USB1_UTMIP_MISC_CFG0_0

Offset: 0x824 | Read/Write: R/W | Reset: 0bx0000011111000000000000001111000
30:27 0x0 UTMIP_DPDM_OBSERVE_SEL: Select DP/DM obs signals
26 0x0 UTMIP_DPDM_OBSERVE: Use DP/DM as obs bus
25 0x1 UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON
24 0x1 UTMIP_ALLOW_LS_ON_SOFT_DISCON
23 0x1 UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP
22 0x1 UTMIP_SUSPEND_EXIT_ON_EDGE: Suspend exit requires edge or simply a value.
UTMIP_LS_TO_FS_SKIP_4MS: Do not block changes for 4 ms when going from LS to FS (should not
21 0x1
happen)
UTMIP_INJECT_ERROR_TYPE: Force error insertion into RX path. (Used for IOBIST.)

0 = DISABLE
20:19 0x0 1 = BIT_ERR
2 = RX_ERR
3 = BIT_RX_ERR
18 0x0 UTMIP_FORCE_HS_CLOCK_ON: Force HS clock always on.
17 0x0 UTMIP_DISABLE_HS_TERM: Force HS termination inactive.
16 0x0 UTMIP_FORCE_HS_TERM: Force HS termination active.
15 0x0 UTMIP_DISABLE_PULLUP_DP: Force DP pullup inactive. (Overrides FORCE_PULLUP_DP.)
14 0x0 UTMIP_DISABLE_PULLUP_DM: Force DM pullup inactive. (Overrides FORCE_PULLUP_DM.)
13 0x0 UTMIP_DISABLE_PULLDN_DP: Force DP pulldown inactive. (Overrides FORCE_PULLDN_DP.)
12 0x0 UTMIP_DISABLE_PULLDN_DM: Force DM pulldown inactive. (Overrides FORCE_PULLDN_DM.)
11 0x0 UTMIP_FORCE_PULLUP_DP: Force DP pullup active.
10 0x0 UTMIP_FORCE_PULLUP_DM: Force DM pullup active.
9 0x0 UTMIP_FORCE_PULLDN_DP: Force DP pulldown active.
8 0x0 UTMIP_FORCE_PULLDN_DM: Force DM pulldown active.
7:5 0x3 UTMIP_STABLE_COUNT: Number of cycles of crystal clock of signal not changing to consider stable.
4 0x1 UTMIP_STABLE_ALL: Determines if all signal need to be stable to not change a config.
3 0x1 UTMIP_NO_FREE_ON_SUSPEND: Do not use free running terminations during suspend.
2 0x0 UTMIP_NEVER_FREE_RUNNING_TERMS: Ignore free-running terminations, even when no clock
1 0x0 UTMIP_ALWAYS_FREE_RUNNING_TERMS: Use free-running terminations at all time
0 0x0 UTMIP_COMB_TERMS: Use combinational terminations or synced through CLKXTAL

30 0x1 UTMIP_PHY_XTAL_CLOCKEN: Selects whether to enable the crystal clock in the module.

USB Complex
29 0x0 UTMIP_LINESTATE_BYPASS: Bypass LineState reclocking logic
28 0x0 UTMIP_LINESTATE_NEG: Use negative edge sync for line state
UTMIP_LINESTATE_XCVRSEL3: 0: Use FS filtering on line state when XcvrSel=3 1: Use LS filtering

27 0x0
on line state when XcvrSel=3
26:25 0x0 UTMIP_OBS_SEL
24 0x0 UTMIP_FSLS_TDM
23 0x0 UTMIP_FORCE_IOBIST_CLK_ON
22:18 0x6 UTMIP_PLL_ACTIVE_DLY_COUNT: Reserved. Config moved to the Clock and Reset space.
17:6 0x600 UTMIP_PLLU_STABLE_COUNT: Reserved. Moved to the Clock and Reset space.
5 0x1 UTMIP_RX_ERROR_CNT_CLR
4 0x0 UTMIP_RX_ERROR_CNT_EN
3 0x0 UTMIP_FLIP_FSLS_POLARITY
2 0x1 UTMIP_SUSPEND_TERMSEL
UTMIP_XCVRSEL3: Bit 0: 0: 0xa5 -> treat as KeepAlive 1: treat as regular packet

1:0 0x0
Bit 1: 0: Turn on FS EOP detection 1: Turn off FS EOP detection
19.13.3.12 USB1_UTMIP_DEBOUNCE_CFG0_0
UTMIP Avalid and Bvalid Debounce

Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and SessEnd. Each of these signals has its own debouncer,
and for each of those one out of 2 debouncing times can be chosen (BIAS_DEBOUNCE_A or BIAS_DEBOUNCE_B.)
The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
0xffff -> No debouncing at all
ms = *1000 / (1/19.2MHz) / 4
So to program a 1 ms debounce for BIAS_DEBOUNCE_A:
BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0
31:16 0xffff UTMIP_BIAS_DEBOUNCE_B: simulation value -- Used for interrupts
15:0 0xffff UTMIP_BIAS_DEBOUNCE_A: simulation value -- Used for interrupts
19.13.3.13 USB1_UTMIP_BAT_CHRG_CFG0_0
UTMIP Battery Charger Configuration

Offset: 0x830 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxxxxxx000000xx000001
UTMIP_CHRG_DEBOUNCE_TIMESCALE: Debouncer time scaling, factor-1 to slow down debouncing

13:8 0x0
by. So 0 is 1, 1 is 2, etc.
5 0x0 UTMIP_OP_I_SRC_EN
4 0x0 UTMIP_ON_SRC_EN

USB Complex
3 0x0 UTMIP_OP_SRC_EN
2 0x0 UTMIP_ON_SINK_EN
1 0x0 UTMIP_OP_SINK_EN
0 0x1 UTMIP_PD_CHRG: Power down charger circuit
19.13.3.14 USB1_UTMIP_SPARE_CFG0_0
UTMIP Spare Configuration Bits

UTMIP_SPARE: Spare register bits

0: HS_RX_IPG_ERROR_ENABLE
1: HS_RX_FLUSH_ALAP. Flush as late as possible
2: HS_RX_LATE_SQUELCH. Delay Squelch by 1 CLK480 cycle.
3: FUSE_SETUP_SEL. Select between regular CFG value and JTAG values for UX_SETUP
31:0 -65288 4: FUSE_TERM_RANGE_ADJ_SEL. Select between regular CFG value and JTAG values for
UX_TERM_RANGE_ADJ
5: FUSE_SPARE. Select between regular CFG value and JTAG values. For any ECOs.
6: FUSE_HS_SQUELCH_LEVEL. Select between regular CFG value and JTAG values
7: FUSE_HS_IREF_CAP_CFG. Select between regular CFG value and JTAG values
31 to 8: Reserved

Offset: 0x838 | Read/Write: R/W | Reset: 0bxxxx0000000110001000001000010101
27:26 0x0 UTMIP_XCVR_RPU_RANGE_ADJ: 1.5k pull-up resistor range shift.
25:24 0x0 UTMIP_XCVR_HS_IREF_CAP: High-speed Iref cap control for bias current stability.
23:22 0x0 UTMIP_XCVR_SPARE: Spare bits for USB transceiver pad.
21:18 0x6 UTMIP_XCVR_TERM_RANGE_ADJ: Range adjustment on terminations.
17 0x0 UTMIP_RCTRL_SW_SET: Use a software override on RCTRL instead of automatic bias control.
UTMIP_RCTRL_SW_VAL: Encoded value to use on RCTRL when software override is enabled, 0 to 16

16:12 0x8
only.
11 0x0 UTMIP_TCTRL_SW_SET: Use a software override on TCTRL instead of automatic bias control
UTMIP_TCTRL_SW_VAL: Encoded value to use on TCTRL when software override is enabled, 0 to 16

10:6 0x8
only.
5 0x0 UTMIP_FORCE_PDDR_POWERUP: Force PDDR input into power up.
UTMIP_FORCE_PDDR_POWERDOWN: Force PDDR input into power down. (Overrides

4 0x1
FORCE_PDDR_POWERUP.)
3 0x0 UTMIP_FORCE_PDCHRP_POWERUP: Force PDCHRP input into power up.
UTMIP_FORCE_PDCHRP_POWERDOWN: Force PDCHRP input into power down. (Overrides

2 0x1
FORCE_PDCHRP_POWERUP.)
1 0x0 UTMIP_FORCE_PDDISC_POWERUP: Force PDDISC input into power up.

USB Complex
UTMIP_FORCE_PDDISC_POWERDOWN: Force PDDISC input into power down. (Overrides

0 0x1
FORCE_PDDISC_POWERUP.)

Offset: 0x83c | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxxxxxx00000000101101
UTMIP_BIAS_DEBOUNCE_TIMESCALE: Debouncer time scaling. Slows down debouncing by a factor-

13:8 0x0
1. So 0 is 1, 1 is 2, etc.
UTMIP_BIAS_PDTRK_COUNT: Control the BIAS cell power down lag. The lag should be 20 µs. For a
7:3 0x5
crystal clock of 13 MHz, it should be set to 5.
2 0x1 UTMIP_VBUS_WAKEUP_POWERDOWN: Reserved. See the PMC registers for this functionality.
1 0x0 UTMIP_FORCE_PDTRK_POWERUP: Force PDTRK input into power up.
UTMIP_FORCE_PDTRK_POWERDOWN: Force PDTRK input into power down. (Overrides

0 0x1
FORCE_PDTRK_POWERUP.)
19.13.3.17 USB1_UTMIP_BIAS_STS0_0
UTMIP Bias Cell Status Register 0

31:16 X UTMIP_TCTRL: Thermal encoding output from USB bias pad.
15:0 X UTMIP_RCTRL: Thermal encoding output from USB bias pad.
19.13.3.18 USB1_UTMIP_CHRG_DEB_CFG0_0
UTMIP VDcd_Det and VDat_Det Debounce

Debounce values VDcd_Det and VDat_Det. Each of these signals has its own debouncer and for each of those, 1 out of 2
debouncing times can be chosen (CHRG_DEBOUNCE_PERIOD_A or CHRG_DEBOUNCE_PERIOD_B).
The values of DEBOUNCE_PERIOD_A and DEBOUNCE_PERIOD_B are calculated as follows:
ms = *1000 / (1/19.2MHz) / 4
So to program a 1 ms debounce for CHG_DEBOUNCE_PERIOD:
CHG_DEBOUNCE_PERIOD[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0
31:16 0xffff UTMIP_CHRG_DEBOUNCE_PERIOD_B: Simulation value -- Used for interrupts
15:0 0xffff UTMIP_CHRG_DEBOUNCE_PERIOD_A: Simulation value -- Used for interrupts

USB Complex
19.13.3.19 USB1_UTMIP_MISC_STS0_0
UTMIP MISC Status Register

21 X UTMIP_FS_DRV_EN: Indicates when the controller is driving on the bus
20:0 X UTMIP_SPARE_FUSES: Spare Fuses value to keep the connections preserved
19.13.3.20 USB1_UTMIP_PMC_WAKEUP0_0
UTMIP PMC Wakeup value

Offset: 0x84c | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0
1 RO X UTMIP_LINE_WAKEUP_EVENT_INT_STS: Indicates the status of the PMC wakeup event
0 RW 0x0 UTMIP_LINE_WAKEUP_EVENT_INT_ENB: Interrupt mask for the PMC wakeup event
19.13.3.21 USB2_QH_USB2D_QH_EP_n_OUT_0
USB2D Queue Head for OUT Endpoint n

There are 16 USB2D Queue Head for OUT Endpoint registers, where n = 0 through 15.
Offset: 0x1000 + (n * 0x80) | Read/Write: R/W | Reset: 0b00000000000000000000000000000000
USB2D_QH: Queue Head for OUT endpoint n. This is used to store a local Queue Head data structure
31:0 0x0
for either device mode or host mode. In device mode, it holds the Queue Head for OUT endpoint n.
19.13.3.22 USB2_QH_USB2D_QH_EP_n_IN_0
USB2D Queue Head for IN Endpoint n

There are 16 USB2D Queue Head for IN Endpoint registers, where n = 0 through 15.
USB2D_QH: Queue Head for IN endpoint n. This is used to store a local Queue Head data structure for
31:0 0x0
either device mode or host mode. In device mode, it holds the Queue Head for IN endpoint n.
19.13.4 USB2 Controller Registers
19.13.4.1 USB2_CONTROLLER_1_USB2D_ID_0


USB Complex
19.13.4.2 USB2_CONTROLLER_1_USB2D_HW_HOST_0

19.13.4.3 USB2_CONTROLLER_1_USB2D_HW_DEVICE_0

5:1 X
19.13.4.4 USB2_CONTROLLER_1_USB2D_HW_TXBUF_0

23:16 X
15:8 X
7:0 X
19.13.4.5 USB2_CONTROLLER_1_USB2D_HW_RXBUF_0

15:8 X
depth of the receive buffer is 128 words.

USB Complex
7:0 X
19.13.4.6 USB2_CONTROLLER_1_USB2D_GPTIMER0LD_0
GPTIMER0LD: This field has the value to be loaded into the GPTCNT countdown timer on a reset action.
23:0 0x0
19.13.4.7 USB2_CONTROLLER_1_USB2D_GPTIMER0CTRL_0
31 RW 0x0
30 WO 0x0 GPTRST: Writing a one to this bit reloads the GPTCNT with the value in GPTLD.
shot mode, the timer counts down to zero, generates an interrupt, and stops until the counter is
24 RW 0x0
reset by software. In repeat mode, the timer counts down to zero, generates an interrupt, and
automatically reloads the counter to begin again.
23:0 RO X GPTCNT: This field has the value of the running timer.
23:0 0x0
31 RW 0x0
24 RW 0x0

USB Complex
19.13.4.10 USB2_CONTROLLER_1_USB2D_CAPLENGTH_0

7:0 X
19.13.4.11 USB2_CONTROLLER_1_USB2D_HCIVERSON_0

19.13.4.12 USB2_CONTROLLER_1_USB2D_HCSPARAMS_0

N_PTT: Number of Ports per Transaction Translator: Indicates the number of ports assigned to each
23:20 X transaction translator within the USB2.0 host controller. Field always equals N_PORTS. This is a non-
15:12 X
set to 0.
11:8 X
control.
1 = Ports have port power switches
4 X
0= Ports do not have port power switches.
This field affects the functionality of the port Power field in each port status and control register. This
field is set to 1.
3:0 X
19.13.4.13 USB2_CONTROLLER_1_USB2D_HCCPARAMS_0

PPC: Per-Port Change Event Capability. Default = 1b. This field indicates the support for per-port change
18 X
events. This field is related to the USBCMD PPE field, USBSTS PPCI field, and USBINTR PPCE field.

USB Complex
LEN: Link Power Management Capability. Default = 1b. This field indicates the support for LPM L1 state.
17 X This field is related to the USBCMD HIRD field, POSTSCx SSTS and DA fields, and HOSTPCx LEN, BA,
and EPLPM fields.
15:8 X
7:4 X
2 X
PFL: Programmable Frame List Flag. 0 = System software must use a frame list length of 1024 elements
with this host controller. The USBCMD register Frame List Size field is a read-only register and must be
set to zero. 1 = System software can specify and use a smaller frame list and configure the host
1 X
controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-
page boundary. This requirement ensures that the frame list is always physically contiguous. This field
will always be "1".
19.13.4.14 USB2_CONTROLLER_1_USB2D_DCIVERSION_0

15:0 X
19.13.4.15 USB2_CONTROLLER_1_USB2D_DCCPARAMS_0

HC: Host Capable: 1 = This controller is capable of operating as an EHCI compatible USB 2 0 host
8 X
controller operating as an EHCI compatible USB 2.0 host controller. This field is set to 1.
7 X DC: Device Capable: 1 = Controller is capable of operating as USB 2.0 device. This field is set to 1
5 X
state. This field is related to the DEVLCx ASUS, STL,BA and NYT fields.

USB Complex
19.13.4.16 USB2_CONTROLLER_1_USB2D_EXTSTS_0

4 RW 0x0
3 RW 0x0
2 RW 0x0
0 = DISABLE
1 = ENABLE
1 RW 0x0
0 = DISABLE
1 = ENABLE
0 RO X
bits are cleared.
0 = DISABLE
1 = ENABLE
19.13.4.17 USB2_CONTROLLER_1_USB2D_USBEXTINTR_0

UPIE: UPIE Interrupt Enable. 1 = USB controller issues an interrupt if the UPA bit in USBSTS register
transitions.
2 0x0
0 = DISABLE
1 = ENABLE
UAIE: UAIE Interrupt Enable. 1 = USB controller issues an interrupt if the UAI bit in USBSTS register
transitions.
1 0x0
0 = DISABLE
1 = ENABLE
NAKE: NAK Interrupt Enable. 1 = USB controller issues an interrupt if the NAKI bit in USBSTS register
transitions.
0 0x0
0 = DISABLE
1 = ENABLE

USB Complex
19.13.4.18 USB2_CONTROLLER_1_USB2D_USBCMD_0

27:24 RW 0x0
LPM Token, specifically: a value 0000b equals 50µs and each additional increment adds 75µs.
For example, the value 0001b equals 125µs, and a value 1111b equals 1,175µs (~1.2ms).
maximum interrupt interval measured in micro-frames. Valid values are shown below.
Value Maximum Interrupt Interval
00h Immediate (no threshold)
01h 1 micro-frame
02h 2 micro-frames
04h 4 micro-frames
08h 8 micro-frames
23:16 RW 0x8 10h 16 micro-frames
20h 32 micro-frames
40h 64 micro-frames
0 = IMMEDIATE
2 = ONE_MF
4 = TWO_MF
8 = EIGHT_MF
16 = SIXTEEN_MF
32 = THIRTY_TWO_MF
64 = SIXTY_FOUR_MF
ATDTW: Add DTD Tripwire. This bit is used as a semaphore when a dTD is added to an active
0 = CLEAR
1 = SET
setup data arrives and firmware is copying setup data from the QH for a previous setup packet.
13 RW 0x0
This bit is set and cleared by software and will be cleared by hardware when a hazard exists.
0 = CLEAR
1 = SET
0 = DISABLE
1 = ENABLE

9:8 RW 0x3 3h and is R/W. Otherwise it defaults to zero and is RO. It contains a count of the number of
successive transactions the host controller is allowed to execute from a high-speed queue head
on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid
values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as

USB Complex

this will result in undefined behavior. This field is set to 3h in this implementation and is
Read/Write capable.
LR: Light Host/Device Controller Reset (OPTIONAL) . Read Only. Not Implemented. This field will
7 RO X
always be "0".
6 RW 0x0
Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so
will yield undefined results. This bit is only used in host mode. Writing a one to this bit when
device mode is selected will have undefined results.
0 = CLEAR
1 = SET
processing the Asynchronous Schedule. 0 = Do not process the Asynchronous Schedule. 1 =
Use the ASYNCLISTADDR register to access the Asynchronous Schedule. Only the host
5 RW 0x0
0 = DISABLE
1 = ENABLE
Periodic Schedule. 0 = Do not process the Periodic Schedule 1 = Use the PERIODICLISTBASE
4 RW 0x0 register to access the Periodic Schedule. Only the host controller uses this bit.
0 = DISABLE
1 = ENABLE
FS1_FS0: Frame List Size. (Read/Write). 000 = Default. This field is Read/Write only if
Programmable Frame List Flag in the HCCPARAMS registers is set to one. Hence this field is
Read/Write for this implementation. This field specifies the size of the frame list that controls
which bits in the Frame Index Register should be used for the Frame List Current index. Note that
this field is made up from USBCMD bits 15, 3, and 2.
3:2 RW 0x0 010 = 256 elements (1024 bytes)
process early by writing a zero to this register. Host Controller: When software writes a one to this
bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their
initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset
is not driven on downstream ports. Software should not set this bit to a one when the HCHalted
1 RW 0x0 bit in the USBSTS register is a zero. Attempting to reset an actively running host controller results
in undefined behavior. Device Controller: When software writes a one to this bit, the Device
Controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value.
Any transaction currently in progress on USB is immediately terminated. Writing a one to this bit
in device mode is not recommended.
0 = CLEAR
1 = SET
0 RW 0x0 transaction and has entered the stopped state. Software should not write a one to this field unless
the host controller is in the Halted state (i.e., HCHalted in the USBSTS register is a one). Device
Controller: Writing a one to this bit will cause the device controller to enable a pull-up on D+ and
initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-
up will become disabled upon transitioning into high-speed mode. Software should use this bit to

USB Complex

prevent an attach event before the device controller has been properly initialized. Writing a 0 to
this will cause a detach event.
0 = STOP
1 = RUN
19.13.4.19 USB2_CONTROLLER_1_USB2D_USBSTS_0

AS: Asynchronous Schedule Status. This bit reports the current status of the Asynchronous
15 RW 0x0 USBCMD register.
If AS = ASE: 1= Enable Asynchronous Schedule. 0= Disable Asynchronous Schedule.
0 = DISABLE
1 = ENABLE
PS: Periodic Schedule Status. This bit reports the current status of the Periodic Schedule. When
set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host
Controller is not required to immediately disable or enable the Periodic Schedule when software
transitions the Periodic Schedule Enable bit in the USBCMD register.
14 RW 0x0
If PS = PSE:: 1 = Periodic Schedule is enabled. 0 = Periodic Schedule is disabled.
0 = DISABLE
1 = ENABLE
13 RO X
0 = DISABLE
1 = ENABLE
12 RW 0x1
host controller.
0 = UNHALTED
1 = HALTED
UALT_INT: ULPI alt_int Interrupt. 0 = Default. This interrupt bit is set when an RXCMD is
received through the ULPI interface with bit 7 set (alt_int). The alt_int bit is set when an
unmasked event occurs on any bit in the Carkit Interrupt Latch Register, in the ULPI PHY. The
11 RW 0x0 Viewport to check the source of the interrupt. Only present in designs where configuration
1 = ULPI_ALT_INT
10 RW 0x0
0 = NOT_ULPI_INT
1 = ULPI_INT

USB Complex
0 = NOTSUSPEND
1 = SUSPENDED
indicate that an SOF was expected. Therefore, this bit will be set roughly every 1ms in device FS
Since device controller is initialized to FS before connect, this bit will be set at an interval of 1ms
7 RW 0x0
during the prelude to the connect and chirp. In host mode, this bit will be set every 125 µs and
can be used by host controller driver as a time base. Software writes a 1 to this bit to clear it. This
is a non-EHCI status bit.
0 = SOF_NOT_RCVD
1 = SOF_RCVD
0 = NO_USB_RESET
1 = USB_RESET
5 RW 0x0
indicates the assertion of that interrupt source. Only used by the host controller.
0 = NOT_ADVANCED
1 = ADVANCED
4 RO X 0 = NO_ERROR
1 = ERROR
frame list size. For example. If the frame list size (as programmed in the Frame List Size field of
3 RW 0x0
0 = NO_ROLLOVER
1 = ROLLOVER
mechanisms are the USB Reset Received bit and the DCSuspend bits respectively. This bit is not
EHCI compatible.
0 = NO_PORT_CHANGE
1 = PORT_CHANGE
1 RW 0x0 on which the error interrupt occurred also ad its interrupt on complete (IOC) bit set.
0 = NO_ERROR
1 = ERROR
bytes.
0 = NO_INT
1 = INT

USB Complex
19.13.4.20 USB2_CONTROLLER_1_USB2D_USBINTR_0

31:16 0x0
UALTIE: ULPI alt_int Interrupt Enable. 1 = USB controller issues an interrupt if the ULPI_ALT_INT bit in
the USBSTS register transitions. The interrupt is acknowledged by software writing a 1 to the
0 = DISABLE
1 = ENABLE
10 0x0
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
7 0x0
0 = DISABLE
1 = ENABLE
register = 1. The interrupt is acknowledged by software clearing the USB Reset Received bit. Only used
0 = DISABLE
1 = ENABLE
AAE: Interrupt on Asynchronous Advance Enable. 1 = the host controller issues an interrupt at the next
interrupt threshold if the Interrupt on Async Advance bit in the USBSTS register = 1. The interrupt is
0 = DISABLE
1 = ENABLE
SEE: System Error Enable. 1 = Host/device controller issues an interrupt if the System Error bit in the
4 0x0
0 = DISABLE
1 = ENABLE
FRE: Frame List Rollover Enable. 1 = Host controller issues an interrupt if the Frame List Rollover bit in
the USBSTS register = 1. The interrupt is acknowledged by software clearing the Frame List Rollover
3 0x0 bit. Only used by the host controller.
0 = DISABLE
1 = ENABLE
2 0x0 bit.
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE

USB Complex
0 0x0
0 = DISABLE
1 = ENABLE
19.13.4.21 USB2_CONTROLLER_1_USB2D_FRINDEX_0

based on the value of the Frame List Size field in the USBCMD register, when used in host mode.
USBCMD [Frame List Size] Number Elements N
000b (1024) 12
001b (512) 11
13:0 X 010b (256) 10
011b (128) 9
100b (64) 8
101b (32) 7
110b (16) 6
111b (8) 5
index. In either mode, bits 2:0 indicate the current micro-frame.
19.13.4.22 USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0

31:25 0x0
device address within 2ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with
USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement.
the system memory. HCD loads this register prior to starting the schedule execution by the Host
31:12 0x0

USB Complex
19.13.4.23 USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0

reference a list of up to 32 Queue Heads (QH). Only used by the device controller.
19.13.4.24 USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0

30:24 RW 0x0 TTHA: Internal TT Hub Address representation. This field is used to match the Hub Address field
in QH (queue head) and siTD to determine if the packet is routed to the internal TT for directly
attached FS/LS devices. If the Hub Address in the QH or siTD does not match this address, then
the packet will be broadcast on the High-Speed ports destined for a downstream High Speed hub
with the address in QH/siTD.
TTAC: Embedded TT Async Buffers Clear. (Read/Write to set). This field will clear all pending
1 RW 0x0
TTAS: Embedded TT Async Buffers Status. (Read Only). This read-only bit will be 1 if one or
19.13.4.25 USB2_CONTROLLER_1_USB2D_BURSTSIZE_0
USB2D Burst Size register

15:8 0x8
7:0 0x8
19.13.4.26 USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0

21:16 0x2 that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The
minimum value is 2, and this value should be a low as possible to maximize USB performance. A higher
value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO

USB Complex

is set.
TXSCHHEALTH: Scheduler Health Counter. (Read/Write To Clear) [Default = 0] This register

TXSCHOH: Scheduler Overhead. (Read/Write) [Default = 0] This register adds an additional fixed offset
to the schedule time estimator described above as Tff. As an approximation, the value chosen for this
register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per
7:0 0x0 second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can
needlessly reduce USB utilization. The time unit represented in this register is 1.267 µs when a device
is connected in High-Speed Mode. The time unit represented in this register is 6.333 µs when a device
is connected in Low/Full Speed Mode
19.13.4.27 USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0
USB2D ICUSB Control Register

PTS bits must be set to 11 in the PORTSCx. Writing a '1' to this bit selects the IC_USB interface.
3 0x0
0 = DISABLE
1 = ENABLE
000= No voltage
010= 1.2V - reserved
011= 1.5V - reserved
2:0 0x0
100 = 1.8V
101 = 3.0V
110 = reserved
111 = reserved
The Voltage negotiation should happen between enabling port power (PP) and asserting the run/stop bit.
19.13.4.28 USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0
Note: EXECUTING READ OPERATIONS THROUGH THE ULPI VIEWPORT SHOULD HAVE NO HARMFUL
SIDE EFFECTS TO STANDARD USB OPERATIONS.
There are two operations that can be performed with the ULPI Viewport-- wakeup and read /write operations.
The wakeup operation is used to put the ULPI interface into normal operation mode and re-enable the clock if necessary. A
mode, or Carkit mode.

USB Complex
To execute a wakeup operation, write all 32 bits of the ULPI Viewport where ULPI_PORT is constructed appropriately and the
complete.
was a read.
Control register.
Please refer to the ULPI Specification Revision 1.1 for further information on the use of the optional features.

31 RW 0x0
at the same time.
0 = CLEAR
1 = SET
30 RW 0x0
at the same time.
0 = CLEAR
1 = SET
29 RW 0x0
0 = READ
1 = WRITE
ULPI_SYNC_STATE: ULPI sync state. (1) Normal Sync. State. (0) In another state (i.e., Carkit,
27 RO X
0 = NOT_NORMAL
1 = NORMAL
23:16 RW 0x0
15:8 RO X
7:0 RW 0x0 ULPI_DATA_WR: ULPI PHY data write. The data to write to the ULPI PHY register is written

USB Complex

here.
19.13.4.29 USB2_CONTROLLER_1_USB2D_PORTSC1_0

DA: Device Address. Default = 0000000b. The 7-bit USB device address for the device attached
to an immediately downstream of the associated root port. A value of zero indicates no device is
present or software support for this feature is not present. This is used by the Controller when
31:25 RW 0x0 sending the LPM token.
This field is only valid when the core is operating in host mode. If in device mode it will be read
only and always equal to 0000000b.
SSTS: Suspend Status. Default = 00b. These two bits are used by software to determine whether
an L1-based suspend request was successful, specifically:
these bits is invalid whenever bit 7 of this register (SUSP) is one. Ideally, the Controller driver
24:23 RO X
possible L1 failure.
This field is only valid when the core is operating in host mode. If in device mode it will be always
equal to 00b.
0 = L1STATE_ENTERED
1 = NYET_PERIPH
22 RW 0x0
0 = DISABLE
1 = ENABLE
21 RW 0x0
be cleared to 0.
0 = DISABLE
1 = ENABLE
20 RW 0x0
be cleared to 0.
0 = DISABLE
1 = ENABLE
mode.
Value Specific Test.
19:16 RW 0x0
0000b Not enabled.
0001b J_ STATE.
0010b K_STATE.

USB Complex

0011b SEQ_NAK. 0100b Packet.
0101b FORCE_ENABLE.
0110b to 1111b Reserved.
Refer to Chapter 7 of the USB Specification Revision 2.0 for details on each test mode.
0 = NORMAL_OP
1 = TEST_J
2 = TEST_K
3 = TEST_SE0_NAK
4 = TEST_PKT
15:14 RO X
13 RO X
always be 0.
PPC PP Operation
12 RW 0x1
0 = NOT_POWERED
1 = POWERED
00b = SE0
10b = J-state
01b = K-state
11b = Undefined
of line state by the host controller driver is not necessary (unlike EHCI), because the port
mode, the use of line state by the device controller driver is not necessary.
0 = SE0
1 = K_STATE
2 = J_STATE
3 = UNDEFINED
Address (DA) is specified Controller will instigate L1 entry during suspend (bit 7) and L1 exit
during resume (bit 6). When set to zero the Controller will use the legacy (L2) mechanism.
9 RW 0x0 Software should only set this bit when the device attached immediately downstream supports L1
transitions. When acting as device, this bit is read-only and set to '1' by the hardware when the
Controller enters is L1 state (LPM token received and accepted). Note: HSP is redundant with
PSPD(27:26). This bit is not defined in the EHCI specification.
PR: This field is zero if Port Power (PP) is zero.

In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. When software writes a one
to this bit, the bus-reset sequence as defined in the USB Specification Revision 2.0 is started.
This bit will automatically change to zero after the reset sequence is complete. This behavior is
different from EHCI where the host controller driver is required to set this bit to a zero after the
8 RW 0x0
reset duration is timed in the driver.
In Device Mode: This bit is a read-only status bit. Device reset from the USB bus is also indicated
in the USBSTS register.
0 = NOT_USB_RESET
1 = USB_RESET

USB Complex
SUSP: Port suspend. 1=Port in suspend state. 0=Port not in suspend state.
In Host Mode: Read/Write. Port Enabled bit and Suspend bit of this register define the port states
as follows:
0x Disable
10 Enable
11 Suspend
When in the suspend state, downstream propagation of data is blocked on this port, except for
port reset. The blocking occurs at the end of the current transaction if a transaction was in
7 RO X
progress when this bit was written to 1. In the suspend state, the port is sensitive to resume
detection. Note that the bit status does not change until the port is suspended and that there may
be a delay in suspending a port if there is a transaction currently in progress on the USB. The
host controller will unconditionally set this bit to zero when software sets the Force Port Resume
bit to zero. A write of zero to this bit is ignored by the host controller. If host software sets this bit
to a one when the port is not enabled (i.e., Port enabled bit is a zero), the results are undefined.
This field is zero if Port Power (PP) is zero in host mode.
In Device Mode: Read Only. This bit is a read-only status bit.
0 = NOT_SUSPEND
1 = SUSPEND
In Device mode: After the device has been in Suspend State for 5 ms or more, software must set
0 = NO_RESUME
1 = RESUME

1 = CHANGE

1 = OVER_CURRENT
3 RW 0x0
In Device mode: The device port is always enabled. (This bit will be zero)
0 = NO_CHANGE
1 = CHANGE
PE: Port Enabled/Disabled: 1=Enable. 0=Disable (default)

2 RW 0x1 Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault
enabling a port due to other host controller and bus events. When the port is disabled, (0b)

USB Complex

0 = PORT_DISABLED
1 = PORT_ENABLED
CSC: Connect Status Change: 1 =Change in Current Connect Status. 0=No change (default)
1 RW 0x0
0 = NO_CHANGE
1 = CHANGE
CCS: Current Connect Status.

mode.
0 RO X In Device Mode: 1=Attached. 0=Not Attached (default). A one indicates that the device
0 = NOT_CONNECTED
1 = CONNECTED
19.13.4.30 USB2_CONTROLLER_1_USB2D_HOSTPC1_DEVLC_0

This register controls the LPM behavior and controls the behavior of each USB port. Only available when in device mode. This
register shares the same address with the HOSTPC1 register (which is used only in host mode).

This register controls the LPM behavior and controls the behavior of each USB port. Only available when in host mode. This
register shares the same address with the DEVLC register (which is used only in device mode).
0 = UTMI
31:29 RW 0x0 1 = RESERVED
2 = ULPI
3 = ICUSB_SER
28 RW 0x0
0 = PARALLEL_IF
1 = SERIAL_IF
1 = RESERVED

USB Complex
PSPD: This register field indicates the speed at which the port is operating.
00 = Full Speed
01 = Low Speed
10 = High Speed. This bit is not defined in the EHCI specification.
26:25 RO X
0 = FULL_SPEED
1 = LOW_SPEED
2 = HIGH_SPEED
3 = RESERVED
ALPD: Auto Low Power While Disconnect - RW. Default = 0b. If set, this feature will be enabled,
and every time the port enters the disconnect state, it will also enter in low power state, disabling
the transceiver clock. The behavior will be same as if the PHCD bit was enabled (in fact this bit
will be set to 1 as soon as low power mode is enabled).When this field is set the WKCN field of
PORTSCx register (Wake on Connect Enable) will also be set. This way the core will wake up in
the register USBMODE
23 RW 0x0
clock. Writing a 0 enables it. Reading this bit will indicate the status of the PHY clock. NOTE: The
PHY clock cannot be disabled if it is being used as the system clock. In device mode, the PHY
can be put into Low Power Clock Disable when the device is not running (USBCMD RS=0b) or
the host has signaled suspend (PORTSCx SUSP=1b). Low Power Clock Disable will be cleared
automatically when the host has signaled resume. Before forcing a resume from the device, the
22 RW 0x0
Controller driver must clear this bit. In host mode, the PHY can be put into Low Power Suspend
Clock Disable when the downstream device has been put into suspend mode or when no
downstream device is connected. Low Power Clock Disable is completely under the control of
software.
0 = DISABLE
1 = ENABLE
LPMX: Auto LPM set - RW. Default = 00b. This bit field is valid during Host Mode Only. For
Device Mode this is reserved.
Value Meaning
ASUS: Auto Low Power - RW. Default = 0b. This bit field is valid during Device Mode Only. In
Host Mode it is part of ELPM field. This bit is used to control the auto low power feature. If set, the
auto low power feature will be enabled and every time the port enters in suspend state it will also
17 RW 0x0 enter in low power state, disabling the transceiver clock. The behavior will be the same as if the
PHCD bit was enabled (in fact this bit will be set to '1' as soon as low power mode is enabled).
0 = DISABLE
1 = ENABLE
EPLPM: Endpoint for LPM token - RW. Default = 0000b. This bit field is valid during Host Mode
only. For Device Mode [19:18] is reserved and 17 is ASUS, while 16 is STL. This sets the
19:16 RW 0x0
endpoint number to which the LPM token will be sent. It will be directly mapped to the ENDP field
in the LPM token with the EXT PID.
STL: STALL reply to LPM token - RW. Default = 0b. This bit field is valid during Device Mode
16 RW 0x0 Only. In Host Mode it is a part of ELPM field. When this bit is set to '1', the Controller will reply
always with STALL to all incoming LPM tokens. This bit overrides the LPM NYET bit (NYT).

USB Complex

0 = DISABLE
1 = ENABLE
LPMFRM: Auto LPM SOF Threshold - RW. Default = 0000b. This bit field is valid during Host
Mode Only. For Device Mode this is reserved. This holds the SOF counter threshold. When the
15:12 RW 0x0 number of SOFs with no activity in between reaches this threshold and the auto LPM is enabled,
an LPM token is sent and the port enters the suspend state. The SOF counter for this threshold is
incremented each 125 µs, even if the port is not in HS operation.
BA: bmAttributes - RO. Default = 00000000000b. This holds the bmAttributes field of the LPM
11:1 RO X
sub-token received, after the EXT PID token.
NYT_ASUS: NYET reply to LPM token - RW. Default = 0b. This bit is NYT during Device Mode.
When this bit is '1', the device controller will NYET all the LPM tokens. When this bit is set to '0',
the Controller will ACK all the LPM tokens if the STALL bit (STL) is also set to '0'.
This bit is ASUS in Host Mode. This bit is used to control the auto low power feature. If set, the
0 RW 0x0 auto low power feature is enabled and every time the port enters the suspend state, it also enters
the low power state, disabling the transceiver clock. The behavior is the same as if the PHCD bit
was enabled (this bit is set to '1' as soon as low power mode is enabled).
0 = DISABLE
1 = ENABLE
19.13.4.31 USB2_CONTROLLER_1_USB2D_OTGSC_0

1 = ENABLE
interrupt.
29 RW 0x0
0 = DISABLE
1 = ENABLE
1 = ENABLE
1 = ENABLE
1 = ENABLE
1 = ENABLE
1 = ENABLE
bus pulsing is only detected when USBMODE.CM = Host (11) and PORTSC(0). PortPower = Off
22 RW 0x0 (0). Software writes a 1 to clear this bit.
0 = INT_CLEAR
1 = INT_SET
21 RW 0x0
0 = INT_CLEAR
1 = INT_SET

USB Complex
end threshold. Software writes a 1 to clear this bit.
20 RW 0x0
0 = INT_CLEAR
1 = INT_SET
19 RW 0x0
0 = INT_CLEAR
1 = INT_SET
18 RW 0x0
0 = INT_CLEAR
1 = INT_SET
17 RW 0x0
0 = INT_CLEAR
1 = INT_SET
16 RW 0x0
0 = INT_CLEAR
1 = INT_SET
1 = STS_SET
1 = STS_SET
1 = STS_SET
1 = STS_SET
1 = STS_SET
1 = STS_SET

8 RO X 0 = A_DEV
1 = B_DEV
IDPU: USB ID Pullup

5 RW 0x1 0 = CLEAR
1 = SET
SRP.
4 RW 0x0
0 = NO_DATA_PULSE
1 = DATA_PULSE
the pulldown on DM.
3 RW 0x0
0 = NO_OTG_TERM
1 = OTG_TERM
pulsing during SRP.
1 RW 0x0
0 = NO_VBUS_CHRG
1 = VBUS_CHRG

USB Complex
1 = VBUS_DISCHRG
19.13.4.32 USB2_CONTROLLER_1_USB2D_USBMODE_0

ALPDD: Auto Low Power While Disconnect Delay. Used when the ALPD field of the HOSTPCx
31:16 RW 0x0
65535*64*100/3 = 139,808 ms. The minimum value is 0. Only used in Host mode.
15 RW 0x0 SRT: Shorten USB Reset Time. Software should never set this to 1.
5 RW 0x0 power source (charge pump) and an off-chip source in systems when both are available. Only to
be used in Host Mode. Software should not use this.
SDIS: Stream disable: 1 Streaming is disabled - helpful to avoid overruns/underruns when system
load is too high.
4 RO X
0 = STREAM_ENABLE
1 = STREAM_DISABLE
mechanism. 0 - Setup lockout is ON (default) 1 Setup lockout is OFF. Firmware requires the use
3 RO X of setup tripwire semaphore in USB2D_USBCMD register.
0 = LOCKOUT_ON
1 = LOCKOUT_OFF
ES: Endian Select: Note: For this implementation, this should be always set to 0 (little endian).
1 = RESERVED
RESET bit in the USBCMD register before reprogramming this register. 00 = Idle [Default]. 01 =
1:0 RO X Reserved. 10 = Device Controller. 11 = Host Controller.
0 = IDLE
1 = RESERVED
2 = DEVICE_MODE
3 = HOST_MODE
19.13.4.33 USB2_CONTROLLER_1_USB2D_ENDPTNAK_0
USB2D Endpoint NAK register

31:16 0x0
0 = CLEAR
1 = SET
15:0 0x0
0 = CLEAR
1 = SET

USB Complex
19.13.4.34 USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0
USB2D Endpoint NAK Enable Register

31:16 0x0
0 = DISABLE
1 = ENABLE
15:0 0x0
0 = DISABLE
1 = ENABLE
19.13.4.35 USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0

0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
10 0x0 set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the

USB Complex

response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. This
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD

USB Complex
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
19.13.4.36 USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0

0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME

USB Complex
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME

USB Complex
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME

USB Complex
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME

USB Complex
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
19.13.4.37 USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0

31 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
30 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
29 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
28 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
27 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH

USB Complex
26 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
25 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
24 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
23 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
22 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
21 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
20 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
19 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
18 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
0 = DONT_FLUSH
1 = FLUSH

USB Complex
0 = DONT_FLUSH
1 = FLUSH
15 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
14 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
13 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
12 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
11 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
10 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
9 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
8 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
7 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH

USB Complex
6 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
5 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
4 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
3 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
2 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
1 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
0 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
19.13.4.38 USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0

31 X
0 = NOT_READY
1 = READY

USB Complex
30 X
0 = NOT_READY
1 = READY
29 X
0 = NOT_READY
1 = READY
28 X
0 = NOT_READY
1 = READY
27 X
0 = NOT_READY
1 = READY
26 X
0 = NOT_READY
1 = READY
25 X
0 = NOT_READY
1 = READY
24 X
0 = NOT_READY
1 = READY

USB Complex
23 X
0 = NOT_READY
1 = READY
22 X
0 = NOT_READY
1 = READY
21 X
0 = NOT_READY
1 = READY
20 X
0 = NOT_READY
1 = READY
19 X
0 = NOT_READY
1 = READY
18 X
0 = NOT_READY
1 = READY
17 X
0 = NOT_READY
1 = READY

USB Complex
16 X
0 = NOT_READY
1 = READY
15 X
0 = NOT_READY
1 = READY
14 X
0 = NOT_READY
1 = READY
13 X
0 = NOT_READY
1 = READY
12 X
0 = NOT_READY
1 = READY
11 X
0 = NOT_READY
1 = READY
10 X
0 = NOT_READY
1 = READY

USB Complex
9 X
0 = NOT_READY
1 = READY
8 X
0 = NOT_READY
1 = READY
7 X
0 = NOT_READY
1 = READY
6 X
0 = NOT_READY
1 = READY
5 X
0 = NOT_READY
1 = READY
4 X
0 = NOT_READY
1 = READY
3 X
0 = NOT_READY
1 = READY

USB Complex
2 X
0 = NOT_READY
1 = READY
1 X
0 = NOT_READY
1 = READY
0 X
0 = NOT_READY
1 = READY
19.13.4.39 USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0

31 0x0
0 = NOT_COMPLETE
1 = COMPLETE
30 0x0
0 = NOT_COMPLETE
1 = COMPLETE
29 0x0
0 = NOT_COMPLETE
1 = COMPLETE
28 0x0
0 = NOT_COMPLETE
1 = COMPLETE

USB Complex
27 0x0
0 = NOT_COMPLETE
1 = COMPLETE
26 0x0
0 = NOT_COMPLETE
1 = COMPLETE
25 0x0
0 = NOT_COMPLETE
1 = COMPLETE
24 0x0
0 = NOT_COMPLETE
1 = COMPLETE
23 0x0
0 = NOT_COMPLETE
1 = COMPLETE
22 0x0
0 = NOT_COMPLETE
1 = COMPLETE
21 0x0
0 = NOT_COMPLETE
1 = COMPLETE
20 0x0
0 = NOT_COMPLETE
1 = COMPLETE
19 0x0
0 = NOT_COMPLETE
1 = COMPLETE
18 0x0
0 = NOT_COMPLETE
1 = COMPLETE

USB Complex
17 0x0
0 = NOT_COMPLETE
1 = COMPLETE
16 0x0
0 = NOT_COMPLETE
1 = COMPLETE
15 0x0
0 = NOT_COMPLETE
1 = COMPLETE
14 0x0
0 = NOT_COMPLETE
1 = COMPLETE
13 0x0
0 = NOT_COMPLETE
1 = COMPLETE
12 0x0
0 = NOT_COMPLETE
1 = COMPLETE
11 0x0
0 = NOT_COMPLETE
1 = COMPLETE
10 0x0
0 = NOT_COMPLETE
1 = COMPLETE
9 0x0
0 = NOT_COMPLETE
1 = COMPLETE
8 0x0
0 = NOT_COMPLETE
1 = COMPLETE

USB Complex
7 0x0
0 = NOT_COMPLETE
1 = COMPLETE
6 0x0
0 = NOT_COMPLETE
1 = COMPLETE
5 0x0
0 = NOT_COMPLETE
1 = COMPLETE
4 0x0
0 = NOT_COMPLETE
1 = COMPLETE
3 0x0
0 = NOT_COMPLETE
1 = COMPLETE
2 0x0
0 = NOT_COMPLETE
1 = COMPLETE
1 0x0
0 = NOT_COMPLETE
1 = COMPLETE
0 0x0
0 = NOT_COMPLETE
1 = COMPLETE
19.13.4.40 USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0


23 X 0 = DISABLE
1 = ENABLE

USB Complex
TXT: TX Endpoint Type. Endpoint 0 is fixed as a Control Endpoint.

0 = CTRL
19:18 X 1 = ISO
2 = BULK
3 = INTR
0 = EP_OK
1 = EP_STALL

7 X 0 = DISABLE
1 = ENABLE

0 = CTRL
3:2 X 1 = ISO
2 = BULK
3 = INTR
0 = EP_OK
1 = EP_STALL
19.13.4.41 USB2_CONTROLLER_1_USB2D_ENDPTCTRLn_0

1 = ENABLE
22 RW 0x0 device.
0 = KEEP_GOING
1 = RESET_PID_SEQ
0 = DIS_PID_SEQ
1 = ENB_PID_SEQ
TXT: TX Endpoint Type: 00 = Control. 01 = Isochronous. 10 = Bulk. 11 = Interrupt.

0 = CTRL
19:18 RW 0x0 1 = ISO
2 = BULK
3 = INTR
16 RW 0x0 SETUP request if this Endpoint is configured as a Control Endpoint. Software can write a one to
this bit to force the endpoint to return a STALL handshake to the Host. It will continue to returning

USB Complex

0 = EP_OK
1 = EP_STALL
1 = ENABLE
6 RW 0x0 device.
0 = KEEP_GOING
1 = RESET_PID_SEQ
0 = DIS_PID_SEQ
1 = ENB_PID_SEQ

0 = CTRL
3:2 RW 0x0 1 = ISO
2 = BULK
3 = INTR
STALL until this bit is either cleared by software or automatically cleared as above,
0 = EP_OK
1 = EP_STALL

These are used to generate the actual RTL registers for USB2 controller interface.
ULPIS2S resets to be used as follows:
§ Assert ULPIS2S_SLV0_CLAMP_XMIT to ensure that the signals between SLV0 and the line simulator are clean.
§ Assert ULPIS2S_SLV0_RESET
§ Do a functional asynchronous reset of the ChipIdea controller
§ Deassert ULPIS2S_SLV0_RESET
§ Deassert ULPIS2S_SLV0_CLAMP_XMIT
NULPI_SLV1_RESET should be used in the same way if there is some explicit way to reset the external ULPI controller
(which is not necessarily the case). There is usually no reason to assert ULPIS2S_LINE_RESET.
This register controls the suspend and resume behavior of the USB controller/PHY.

Offset: 0x400 | Read/Write: R/W | Reset: 0bxxxxx00111110000x1001000xx000000
26 RW 0x0 from device. This is used only for cases where wakeup response needs to be within 1ms of spec.
Used for Host mode ONLY.
USB Complex

0 = DISABLE
1 = ENABLE
UTMIP_SUSPL1_SET: Enable SuspendL1 for UTMIP PHY Enabling this will only cutoff clocks to
the UTMIP logic. The USB PLLs, PllU and UTMIP PLL will still be running.
25 RW 0x0
0 = DISABLE
1 = ENABLE
ULPI_PADS_CLKEN_RESET: Async reset for the synchronizers that are used in the external
and loopback ULPI 60 MHz clock.
24 RW 0x1
0 = DISABLE
1 = ENABLE
ULPI_PADS_RESET: Async reset for trimmers and line state logic that is implemented in the pad
macros.
23 RW 0x1
0 = DISABLE
1 = ENABLE
ULPIS2S_LINE_RESET: Async reset of the line simulator logic that sits between the two virtual
PHYs (active high). The ULPI PHY registers should be programmed while ULPI is in reset.
22 RW 0x1
0 = DISABLE
1 = ENABLE
ULPIS2S_SLV1_RESET: Async reset of the SLV1 ULPI logic. This corresponds to resetting the
virtual PHY that is connected to the internal ULPI controller (active high). The ULPI PHY registers
21 RW 0x1 should be programmed while ULPI is in reset.
0 = DISABLE
1 = ENABLE
ULPIS2S_SLV0_RESET: Async reset of the SLV0 ULPI logic. This corresponds to resetting the
virtual PHY that is connected to the external ULPI controller. (active high). The ULPI PHY
20 RW 0x1 registers should be programmed while ULPI is in reset.
0 = DISABLE
1 = ENABLE
UHSIC_PHY_ENB: Enable UHSIC PHY mode. Set this to 1 if using UHSIC PHY. Otherwise set
this to 0.
19 RW 0x0
0 = DISABLE
1 = ENABLE
USB_WAKEUP_DEBOUNCE_COUNT: USB PHY wakeup debounce counter USB will debounce

18:16 RW 0x0 any wakeup event by the number of clocks programmed in this counter. A value of 0 results in no
debounce.
UHSIC_RESET: Reset going to UHSIC PHY (active high). This should be set to 1 whenever
programming the UHSIC config registers. It should be cleared to 0 after the programming of
UHSIC config registers is done. UHSIC config registers should be programmed only once before
14 RW 0x1 doing any transactions on UHSIC. The UHSIC PHY registers should be programmed while
UHSIC is in reset.
0 = DISABLE
1 = ENABLE
ULPI_PHY_ENB: Enable ULPI PHY mode. Set this to 1 if using null or link ULPI PHY. Otherwise
set this to 0.
13 RW 0x0
0 = DISABLE
1 = ENABLE
UTMIP_PHY_ENB: Enable UTMIP PHY mode Set this to 1 if using UTMIP PHY. Otherwise set
this to 0.
12 RW 0x0
0 = DISABLE
1 = ENABLE
11 RW 0x1 doing any transactions on UTMIP. The UTMIP PHY registers should be programmed while
UTMIP is in reset.
0 = DISABLE
1 = ENABLE
10 RW 0x0 USB_SUSP_POL: Polarity of the suspend signal going to UHSIC PHY.

USB Complex

0 = Active low (default)
1 = Active high.
This should not be changed by software.
0 = ACTIVE_LOW
1 = ACTIVE_HIGH
9 RW 0x0
0 = DISABLE
1 = ENABLE
USB PHY clock is woken up from suspend. Software must write a 1 to clear this bit.
8 RO 0x0
0 = UNSET
1 = SET
0 = UNSET
1 = SET
USB_CLKEN: USB AHB clock enable status. Indicates whether the AHB clock to the USB
set to 0. NOTE: even when this is set to 0, all essential blocks that are required to resume USB
6 RO X
0 = UNSET
1 = SET
USB_SUSP_CLR: Suspend Clear Software must write a 1 to this bit to bring the PHY out of
5 RW 0x0
0 = UNSET
1 = SET

enabled (1), USB device will wake up from suspend on a disconnect event. This is only valid
0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE
USB_WAKE_ON_RESUME_EN: Wake on resume enable. If this bit is enabled, the USB will
wake up from suspend whenever a resume event is detected on USB. This is valid for both USB
2 RW 0x0 device and USB host modes.
0 = DISABLE
1 = ENABLE

1 RW 0x0
0 = DISABLE
1 = ENABLE
USB_WAKEUP_INT_STS: USB wakeup interrupt status. This bit is set whenever the USB wakes
up from suspend (a wakeup event is generated). Software must write a 1 to clear this bit. Note
that during the wakeup sequence, PHY clocks will be resumed from suspend. Software can
check when the PHY clocks are resumed by reading the bit USB_PHY_CLK_VALID. There is
also a separate interrupt generated when PHY clock is resumed if
0 RO 0x0
USB_PHY_CLK_VALID_INT_EN is set. During the wakeup sequence, first
USB_WAKEUP_INT_STS will be set, and it will take some time for the PHY clock to resume,
which can be detected by checking USB_PHY_CLK_VALID.
0 = UNSET
1 = SET

USB Complex
§ A_VBUS_VLD
§ A_SESS_VLD
§ B_SESS_VLD
§ B_SESS_END

30 RW 0x0
0 = DISABLE
1 = ENABLE

0 = SEL_A
1 = SEL_B
A_VBUS_VLD_SW_VALUE: A_VBUS_VLD software value. Software should write the appropriate

28 RW 0x0 set.
0 = UNSET
1 = SET

0 = DISABLE
1 = ENABLE

is 1.
26 RO X
0 = UNSET
1 = SET

25 RO 0x0
0 = UNSET
1 = SET

USB Complex

24 RW 0x0
0 = DISABLE
1 = ENABLE
22 RW 0x0
0 = DISABLE
1 = ENABLE

0 = SEL_A
1 = SEL_B

20 RW 0x0 set.
0 = UNSET
1 = SET

A_SESS_VLD. Software sets this bit to drive the value in A_SESS_VLD_SW_VALUE to the USB
0 = DISABLE
1 = ENABLE

is 1.
18 RO X
0 = UNSET
1 = SET

change is detected in the value of A_SESS_VLD. software writes a 1 to clear it
17 RO 0x0
0 = UNSET
1 = SET

16 RW 0x0
0 = DISABLE
1 = ENABLE
14 RW 0x0
0 = DISABLE
1 = ENABLE

0 = SEL_A
1 = SEL_B

12 RW 0x0 set.
0 = UNSET
1 = SET

0 = DISABLE
1 = ENABLE

is 1.
10 RO X
0 = UNSET
1 = SET

USB Complex

9 RO 0x0
0 = UNSET
1 = SET

8 RW 0x0
0 = DISABLE
1 = ENABLE
6 RW 0x0
0 = DISABLE
1 = ENABLE

0 = SEL_A
1 = SEL_B

4 RW 0x0 set.
0 = UNSET
1 = SET
B_SESS_END_SW_EN: B_SESS_END software enable. Enable Software Controlled

B_SESS_END Software sets this bit to drive the value in B_SESS_END_SW_VALUE to the USB
0 = DISABLE
1 = ENABLE
B_SESS_END_STS: B_SESS_END status. This is set to 1 whenever B_SESS_END sensor output

is 1.
2 RO X
0 = UNSET
1 = SET

1 RO 0x0
0 = UNSET
1 = SET

0 RW 0x0
0 = DISABLE
1 = ENABLE
This register controls the battery charger (VDCD_DET, VDAT_DET), VBUS_WAKEUP and ID sensors. The following sensors
§ VBUS_WAKEUP
§ ID
§ VDAT_DET
§ VDCD_DET

USB Complex
There are debouncers for VDAT_DET and VDCD_DET. These use separate debouncers -CHRG_DEBOUNCE_PERIOD_A
For each sensor, we can select whether to use CHRG_DEBOUNCE_PERIOD_A or CHRG_DEBOUNCE_PERIOD_B by
setting the field _DEB_SEL_B to the appropriate value (SEL_A or SEL_B).

USB2 PHY VBUS Wakeup and ID Control Register

1 = ENABLE

30 RW 0x0
0 = DISABLE
1 = ENABLE
0 = SEL_A
1 = SEL_B
28 RW 0x0
0 = UNSET
1 = SET

27 RW 0x0
0 = DISABLE
1 = ENABLE

26 RO X 0 = UNSET
1 = SET

change is detected in the value of VDCD_DET. software writes a 1 to clear it
25 RO 0x0
0 = UNSET
1 = SET

24 RW 0x0
0 = DISABLE
1 = ENABLE
23 RO X VOP_DIV2P7_DET:This read-only status bit from battery charging divider circuit of USB2OTG pad
0 = UNSET
USB Complex

1 = SET
VOP_DIV2P0_DET:This read-only status bit from battery charging divider circuit of USB2OTG pad
22 RO X 0 = UNSET
1 = SET
0 = SEL_A
1 = SEL_B
20 RW 0x0
0 = UNSET
1 = SET
VDAT_DET_SW_EN: VDAT_DET software enable. Enable Software Controlled VDAT_DET.

Software sets this bit to drive the value in VDAT_DET_SW_VALUE to the USB controller
19 RW 0x0
0 = DISABLE
1 = ENABLE
VDAT_DET_STS: VDAT_DET status. This is set to 1 whenever the VDAT_DET sensor output is 1.
18 RO X 0 = UNSET
1 = SET

change is detected in the value of VDAT_DET. software writes a 1 to clear it
17 RO 0x0
0 = UNSET
1 = SET

16 RW 0x0
0 = DISABLE
1 = ENABLE
VON_DIV2P7_DET:This read-only status bit from battery charging divider circuit of USB2OTG pad
15 RO X 0 = UNSET
1 = SET
VON_DIV2P0_DET:This read-only status bit from battery charging divider circuit of USB2OTG pad
14 RO X 0 = UNSET
1 = SET

0 = SEL_A
1 = SEL_B

0 = UNSET
1 = SET
VBUS_WAKEUP_SW_EN: VBUS wakeup software enable. Enable Software Controlled

VBUS_WAKEUP. Software sets this bit to drive the value in VBUS_WAKEUP_SW_VALUE to the
11 RW 0x0 USB controller.
0 = DISABLE
1 = ENABLE

output is 1.
10 RO X
0 = UNSET
1 = SET
a change is detected in the value of VBUS_WAKEUP. software writes a 1 to clear it
9 RO 0x0
0 = UNSET
1 = SET

USB Complex

8 RW 0x0
0 = DISABLE
1 = ENABLE

7 RO X 0 = UNSET
1 = SET

1 = ENABLE
0 = SEL_A
1 = SEL_B
4 RW 0x0
0 = UNSET
1 = SET
ID_SW_EN: ID software enable. Enable Software Controlled ID. Software sets this bit to drive the
value in ID_SW_VALUE to the USB controller
3 RW 0x0
0 = DISABLE
1 = ENABLE

2 RO X 0 = UNSET
1 = SET
1 RO 0x0
0 = UNSET
1 = SET

0 RW 0x0
0 = DISABLE
1 = ENABLE
USB PHY Alternate VBUS Status Register


8 X 0 = UNSET
1 = SET

7 X 0 = UNSET
1 = SET

6 X 0 = UNSET
1 = SET

5 X 0 = UNSET
1 = SET
4 X ID_DIG_ALT: ID alternate status

0 = UNSET

USB Complex

1 = SET

3 X 0 = UNSET
1 = SET

2 X 0 = UNSET
1 = SET

1 X 0 = UNSET
1 = SET

0 X 0 = UNSET
1 = SET
19.13.5.5 USB2_IF_USB_ULPIS2S_CTRL_0
This register is used to set up parameters for ULPI null PHY mode.
Note: Current ULPI configuration registers use settings that support NV software drivers and should NOT be
ULPI NULL PHY Control Register

Offset: 0x418 | Read/Write: R/W | Reset: 0bxxxxxxxx0000xx0000000000xxxx0000
ULPIS2S_CLAMP_LINE_DRIVE: The line drive value that should be sent into the line simulator during
23:20 0x0
transmit clamping. The suggested value is 0x1: tri-state.
ULPIS2S_SLV1_CLAMP_XMIT: When set to 1, the outputs of the SLV1 transmit state machine are
17 0x0 clamped to 0. This bit should be set before the SLV0 async reset is asserted to prevent meta-stability
issues in the line simulator.
ULPIS2S_SLV0_CLAMP_XMIT: When set to 1, the outputs of the SLV0 transmit state machine are
16 0x0 clamped to 0. This bit should be set before the SLV0 async reset is asserted to prevent meta-stability
issues in the line simulator.
ULPIS2S_DISABLE_STP_PU: When set to 1 and in ULPIS2S mode, the pullup on the STP pin will
15 0x0 NOT be active, even if the remote LINK asks to do so. In this case, an external pullup resistor would be
required to ensure valid levels when the remote link is not powered.
ULPIS2S_SUPPORT_HS_KEEP_ALIVE: When enabled, the PHY will support HS KeepAlive packets.

In that case, this would be the only thing that is supported in Opmode3. All other Opmode3 generate
14 0x0 packets are not supported under any circumstances.
0 = DISABLE
1 = ENABLE
ULPIS2S_DISCON_DONT_CHECK_SE0: When enabled, the disconnect detection logic will only check
that that the other side is 'driving' tri-state. It will not check whether or not the local side is driving SE0.
13 0x0
0 = DISABLE
1 = ENABLE
ULPIS2S_FORCE_ULPI_CLK_OUT: When enabled and ULPIS2S_ENA is ENABLED, the external

ULPI_CLOCK pad will always carry the internal 60MHz clock, even if the interface is in shutdown mode.
12 0x0
0 = DISABLE
1 = ENABLE
11:8 0x0 ULPIS2S_SPARE: Reserved bits.
ULPIS2S_PLLU_MASTER_BLASTER60: When enabled, the PLLU 60MHz clock will be forced on.
3 0x0 0 = DISABLE
1 = ENABLE
2 0x0 ULPIS2S_SUPPORT_DISCONNECT: When disabled, the PHY will never detect a Disconnect.

USB Complex

0 = DISABLE
1 = ENABLE
ULPIS2S_SLV1_FORCE_DEVICE: When disabled, the slave port that is connected to the pins can be
programmed to be host or a device depending on the value of the DpPulldown and DmPulldown bits in
the OTG_CTRL ULPI register. When enabled, the values of those bits in the OTG_CTRL register is
1 0x0
ignored and the port will always behave like a device.
0 = DISABLE
1 = ENABLE
ULPIS2S_ENA: When enabled, the ULPI link interface coming out of the USB2 controller enters a NULL
PHY with two slaves. As a result the external pins will have a slave ULPI interface. When disabled, the
0 0x0 ULPI link interface coming out of the USB2 controller go straight to the pins.
0 = DISABLE
1 = ENABLE
19.13.5.6 USB2_IF_USB_ULPIS2S_SLV1_ID_0
This register controls the product and vendor ID fields for ULPI null PHY presented to external ULPI master.
Note: Current ULPI configuration registers use settings that support NV software drivers and should NOT be
31:16 0x0 ULPIS2S_SLV1_VENDOR_ID: PHY vendor_id as seen by the external ULPI master
15:0 0x0 ULPIS2S_SLV1_PRODUCT_ID: PHY product_id as seen by the external ULPI master

This register controls the interpacket delay between two consecutive transmit packets in HS mode. This only applies to host
mode as device never transmits two packets in a row.
IP_DELAY_TX2TX_HS: HS Tx to Tx inter-packet delay. This is valid only for UHSIC PHY. Software
6:0 0x12
should not change this.
USB Controller Resume Signalling Delay

15:0 0x6978
For ICUSB PADCTLS

Spare Register

USB Complex

31:16 0xffff SPARE_HI[0] - usb_port_reset_fix_en. Enable port-reset fix
SPARE_HI[1] - hsic_conn_det_feature_enable. Enable HSIC connect detection

15:0 0x0 SPARE_LO[4] - usb_hs_rsm_eop_fix_en. Enable HS_RESUME EOP fix
SPARE_LO[5] - usb_port_suspend_fix_en
19.13.5.10 USB2_IF_ULPI_DIR_OVERRIDE_0
ULPI Override
ULPI_DIR_OVERRIDE: By default, this bit is set. This will override ulpi_dir; i.e., when this bit is set,
0 0x1
ulpi_dir is always asserted. Software needs to explicitly clear this bit, once slv1 Lp0 context is restored.

15:8 0xf REQUEST_EXPIRY_COUNTER: Time to wait for coalescing the request.
1 0x0
0 = DISABLE
1 = ENABLE

0 0x0 0 = DISABLE
1 = ENABLE

19.13.6.1 UTMIP REGISTER: PLL_CFG0

This register was used to configure PLL inside UTMIP block prior to Tegra K1 devices. This has been de-featured from UTMIP
space and moved to CAR space. This register is used to configure the PHY PLL contained in the UTMIP module. Refer to the
Clock and Reset Controller section for details on this register.

USB Complex
This register was used to configure the PLL inside the UTMIP block prior to Tegra K1 devices. This register has been
defeatured from UTMIP space and moved to CAR space. Refer to the Clock and Reset Controller section for details on this
register.

21 0x1 UTMIP_XCVR_LSBIAS_SEL: Low speed bias selection method for USB transceiver pad
20 0x0 UTMIP_XCVR_DISCON_METHOD: Disconnect method on the USB transceiver pad

18 0x1

16 0x1
FORCE_PD2_POWERUP.)

14 0x1
FORCE_PD_POWERUP.)

29 0x0 UTMIP_IDDIG_C_SEL:
0: IdDig_c = IdDig_c.

USB Complex

1: IdDig_c = IDDIG_C_VAL.
27 0x0 UTMIP_IDDIG_B_SEL:
0: IdDig_b = IdDig_b.
1: IdDig_b = IDDIG_B_VAL.
25 0x0 UTMIP_IDDIG_A_SEL:
0: IdDig_a = IdDig_a.
1: IdDig_a = IDDIG_A_VAL.
UTMIP_IDDIG_SEL:
20 0x0 0: IdDig = IdDig.
1: IdDig = IDDIG_VAL.
UTMIP_GPI_SEL:
18 0x0 0: StaticGpi = IdDig.
1: StaticGpi = GPI_VAL.
14:12 0x0 UTMIP_ACTIVE_PULLUP_OFFSET: Active 1.5K pullup control offset.


USB Complex
7 0x0 UTMIP_PASS_CHIRP: When in Chirp Mode, allow chirp RX data through


13:8 0x4 UTMIP_FSLS_IDLE_WAIT_MAX: 4 bits of SEO should exceed the time limit

USB Complex

10:5 0x20 UTMIP_LS_SE0_COUNT: Only for this number of 60MHz of SEO and Idle to end packet
UTMIP_FS_EOP_LENGTH: Whether full speed EOP is determined within 3 or 4 60MHz cycles

0 0x0 0: 3 60 MHz cycles
1: 4 60 MHz cycles

8 0x0 UTMIP_HS_DISCON_DISABLE: Disable high speed disconnect
6 0x0 UTMIP_HS_PREAMBLE_OUTPUT_ENABLE: Output enable turns on 1 cycle before
5 0x0 UTMIP_SIE_RESUME_ON_LINESTATE: SIE, not macrocell, detects LineState change to resume

4 0x0
packets

USB Complex

22 0x1 UTMIP_SUSPEND_EXIT_ON_EDGE: Suspend exit requires edge or simply a value.
21 0x1
happen)

0 = DISABLE
20:19 0x0 1 = BIT_ERR
2 = RX_ERR
3 = BIT_RX_ERR
15 0x0 UTMIP_DISABLE_PULLUP_DP: Force DP pullup inactive. (Overrides FORCE_PULLUP_DP.)
14 0x0 UTMIP_DISABLE_PULLUP_DM: Force DM pullup inactive. (Overrides FORCE_PULLUP_DM.)
13 0x0 UTMIP_DISABLE_PULLDN_DP: Force DP pulldown inactive. (Overrides FORCE_PULLDN_DP.)
12 0x0 UTMIP_DISABLE_PULLDN_DM: Force DM pulldown inactive. (Overrides FORCE_PULLDN_DM.)
11 0x0 UTMIP_FORCE_PULLUP_DP: Force DP pullup active.
10 0x0 UTMIP_FORCE_PULLUP_DM: Force DM pullup active.
9 0x0 UTMIP_FORCE_PULLDN_DP: Force DP pulldown active.
8 0x0 UTMIP_FORCE_PULLDN_DM: Force DM pulldown active.
3 0x1 UTMIP_NO_FREE_ON_SUSPEND: Do not use free running terminations during suspend.


USB Complex
29 0x0 UTMIP_LINESTATE_BYPASS: Bypass LineState reclocking logic
UTMIP_LINESTATE_XCVRSEL3:
27 0x0 0: Use FS filtering on line state when XcvrSel=3
1: Use LS filtering on line state when XcvrSel=3
22:18 0x6 UTMIP_PLL_ACTIVE_DLY_COUNT: Reserved. Config moved to the Clock and Reset space.
17:6 0x600 UTMIP_PLLU_STABLE_COUNT: Reserved. Moved to the Clock and Reset space.
UTMIP_XCVRSEL3:
Bit 0:
0: 0xa5 -> treat as KeepAlive
1:0 0x0 1: treat as regular packet
Bit 1:
0: Turn on FS EOP detection
1: Turn off FS EOP detection

Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and SessEnd. Each of these signals has its own debouncer.
For each of those, one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or BIAS_DEBOUNCE_B.)
ms = *1000 / (1/19.2MHz) / 4
So to program a 1 ms debounce for BIAS_DEBOUNCE_A:
BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0


USB Complex

13:8 0x0
0 0x1 UTMIP_PD_CHRG: Power-down charger circuit


31:0 -65288 1: HS_RX_FLUSH_ALAP. Flush as late as possible
31 to 3: Reserved

27:26 0x0 UTMIP_XCVR_RPU_RANGE_ADJ: 1.5k pull-up resistor range shift.
25:24 0x0 UTMIP_XCVR_HS_IREF_CAP: High-speed Iref cap control for bias current stability.
17 0x0 UTMIP_RCTRL_SW_SET: Use a software override on RCTRL instead of automatic bias control.

16:12 0x8
only.

10:6 0x8
only.

4 0x1

2 0x1
0 0x1 UTMIP_FORCE_PDDISC_POWERDOWN: Force PDDISC input into power down. (Overrides

USB Complex


UTMIP_BIAS_DEBOUNCE_TIMESCALE: Debouncer time scaling. Slows down debouncing by a factor-

13:8 0x0
1. So 0 is 1, 1 is 2, etc.
7:3 0x5
2 0x1 UTMIP_VBUS_WAKEUP_POWERDOWN: Reserved. See the PMC registers for this functionality.

0 0x1

UTMIP VDcd_Det and VDat_Det Debounce

Debounce values VDcd_Det and VDat_Det. Each of these signals has its own debouncer. For each of those, 1 out of 2
ms = *1000 / (1/19.2MHz) / 4
So to program a 1 ms debounce for CHG_DEBOUNCE_PERIOD:
CHG_DEBOUNCE_PERIOD[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0
31:16 0xffff UTMIP_CHRG_DEBOUNCE_PERIOD_B: simulation value -- Used for interrupts
15:0 0xffff UTMIP_CHRG_DEBOUNCE_PERIOD_A: simulation value -- Used for interrupts

USB Complex

20:0 X UTMIP_SPARE_FUSES: Spare fuses value to keep the connections preserved
UTMIP PMC Wakeup value

19.13.7 UHSIC Configuration Registers

Note: Current HSIC configuration registers use settings that support NV software drivers and should NOT be
19.13.7.1 USB2_UHSIC_MISC_STS0_0
UHSIC SPARE Fuse Value

Offset: 0xc30 | Read/Write: RO | Reset: 0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
0 X UHSIC_TX_HS_VLD: Indicates when the controller is driving on the bus
19.13.7.2 USB2_UHSIC_PMC_WAKEUP0_0
UHSIC PMC Wakeup Value

Offset: 0xc34 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0
1 RO X UHSIC_LINE_WAKEUP_EVENT_INT_STS: Indicates the status of the PMC wakeup event
0 RW 0x0 UHSIC_LINE_WAKEUP_EVENT_INT_ENB: Interrupt mask for the PMC wakeup event


USB Complex
USB2D_QH: Queue Head for OUT endpoint n. This is used to store a local Queue Head data structure
31:0 0x0
for either device mode or host mode. In device mode, it holds the Queue Head for OUT endpoint n.
There are 16 USB2D Queue Head for IN Endpoint registers, where n = 0 through 15.
USB2D Queue Head for IN Endpoint n

31:0 0x0
19.13.8 USB3 Controller Registers
19.13.8.1 USB2_CONTROLLER_2_USB2D_ID_0

19.13.8.2 USB2_CONTROLLER_2_USB2D_HW_HOST_0

19.13.8.3 USB2_CONTROLLER_2_USB2D_HW_DEVICE_0

5:1 X

USB Complex
19.13.8.4 USB2_CONTROLLER_2_USB2D_HW_TXBUF_0

23:16 X
15:8 X
7:0 X
19.13.8.5 USB2_CONTROLLER_2_USB2D_HW_RXBUF_0

15:8 X
depth of the receive buffer is 128 words.
7:0 X
23:0 0x0
31 RW 0x0
24 RW 0x0

USB Complex
23:0 0x0
31 RW 0x0
24 RW 0x0
19.13.8.10 USB2_CONTROLLER_2_USB2D_CAPLENGTH_0

7:0 X
19.13.8.11 USB2_CONTROLLER_2_USB2D_HCIVERSON_0

19.13.8.12 USB2_CONTROLLER_2_USB2D_HCSPARAMS_0

23:20 X N_PTT: Number of Ports per Transaction Translator: Indicates the number of ports assigned to each

USB Complex

transaction translator within the USB2.0 host controller. Field always equals N_PORTS. This is a non-
15:12 X
set to 0.
11:8 X
4 X control. 1 = Ports have port power switches 0= Ports do not have port power switches. This field affects
the functionality of the port Power field in each port status and control register. This field is set to 1.
3:0 X
19.13.8.13 USB2_CONTROLLER_2_USB2D_HCCPARAMS_0

PPC: Per-Port Change Event Capability - RO. Default = 1b. This field indicates the support for per-port
18 X change events. This field is related to the USBCMD PPE field, USBSTS PPCI field, and USBINTR PPCE
field.
17 X state. This field is related to the USBCMD HIRD field, POSTSCx SSTS and DA fields, and HOSTPCx
LEN, BA, and EPLPM fields.
15:8 X
7:4 X
2 X
PFL: Programmable Frame List Flag.

0 = System software must use a frame list length of 1024 elements with this host controller. The
USBCMD register Frame List Size field is a read-only register and must be set to zero.
1 X 1 = System software can specify and use a smaller frame list and configure the host controller via the
USBCMD register Frame List Size field.
The frame list must always be aligned on a 4K-page boundary. This requirement ensures that the frame
list is always physically contiguous. This field will always be "1".
19.13.8.14 USB2_CONTROLLER_2_USB2D_DCIVERSION_0

15:0 X

USB Complex
19.13.8.15 USB2_CONTROLLER_2_USB2D_DCCPARAMS_0

HC: Host Capable:

8 X 1 = This controller is capable of operating as an EHCI compatible USB 2.0 host controller. This field is set
to 1.
DC: Device Capable:

7 X
1 = Controller is capable of operating as USB 2.0 device. This field is set to 1.
5 X
state. This field is related to the DEVLCx ASUS, STL, BA, and NYT fields.
19.13.8.16 USB2_CONTROLLER_2_USB2D_EXTSTS_0

4 RW 0x0
3 RW 0x0
2 RW 0x0
0 = DISABLE
1 = ENABLE
1 RW 0x0
0 = DISABLE
1 = ENABLE
0 RO X
bits are cleared.
0 = DISABLE
1 = ENABLE
19.13.8.17 USB2_CONTROLLER_2_USB2D_USBEXTINTR_0


USB Complex
UPIE: UPIE Interrupt Enable. 1 = USB controller issues an interrupt if UPA bit in USBSTS register
transitions.
2 0x0
0 = DISABLE
1 = ENABLE
UAIE: UAIE Interrupt Enable. 1 = USB controller issues an interrupt if UAI bit in USBSTS register
transitions.
1 0x0
0 = DISABLE
1 = ENABLE
NAKE: NAK Interrupt Enable. 1 = USB controller issues an interrupt if NAKI bit in USBSTS register
transitions.
0 0x0
0 = DISABLE
1 = ENABLE
19.13.8.18 USB2_CONTROLLER_2_USB2D_USBCMD_0

27:24 RW 0x0
LPM Token, specifically: a value 0000b equals 50 µs and each additional increment adds 75 µs.
For example, the value 0001b equals 125 µs, and a value 1111b equals 1,175 µs (~1.2ms).
maximum interrupt interval measured in micro-frames. Valid values are shown below.
Value Maximum Interrupt Interval
00h = Immediate (no threshold)
01h = 1 micro-frame
02h = 2 micro-frames
23:16 RW 0x8 10h = 16 micro-frames
0 = IMMEDIATE
2 = ONE_MF
4 = TWO_MF
8 = EIGHT_MF
16 = SIXTEEN_MF
32 = THIRTY_TWO_MF
64 = SIXTY_FOUR_MF

USB Complex
ATDTW: Add DTD Tripwire. This bit is used as a semaphore when a dTD is added to an active
0 = CLEAR
1 = SET
setup data arrives and firmware is copying setup data from the QH for a previous setup packet.
13 RW 0x0
This bit is set and cleared by software and will be cleared by hardware when a hazard exists.
0 = CLEAR
1 = SET
0 = DISABLE
1 = ENABLE

3h and is R/W. Otherwise it defaults to zero and is RO. It contains a count of the number of
9:8 RW 0x3 successive transactions the host controller is allowed to execute from a high-speed queue head
on the Asynchronous schedule before continuing traversal of the Asynchronous schedule.
Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a
one as this will result in undefined behavior. This field is set to 3h in this implementation.
LR: Light Host/Device Controller Reset (OPTIONAL). Not Implemented. This field will always be
7 RO X
"0".
6 RW 0x0 Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so
will yield undefined results.
This bit is only used in Host mode. Writing a one to this bit when device mode is selected will
have undefined results.
0 = CLEAR
1 = SET
processing the Asynchronous Schedule.
0 = Do not process the Asynchronous Schedule.
5 RW 0x0 1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
Only the host controller uses this bit.
0 = DISABLE
1 = ENABLE
Periodic Schedule.
0 = Do not process the Periodic Schedule
4 RW 0x0 1 = Use the PERIODICLISTBASE register to access the Periodic Schedule. Only the host
0 = DISABLE
1 = ENABLE
FS1_FS0: Frame List Size 000 = Default. This field is Read/Write only if Programmable Frame
List Flag in the HCCPARAMS registers is set to one. Hence this field is Read/Write for this
implementation. This field specifies the size of the frame list that controls which bits in the Frame
Index Register should be used for the Frame List Current index.
3:2 RW 0x0 Note that this field is made up from USBCMD bits 15, 3, and 2.

USB Complex

process early by writing a zero to this register. Host Controller: When software writes a one to this
bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their
initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset
is not driven on downstream ports. Software should not set this bit to a one when the HCHalted
1 RW 0x0 bit in the USBSTS register is a zero. Attempting to reset an actively running host controller results
in undefined behavior. Device Controller: When software writes a one to this bit, the Device
Controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value.
Any transaction currently in progress on USB is immediately terminated. Writing a one to this bit
in device mode is not recommended.
0 = CLEAR
1 = SET
transaction and has entered the stopped state. Software should not write a one to this field unless
the host controller is in the Halted state (i.e., HCHalted in the USBSTS register is a one). Device
0 RW 0x0 Controller: Writing a one to this bit will cause the device controller to enable a pull-up on D+ and
initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-
up will become disabled upon transitioning into high-speed mode. Software should use this bit to
prevent an attach event before the device controller has been properly initialized. Writing a 0 to
this will cause a detach event.
0 = STOP
1 = RUN
19.13.8.19 USB2_CONTROLLER_2_USB2D_USBSTS_0

AS: Asynchronous Schedule Status. This bit reports the current real status of the Asynchronous
USBCMD register.
15 RW 0x0 If AS = ASE:
1= Enable Asynchronous Schedule
0= Disable Asynchronous Schedule
0 = DISABLE
1 = ENABLE
PS: Periodic Schedule Status. This bit reports the current real status of the Periodic Schedule.
When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The
Host Controller is not required to immediately disable or enable the Periodic Schedule when
14 RW 0x0 software transitions the Periodic Schedule Enable bit in the USBCMD register.
If PS = PSE:
1 = Periodic Schedule is enabled

USB Complex

0 = Periodic Schedule is disabled
0 = DISABLE
1 = ENABLE
13 RO X
0 = DISABLE
1 = ENABLE
12 RW 0x1
host controller.
0 = UNHALTED
1 = HALTED
11 RW 0x0 UALT_INT: ULPI alt_int Interrupt. 0 = Default. This interrupt bit is set when an RXCMD is
received through the ULPI interface with bit 7 set (alt_int). The alt_int itself is set when an
unmasked event occurs on any bit in the Carkit Interrupt Latch Register, in the ULPI PHY. The
Viewport to check the source of the interrupt. Only present in designs where configuration
1 = ULPI_ALT_INT
10 RW 0x0
0 = NOT_ULPI_INT
1 = ULPI_INT
0 = NOTSUSPEND
1 = SUSPENDED
indicate that an SOF was expected. Therefore, this bit will be set roughly every 1ms in device FS
Since device controller is initialized to FS before connect, this bit will be set at an interval of 1ms
7 RW 0x0
during the prelude to the connect and chirp. In host mode, this bit will be set every 125 µs and
can be used by host controller driver as a time base. Software writes a 1 to this bit to clear it. This
is a non-EHCI status bit.
0 = SOF_NOT_RCVD
1 = SOF_RCVD
0 = NO_USB_RESET
1 = USB_RESET
5 RW 0x0
indicates the assertion of that interrupt source. Only used by the host controller
0 = NOT_ADVANCED
1 = ADVANCED
4 RO X 0 = NO_ERROR
1 = ERROR
3 RW 0x0 frame list size. For example. If the frame list size (as programmed in the Frame List Size field of

USB Complex

0 = NO_ROLLOVER
1 = ROLLOVER
mechanisms are the USB Reset Received bit and the DCSuspend bits respectively. This bit is not
EHCI compatible.
0 = NO_PORT_CHANGE
1 = PORT_CHANGE
1 RW 0x0 on which the error interrupt occurred also ad its interrupt on complete (IOC) bit set.
0 = NO_ERROR
1 = ERROR
bytes.
0 = NO_INT
1 = INT
19.13.8.20 USB2_CONTROLLER_2_USB2D_USBINTR_0

31:16 0x0
UALTIE: ULPI alt_int Interrupt Enable. 1 = USB controller issues an interrupt if ULPI_ALT_INT bit in
USBSTS register transitions. The interrupt is acknowledged by software by writing a 1 to the
0 = DISABLE
1 = ENABLE
10 0x0
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
7 0x0
0 = DISABLE
1 = ENABLE
6 0x0 register = 1. The interrupt is acknowledged by software clearing the USB Reset Received bit. Only used
by the device controller.

USB Complex

0 = DISABLE
1 = ENABLE
AAE: Interrupt on Asynchronous Advance Enable. 1 = the host controller issues an interrupt at the next
interrupt threshold if Interrupt on Async Advance bit in USBSTS register = 1. The interrupt is
0 = DISABLE
1 = ENABLE
SEE: System Error Enable. 1 = Host/device controller issues an interrupt if the System Error bit in
4 0x0
0 = DISABLE
1 = ENABLE
FRE: Frame List Rollover Enable. 1 = Host controller issues an interrupt if Frame List Rollover bit in the
USBSTS register = 1. The interrupt is acknowledged by software clearing the Frame List Rollover bit.
3 0x0 Only used by the host controller.
0 = DISABLE
1 = ENABLE
2 0x0 bit.
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 0x0
0 = DISABLE
1 = ENABLE
19.13.8.21 USB2_CONTROLLER_2_USB2D_FRINDEX_0

based on the value of the Frame List Size field in the USBCMD register, when used in host mode.
USBCMD [Frame List Size] Number Elements N
000b (1024) 12
001b (512) 11
13:0 X 010b (256) 10
011b (128) 9
100b (64) 8
101b (32) 7
110b (16) 6
111b (8) 5
index. In either mode, bits 2:0 indicate the current micro-frame.

USB Complex
19.13.8.22 USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0

31:25 0x0
device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with
USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement.
the system memory. HCD loads this register prior to starting the schedule execution by the Host
31:12 0x0
19.13.8.23 USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0

reference a list of up to 32 Queue Heads (QH). Only used by the device controller.
19.13.8.24 USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0

TTHA: Internal TT Hub Address representation. This field is used to match the Hub Address field
in QH and siTD to determine if the packet is routed to the internal TT for directly attached FS/LS
30:24 RW 0x0 devices.If the Hub Address in the QH or siTD does not match this address then the packet will be
broadcast on the High Speed ports destined a downstream High Speed hub with the address in
QH/siTD.
1 RW 0x0 TTAC: Embedded TT Async Buffers Clear. (Read/Write to set). This field will clear all pending

USB Complex

TTAS: Embedded TT Async Buffers Status. (Read Only). This read only bit will be 1 if one or
19.13.8.25 USB2_CONTROLLER_2_USB2D_BURSTSIZE_0
USB2D Burst Size Register

15:8 0x8
7:0 0x8
19.13.8.26 USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0

that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The
minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher
21:16 0x2 value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO
is set.
TXSCHHEALTH: Scheduler Health Counter. (Read/Write To Clear) [Default = 0]. This register
TXSCHOH: Scheduler Overhead. (Read/Write) [Default = 0]. This register adds an additional fixed
offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for
this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10
7:0 0x0 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it
can needlessly reduce USB utilization. The time unit represented in this register is 1.267 µs when a
device is connected in High-Speed Mode. The time unit represented in this register is 6.333 µs when a
device is connected in Low/Full Speed Mode.

USB Complex
19.13.8.27 USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0
USB2D ICUSB Control Register

bits PTS must be set to 11 in the PORTSCx. Writing a '1' to this bit selects the IC_USB interface.
3 0x0
0 = DISABLE
1 = ENABLE
000 = No voltage
001 = 1.0V – reserved
2:0 0x0 100 = 1.8V
101 = 3.0V
110 = reserved
111 = reserved
The Voltage negotiation should happen between enabling port power (PP) and asserting the run/stop bit in
register.
19.13.8.28 USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0

Note: EXECUTING READ OPERATIONS THROUGH THE ULPI VIEWPORT SHOULD HAVE NO HARMFUL
SIDE EFFECTS TO STANDARD USB OPERATIONS.
There are two operations that can be performed with the ULPI Viewport: wakeup and read /write operations.
The wakeup operation is used to put the ULPI interface into normal operation mode and re-enable the clock, if necessary. A
mode, or Carkit mode.
To execute a wakeup operation, write all 32 bits of the ULPI Viewport where ULPI_PORT is constructed appropriately and the
complete.
was a read.
USB Complex
Control register.
Refer to the ULPI Specification Revision 1.1 for further information on the use of the optional features.
31 RW 0x0
at the same time.
0 = CLEAR
1 = SET
30 RW 0x0
at the same time.
0 = CLEAR
1 = SET
29 RW 0x0
0 = READ
1 = WRITE
ULPI_SYNC_STATE: ULPI sync state. (1) Normal Sync. State. (0) In another state (i.e., Carkit,
27 RO X
0 = NOT_NORMAL
1 = NORMAL
23:16 RW 0x0
15:8 RO X
ULPI_DATA_WR: ULPI PHY data write. The data to write to the ULPI PHY register is written
7:0 RW 0x0
here.
19.13.8.29 USB2_CONTROLLER_2_USB2D_PORTSC1_0

DA: Device Address. Default = 0000000b. The 7-bit USB device address for the device attached
to an immediately downstream of the associated root port. A value of zero indicates no device is
present or software support for this feature is not present. This is used by the Controller when
31:25 RW 0x0 sending the LPM token.
This field is only valid when the core is operating in host mode. If in device mode, it will be read
only and always equal to 0000000b.

USB Complex
SSTS: Suspend Status. Default = 00b. These two bits are used by software to determine whether
an L1-based suspend request was successful, specifically:
24:23 RO X these bits is invalid whenever bit 7 of this register (SUSP) is one. Ideally, the Controller driver
possible L1 failure. This field is only valid when the core is operating in host mode. If in device
mode it will be always equal to 00b.
0 = L1STATE_ENTERED
1 = NYET_PERIPH
22 RW 0x0
0 = DISABLE
1 = ENABLE
21 RW 0x0
be cleared to 0.
0 = DISABLE
1 = ENABLE
20 RW 0x0
be cleared to 0.
0 = DISABLE
1 = ENABLE
mode.
Value Specific Test.
0000b: Not enabled.
0001b: J_ STATE.
0010b: K_STATE.
0011b: SEQ_NAK.
0100b: Packet.
19:16 RW 0x0
0101b: FORCE_ENABLE.
0110b to 1111b: Reserved.
Refer to Chapter 7 of the USB Specification Revision 2.0 for details on each test mode.
0 = NORMAL_OP
1 = TEST_J
2 = TEST_K
3 = TEST_SE0_NAK
4 = TEST_PKT
15:14 RO X
13 RO X
always be 0.

USB Complex
PPC PP Operation
12 RW 0x1
0 = NOT_POWERED
1 = POWERED
00b = SE0
01b = K-state
10b = J-state
11b = Undefined
of line-state by the host controller driver is not necessary (unlike EHCI), because the port
mode, the use of line-state by the device controller driver is not necessary.
0 = SE0
1 = K_STATE
2 = J_STATE
3 = UNDEFINED
Address (DA) is specified Controller will instigate L1 entry during suspend (bit 7) and L1 exit
during resume (bit 6). When set to zero the Controller will use the legacy (L2) mechanism.
9 RW 0x0 Software should only set this bit when the device attached immediately downstream supports L1
transitions. When acting as device, this bit is read-only and set to '1' by the hardware when the
Controller enters is L1 state (LPM token received and accepted). Note: HSP is redundant with
PSPD(27:26). This bit is not defined in the EHCI specification.
PR: This field is zero if Port Power (PP) is zero.

In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. When software writes a one
to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This
bit will automatically change to zero after the reset sequence is complete. This behavior is
different from EHCI where the host controller driver is required to set this bit to a zero after the
8 RW 0x0
reset duration is timed in the driver.
In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated
in the USBSTS register.
0 = NOT_USB_RESET
1 = USB_RESET

USB Complex
SUSP: Port suspend. 1=Port in suspend state. 0=Port not in suspend state.
In Host Mode: Read/Write. Port Enabled Bit and Suspend bit of this register define the port states
as follows:
0x Disable
10 Enable
11 Suspend
When in suspend state, downstream propagation of data is blocked on this port, except for port
reset. The blocking occurs at the end of the current transaction if a transaction was in progress
7 RO X
when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note
that the bit status does not change until the port is suspended and that there may be a delay in
suspending a port if there is a transaction currently in progress on the USB. The host controller
will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. A
write of zero to this bit is ignored by the host controller. If host software sets this bit to a one when
the port is not enabled (i.e., Port enabled bit is a zero) the results are undefined. This field is zero
if Port Power (PP) is zero in host mode.
In Device Mode: Read Only. This bit is a read only status bit.
0 = NOT_SUSPEND
1 = SUSPEND
In Device mode: After the device has been in Suspend State for 5ms or more, software must set
0 = NO_RESUME
1 = RESUME

1 = CHANGE

1 = OVER_CURRENT
3 RW 0x0
In Device mode: The device port is always enabled. (This bit will be zero)
0 = NO_CHANGE
1 = CHANGE
PE: Port Enabled/Disabled: 1=Enable. 0=Disable (default)

2 RW 0x1 Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault
enabling a port due to other host controller and bus events. When the port is disabled, (0b)

USB Complex

0 = PORT_DISABLED
1 = PORT_ENABLED
CSC: Connect Status Change: 1 =Change in Current Connect Status. 0=No change (default).
1 RW 0x0
0 = NO_CHANGE
1 = CHANGE
CCS: Current Connect Status:

mode.
0 RO X In Device Mode: 1=Attached 0=Not Attached (default) A one indicates that the device
0 = NOT_CONNECTED
1 = CONNECTED
19.13.8.30 USB2_CONTROLLER_2_USB2D_HOSTPC1_DEVLC_0

This register controls the LPM behavior and the behavior of each USB port in device mode only. This register shares the same
address with the HOSTPC1 register (which is used only in host mode).

This register controls the LPM behavior and controls the behavior of each USB port in host mode only. This register shares the
same address with the DEVLC register (which is used only in device mode).
0 = UTMI
1 = RESERVED
31:29 RW 0x0
2 = ULPI
3 = ICUSB_SER
4 = HSIC
28 RW 0x0
0 = PARALLEL_IF
1 = SERIAL_IF
1 = RESERVED

USB Complex
PSPD: This register field indicates the speed at which the port is operating.
00 = Full Speed
01 = Low Speed
10 = High Speed.
26:25 RO X
0 = FULL_SPEED
1 = LOW_SPEED
2 = HIGH_SPEED
3 = RESERVED
ALPD: Auto Low Power While Disconnect - RW. Default = 0b. If set, this feature will be enabled
and every time the port enters the disconnect state it will also enter in low power state, disabling
the transceiver clock. The behavior will be same as if the PHCD bit was enabled(in fact this bit
will be set to 1 as soon as low power mode is enabled).When this field is set the WKCN field of
PORTSCx register(Wake on Connect Enable) will also be set. This way the core will wake up in
the USBMODE register.
23 RW 0x0
clock. Write a 0 enables it. Reading this bit will indicate the status of the PHY clock. NOTE: The
PHY clock cannot be disabled if it is being used as the system clock.
In device mode, the PHY can be put into Low Power Clock Disable when the device is not
running (USBCMD RS=0b) or the host has signaled suspend (PORTSCx SUSP=1b). Low Power
Clock Disable will be cleared automatically when the host has signaled resume. Before forcing a
22 RW 0x0
resume from the device, the Controller driver must clear this bit.
In host mode, the PHY can be put into Low Power Suspend Clock Disable when the downstream
device has been put into suspend mode or when no downstream device is connected. Low Power
Clock Disable is completely under the control of software.
0 = DISABLE
1 = ENABLE
LPMX: Auto LPM set. Default = 00b. This bit field is valid during Host Mode Only. For Device
Mode, this is reserved.
Value Meaning
ASUS: Auto Low Power. Default = 0b. This bit field is valid during Device Mode Only. In Host
Mode it is part of ELPM field. This bit is used to control the auto low power feature. If set, the auto
low power feature will be enabled and every time the port enters the suspend state, it will also
17 RW 0x0 enter the low power state, disabling the transceiver clock. The behavior will be the same as if the
PHCD bit was enabled (in fact this bit will be set to '1' as soon as low power mode is enabled).
0 = DISABLE
1 = ENABLE
EPLPM: Endpoint for LPM token. Default = 0000b. This bit field is valid during Host Mode only.
For Device Mode, bits [19:18] are reserved and bit 17 is ASUS, while bit 16 is STL. This sets the
19:16 RW 0x0
endpoint number to which the LPM token will be sent. It will be directly mapped to the ENDP field
in the LPM token with the EXT PID.

USB Complex
STL: STALL reply to LPM token. Default = 0b. This bit field is valid during Device Mode only. In
Host Mode it is a part of ELPM field. When this bit is set to '1', the Controller will reply always with
16 RW 0x0 STALL to all incoming LPM tokens. This bit overrides the LPM NYET bit (NYT).
0 = DISABLE
1 = ENABLE
LPMFRM: Auto LPM SOF Threshold. Default = 0000b. This bit field is valid during Host Mode
only. For Device Mode, this is reserved. This holds the SOF counter threshold. When the number
15:12 RW 0x0 of SOF with no activity in between reaches this threshold and the auto LPM is enabled, an LPM
token will be sent and the port will enter in suspend state. The SOF counter for this threshold is
incremented each 125 µs, even if the port is not in HS operation.
BA: BmAttributes . Default = 00000000000b. This holds the bmAttributes field of the LPM sub-
11:1 RO X
token received, after the EXT PID token.
NYT_ASUS: NYET reply to LPM token. Default = 0b. This bit is NYT during Device Mode. Details
follow: When this bit is to '1', the device controller will NYET all the LPM tokens. When this bit is
set to '0', the Controller will ACK all the LPM tokens if the STALL bit (STL) is also set to '0'. This
bit is ASUS in Host Mode. Details follow: This bit is used to control the auto low power feature. If
set, the auto low power feature will be enabled and every time the port enters in suspend state it
0 RW 0x0
will also enter in low power state, disabling the transceiver clock. The behavior will be the same
as if the PHCD bit was enabled (in fact this bit will be set to '1' as soon as low power mode is
enabled).
0 = DISABLE
1 = ENABLE
19.13.8.31 USB2_CONTROLLER_2_USB2D_OTGSC_0

1 = ENABLE
interrupt.
29 RW 0x0
0 = DISABLE
1 = ENABLE
1 = ENABLE
1 = ENABLE
1 = ENABLE
1 = ENABLE
1 = ENABLE
bus pulsing is only detected when USBMODE.CM = Host (11) and PORTSC(0).PortPower = Off (0).
22 RW 0x0 Software writes a 1 to clear this bit.
0 = INT_CLEAR
1 = INT_SET

USB Complex
21 RW 0x0
0 = INT_CLEAR
1 = INT_SET
end threshold. Software writes a 1 to clear this bit .
20 RW 0x0
0 = INT_CLEAR
1 = INT_SET
19 RW 0x0
0 = INT_CLEAR
1 = INT_SET
18 RW 0x0
0 = INT_CLEAR
1 = INT_SET
17 RW 0x0
0 = INT_CLEAR
1 = INT_SET
16 RW 0x0
0 = INT_CLEAR
1 = INT_SET
1 = STS_SET
1 = STS_SET
1 = STS_SET
1 = STS_SET
1 = STS_SET
1 = STS_SET

8 RO X 0 = A_DEV
1 = B_DEV
IDPU: USB ID Pullup

5 RW 0x1 0 = CLEAR
1 = SET
SRP.
4 RW 0x0
0 = NO_DATA_PULSE
1 = DATA_PULSE
the pulldown on DM.
3 RW 0x0
0 = NO_OTG_TERM
1 = OTG_TERM

USB Complex
pulsing during SRP.
1 RW 0x0
0 = NO_VBUS_CHRG
1 = VBUS_CHRG
1 = VBUS_DISCHRG
19.13.8.32 USB2_CONTROLLER_2_USB2D_USBMODE_0

ALPDD: Auto Low Power While Disconnect Delay, Used when the ALPD field of the HOSTPCx
31:16 RW 0x0
65535*64*100/3 = 139,808 ms. The minimum value is 0. Only used in host mode.
15 RW 0x0 SRT: Shorten USB Reset Time. Software should never set this bit to 1.
5 RW 0x0 power source (charge pump) and an off-chip source in systems when both are available. Only to
be used in Host Mode. No functionality is implemented for this, so software should not use this.
SDIS: Stream disable: 1 Streaming is disabled - helpful to avoid overruns/underruns when system
load is too high.
4 RO X
0 = STREAM_ENABLE
1 = STREAM_DISABLE
mechanism.
0 - Setup lockout is ON (default)
3 RO X 1 - Setup lockout is OFF.
Firmware requires the use of setup tripwire semaphore in USB2D_USBCMD register.
0 = LOCKOUT_ON
1 = LOCKOUT_OFF
ES: Endian Select: Note: For this implementation, this should be always set to 0 (little endian).
1 = RESERVED
RESET bit in the USBCMD register before reprogramming this register.
00 = Idle [Default]
01 = Reserved
1:0 RO X 10 = Device Controller
11 = Host Controller.
0 = IDLE
1 = RESERVED
2 = DEVICE_MODE
3 = HOST_MODE

USB Complex
19.13.8.33 USB2_CONTROLLER_2_USB2D_ENDPTNAK_0
USB2D Endpoint NAK Register

31:16 0x0
0 = CLEAR
1 = SET
15:0 0x0
0 = CLEAR
1 = SET
19.13.8.34 USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0
USB2D Endpoint NAK Enable Register

31:16 0x0
0 = DISABLE
1 = ENABLE
15:0 0x0
0 = DISABLE
1 = ENABLE
19.13.8.35 USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0

0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD

USB Complex
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD

USB Complex
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
0 = NOT_RCVD
1 = SETUP_RCVD
19.13.8.36 USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0

0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME

USB Complex
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME

USB Complex
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME

USB Complex
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME

USB Complex
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
0 = DONT_PRIME
1 = PRIME
19.13.8.37 USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0

31 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH

USB Complex
30 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
29 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
28 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
27 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
26 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
25 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
24 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
23 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
22 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
21 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH

USB Complex
20 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
19 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
18 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
0 = DONT_FLUSH
1 = FLUSH
0 = DONT_FLUSH
1 = FLUSH
15 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
14 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
13 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
12 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
11 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH

USB Complex
10 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
9 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
8 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
7 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
6 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
5 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
4 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
3 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
2 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
1 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH

USB Complex
0 0x0
in device mode.
0 = DONT_FLUSH
1 = FLUSH
19.13.8.38 USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0

31 X
0 = NOT_READY
1 = READY
30 X
0 = NOT_READY
1 = READY
29 X
0 = NOT_READY
1 = READY
28 X
0 = NOT_READY
1 = READY
27 X
0 = NOT_READY
1 = READY
26 X
0 = NOT_READY
1 = READY

USB Complex
25 X
0 = NOT_READY
1 = READY
24 X
0 = NOT_READY
1 = READY
23 X
0 = NOT_READY
1 = READY
22 X
0 = NOT_READY
1 = READY
21 X
0 = NOT_READY
1 = READY
20 X
0 = NOT_READY
1 = READY
19 X
0 = NOT_READY
1 = READY

USB Complex
18 X
0 = NOT_READY
1 = READY
17 X
0 = NOT_READY
1 = READY
16 X
0 = NOT_READY
1 = READY
15 X
0 = NOT_READY
1 = READY
14 X
0 = NOT_READY
1 = READY
13 X
0 = NOT_READY
1 = READY
12 X
0 = NOT_READY
1 = READY

USB Complex
11 X
0 = NOT_READY
1 = READY
10 X
0 = NOT_READY
1 = READY
9 X
0 = NOT_READY
1 = READY
8 X
0 = NOT_READY
1 = READY
7 X
0 = NOT_READY
1 = READY
6 X
0 = NOT_READY
1 = READY
5 X
0 = NOT_READY
1 = READY

USB Complex
4 X
0 = NOT_READY
1 = READY
3 X
0 = NOT_READY
1 = READY
2 X
0 = NOT_READY
1 = READY
1 X
0 = NOT_READY
1 = READY
0 X
0 = NOT_READY
1 = READY
19.13.8.39 USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0

31 0x0
0 = NOT_COMPLETE
1 = COMPLETE
30 0x0
0 = NOT_COMPLETE
1 = COMPLETE

USB Complex
29 0x0
0 = NOT_COMPLETE
1 = COMPLETE
28 0x0
0 = NOT_COMPLETE
1 = COMPLETE
27 0x0
0 = NOT_COMPLETE
1 = COMPLETE
26 0x0
0 = NOT_COMPLETE
1 = COMPLETE
25 0x0
0 = NOT_COMPLETE
1 = COMPLETE
24 0x0
0 = NOT_COMPLETE
1 = COMPLETE
23 0x0
0 = NOT_COMPLETE
1 = COMPLETE
22 0x0
0 = NOT_COMPLETE
1 = COMPLETE
21 0x0
0 = NOT_COMPLETE
1 = COMPLETE
20 0x0
0 = NOT_COMPLETE
1 = COMPLETE

USB Complex
19 0x0
0 = NOT_COMPLETE
1 = COMPLETE
18 0x0
0 = NOT_COMPLETE
1 = COMPLETE
17 0x0
0 = NOT_COMPLETE
1 = COMPLETE
16 0x0
0 = NOT_COMPLETE
1 = COMPLETE
15 0x0
0 = NOT_COMPLETE
1 = COMPLETE
14 0x0
0 = NOT_COMPLETE
1 = COMPLETE
13 0x0
0 = NOT_COMPLETE
1 = COMPLETE
12 0x0
0 = NOT_COMPLETE
1 = COMPLETE
11 0x0
0 = NOT_COMPLETE
1 = COMPLETE
10 0x0
0 = NOT_COMPLETE
1 = COMPLETE

USB Complex
9 0x0
0 = NOT_COMPLETE
1 = COMPLETE
8 0x0
0 = NOT_COMPLETE
1 = COMPLETE
7 0x0
0 = NOT_COMPLETE
1 = COMPLETE
6 0x0
0 = NOT_COMPLETE
1 = COMPLETE
5 0x0
0 = NOT_COMPLETE
1 = COMPLETE
4 0x0
0 = NOT_COMPLETE
1 = COMPLETE
3 0x0
0 = NOT_COMPLETE
1 = COMPLETE
2 0x0
0 = NOT_COMPLETE
1 = COMPLETE
1 0x0
0 = NOT_COMPLETE
1 = COMPLETE
0 0x0
0 = NOT_COMPLETE
1 = COMPLETE

USB Complex
19.13.8.40 USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0


23 X 0 = DISABLE
1 = ENABLE
TXT: TX Endpoint Type. Endpoint0 is fixed as a Control Endpoint.

0 = CTRL
19:18 X 1 = ISO
2 = BULK
3 = INTR
0 = EP_OK
1 = EP_STALL

7 X 0 = DISABLE
1 = ENABLE

0 = CTRL
3:2 X 1 = ISO
2 = BULK
3 = INTR
0 = EP_OK
1 = EP_STALL
19.13.8.41 USB2_CONTROLLER_2_USB2D_ENDPTCTRLn_0

1 = ENABLE
22 RW 0x0 device.
0 = KEEP_GOING
1 = RESET_PID_SEQ
0 = DIS_PID_SEQ
1 = ENB_PID_SEQ
19:18 RW 0x0 TXT: TX Endpoint Type: 00 = Control. 01 = Isochronous. 10 = Bulk. 11 = Interrupt.

0 = CTRL

USB Complex

1 = ISO
2 = BULK
3 = INTR
0 = EP_OK
1 = EP_STALL
1 = ENABLE
6 RW 0x0 device.
0 = KEEP_GOING
1 = RESET_PID_SEQ
0 = DIS_PID_SEQ
1 = ENB_PID_SEQ

0 = CTRL
3:2 RW 0x0 1 = ISO
2 = BULK
3 = INTR
STALL until this bit is either cleared by software or automatically cleared as above,
0 = EP_OK
1 = EP_STALL

These are used to generate the actual RTL registers for the USB3 controller interface.

This register controls the suspend and resume behavior of the USB controller/PHY.
Offset: 0x400 | Read/Write: R/W | Reset: 0bxxxxx00xxxxx000001001000xx000000
from device. This is used only for cases where wakeup response needs to be within 1 ms of spec.
26 RW 0x0 Used for Host mode ONLY.
0 = DISABLE
1 = ENABLE

USB Complex
UTMIP_SUSPL1_SET: Enable SuspendL1 for UTMIP PHY. Enabling this will only cut off clocks
to the UTMIP logic. The USB PLLs, PllU and UTMIP PLL will still be running.
25 RW 0x0
0 = DISABLE
1 = ENABLE
UHSIC_PHY_ENB: Set this to 0.

1 = ENABLE
USB_WAKEUP_DEBOUNCE_COUNT: USB PHY wakeup debounce counter. The USB will

18:16 RW 0x0 debounce any wakeup event by the number of clocks programmed in this counter. A value of 0
results in no debounce.
ICUSB_MOD_CLK_ENB: ICUSB module clock enable. Enables transceiver clock to USB

controller when in ICUSB mode. After setting ICUSB_PHY_ENB, software needs to wait until
PLLU output is stable before setting ICUSB_MOD_CLK_ENB to ENABLE. This will be reset to
15 RW 0x0 DISABLE whenever ICUSB is in suspend. Software needs to enable it after ICUSB comes out of
suspend after waiting for PLLU output to be stable again.
0 = DISABLE
1 = ENABLE
UHSIC_RESET: Reset going to UHSIC PHY (active high). This should be set to 1 whenever
programming the UHSIC config registers. It should be cleared to 0 after the programming of
UHSIC config registers is done. UHSIC config registers should be programmed only once before
14 RW 0x1 doing any transactions on UHSIC. The UHSIC PHY registers should be programmed while the
UHSIC is in reset.
0 = DISABLE
1 = ENABLE
ICUSB_PHY_ENB: Enable ICUSB PHY mode. Setting this will enable the PLLU output clock
when ICUSB is not in suspend mode.
13 RW 0x0
0 = DISABLE
1 = ENABLE
UTMIP_PHY_ENB: Enable UTMIP PHY mode. Set this to 1 if using UTMIP PHY. Otherwise set
this to 0.
12 RW 0x0
0 = DISABLE
1 = ENABLE
11 RW 0x1 doing any transactions on USB. The UTMIP PHY registers should be programmed while UTMIP
is in reset.
0 = DISABLE
1 = ENABLE
USB_SUSP_POL: Polarity of the suspend signal going to the USB PHY. 0 = Active low (default),
1 = Active high. This should not be changed by software.
10 RW 0x0
0 = ACTIVE_LOW
1 = ACTIVE_HIGH
9 RW 0x0
0 = DISABLE
1 = ENABLE
the USB PHY clock is woken up from suspend. Software must write a 1 to clear this bit.
8 RO 0x0
0 = UNSET
1 = SET
0 = UNSET
1 = SET
6 RO X USB_CLKEN: USB AHB clock enable status. Indicates whether the AHB clock to the USB

USB Complex

set to 0. NOTE: Even when this is set to 0, all essential blocks that are required to resume USB
0 = UNSET
1 = SET
USB_SUSP_CLR: Suspend Clear. Software must write a 1 to this bit to bring the PHY out of
5 RW 0x0
0 = UNSET
1 = SET

enabled (1), USB device will wake up from suspend on a disconnect event. This is only valid
0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE
USB_WAKE_ON_RESUME_EN: Wake on resume enable. If this bit is enabled, USB will wake up
from suspend whenever a resume event is detected on USB. This is valid for both USB device
2 RW 0x0 and USB host modes.
0 = DISABLE
1 = ENABLE

1 RW 0x0
0 = DISABLE
1 = ENABLE
USB_WAKEUP_INT_STS: USB wakeup interrupt status. This bit is set whenever USB wakes up
from suspend (a wakeup event is generated). Software must write a 1 to clear this bit. Note that
during the wakeup sequence, PHY clocks will be resumed from suspend. Software can check
when the PHY clocks are resumed by reading the bit USB_PHY_CLK_VALID. There is also a
0 RO 0x0 separate interrupt generated when PHY clock is resumed if USB_PHY_CLK_VALID_INT_EN is
set. During the wakeup sequence, first USB_WAKEUP_INT_STS will be set, and it will take some
time for the PHY clock to resume, which can be detected by checking USB_PHY_CLK_VALID.
0 = UNSET
1 = SET

§ A_VBUS_VLD
§ A_SESS_VLD
§ B_SESS_VLD
§ B_SESS_END

USB Complex
30 RW 0x0
0 = DISABLE
1 = ENABLE

0 = SEL_A
1 = SEL_B
A_VBUS_VLD_SW_VALUE: A_VBUS_VLD software value. Software should write the appropriate

28 RW 0x0 set.
0 = UNSET
1 = SET

0 = DISABLE
1 = ENABLE

is 1.
26 RO X
0 = UNSET
1 = SET

25 RO 0x0
0 = UNSET
1 = SET

24 RW 0x0
0 = DISABLE
1 = ENABLE
22 RW 0x0
0 = DISABLE
1 = ENABLE

0 = SEL_A
1 = SEL_B

20 RW 0x0 set.
0 = UNSET
1 = SET

19 RW 0x0 A_SESS_VLD. Software sets this bit to drive the value in A_SESS_VLD_SW_VALUE to the USB
controller.
0 = DISABLE
USB Complex

1 = ENABLE

is 1.
18 RO X
0 = UNSET
1 = SET

change is detected in the value of A_SESS_VLD. Software writes a 1 to clear it.
17 RO 0x0
0 = UNSET
1 = SET

16 RW 0x0
0 = DISABLE
1 = ENABLE
14 RW 0x0
0 = DISABLE
1 = ENABLE

0 = SEL_A
1 = SEL_B

12 RW 0x0 set.
0 = UNSET
1 = SET

0 = DISABLE
1 = ENABLE

is 1.
10 RO X
0 = UNSET
1 = SET

9 RO 0x0
0 = UNSET
1 = SET

8 RW 0x0
0 = DISABLE
1 = ENABLE
6 RW 0x0
0 = DISABLE
1 = ENABLE

0 = SEL_A
1 = SEL_B

4 RW 0x0 set.
0 = UNSET
1 = SET

USB Complex
B_SESS_END_SW_EN: Enable Software Controlled B_SESS_END. Software sets this bit to drive
the value in B_SESS_END_SW_VALUE to the USB controller.
3 RW 0x0
0 = DISABLE
1 = ENABLE
B_SESS_END_STS: B_SESS_END status. This is set to 1 whenever the B_SESS_END sensor

output is 1.
2 RO X
0 = UNSET
1 = SET

1 RO 0x0
0 = UNSET
1 = SET

0 RW 0x0
0 = DISABLE
1 = ENABLE
USB PHY VBUS Wakeup and ID Control Register

This register controls the battery charger (VDCD_DET, VDAT_DET), VBUS_WAKEUP, and ID sensors. The following sensors
§ VBUS_WAKEUP
§ ID
§ VDAT_DET
§ VDCD_DET
There are debouncers for VDAT_DET and VDCD_DET. These use separate debouncers - CHRG_DEBOUNCE_PERIOD_A
For each sensor, we can select whether to use HRG_DEBOUNCE_PERIOD_A or CHRG_DEBOUNCE_PERIOD_B by setting


USB Complex
1 = ENABLE

30 RW 0x0
0 = DISABLE
1 = ENABLE
0 = SEL_A
1 = SEL_B
28 RW 0x0
0 = UNSET
1 = SET

27 RW 0x0
0 = DISABLE
1 = ENABLE

26 RO X 0 = UNSET
1 = SET

change is detected in the value of VDCD_DET. Software writes a 1 to clear it.
25 RO 0x0
0 = UNSET
1 = SET

24 RW 0x0
0 = DISABLE
1 = ENABLE
VOP_DIV2P7_DET:This read-only status bit is from the battery charging divider circuit of USB2OTG
pad
23 RO X
0 = UNSET
1 = SET
VOP_DIV2P0_DET:This read-only status bit is from the battery charging divider circuit of USB2OTG
pad
22 RO X
0 = UNSET
1 = SET
0 = SEL_A
1 = SEL_B
20 RW 0x0
0 = UNSET
1 = SET
VDAT_DET_SW_EN: Enable Software Controlled VDAT_DET. Software sets this bit to drive the
value in VDAT_DET_SW_VALUE to the USB controller.
19 RW 0x0
0 = DISABLE
1 = ENABLE
VDAT_DET_STS: VDAT_DET status. This is set to 1 whenever VDAT_DET sensor output is 1.

18 RO X 0 = UNSET
1 = SET

17 RO 0x0 change is detected in the value of VDAT_DET. software writes a 1 to clear it
0 = UNSET
USB Complex

1 = SET

16 RW 0x0
0 = DISABLE
1 = ENABLE
VON_DIV2P7_DET: This read-only status bit is from the battery charging divider circuit of
USB2OTG pad
15 RO X
0 = UNSET
1 = SET
VON_DIV2P0_DET: This read-only status bit is from the battery charging divider circuit of
USB2OTG pad generated whenever VDAT_DET_CHG_DET is set to 1.
14 RO X
0 = UNSET
1 = SET

0 = SEL_A
1 = SEL_B

0 = UNSET
1 = SET
VBUS_WAKEUP_SW_EN: Enable Software Controlled VBUS_WAKEUP. Software sets this bit to

drive the value in VBUS_WAKEUP_SW_VALUE to the USB controller.
11 RW 0x0
0 = DISABLE
1 = ENABLE

output is 1.
10 RO X
0 = UNSET
1 = SET
a change is detected in the value of VBUS_WAKEUP. software writes a 1 to clear it.
9 RO 0x0
0 = UNSET
1 = SET

8 RW 0x0
0 = DISABLE
1 = ENABLE

7 RO X 0 = UNSET
1 = SET

1 = ENABLE
0 = SEL_A
1 = SEL_B
4 RW 0x0
0 = UNSET
1 = SET
ID_SW_EN: Enable Software Controlled ID. Software sets this bit to drive the value in
ID_SW_VALUE to the USB controller
3 RW 0x0
0 = DISABLE
1 = ENABLE

USB Complex

2 RO X 0 = UNSET
1 = SET
1 RO 0x0
0 = UNSET
1 = SET

0 RW 0x0
0 = DISABLE
1 = ENABLE
USB PHY Alternate VBUS Status Register


8 X 0 = UNSET
1 = SET

7 X 0 = UNSET
1 = SET

6 X 0 = UNSET
1 = SET

5 X 0 = UNSET
1 = SET
ID_DIG_ALT: ID alternate status

4 X 0 = UNSET
1 = SET

3 X 0 = UNSET
1 = SET

2 X 0 = UNSET
1 = SET

1 X 0 = UNSET
1 = SET

0 X 0 = UNSET
1 = SET
19.13.9.5 USB3_IF_ICUSB_XCVR_CFG_0
ICUSB Transceiver Configuration Register

Offset: 0x414 | Read/Write: R/W | Reset: 0bxxxxxxxxxxx10000xx0000000xxx1111
31:24 RO X ICUSB_CALOUT: ICUSB PHY calibration code

USB Complex
ICUSB_CALOUT_EN: ICUSB PHY auto-calibration enable

1 = ENABLE
19:16 RW 0x0 ICUSB_DRV: ICUSB PHY Drive strength offset
13:8 RW 0x0 ICUSB_SLEW: ICUSB PHY FS/LS slew rate control
ICUSB_SEL_DIFF_RCVR: ICUSB differential receiver select

7 RW 0x0 0 = SINGLE
1 = DIFF
ICUSB_IDDQ: ICUSB PHY IDDQ shutdown mode

3 RW 0x1 0 = NORMAL
1 = OFF
ICUSB_PD_ZI: ICUSB PHY Single-ended receiver power down

2 RW 0x1 0 = NORMAL
1 = OFF
ICUSB_PD_DR: ICUSB PHY Differential receiver power down

1 RW 0x1 0 = NORMAL
1 = OFF
ICUSB_PD_TX: ICUSB PHY Low/full-speed driver power down

0 RW 0x1 0 = NORMAL
1 = OFF

This controls the interpacket delay between two consecutive transmit packets in HS mode. This only applies to host mode
because device never transmits two packets in a row.
IP_DELAY_TX2TX_HS: HS Tx to Tx inter-packet delay. This is valid only for the UTMIP PHY. Software
6:0 0x12
should not change this.
USB Controller Resume Signalling Delay

15:0 0x6978
19.13.9.8 USB3_IF_ICUSB_PADCTLS_0
ICUSB Pad Controls Config

Offset: 0x494 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxxxxxxxxxxx000000000
ICUSB_RPU2_EN: Config RPU2_EN state.

8 0x0 0 = DISABLE
1 = ENABLE

USB Complex
7 0x0 ICUSB_DISABLE_PULLUP_DP: Force DP pull-up inactive. (Overrides FORCE_PULLUP_DP.)
6 0x0 ICUSB_DISABLE_PULLUP_DM: Force DM pull-up inactive. (Overrides FORCE_PULLUP_DM.)
5 0x0 ICUSB_DISABLE_PULLDN_DP: Force DP pull-down inactive. (Overrides FORCE_PULLDN_DP.)
4 0x0 ICUSB_DISABLE_PULLDN_DM: Force DM pull-down inactive. (Overrides FORCE_PULLDN_DM.)
3 0x0 ICUSB_FORCE_PULLUP_DP: Force DP pull-up active.
2 0x0 ICUSB_FORCE_PULLUP_DM: Force DM pull-up active.
1 0x0 ICUSB_FORCE_PULLDN_DP: Force DP pull-down active.
0 0x0 ICUSB_FORCE_PULLDN_DM: Force DM pull-down active.
Spare Register

31:16 0xffff SPARE_HI[0] - usb_port_reset_fix_en. Enable port-reset fix
SPARE_HI[1] - hsic_conn_det_feature_enable. enable HSIC connect detection

15:0 0x0 SPARE_LO[4] - usb_hs_rsm_eop_fix_en. Enable HS_RESUME EOP fix
SPARE_LO[5] - usb_port_suspend_fix_en

15:8 0xf REQUEST_EXPIRY_COUNTER: Time to wait for coalescing the request.
1 0x0
0 = DISABLE
1 = ENABLE

0 0x0 0 = DISABLE
1 = ENABLE
19.13.10 XUSB Host Registers
19.13.10.1 XUSB_HOST_AXI_BAR0_SZ_0
19:0 0x8 AXI_BAR0_SIZE: The size of the address range associated with BARi is in 4K increments. Value of 0
signifies BARi is not used.

USB Complex
Offset: 0xc | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxx00000000000000000000)
19.13.10.5 XUSB_HOST_AXI_BAR0_START_0
Offset: 0x40 | Read/Write: R/W | Reset: 0x70090000 (0b01110000000010010000xxxxxxxxxxxx)
31:12 0x70090 AXI_BAR0_START: The start of the AXI address space for BARi. The AXI target address is
compared to start/size for each BAR to determine if the access is to that BAR.
31:12 0x0 AXI_BAR1_START: The start of AXI address space for BARi. The AXI target address is compared to
start/size for each BAR to determine if the access is to that BAR.
31:12 0x0 AXI_BAR2_START: The start of the AXI address space for BARi. The AXI target address is compared
to start/size for each BAR to determine if the access is to that BAR.
Offset: 0x4c | Read/Write: R/W | Reset: 0x00000000 (0b00000000000000000000xxxxxxxxxxxx)
31:12 0x0 AXI_BAR3_START: The start of the AXI address space for BARi. The AXI target address is compared
to start/size for each BAR to determine if the access is to that BAR.

USB Complex
19.13.10.9 XUSB_HOST_FPCI_BAR0_0
Offset: 0x80 | Read/Write: R/W | Reset: 0x00700901 (0b0000000001110000000010010000xxx1)
31:4 0x70090 FPCI_BAR0_START: The start of the FPCI address space mapped into the BARi range of PCI
memory space. The 40-bit FPCI address is determined by a 12-bit left shift of the value of this register.
0 0x1 FPCI_BAR0_ACCESS_TYPE: Indicates if the address region is memory mapped versus configuration
or I/O space.
0 = memory-mapped access (PW only)
1 = I/O or config access (NPW only)
31:4 0x0 FPCI_BAR1_START: The start of FPCI address space mapped into the BARi range of PCI memory
space. The 40-bit FPCI address is determined by a 12-bit left shift of the value of this register.
0 0x1 FPCI_BAR1_ACCESS_TYPE: Indicates if the address region is memory mapped versus configuration or
I/O space.
0 = Memory-mapped access (PW only)
0 0x1 FPCI_BAR2_ACCESS_TYPE: Indicates if the address region is memory mapped versus configuration
or I/O space.
Offset: 0x8c | Read/Write: R/W | Reset: 0x00000001 (0b0000000000000000000000000000xxx1)
0 0x1 FPCI_BAR3_ACCESS_TYPE: Indicates if the address region is memory mapped versus configuration or
I/O space.
19.13.10.13 XUSB_HOST_MSI_BAR_SZ_0
MSI BAR SIZE

Offset: 0xc0 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxx00000000000000000000)

USB Complex
19:0 0x0 MSI_BAR_SIZE: The size of the address range associated with MSI BAR is in 4K increments. Value of 0
signifies BAR is not used.
19.13.10.14 XUSB_HOST_MSI_AXI_BAR_ST_0
MSI AXI BAR START

Offset: 0xc4 | Read/Write: R/W | Reset: 0x00000000 (0b00000000000000000000xxxxxxxxxxxx)
31:12 0x0 MSI_AXI_BAR_START: The start of the upstream AXI address space for MSI BAR. The upstream FPCI
address is compared to start/1KB range for the MSI BAR to determine if the access is MSI. Bits 31:12 of
MSI BAR start correspond to AXI address bits 31:12.
19.13.10.15 XUSB_HOST_MSI_FPCI_BAR_ST_0
MSI FPCI BAR START

Offset: 0xc8 | Read/Write: R/W | Reset: 0x00000000 (0b0000000000000000000000000000xxxx)
31:4 0x0 MSI_FPCI_BAR_START: The start of the upstream FPCI address space for MSI BAR. The upstream
FPCI address is compared to start/1KB range for MSI BAR to determine if the access is MSI. Bits 31:4 of
MSI BAR start correspond to UFPCI address bits 39:12.
19.13.10.16 XUSB_HOST_MSI_VEC0_0
MSI VECTORi, i in [0,7], RW

31:0 0x0 MSI_VECTOR0: Each vector register corresponds to 32 of the possible 256 MSI vectors.VECTOR0
corresponds to MSI vectors 31-0. Vector7 corresponds to MSI vectors 255-223.When an upstream MSI
is sent, the bit corresponding to the MSI vector is set to 1 by hardware if the corresponding enable bit is
1.The bit is set to 0 if a 1 is written to its location.

USB Complex
19.13.10.24 XUSB_HOST_MSI_EN_VEC0_0
MSI ENABLE VECTORi, i in [0,7], RW

31:0 0x0 MSI_ENABLE_VECTOR0: Each vector register corresponds to the enable bit for 32 of the possible 256

USB Complex

MSI vectors. ENABLE VECTOR0 corresponds to enable bits for MSI vectors 31-0. Vector7 corresponds
to enable bits for MSI vectors 255-223.When an upstream MSI is sent, the bit corresponding to the MSI
vector is set to 1 by hardware if the corresponding enable bit is 1.

USB Complex
19.13.10.32 XUSB_HOST_CONFIGURATION_0
Configuration
Offset: 0x180 | Read/Write: R/W | Reset: 0x800X8X40 (0b1xxxxxxxxxxx1xxx10xxxxxx01000000)
31 RW 0x1 CLKEN_OVERRIDE: This can override the clock enable in case of a malfunction.
19 RW 0x1 PW_NO_DEVSEL_ERR_CYA: Setting this bit disables detection of DECERR due to no DEVSEL for
DS PWs only.
What are DS and PW? PW= pass write?
18 RO X INITIATOR_READ_IDLE: This read-only bit provides status reads on AFI upstream A value of 1b
indicates there are no outstanding reads to the initiator.
17 RO X INITIATOR_WRITE_IDLE: This read-only bit provides status writes on AFI upstream A value of 1b
indicates there are no outstanding writes to the initiator.
15 RW 0x1 WDATA_LEAD_CYA: Used to en(dis)able the handling of write data ahead of requests on IPFS AXI
target.
14 RW 0x0 WR_INTRLV_CYA: Used to en(dis)able the handling of interleaved write requests on IPFS AXI
target.
11 RO X TARGET_READ_IDLE: This read-only bit provides status reads to IPFS target. A value of 1b
indicates there are no outstanding reads to the downstream FPCI.
10 RO X TARGET_WRITE_IDLE: This read-only bit provides status writes to IPFS target. A value of 1b
indicates there are no outstanding writes to the downstream FPCI.
9 RO X MSI_VEC_EMPTY: This read-only bit provides status on whether MSI Vector registers have any
active bits valid or not.
7 RW 0x0 UFPCI_MSIAW: MSI After Write ordering rule.

1 = Whenever MSI is ready assert the interrupt
0 = Default behavior, apply MSIAW ordering rule
6 RW 0x1 UFPCI_PWPASSPW: Input to the upstream FPCI

1 = Whenever write is ready, send it.
0 = Write goes only when outstanding PWs outside of new write's region are retired (default).
5 RW 0x0 UFPCI_PASSPW: Input to the upstream FPCI. Allows the upstream FPCI reads to pass writes.
4 RW 0x0 UFPCI_PWPASSNPW: Used for the upstream FPCI. Allows the upstream FPCI PWs to pass
NPWs.
3 RW 0x0 DFPCI_PWPASSNPW: Used for the downstream FPCI. Allows the downstream FPCI PWs to pass
NPWs.

USB Complex
2 RW 0x0 DFPCI_RSPPASSPW: Input to the downstream FPCI. Allows the downstream FPCI responses to
pass writes
1 RW 0x0 DFPCI_PASSPW: Input to the downstream FPCI. Allow the downstream FPCI reads to pass writes.
0 RW 0x0 EN_FPCI: When the IPFS device block is disabled, it is completely invisible on the IPFS bus; i.e., it
does not even process IPFS configuration accesses.
19.13.10.33 XUSB_HOST_FPCI_ERROR_MASKS_0
FPCI Error Masks

2 0x0 MASK_FPCI_MASTER_ABORT: This bit allows an FPCI error to be forwarded to an AXI response when
the FPCI error response indicates a Master Abort.
1 = Forward error
0 = Return AXI OKAY response (2'b0)
1 0x0 MASK_FPCI_DATA_ERROR: This bit allows an FPCI error to be forwarded to an AXI response when the
FPCI error response indicates a Data Error.
1 = Forward error
0 0x0 MASK_FPCI_TARGET_ABORT: This bit allows an FPCI error to be forwarded to an AXI response when
FPCI error response indicates a Target Abort. This bit also covers a decode error generated when there is
no DEVSEL received.
1 = Forward error
19.13.10.34 XUSB_HOST_INTR_MASK_0
Interrupt Masks
Offset: 0x188 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxx0xxxxxxx0xxxxxxx0)
16 0x0 IP_INT_MASK: IP (SATA/AZA) interrupt to the CPU complex gated by the mask.
8 0x0 MSI_MASK: MSI to the CPU complex gated by the mask.
0 0x0 INT_MASK: Interrupt to the CPU complex gated by the mask.
19.13.10.35 XUSB_HOST_INTR_CODE_0
Interrupt Control
4:0 0x0 INT_CODE: Eight interrupt codes. If the code is 0, logging of the next interrupt is enabled
0 = INT_CODE_CLEAR : Clear interrupt code
1 = INT_CODE_INI_SLVERR: Interrupt code for CPU AXI SLVERR response to IPFS
2 = INT_CODE_INI_DECERR: Interrupt code for CPU AXI DECERR response to IPFS
3 = INT_CODE_TGT_SLVERR: Interrupt code for PCIe endpoint FPCI target abort or data error response
to IPFS
4 = INT_CODE_TGT_DECERR: Interrupt code for PCIe2 FPCI master abort response to IPFS
5 = INT_CODE_TGT_WRERR: Interrupt code for bufferable write to non-posted write address region
6 = RSVD1: Reserved

USB Complex

7 = INT_CODE_DFPCI_DECERR: Interrupt code for PCIe2 response to downstream request when
downstream FPCI address does not fall in a claimable downstream region
8 = INT_CODE_AXI_DECERR: Interrupt code for IPFS response to downstream request when AXI target
AXI address does not fall in any IPFS downstream BARs
9 = INT_CODE_FPCI_TIMEOUT: Interrupt code for FPCI Timeout
10 = RSVD2: Reserved for future expansion
11 = RSVD3
12 = RSVD4
13 = RSVD5
14 = RSVD6
15 = INT_CODE_SM_FATAL_ERROR: Interrupt code for SM fatal error
16 = INT_CODE_SM_NON_FATAL_ERROR: Interrupt code for SM non-fatal error
19.13.10.36 XUSB_HOST_INTR_SIGNATURE_0
Interrupt Signature
31:2 0x0 INT_INFO: For interrupt codes 1-5/7-8, this field contains address bits [31:2], either in FPCI memory
space or AXI space. For FPCI generated errors, the field contains the FPCI address. For AXI/IPFS
generated errors, the field contains the AXI address.
0 0x0 DIR: Indicates the direction of the AXI/FPCI transaction. 1=RD/0=WRIF signature type is 6 (sideband
message), this field is 1.
0 = WRITE: Interrupt due to a write transaction
1 = READ: Interrupt due to a read transaction
19.13.10.37 XUSB_HOST_UPPER_FPCI_ADDR_0
Upper FPCI Address

7:0 0x0 INT_INFO_UPPER: These 8 bits are the upper byte of the captured FPCI address (bits [39:32]) when the
interrupt code is 3, 4, or 7. These bits determine the region in the Hypertransport Address Map that was
accessed.
19.13.10.38 XUSB_HOST_IPFS_INTR_ENABLE_0
IPFS Interrupt Enable

Offset: 0x198 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxx00xxxx00000000)
13 0x0 EN_SM_NON_FATAL_ERROR: Enable bit for interrupt code 15
12 0x0 EN_SM_FATAL_ERROR: Enable bit for interrupt code 14
7 0x0 EN_FPCI_TIMEOUT: Enable bit for interrupt code 9
6 0x0 EN_AXI_DECERR: Enable bit for interrupt code 8
5 0x0 EN_DFPCI_DECERR: Enable bit for interrupt code 7
4 0x0 EN_TGT_WRERR: Enable bit for interrupt code 5
3 0x0 EN_TGT_DECERR: Enable bit for interrupt code 4
2 0x0 EN_TGT_SLVERR: Enable bit for interrupt code 3

USB Complex
1 0x0 EN_INI_DECERR: Enable bit for interrupt code 2
0 0x0 EN_INI_SLVERR: Enable bit for interrupt code 1
19.13.10.39 XUSB_HOST_UFPCI_CONFIG_0
Upstream FPCI Configuration

4:0 0x2 UNITID_T0C0: Upstream FPCI Unit ID for controller 0. HyperTransport, upstream FPCI request
19.13.10.40 XUSB_HOST_CFG_REVID_0
CFG_REVID Register
Offset: 0x1a0 | Read/Write: R/W | Reset: 0x000X10XX (0bxxxxxxxxxxxxxxxxxx0100xxxxxxx1xx)
19 RO X DEV2SM_NONISO_REQUEST_PEND: This bit indicates if there is a non-ISO request pending.

0 = NO
1 = YES
18 RO X DEV2SM_ISO_REQUEST_PEND: This bit indicates if there is an ISO request pending.

0 = NO
1 = YES
13:12 RW 0x1 STRAP_CPU_MODE: MCP: Mode to send MSI. It can be programmable.

0 = NB_INTEL
1 = NB_AMD
2 = AMD
3 = TMTA
11 RW 0x0 CFG_REVID_WRITE_ENABLE: MCP: The enable to override the rev ID. It can be
programmable.
0 = CLEAR
1 = SET
10 RW 0x0 CFG_REVID_OVERRIDE: MCP: Provides a way to override the current revision ID. It can be
programmable.
0 = DISABLE
1 = ENABLE
4 RO X DEV2LEG_NONCOH_REQUEST_PEND: MCP: Tells the leg block that a non-coherent request

is pending.
0 = NO
1 = YES
3 RO X DEV2LEG_COH_REQUEST_PEND: MCP comment: Tells the leg block that a coherent request
is pending.
0 = NO
1 = YES
2 RW 0x1 SM2DEV_FPCI_TIMEOUT_EN: FPCI timeout enable bit for Controller

0 = DISABLE
1 = ENABLE
19.13.10.41 XUSB_HOST_FPCI_TIMEOUT_0
FPCI_TIMEOUT Register
Offset: 0x1a4 | Read/Write: R/W | Reset: 0x000f0000 (0bxxxxxxxxxxxx11110000000000000000)
USB Complex
19:0 0xf0000 SM2ALL_FPCI_TIMEOUT_THRESH: This field sets the timeout threshold value for the FPCI bus. It
starts counting for each queue (ISO/NISO- RD/WR) with a pending request in the FPCI wrapper, the
count resets when the requests are popped.
19.13.10.42 XUSB_HOST_TOM_0
Top of Memory Limit

Offset: 0x1a8 | Read/Write: R/W | Reset: 0x3fff0fff (0bxx11111111111111xxxx111111111111)
29:16 0x3fff LEG2ALL_TOM2: Top of Memory Limit 2.
11:0 0xfff LEG2ALL_TOM1: Top of Memory Limit 1.
19.13.10.43 XUSB_HOST_INITIATOR_ISO_PW_RESP_PENDING_0
Initiator ISO PW Response Pending

Offset: 0x1ac | Read/Write: RO | Reset: 0x000000XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
7:0 X NUM_INITIATOR_ISO_PW_RESP_PEND: Number of pending initiator ISO PW responses
19.13.10.44 XUSB_HOST_INITIATOR_NISO_PW_RESP_PENDING_0
Initiator Non-ISO PW Response Pending

Offset: 0x1b0 | Read/Write: RO | Reset: 0x000000XX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
7:0 X NUM_INITIATOR_NISO_PW_RESP_PEND: Number of pending initiator NISO PW responses
19.13.10.45 XUSB_HOST_INTR_STATUS_0
IPFS Interrupt Status

Offset: 0x1b4 | Read/Write: RO | Reset: 0x0000000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
2 X IP_INTR_STATUS: Status of IP (SATA/AZA) interrupt
1 X MSI_INTR_STATUS: Status of MSI interrupt
0 X IPFS_INTR_STATUS: Status of IPFS interrupt
19.13.10.46 XUSB_HOST_DFPCI_BEN_0
Downstream FPCI Byte Enables

Offset: 0x1b8 | Read/Write: R/W | Reset: 0x00000000 (0b0xxxxxxxxxxxxxxxxxxxxxxxxxxx0000)
31 0x0 EN_DFPCI_BEN: Enable bit for BEN. When set, the programmed BE is sent on the DFPCI bus

USB Complex
3:0 0x0 DFPCI_BYTE_ENABLE_N: Active low byte enables
19.13.10.47 XUSB_HOST_CLKGATE_HYSTERESIS_0
Offset: 0x1bc | Read/Write: R/W | Reset: 0x00000014 (0bxxxxxxxxxxxxxxxxxxxxxxxx00010100)
7:0 0x14 CLK_DISABLE_CNT: Number of IPFS clock cycles to wait after clock gating criteria are met to disable
IPFS/FPCI clocks
19.13.10.48 XUSB_HOST_XUSB_HOST_MCCIF_FIFOCTRL_0
Memory Client Interface FIFO Control Register
software compatibility.
The clock override/ovr_mode fields of this register control the second-level clock gating for the client and MC side of the
A '1' written to the rclk/wclk field results in one of the following:
§ With wclk/rclk override mode = LEGACY, the clock reverts to the legacy mode of operation (where the clock is on
whenever the client clock is enabled).
§ With wclk/rclk override mode = ON, the clock is always on inside the MCCIF and PC.
A '1' written to the cclk override field keeps the client's clock always on inside the MCCIF.Offset: 0x1dc | Read/Write: R/W |
Reset: 0x00000000 (0bxxxxxxxxxxx00000xxxxxxxxxxxx0000)
XUSB_HOST_RCLK_OVR_MODE:
1 = ON
XUSB_HOST_WCLK_OVR_MODE:
1 = ON
18 0x0 XUSB_HOST_CCLK_OVERRIDE
17 0x0 XUSB_HOST_RCLK_OVERRIDE
16 0x0 XUSB_HOST_WCLK_OVERRIDE
3 DISABLE XUSB_HOST_MCCIF_RDCL_RDFAST:
0 = DISABLE
1 = ENABLE
2 DISABLE XUSB_HOST_MCCIF_WRMC_CLLE2X:
0 = DISABLE
1 = ENABLE
1 DISABLE XUSB_HOST_MCCIF_RDMC_RDFAST:
0 = DISABLE
1 = ENABLE
0 DISABLE XUSB_HOST_MCCIF_WRCL_MCLE2X:
0 = DISABLE
1 = ENABLE

USB Complex
19.13.11 XUSB Host IFPS Registers
19.13.11.1 XUSB_HOST_ORDERING_RULES_0
Offset: 0x1e0 | Read/Write: R/W | Reset: 0x00000000 (0b000)
UPSTREAM_MSIAW: Modified Upstream MSIAW ordering.

3 0x0 0 = Tegra K1 MSIAW behavior
1 = Legacy (Tegra 3) MSIAW behavior
UPSTREAM_RESPAW: Modified RespAW ordering.

2 0x0 0 = Tegra K1 RespAW behavior
1 = Legacy (Tegra 3) RespAW behavior
UPSTREAM_RAW: Modified RAW ordering.

1 0x0 0 = Tegra K1 RAW behavior
1 = Legacy (Tegra 3) RAW behavior
19.13.11.2 XUSB_HOST_A2F_UFPCI_CFG0_0
Offset: 0x1e4 | Read/Write: R/W | Reset: 0x00000050 (0b00000000xxxxx0000000000001010000)
31:24 0x0 STATIC_WAIT_IDLE_CNTR
18:16 0x0 STATIC_UFPCI_UFA_STARVE_CNTR_PRI1
15:12 0x0 STATIC_UFPCI_UFA_STARVE_CNTR_PRI0
11:10 0x0 STATIC_UFPCI_RR_BURST_SZ_PRI1
9:8 0x0 STATIC_UFPCI_RR_BURST_SZ_PRI0
7 0x0 STATIC_WAIT_CLAMP_EN
6 0x1 STATIC_UFPCI_UFA_DYN_BLOCK_EN
5 0x0 STATIC_UFPCI_UFA_BLK_COHERENT
4:2 0x4 STATIC_UFPCI_BLOCK_CMD_THRESHOLD
1 0x0 STATIC_CYA_UFA_ARB
0 0x0 STATIC_CYA_BACK2BACK_UPSTREAM_BLOCK
19.13.11.3 XUSB_HOST_A2F_UFPCI_CFG1_0
Offset: 0x1e8 | Read/Write: R/W | Reset: 0x00000000 (0b00000000)
7:0 0x0 STATIC_WAIT_UNCLAMP_CNTR
19.13.12 XUSB PADCTL Registers
19.13.12.1 XUSB_PADCTL_BOOT_MEDIA_0

USB Complex
4:1 0x0 BOOT_PORT:

0 = USB2_OTG0
1 = USB2_OTG1
2 = USB2_OTG2
3 = USB2_OTG3
4 = USB2_OTG4
5 = USB2_OTG5
6 = USB2_OTG6
7 = ULPI
9 = HSIC0
10 = HSIC1
0 0x0 BOOT_MEDIA_ENABLE:
0 = NO
1 = YES
19.13.12.2 XUSB_PADCTL_USB2_PAD_MUX_0
Offset: 0x4 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxx00x0xxxxxx000000)
15 0x0 USB2_HSIC_PAD_PORT1:
0 = SNPS
1 = XUSB
14 0x0 USB2_HSIC_PAD_PORT0:
0 = SNPS
1 = XUSB
12 0x0 USB2_ULPI_PAD_PORT:
0 = SNPS
1 = XUSB
5:4 0x0 USB2_OTG_PAD_PORT2:

0 = SNPS
1 = XUSB
2 = UART

0 = SNPS
1 = XUSB
2 = UART

0 = SNPS
1 = XUSB
2 = UART
19.13.12.3 XUSB_PADCTL_USB2_PORT_CAP_0
Offset: 0x8 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxx00xxxxxxxxxxxx000000000000)
25 0x0 ULPI_PORT_INTERNAL:
0 = NO
1 = YES
24 0x0 ULPI_PORT_CAP:
0 = ULPI_MASTER
1 = ULPI_PHY
11 0x0 PORT2_REVERSE_ID:
0 = NO

USB Complex
1 = YES
PORT2_INTERNAL:
10 0x0 0 = NO
1 = YES
PORT2_CAP:
0 = DISABLED
9:8 0x0 1 = HOST_ONLY
2 = DEVICE_ONLY
3 = OTG_CAP
0 = NO
1 = YES
6 0x0 PORT1_INTERNAL:
0 = NO
1 = YES
5:4 0x0 PORT1_CAP:

0 = DISABLED
1 = HOST_ONLY
2 = DEVICE_ONLY
3 = OTG_CAP
0 = NO
1 = YES
0 = NO
1 = YES
1:0 0x0 PORT0_CAP:

0 = DISABLED
1 = HOST_ONLY
2 = DEVICE_ONLY
3 = OTG_CAP
19.13.12.4 XUSB_PADCTL_SNPS_OC_MAP_0
Offset: 0xc | Read/Write: R/W | Reset: 0x000001ff (0bxxxxxxxxxxxxxxxxxxxxxxx111111111)
8:6 0x7 CONTROLLER3_OC_PIN:

0 = OC_DETECTED0
1 = OC_DETECTED1
2 = OC_DETECTED2
3 = OC_DETECTED3
4 = OC_DETECTED_VBUS_PAD0
7 = OC_DETECTION_DISABLED

0 = OC_DETECTED0
1 = OC_DETECTED1
2 = OC_DETECTED2
3 = OC_DETECTED3

USB Complex
0 = OC_DETECTED0
1 = OC_DETECTED1
2 = OC_DETECTED2
3 = OC_DETECTED3
19.13.12.5 XUSB_PADCTL_USB2_OC_MAP_0
Offset: 0x10 | Read/Write: R/W | Reset: 0x000001ff (0bxxxxxxxxxxxxxxxxxxxxxxx111111111)
PORT2_OC_PIN:
0 = OC_DETECTED0
1 = OC_DETECTED1
2 = OC_DETECTED2
8:6 0x7 3 = OC_DETECTED3
5:3 0x7 PORT1_OC_PIN:

0 = OC_DETECTED0
1 = OC_DETECTED1
2 = OC_DETECTED2
3 = OC_DETECTED3
2:0 0x7 PORT0_OC_PIN:

0 = OC_DETECTED0
1 = OC_DETECTED1
2 = OC_DETECTED2
3 = OC_DETECTED3
19.13.12.6 XUSB_PADCTL_SS_PORT_MAP_0
0 = NO
1 = YES
6:4 0x7 PORT1_MAP:

0 = USB2_PORT0
1 = USB2_PORT1
2 = USB2_PORT2
7 = INIT_DISABLED
0 = NO
1 = YES

USB Complex
2:0 0x7 PORT0_MAP:

0 = USB2_PORT0
1 = USB2_PORT1
2 = USB2_PORT2
7 = INIT_DISABLED
19.13.12.7 XUSB_PADCTL_OC_DET_0
Offset: 0x18 | Read/Write: R/W | Reset: 0x0000fce0 (0bx0000000x00000001111110011100000)
OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2:
30 0x0 0 = NO
1 = YES
29 0x0 OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1:
0 = NO
1 = YES
28 0x0 OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0:
0 = NO
1 = YES
27 0x0 OC_DETECTED_INTERRUPT_ENABLE3:
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
OC_DETECTED_VBUS_PAD2:
22 0x0 0 = NO
1 = YES
21 0x0 OC_DETECTED_VBUS_PAD1:
0 = NO
1 = YES
20 0x0 OC_DETECTED_VBUS_PAD0:
0 = NO
1 = YES
19 0x0 OC_DETECTED3:
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
15:13 0x7 VBUS_ENABLE1_OC_MAP:

USB Complex

0 = OC_DETECTED0
1 = OC_DETECTED1
2 = OC_DETECTED2
3 = OC_DETECTED3
12:10 0x7 VBUS_ENABLE0_OC_MAP:

0 = OC_DETECTED0
1 = OC_DETECTED1
2 = OC_DETECTED2
3 = OC_DETECTED3
9 0x0 VBUS_ENABLE1:
0 = NO
1 = YES
8 0x0 VBUS_ENABLE0:
0 = NO
1 = YES
VBUS_ENABLE2_OC_MAP:
0 = OC_DETECTED0
1 = OC_DETECTED1
2 = OC_DETECTED2
7:5 0x7 3 = OC_DETECTED3
VBUS_ENABLE2:
4 0x0 0 = NO
1 = YES
3 0x0 SET_OC_DETECTED3:
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
19.13.12.8 XUSB_PADCTL_ELPG_PROGRAM_0
Offset: 0x1c | Read/Write: R/W | Reset: 0x07770000 (0bxxxxx111x111x11100x0000000x00000)
AUX_MUX_LP0_VCORE_DOWN:
26 0x1 0 = NO
1 = YES
25 0x1 AUX_MUX_LP0_CLAMP_EN_EARLY:
0 = NO

USB Complex

1 = YES
AUX_MUX_LP0_CLAMP_EN:
24 0x1 0 = NO
1 = YES
22 0x1 SSP1_ELPG_VCORE_DOWN:
0 = NO
1 = YES
21 0x1 SSP1_ELPG_CLAMP_EN_EARLY:
0 = NO
1 = YES
20 0x1 SSP1_ELPG_CLAMP_EN:
0 = NO
1 = YES
18 0x1 SSP0_ELPG_VCORE_DOWN:
0 = NO
1 = YES
17 0x1 SSP0_ELPG_CLAMP_EN_EARLY:
0 = NO
1 = YES
16 0x1 SSP0_ELPG_CLAMP_EN:
0 = NO
1 = YES
15 0x0 SS_PORT1_WAKEUP_EVENT:
0 = NO
1 = YES
14 0x0 SS_PORT0_WAKEUP_EVENT:
0 = NO
1 = YES
12 0x0 USB2_HSIC_PORT1_WAKEUP_EVENT:
0 = NO
1 = YES
11 0x0 USB2_HSIC_PORT0_WAKEUP_EVENT:
0 = NO
1 = YES
USB2_PORT2_WAKEUP_EVENT:
10 0x0 0 = NO
1 = YES
9 0x0 USB2_PORT1_WAKEUP_EVENT:
0 = NO
1 = YES
8 0x0 USB2_PORT0_WAKEUP_EVENT:
0 = NO
1 = YES
7 0x0 SS_PORT1_WAKE_INTERRUPT_ENABLE:
0 = NO
1 = YES
6 0x0 SS_PORT0_WAKE_INTERRUPT_ENABLE:
0 = NO
1 = YES
4 0x0 USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE:
0 = NO
1 = YES
3 0x0 USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE:
0 = NO

USB Complex

1 = YES
USB2_PORT2_WAKE_INTERRUPT_ENABLE:
2 0x0 0 = NO
1 = YES
1 0x0 USB2_PORT1_WAKE_INTERRUPT_ENABLE:
0 = NO
1 = YES
0 0x0 USB2_PORT0_WAKE_INTERRUPT_ENABLE:
0 = NO
1 = YES
19.13.12.9 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0
Offset: 0x20 | Read/Write: R/W | Reset: 0x00XX00XX (0b000000000x000x000000000000x000x1)
31 RW 0x0 GENERATE_SRP:
0 = NO
1 = YES
30 RW 0x0 SRP_INTR_EN:
0 = NO
1 = YES
29 RW 0x0 SRP_DETECTED:
0 = NO
1 = YES
28 RW 0x0 SRP_DETECT_EN:
0 = NO
1 = YES
27 RW 0x0 DCD_INTR_EN:
0 = NO
1 = YES
26 RW 0x0 DCD_DETECTED:
0 = NO
1 = YES
25 RW 0x0 ZIN_FILTER_EN:
0 = NO
1 = YES
24 RW 0x0 ZIN_CHNG_INTR_EN:
0 = NO
1 = YES
23 RW 0x0 ZIN_ST_CHNG:
0 = NO
1 = YES
22 RO X ZIN:
0 = NO
1 = YES
21 RW 0x0 ZIP_FILTER_EN:
0 = NO
1 = YES
20 RW 0x0 ZIP_CHNG_INTR_EN:
0 = NO
1 = YES
19 RW 0x0 ZIP_ST_CHNG:
0 = NO
1 = YES

USB Complex
18 RO X ZIP:
0 = NO
1 = YES
17 RW 0x0 USBON_RPU:
0 = NO
1 = YES
16 RW 0x0 USBON_RPD:
0 = NO
1 = YES
15 RW 0x0 USBOP_RPU:
0 = NO
1 = YES
14 RW 0x0 USBOP_RPD:
0 = NO
1 = YES
13 RW 0x0 OP_I_SRC_EN:
0 = NO
1 = YES
12 RW 0x0 ON_SRC_EN:
0 = NO
1 = YES
11 RW 0x0 ON_SINK_EN:
0 = NO
1 = YES
10 RW 0x0 OP_SRC_EN:
0 = NO
1 = YES
9 RW 0x0 OP_SINK_EN:
0 = NO
1 = YES
8 RW 0x0 VDAT_DET_FILTER_EN:
0 = NO
1 = YES
7 RW 0x0 VDAT_DET_CHNG_INTR_EN:
0 = NO
1 = YES
6 RW 0x0 VDAT_DET_ST_CHNG:
0 = NO
1 = YES
5 RO X VDAT_DET:
0 = NO
1 = YES
4 RW 0x0 VDCD_DET_FILTER_EN:
0 = NO
1 = YES
3 RW 0x0 VDCD_DET_CHNG_INTR_EN:
0 = NO
1 = YES
2 RW 0x0 VDCD_DET_ST_CHNG:
0 = NO
1 = YES
1 RO X VDCD_DET:
0 = NO
1 = YES

USB Complex
0 RW 0x1 PD_CHG:
0 = NO
1 = YES
Offset: 0x24 | Read/Write: R/W | Reset: 0x0000000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx0xxxx)
DIV_DET_EN:
4 RW 0x0 0 = NO
1 = YES
VOP_DIV2P7_DET:
3 RO X 0 = NO
1 = YES
VOP_DIV2P0_DET:
2 RO X 0 = NO
1 = YES
VON_DIV2P7_DET:
1 RO X 0 = NO
1 = YES
VON_DIV2P0_DET:
0 RO X 0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES

USB Complex

0 = NO
1 = YES
22 RO X ZIN:
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
18 RO X ZIP:
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
5 RO X VDAT_DET:
0 = NO
USB Complex

1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
1 RO X VDCD_DET:
0 = NO
1 = YES
0 RW 0x1 PD_CHG:
0 = NO
1 = YES
Offset: 0x2c | Read/Write: R/W | Reset: 0x0000000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx0xxxx)
DIV_DET_EN:
4 RW 0x0 0 = NO
1 = YES
VOP_DIV2P7_DET:
3 RO X 0 = NO
1 = YES
VOP_DIV2P0_DET:
2 RO X 0 = NO
1 = YES
VON_DIV2P7_DET:
1 RO X 0 = NO
1 = YES
VON_DIV2P0_DET:
0 RO X 0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES

USB Complex
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
22 RO X ZIN:
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
18 RO X ZIP:
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES

USB Complex
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
5 RO X VDAT_DET:
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
0 = NO
1 = YES
1 RO X VDCD_DET:
0 = NO
1 = YES
0 RW 0x1 PD_CHG:
0 = NO
1 = YES
19.13.12.14 PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0
Offset: 0x34 | Read/Write: R/W | Reset: 0x0000000X (0bxxxxxxxxxxxxxxxxxxxxxxxxxxx0xxxx)
DIV_DET_EN:
4 RW 0x0 0 = NO
1 = YES
VOP_DIV2P7_DET:
3 RO X 0 = NO
1 = YES
VOP_DIV2P0_DET:
2 RO X 0 = NO
1 = YES
VON_DIV2P7_DET:
1 RO X 0 = NO
1 = YES
VON_DIV2P0_DET:
0 RO X 0 = NO
1 = YES
19.13.12.15 XUSB_PADCTL_USB2_BATTERY_CHRG_BIASPAD_0
Offset: 0x38 | Read/Write: R/W | Reset: 0x0000XXXX (0bxxxxxxxxxxx00000000xxxxxx00x00x0)

USB Complex
20 RW 0x0 ID_OVERRIDE:
0 = NO
1 = YES
19:18 RW 0x0 ID_SOURCE_SELECT:

0 = NO_OVERRIDE
1 = GPIO
2 = VBUS_OVERRIDE
17 RW 0x0 VBUS_OVERRIDE:
0 = NO
1 = YES
16:15 RW 0x0 VBUS_SOURCE_SELECT:

0 = NO_OVERRIDE
1 = GPIO
2 = VBUS_OVERRIDE
14 RW 0x0 ID_CONNECT_CHNG_INTR_EN:
0 = NO
1 = YES
13 RW 0x0 ID_CONNECT_ST_CHNG:
0 = NO
1 = YES
12 RO X ID_CONNECT_STATUS:
0 = NO
1 = YES
11 RO X IDDIG_C:
0 = NO
1 = YES
10 RO X IDDIG_B:
0 = NO
1 = YES
9 RO X IDDIG_A:
0 = NO
1 = YES
8 RO X IDDIG:
0 = NO
1 = YES
6 RW 0x0 VBUS_VLD_CHNG_INTR_EN:
0 = NO
1 = YES
5 RW 0x0 VBUS_VLD_ST_CHNG:
0 = NO
1 = YES
4 RO X VBUS_VLD:
0 = NO
1 = YES
3 RW 0x0 OTG_VBUS_SESS_VLD_CHNG_INTR_EN:
0 = NO
1 = YES
2 RW 0x0 OTG_VBUS_SESS_VLD_ST_CHNG:
0 = NO
1 = YES
1 RO X OTG_VBUS_SESS_VLD:
0 = NO
1 = YES
0 RW 0x0 PD_OTG:
0 = NO

USB Complex

1 = YES
19.13.12.16 XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0
Offset: 0x3c | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxx00000000000)
10:0 0x0 TDCD_DBNC
19.13.12.17 XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0
USB3/PCIE PLL0 control signals: One set per PLL
Offset: 0x40 | Read/Write: R/W | Reset: 0x3X2X0000 (0bxx11xxx0xx10xxx000000x0000000000)
29:28 RW 0x3 PLL1_REFCLK_NDIV
27 RO X PLL1_LOCKDET
24 RW 0x0 PLL1_MODE
16 RW 0x0 PLL0_MODE
15:12 RW 0x0 REFCLK_SEL
11 RW 0x0 REFCLK_TERM100
9 RW 0x0 PLL_CKBUFPD_OVR
8 RW 0x0 PLL_CKBUFPD_M
7 RW 0x0 PLL_CKBUFPD_BL
6 RW 0x0 PLL_CKBUFPD_BR
5 RW 0x0 PLL_CKBUFPD_TL
4 RW 0x0 PLL_CKBUFPD_TR
3 RW 0x0 PLL_PWR_OVRD
2 RW 0x0 PLL_EMULATION_RST_
1 RW 0x0 PLL_RST_
0 RW 0x0 PLL_IDDQ
Offset: 0x44 | Read/Write: R/W | Reset: 0xXX880037 (0bxxxxxxxx100010000x00000000110111)
31:24 RO X PLL_MISC_OUT
23:20 RW 0x8 PLL1_CP_CNTL
15 RW 0x0 PLL_BYPASS_EN
13 RW 0x0 PLL_EMULATION_ON

USB Complex
12 RW 0x0 TCLKOUT_EN
11:8 RW 0x0 TCLKOUT_SEL
7 RW 0x0 XDIGCLK4P5_EN
6 RW 0x0 REFCLKBUF_EN
5 RW 0x1 TXCLKREF_EN
4 RW 0x1 TXCLKREF_SEL
3 RW 0x0 XDIGCLK_EN
2:0 RW 0x7 XDIGCLK_SEL
Offset: 0x48 | Read/Write: R/W | Reset: 0x0000XX0e (0b0000xx000000xx00x0xxxxxx0xx01110)
31:28 RW 0x0 PLL_TEMP_CNTL
25:20 RW 0x0 PLL_BW_CNTL
17:16 RW 0x0 PLL_BGAP_CNTL
15 RO X RCAL_DONE
14 RW 0x0 RCAL_RESET
12:8 RO X RCAL_VAL
7 RW 0x0 RCAL_BYPASS
4:0 RW 0xe RCAL_CODE
Offset: 0x4c | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxx000000000000)
11:0 0x0 PLL_MISC_CNTL
19.13.12.21 XUSB_PADCTL_IOPHY_USB3_PAD0_CTL_1_0
USB3 PADS: XUSB Static controls: Unit specific
Offset: 0x50 | Read/Write: R/W | Reset: 0x0000ec14 (0bxxxxxxxxx00000001110110000010100)
22:21 0x0 RX_DIV
20:19 0x0 TX_DIV
18:15 0x1 TX_DRV_CNTL
14:11 0xd TX_CMADJ
10:5 0x20 TX_AMP
4:3 0x2 RX_RATE
2:1 0x2 TX_RATE
0 0x0 RATE_MODE

USB Complex
Offset: 0x54 | Read/Write: R/W | Reset: 0x0000ec14 (0bxxxxxxxxx00000001110110000010100)
22:21 0x0 RX_DIV
20:19 0x0 TX_DIV
18:15 0x1 TX_DRV_CNTL
14:11 0xd TX_CMADJ
10:5 0x20 TX_AMP
4:3 0x2 RX_RATE
2:1 0x2 TX_RATE
0 0x0 RATE_MODE
31:24 0x24 CDR_CNTL
23:8 0x10 RX_EQ
7:4 0x0 RX_WANDER
3:2 0x0 RX_TERM_CNTL
1:0 0x0 TX_TERM_CNTL
31:24 0x24 CDR_CNTL
23:8 0x10 RX_EQ
7:4 0x0 RX_WANDER
3:2 0x0 RX_TERM_CNTL
1:0 0x0 TX_TERM_CNTL
15:0 0x0 EOM_CNTL
15:0 0x0 EOM_CNTL

USB Complex
31:0 0x0 DFE_CNTL
31:0 0x0 DFE_CNTL
19.13.12.29 XUSB_PADCTL_IOPHY_MISC_PAD_P0_CTL_1_0
USB3 PADS: Miscellaneous Dir Control: Common for all USB3/PCIE/SATA
USB3 PADS: Miscellaneous Ovrd: Common for all USB3/PCIE/SATA
Offset: 0x70 | Read/Write: R/W | Reset: 0x000aX330 (0bxxxx0000000010100xxx001100110000)
27 RW 0x0 RX_PWR_OVRD
26 RW 0x0 TX_PWR_OVRD
25 RW 0x0 RATE_MODE_OVRD
24 RW 0x0 RATE_MODE
23:22 RW 0x0 RX_DIV
21:20 RW 0x0 TX_DIV
19:18 RW 0x2 RX_RATE
17:16 RW 0x2 TX_RATE
15 RW 0x0 TX_RDET
13 RO X TX_STAT_PRESENT
12 RO X RX_STAT_IDLE
11 RW 0x0 RX_DATA_EN
10 RW 0x0 RX_DATA_READY
9:8 RW 0x3 RX_SLEEP
7 RW 0x0 TX_DATA_EN
6 RW 0x0 TX_DATA_READY
5:4 RW 0x3 TX_SLEEP
3 RW 0x0 CKBUFPD_OVRD
2 RW 0x0 CKBUFPD
1 RW 0x0 IDDQ_OVRD
0 RW 0x0 IDDQ

USB Complex
24 RW 0x0 RATE_MODE
23:22 RW 0x0 RX_DIV
21:20 RW 0x0 TX_DIV
15 RW 0x0 TX_RDET
9:8 RW 0x3 RX_SLEEP
7 RW 0x0 TX_DATA_EN
5:4 RW 0x3 TX_SLEEP
2 RW 0x0 CKBUFPD
1 RW 0x0 IDDQ_OVRD
0 RW 0x0 IDDQ
Offset: 0x78 | Read/Write: R/W | Reset: 0xX0000000 (0bxx000x00xxxxxxxxxx00000000000000)
31:30 RO X SPARE_OUT
29:28 RW 0x0 SPARE_IN
27 RW 0x0 TEST_EN
25 RW 0x0 PRBS_CHK_EN
24 RW 0x0 PRBS_ERROR
13 RW 0x0 RX_CDR_RESET
12 RW 0x0 TX_SYNC
11 RW 0x0 FED_LOOP
10:8 RW 0x0 TX_DATA_MODE
7 RW 0x0 FEA_LOOP
6:4 RW 0x0 FEA_MODE
3 RW 0x0 NEA_LOOP
2 RW 0x0 NED_LOOP

USB Complex
1:0 RW 0x0 NED_MODE
Offset: 0x7c | Read/Write: R/W | Reset: 0xX0000000 (0bxx000x00xxxxxxxxxx00000000000000)
27 RW 0x0 TEST_EN
12 RW 0x0 TX_SYNC
11 RW 0x0 FED_LOOP
7 RW 0x0 FEA_LOOP
6:4 RW 0x0 FEA_MODE
3 RW 0x0 NEA_LOOP
2 RW 0x0 NED_LOOP
1:0 RW 0x0 NED_MODE
Offset: 0x80 | Read/Write: R/W | Reset: 0x00040200 (0b000000000000010000000010xxxx0000)
31:20 0x0 CDR_TEST
19 0x0 RX_IDLE_MODE_OVRD
18 0x1 RX_IDLE_MODE
17 0x0 RX_IDLE_BYP
16 0x0 TX_RDET_BYP
15:14 0x0 RX_IDLE_T
13:12 0x0 TX_RDET_T
11:8 0x2 TX_SEL_LOAD
3:0 0x0 MISC_CNTL
31:20 0x0 CDR_TEST

USB Complex
18 0x1 RX_IDLE_MODE
17 0x0 RX_IDLE_BYP
16 0x0 TX_RDET_BYP
15:14 0x0 RX_IDLE_T
13:12 0x0 TX_RDET_T
3:0 0x0 MISC_CNTL
Offset: 0x88 | Read/Write: R/W | Reset: 0xXX000XX0 (0bx100x0000000xxxxxx0000x000x0xxxx)
31 RO X AUX_RX_STAT_IDLE
30 RW 0x1 AUX_RX_IDLE_MODE
29 RW 0x0 AUX_RX_IDLE_EN
28 RW 0x0 AUX_RX_TERM_EN
27 RO X AUX_TX_STAT_PRESENT
26 RW 0x0 AUX_TX_RDET_CLK_EN
25 RW 0x0 AUX_TX_RDET_EN
24 RW 0x0 AUX_TX_TERM_EN
23 RW 0x0 AUX_MODE_OVRD
22 RW 0x0 AUX_HOLD_EN
21 RW 0x0 AUX_IDDQ_OVRD
20 RW 0x0 AUX_IDDQ
13 RW 0x0 TX_BYP_OVRD
12 RW 0x0 RX_BYP_MODE
11 RW 0x0 RX_BYP_EN
10 RW 0x0 RX_BYP_DIR
9 RO X RX_BYP_IN
8 RW 0x0 RX_BYP_OUT
7 RW 0x0 TX_BYP_EN
6 RW 0x0 TX_BYP_DIR
5 RO X TX_BYP_IN
4 RW 0x0 TX_BYP_OUT
Offset: 0x8c | Read/Write: R/W | Reset: 0xXX000XX0 (0bx100x0000000xxxxxx00000x00x0xxxx)

USB Complex
20 RW 0x0 AUX_IDDQ
11 RW 0x0 RX_BYP_EN
9 RW 0x0 RX_BYP_OUT
8 RO X RX_BYP_IN
7 RW 0x0 TX_BYP_EN
6 RW 0x0 TX_BYP_DIR
5 RO X TX_BYP_IN
4 RW 0x0 TX_BYP_OUT
Offset: 0x90 | Read/Write: R/W | Reset: 0x0000X0XX (0bxxxxxxxxxxxxxxxxxxxxxxx00xx00xx0)
17:12 RO X RX_QEYE_OUT
8 RW 0x0 RX_QEYE_EN
7 RW 0x0 EOM_EN
5 RO X EOM_TRAIN_DONE
4 RW 0x0 EOM_TRAIN_EN
3 RW 0x0 DFE_RESET
1 RO X DFE_TRAIN_DONE
0 RW 0x0 DFE_TRAIN_EN
Offset: 0x94 | Read/Write: R/W | Reset: 0x0000X0XX (0bxxxxxxxxxxxxxxxxxxxxxxx00xx00xx0)

USB Complex
8 RW 0x0 RX_QEYE_EN
7 RW 0x0 EOM_EN
3 RW 0x0 DFE_RESET
Offset: 0x98 | Read/Write: R/W | Reset: 0xXX000000 (0bxxxxxxxx000000000000000000000000)
31:24 RO X MISC_OUT
23:16 RW 0x0 MISC_OUT_SEL
15:0 RW 0x0 MISC_TEST
Offset: 0x9c | Read/Write: R/W | Reset: 0xXX000000 (0bxxxxxxxx000000000000000000000000)
31:24 RO X MISC_OUT
19.13.12.41 XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0
USB2 OTG, HSIC, ICUSB Control Settings
OTGPAD0, CTL0 static settings

One set per pad (except the BIAS pad which is just one set)
Offset: 0xa0 | Read/Write: R/W | Reset: 0x003808a0 (0bxxxxxxxx001110000000100010100000)
23 0x0 LSBIAS_SEL
22 0x0 DISCON_DETECT_METHOD
21 0x1 PD_ZI
20 0x1 PD2
19 0x1 PD
18 0x0 TERM_EN
17:16 0x0 LS_FSLEW
15:14 0x0 LS_RSLEW
13:12 0x0 FS_SLEW

USB Complex
11:6 0x22 HS_SLEW
5:0 0x20 HS_CURR_LEVEL

23 0x0 LSBIAS_SEL
21 0x1 PD_ZI
20 0x1 PD2
19 0x1 PD
18 0x0 TERM_EN
17:16 0x0 LS_FSLEW
15:14 0x0 LS_RSLEW
13:12 0x0 FS_SLEW
11:6 0x22 HS_SLEW

23 0x0 LSBIAS_SEL
21 0x1 PD_ZI
20 0x1 PD2
19 0x1 PD
18 0x0 TERM_EN
17:16 0x0 LS_FSLEW
15:14 0x0 LS_RSLEW
13:12 0x0 FS_SLEW
11:6 0x22 HS_SLEW

USB Complex

Offset: 0xac | Read/Write: R/W | Reset: 0x00000004 (0bxxxxxxxxxxxxxxxxxxx0000000000100)
12:11 0x0 RPU_RANGE_ADJ
10:9 0x0 HS_IREF_CAP
8:7 0x0 SPARE
6:3 0x0 TERM_RANGE_ADJ
2 0x1 PD_DR
1 0x0 PD_DISC_FORCE_POWERUP
0 0x0 PD_CHRP_FORCE_POWERUP

Offset: 0xb0 | Read/Write: R/W | Reset: 0x00000004 (0bxxxxxxxxxxxxxxxxxxx0000000000100)
8:7 0x0 SPARE
2 0x1 PD_DR

Offset: 0xb4 | Read/Write: R/W | Reset: 0x00000004 (0bxxxxxxxxxxxxxxxxxxx0000000000100)
8:7 0x0 SPARE
2 0x1 PD_DR
19.13.12.47 XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0
Offset: 0xb8 | Read/Write: R/W | Reset: 0x00003000 (0bxxxxxxxxxxxxxxx00011000000000000)
USB Complex
16:14 0x0 ADJRPU
13 0x1 PD_TRK
12 0x1 PD
11:9 0x0 TERM_OFFSET
8:7 0x0 VBUS_LEVEL
6:5 0x0 HS_CHIRP_LEVEL
4:2 0x0 HS_DISCON_LEVEL
1:0 0x0 HS_SQUELCH_LEVEL
19.13.12.48 XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
BIASPAD, CTL1 static settings

Offset: 0xbc | Read/Write: RO | Reset: 0xXXXXXXXX (0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)
31:16 X TCTRL
15:0 X RCTRL
19.13.12.49 XUSB_PADCTL_HSIC_PAD0_CTL_0_0
HSIC PAD0, CTL0

19:16 0x0 HSIC_OPT
15:12 0x0 TX_SLEWN
11:8 0x0 TX_SLEWP
7:4 0x8 TX_RTUNEN
3:0 0x8 TX_RTUNEP
HSIC PAD1, CTL0

19:16 0x0 HSIC_OPT
15:12 0x0 TX_SLEWN
11:8 0x0 TX_SLEWP
7:4 0x8 TX_RTUNEN
3:0 0x8 TX_RTUNEP

USB Complex
HSIC PAD0, CTL1

Offset: 0xc8 | Read/Write: R/W | Reset: 0x000001b8 (0bxxxxxxxxxxxxxxxxxxxxx00110111000)
10 0x0 RPU_STROBE
9 0x0 RPU_DATA
8 0x1 RPD_STROBE
7 0x1 RPD_DATA
6 0x0 LPBK
5 0x1 PD_ZI
4 0x1 PD_RX
3 0x1 PD_TRX
2 0x0 PD_TX
1 0x0 IDDQ
0 0x0 AUTO_TERM_EN
HSIC PAD1, CTL1

Offset: 0xcc | Read/Write: R/W | Reset: 0x000001b8 (0bxxxxxxxxxxxxxxxxxxxxx00110111000)
10 0x0 RPU_STROBE
9 0x0 RPU_DATA
8 0x1 RPD_STROBE
7 0x1 RPD_DATA
6 0x0 LPBK
5 0x1 PD_ZI
4 0x1 PD_RX
3 0x1 PD_TRX
2 0x0 PD_TX
1 0x0 IDDQ
0 0x0 AUTO_TERM_EN
HSIC PAD0, CTL2

Offset: 0xd0 | Read/Write: R/W | Reset: 0xXXXX0022 (0bxxxxxxxxxxxxxxxxxxxxxxxx00100010)
31:16 RO X CALIOUT

USB Complex
7:4 RW 0x2 RX_STROBE_TRIM
3:0 RW 0x2 RX_DATA_TRIM
HSIC PAD1, CTL2

Offset: 0xd4 | Read/Write: R/W | Reset: 0xXXXX0022 (0bxxxxxxxxxxxxxxxxxxxxxxxx00100010)
31:16 RO X CALIOUT
7:4 RW 0x2 RX_STROBE_TRIM
3:0 RW 0x2 RX_DATA_TRIM
19.13.12.55 XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
ULPI LINK and NULL Mode Trimmer Controls

Offset: 0xd8 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxx0000000000xxxxx00x00000000)
25 0x0 CTL_SEL_DEL1
24 0x0 CTL_SEL_DEL0
23:16 0x0 CTL_TRIM_VAL
10 0x0 DAT_SEL_DEL1
9 0x0 DAT_SEL_DEL0
7:0 0x0 DAT_TRIM_VAL
19.13.12.56 XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
Offset: 0xdc | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxx00000xxx00000)
12:8 0x0 NULL_LBKCLK_TRIM_VAL
4:0 0x0 NULL_CLKOUT_TRIM_VAL
19.13.12.57 XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0
HSIC STROBE Trimmer Control

Offset: 0xe0 | Read/Write: R/W | Reset: 0x00000001 (0bxxxxxxxxxxxxxxxxxxxxxxxxxx000001)
5:0 0x1 STRB_TRIM_VAL

USB Complex
19.13.12.58 XUSB_PADCTL_WAKE_CTRL_0
Wake Logic AUX RDET CLK FORCE ON

Offset: 0xe4 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxxxxxxxx000000)
5 0x0 LANE_S0_FORCE_TX_RDET_CLK_ENABLE
4 0x0 LANE_P4_FORCE_TX_RDET_CLK_ENABLE
1 0x0 LANE_P 1_FORCE_TX_RDET_CLK_ENABLE
0 0x0 LANE_P 0_FORCE_TX_RDET_CLK_ENABLE
19.13.12.59 XUSB_PADCTL_PM_SPARE_0
PAD Macro Spare Bits

Offset: 0xe8 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxxxxxxxxxxxxxxx000000000000)
11 0x0 HSIC_PM_SPARE_BIT3
7 0x0 ULPI_PM_SPARE_BIT3
3 0x0 OTG_PM_SPARE_BIT3
USB3 Pads : Miscellaneous Direction Control : The following lanes are only used by PCIe
USB3 Pads : Miscellaneous Ovrd : The following lanes are only used by PCIe
Offset: 0xec | Read/Write: R/W | Reset: 0x000aX330 (0bxxxx0000000010100xxx001100110000)
24 RW 0x0 RATE_MODE

USB Complex
23:22 RW 0x0 RX_DIV
21:20 RW 0x0 TX_DIV
15 RW 0x0 TX_RDET
9:8 RW 0x3 RX_SLEEP
7 RW 0x0 TX_DATA_EN
5:4 RW 0x3 TX_SLEEP
2 RW 0x0 CKBUFPD
1 RW 0x0 IDDQ_OVRD
0 RW 0x0 IDDQ
Offset: 0xf0 | Read/Write: R/W | Reset: 0x000aX330 (0bxxxx0000000010100xxx001100110000)
24 RW 0x0 RATE_MODE
23:22 RW 0x0 RX_DIV
21:20 RW 0x0 TX_DIV
15 RW 0x0 TX_RDET

USB Complex
9:8 RW 0x3 RX_SLEEP
7 RW 0x0 TX_DATA_EN
5:4 RW 0x3 TX_SLEEP
2 RW 0x0 CKBUFPD
1 RW 0x0 IDDQ_OVRD
0 RW 0x0 IDDQ
Offset: 0xf4 | Read/Write: R/W | Reset: 0x000aX330 (0bxxxx0000000010100xxx001100110000)
24 RW 0x0 RATE_MODE
23:22 RW 0x0 RX_DIV
21:20 RW 0x0 TX_DIV
15 RW 0x0 TX_RDET
9:8 RW 0x3 RX_SLEEP
7 RW 0x0 TX_DATA_EN
5:4 RW 0x3 TX_SLEEP
2 RW 0x0 CKBUFPD
1 RW 0x0 IDDQ_OVRD
0 RW 0x0 IDDQ

USB Complex
Offset: 0xf8 | Read/Write: R/W | Reset: 0xX0000000 (0bxx000x00xxxxxxxxxx00000000000000)
27 RW 0x0 TEST_EN
12 RW 0x0 TX_SYNC
11 RW 0x0 FED_LOOP
7 RW 0x0 FEA_LOOP
6:4 RW 0x0 FEA_MODE
3 RW 0x0 NEA_LOOP
2 RW 0x0 NED_LOOP
1:0 RW 0x0 NED_MODE
Offset: 0xfc | Read/Write: R/W | Reset: 0xX0000000 (0bxx000x00xxxxxxxxxx00000000000000)
27 RW 0x0 TEST_EN
12 RW 0x0 TX_SYNC
11 RW 0x0 FED_LOOP
7 RW 0x0 FEA_LOOP
6:4 RW 0x0 FEA_MODE
3 RW 0x0 NEA_LOOP
2 RW 0x0 NED_LOOP
1:0 RW 0x0 NED_MODE

USB Complex
Offset: 0x100 | Read/Write: R/W | Reset: 0xX0000000 (0bxx000x00xxxxxxxxxx00000000000000)
27 RW 0x0 TEST_EN
12 RW 0x0 TX_SYNC
11 RW 0x0 FED_LOOP
7 RW 0x0 FEA_LOOP
6:4 RW 0x0 FEA_MODE
3 RW 0x0 NEA_LOOP
2 RW 0x0 NED_LOOP
1:0 RW 0x0 NED_MODE
31:20 0x0 CDR_TEST
18 0x1 RX_IDLE_MODE
17 0x0 RX_IDLE_BYP
16 0x0 TX_RDET_BYP
15:14 0x0 RX_IDLE_T
13:12 0x0 TX_RDET_T
3:0 0x0 MISC_CNTL
31:20 0x0 CDR_TEST

USB Complex
18 0x1 RX_IDLE_MODE
17 0x0 RX_IDLE_BYP
16 0x0 TX_RDET_BYP
15:14 0x0 RX_IDLE_T
13:12 0x0 TX_RDET_T
3:0 0x0 MISC_CNTL
Offset: 0x10c | Read/Write: R/W | Reset: 0x00040200 (0b000000000000010000000010xxxx0000)
31:20 0x0 CDR_TEST
18 0x1 RX_IDLE_MODE
17 0x0 RX_IDLE_BYP
16 0x0 TX_RDET_BYP
15:14 0x0 RX_IDLE_T
13:12 0x0 TX_RDET_T
3:0 0x0 MISC_CNTL

USB Complex
20 RW 0x0 AUX_IDDQ
11 RW 0x0 RX_BYP_EN
9 RO X RX_BYP_IN
8 RW 0x0 RX_BYP_OUT
7 RW 0x0 TX_BYP_EN
6 RW 0x0 TX_BYP_DIR
5 RO X TX_BYP_IN
4 RW 0x0 TX_BYP_OUT
20 RW 0x0 AUX_IDDQ
11 RW 0x0 RX_BYP_EN
9 RW 0x0 RX_BYP_OUT
8 RO X RX_BYP_IN

USB Complex
7 RW 0x0 TX_BYP_EN
6 RW 0x0 TX_BYP_DIR
5 RO X TX_BYP_IN
4 RW 0x0 TX_BYP_OUT
20 RW 0x0 AUX_IDDQ
11 RW 0x0 RX_BYP_EN
9 RW 0x0 RX_BYP_OUT
8 RO X RX_BYP_IN
7 RW 0x0 TX_BYP_EN
6 RW 0x0 TX_BYP_DIR
5 RO X TX_BYP_IN
4 RW 0x0 TX_BYP_OUT
Offset: 0x11c | Read/Write: R/W | Reset: 0x000XX0XX (0bxxxxxxxxxxxxxxxxxxxxxxx00xx00xx0)

USB Complex
8 RW 0x0 RX_QEYE_EN
7 RW 0x0 EOM_EN
3 RW 0x0 DFE_RESET
Offset: 0x120 | Read/Write: R/W | Reset: 0x000XX0XX (0bxxxxxxxxxxxxxxxxxxxxxxx00xx00xx0)
8 RW 0x0 RX_QEYE_EN
7 RW 0x0 EOM_EN
3 RW 0x0 DFE_RESET
8 RW 0x0 RX_QEYE_EN
7 RW 0x0 EOM_EN
3 RW 0x0 DFE_RESET

USB Complex
31:24 RO X MISC_OUT
31:24 RO X MISC_OUT
31:24 RO X MISC_OUT
19.13.12.78 XUSB_PADCTL_USB3_PAD_MUX_0
Offset: 0x134 | Read/Write: R/W | Reset: 0x08000000 (0bxxxx100000000000xxxxxxxxx0000000)
SATA_PAD_LANE0:
0 = PCIE
27:26 0x2 1 = USB3_SS
2 = SATA
3 = RESERVED
PCIE_PAD_LANE4:
0 = PCIE
25:24 0x0 1 = USB3_SS
2 = SATA
3 = RESERVED
PCIE_PAD_LANE3:
0 = PCIE
23:22 0x0 1 = USB3_SS
2 = SATA
3 = RESERVED
PCIE_PAD_LANE2:
0 = PCIE
21:20 0x0 1 = USB3_SS
2 = SATA
3 = RESERVED
PCIE_PAD_LANE1:
19:18 0x0 0 = PCIE
1 = USB3_SS
2 = SATA
USB Complex

3 = RESERVED
PCIE_PAD_LANE0:
0 = PCIE
17:16 0x0 1 = USB3_SS
2 = SATA
3 = RESERVED
FORCE_SATA_PAD_IDDQ_DISABLE_MASK0:
6 0x0 0 = NOT_DISABLED
1 = DISABLED
FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4:
1 = DISABLED
1 = DISABLED
1 = DISABLED
1 = DISABLED
1 = DISABLED
FORCE_PCIE_PAD_IDDQ_DISABLE:
1 = DISABLED
19.13.12.79 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0
USB3/SATA PLL0 control signals : One set per PLL
Offset: 0x138 | Read/Write: R/W | Reset: 0x3X3X0000 (0bxx11xxx0xx11xxx000000x0000000000)
24 RW 0x0 PLL1_MODE
16 RW 0x0 PLL0_MODE
15:12 RW 0x0 REFCLK_SEL
11 RW 0x0 REFCLK_TERM100
9 RW 0x0 PLL_CKBUFPD_OVR
8 RW 0x0 PLL_CKBUFPD_M
7 RW 0x0 PLL_CKBUFPD_BL

USB Complex
6 RW 0x0 PLL_CKBUFPD_BR
5 RW 0x0 PLL_CKBUFPD_TL
4 RW 0x0 PLL_CKBUFPD_TR
3 RW 0x0 PLL_PWR_OVRD
2 RW 0x0 PLL_EMULATION_RST_
1 RW 0x0 PLL_RST_
0 RW 0x0 PLL_IDDQ
Offset: 0x13c | Read/Write: R/W | Reset: 0xXX441020 (0bxxxxxxxx010001000x01000000100000)
31:24 RO X PLL_MISC_OUT
15 RW 0x0 PLL_BYPASS_EN
13 RW 0x0 PLL_EMULATION_ON
12 RW 0x1 TCLKOUT_EN
11:8 RW 0x0 TCLKOUT_SEL
7 RW 0x0 XDIGCLK4P5_EN
6 RW 0x0 REFCLKBUF_EN
5 RW 0x1 TXCLKREF_EN
4 RW 0x0 TXCLKREF_SEL
3 RW 0x0 XDIGCLK_EN
2:0 RW 0x0 XDIGCLK_SEL
Offset: 0x140 | Read/Write: R/W | Reset: 0x0000XX80 (0b0000xx000000xx00x0xxxxxx1xx00000)
31:28 RW 0x0 PLL_TEMP_CNTL
25:20 RW 0x0 PLL_BW_CNTL
17:16 RW 0x0 PLL_BGAP_CNTL
15 RO X RCAL_DONE
14 RW 0x0 RCAL_RESET
12:8 RO X RCAL_VAL
7 RW 0x1 RCAL_BYPASS

USB Complex
4:0 RW 0x0 RCAL_CODE
11:0 0x0 PLL_MISC_CNTL
19.13.12.83 XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_1_0
Miscellaneous controls for USB3/SATA pads
24 RW 0x0 RATE_MODE
23:22 RW 0x0 RX_DIV
21:20 RW 0x0 TX_DIV
15 RW 0x0 TX_RDET
9:8 RW 0x3 RX_SLEEP
7 RW 0x0 TX_DATA_EN
5:4 RW 0x3 TX_SLEEP
2 RW 0x0 CKBUFPD
1 RW 0x0 IDDQ_OVRD
0 RW 0x0 IDDQ
Offset: 0x14c | Read/Write: R/W | Reset: 0xX0000000 (0bxx000x00xxxxxxxxxx00000000000000)

USB Complex
27 RW 0x0 TEST_EN
12 RW 0x0 TX_SYNC
11 RW 0x0 FED_LOOP
7 RW 0x0 FEA_LOOP
6:4 RW 0x0 FEA_MODE
3 RW 0x0 NEA_LOOP
2 RW 0x0 NED_LOOP
1:0 RW 0x0 NED_MODE
31:20 0x0 CDR_TEST
18 0x1 RX_IDLE_MODE
17 0x0 RX_IDLE_BYP
16 0x0 TX_RDET_BYP
15:14 0x0 RX_IDLE_T
13:12 0x0 TX_RDET_T
3:0 0x0 MISC_CNTL

USB Complex
20 RW 0x0 AUX_IDDQ
11 RW 0x0 RX_BYP_EN
9 RO X RX_BYP_IN
8 RW 0x0 RX_BYP_OUT
7 RW 0x0 TX_BYP_EN
6 RW 0x0 TX_BYP_DIR
5 RO X TX_BYP_IN
4 RW 0x0 TX_BYP_OUT
8 RW 0x0 RX_QEYE_EN
7 RW 0x0 EOM_EN
3 RW 0x0 DFE_RESET
31:24 RO X MISC_OUT

USB Complex
19.13.13 XUSB PCI Config Registers

19.13.13.1 T_XUSB_CFG_0
Offset: 0x00 | Read/Write: R
Bits Reset R/W Description
31:16 FA3h R T_XUSB_CFG_0_DEVICE_ID_UNIT:

FA3h: DEVICE_ID_UNIT_XUSB (default)
15:0 10DEh R T_XUSB_CFG_0_VENDOR_ID:

10DEh: VENDOR_ID_NVIDIA (default)
19.13.13.2 T_XUSB_CFG_1
FPCI Configuration Register

Offset: 0x04 | Read/Write: R/W
26:25 0 R T_XUSB_CFG_1_DEVSEL_TIMING:
0h: DEVSEL_TIMING_FAST (default)
1h: DEVSEL_TIMING_MEDIUM
2h: DEVSEL_TIMING_SLOW
31 0 R T_XUSB_CFG_1_DETECTED_PERR:
0h: DETECTED_PERR_NOT_ACTIVE (default)
1h: DETECTED_PERR_ACTIVE
1h: DETECTED_PERR_CLEAR
30 0 R T_XUSB_CFG_1_SIGNALED_SERR:
0h: SIGNALED_SERR_NOT_ACTIVE (default)
1h: SIGNALED_SERR_ACTIVE
1h: SIGNALED_SERR_CLEAR
18:11 0 R Reserved
29 0 R T_XUSB_CFG_1_RECEIVED_MASTER:
0h: RECEIVED_MASTER_NO_ABORT (default)
1h: RECEIVED_MASTER_ABORT
1h: RECEIVED_MASTER_CLEAR
28 0 R T_XUSB_CFG_1_RECEIVED_TARGET:
0h: RECEIVED_TARGET_NO_ABORT (default)
1h: RECEIVED_TARGET_ABORT
1h: RECEIVED_TARGET_CLEAR
27 0 R T_XUSB_CFG_1_SIGNALED_TARGET:
0h: SIGNALED_TARGET_NO_ABORT (default)
1h: SIGNALED_TARGET_ABORT
1h: SIGNALED_TARGET_CLEAR
24 0 R T_XUSB_CFG_1_MASTER_DATA_PERR:
0h: MASTER_DATA_PERR_NOT_ACTIVE (default)
1h: MASTER_DATA_PERR_ACTIVE
1h: MASTER_DATA_PERR_CLEAR
23 1h R T_XUSB_CFG_1_FAST_BACK2BACK:
0h: FAST_BACK2BACK_INCAPABLE
1h: FAST_BACK2BACK_CAPABLE (default)

USB Complex
22 0 R Reserved
21 1h R T_XUSB_CFG_1_66MHZ:
0h: 66MHZ_INCAPABLE
1h: 66MHZ_CAPABLE (default)
20 1h R T_XUSB_CFG_1_CAPLIST:
0h: CAPLIST_NOT_PRESENT
1h: CAPLIST_PRESENT (default)
19 None R T_XUSB_CFG_1_INTR_STATUS:
0h: INTR_STATUS_0
1h: INTR_STATUS_1
10 0 R/W T_XUSB_CFG_1_INTR_DISABLE:
0h: INTR_DISABLE_ON (default)
1h: INTR_DISABLE_OFF
9 0 R T_XUSB_CFG_1_BACK2BACK:
0h: BACK2BACK_DISABLED (default)
1h: BACK2BACK_ENABLED
8 0 R T_XUSB_CFG_1_SERR:
0h: SERR_DISABLED (default)
1h: SERR_ENABLED
7 0 R T_XUSB_CFG_1_STEP:
0h: STEP_DISABLED (default)
1h: STEP_ENABLED
6 0 R T_XUSB_CFG_1_PERR:
0h: PERR_DISABLED (default)
1h: PERR_ENABLED
5 0 R T_XUSB_CFG_1_PALETTE_SNOOP:
0h: PALETTE_SNOOP_DISABLED (default)
1h: PALETTE_SNOOP_ENABLED
4 0 R T_XUSB_CFG_1_WRITE_AND_INVAL:
0h: WRITE_AND_INVAL_DISABLED (default)
1h: WRITE_AND_INVAL_ENABLED
3 0 R T_XUSB_CFG_1_SPECIAL_CYCLE:
0h: SPECIAL_CYCLE_DISABLED (default)
1h: SPECIAL_CYCLE_ENABLED
2 0 R/W T_XUSB_CFG_1_BUS_MASTER:
0h: BUS_MASTER_DISABLED (default)
1h: BUS_MASTER_ENABLED
1 0 R/W T_XUSB_CFG_1_MEMORY_SPACE:
0h: MEMORY_SPACE_DISABLED (default)
1h: MEMORY_SPACE_ENABLED
0 0 R/W T_XUSB_CFG_1_IO_SPACE:
0h: IO_SPACE_DISABLED (default)
1h: IO_SPACE_ENABLED
19.13.13.3 T_XUSB_CFG_2
PCI Revision ID and Class Code Register

31:24 Ch R T_XUSB_CFG_2_BASE_CLASS:
The CLASS_CODE bits identify the generic function of the device and (in some cases) a specific
register-level programming interface. The register is broken into three byte-size fields. The upper
byte (at offset 0BH) is a base class code which broadly classifies the type of function the device

USB Complex

performs. The middle-byte (at offset 0BH) is a sub-class code which identifies more specifically
the function of the device. The lower byte (at offset 09H) identifies a specific register-level
programming interface (if any) so that device independent software can interact with the device.
The Class Code and Revision ID are defined by parameters per block.
Ch: BASE_CLASS_SBC (default)
23:16 3h R T_XUSB_CFG_2_SUB_CLASS:
3h: SUB_CLASS_XUSB (default)
15:8 30h R T_XUSB_CFG_2_PROG_IF:

30h: PROG_IF_XHCI (default)
7:0 A1h R T_XUSB_CFG_2_REVISION_ID:

The REVISION_ID bits specify a device specific revision identifier. The value is chosen by the
vendor. Zero is an acceptable value. This field should be viewed as a vendor defined extension
to the DEVICE_ID.
A1h: REVISION_ID_VAL (default)
A1h: REVISION_ID_A01
19.13.13.4 T_XUSB_CFG_3
PCI Configuration Register

Offset: 0x0C | Read/Write: R
31:24 0 R Reserved
23 0 R T_XUSB_CFG_3_HEADER_TYPE_FUNC:
0h: HEADER_TYPE_FUNC_SINGLE (default)
1h: HEADER_TYPE_FUNC_MULTI
22:16 0 R T_XUSB_CFG_3_HEADER_TYPE_DEVICE:
The HEADER_TYPE bits identify the layout of the bytes 10h through 3Fh in configuration space
and also whether or not the device contains multiple functions. Bit 7 in this register is used to
identify a multi-function device. If the bit is 0, then the device is single function. If the bit is 1, then
the device has multiple functions. Bits 6 through 0 specify the layout of bytes 10h through 3Fh.
The LATENCY_TIMER and HEADER_TYPE are defined by parameters per block.
0h: HEADER_TYPE_DEVICE_NON_BRIDGE (default)
1h: HEADER_TYPE_DEVICE_P2P_BRIDGE
15:11 0 R T_XUSB_CFG_3_LATENCY_TIMER:
The LATENCY_TIMER bits contain, in units of PCI bus clocks, the value of the Latency Timer for
this PCI bus master. This register must be implemented as writable by any master that can burst
more than two data phases. This register may be implemented as read-only for devices that burst
two or fewer data phases, but the hardwired value must be limited to 16 or less. A typical
implementation would be to build the five high-order bits (leaving the bottom three as read-only),
resulting in a timer granularity of eight clocks. At reset, the register should be set to 0 (if
programmable). LATENCY_TIMER bits are writable.
0h: LATENCY_TIMER_0_CLOCKS (default)
1h: LATENCY_TIMER_8_CLOCKS
1Eh: LATENCY_TIMER_240_CLOCKS
1Fh: LATENCY_TIMER_248_CLOCKS
10:8 0 R Reserved
7:0 0 R T_XUSB_CFG_3_CACHE_LINE_SIZE:
0h: CACHE_LINE_SIZE_0 (default)
20h: CACHE_LINE_SIZE_32
40h: CACHE_LINE_SIZE_64
19.13.13.5 T_XUSB_CFG_4


USB Complex
31:15 0 R/W T_XUSB_CFG_4_BASE_ADDRESS:

The BASE_ADDRESS bits contain the base address of the device. The number of upper bits that
a device actually implements depends on how much of the address space the device will respond
to. A device that wants a 1 MB memory address space (using a 32-bit base address register)
would build the top 12 bits of the address register, hardwiring the other bits to 0. Power-up
software can determine how much address space the device required by writing a value of all 1's
to the register and then reading the value back. The device will return 0's in all don't-care address
bits, effectively specifying the address space required.
0h: BASE_ADDRESS_DEFAULT (default)
14:4 0 R T_XUSB_CFG_4_BAR_SIZE_32KB:
0h: BAR_SIZE_32KB_RSVD (default)
3 1h R T_XUSB_CFG_4_PREFETCHABLE:
0h: PREFETCHABLE_NOT
1h: PREFETCHABLE_MERGABLE (default)
2:1 2h R T_XUSB_CFG_4_ADDRESS_TYPE:
The ADDRESS_TYPE bits contain the type of the Base Address. It can be 32 bits, 20 bits, or 64
bits wide.
0h: ADDRESS_TYPE_32_BIT
2h: ADDRESS_TYPE_64_BIT (default)
0 0 R T_XUSB_CFG_4_SPACE_TYPE:
The SPACE_TYPE bit indicates whether the register maps into Memory or I/O space.
0h: SPACE_TYPE_MEMORY (default)
1h: SPACE_TYPE_IO
19.13.13.6 T_XUSB_CFG_5
31:0 0 R/W T_XUSB_CFG_5_BASE_ADDRESSHI:

0h: BASE_ADDRESSHI_DEFAULT (default)
19.13.13.7 T_XUSB_CFG_6
Offset: 0x18-0x28 | Read/Write: R
31:0 0 R T_XUSB_CFG_6_RSVD:
0h: RSVD_00 (default)
19.13.13.8 T_XUSB_CFG_11

The SUBSYSTEM_VENDOR_ID bits and SUBSYSTEM_ID bits are used to uniquely identify the add-in board or subsystem
where the device resides. When the device is on the motherboard, there is no serial ROM and the registers both initialize to
NONE. The motherboard BIOS must set the values of the Subsystem ID and Subsystem Vendor ID by writing the proper
values to the SUBSYSTEM_VENDOR_ID and SUBSYSTEM_ID bits in the PCI_T_16 register (NOT PCI_T_11).
Offset: 0x2c | Read/Write: R
31:16 0 R T_XUSB_CFG_11_SUBSYSTEM_ID:
0h: SUBSYSTEM_ID_NONE (default)
15:0 0 R T_XUSB_CFG_11_SUBSYSTEM_VENDOR_ID:
0h: SUBSYSTEM_VENDOR_ID_NONE (default)

USB Complex
19.13.13.9 T_XUSB_CFG_12

31:0 0 R T_XUSB_CFG_12_RESERVED:
0h: RESERVED_0 (default)
19.13.13.10 T_XUSB_CFG_13
PCI Capability Pointer Register

31:8 0 R Reserved
7:0 44h R T_XUSB_CFG_13_CAP_PTR:

The CAP_PTR bits indicate the offset into configuration space where the
capabilities list begins. This always points to 0x44 where at least the PCI-PM
registers are expected to reside.
44h: CAP_PTR_PMCAP
C0h: CAP_PTR_MSI
70h: CAP_PTR_MSIX
DCh: CAP_PTR_MMAP
44h: CAP_PTR_DEFAULT (default)
19.13.13.11 T_XUSB_CFG_14

31:0 0 R T_XUSB_CFG_14_RESERVED:
0h: RESERVED_0 (default)
19.13.13.12 T_XUSB_CFG_15

Offset: 0x3c | Read/Write: R/W
31:24 0 R T_XUSB_CFG_15_MAX_LAT:
The MAX_LAT bits contain the maximum time the device requires to gain
access to the CPI bus. This read-only register is used to specify the device's
desired settings for Latency Timer values. The value specifies a period of time in
units of 1/4 microseconds. Values of 0 indicate that the device has no major
requirements for the settings of Latency Timers. MAX_LAT is nonzero.
The INTR_PIN, MIN_GNT, and MAX_LAT are configurable per block.
For a 64-byte buffer with two 32-byte sections, the maximum tolerable latency
for the XHCI once a large XUSB ISO transaction has begun is about 23 µs. The
latency timer is hardwired to 20 µs. This value only applies in External PCI
operation.
0h: MAX_LAT_NO_REQUIREMENTS (default)
14h: MAX_LAT_5US
50h: MAX_LAT_20US

USB Complex
23:16 0 R T_XUSB_CFG_15_MIN_GNT:
The MIN_GNT bits contain the length of the burst period a device needs
assuming a clock rate of 33 MHz. This read-only register is used to specify the
device's desired settings for Latency Timer values. The value specifies a period
of time in units of 1/4 microsecond. Values of 0 indicate that the device has no
major requirements for the settings of Latency Timers. MIN_GNT is nonzero.
0h: MIN_GNT_NO_REQUIREMENTS (default)
1h: MIN_GNT_240NS
15:8 1h R T_XUSB_CFG_15_INTR_PIN:
The INTR_PIN bits contain the interrupt pin the device (or device function) uses.
A value of 1 corresponds to INTA#. A value of 2 corresponds to INTB#. A value
of 3 corresponds to INTC#. A value of 4 corresponds to INTD#. Devices (or
device functions) that do not use an interrupt pin must put a 0 in this register.
0h: INTR_PIN_NONE
1h: INTR_PIN_INTA (default)
2h: INTR_PIN_INTB
3h: INTR_PIN_INTC
4h: INTR_PIN_INTD
7:0 0 R/W T_XUSB_CFG_15_INTR_LINE:

The INTR_LINE bits contain the interrupt routing information. The register is
read/write and must be implemented by any device (or device function) that uses
an interrupt pin. POST software will write the routing information into this register
as it initializes and configures the system. The value in this register tells which
input of the system interrupt controller(s) the device's interrupt pin is connected
to. Device drivers and operating systems can use this information to determine
priority and vector information. INTR_LINE is initialized to 0xff (no connection) at
reset. Some PCI BIOS' cannot handle aliased INTR_LINEs. Some PCI BIOS'
cannot handle INTR_LINE initialized to 0xff.
0h: INTR_LINE_IRQ0 (default)
1h: INTR_LINE_IRQ1
Fh: INTR_LINE_IRQ15
FFh: INTR_LINE_UNKNOWN
19.13.13.13 T_XUSB_CFG_16
Backdoor register write for updating subsystem ID/vendor ID.
31:16 0 R/W T_XUSB_CFG_16_SUBSYSTEM_ID:

0h: SUBSYSTEM_ID_NONE (default)
15:0 0 R/W T_XUSB_CFG_16_SUBSYSTEM_VENDOR_ID:

0h: SUBSYSTEM_VENDOR_ID_NONE (default)
19.13.13.14 T_XUSB_CFG_17
31 1h R T_XUSB_CFG_17_D3CPME_SUPPORT:
1h: D3CPME_SUPPORT_YES
0h: D3CPME_SUPPORT_NO
30 1h R T_XUSB_CFG_17_D3HPME_SUPPORT:
1h: D3HPME_SUPPORT_YES
0h: D3HPME_SUPPORT_NO
29 0 R T_XUSB_CFG_17_D2PME_SUPPORT:
1h: D2PME_SUPPORT_YES
0h: D2PME_SUPPORT_NO
28 0 R T_XUSB_CFG_17_D1PME_SUPPORT:

USB Complex

27 1h R T_XUSB_CFG_17_D0PME_SUPPORT:
26 0 R T_XUSB_CFG_17_D2_SUPPORT:
0h: D2_SUPPORT_NO
1h: D2_SUPPORT_YES
25 0 R T_XUSB_CFG_17_D1_SUPPORT:
0h: D1_SUPPORT_NO
1h: D1_SUPPORT_YES
24:22 0 R T_XUSB_CFG_17_AUXCUR:
0h: AUXCUR_SELF
1h: AUXCUR_55MA
2h: AUXCUR_100MA
3h: AUXCUR_160MA
4h: AUXCUR_220MA
5h: AUXCUR_270MA
6h: AUXCUR_320MA
7h: AUXCUR_375MA
21 0 R T_XUSB_CFG_17_DSI:
0h: DSI_NONE
1h: DSI_NEEDED
20 0 R T_XUSB_CFG_17_RSVD:
0h: RSVD_0
19 0 R T_XUSB_CFG_17_PMECLK:
0h: PMECLK_NOT_REQUIRED
1h: PMECLK_REQUIRED
18:16 3h R T_XUSB_CFG_17_VER:
3h: VER_1P2
15:8 C0h R T_XUSB_CFG_17_NEXT_PTR:

C0h: NEXT_PTR_MSI
70h: NEXT_PTR_MSIX
DCh: NEXT_PTR_MMAP
0h: NEXT_PTR_NULL
C0h: NEXT_PTR_DEFAULT (default)
7:0 1h R T_XUSB_CFG_17_CAP:
1h: CAP_PCIPM
19.13.13.15 T_XUSB_CFG_18_PMCSR
31:24 0 R Reserved
23:16 0 R T_XUSB_CFG_18_PMCSR_BSE_RSVD:
0h: BSE_RSVD_00
15 0 RW1C T_XUSB_CFG_18_PMCSR_PMESTATUS:
0h: PMESTATUS_NOT_PENDING (default)
1h: PMESTATUS_PENDING
1h: PMESTATUS_CLEAR
14:13 0 R T_XUSB_CFG_18_PMCSR_DSCALE:
0h: DSCALE_INIT
12:9 0 R T_XUSB_CFG_18_PMCSR_DSEL:
0h: DSEL_INIT

USB Complex
8 0 R/W T_XUSB_CFG_18_PMCSR_PME:
1h: PME_ENABLE
0h: PME_DISABLE (default)
7:4 0 R T_XUSB_CFG_18_PMCSR_RSVD1:
0h: RSVD1_00
3 1h R T_XUSB_CFG_18_PMCSR_NSR:
1h: NSR_NORESET
0h: NSR_RESET
2 0 R T_XUSB_CFG_18_PMCSR_RSVD0:
0h: RSVD0_0
1:0 0 R/W T_XUSB_CFG_18_PMCSR_PWRSTATE:

0h: PWRSTATE_D0 (default)
1h: PWRSTATE_D1
2h: PWRSTATE_D2
3h: PWRSTATE_D3H
19.13.13.16 T_XUSB_CFG_24
XUSB XHCI Configuration Control

31:16 0 R Reserved
15:14 0 R T_XUSB_CFG_24_RSVDP:
0h: RSVDP_VALUE
13:8 20h R/W T_XUSB_CFG_24_FLADJ:

Frame Length Adjustment Register. This register is in the auxiliary power well.
This feature is used to adjust any offset from the clock source that generates the
clock that drives the SOF counter. When a new value is written into these six bits,
the length of the frame is adjusted. Its initial programmed value is system
dependent based on the accuracy of hardware USB clock and is initialized by
system BIOS. This register should only be modified when the HChalted bit in the
USBSTS register is a one. Changing value of this register while the host
controller is operating yields undefined results. It should not be reprogrammed by
USB system software unless the default or BIOS programmed values are
incorrect, or the system is restoring the register while returning from a suspended
state.
20h: FLADJ_VALUE (default)
7:0 30h R T_XUSB_CFG_24_SBRN:

Serial Bus Release Number Register. This register contains the release of the
Universal Serial Bus Specification with which this Universal Serial Bus Host
Controller module is compliant.
30h: SBRN_VALUE
19.13.13.17 T_XUSB_CFG_EMU_RSVD
MSIX is not part of Tegra K1 processors.
The PCIe and HT capabilities are not required. PCIe capability will be trapped by the emulation only IP - the emulation only IP
put the PCIe capability at 80h ~ BBh, and uses BCh ~ BFh, so these regions are reserved for the emulation only IP. (The
emulation only IP will mask the pointers to insert the PCIe capability to the config space of the unit.)
Offset: 0x80-0xBB | Read/Write: R/W
31:0 Unknown R/W T_XUSB_CFG_EMU_RSVD_FIELD

USB Complex
19.13.13.18 T_XUSB_MSI_CTRL
MSI Message Control and Capability Register B0h

MSI_CTRL is the main control register for MSI support.
Offset: 0xc0 | Read/Write: R/W
31:25 0 R Reserved
24 0 R T_XUSB_MSI_CTRL_VECTOR_MASK_CAP:
The VECTOR_MASK_CAP field indicates whether or not the controller supports
MSI-per-vector masking.
0h: VECTOR_MASK_CAP_DIS
1h: VECTOR_MASK_CAP_EN
0h: VECTOR_MASK_CAP_DEFAULT (default)
23 1h R T_XUSB_MSI_CTRL_64_ADDR_CAP:
The 64_ADDR_CAP field indicates whether or not the controller is capable of
generating a 64-bit message address. A value of 1 means the controller is
capable of generating a 64-bit message address.
0h: 64_ADDR_CAP_DIS
1h: 64_ADDR_CAP_EN
1h: 64_ADDR_CAP_DEFAULT (default)
22:20 0 R/W T_XUSB_MSI_CTRL_MULT_MSG_ENABLE:

System software writes to this field to indicate the number of allocated vectors
(less than or equal to the number of vectors requested). The number of vectors is
aligned as a power of two. When MSI is enabled, the controller will be allocated
at least one vector.
0h: MULT_MSG_ENABLE_1
0h: MULT_MSG_ENABLE_DEFAULT (default)
19:17 0 R T_XUSB_MSI_CTRL_MULT_MSG_CAP:
System software reads this field to determine the number of requested vectors.
The number of requested vectors must be aligned to a power of two. Values of 6
and 7 in this field are reserved.
0h: MULT_MSG_CAP_1
1h: MULT_MSG_CAP_2
2h: MULT_MSG_CAP_4
3h: MULT_MSG_CAP_8
4h: MULT_MSG_CAP_16
5h: MULT_MSG_CAP_32
0h: MULT_MSG_CAP_DEFAULT (default)
16 0 R/W T_XUSB_MSI_CTRL_MSI_ENABLE:
The MSI_ENABLE field enables the MSI capability. If MSI_ENABLE is written to
a 1, the controller is permitted to use MSI to request service and is prohibited
from using the legacy interrupt. System configuration software sets this bit to
enable MSI.
A device driver is prohibited from writing this bit to mask the controller's service
request.
If this bit is written to a 0, the controller is prohibited from using MSI to request
service.
0h: MSI_ENABLE_OFF
1h: MSI_ENABLE_ON
0h: MSI_ENABLE_DEFAULT (default)
15:8 E0h R T_XUSB_MSI_CTRL_NEXT_PTR:

The NEXT_PTR field identifies the next item in the capabilities list. It is a read-
only field.
70h: NEXT_PTR_MSIX
DCh: NEXT_PTR_MMAP
44h: NEXT_PTR_PMCAP

USB Complex

0h: NEXT_PTR_NULL
E0h: NEXT_PTR_MAILBOX
E0h: NEXT_PTR_DEFAULT (default)
7:0 5h R T_XUSB_MSI_CTRL_CAP_ID:
The CAP_ID field identifies this capability block as the MSI capability block. This
is read-only as 0x5.
5h: CAP_ID_MSI (default)
19.13.13.19 T_XUSB_MSI_ADDR1
MSI Message Address Register 84h

MSI_ADDR1 specifies the lower 32 bits to which an MSI memory write transaction should occur.
31:2 0 R/W T_XUSB_MSI_ADDR1_MSG_ADDR:

System-specified message address. When MSI is enabled, this field specifies
the Dword-aligned address for the MSI memory write transaction.
0h: MSG_ADDR_DEFAULT (default)
1:0 0 R Reserved
19.13.13.20 T_XUSB_MSI_ADDR2
MSI Message Upper Address Register 88h

MSI_ADDR2 specifies the upper 32 bits to which an MSI memory write transaction should occur.
31:0 0 R/W T_XUSB_MSI_ADDR2_MSG_ADDR:

System-specified message address. When MSI is enabled, this field specifies the upper 32 bits of
the address for the MSI memory write transaction. The contents of this register only apply when
T_XUSB_CFG_MSI_CTRL_64_ADDR_CAP bit is set.
0h: MSG_ADDR_DEFAULT (default)
19.13.13.21 T_XUSB_MSI_DATA
MSI Message Data Register 8Ch

The MSI_DATA register contains the system-specified message.
Offset: 0xcc | Read/Write: R/W
31:16 0 R Reserved
15:0 0 R/W T_XUSB_MSI_DATA_MSG_DATA:

System-specified message When MSI is enabled, the message data is driven onto the lower 16
bits of the MSI memory write.
The MULT_MSG_ENABLE field in configuration register 80h specifies the number of low-order
message data bits that the XHCI is permitted to modify to generate its system software allocated
vectors.
0h: MSG_DATA_DEFAULT (default)

USB Complex
19.13.14 XUSB PCIe PADCTL REFCLK Configuration Registers
19.13.14.1 NV_PROJ__PCIE2_PADS_REFCLK_CFG0
Bits Reset Description
31:28 0h NV_PROJ__PCIE2_PADS_REFCLK_CFG0_REFCLK1_DRVI
0h: NV_PROJ__PCIE2_PADS_REFCLK_CFG0_REFCLK1_DRVI_DEFAULT
27:24 0h NV_PROJ__PCIE2_PADS_REFCLK_CFG0_REFCLK1_PREDI
0h: NV_PROJ__PCIE2_PADS_REFCLK_CFG0_REFCLK1_PREDI_DEFAULT
23 0h NV_PROJ__PCIE2_PADS_REFCLK_CFG0_REFCLK1_E_TERM
0h: NV_PROJ__PCIE2_PADS_REFCLK_CFG0_REFCLK1_E_TERM_DEFAULT
22:18 0h NV_PROJ__PCIE2_PADS_REFCLK_CFG0_REFCLK1_TERM
0h: NV_PROJ__PCIE2_PADS_REFCLK_CFG0_REFCLK1_TERM_DEFAULT
19.13.14.2 NV_PROJ__PCIE2_PADS_REFCLK_CFG1
Offset: 0xcc | Read/Write: R/W
Bits Reset Description
Control for reference current on IBIAS outputs of PEX CLK COMP pad.
REF[2:0] IBIAS current output
000 50 µA
001 75 µa
010 100 µA
011 125 µA
100 150 µA
101 200 µA
110 250 µA
111 300 µA
19.13.15 XUSB Mailbox Registers
19.13.15.1 T_XUSB_CFG_ARU_MAILBOX_CAP
Offset: 0xe0 | Read/Write: R/W | Reset: 0xXXXXXXXX (0b00000000000000000000000000000000)

USB Complex
31:24 0 R/W T_XUSB_CFG_ARU_MAILBOX_CAP_RSVD:

0h: MAILBOX_CAP_RSVD_INIT (default)
23:16 14h RW T_XUSB_CFG_ARU_MAILBOX_CAP_LENGTH:

14h: MAILBOX_CAP_LENGTH_INIT (default)
15:8 0 RW T_XUSB_CFG_ARU_MAILBOX_CAP_NEXTPTR
0h: MAILBOX_CAP_NEXTPTR_NULL
0h: MAILBOX_CAP_NEXTPTR_INIT (default)
7:0 9h RW T_XUSB_CFG_ARU_MAILBOX_CAP_ID:
9h: MAILBOX_CAP_ID_INIT (default)
19.13.15.2 T_XUSB_CFG_ARU_MAILBOX_CMD
31 0 R/W T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN:
0h: MAILBOX_CMD_INT_EN_INIT (default)
30 0 RW T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_XHCI:
0h: MAILBOX_CMD_DEST_XHCI_INIT (default)
29 0 RW T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI:
0h: MAILBOX_CMD_DEST_SMI_INIT (default)
28 0 RW T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_PME:
0h: MAILBOX_CMD_DEST_PME_INIT (default)
27 0 RW T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON:
0h: MAILBOX_CMD_DEST_FALCON_INIT (default)
26:0 0 RW T_XUSB_CFG_ARU_MAILBOX_CMD_RSVD:
0h: MAILBOX_CMD_RSVD_INIT (default)
19.13.15.3 T_XUSB_CFG_ARU_MAILBOX_DATA_IN
31:0 0 R/W T_XUSB_CFG_ARU_MAILBOX_DATA_IN_MSG:

0h: MAILBOX_DATA_IN_MSG_INIT (default)
19.13.15.4 T_XUSB_CFG_ARU_MAILBOX_DATA_OUT
Offset: 0xec | Read/Write: R/W | Reset: 0xXXXXXXXX (0b00000000000000000000000000000000)
31:0 0 R/W T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_MSG:

0h: MAILBOX_DATA_OUT_MSG_INIT (default)
19.13.15.5 T_XUSB_CFG_ARU_MAILBOX_OWNER
Offset: 0xf0 | Read/Write: R/W | Reset: 0xXXXXXXXX (0b00000000000000000000000000000000)
31:8 0 R/W T_XUSB_CFG_ARU_MAILBOX_ OWNER_RSVD:

0h: MAILBOX_OWNER_RSVD_INIT (default)
7:0 0 RW T_XUSB_CFG_ARU_MAILBOX_ OWNER_ID:

0h: MAILBOX_OWNER_ID_INIT (default)

USB Complex
19.13.16 XUSB CSB Registers
19.13.16.1 XUSB_CSB_MEMPOOL_ILOAD_ATTR_0
L2IMEMOP Static Configuration Register

Offset: 0x0101a00 | Read/Write: R/W | Reset: 0b000xxxxxxxxx00000000000000000000
TC
31 RW 0x0
0: TC_DEFAULT
NS
30 RW 0x0
0: NS_DEFAULT
RO
29 RW 0x0
0: RO_DEFAULT
SIZE
19:8 RW 0x0
0: SIZE_DEFAULT
RSVD
7:0 RO 0x0
0: RSVD_DEFAULT
19.13.16.2 XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_0

Offset: 0x0101a04 | Read/Write: R/W | Reset: 0b00000000000000000000000000000000
31:8 RW 0x0 RSVD

0: RSVD_DEFAULT
7:0 RO 0x0 SRC_ADDR

0: SRC_ADDR_DEFAULT
19.13.16.3 XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_0

Offset: 0x0101a08 | Read/Write: R/W | Reset: 0b000000000000000000000000000000000
7:0 0x0 SRC_ADDR

0: SRC_ADDR_DEFAULT
19.13.16.4 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_0
L2IMEMOP Operational Register

Offset: 0x0101a10 | Read/Write: R/W | Reset: 0b0000000xxxxx00000000000000000000
31:24 RW 0x0 SRC_COUNT

0: SRC_COUNT_DEFAULT
19:8 RW 0x0 SRC_OFFSET

0: SRC_OFFSET_DEFAULT
7:0 RO 0x0 RSVD

USB Complex

0: RSVD_DEFAULT
19.13.16.5 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_0
L2IMEMOP Operational Register

L2IMEMop Action encodings
bit[0] : 1=> RESULT, 0=> NO RESULT
bit[1] : 1=> OPTIMIZED, 0=> UNOPTIMIZED
bit[7:4] 0001 => LOAD_LOCKED
0010 => UNLOCK
0100 => INVALIDATE_ALL
0101 => QUERY_INDEX
0110 => QUERY_SPACE
Offset: 0x0101a14 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxx000000000000000000
31:24 RW X ACTION
0x10: L2IMEM_LOAD_LOCKED
0x11: L2IMEM_LOAD_LOCKED_RESULT
0x20: L2IMEM_UNLOCK
0x21: L2IMEM_UNLOCK_RESULT
0x22: L2IMEM_UNLOCK_OPTIMIZED
0x23: L2IMEM_UNLOCK_OPTIMIZED_RESULT
0x40: L2IMEM_INVALIDATE_ALL
0x41: L2IMEM_INVALIDATE_ALL_RESULT
0x50: L2IMEM_QUERY_INDEX_RESULT
0x60: L2IMEM_QUERY_SPACE_RESULT
0xFF: WAITFENCE_RESULT
17:8 RW 0x0 DEST_INDEX

0: DEST_INDEX_DEFAULT
7:0 RO 0x0 RSVD

0: RSVD_DEFAULT
19.13.16.6 XUSB_CSB_MEMPOOL_APMAP_0
Aperture Programming Register

Offset: 0x010181c | Read/Write: R/W | Reset: 0b1xxxxxxxxxxx0xxxxxxxxxxxxxx00xxxxx000
31 0x1 BOOTPATH
1: BOOTPATH_DEFAULT
24 0x0 XREQ_READ
0: XREQ_READ_DEFAULT
9:8 0x0 XMAP

0: XMAP_A
1: XMAP_B
2: XMAP_C

USB Complex
2:0 0x0 FDDMA

0: FDDMA_A
1: FDDMA_B
2: FDDMA_C
3: FDDMA_D
4: FDDMA_E
19.13.17 XUSB Falcon Registers
19.13.17.1 FALCON_CPUCTL_0
Bit Reset R/W Description
5 X RO STOPPED: This bit indicates whether the CPU is currently in the stopped state. The Falcon processor will exit this state if
a 1 is written to the STARTCPU bit, or if an interrupt arrives on one of its two inputs and the corresponding IE bit in CSW is
set
0: STOPPED_FALSE
1: STOPPED_TRUE
4 X RO HALTED: This bit indicates whether the CPU is currently in the halted state. The Falcon processor can only exit this state
when a 1 is written to the STARTCPU bit.
0: HALTED_FALSE
1: HALTED_TRUE
3 X WO HRESET: Setting HRESET to true will apply a hard reset. This bit will auto-clear and setting to false has no effect.
0: HRESET_FALSE
1: HRESET_TRUE
2 X WO SRESET: Setting SRESET to true will apply a soft reset. This bit will auto-clear and setting to false has no effect.
0: SRESET_FALSE
1: SRESET_TRUE
1 X WO STARTCPU: Setting STARTCPU to true will start CPU execution while in a HALTED state. If a start request is still
pending, setting to false cancel the start request. Writing any value has no effect while the CPU is running.
0: STARTCPU_FALSE
1: STARTCPU_TRUE
0 X WO IINVAL: Setting IINVAL to true causes all blocks in IMEM except block 0 to be marked as INVALID. This bit will auto-clear
and setting to false has no effect.
0: IINVAL_FALSE
1: IINVAL_TRUE
19.13.17.2 FALCON_BOOTVEC_0
The BOOTVEC register stores the initial execution start address of the CPU when it is first started after a reset.
31:0 0x0 VEC

0: VEC_INIT
19.13.17.3 FALCON_DMACTL_0
Offset: 0x10c | Read/Write: R/W | Reset: 0b0000000000000000000000000xxxxxxx1
7 X RO SECURE_STAT
6:3 X RO DMAQ_NUM: Indicates the valid request number at the DMA request queue
2 X RO IMEM_SCRUBBING:

USB Complex

0: Indicates scrubbing is done. For a non-secure Falcon, this value is always 0.
1: Indicates secure scrubber is pending and scrubbing IMEM, any access to IMEM will be blocked until scrubbing is done
0: IMEM_SCRUBBING_DONE
1: IMEM_SCRUBBING_PENDING
1 X RO DMEM_SCRUBBING:
0: Indicates scrubbing is done. For a non-secure Falcon, this value is always 0.
1: Indicates secure scrubber is pending and scrubbing DMEM, any access to DMEM will be blocked until scrubbing is
done
0: DMEM_SCRUBBING_DONE
1: DMEM_SCRUBBING_PENDING
0 0x1 RW REQUIRE_CTX: When REQUIRE_CTX is set to true, a valid context must be loaded before any DMA request can be
serviced. Pending requests without a valid current context remain pending, and do not prevent the engine from reporting
idle. When this bit is set to false, DMA requests are serviced regardless of the current context. Note that once a request is
issued, it must complete before the engine will be able to report idle, as needed for example to process WFI context switch
requests.
0:REQUIRE_CTX_FALSE
1: REQUIRE_CTX_TRUE
1: REQUIRE_CTX_INIT
19.13.17.4 FALCON_IMFILLRNG1_0
IMFILLRNG1 indicates tag values for the low and high end of the PC range to be auto-filled. The PC range is [tag_lo<<8 ..
tag_hi<<8+255].
If the user enables the auto-fill feature and leaves IMFILLRNG1 as zero, instruction 0x0~0x0ff always works as auto-fill range.
31:16 0x0 TAG_HI

0: TAG_HI_INIT
15:0 0x0 TAG_LO

TAG_LO_INIT
19.13.17.5 FALCON_IMFILLCTL_0
7:0 0x0 NBLOCKS

0: NBLOCKS_INIT
19.13.18 XUSB XHCI Registers

19.13.18.1 T_XUSB_XHCI_CAP_REG0
31:16 Unknown R T_XUSB_XHCI_CAP_REG0_HCIVERSION:

100h: HCIVERSION_INIT
15:8 Unknown R T_XUSB_XHCI_CAP_REG0_RSVD:

0h: RSVD_00
7:0 Unknown R T_XUSB_XHCI_CAP_REG0_CAPLENGTH:

20h: CAPLENGTH_INIT

USB Complex
19.13.18.2 T_XUSB_XHCI_CAP_HCSPARAMS1
31:24 Unknown R T_XUSB_XHCI_CAP_HCSPARAMS1_MAXPORTS:

10h: MAXPORTS_INIT
23 0 R Reserved
22:19 Unknown R T_XUSB_XHCI_CAP_HCSPARAMS1_RSVD0:

0h: RSVD0_00
18:8 Unknown R T_XUSB_XHCI_CAP_HCSPARAMS1_MAXINTRS:

1h: MAXINTRS_INIT
T_XUSB_XHCI_CAP_HCSPARAMS1_MAXSLOTS:
7:0 Unknown R
FFh: MAXSLOTS_INIT
31:27 Unknown R T_XUSB_XHCI_CAP_HCSPARAMS2_MAXSPBLO:

0h: MAXSPBLO_INIT
26 Unknown R T_XUSB_XHCI_CAP_HCSPARAMS2_SPR:
1h: SPR_TRUE
0h: SPR_FALSE
25:21 Unknown R T_XUSB_XHCI_CAP_HCSPARAMS2_MAXSPBHI:

0h: MAXSPBHI_INIT
20:8 Unknown R T_XUSB_XHCI_CAP_HCSPARAMS2_RSVD:

0h: RSVD_00
7:4 Unknown R T_XUSB_XHCI_CAP_HCSPARAMS2_ERST_MAX:

Fh: ERST_MAX_INIT
T_XUSB_XHCI_CAP_HCSPARAMS2_IST:
3:0 Unknown R
8h: IST_INIT
31:16 Unknown R T_XUSB_XHCI_CAP_HCSPARAMS3_U2LAT:

40h: U2LAT_INIT
15:8 Unknown R T_XUSB_XHCI_CAP_HCSPARAMS3_RSVD:

0h: RSVD_00
T_XUSB_XHCI_CAP_HCSPARAMS3_U1LAT:
7:0 Unknown R
2h: U1LAT_INIT
19.13.18.5 T_XUSB_XHCI_CAP_HCCPARAMS
31:16 Unknown R T_XUSB_XHCI_CAP_HCCPARAMS_XECP:

180h: XECP_USBLEGSUP
184h: XECP_SUPPROT_USB3
187h: XECP_SUPPROT_USB2

USB Complex
15:12 Unknown R T_XUSB_XHCI_CAP_HCCPARAMS_MAXPSASIZE:

Fh: MAXPSASIZE_INIT
11:9 Unknown R T_XUSB_XHCI_CAP_HCCPARAMS_RSVD:

0h: RSVD_00
8 Unknown R T_XUSB_XHCI_CAP_HCCPARAMS_PAE:
1h: PAE_TRUE
0h: PAE_FALSE
7 Unknown R T_XUSB_XHCI_CAP_HCCPARAMS_NSS:
1h: NSS_TRUE
0h: NSS_FALSE
6 Unknown R T_XUSB_XHCI_CAP_HCCPARAMS_LTC:
1h: LTC_TRUE
0h: LTC_FALSE
5 Unknown R T_XUSB_XHCI_CAP_HCCPARAMS_LHRC:
1h: LHRC_TRUE
0h: LHRC_FALSE
4 Unknown R T_XUSB_XHCI_CAP_HCCPARAMS_PIND:
1h: PIND_TRUE
0h: PIND_FALSE
3 Unknown R T_XUSB_XHCI_CAP_HCCPARAMS_PPC:
1h: PPC_TRUE
0h: PPC_FALSE
2 Unknown R T_XUSB_XHCI_CAP_HCCPARAMS_CSZ:
1h: CSZ_64B
0h: CSZ_32B
1 Unknown R T_XUSB_XHCI_CAP_HCCPARAMS_BNC:
1h: BNC_TRUE
0h: BNC_FALSE
0 Unknown R T_XUSB_XHCI_CAP_HCCPARAMS_AC64:
1h: AC64_TRUE
0h: AC64_FALSE
19.13.18.6 T_XUSB_XHCI_CAP_DBOFF
31:2 Unknown R T_XUSB_XHCI_CAP_DBOFF_OFFSET:

300h: OFFSET_INIT
1:0 Unknown R T_XUSB_XHCI_CAP_DBOFF_RSVD:

0h: RSVD_00
19.13.18.7 T_XUSB_XHCI_CAP_RTSOFF
31:5 Unknown R T_XUSB_XHCI_CAP_RTSOFF_OFFSET:

40h: OFFSET_INIT
4:0 Unknown R T_XUSB_XHCI_CAP_RTSOFF_RSVD:

0h: RSVD_00
19.13.18.8 T_XUSB_XHCI_CAP_RSVD0
USB Complex
31:0 Unknown R T_XUSB_XHCI_CAP_RSVD0_F:

0h: F_00
19.13.18.9 T_XUSB_XHCI_OP_USBCMD
31:12 0 R T_XUSB_XHCI_OP_USBCMD_RSVD1:
0h: RSVD1_00 (default)
11 0 R/W T_XUSB_XHCI_OP_USBCMD_EU3S:
0h: EU3S_DISABLE (default)
1h: EU3S_ENABLE
10 0 R/W T_XUSB_XHCI_OP_USBCMD_EWE:
0h: EWE_DISABLE (default)
1h: EWE_ENABLE
9 0 RW1C T_XUSB_XHCI_OP_USBCMD_CRS:
0h: CRS_INIT (default)
1h: CRS_START
0h: CRS_NOOP
8 0 RW1C T_XUSB_XHCI_OP_USBCMD_CSS:
0h: CSS_INIT (default)
1h: CSS_START
0h: CSS_NOOP
7 0 R/W T_XUSB_XHCI_OP_USBCMD_LHCRST:
0h: LHCRST_NOT_PENDING (default)
1h: LHCRST_PENDING
1h: LHCRST_SET
6:4 0 R T_XUSB_XHCI_OP_USBCMD_RSVD0:
3 0 R/W T_XUSB_XHCI_OP_USBCMD_HSEE:
0h: HSEE_DISABLE (default)
1h: HSEE_ENABLE
2 0 R/W T_XUSB_XHCI_OP_USBCMD_INTE:
0h: INTE_DISABLE (default)
1h: INTE_ENABLE
1 0 R/W T_XUSB_XHCI_OP_USBCMD_HCRST:
0h: HCRST_NOT_PENDING (default)
1h: HCRST_PENDING
1h: HCRST_SET
0 0 R/W T_XUSB_XHCI_OP_USBCMD_RS:
0h: RS_STOP (default)
1h: RS_RUN
19.13.18.10 T_XUSB_XHCI_OP_USBSTS
31:13 0 R T_XUSB_XHCI_OP_USBSTS_RSVD2:
12 0 R T_XUSB_XHCI_OP_USBSTS_HCE:
0h: HCE_NO_ERROR (default)
1h: HCE_ERROR
11 1 R T_XUSB_XHCI_OP_USBSTS_CNR:

USB Complex

1h: CNR_NOT_READY (default)
0h: CNR_READY
10 0 RW1C T_XUSB_XHCI_OP_USBSTS_SRE:
0h: SRE_NOT_PENDING (default)
1h: SRE_PENDING
1h: SRE_CLEAR
9 0 R T_XUSB_XHCI_OP_USBSTS_RSS:
0h: RSS_NOT_PENDING (default)
1h: RSS_PENDING
8 0 R T_XUSB_XHCI_OP_USBSTS_SSS:
0h: SSS_NOT_PENDING (default)
1h: SSS_PENDING
7:5 0 R T_XUSB_XHCI_OP_USBSTS_RSVD1:
4 0 RW1C T_XUSB_XHCI_OP_USBSTS_PCD:
0h: PCD_NOT_PENDING (default)
1h: PCD_PENDING
1h: PCD_CLEAR
3 0 RW1C T_XUSB_XHCI_OP_USBSTS_EINT:
0h: EINT_NOT_PENDING (default)
1h: EINT_PENDING
1h: EINT_CLEAR
2 0 RW1C T_XUSB_XHCI_OP_USBSTS_HSE:
0h: HSE_NOT_PENDING (default)
1h: HSE_PENDING
1h: HSE_CLEAR
1 0 R T_XUSB_XHCI_OP_USBSTS_RSVD0:
0 1 R T_XUSB_XHCI_OP_USBSTS_HCH:
1h: HCH_HALTED (default)
0h: HCH_RUNNING
19.13.18.11 T_XUSB_XHCI_OP_PGSZ
31:16 0 R T_XUSB_XHCI_OP_PGSZ_RSVD0:
15:0 1 R T_XUSB_XHCI_OP_PGSZ_PAGESIZE:
1h: PAGESIZE_4K (default)
19.13.18.12 T_XUSB_XHCI_OP_DNCTRL
31:16 0 R Reserved
15 0 R/W T_XUSB_XHCI_OP_DNCTRL_N15:
0h: N15_DISABLE (default)
1h: N15_ENABLE
1h: N14_ENABLE

USB Complex
1h: N13_ENABLE
1h: N12_ENABLE
1h: N11_ENABLE
1h: N10_ENABLE
1h: N9_ENABLE
1h: N8_ENABLE
1h: N7_ENABLE
1h: N6_ENABLE
1h: N5_ENABLE
1h: N4_ENABLE
1h: N3_ENABLE
1h: N2_ENABLE
1h: N1_ENABLE
1h: N0_ENABLE
19.13.18.13 T_XUSB_XHCI_OP_CRCR0
31:6 0 W T_XUSB_XHCI_OP_CRCR0_CRPLO:
0h: CRPLO_INIT (default)
5:4 0 R T_XUSB_XHCI_OP_CRCR0_RSVD0:
3 0 R T_XUSB_XHCI_OP_CRCR0_CRR:
0h: CRR_STOPPED (default)
1h: CRR_RUNNING

USB Complex
2 0 RW1C T_XUSB_XHCI_OP_CRCR0_CA:
0h: CA_INIT (default)
1h: CA_ABORT
1 0 RW1C T_XUSB_XHCI_OP_CRCR0_CS:
0h: CS_INIT (default)
1h: CS_STOP
0 0 RW1C T_XUSB_XHCI_OP_CRCR0_RCS:
0h: RCS_0 (default)
1h: RCS_1
19.13.18.14 T_XUSB_XHCI_OP_CRCR1
31:0 0 W T_XUSB_XHCI_OP_CRCR1_CRPHI:
0h: CRPHI_INIT (default)
19.13.18.15 T_XUSB_XHCI_OP_DCBAAP0
31:6 0 R/W T_XUSB_XHCI_OP_DCBAAP0_DCBAAPLO:

0h: DCBAAPLO_INIT (default)
5:0 0 R T_XUSB_XHCI_OP_DCBAAP0_RSVD0:
19.13.18.16 T_XUSB_XHCI_OP_DCBAAP1
31:0 0 R/W T_XUSB_XHCI_OP_DCBAAP1_DCBAAPHI:

0h: DCBAAPHI_INIT (default)
19.13.18.17 T_XUSB_XHCI_OP_CONFIG
31:8 0 R T_XUSB_XHCI_OP_CONFIG_RSVD0:
7:0 0 R/W T_XUSB_XHCI_OP_CONFIG_MAXSLOTSEN:

0h: MAXSLOTSEN_INIT (default)
19.13.18.18 T_XUSB_XHCI_OP_PORTSC
Offset: 0x420 – 0x510 | Read/Write: R/W
31 0 R T_XUSB_XHCI_OP_PORTSC_WPR:
0h: WPR_NOT_PENDING (default)
1h: WPR_PENDING
1h: WPR_SET

USB Complex
30 0 R T_XUSB_XHCI_OP_PORTSC_DR:
0h: DR_FALSE (default)
1h: DR_TRUE
29:28 0 R T_XUSB_XHCI_OP_PORTSC_RSVD2:
27 0 R/W T_XUSB_XHCI_OP_PORTSC_WOE:
0h: WOE_DISABLED (default)
1h: WOE_ENABLED
26 0 R/W T_XUSB_XHCI_OP_PORTSC_WDE:
0h: WDE_DISABLED (default)
1h: WDE_ENABLED
25 0 R/W T_XUSB_XHCI_OP_PORTSC_WCE:
0h: WCE_DISABLED (default)
1h: WCE_ENABLED
24 0 R T_XUSB_XHCI_OP_PORTSC_CAS:
0h: CAS_INIT (default)
23 0 RW1C T_XUSB_XHCI_OP_PORTSC_CEC:
0h: CEC_NOT_PENDING (default)
1h: CEC_PENDING
1h: CEC_CLEAR
22 0 RW1C T_XUSB_XHCI_OP_PORTSC_PLC:
0h: PLC_NOT_PENDING (default)
1h: PLC_PENDING
1h: PLC_CLEAR
21 0 RW1C T_XUSB_XHCI_OP_PORTSC_PRC:
0h: PRC_NOT_PENDING (default)
1h: PRC_PENDING
1h: PRC_CLEAR
20 0 RW1C T_XUSB_XHCI_OP_PORTSC_OCC:
0h: OCC_NOT_PENDING (default)
1h: OCC_PENDING
1h: OCC_CLEAR
19 0 RW1C T_XUSB_XHCI_OP_PORTSC_WRC:
0h: WRC_NOT_PENDING (default)
1h: WRC_PENDING
1h: WRC_CLEAR
18 0 RW1C T_XUSB_XHCI_OP_PORTSC_PEC:
0h: PEC_NOT_PENDING (default)
1h: PEC_PENDING
1h: PEC_CLEAR
17 0 RW1C T_XUSB_XHCI_OP_PORTSC_CSC:
0h: CSC_NOT_PENDING (default)
1h: CSC_PENDING
1h: CSC_CLEAR
16 0 RW1C T_XUSB_XHCI_OP_PORTSC_LWS:
0h: LWS_DISABLED (default)
1h: LWS_ENABLED
15:14 0 R/W T_XUSB_XHCI_OP_PORTSC_PIC:

0h: PIC_OFF (default)
1h: PIC_AMBER
2h: PIC_GREEN
3h: PIC_UNDEFINED
13:10 0 R T_XUSB_XHCI_OP_PORTSC_PSPD:
0h: PSPD_UNDEFINED (default)
1h: PSPD_FS
2h: PSPD_LS
3h: PSPD_HS

USB Complex

4h: PSPD_SS
Fh: PSPD_UNKNOWN
9 1 R/W T_XUSB_XHCI_OP_PORTSC_PP:
0h: PP_OFF
1h: PP_ON (default)
8:5 4h RW1C T_XUSB_XHCI_OP_PORTSC_PLS:

0h: PLS_U0
1h: PLS_U1
2h: PLS_U2
3h: PLS_U3
4h: PLS_DISABLED (default)
5h: PLS_RXDETECT
6h: PLS_INACTIVE
7h: PLS_POLLING
8h: PLS_RECOVERY
9h: PLS_HOTRESET
Ah: PLS_COMPLIANCE
Bh: PLS_LOOPBACK
Fh: PLS_RESUME
0h: PLS_GOTO_U0
1h: PLS_GOTO_U1
2h: PLS_GOTO_U2
3h: PLS_GOTO_U3
4 0 R/W T_XUSB_XHCI_OP_PORTSC_PR:
0h: PR_NOT_PENDING (default)
1h: PR_PENDING
1h: PR_SET
3 0 R T_XUSB_XHCI_OP_PORTSC_OCA:
0h: OCA_FALSE (default)
1h: OCA_TRUE
2 0 R T_XUSB_XHCI_OP_PORTSC_RSVD0:
1 0 RW1C T_XUSB_XHCI_OP_PORTSC_PED:
0h: PED_DISABLED (default)
1h: PED_ENABLED
1h: PED_CLEAR
0 0 R T_XUSB_XHCI_OP_PORTSC_CCS:
0h: CCS_NODEV (default)
1h: CCS_DEV
19.13.18.19 T_XUSB_XHCI_OP_PORTPMSCSS
31:17 0 R T_XUSB_XHCI_OP_PORTPMSCSS_RSVD0:
16 0 R/W T_XUSB_XHCI_OP_PORTPMSCSS_FLA:
0h: FLA_INIT (default)
15:8 0 R/W T_XUSB_XHCI_OP_PORTPMSCSS_U2TIMEOUT:

0h: U2TIMEOUT_INIT (default)
7:0 0 R/W T_XUSB_XHCI_OP_PORTPMSCSS_U1TIMEOUT:

0h: U1TIMEOUT_INIT (default)
19.13.18.20 T_XUSB_XHCI_OP_PORTPMSCHS

USB Complex
31:28 0 R/W T_XUSB_XHCI_OP_PORTPMSCHS_TM:

0h: TM_DISABLE (default)
1h: TM_JSTATE
2h: TM_KSTATE
3h: TM_SE0NAK
4h: TM_PACKET
5h: TM_FORCEEN
Fh: TM_ERROR
27:17 0 R T_XUSB_XHCI_OP_PORTPMSCHS_RSVD0:
16 0 R/W T_XUSB_XHCI_OP_PORTPMSCHS_HLE:
0h: HLE_INIT (default)
15:8 0 R/W T_XUSB_XHCI_OP_PORTPMSCHS_L1DS:

0h: L1DS_INIT (default)
7:4 0 R/W T_XUSB_XHCI_OP_PORTPMSCHS_HIRD:

0h: HIRD_INIT (default)
3 0 R/W T_XUSB_XHCI_OP_PORTPMSCHS_RWE:
0h: RWE_DISABLED (default)
1h: RWE_ENABLED
2:0 0 R T_XUSB_XHCI_OP_PORTPMSCHS_L1S:
0h: L1S_INVLD (default)
1h: L1S_SUCCESS
2h: L1S_NYET
3h: L1S_STALL
4h: L1S_ERROR
19.13.18.21 T_XUSB_XHCI_OP_PORTLISC
Offset: 0x428 – 0x458 | Read/Write: R
31:16 0 R T_XUSB_XHCI_OP_PORTLISC_RSVD0:
15:0 0 R T_XUSB_XHCI_OP_PORTLISC_LEC:
0h: LEC_INIT (default)
19.13.18.22 T_XUSB_XHCI_OP_PORTHLPMC
Offset: 0x42c – 0x51c | Read/Write: R
13:10 0 R T_XUSB_XHCI_OP_PORTHLPMC_BESLD:
0h: BESLD_INIT (default)
9:2 0 R T_XUSB_XHCI_OP_ PORTHLPMC_L1_TIMEOUT:

0h: L1_TIMEOUT_INIT (default)
1:0 0 R T_XUSB_XHCI_OP_ PORTHLPMC_HIRDM:

0h: HIRDM_INIT (default)
19.13.18.23 T_XUSB_XHCI_EC_USBLEGSUP
31:25 0 R T_XUSB_XHCI_EC_USBLEGSUP_RSVD1:

USB Complex
24 0 R/W T_XUSB_XHCI_EC_USBLEGSUP_OSSEM:
0h: OSSEM_INIT (default)
23:17 0 R T_XUSB_XHCI_EC_USBLEGSUP_RSVD0:
16 0 R/W T_XUSB_XHCI_EC_USBLEGSUP_BIOSSEM:
0h: BIOSSEM_INIT (default)
15:8 4h R T_XUSB_XHCI_EC_USBLEGSUP_NEXT:
4h: NEXT_SUPPROT_USB3 (default)
7:0 1h R T_XUSB_XHCI_EC_USBLEGSUP_CAPID:
1h: CAPID_USBLEGSUP (default)
19.13.18.24 T_XUSB_XHCI_EC_USBLEGCTLSTS
31 0 RW1C T_XUSB_XHCI_EC_USBLEGCTLSTS_BAR:
0h: BAR_NOT_PENDING (default)
1h: BAR_PENDING
1h: BAR_CLEAR
30 0 RW1C T_XUSB_XHCI_EC_USBLEGCTLSTS_PCIC:
0h: PCIC_NOT_PENDING (default)
1h: PCIC_PENDING
1h: PCIC_CLEAR
29 0 RW1C T_XUSB_XHCI_EC_USBLEGCTLSTS_OSOC:
0h: OSOC_NOT_PENDING (default)
1h: OSOC_PENDING
1h: OSOC_CLEAR
28:21 0 R T_XUSB_XHCI_EC_USBLEGCTLSTS_RSVD3:
20 0 R T_XUSB_XHCI_EC_USBLEGCTLSTS_HSE:
0h: HSE_NOT_PENDING (default)
1h: HSE_PENDING
16 0 R T_XUSB_XHCI_EC_USBLEGCTLSTS_EVI:
0h: EVI_NOT_PENDING (default)
1h: EVI_PENDING
15 0 R/W T_XUSB_XHCI_EC_USBLEGCTLSTS_BAREN:
0h: BAREN_DISABLED (default)
1h: BAREN_ENABLED
14 0 R/W T_XUSB_XHCI_EC_USBLEGCTLSTS_PCIEN:
0h: PCIEN_DISABLED (default)
1h: PCIEN_ENABLED
13 0 R/W T_XUSB_XHCI_EC_USBLEGCTLSTS_OSOEN:
0h: OSOEN_DISABLED (default)
1h: OSOEN_ENABLED
4 0 R/W T_XUSB_XHCI_EC_USBLEGCTLSTS_HSEEN:
0h: HSEEN_DISABLED (default)
1h: HSEEN_ENABLED

USB Complex
0 0 R/W T_XUSB_XHCI_EC_USBLEGCTLSTS_SMIEN:
0h: SMIEN_DISABLED (default)
1h: SMIEN_ENABLED
19.13.18.25 T_XUSB_XHCI_EC_SUPPROT_USB3_0
31:24 3h R T_XUSB_XHCI_EC_SUPPROT_USB3_0_MAJORREV:
3h: MAJORREV_3 (default)
23:16 0 R T_XUSB_XHCI_EC_SUPPROT_USB3_0_MINORREV:
0h: MINORREV_0 (default)
15:8 4h R T_XUSB_XHCI_EC_SUPPROT_USB3_0_NEXT:
4h: NEXT_SUPPROT_USB2 (default)
7:0 2h R T_XUSB_XHCI_EC_SUPPROT_USB3_0_CAPID:
2h: CAPID_SUPPROT_USB3 (default)
31:0 20425355h R T_XUSB_XHCI_EC_SUPPROT_USB3_1_NAMESTR:

20425355h: NAMESTR_USB (default)
31:16 0 R T_XUSB_XHCI_EC_SUPPROT_USB3_2_RSVD0:
15:8 Unknown R T_XUSB_XHCI_EC_SUPPROT_USB3_2_PORTCNT:
7:0 1h R T_XUSB_XHCI_EC_SUPPROT_USB3_2_PORTOFS:
1h: PORTOFS_VAL (default)
31:0 0 R T_XUSB_XHCI_EC_SUPPROT_USB3_3_SLOTTYPE:
0h: SLOTTYPE_VAL (default)
31:24 2h R T_XUSB_XHCI_EC_SUPPROT_USB2_0_MAJORREV:
2h: MAJORREV_3 (default)
23:16 0h R T_XUSB_XHCI_EC_SUPPROT_USB2_0_MINORREV:
0h: MINORREV_0 (default)

USB Complex
15:8 4h R T_XUSB_XHCI_EC_SUPPROT_USB2_0_NEXT:
4h: NEXT_DBCAP (default)
7:0 2h R T_XUSB_XHCI_EC_SUPPROT_USB2_0_CAPID:
2h: CAPID_SUPPROT_USB3 (default)
31:0 20425355h R T_XUSB_XHCI_EC_SUPPROT_USB2_1_NAMESTR:

20425355h: NAMESTR_USB (default)
27:25 0 R T_XUSB_XHCI_EC_SUPPROT_USB2_2_MHD:
0h: MHD (default)
20 1 R T_XUSB_XHCI_EC_SUPPROT_USB2_2_BLC:
1h: BLC_TRUE (default)
19 1 R T_XUSB_XHCI_EC_SUPPROT_USB2_2_HLC:
1h: HLC_TRUE (default)
18 0 R T_XUSB_XHCI_EC_SUPPROT_USB2_2_IHI:
0h: IHI_TRUE (default)
17 0 R T_XUSB_XHCI_EC_SUPPROT_USB2_2_HSO:
0h: HSO_TRUE (default)
16 0 R T_XUSB_XHCI_EC_SUPPROT_USB2_2_RSVD0:
15:8 Unknown R T_XUSB_XHCI_EC_SUPPROT_USB2_2_PORTCNT:
7:0 Unknown R T_XUSB_XHCI_EC_SUPPROT_USB2_2_PORTOFS:
31:0 0 R T_XUSB_XHCI_EC_SUPPROT_USB2_3_SLOTTYPE:
0h: SLOTTYPE_VAL (default)
19.13.18.33 T_XUSB_XHCI_EC_DBCAP_DCID
31:21 0 R Reserved
20:16 1h R T_XUSB_XHCI_EC_DBCAP_DCID_DCERSTM:

USB Complex

1h: DCERSTM_VALUE (default)
15:8 0 R T_XUSB_XHCI_EC_DBCAP_DCID_NEXT:
0h: NEXT_NONE (default)
7:0 Ah R T_XUSB_XHCI_EC_DBCAP_DCID_CAPID:
Ah: CAPID_DBCAP (default)
19.13.18.34 T_XUSB_XHCI_EC_DBCAP_DCDB
Offset: 0x634 | Read/Write: W
31:16 0 R T_XUSB_XHCI_EC_DBCAP_DCDB_RSVD1:
15:8 0 W T_XUSB_XHCI_EC_DBCAP_DCDB_DBTARGET:
0h: DBTARGET_INIT (default)
7:0 0 R T_XUSB_XHCI_EC_DBCAP_DCDB_RSVD0:
19.13.18.35 T_XUSB_XHCI_EC_DBCAP_DCERSTSZ
31:16 0 R T_XUSB_XHCI_EC_DBCAP_DCERSTSZ_RSVD0:
15:0 0 R/W T_XUSB_XHCI_EC_DBCAP_DCERSTSZ_ERSTSZ:

0h: ERSTSZ_INIT (default)
19.13.18.36 T_XUSB_XHCI_EC_DBCAP_RSVD0
31:0 0 R T_XUSB_XHCI_EC_DBCAP_RSVD0_RSVD0:
19.13.18.37 T_XUSB_XHCI_EC_DBCAP_DCERSTBALO
31:4 0 R/W T_XUSB_XHCI_EC_DBCAP_DCERSTBALO_ADDRLO:

0h: ADDRLO_INIT (default)
3:0 0 R T_XUSB_XHCI_EC_DBCAP_DCERSTBALO_RSVD0:
19.13.18.38 T_XUSB_XHCI_EC_DBCAP_DCERSTBAHI
31:0 0 R/W T_XUSB_XHCI_EC_DBCAP_DCERSTBAHI_ADDRHI:

0h: ADDRHI_INIT (default)

USB Complex
19.13.18.39 T_XUSB_XHCI_EC_DBCAP_DCERDPLO
31:4 0 R/W T_XUSB_XHCI_EC_DBCAP_DCERDPLO_ADDRLO:

3 0 R T_XUSB_XHCI_EC_DBCAP_DCERDPLO_RSVD0:
2:0 0 R/W T_XUSB_XHCI_EC_DBCAP_DCERDPLO_DESI:

0h: DESI_INIT (default)
19.13.18.40 T_XUSB_XHCI_EC_DBCAP_DCERDPHI
31:0 0 R/W T_XUSB_XHCI_EC_DBCAP_DCERDPHI_ADDRHI:

19.13.18.41 T_XUSB_XHCI_EC_DBCAP_DCCTRL
31 0 R/W T_XUSB_XHCI_EC_DBCAP_DCCTRL_DCE:
0h DCE_DIS (default)
1h DCE_EN
30:24 0 R T_XUSB_XHCI_EC_DBCAP_DCCTRL_DEVADR:
0h: DEVADR_INIT (default)
23:16 15h R T_XUSB_XHCI_EC_DBCAP_DCCTRL_MAXBURST:

15h: MAXBURST_INIT (default)
15:5 0 R T_XUSB_XHCI_EC_DBCAP_DCCTRL_RSVD0:
4 0 RW1C T_XUSB_XHCI_EC_DBCAP_DCCTRL_DRC:
0h: DRC_INIT (default)
1h: DRC_SET
1h: DRC_CLEAR
3 0 R/W T_XUSB_XHCI_EC_DBCAP_DCCTRL_HIT:
0h: HIT_FALSE (default)
1h: HIT_TRUE
2 0 R/W T_XUSB_XHCI_EC_DBCAP_DCCTRL_HOT:
0h: HOT_FALSE (default)
1h: HOT_TRUE
1 0 R/W T_XUSB_XHCI_EC_DBCAP_DCCTRL_LSE:
0h: LSE_DIS (default)
1h: LSE_EN
0 0 R T_XUSB_XHCI_EC_DBCAP_DCCTRL_DCR:
0h: DCR_STOP (default)
1h: DCR_RUN

USB Complex
19.13.18.42 T_XUSB_XHCI_EC_DBCAP_DCST
31:24 0 R T_XUSB_XHCI_EC_DBCAP_DCST_DPN:
0h: DPN_INIT (default)
23:1 0 R T_XUSB_XHCI_EC_DBCAP_DCST_RSVD:
0h: RSVD_00 (default)
0 0 R T_XUSB_XHCI_EC_DBCAP_DCST_ER:
0h: ER_EMPTY (default)
1h: ER_NOTEMPTY
19.13.18.43 T_XUSB_XHCI_EC_DBCAP_DCPORTSC
31:24 0 R T_XUSB_XHCI_EC_DBCAP_DCPORTSC_RSVD4:
23 0 RW1C T_XUSB_XHCI_EC_DBCAP_DCPORTSC_CEC:
0h: CEC_NOT_PENDING (default)
1h: CEC_PENDING
1h: CEC_CLEAR
22 0 RW1C T_XUSB_XHCI_EC_DBCAP_DCPORTSC_PLC:
0h: PLC_NOT_PENDING (default)
1h: PLC_PENDING
1h: PLC_CLEAR
21 0 RW1C T_XUSB_XHCI_EC_DBCAP_DCPORTSC_PRC:
0h: PRC_NOT_PENDING (default)
1h: PRC_PENDING
1h: PRC_CLEAR
17 0 RW1C T_XUSB_XHCI_EC_DBCAP_DCPORTSC_CSC:
0h: CSC_NOT_PENDING (default)
1h: CSC_PENDING
1h: CSC_CLEAR
13:10 0 R T_XUSB_XHCI_EC_DBCAP_DCPORTSC_PS:
0h: PS_UNDEFINED (default)
4h: PS_SS
9 0 R T_XUSB_XHCI_EC_DBCAP_DCPORTSC_RSVD1:
8:5 4h R T_XUSB_XHCI_EC_DBCAP_DCPORTSC_PLS:
0h: PLS_U0
1h: PLS_U1
2h: PLS_U2
3h: PLS_U3
4h: PLS_DISABLED (default)
5h: PLS_RXDETECT
6h: PLS_INACTIVE
7h: PLS_POLLING
8h: PLS_RECOVERY
9h: PLS_HOTRESET
Ah: PLS_COMPLIANCE
Bh: PLS_LOOPBACK
Fh: PLS_RESUME

USB Complex
4 0 R T_XUSB_XHCI_EC_DBCAP_DCPORTSC_PR:
0h: PR_NORST (default)
1h: PR_RST
1 0 R/W T_XUSB_XHCI_EC_DBCAP_DCPORTSC_PED:
0h: PED_DIS (default)
1h: PED_EN
0 0 R T_XUSB_XHCI_EC_DBCAP_DCPORTSC_CCS:
0h: CCS_NOCON (default)
1h: CCS_CON
19.13.18.44 T_XUSB_XHCI_EC_DBCAP_RSVD1
31:0 0 R T_XUSB_XHCI_EC_DBCAP_RSVD1_RSVD0:
19.13.18.45 T_XUSB_XHCI_EC_DBCAP_DCECPLO
31:4 0 R/W T_XUSB_XHCI_EC_DBCAP_DCECPLO_ADDRLO:

3:0 0 R T_XUSB_XHCI_EC_DBCAP_DCECPLO_RSVD0:
19.13.18.46 T_XUSB_XHCI_EC_DBCAP_DCECPHI
31:0 0 R/W T_XUSB_XHCI_EC_DBCAP_DCECPHI_ADDRHI:

19.13.18.47 T_XUSB_XHCI_EC_DBCAP_INFO0
31:16 0 R/W T_XUSB_XHCI_EC_DBCAP_INFO0_VENDORID:

0h: VENDORID_INIT (default)
15:8 0 R Reserved
7:0 0 R/W T_XUSB_XHCI_EC_DBCAP_INFO0_PROTOCOL:

0h: PROTOCOL_VENDOR (default)
1h: PROTOCOL_GNU
19.13.18.48 T_XUSB_XHCI_EC_DBCAP_INFO1

USB Complex
31:16 0 R/W T_XUSB_XHCI_EC_DBCAP_INFO1_DEV_REV:

0h: DEV_REV_INIT (default)
15:0 0 R/W T_XUSB_XHCI_EC_DBCAP_INFO1_PRODUCTID:

0h: PRODUCTID_INIT (default)
19.13.18.49 T_XUSB_XHCI_RT_MFINDEX
31:14 0 R T_XUSB_XHCI_RT_MFINDEX_RSVD0:
0h: RSVD0_00
13:0 Unknown R T_XUSB_XHCI_RT_MFINDEX_MFINDEX:
19.13.18.50 T_XUSB_XHCI_RT_IMAN
31:2 0 R T_XUSB_XHCI_RT_IMAN_RSVD0:
0h: RSVD0_00
1 0 R/W T_XUSB_XHCI_RT_IMAN_IE:
0h: IE_DISABLED (default)
1h: IE_ENABLED
0 0 RW1C T_XUSB_XHCI_RT_IMAN_IP:
0h: IP_NOT_PENDING (default)
1h: IP_PENDING
1h: IP_CLEAR
19.13.18.51 T_XUSB_XHCI_RT_IMOD
31:16 Unknown R/W T_XUSB_XHCI_RT_IMOD_IMODC:
15:0 0FA0h R/W T_XUSB_XHCI_RT_IMOD_IMODI:

FA0h: IMODI_INIT (default)
19.13.18.52 T_XUSB_XHCI_RT_ERSTSZ
31:16 0 R T_XUSB_XHCI_RT_ERSTSZ_RSVD0:
0h: RSVD0_00
15:0 0 R/W T_XUSB_XHCI_RT_ERSTSZ_SZ:

0h: SZ_INIT (default)
19.13.18.53 T_XUSB_XHCI_RT_ERRSVD
31:0 0 R T_XUSB_XHCI_RT_ERRSVD_RSVD0:

USB Complex

0h: RSVD0_00
19.13.18.54 T_XUSB_XHCI_RT_ERSTBA0
31:4 0 R/W T_XUSB_XHCI_RT_ERSTBA0_ERSTBLO:

0h: ERSTBLO_INIT (default)
3:0 0 R T_XUSB_XHCI_RT_ERSTBA0_RSVD0:
0h: RSVD0_00
19.13.18.55 T_XUSB_XHCI_RT_ERSTBA1
31:0 0 R/W T_XUSB_XHCI_RT_ERSTBA1_ERSTBHI:

0h: ERSTBHI_INIT (default)
19.13.18.56 T_XUSB_XHCI_RT_ERDP0
31:4 0 R/W T_XUSB_XHCI_RT_ERDP0_DQPTRLO:

0h: DQPTRLO_INIT (default)
2:0 0 R/W T_XUSB_XHCI_RT_ERDP0_DESI:

0h: DESI_INIT (default)
19.13.18.57 T_XUSB_XHCI_RT_ERDP1
31:0 0 R/W T_XUSB_XHCI_RT_ERDP1_DQPTRHI:

0h: DQPTRHI_INIT (default)
19.13.18.58 T_XUSB_XHCI_DB
Offset: 0xc00 – 0xffc | Read/Write: W
31:16 0 W T_XUSB_XHCI_DB_STREAMID:
0h: STREAMID_INIT (default)
15:8 0 R T_XUSB_XHCI_DB_RSVD0:
0h: RSVD0_00
7:0 0 W T_XUSB_XHCI_DB_TARGET:
0h: TARGET_INIT (default)


USB Complex
USB_PHY PLL Configuration Register 0
This register was used to configure the PLL inside UTMIP block prior to Tegra K1 processors. This has been defeatured from
UTMIP space and moved to Clock and Reset (CAR) space. Refer to the UTMIP_PLL register descriptions in the Clock and
Reset Controller section.
This register was used to configure the PLL inside the UTMIP block prior to Tegra K1 processors. This has been defeatured
from UTMIP space and moved to CAR space. Refer to the UTMIP_PLL register descriptions in the Clock and Reset Controller
section.

21 0x1 UTMIP_XCVR_LSBIAS_SEL: Low speed bias selection method for usb transceiver pad
20 0x0 UTMIP_XCVR_DISCON_METHOD: Disconnect method on the usb transceiver pad

18 0x1

16 0x1
FORCE_PD2_POWERUP.)

14 0x1
FORCE_PD_POWERUP.)

USB Complex

29 0x0 UTMIP_IDDIG_C_SEL: 0: IdDig_c = IdDig_c. 1: IdDig_c = IDDIG_C_VAL.
27 0x0 UTMIP_IDDIG_B_SEL: 0: IdDig_b = IdDig_b. 1: IdDig_b = IDDIG_B_VAL.
25 0x0 UTMIP_IDDIG_A_SEL: 0: IdDig_a = IdDig_a. 1: IdDig_a = IDDIG_A_VAL.
20 0x0 UTMIP_IDDIG_SEL: 0: IdDig = IdDig. 1: IdDig = IDDIG_VAL.
18 0x0 UTMIP_GPI_SEL: 0: StaticGpi = IdDig. 1: StaticGpi = GPI_VAL.
14:12 0x0 UTMIP_ACTIVE_PULLUP_OFFSET: Active 1.5K pull-up control offset.


USB Complex
7 0x0 UTMIP_PASS_CHIRP: When in Chirp Mode, allow chirp rx data through


13:8 0x4 UTMIP_FSLS_IDLE_WAIT_MAX: 4 bits of of SEO should exceed the time limit

USB Complex

10:5 0x20 UTMIP_LS_SE0_COUNT: Only for this number of 60 MHz of SEO and Idle to end packet
0 0x0 UTMIP_FS_EOP_LENGTH: Whether full-speed EOP is determined within 3(0) or 4(1) 60 MHz cycles

8 0x0 UTMIP_HS_DISCON_DISABLE: Disable high-speed disconnect
6 0x0 UTMIP_HS_PREAMBLE_OUTPUT_ENABLE: output enable turns on 1 cycle before
5 0x0 UTMIP_SIE_RESUME_ON_LINESTATE: SIE, not macrocell, detects Line State change to resume

4 0x0
packets

USB Complex

22 0x1 UTMIP_SUSPEND_EXIT_ON_EDGE: Suspend exit requires edge or simply a value...
21 0x1
happen)

0 = DISABLE
20:19 0x0 1 = BIT_ERR
2 = RX_ERR
3 = BIT_RX_ERR
15 0x0 UTMIP_DISABLE_PULLUP_DP: Force DP pull-up inactive. (Overrides FORCE_PULLUP_DP.)
14 0x0 UTMIP_DISABLE_PULLUP_DM: Force DM pull-up inactive. (Overrides FORCE_PULLUP_DM.)
13 0x0 UTMIP_DISABLE_PULLDN_DP: Force DP pull-down inactive. (Overrides FORCE_PULLDN_DP.)
12 0x0 UTMIP_DISABLE_PULLDN_DM: Force DM pull-down inactive. (Overrides FORCE_PULLDN_DM.)
11 0x0 UTMIP_FORCE_PULLUP_DP: Force DP pull-up active.
10 0x0 UTMIP_FORCE_PULLUP_DM: Force DM pull-up active.
9 0x0 UTMIP_FORCE_PULLDN_DP: Force DP pull-down active.
8 0x0 UTMIP_FORCE_PULLDN_DM: Force DM pull-down active.
3 0x1 UTMIP_NO_FREE_ON_SUSPEND: Do not use free-running terminations during suspend.


USB Complex
29 0x0 UTMIP_LINESTATE_BYPASS: Bypass Line State reclocking logic
UTMIP_LINESTATE_XCVRSEL3: 0: Use FS filtering on line state when XcvrSel=3 1: Use LS filtering

27 0x0
on line state when XcvrSel=3
22:18 0x6 UTMIP_PLL_ACTIVE_DLY_COUNT: Reserved. Refer to the Clock and Reset registers for this feature.
17:6 0x600 UTMIP_PLLU_STABLE_COUNT: Reserved. Refer to the Clock and Reset registers for this feature.
UTMIP_XCVRSEL3
1:0 0x0 Bit 0: 0: 0xa5 -> treat as KeepAlive 1: treat as regular packet
Bit 1: 0: Turn on FS EOP detection 1: Turn off FS EOP detection

Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and SessEnd. Each of these signals has its own debouncer,
and for each of those, one out of 2 debouncing times can be chosen (BIAS_DEBOUNCE_A or BIAS_DEBOUNCE_B.)
ms = *1000 / (1/19.2MHz) / 4
So to program a 1 ms debounce for BIAS_DEBOUNCE_A, BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0


13:8 0x0

USB Complex
0 0x1 UTMIP_PD_CHRG: Power down charger circuit


31:0 -65288 1: HS_RX_FLUSH_ALAP. Flush as late as possible
31 to 3: Reserved

27:26 0x0 UTMIP_XCVR_RPU_RANGE_ADJ: 1.5k pull-up resistor range shift
25:24 0x0 UTMIP_XCVR_HS_IREF_CAP: High Speed Iref cap control for bias current stability
17 0x0 UTMIP_RCTRL_SW_SET: Use a software override on RCTRL instead of automatic bias control

16:12 0x8
only

10:6 0x8
only

4 0x1

2 0x1
UTMIP_FORCE_PDDISC_POWERDOWN: Force PDDISC input into power down. (Overrides

0 0x1

USB Complex

UTMIP_BIAS_DEBOUNCE_TIMESCALE: Debouncer time scaling, factor - 1 to slow down debouncing

13:8 0x0
7:3 0x5
2 0x1 UTMIP_VBUS_WAKEUP_POWERDOWN: Reserved. Refer to the PMC registers for this feature.

0 0x1

UTMIP VDcd_Det and VDat_Det debounce

Debounce values VDcd_Det and VDat_Det. Each of these signals has its own debouncer. For each of those, one out of 2
ms = *1000 / (1/19.2MHz) / 4
So to program a 1 ms debounce for CHG_DEBOUNCE_PERIOD, we have: CHG_DEBOUNCE_PERIOD[15:0] = 1000 * 19.2 /

4 = 4800 = 0x12c0
31:16 0xffff UTMIP_CHRG_DEBOUNCE_PERIOD_B: simulation value -- Used for interrupts
15:0 0xffff UTMIP_CHRG_DEBOUNCE_PERIOD_A: simulation value -- Used for interrupts


USB Complex
20:0 X UTMIP_SPARE_FUSES: Spare Fuses value, to keep the connections preserved
UTMIP PMC Wakeup Value

19.13.19.21 USB3_UHSIC_PLL_CFG0_0
UHSIC PHY PLL Configuration Register 0

0 0x0 UHSIC_PLL_SPARE: Reserved
19.13.19.22 USB3_UHSIC_PLL_CFG1_0
UHSIC PLL and PLLU Configuration Register 1

This register is used to configure the PHY PLL contained in the UHSIC module as well as the PLLU power up and down.
PLL CONFIGURATION and PARAMETERS
In normal operation, the following clock generators are in play for USB:
Crystal clock -> enters PLLU to generate 12 MHz clock -> enters USB_PHY PLL to generate 480/60 MHz clock
The following parameters control the bring-up of the PLLs:
Coming out of reset or suspend
PllUOnState: start pllu_enable_count and pll_lock_count
Wait ~1 µs to enable the PLL_U (pllu_enable_count == ClkXtal * PLLU_ENABLE_DLY_COUNT * 8)
Wait ~1 ms until PLLU is stable (pll_lock_count == ClkXtal * PLLU_STABLE_COUNT * 256) => USB_PHY
PLL_ENABLE
Numbers for a 19.2 MHz crystal clock
§ PLLU_ENABLE_DLY_COUNT[4:0] = 1 * 19.2 / 8 = 2.4 = 3 = 0x03
§ PLLU_STABLE_COUNT[11:0] = 1000 * 19.2 / 256 = 75 = 0x4b (Note: currently defaults to 0x600)
§ XTAL_FREQ_COUNT[11:0] = 2500 * 19.2 / 256 = 187 = 0xbb
Offset: 0xc04 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxx0001100000011000000
18:14 0x3 UHSIC_PLLU_ENABLE_DLY_COUNT: 1 µs / (1/19.2MHz) = 19 / 8 = 2.36 = 3

USB Complex
13 0x0 UHSIC_FORCE_PLLU_POWERUP
12 0x0 UHSIC_FORCE_PLLU_POWERDOWN
11:0 0xc0 UHSIC_XTAL_FREQ_COUNT: 2.5ms / (1/19.2MHz) = 48000 / 256 = 187 = 0xBB
19.13.19.23 USB3_UHSIC_HSRX_CFG0_0
UHSIC High Speed Receive Config 0

Offset: 0xc08 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxx0010100111000111000
18 0x0 UHSIC_NO_STRIPPING: Do not strip incoming data
17:13 0xa UHSIC_IDLE_WAIT: Number of idle cycles to declare IDLE.
12:8 0xe UHSIC_ELASTIC_OVERRUN_LIMIT
7 0x0 UHSIC_ELASTIC_OVERRUN_DISABLE: Do not declare overrun errors until overflow of FIFO
6:2 0xe UHSIC_ELASTIC_UNDERRUN_LIMIT
1 0x0 UHSIC_ELASTIC_UNDERRUN_DISABLE: Do not declare underrun errors
0 0x0 UHSIC_PASS_FEEDBACK: Pass through the feedback, do not block it.
19.13.19.24 USB3_UHSIC_HSRX_CFG1_0
UHSIC High Speed Receive Config 1

Offset: 0xc0c | Read/Write: R/W | Reset: 0bxxxxxxxx100010000010100100010011
23:20 0x8 UHSIC_TX_BLOCK_CNT: Controls how long after the end of transmission the receive path is
blocked
19:14 0x20 UHSIC_RX_STROBE_DLY_TRIMMER: Number of delays cells between UH_RX_STROBE and

RxStrobeClk in zero cycle path
13:9 0x14 UHSIC_INPUT_FIFO_DEPTH: Depth of the 2-bit wide input FIFO. Maximum depth is 20. Can be
tuned
8 0x1 UHSIC_LINE_STATE_RESUME_FAKE_SE0: When enabled, send an SE0 for 2 LS symbols at

the end of ResumeK
7 0x0 UHSIC_LINE_STATE_BYPASS: Bypass Line State reclocking logic
6 0x0 UHSIC_EARLY_LINE_STATE_FILTER: Assumes line state filtering table is inclusive, not

exclusive
5:1 0x9 UHSIC_HS_SYNC_START_DLY: How long to wait before start of sync launches RxActive
0 0x1 UHSIC_HS_ALLOW_KEEP_ALIVE: Allow Keep Alive packets
19.13.19.25 USB3_UHSIC_TX_CFG0_0
UHSIC Transmit Config Signals

Offset: 0xc10 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxxxxxxxxxx0000000000
9 0x0 UHSIC_HS_READY_WAIT_FOR_VALID

USB Complex
8 0x0 UHSIC_PACKET_INVERT_DATA: Invert data during a regular packet
7 0x0 UHSIC_PACKET_FORCE_STROBE_LOW: Force STROBE low during a regular instead of

toggling it
6 0x0 UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE: output enable turns off 1 cycle after
5 0x0 UHSIC_SIE_RESUME_ON_LINESTATE: SIE, not macrocell, detects Line State change to resume
4 0x0 UHSIC_SOF_ON_NO_STUFF: SOF when OpMode 3 -- perhaps, when the sending controller
made packets
3 0x0 UHSIC_SOF_ON_NO_ENCODE: SOF when OpMode 2 -- not likely, for Chirp
2 0x0 UHSIC_NO_STUFFING: No bit stuffing, static programming
1 0x0 UHSIC_NO_ENCODING: No encoding, static programming
0 0x0 UHSIC_NO_SYNC_NO_EOP: Do not send SYNC or EOP
19.13.19.26 USB3_UHSIC_MISC_CFG0_0
UHSIC Miscellaneous Configurations

Offset: 0xc14 | Read/Write: R/W | Reset: 0bxxxxxxxxxxx001000100111010001110
20 0x0 UHSIC_DISABLE_BUSRESET: When 1, the PHY will not send out BusReset during
XcvrSelect0, TermSelect0, and Opmode2. It will send out a non-bit-stuffed, non-encoded packet
instead.
19 0x0 UHSIC_FORCE_TERMSEL: Value to be forced on TermSelect when FORCE_XCVR_MODE is

set.
18 0x1 UHSIC_EXTEND_BK_ACTIVE: Drive the bus keeper one cycle longer when going out of IDLE
17:16 0x0 UHSIC_FORCE_XCVRSEL: Value to be forced on XcvrSelect when FORCE_XCVR_MODE is

set.
15 0x0 UHSIC_FORCE_XCVR_MODE: 1: Force the values of XcvrSelect and TermSelect via config bits
instead of via the controller
14 0x1 UHSIC_SYMMETRIC_CONNECT_DATA
0: DATA goes high before STROBE goes low and low before STROBE goes high.
1: DATA goes high before STROBE goes low and goes low *after* STROBE goes high.
13 0x0 UHSIC_ASYNC_CONNECT_DATA
0: DATA keeps setup and hold requirements during CONNECT.
1: DATA moves together with STROBE
12 0x0 UHSIC_LONG_CONNECT_STROBE
0: STROBE is 2 periods long during connect.
1: STROBE is 3 periods long during connect
11 0x1 UHSIC_ACTIVE_BK_DRIVE_RX: 1: Use RX state (EOP, etc.) to determine starting time to drive
bus keeper instead of waiting for IDLE detection.
10 0x1 UHSIC_ACTIVE_BK_DRIVE_TX: 1: Use TX state to determine starting time to drive bus keeper
instead of waiting for IDLE detection.
9 0x1 UHSIC_DETECT_SHORT_IDLE
0: Use 3 edges (negative and positive) to detect an idle state on the line.
1: Use 4 edges.
8 0x0 UHSIC_DETECT_SHORT_CONNECT:
0: Use 3 edges (negative and positive) to detect a connect state on the line.
1: Use 4 edges.

USB Complex
7 0x1 UHSIC_SUSPEND_EXIT_ON_EDGE: Suspend exit requires edge or simply a value.
6:5 0x0 UHSIC_INJECT_ERROR_TYPE: Force error insertion into RX path. (Used for IOBIST.)
0 = DISABLE
1 = BIT_ERR
2 = RX_ERR
3 = BIT_RX_ERR
4:2 0x3 UHSIC_STABLE_COUNT: Number of crystal clock cycles of signal not changing to consider
stable.
1 0x1 UHSIC_STABLE_ALL: Determines if all signals need to be stable to not change a config.
0 0x0 UHSIC_COMB_TERMS: Use combinational terminations or synced through CLKXTAL
19.13.19.27 USB3_UHSIC_MISC_CFG1_0
UHSIC Miscellaneous Configurations

Offset: 0xc18 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxx100001100000000010
17 0x1 UHSIC_PHY_XTAL_CLOCKEN: Selects whether to enable the crystal clock in the module.
16:15 0x0 UHSIC_OBS_SEL: Select which one of 4 observation vectors is presented on the observation
bus
14 0x0 UHSIC_FORCE_IOBIST_CLK_ON: Always enable IoBist CLK60. This would be required when
you want to use RX_ERROR_CNT_EN.
13:2 0x600 UHSIC_PLLU_STABLE_COUNT: PLLU frequency lock delay.
1 0x1 UHSIC_RX_ERROR_CNT_CLR: Clear IOBST RxError counter
0 0x0 UHSIC_RX_ERROR_CNT_EN: Enable IOBIST RxError counter when not in IOBIST mode.
Allows one to read out the number of errors via JTAG during normal operation
19.13.19.28 USB3_UHSIC_PADS_CFG0_0
UHSIC Pads Settings

Offset: 0xc1c | Read/Write: R/W | Reset: 0b0b00000000000000001000100010001000
31:24 0x0 UHSIC_HSIC_OPT: Spare config bits
23:20 0x0 UHSIC_TX_SLEWN: Output slew rate (fall time) adjustment
19:16 0x0 UHSIC_TX_SLEWP: Output slew rate (rise time) adjustment
15:12 0x8 UHSIC_TX_RTUNEN: Fine-tuned 50 Ohm termination resistor for NMOS driver
11:8 0x8 UHSIC_TX_RTUNEP: Fine-tuned 50 Ohm termination resistor for PMOS driver
7:4 0x8 UHSIC_TX_RTERMN: Output impedance adjustment for NMOS driver
3:0 0x8 UHSIC_TX_RTERMP: Output impedance adjustment for PMOS driver

USB Complex
19.13.19.29 USB3_UHSIC_PADS_CFG1_0
UHSIC Pads Settings

Offset: 0xc20 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxxxxxxx0011001111101
12 0x0 UHSIC_RPU_STROBE: Enable pull up on IO_STROBE
11 0x0 UHSIC_RPU_DATA: Enable pull up on IO_DATA
10 0x1 UHSIC_RPD_STROBE: Enable pull down on IO_STROBE
9 0x1 UHSIC_RPD_DATA: Enable pull down on IO_DATA
8 0x0 UHSIC_LPBK: Internal digital loopback
7 0x0 UHSIC_RX_SEL: 0: Differential read buffers, 1: Single-ended buffers
6 0x1 UHSIC_PD_ZI: Power down single ended receiver
5 0x1 UHSIC_PD_RX: Power down receiver
4 0x1 UHSIC_PD_TRK: Power down tracking circuit
3 0x1 UHSIC_PD_TX: Power down transmitter
2 0x1 UHSIC_PD_BG: Power down band-gap and bias generator
1 0x0 UHSIC_IDDQ: Shut down analog blocks for IDDQ testing
0 0x1 UHSIC_AUTO_RTERM_EN: Enable auto-termination
19.13.19.30 USB3_UHSIC_CMD_CFG0_0
Determine start-up behavior.
When AUTO_NEGIOTIATE == 0
§ Firmware is supposed to take care of things.
HOST
if Opmode1: do not drive anything
else
Initial power up:
§ Asynchronously drive 00
§ After a few crystal clocks, enable bus keepers
Offset: 0xc24 | Read/Write: R/W | Reset: 0bxxxxxxxxxxxxxxxxxxxxxxxxx0000101
6 0x0 UHSIC_FORCE_ACTIVATED: Force PHY into activated state without connect handshake (both
host and device)
5 0x0 UHSIC_PRETEND_CONNECT_DETECT: While in HOST mode, act as if the input stage has seen
a CONNECT pulse from the external PHY
4 0x0 UHSIC_FORCE_RESET: While in HOST mode, force global state machine into RESET state
3 0x0 UHSIC_FORCE_CONNECT: Upon rising value of this bit, force device to send connect. Only useful
when AUTO_CONNECT is disabled.
2 0x1 UHSIC_AUTO_CONNECT: As device, automatically send Connect during activation.

USB Complex
1 0x0 UHSIC_FORCE_ACTIVATE: Upon rising value of this bit, instruct state machine to go into
activation mode. Only useful when AUTO_ACTIVATE is disabled.
0 0x1 UHSIC_AUTO_ACTIVATE: Upon power up, automatically move to activation mode and start going
through connect procedure.
19.13.19.31 USB3_UHSIC_STAT_CFG0_0
31:16 RO X UHSIC_CALIOUT
15:8 RO X UHSIC_SPARE_STATUS
2:1 RO X UHSIC_BUS_STATE
0 RW 0x0 UHSIC_CONNECT_DETECT
19.13.19.32 USB3_UHSIC_SPARE_CFG0_0
UTMIP Spare Configurations, Spare Configuration Bits

Offset: 0xc2c | Read/Write: R/W | Reset: 0b11111111111111110000000000000000
31:0 -65536 UHSIC_SPARE: Bit 0: HS_RX_IPG_ERROR_ENABLE

Bit 1: HS_RX_FLUSH_ALAP
Bit 2: FORCE_TRIM_ZERO
Bit 3: TX_EN_INIT_CTRL
Bits 7 :4: RX_DATA_TRIM[3:0]
Bit 11:8: RX_STROBE_TRIM[3:0]
Bit 12: FORCE_BK_ON
Bit 13: BYPASS_INIT_BLOCK
Bit 14: FORCE_SM_IDLE
Bit 15: FORCE_BK_OFF
Bit 16: ALLOW_FLUSH_SHIFT
19.13.19.33 USB3_UHSIC_MISC_STS0_0
UHSIC SPARE Fuse Value

Offset: 0xc30 | Read/Write: RO | Reset: 0bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
0 X UHSIC_TX_HS_VLD: Indicates when the controller is driving on the bus
19.13.19.34 USB3_UHSIC_PMC_WAKEUP0_0
UHSIC PMC Wakeup Value

1 RO X UHSIC_LINE_WAKEUP_EVENT_INT_STS: Indicates the status of the PMC wakeup event
0 RW 0x0 UHSIC_LINE_WAKEUP_EVENT_INT_ENB: Interrupt mask for the PMC wakeup event

USB Complex

USB2D_QH: Queue Head for OUT endpoint n. This is used to store a local Queue Head data structure for
31:0 0x0
either device mode or host mode. In device mode, it holds the Queue Head for OUT endpoint n.
USB2D Queue Head for IN Endpoint 0

31:0 0x0

20.0 AUDIO HUB (AHUB)

®
The audio hub (AHUB) in Tegra K1 mobile processors has external I2S and S/PDIF interfaces. It can process audio for
Digital Audio Mixers (DAMs), Audio Multiplexers (AMXs), Audio Demultiplexers (ADXs), Audio Flow Controllers (AFCs), and
DMA (APBIF-DMA) channels to communicate with the memory. The AHUB supports multiple interfaces to the audio devices in
the system cellular baseband; different audio codecs; Bluetooth modules; A/V receivers; etc. The AHUB can support the
different interface, protocol, and signal quality requirements of these audio devices.
Figure 43: Audio Hub Functional Block Diagram

Audio Hub
The Audio Hub (AHUB) consists of

 10 APBIF DMA channels
2
 5 I S controllers
 1 S/PDIF controller
 3 Digital Audio sample-rate conversion and Mixing blocks (DAMs)
 2 Audio Multiplexers (AMX) and 2 Audio Demultiplexers (ADXs) for audio processing.
 6 Audio Flow Controllers (AFCs)
20.1 Crossbar
The crossbar (XBAR) is a 36x39 full crossbar switch with unidirectional data flow, with 36 TX and 39 RX clients. The XBAR
has multicasting capability: A TX client can send audio data to multiple RX clients, while a RX client can receive data from only
one TX at a time. It also has the ability to connect TX clients with Rx clients in many sessions that function independently of
each other.
20.1.1 XBAR Programming Guidelines

To connect two modules in AHUB, for example, DAM0’s output to I2S1’s input:
1. Go to the register corresponding to the receiver, in this case, the I2S1 AUDIO_I2S1_RX0_0 register.
2. Enable the bit that corresponds to the transmitter, in this case, the field DAM1_TX0.
3. Ensure that all other fields in the AUDIO_I2S1_RX0_0 register are disabled. At power on, all the fields are disabled.
So this step is required only while setting up the audio routing after removing the previous use case’s audio routing.
20.2 Audio Client Interface (ACIF)

Audio streams are routed through the AHUB by interconnecting various modules using the Audio Client Interface (ACIF).
All the AHUB modules have one or more Transmit Audio Client Interfaces (TxCIFs) and one or more Receive Audio Client
Interfaces (RxCIFs). Hence all modules in the AHUB have registers named <module>_AUDIOCIF_<tag>_CTRL that are used
to configure the interfaces. The audio CIF interface includes common functionalities that are used in all the AHUB modules
such as:
 Converting the number of channels in the input stream(s) before the stream is fed into the module. This feature is
limited to converting a mono stream to a stereo stream and vice-versa.
 Converting the number of bits/sample for the input stream(s) before the stream is fed into the module.
20.2.1 General ACIF Register Specification

The ACIF registers are present in the AHUB modules. For convenience of reference for the programming guidelines below,
here is a sample ACIF register.
29:24 RW 0x0 FIFO_THRESHOLD
AUDIO_CHANNELS:
0 = CH1
1 = CH2
2 = CH3
3 = CH4
23:20 RW 0x0 4 = CH5
5 = CH6
6 = CH7
7 = CH8
8 = CH9
9 = CH10

Audio Hub

10 = CH11
11 = CH12
12 = CH13
13 = CH14
14 = CH15
15 = CH16
CLIENT_CHANNELS:
0 = CH1
1 = CH2
2 = CH3
3 = CH4
4 = CH5
5 = CH6
6 = CH7
19:16 RW 0x0 7 = CH8
8 = CH9
9 = CH10
10 = CH11
11 = CH12
12 = CH13
13 = CH14
14 = CH15
15 = CH16
AUDIO_BITS:
0 = BIT4
1 = BIT8
2 = BIT12
14:12 RW 0x1 3 = BIT16
4 = BIT20
5 = BIT24
6 = BIT28
7 = BIT32
CLIENT_BITS:
0 = BIT4
1 = BIT8
2 = BIT12
10:8 RW 0x1 3 = BIT16
4 = BIT20
5 = BIT24
6 = BIT28
7 = BIT32
EXPAND:
0 = ZERO
7:6 RW 0x0 1 = ONE
2 = LFSR
3 = RSVD
STEREO_CONV:
0 = CH0
5:4 RW 0x0 1 = CH1
2 = AVG
3 = RSVD
REPLICATE:
1 = ENABLE
DIRECTION:
2 RO X 0 = TXCIF
1 = RXCIF
TRUNCATE:
1 RW 0x0 0 = ROUND
1 = CHOP
0 RW 0x0 MONO_CONV:

Audio Hub

0 = ZERO
1 = COPY
20.2.2 ACIF Programming Guidelines
The following programming guidelines are common for the ACIF registers in all AHUB modules. The programming guidelines
of the respective modules will refer to this subsection when it comes to programming the ACIF registers.
1. Set the AUDIO_CHANNELS field to the number of channels in the input or output stream of a module, depending on
whether the ACIF in question is an RxCIF or TxCIF respectively
2. Set the CLIENT_CHANNELS field to the number of channels of the stream as dealt with inside the module. This
setting is different from AUDIO_CHANNELS only when a conversion of the number of channels of an audio stream is
desired.
3. Similarly, set the AUDIO_BITS and CLIENT_BITS fields.
4. If AUDIO_BITS and CLIENT_BITS do not match, the EXPAND and TRUNCATE fields are used to determine how to
transition from AUDIO_BITS to CLIENT_BITS (in the case of a RxCIF) or from CLIENT_BITS to AUDIO_BITS (in the
case of an TxCIF). Expanding always results in the actual data being shifted to the MSB bits and the rest filled with
zeros, ones, or some random bits from an LFSR. TRUNCATE can be set to chopping or rounding.
5. If AUDIO_CHANNELS and the CLIENT_CHANNELS are different, the STEREO_CONV field is used to determine
how a stereo stream is converted to a mono stream, and the MONO_CONV field is used to determine how a mono
stream is converted to a stereo stream.
20.3 APBIF
Note: Tegra K1 devices contain identical APBIF and APBIF2 functional blocks. Unless specified
otherwise, references to APBIF in this document also apply to APBIF2. Each block has its
own register set.
The AMBA Peripheral Bus Interface (APBIF) is the agent for the APB control flow and DMA operation, which sends or receives
data from/to Memory. The APBIF is composed of N instances of AHUBIF and APB interfaces as shown in the figure below.
Figure 44: APBIF Block Diagram
TX
AHUBCIF
Channel 0
RX
AHUBCIF
Channel 1
APB AHUB
APBIF
AHUBCIF
Channel N-1

Audio Hub
20.3.1 APBIF Features

 Separate APB DMA operations for all AHUB clients
 Each channel is bidirectional and needs one TX and one RX AHUBCIF.
 Scalable N channel design
 Maintain interrupt registers for AHUB clients
20.3.2 APBIF Programming Guidelines

Note: APBIF is comprised of APBIF1 (channels 0 to 3) and APBIF2 (channels 4 through 9).
Refer to the APBIF and APBIF2 register descriptions for more information.
1. Program the CLK_RST_CONTROLLER_CLK_OUT_ENB_V register to enable Audio XBAR and APBIF

2. Program the CLK_RST_CONTROLLER_CLK_SOURCE_AUDIO_0 register. Set the AUDIO_CLK_SRC field to
CLK_SRC_ALT if an alternate clock source needs to be chosen followed by setting of AUDIO_CLK_SRC_RATE to
choose the alternate clock source for DAM.
3. Deassert APBIF and AUDIO reset by programming the CLK_RST_CONTROLLER_RST_DEVICES_V register.
4. Wait for resets by polling until the reset bit clears.
5. Configure the ACIF interfaces of the APBIF according to the programming guidelines available in the ACIF
Programming Guidelines section.
6. Configure the control register for the APBIF Tx and Rx channels. APBIF_CHANNEL0_CTRL_0 is the control register
for both Tx and Rx channel 0 (similar control registers are present for all 10 APBIF channels). Configuration options
for the Tx channels are :
- TX_ENABLE: enables the Tx channel
- TX_THRESHOLD: sets the FIFO threshold for sending the tx_req signal to APBDMA
- TX_PACK_EN: enables Tx packed mode
- TX_PACK: pack options of four 8-bit words or two 16-bit words. The options are similar for Rx channels as well
- LOOPBACK: enables APBIF internal loopback (debugging feature).
20.4 I2S Controller

2
The Inter-IC Sound (I S) controller implements full-duplex and bidirectional and single direction point-to-point serial interfaces.
2
It can interface with I S-compatible products, such as compact disc players, digital audio tape devices, digital sound
processors, modems, Bluetooth chips, etc.
Figure 45: I2S Interaction with External Device
I2S_SCLK
RxCIF I2S_LRCK
RX
I2S Controller
I2S_RST
AHUB I2S Controller of External
Device
I2S_DOUT
TX
TxCIF
I2S_DIN
2
The I S controller can operate both as master and slave. It supports the following data transfer modes:
2
 I S mode
 Left Justified Mode (LJM)
 Right Justified Mode (RJM)

Audio Hub
2
 DSP mode, as defined in the Philips inter-IC-sound (I S) bus specification
 PCM mode with short (one-bit-clock wide) and long-fsync (two bit-clocks wide
 Network (Telephony) mode with independent slot selection for both Tx and Rx
 TDM mode with flexibility in number of slots with up to 16 slots.
 Capability to drive-out a High-Z outside the prescribed slot for transmission
2
The I S controller can transmit and receive word lengths of 8, 16, 24, and 32.
It supports u-Law and A-Law compression/decompression.

2 2
The I S controller can control the flow of traffic from another I S controller operating on an independent bit clock (with a ppm
difference compared to its own bit clock).
20.4.1 Transmission/Reception Data Formats
20.4.1.1 LRCK Modes

This subsection illustrates three LRCK modes: Basic I2S mode, Right Justified mode, and Left Justified mode.
Basic I2S Mode

In Basic I2S mode, data starts one sclk after the LRCK edge (offset = 1).
Figure 46: Basic I2S Mode
1/Fs
LRCK Right Channel Left Channel Right Channel Left Channel
SCLK
DATA 1 2 n 1 2 n
MSB LSB MSB LSB
Right Justified (RJ) Mode

In RJ mode, data starts (r/2 – n) SCLKs after the LRCK edge (offset = r/2 – n, where r = number of SCLKs per LRCK, n =
number of bits/sample).
Figure 47: RJ Mode
1/Fs
SCLK
DATA 1 2 n 1 2 n
MSB LSB MSB LSB
Left Justified (LJ) Mode

In LJ mode, data starts 0 SCLKs after the LRCK edge (offset = 0).

Audio Hub
Figure 48: LJ Mode
1/Fs
SCLK
DATA 1 2 n 1 2 n
MSB LSB MSB LSB
FSYNC Modes
The width of the FSYNC, the offset value, number of slots and number of SCLKs per 1/Fs are all configurable. The slots are
always contiguous.
Figure 49: FSync Mode
1/Fs
FSYNC
SCLK
DATA Offset 1 2 3 n 1 2 3 n
Slot1 Slot2
MSB LSB MSB LSB
PCM Mode
Figure 50: PCM Mode

Audio Hub
Data Formats in NW Mode

Telephone Codec Mode
Frame Sync Telephone Audio
Bit Clock
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
Rx Data 5 4 3 2 1 0
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
Tx Data 5 4 3 2 1 0
Frame Sync
Bit Clock
Rx Data Don’t care 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Don’t care
Tx Data High Z 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 High Z
Data Format in TDM Mode
Slot 0 Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 0 Slot 1 Slot 2 Slot 3
TDM Frame
1. FS duration of a slot is shown. FS duration of a single bit is also supported.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK
Frame Sync (1)
Frame Sync (2) Slot 0 Slot 1

(0 bit delay)
Frame Sync (2)

Slot 0 Slot 1
(1 bit delay)
Frame Sync (2) Slot 0 Slot 1

(2 bit delay)
1. FS duration of a slot is shown. FS duration of a single bit is also supported.

2. Last bit of the last slot of the previous frame. No gap is allowed between this bit and the first bit of slot 0.

Audio Hub
20.4.2 I2S Controller Programming Guidelines
20.4.2.1 Module Initialization

1. Program the CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0 register to enable the I2S clock.
2. Program the CLK_RST_CONTROLLER_CLK_SOURCE_I2S0_0 register (for I2S0) and similar registers for other
instances to program the I2S clock source. Set I2S0_CLK_SRC to select the clock source.
3. Choose SYNC_CLK as the clock source in the I2S0_CLK_SRC field of the
CLK_RST_CONTROLLER_CLK_SOURCE_I2S0_0 register to select alt clock sources.
4. This should be followed by setting the CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S0_0 register to choose
2
the alternate clock source for I S.
5. Deassert I2S0 and AUDIO resets by programming the CLK_RST_CONTROLLER_RST_DEVICES_L register.
6. Wait for resets to happen before proceeding further.
7. Configure the ACIF registers I2S_AUDIOCIF_I2SRX_CTRL_0 and I2S_AUDIOCIF_I2STX_CTRL_0 by following the
guidelines in the ACIF Programming Guidelines subsection.
8. Enable Rx transmit or Tx transmit by configuring I2S_CTRL_0.
20.4.2.2 I2S Sampling Rate Selection

The channel_bit_cnt can be calculated using the equation:
channel_bit_cnt = (frequency of bit_clk) / (2 * required sampling rate) -1
If this calculation returns a fractional value, use the non-symmetry feature of the controller to attain the required sampling rate.
In that case, the channel_bit_cnt value should be programmed with an integer that is closest to the fraction, but less than the
fraction.
The table below contains some examples for common sampling rates with CLK_SOURCE_I2S = 24 MHz:
I2S_NEW_TIMING[12:00]
(mark-space ratio:: Left_channel : Right_channel)
Sampling
Rate
CLK_DIVISOR=0 CLK_DIVISOR=1 CLK_DIVISOR=3 CLK_DIVISOR=5 CLK_DIVISOR=7
BIT_CLK=24 MHz BIT_CLK=12 MHz BIT_CLK=6 MHz BIT_CLK=4 MHz BIT_CLK=3 MHz
0x05DB 0x02ED 0x0176 0x00F9 0x10BB

8 KHz
(1500:1500) (750:750) (375:375) (250:250) (187:188)
0x0176 0x10BB 0x103E

32 KHz Not supported Not supported
(375:375) (187:188) (62:63)
0x010F 0x0087 0x0043 0x002C 0x0021

44.1 KHz
(272:272) (136:136) (68:68) (45:45) (34:34)
0x00F9 0x007C 0x103E

(250:250) (125:125) (62:63)
0x007C 0x103E 0x101F

(125:125) (62:63) (31:32)

Audio Hub
Notes:
 Ideally, any sampling rate can be generated, either accurately or approximately with any clk_src selected for I2S, if
the clk_divisor and the channel_bit_cnt are programmed accordingly.
 The NON_SYM.EN feature is meant to create the sampling rates approximately by realizing an odd bit rate with a
non-50:50 mark/space ratio. However, if the bit rate (2*channel_bit_cnt) itself is a fraction, the resultant sampling rate
will not be accurate. The entries shown as not supported in the above table are attributed to such a deviation.
 When the channel_bit_cnt is less than 32, the bit_size should be programmed to be less than channel_bit_cnt.
20.4.2.3 Programming I2S to Operate in Various Modes

After the module initialization (reset and clock programming), program the corresponding bits of the following registers.
Table 71: I2S Programming for Various Modes
Register Basic LJM RJM DSP PCM NW TDM
FRAME_FORMAT 0 0 0 1 1 1 1
LRCK_POLARITY 0 1 1 1 1 1 1
Number Number Number of Number Number Number

of bit of bit bits in left of bit of bit of bit
Number of bit clocks
CHANNEL_BIT_CNT clocks in clocks in channel + clocks clocks clocks
in left channel
left left right per per per
channel channel channel frame frame frame
1: Short
CHANNEL_BIT_CNT Fsync
TX_DATA_OFFSET 1 0 1 1 0/1/2
-BITS_PER_SAMPLE 0: Long
Fsync
1:short
CHANNEL_BIT_CNT Fsync
RX_DATA_OFFSET 1 0 – 1 1 0/1/2
BITS_PER_SAMPLE 0:Long
Fsync
Number Number 0: Short Bits per

of bit of bit Fsync
Number of bit clocks sample
FSYNC_WIDTH clocks in clocks in 1 0
in left channel 1: Long (slot
left left
Fsync size)
channel channel
HIGHZ_CTRL 0 0 0 0 2 2 0/1/2
EDGE_CTRL 0 0 0 0 1 1 1
TOTAL_SLOTS 0 0 0 1 0 3 0,1..7
SLOT_ENABLES 0x01 0x01 0x01 0x03 0x01 * **
* In NW mode, there can only be one active slot. So 0x01, 0x02, 0x04, 0x08 are allowed values.
** In TDM mode, there is no restriction on what/how many slots are enabled.
The only restriction on the programming sequence is that all other registers must be programmed first before the Tx/Rx
channels are enabled (which is done by setting XFER_EN_TX/XFER_EN_RX).

Audio Hub
20.4.2.4 Enabling I2S Interrupts

1. Enable the MONITOR_INT_EN bit in the I2S_FLOW_STATUS_0 register.
2. Enable the I2SX_TXCIF_OVERRUN and I2SX_RXCIF_UNDERRUN bits in the APBIF_I2S_INT_MASK_0 register.
20.4.2.5 General Guidelines

 Always enable I2S interrupts and monitor overruns in TxCIF and underruns in RxCIF. When any one of them occurs,
apply soft reset to I2S before using it again.
 Enable flow control only when the signals originate (at least partly) from one I2S and go through another I2S. Use the
AFC controller to do this.
20.5 Serial Peripheral Device Interface (S/PDIF)

This interface is primarily intended to carry audio data coded other than as linear PCM coded audio samples. Provisions are
also made to allow the interface to carry data related to computer software or signals coded using non-linear PCM. The format
specification for these applications is not part of this standard.
20.5.1 S/PDIF Features

 Fully implements the IEC-958 standard interface
 Provides mono and stereo support for sampling frequencies 32 kHz, 44.1 kHz, and 48 kHz
 Supports the following data formats.
- 16-bit
- 20-bit
- 24-bit
- Raw
 Supports “autolock” mode to automatically detect the “spdifin” sample rate and lock onto the data stream.
 Supports “override” mode to provide a manual control to sample the “spdifin” data stream.
 Provides a loopback mode to route the “spdifout” back to “spdifin” for self-testing.
20.5.2 S/PDIF Programming Guidelines
20.5.2.1 16-, 20-, 24-bit Modes

During transmission, the audio data is taken from the TX data FIFO, the channel status bit is taken from the TX channel status
page buffer, and the user status bit is from the TX user FIFO. The preamble bits are generated by the hardware. The Valid bit
is always zero.
During reception, the audio data is stored in the RX data FIFO, the channel status bit is stored in the RX channel status page
buffer and the user status bit is stored in the RX user FIFO.
In addition to storing the audio data, the RX data FIFO also stores the preamble bits, channel status bit, user status bit and the
valid bit. The reception of the channel bits start after the B-preamble is detected.
The audio-data sample has 16, 20, or 24 bits of data. Firmware has to transmit 16-, 20-, or 24-bit data and read 16-, 20-, or
24-bit data.

Audio Hub
20.5.2.2 Raw Mode

During transmission, the audio data, the preamble bits, channel status bits, the user bits, and the valid bits are transmitted
from the RX data FIFO. The firmware has to provide the correct preamble bits for the receiving device to synchronize with the
transmitter. The firmware has to provide preambles according to the following table:
Preceding State in the Parity Bit: 0/1
Table 72: Preamble Bits

Symbol Preamble Code Channel Coding Description
“B” (or “Z”) 0001/0001 11101000/00010111 Start of a block.
“M” (or “X”) 0010/0010 11100010/00011101 Start of sub-frame 1.
“W” (or “Y”) 0011/0011 11100100/00011011 Start of sub-frame 2.
During reception, the audio-data, the preamble bits, channel status bits, the user bits and the valid bits are stored in the RX
data FIFO. The user bit is also stored in the RX user FIFO. The channel bit is also stored in the RX channel status page buffer.
But the channel status bits are stored in the RX channel status page buffer only after the B-preamble is detected.

Audio Hub
Figure 51: S/PDIF Data Format for Raw Mode
0 3 4 7 8 27 28 29 30 31
SPDIF Input
Sync L M
Aux Audio Sample Word V U C P
Preamble S S
B B
0 3 4 7 8 27 28 29 30 31
L M
Audio Sample Word V U C P
S S
B B
0 3 4 7 8 27 28 29 30 31
L M
S S
B B 16 X
32-bit
FIFO
0 3 4 7 8 27 28 29 30 31
SPDIF
_DATA
L M _IN
S S
B B
0 3 4 7 8 27 28 29 30 31
L M
S S
B B
20.5.2.3 Module Reset

The application may initialize or reset the S/PDIF module via the clock and reset (CAR) control’s RST_DEVICES_L_0 register.
20.5.2.4 Clock Source/Divider Control

The SPDIFOUT clock source/divider can be selected by programming CAR’s CLK_SOURCE_SPDIF register. Refer to the
S/PDIF registers below for the needed input frequency for the desire output audio sample rate.
The SPDIFIN clock source/divider can be selected by programming CAR’s CLK_SOURCE_SPDIF register. Refer to the
SPDIF registers below for the needed oversample frequency.
20.5.2.5 Clock Enable Control

The application may enable the S/PDIF clocks by programming the CAR’s CLK_OUT_ENB_L_0 register.

Audio Hub
20.5.2.6 Detecting Incoming Sampling Rate

The SPDIFIN is capable of detecting and locking onto the ‘spdifin’ data stream regardless of the sample rate. It achieves this
by using an oversampling technique.
In addition to reading the sampling rate from the channel status information, one can also read the PERIOD field in the
STROBE_CTRL_0 register to estimate the incoming sample rate. The last two digits of PERIOD indicate the fractional clock
period.
Sample rate ≈ (‘spdifin’ clock frequency * 1000) / (PERIOD * 128)
If using the PERIOD method, it is better to read this field toward the end of the song or just before turning off the SPDIFIN.
Although the hardware can lock onto the SPDIFIN data stream in as little as 2 subframes of time, the hardware is actually
constantly re-adjusting itself (due to jitter, synchronization loss, etc. in the data stream) to provide the strobe point to the center
of the biphase data stream. Over time, the strobe point will vary less and less because the hardware has already adjusted to
all the variations seen in the data stream.
20.5.2.7 S/PDIF Transmit Data Flow

Make sure that the TX_FIFO is filled before enabling the transmission by setting the TX_EN field of CTRL_0 register. Never
allow the TX_FIFO to go empty at any time during transmission. The interrupt is generated when the Tx Data FIFO empty
count is greater than the Tx DATA attention value (TX_ATN_LVL field of DATA_FIFO_CSR_0 register) if the Tx interrupt
enable is set.
20.5.2.8 S/PDIF Receive Data Flow

To enable the reception of RX_FIFO, set the RX_EN field of the CTRL_0 register. Never allow the RX_FIFO to become full at
any time during reception. The interrupt is generated when the Rx Data FIFO data count is greater than the Rx DATA attention
value (RX_ATN_LVL field of the DATA_FIFO_CSR register), if the Rx interrupt enable bit is set.
20.5.2.9 Method of Filling/Retrieve Data from TX/RX User/Data FIFO

Use the DMA method by programming the APB DMA and APBIF registers. With this method, the FIFO attention levels need to
be set in the APBIF just like in method 2. But instead of enabling interrupts when the FIFO attention level is reached, one
should program the APB DMA registers. Now, every time the attention level is reached, a DMA request will be generated by
the APBIF to the APB DMA and the APB DMA will perform the data moving task from/to APBIF FIFOs to the AHB bus.
20.6 Digital Audio Mixers

The digital audio mixers (DAMs) can mix up to two input stereo streams of different frame rates and sample sizes and produce
one output audio stream.
The Sample Rate Converter converts the frame rate of one of the input channels using a collection of Low-Latency Filters
(LLFs):
 Input/output frequencies supported: 8, 11.025, 16, 22.05, 44.1, 48, 88.2, 96, 176.4, and192kHz
 Mono/Stereo audio for both input channels is supported. Stereo SRC is supported for channel 0. Channel 1, which is
the bypass channel, does not support SRC.
 Up-conversion and down-conversion from any supported frequency to any supported frequency
 8-, 16-, 24-, 32-bit audio data
 Fixed latency on round trip between baseband and codec of ~7 ms.
The bit-width converter at the CIF should convert the input stream to 32 bits because SRC operates only on 32-bit data
A programmable gain controller is available in both input channels. It can be programmed to give a linear gain between -8 and
7.9998.

Audio Hub
The DAM Mixer mixes the output from channel 0 (stereo SRC channel) with channel 1 (bypass channel). The Mixer handles
saturation and has the following mixing options:
 Both channels wait on each other
 Channels wait on none
 Channel 0 waits on channel 1
 Channel 1 waits on channel 0
20.6.1 DAM Programming Guidelines

1. Program the CLK_RST_CONTROLLER_CLK_OUT_ENB_V register to enable the DAM clock.
2. Program CLK_RST_CONTROLLER_CLK_SOURCE_DAM0_0 (for DAM0) and similar registers for other instances to
program the DAM clock source. Set the DAM0_CLK_SRC field to CLK_SRC_ALT, if an alternate clock source is
needed followed by setting DAM0_CLK_SRC_RATE to choose the DAM alternate clock source.
3. Deassert DAM0 and AUDIO reset by programming the CLK_RST_CONTROLLER_RST_DEVICES_V register.
4. Poll for this bit to clear.
5. Configure the CIF registers (DAM_AUDIOCIF_CH0_CTRL_0, DAM_AUDIOCIF_CH1_CTRL_0, and
DAM_AUDIOCIF_OUT_CTRL_0) according to the guideline given in the ACIF Programming Guidelines subsection.
6. Set the input FSIN by programming DAM_CH0_CTRL for channel 0 and DAM_CH1_CTRL for channel1.
7. Set the Gain for both the channels by setting DAM_CH0_CONV and DAM_CH1_CONV for both channel 0 and
channel 1, respectively.
8. Enable the DAM output by setting FSOUT into the DAM_CTRL register.
9. If the use case needs a farrow filter in its pipeline, enable the farrow filter by configuring the DAM_FARROW_PARAM
register.
10. Software can manually program the coefficient RAM by setting the COEF_RAM_EN bit to 0 in the DAM_CH0_CTRL
register. The values for each of the 8 use cases are stored statically in hardware and can be accessed without any
software programming by setting COEF_RAM_EN bit to 1 in DAM_CH0_CTRL register.
- For programming the coefficient RAM with the HW_ADR_EN bit unset in the DAM_AUDIORAMCTL_DAM_CTRL
register, set the coefficient RAM offset in the RAM_ADR field of the DAM_AUDIORAMCTL_DAM_CTRL register
and set data in the DATA field in DAM_AUDIORAMCTL_DAM_DATA.
- For programming the coefficient RAM with the HW_ADR_EN bit set in the DAM_AUDIORAMCTL_DAM_CTRL
register, set the coefficient RAM offset in the RAM_ADR field of the DAM_AUDIORAMCTL_DAM_CTRL register
to 0 and set data in DATA field in DAM_AUDIORAMCTL_DAM_DATA. Hardware auto-increments RAM_ADR
after each write.
11. For channel mixing, the DATA_SYNC field in both DAM_CH0_CTRL and DAM_CH1_CTRL have to be configured
correctly to have mixing in 4 available modes:
- Ch0 wait on Ch1
- Ch1 wait on Ch0
- Both channels wait on each other (preferred option)
- Channels do not wait
12. Set STEREO_SRC_EN in the DAM_CTRL register to enable stereo SRC.
13. Enable the DAM by setting the ENABLE bit in DAM_CTRL.
For details on the fields within each DAM register, refer to the “DAM Registers” subsection.
20.7 Audio Multiplexer Block (AMX)

The Audio Multiplexer Block (AMX) can multiplex up to 4 input streams of up to 16 channels each and generate an output
stream of up to 16 channels
A “byte RAM” helps to form an output frame by any combination of bytes from the 4 input frames

Audio Hub
Two modes for data synchronization between input frames are available:
 Wait For All mode: At the beginning, wait for all enabled input streams to have data before forming the very first
frame.
 Wait for Any mode: Start whenever data is available in any one of the enabled input streams.
In either mode, once the first output frame is sent out, AMX always waits for all active streams to have data available before
forming and sending subsequent frames.
20.7.1 AMX Programming Guidelines

1. Configure Audio CIF control registers AMX_AUDIOCIF_CH0_CTRL, AMX_AUDIOCIF_CH1_CTRL,
AMX_AUDIOCIF_CH2_CTRL, AMX_AUDIOCIF_CH3_CTRL, and AMX_AUDIOCIF_OUT_CTRL according to the
guidelines given in the ACIF Programming Guidelines subsection.
2. Configure the CH_DEP parameter field in the AMX_CTRL_0 register to determine whether to wait for all enabled
channels to have data before transfer or start sending the data when any one of the input channels has data
(WT_ON_ALL & WT_ON_ANY).
3. Configure the MSTR_CH_NUM register for designated master channel, so that if the data is available on a particular
channel, the output can be sent.
4. Enable the AMX output by setting BYTE_EN in AMX_OUT_BYTE_EN0 and AMX_OUT_BYTE_EN1.
5. For Byte RAMCTL programming:
- For programming RAM with the HW_ADR_EN bit cleared in the AMX_AUDIORAMCTL_AMX_CTRL register, set
the RAM offset in the RAM_ADR field of the AMX_AUDIORAMCTL_AMX_CTRL register and set data in the
DATA field in the AMX_AUDIORAMCTL_AMX_DATA register.
- For programming RAM with the HW_ADR_EN bit set in the AMX_AUDIORAMCTL_AMX_CTRL register, set the
RAM offset in the RAM_ADR field of the AMX_AUDIORAMCTL_AMX_CTRL register to 0 and set data in the
DATA field in the AMX_AUDIORAMCTL_AMX_DATA register. Hardware auto-increments the RAM_ADR after
each write.
20.8 Demultiplexer Block (ADX)

The demultiplexer block (ADX) takes an input stream with up to 16 channels and demultiplexes it into four output streams of
up to 16 channels each.
A “byte RAM” helps to form output frames by any combination of bytes from the input frame. Its design is identical to that of the
byte RAM in the AMX except that the data flow direction is reversed.
20.8.1 ADX Programming Guidelines

1. Configure the Audio CIF control registers ADX_AUDIOCIF_IN_CTRL, ADX_AUDIOCIF_CH0_CTRL,
ADX_AUDIOCIF_CH1_CTRL, ADX_AUDIOCIF_CH2_CTRL, and ADX_AUDIOCIF_CH3_CTRL according to the
guidelines given in the ACIF Programming Guidelines subsection.
2. Configure ADX_OUT_CH_CTRL_0 for enabling or disabling four output channels.
3. Enable the ADX input by setting BYTE_EN in ADX_IN_BYTE_EN0 and ADX_IN_BYTE_EN1, respectively.
4. Byte RAMCTL:
For programming RAM with the HW_ADR_EN bit cleared in the ADX_AUDIORAMCTL_ADX_CTRL register, set the
RAM offset in the RAM_ADR field of the ADX_AUDIORAMCTL_ADX_CTRL register, and set data in the DATA field
in the ADX_AUDIORAMCTL_ADX_DATA register.
For programming RAM with the HW_ADR_EN bit set in the ADX_AUDIORAMCTL_ADX_CTRL register, set the RAM
offset in the RAM_ADR field of the ADX_AUDIORAMCTL_ADX_CTRL register to 0, and set data in DATA field in the
ADX_AUDIORAMCTL_ADX_DATA register. Hardware auto-increments RAM_ADR after each write.

Audio Hub
20.9 Audio Flow Controller (AFC)

The audio flow controller (AFC) can control the flow of traffic between two I2S interfaces running at different clocks that are up
to 100ppm apart.
The AFC implements high fidelity interpolation and decimation algorithms that compensate for clock differences.
It can control traffic flow anywhere in the audio route, even to the inputs of AMX blocks.
The AFC can handle burst traffic from DAMs.
20.9.1 AFC Programming Guidelines

1. Program the AFC_AUDIOCIF_AFCTX_CTRL_0 and AFC_AUDIOCIF_AFCRX_CTRL_0 registers according to the
programming guidelines given in the ACIF Programming Guidelines subsection.
2. Program the START_THRESHOLD, HIGH_THRESHOLD, and LOW_THRESHOLD registers depending on the use
case as shown in the following table.
Note: In the table, the numbers in parentheses are example values.
Destination I2S FIFO

Threshold
Use Case AFC_THRESHOLDS_I2S_0 AFC_THRESHOLDS_AFC_0 (To be Programmed in
I2S_AUDIOCIF_I2SRX_CTR
L_0. FIFO_THRESHOLD)
Actual Value HIGH_ START_ LOW_ HIGH_ START_ LOW_

(Typical Value) THRESHOLD THRESHOLD THRESHOLD THRESHOLD THRESHOLD THRESHOLD
START_ START_ START_ START_ START_THRESHOLD + 1

THRESHOLD THRESHOLD START_ START_
THRESHOLD+ THRESHOLD (AFC_THRESHOLDS_
I2S  AFC  I2S 1 +1
THRESHOLD THRESHOLD- 1
-1 I2S_0)
(7) (6)
(8) (7) (6) (8) (8)
START_THRESHOLD + 1
2*SRC-BURST 1*SRC-BURST 1*SRC- 1*SRC- 1*SRC-BURST 1*SRC-BURST
I2S  DAM  AFC  I2S (AFC_THRESHOLDS_
+1 +2 BURST BURST + 1 +1 +1
I2S_0)
START_ START_ START_ START_ Start Threshold + 1

START_ THRESHOLD THRESHOLD THRESHOLD START_
THRESHOLD+ (AFC_THRESHOLDS_
I2S  AFC  AMX  I2S 1
THRESHOLD THRESHOLD- 1
-1 +1 I2S_0)
(7) (6)
(8) (6) (8) (7) (8)
START_THRESHOLD + 1
I2S  DAM  AFC  AMX 2*SRC-BURST 1*SRC-BURST 1*SRC- 2*SRC- 1*SRC-BURST
(4) (AFC_THRESHOLDS_
 I2S +1 +2 BURST BURST + 4 +4
I2S_0)
20.10 Audio Hub Registers

20.10.1 Audio Crossbar Registers

The following macro defines a register for each RX port. No more than one field can be 1 in a register because an RX port can
receive from only one TX port.
Example:
reg DAM0_RX0 incr4
0:0 DAM0_TX0 rw i=0
1:1 I2S0_TX0 rw i=0
2:2 I2S1_TX0 rw i=0
;

Audio Hub
20.10.1.1 AUDIO_APBIF_RXn_0
There are 10 Audio APBIF RX Registers, one per RX port (n = 0 through 9).
For n = 0 through 3: Offset: 0x0 + (n * 0x4) | Read/Write: R/W | Reset: 0x00000000

(0bxxxxxxx0000000000000000000000000)
For n = 4 through 9: Offset: 0x44 + (n * 0x4) | Read/Write: R/W | Reset: 0x00000000

(0bxxxxxxx0000000000000000000000000)
ADX0_TX3:
24 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX2:
23 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX1:
22 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX0:
21 0x0 0 = DISABLE
1 = ENABLE
AMX0_TX0:
20 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX9:
19 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX8:
18 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX7:
17 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX6:
16 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX5:
15 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX4:
14 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX1
13 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX0
12 0x0 0 = DISABLE
1 = ENABLE
DAM2_TX0
11 0x0 0 = DISABLE
1 = ENABLE
DAM1_TX0
10 0x0 0 = DISABLE
1 = ENABLE

Audio Hub
DAM0_TX0
9 0x0 0 = DISABLE
1 = ENABLE
I2S4_TX0
8 0x0 0 = DISABLE
1 = ENABLE
I2S3_TX0
7 0x0 0 = DISABLE
1 = ENABLE
I2S2_TX0
6 0x0 0 = DISABLE
1 = ENABLE
I2S1_TX0
5 0x0 0 = DISABLE
1 = ENABLE
I2S0_TX0
4 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX3
3 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX2
2 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX1
1 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX0
0 0x0 0 = DISABLE
1 = ENABLE
20.10.1.2 AUDIO_I2Sn_RX0_0
There are 5 Audio I2S RX0 Registers, one per I2S channel (n = 0 through 4).
Offset: 0x10 + (n * 0x4) | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxx0000000000000000000000000)
ADX0_TX3:
24 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX2:
23 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX1:
22 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX0:
21 0x0 0 = DISABLE
1 = ENABLE
AMX0_TX0:
20 0x0 0 = DISABLE
1 = ENABLE

Audio Hub
APBIF_TX9:
19 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX8:
18 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX7:
17 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX6:
16 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX5:
15 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX4:
14 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX1
13 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX0
12 0x0 0 = DISABLE
1 = ENABLE
DAM2_TX0
11 0x0 0 = DISABLE
1 = ENABLE
DAM1_TX0
10 0x0 0 = DISABLE
1 = ENABLE
DAM0_TX0
9 0x0 0 = DISABLE
1 = ENABLE
I2S4_TX0
8 0x0 0 = DISABLE
1 = ENABLE
I2S3_TX0
7 0x0 0 = DISABLE
1 = ENABLE
I2S2_TX0
6 0x0 0 = DISABLE
1 = ENABLE
I2S1_TX0
5 0x0 0 = DISABLE
1 = ENABLE
I2S0_TX0
4 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX3
3 0x0 0 = DISABLE
1 = ENABLE
2 0x0 APBIF_TX2

Audio Hub

0 = DISABLE
1 = ENABLE
APBIF_TX1
1 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX0
0 0x0 0 = DISABLE
1 = ENABLE
20.10.1.3 AUDIO_DAMn_RX0_0
There are 3 Audio DAMn RX0 Registers for the RX0 port (n = 0 through 2).
ADX0_TX3:
24 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX2:
23 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX1:
22 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX0:
21 0x0 0 = DISABLE
1 = ENABLE
AMX0_TX0:
20 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX9:
19 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX8:
18 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX7:
17 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX6:
16 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX5:
15 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX4:
14 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX1
13 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX0
12 0x0
0 = DISABLE

Audio Hub

1 = ENABLE
DAM2_TX0
11 0x0 0 = DISABLE
1 = ENABLE
DAM1_TX0
10 0x0 0 = DISABLE
1 = ENABLE
DAM0_TX0
9 0x0 0 = DISABLE
1 = ENABLE
I2S4_TX0
8 0x0 0 = DISABLE
1 = ENABLE
I2S3_TX0
7 0x0 0 = DISABLE
1 = ENABLE
I2S2_TX0
6 0x0 0 = DISABLE
1 = ENABLE
I2S1_TX0
5 0x0 0 = DISABLE
1 = ENABLE
I2S0_TX0
4 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX3
3 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX2
2 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX1
1 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX0
0 0x0 0 = DISABLE
1 = ENABLE
20.10.1.4 AUDIO_DAMn_RX1_0
There are 3 Audio DAMn RX1 Registers for the RX1 port (n = 0 through 2).
ADX0_TX3:
24 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX2:
23 0x0 0 = DISABLE
1 = ENABLE
22 0x0 ADX0_TX1:

Audio Hub

0 = DISABLE
1 = ENABLE
ADX0_TX0:
21 0x0 0 = DISABLE
1 = ENABLE
AMX0_TX0:
20 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX9:
19 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX8:
18 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX7:
17 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX6:
16 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX5:
15 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX4:
14 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX1
13 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX0
12 0x0 0 = DISABLE
1 = ENABLE
DAM2_TX0
11 0x0 0 = DISABLE
1 = ENABLE
DAM1_TX0
10 0x0 0 = DISABLE
1 = ENABLE
DAM0_TX0
9 0x0 0 = DISABLE
1 = ENABLE
I2S4_TX0
8 0x0 0 = DISABLE
1 = ENABLE
I2S3_TX0
7 0x0 0 = DISABLE
1 = ENABLE
I2S2_TX0
6 0x0 0 = DISABLE
1 = ENABLE
I2S1_TX0
5 0x0 0 = DISABLE
1 = ENABLE

Audio Hub
I2S0_TX0
4 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX3
3 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX2
2 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX1
1 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX0
0 0x0 0 = DISABLE
1 = ENABLE
20.10.1.5 AUDIO_SPDIF_RXn_0
There are 2 Audio SPDIF RX Registers, one per RX port (n = 0 through 1).
Offset: 0x3c + (n * 0x04) | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxx0000000000000000000000000)
ADX0_TX3:
24 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX2:
23 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX1:
22 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX0:
21 0x0 0 = DISABLE
1 = ENABLE
AMX0_TX0:
20 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX9:
19 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX8:
18 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX7:
17 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX6:
16 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX5:
15 0x0 0 = DISABLE
1 = ENABLE
14 0x0 APBIF_TX4:

Audio Hub

0 = DISABLE
1 = ENABLE
SPDIF_TX1:
13 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX0:
12 0x0 0 = DISABLE
1 = ENABLE
DAM2_TX0:
11 0x0 0 = DISABLE
1 = ENABLE
DAM1_TX0:
10 0x0 0 = DISABLE
1 = ENABLE
DAM0_TX0:
9 0x0 0 = DISABLE
1 = ENABLE
I2S4_TX0:
8 0x0 0 = DISABLE
1 = ENABLE
I2S3_TX0:
7 0x0 0 = DISABLE
1 = ENABLE
I2S2_TX0:
6 0x0 0 = DISABLE
1 = ENABLE
I2S1_TX0:
5 0x0 0 = DISABLE
1 = ENABLE
I2S0_TX0:
4 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX3:
3 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX2:
2 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX1:
1 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX0:
0 0x0 0 = DISABLE
1 = ENABLE
20.10.1.6 AUDIO_AMX0_RXn_0
There are 4 Audio AMX0 RX Registers, one per RX port (n = 0 through 3).
Offset: 0x5c + (n * 0x04) │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxx0000000000000000000000000)
ADX0_TX3:
24 0x0 0 = DISABLE
1 = ENABLE

Audio Hub
ADX0_TX2:
23 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX1:
22 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX0:
21 0x0 0 = DISABLE
1 = ENABLE
AMX0_TX0:
20 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX9:
19 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX8:
18 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX7:
17 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX6:
16 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX5:
15 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX4:
14 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX1:
13 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX0:
12 0x0 0 = DISABLE
1 = ENABLE
DAM2_TX0:
11 0x0 0 = DISABLE
1 = ENABLE
DAM1_TX0:
10 0x0 0 = DISABLE
1 = ENABLE
DAM0_TX0:
9 0x0 0 = DISABLE
1 = ENABLE
I2S4_TX0:
8 0x0 0 = DISABLE
1 = ENABLE
I2S3_TX0:
7 0x0 0 = DISABLE
1 = ENABLE
I2S2_TX0:
6 0x0 0 = DISABLE
1 = ENABLE

Audio Hub
I2S1_TX0:
5 0x0 0 = DISABLE
1 = ENABLE
I2S0_TX0:
4 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX3:
3 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX2:
2 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX1:
1 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX0:
0 0x0 0 = DISABLE
1 = ENABLE
20.10.1.7 AUDIO_ADX0_RX0_0
Offset: 0x6c │ Read/Write: R/W │ Reset: 0x00000000 (0bxxxxxxx0000000000000000000000000)
ADX0_TX3:
24 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX2:
23 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX1:
22 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX0:
21 0x0 0 = DISABLE
1 = ENABLE
AMX0_TX0:
20 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX9:
19 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX8:
18 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX7:
17 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX6:
16 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX5:
15 0x0 0 = DISABLE
1 = ENABLE

Audio Hub
APBIF_TX4:
14 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX1:
13 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX0:
12 0x0 0 = DISABLE
1 = ENABLE
DAM2_TX0:
11 0x0 0 = DISABLE
1 = ENABLE
DAM1_TX0:
10 0x0 0 = DISABLE
1 = ENABLE
DAM0_TX0:
9 0x0 0 = DISABLE
1 = ENABLE
I2S4_TX0:
8 0x0 0 = DISABLE
1 = ENABLE
I2S3_TX0:
7 0x0 0 = DISABLE
1 = ENABLE
I2S2_TX0:
6 0x0 0 = DISABLE
1 = ENABLE
I2S1_TX0:
5 0x0 0 = DISABLE
1 = ENABLE
I2S0_TX0:
4 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX3:
3 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX2:
2 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX1:
1 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX0:
0 0x0 0 = DISABLE
1 = ENABLE
20.10.1.8 AUDIO_BBC1_RXn_0
There are 2 Audio BBC1 RX registers, one per RX port (n = 0 through 1).
24 0x0 ADX0_TX3:
0 = DISABLE

Audio Hub

1 = ENABLE
ADX0_TX2:
23 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX1:
22 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX0:
21 0x0 0 = DISABLE
1 = ENABLE
AMX0_TX0:
20 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX9:
19 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX8:
18 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX7:
17 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX6:
16 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX5:
15 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX4:
14 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX1:
13 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX0:
12 0x0 0 = DISABLE
1 = ENABLE
DAM2_TX0:
11 0x0 0 = DISABLE
1 = ENABLE
DAM1_TX0:
10 0x0 0 = DISABLE
1 = ENABLE
DAM0_TX0:
9 0x0 0 = DISABLE
1 = ENABLE
I2S4_TX0:
8 0x0 0 = DISABLE
1 = ENABLE
I2S3_TX0:
7 0x0 0 = DISABLE
1 = ENABLE
6 0x0 I2S2_TX0:
0 = DISABLE

Audio Hub

1 = ENABLE
I2S1_TX0:
5 0x0 0 = DISABLE
1 = ENABLE
I2S0_TX0:
4 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX3:
3 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX2:
2 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX1:
1 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX0:
0 0x0 0 = DISABLE
1 = ENABLE
20.10.1.9 AUDIO_AMX1_RXn_0
There are 4 Audio AMX1 RX Registers, one per RX port (n = 0 through 3).
ADX0_TX3:
24 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX2:
23 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX1:
22 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX0:
21 0x0 0 = DISABLE
1 = ENABLE
AMX0_TX0:
20 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX9:
19 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX8:
18 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX7:
17 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX6:
16 0x0 0 = DISABLE
1 = ENABLE

Audio Hub
APBIF_TX5:
15 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX4:
14 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX1:
13 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX0:
12 0x0 0 = DISABLE
1 = ENABLE
DAM2_TX0:
11 0x0 0 = DISABLE
1 = ENABLE
DAM1_TX0:
10 0x0 0 = DISABLE
1 = ENABLE
DAM0_TX0:
9 0x0 0 = DISABLE
1 = ENABLE
I2S4_TX0:
8 0x0 0 = DISABLE
1 = ENABLE
I2S3_TX0:
7 0x0 0 = DISABLE
1 = ENABLE
I2S2_TX0:
6 0x0 0 = DISABLE
1 = ENABLE
I2S1_TX0:
5 0x0 0 = DISABLE
1 = ENABLE
I2S0_TX0:
4 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX3:
3 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX2:
2 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX1:
1 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX0:
0 0x0 0 = DISABLE
1 = ENABLE
20.10.1.10 AUDIO_ADX1_RX0_0
Offset: 0x88 | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxx0000000000000000000000000)

Audio Hub
ADX0_TX3:
24 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX2:
23 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX1:
22 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX0:
21 0x0 0 = DISABLE
1 = ENABLE
AMX0_TX0:
20 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX9:
19 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX8:
18 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX7:
17 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX6:
16 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX5:
15 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX4:
14 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX1:
13 0x0 0 = DISABLE
1 = ENABLE
SPDIF_TX0:
12 0x0 0 = DISABLE
1 = ENABLE
DAM2_TX0:
11 0x0 0 = DISABLE
1 = ENABLE
DAM1_TX0:
10 0x0 0 = DISABLE
1 = ENABLE
DAM0_TX0:
9 0x0 0 = DISABLE
1 = ENABLE
I2S4_TX0:
8 0x0 0 = DISABLE
1 = ENABLE
I2S3_TX0:
7 0x0 0 = DISABLE
1 = ENABLE

Audio Hub
I2S2_TX0:
6 0x0 0 = DISABLE
1 = ENABLE
I2S1_TX0:
5 0x0 0 = DISABLE
1 = ENABLE
I2S0_TX0:
4 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX3:
3 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX2:
2 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX1:
1 0x0 0 = DISABLE
1 = ENABLE
APBIF_TX0:
0 0x0 0 = DISABLE
1 = ENABLE
20.10.1.11 AUDIO_AFCn_RX0_0
There are 6 Audio AFCn RX Registers for the RX0 port (n = 0 through 5).
Offset: 0x8c + (n * 0x04) | Read/Write: R/W | Reset: 0x00000000 (0bxxxxxxx0000000000000000000000000)
ADX0_TX3:
24 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX2:
23 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX1:
22 0x0 0 = DISABLE
1 = ENABLE
ADX0_TX0:
21 0x0 0 = DISABLE

TegraK1 TRM DP06905001 Public v03p

Uploaded by

Copyright:

Available Formats

TegraK1 TRM DP06905001 Public v03p

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

TegraK1 TRM DP06905001 Public v03p

Uploaded by

Copyright:

Available Formats

TECHNICAL REFERENCE MANUAL

NVIDIA Tegra K1 Mobile Processor

v03p OCT 15, 2014 • Activity Monitor/HDMI: New sections.

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 2

7.8 Timers Registers......................................................................................................................................... 258

12.9 Host SYNC Registers ............................................................................................................................... 558

19.2 USB 2.0 Controllers and Interfaces .......................................................................................................... 974

21.15 Window D (WIN_D) Registers .............................................................................................................. 1683

25.3 CEC Registers ........................................................................................................................................ 1954

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 7

30.0 SNOR (GMI) Controller .............................................................................................................................. 2115

37.2 Thermal Sensor ...................................................................................................................................... 2459

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 9

[THIS PAGE INTENTIONALLY LEFT BLANK]

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 10

1.1 The Role of the Technical Reference Manual

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 11

1.2 Block Diagram

Figure 1: Tegra K1 Processor Block Diagram

PPSB Low Latency Register Bus (32-bit)

ARM7 Crossbar Processor Data Bus

APB Peripheral Bus (32-bit)

VCP2 32-bit I2C Master/Slave

Kepler AXI>C11(ACB) ARM7TDMI-S 32-bit Controller PWFM

Graphics HOST (HOST1X) USB2

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 12

1.3 Memory Controller and Internal Bus Architecture

There is a three-level hierarchy of memory clients:

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 13

1.4 Reading Register Tables

32-bit Power-on reset Default provided if different

Bit R/W Reset Description

19:16 RO D64MB EMEM_DEVSIZE

At power-on reset, write only the 9:8 RW W2 EMEM_BANKWIDTH

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 14

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 15

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 16

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 17

[THIS PAGE INTENTIONALLY LEFT BLANK]

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 18

2.0 ADDRESS MAP

2.1 System Address Map

Table 1: System Address Map

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 19

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 20

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 21

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 22

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 23

TEGRA K1 | TRM | DP-06905-001_v03p | SUBJECT TO CHANGE WITHOUT NOTICE | www.nvidia.com 24

2.2 Available DRAM Address Ranges

Table 2: DRAM Address Ranges

AHB_A2 7C00_0000 - 7DFF_FFFF 32 Always MMIO MMIO MMIO MMIO MMIO No No

AHB_A1 7800_0000 - 78FF_FFFF 16 Selectable MMIO MMIO MMIO MMIO No No

APB 7000_0000 - 70FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No

ExtIO 6800_0000 - 68FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No

PPSB 6000_0000 - 60FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No

Graphics Host rsvd + + +

DRAM/ DRAM/ DRAM/ DRAM/ Yes if no Yes if no

IRAM 4000_0000 - 40FF_FFFF 16 Always MMIO MMIO MMIO MMIO MMIO No No