25AA640/25LC640: 64K SPI Bus Serial EEPROM

2008 Microchip Technology Inc.
DS21223H-page 1
25AA640/25LC640
Device Selection Table
Features:
Low-Power CMOS Technology
- Write current: 3 mA, typical
- Read current: 500 A, typical
- Standby current: 500 nA, typical
8192 x 8 Bit Organization
32 Byte Page
Write Cycle Time: 5 ms max.
Self-Timed Erase and Write Cycles
Block Write Protection
- Protect none, 1/4, 1/2 or all of array
Built-in Write Protection
- Power on/off data protection circuitry
- Write enable latch
- Write-protect pin
Sequential Read
High Reliability
- Data retention: > 200 years
- ESD protection: > 4000V
8-pin PDIP, SOIC and TSSOP Packages
Temperature Ranges Supported:
- Industrial (I): -40C to +85C
- Automotive (E): -40C to +125C
Description:
The Microchip Technology Inc. 25AA640/25LC640
(25XX640
*
) is a 64 Kbit Serial Electrically Erasable
PROM [EEPROM]. The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
Block Diagram
Package Types
Part
Number
VCC
Range
Max Clock
Frequency
Temp
Ranges
25AA640 1.8-5.5V 1 MHz I
25LC640 2.5-5.5V 2 MHz I
25LC640 4.5-5.5V 3/2.5 MHz I, E
SI
SO
SCK
CS
HOLD
WP
I/O Control
Memory
Control
Logic
HV Generator
EEPROM
Array
Page
Y Decoder
Sense Amp.
R/W Control
Logic
VCC
VSS
Latches
XDEC
STATUS
Register
2
5
X
X
6
4
0
2
5
X
X
6
4
0
PDIP/SOIC
TSSOP
CS
SO
WP
VSS
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
HOLD
VCC
CS
SO
SCK
SI
VSS
WP
64K SPI Bus Serial EEPROM
*25XX640 is used in this document as a generic part number for the 25AA640/25LC640 devices.
Not recommended for new designs
Please use 25AA640A or 25LC640A.
25AA640/25LC640
DS21223H-page 2 2008 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
()
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V
Storage temperature .................................................................................................................................-65C to 150C
Ambient temperature under bias...............................................................................................................-65C to 125C
ESD protection on all pins.......................................................................................................................................... 4 kV
TABLE 1-1: DC CHARACTERISTICS
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
DC CHARACTERISTICS
Industrial (I): TA = -40C to +85C VCC = 1.8V to 5.5V
Automotive (E): TA = -40C to +125C VCC = 4.5V to 5.5V
Param.
No.
Sym Characteristics Min Max Units Conditions
D1 VIH1 High-level input
voltage
2.0 VCC + 1 V VCC 2.7V (Note 1)
D2 VIH2 0.7 VCC VCC + 1 V VCC < 2.7V (Note 1)
D3 VIL1 Low-level input
voltage
-0.3 0.8 V VCC 2.7V (Note 1)
D4 VIL2 -0.3 0.2 VCC V VCC < 2.7V (Note 1)
D5 VOL Low-level output
voltage
0.4 V IOL = 2.1 mA
0.2 V IOL = 1.0 mA, VCC = < 2.5V
D6 VOH High-level output
voltage
VCC - 0.5 V IOH = -400 A
D7 ILI Input leakage current 1 A CS = VCC, VIN = VSS TO VCC
D8 ILO Output leakage
current
1 A CS = VCC, VOUT = VSS TO VCC
D9 CINT Internal Capacitance
(all inputs and
outputs)
7 pF TA = 25C, CLK = 1.0 MHz,
VCC = 5.0V (Note 1)
D10 ICC Read Operating Current
1
500
mA
A
VCC = 5.5V; FCLK = 3.0 MHz;
SO = Open
VCC = 2.5V; FCLK = 2.0 MHz;
SO = Open
D11 ICC Write
5
3
mA
mA
VCC = 5.5V
VCC = 2.5V
D12 ICCS Standby Current
5
1
A
A
CS = VCC = 5.5V, Inputs tied to VCC or
VSS
CS = VCC = 2.5V, Inputs tied to VCC or
VSS
Note 1: This parameter is periodically sampled and not 100% tested.
2008 Microchip Technology Inc. DS21223H-page 3
25AA640/25LC640
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I): TA = -40C to +85C VCC = 1.8V to 5.5V
Automotive (E): TA = -40C to +125C VCC = 4.5V to 5.5V
Param.
No.
Sym Characteristic Min Max Units Conditions
1 FCLK Clock Frequency
3
2
1
MHz
MHz
MHz
VCC = 4.5V to 5.5V (Note 2)
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
2 TCSS CS Setup Time 100
250
500
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
3 TCSH CS Hold Time 150
250
475
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
4 TCSD CS Disable Time 500 ns
5 TSU Data Setup Time 30
50
50
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
6 THD Data Hold Time 50
100
100
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
7 TR CLK Rise Time 2 s (Note 1)
8 TF CLK Fall Time 2 s (Note 1)
9 THI Clock High Time 150
230
475
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
10 TLO Clock Low Time 150
230
475
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
11 TCLD Clock Delay Time 50 ns
12 TCLE Clock Enable Time 50 ns
13 TV Output Valid from
Clock Low
150
230
475
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
14 THO Output Hold Time 0 ns (Note 1)
15 TDIS Output Disable Time
200
250
500
ns
ns
ns
16 THS HOLD Setup Time 100
100
200
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
17 THH HOLD Hold Time 100
100
200
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
18 THZ HOLD Low to Output
High-Z
100
150
200
ns
ns
ns
19 THV HOLD High to Output
Valid
100
150
200
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
VCC = 1.8V to 5.5V
20 TWC Internal Write Cycle
Time
5 ms
21 Endurance 1M E/W
Cycles
(Note 3)
Note 1: This parameter is periodically sampled and not 100% tested.
2: FCLK max. = 2.5 MHz for TA > 85C.
3: This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance Model which can be obtained from Microchips web site at: www.microchip.com.
25AA640/25LC640
FIGURE 1-1: HOLD TIMING
FIGURE 1-2: SERIAL INPUT TIMING
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
SCK
SO
SI
HOLD
17 16 16 17
19 18
Dont Care
5
High-Impedance
n + 2 n + 1 n n - 1 n
n + 2 n + 1 n n n - 1
CS
SCK
SI
SO
6 5
8
7
11
3
LSB In MSB In
High-Impedance
12
Mode 1,1
Mode 0,0
4
2
CS
SCK
SO
10 9
13
MSB Out LSB Out
3
15
Dont Care
SI
Mode 1,1
Mode 0,0
14
25AA640/25LC640
TABLE 1-3: AC TEST CONDITIONS FIGURE 1-4: AC TEST CIRCUIT
AC Waveform:
VLO = 0.2V
VHI = VCC 0.2V (Note 1)
VHI = 4.0V (Note 2)
Timing Measurement Reference Level
Input 0.5 VCC
Output 0.5 VCC
Note 1: For VCC 4.0V
2: For VCC > 4.0V
VCC
SO
100 pF
1.8 k
2.25 k
25AA640/25LC640
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high, or remains
high during a program cycle, the device will go into
Standby mode when the programming cycle is
complete. When the device is deselected, SO goes to
the high-impedance state, allowing multiple parts to
share the same SPI bus. A low-to-high transition on CS
after a valid write sequence initiates an internal write
cycle. After power-up, a high-to-low transition on CS is
required prior to any sequence being initiated.
2.2 Serial Output (SO)
The SO pin is used to transfer data out of the 25XX640.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
2.3 Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP is low and
WPEN is high, writing to the nonvolatile bits in the STA-
TUS register is disabled. All other operations function
normally. When WP is high, all functions, including
writes to the nonvolatile bits in the STATUS register
operate normally. If the WPEN bit is set, WP low during
a STATUS register write sequence will disable writing
to the STATUS register. If an internal write cycle has
already begun, WP going low will have no effect on the
write.
The WP pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
install the 25XX640 in a system with WP pin grounded
and still be able to write to the STATUS register. The
WP pin functions will be enabled when the WPEN bit is
set high.
2.4 Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
2.5 Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX640. Instructions,
addresses, or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
2.6 Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX640 while in the middle of a serial sequence with-
out having to retransmit the entire sequence over
again. It must be held high any time this function is not
being used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to-
low transition. The 25XX640 must remain selected
during this sequence. The SI, SCK, and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
Name PDIP SOIC TSSOP Description
CS 1 1 3 Chip Select Input
SO 2 2 4 Serial Data Output
WP 3 3 5 Write-Protect Pin
VSS 4 4 6 Ground
SI 5 5 7 Serial Data Input
SCK 6 6 8 Serial Clock Input
HOLD 7 7 1 Hold Input
VCC 8 8 2 Supply Voltage
25AA640/25LC640
3.0 FUNCTIONAL DESCRIPTION
3.1 Principles Of Operation
The 25XX640 is a 8192 byte Serial EEPROM designed
to interface directly with the Serial Peripheral Interface
(SPI) port of many of todays popular microcontroller
families, including Microchips PIC16C6X/7X micro-
controllers. It may also interface with microcontrollers
that do not have a built-in SPI port by using discrete
I/O lines programmed properly with the software.
The 25XX640 contains an 8-bit instruction register. The
device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Data is sampled on the first rising edge of SCK after CS
goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25XX640 in HOLD
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
3.2 Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25XX640 fol-
lowed by the 16-bit address with the three MSBs of the
address being dont care bits. After the correct READ
instruction and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO pin. The data stored in the memory at the next
address can be read sequentially by continuing to pro-
vide clock pulses. The internal Address Pointer is auto-
matically incremented to the next higher address after
each byte of data is shifted out. When the highest
address is reached (1FFFh), the address counter rolls
over to address 0000h allowing the read cycle to be
continued indefinitely. The read operation is terminated
by raising the CS pin (Figure 3-1).
3.3 Write Sequence
Prior to any attempt to write data to the 25XX640 array
or STATUS register, the write enable latch must be set
by issuing the WREN instruction (Figure 3-4). This is
done by setting CS low and then clocking out the
proper instruction into the 25XX640. After all eight bits
of the instruction are transmitted, the CS must be
brought high to set the write enable latch. If the write
operation is initiated immediately after the WREN
instruction without CS being brought high, the data will
not be written to the array because the write enable
latch will not have been properly set.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE
instruction, followed by the address, and then the data
to be written. Up to 32 bytes of data can be sent to the
25XX640 before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page. A page address begins with XXX0 0000
and ends with XXX1 1111. If the internal address
counter reaches XXX1 1111 and the clock continues,
the counter will roll back to the first address of the page
and overwrite any data in the page that may have been
written.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the n
th
data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence, respectively.
While the write is in progress, the STATUS register may
be read to check the status of the WPEN, WIP, WEL,
BP1, and BP0 bits (Figure 3-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
TABLE 3-1: INSTRUCTION SET
Instruction Name Instruction Format Description
READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
WREN 0000 0110 Set the write enable latch (enable write operations)
WRDI 0000 0100 Reset the write enable latch (disable write operations)
RDSR 0000 0101 Read STATUS register
WRSR 0000 0001 Write STATUS register
25AA640/25LC640
FIGURE 3-1: READ SEQUENCE
FIGURE 3-2: BYTE WRITE SEQUENCE
FIGURE 3-3: PAGE WRITE SEQUENCE
SO
SI
SCK
CS
0 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 1
0 1 0 0 0 0 0 1 15 14 13 12 2 1 0
7 6 5 4 3 2 1 0
Instruction 16-bit Address
Data Out
High-Impedance
SO
SI
CS
0 0 0 0 0 0 0 1 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0
Instruction 16-bit Address Data Byte
High-Impedance
Twc
SI
CS
9 10 11 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0 0 0 1 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0
Instruction 16-bit Address Data Byte 1
SCK
0 2 3 4 5 6 7 1 8
SI
CS
41 42 43 46 47
7 6 5 4 3 2 1 0
Data Byte n (32 max)
SCK
32 34 35 36 37 38 39 33 40
7 6 5 4 3 2 1 0
Data Byte 3
7 6 5 4 3 2 1 0
Data Byte 2
44 45
25AA640/25LC640
3.4 Write Enable (WREN) and
Write Disable (WRDI)
The 25XX640 contains a write enable latch. See
Table 3-3 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
The following is a list of conditions under which the
write enable latch will be reset:
Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
FIGURE 3-4: WRITE ENABLE SEQUENCE
FIGURE 3-5: WRITE DISABLE SEQUENCE
SCK
0 2 3 4 5 6 7 1
SI
High-Impedance
SO
CS
0 1 0 0 0 0 0 1
SCK
0 2 3 4 5 6 7 1
SI
High-Impedance
SO
CS
0 1 0 0 0 0 0 10
25AA640/25LC640
3.5 Read Status Register Instruction
(RDSR)
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
The Write-In-Process (WIP) bit indicates whether the
25XX640 is busy with a write operation. When set to a
1, a write is in progress, when set to a 0, no write is
in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a 1, the latch
allows writes to the array and STATUS register, when
set to a 0, the latch prohibits writes to the array and
STATUS register. The state of this bit can always be
updated via the WREN or WRDI commands regardless
of the state of write protection on the STATUS register.
This bit is read-only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile.
See Figure 3-6 for RDSR timing sequence.
FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE
7 6 5 4 3 2 1 0
WPEN X X X BP1 BP0 WEL WIP
SO
SI
CS
9 10 11 12 13 14 15
1 1 0 0 0 0 0 0
7 6 5 4 2 1 0
Instruction
Data from STATUS Register
High-Impedance
SCK
0 2 3 4 5 6 7 1 8
3
25AA640/25LC640
3.6 Write Status Register Instruction
(WRSR)
The Write Status Register instruction (WRSR) allows the
user to select one of four levels of protection for the
array by writing to the appropriate bits in the STATUS
register. The array is divided up into four segments.
The user has the ability to write-protect none, one, two,
or all four of the segments of the array. The partitioning
is controlled as shown in Table 3-2.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the pro-
grammable hardware write-protect feature. Hardware
write protection is enabled when the WP pin is low and
the WPEN bit is high. Hardware write protection is dis-
abled when either the WP pin is high or the WPEN bit
is low. When the chip is hardware write-protected, only
writes to nonvolatile bits in the STATUS register are dis-
abled. See Table 3-3 for a matrix of functionality on the
WPEN bit.
See Figure 3-7 for WRSR timing sequence.
TABLE 3-2: ARRAY PROTECTION
FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE
BP1 BP0
Array Addresses
Write-Protected
0 0 none
0 1 upper 1/4
(1800h-1FFFh)
1 0 upper 1/2
(1000h-1FFFh)
1 1 all
(0000h-1FFFh)
SO
SI
CS
9 10 11 12 13 14 15
0 1 0 0 0 0 0 0 7 6 5 4 2 1 0
Instruction Data to STATUS Register
High-Impedance
SCK
0 2 3 4 5 6 7 1 8
3
25AA640/25LC640
3.7 Data Protection
The following protection has been implemented to
prevent inadvertent writes to the array:
The write enable latch is reset on power-up
A write enable instruction must be issued to set
the write enable latch
After a byte write, page write, or STATUS register
write, the write enable latch is reset
CS must be set high after the proper number of
clock cycles to start an internal write cycle
Access to the array during an internal write cycle
is ignored and programming is continued
3.8 Power-On-State
The 25XX640 powers on in the following state:
The device is in low-power Standby mode
(CS= 1)
The write enable latch is reset
SO is in high-impedance state
A high-to-low transition on CS is required to enter
the active state
.
TABLE 3-3: WRITE-PROTECT FUNCTIONALITY MATRIX
WPEN WP WEL Protected Blocks Unprotected Blocks STATUS Register
X X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 1 Protected Writable Protected
X High 1 Protected Writable Writable
25AA640/25LC640
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
* Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
25LC640
/P017
0410
25LC640
I/SN0410
017
8-Lead TSSOP
Example:
XXXX
YYWW
NNN
5LCX
0410
017
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week 01)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3 e
3 e
25AA640/25LC640
8-Lead PIastic DuaI In-Line (P) - 300 miI Body [PDIP]
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units NCHES
Dimension Limits MN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing eB .430
N
E1
NOTE 1
D
1 2 3
A
A1
A2
L
b1
b
e
E
eB
c
Microchip Technology Drawing C04-018B
25AA640/25LC640
8-Lead PIastic SmaII OutIine (SN) - Narrow, 3.90 mm Body [SOIC]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Units MLLMETERS
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A 1.75
Molded Package Thickness A2 1.25
Standoff A1 0.10 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (optional) h 0.25 0.50
Foot Length L 0.40 1.27
Footprint L1 1.04 REF
Foot Angle I 0 8
Lead Thickness c 0.17 0.25
Lead Width b 0.31 0.51
Mold Draft Angle Top D 5 15
Mold Draft Angle Bottom E 5 15
D
N
e
E
E1
NOTE 1
1 2 3
b
A
A1
A2
L
L1
c
h
h

25AA640/25LC640
8-Lead PIastic SmaII OutIine (SN) - Narrow, 3.90 mm Body [SOIC]
25AA640/25LC640
8-Lead PIastic Thin Shrink SmaII OutIine (ST) - 4.4 mm Body [TSSOP]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Units MLLMETERS
Number of Pins N 8
Pitch e 0.65 BSC
Overall Height A 1.20
Molded Package Thickness A2 0.80 1.00 1.05
Standoff A1 0.05 0.15
Overall Width E 6.40 BSC
Molded Package Width E1 4.30 4.40 4.50
Molded Package Length D 2.90 3.00 3.10
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle I 0 8
Lead Thickness c 0.09 0.20
Lead Width b 0.19 0.30
D
N
E
E1
NOTE 1
1 2
b
e
c
A
A1
A2
L1 L

25AA640/25LC640
APPENDIX A: REVISION HISTORY
Revision F
Corrections to Section 1.0, Electrical Characteristics.
Revision G
Product ID System, Example C: Corrected part
number, added Alternate Pinout and corrected part
number in Header.
Updated Trademark and Sales List pages.
Revision H (June 2008)
Added Not Recommended note; Updated Packaging;
General updates.
25AA640/25LC640
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Product Support Data sheets and errata,
application notes and sample programs, design
resources, users guides and hardware support
documents, latest software releases and archived
software
General Technical Support Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Business of Microchip Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchips customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
25AA640/25LC640
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
RE: Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS21223H 25AA640/25LC640
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
25AA640/25LC640
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX XXX
Pattern Package Temperature
Range
Device

Device 25AA640: 64K bit 1.8V SPI Serial EEPROM
25AA640T: 64K bit 1.8V SPI Serial EEPROM
(Tape and Reel)
25AA640X: 64K bit 1.8V SPI Serial EEPROM
in alternate pinout (ST only)
25AA640XT: 64K bit 1.8V SPI Serial EEPROM
in alternate pinout Tape and Reel (ST only)
25LC640: 64K bit 2.5V SPI Serial EEPROM
25LC640T: 64K bit 2.5V SPI Serial EEPROM
(Tape and Reel)
25LC640X: 64K bit 2.5V SPI Serial EEPROM
in alternate pinout (ST only)
25LC640XT: 64K bit 2.5V SPI Serial EEPROM
in alternate pinout Tape and Reel (ST only)
Temperature Range I = -40C to +85C
E = -40C to +125C
Package P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
ST = Plastic TSSOP (4.4 mm Body), 8-lead
Examples:
a) 25AA640-I/SN: Industrial Temp.,
SOIC package
b) 25AA640T-I/SN: Tape and Reel,
Industrial Temp., SOIC package
c) 25AA640X-I/ST: Alternate Pinout
Industrial Temp., TSSOP package
d) 25LC640-I/SN: Industrial Temp.,
SOIC package
e) 25LC640T-I/SN: Tape and Reel,
Industrial Temp., SOIC package
f) 25LC640X-I/ST: Alternate Pinout,
Industrial Temp., TSSOP package
25AA640/25LC640
NOTES:
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyers risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, rfPIC and SmartShunt are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC
32
logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC

MCUs and dsPIC
DSCs, KEELOQ

code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
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Tel: 678-957-9614
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Mississauga, Ontario,
Canada
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WORLDWIDE SALES AND SERVICE
01/02/08

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Microchip Technology Drawing C04-057B

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