BMS

INSTITUTE OF TECHNOLOGY AND MANAGEMENT

Avalahalli, Doddaballapur Main Road, Bengaluru – 560064

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

COMPUTER ORGANIZATION
18EC35

STUDY MATERIAL

III SEMESTER
 BMS INSTITUTE OF TECHNOLOGY AND MANAGEMENT
YELAHANKA – BANGALORE - 64
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

COURSE DESIGN SHEET

Semester: III ECE Course: COMPUTER Subject Code: 18EC35

ORGANIZATION AND
ARCHITECTURE
Academic Year: Course coordinator: RVA SIE Marks:20
2020-21 Odd Sem Course handled by: Dr.AKD, RVA, HVR CIE Marks:60
No. of Lecture hours /week: 4 Total no. of Lecture:40 hours

COURSE OUTCOMES :

CO1 Illustrate the basic organization of a computer system, different types of

semiconductor and other secondary storage memories and simple processor based
hardwired control and micro programmed control.(M1,M4,M5)

CO2 Apply The Knowledge of Mathematics to interpret the Data, Address in a Computer
Architecture M1,M2
CO3 Analyze different ways of accessing an input -output from various types of memory
and devices including interrupts.M2,3,4
CO4 Present the knowledge of any Computer subsystem individually or in a team.

CO-PO-PSO Matrix:
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2

CO1 2
CO2 2 2
CO3 2 2
CO4 2 2 2 2
Cii 2 2 2 2 2 2

JUSTIFICATION FOR CO-PO MAPPING:

CO2: The Knowledge of mathematics, Boolean algebra is required to understand the data
formats and interpret the address of a memory system in a computer organization. Hence the
correlation of CO2 to PO1 is medium.

CO3: Students should analyze different ways of accessing an input –output using Addressing modes
from various types of memory and devices .Hence the correlation of CO3 to PO2 is medium.

CO4: As Students are demonstrating the concepts related to sub systems of the computer
architecture in a team and also submitting the reports, the correlation of CO4 to PO9,10 and 12
is medium.
CO TARGET AND ATTAINMENT FOR PREVIOUS ACADEMIC YEAR
AND ACTION PLAN FOR THIS ACADEMIC YEAR

Target Attainment Action Plan

CO1
CO2
CO3
CO4

ASSESSMENT METHODS/TOOLS

MODULES DELIVERY ASSESMNENT CO EVALUATION

METHOD METHOD ATTAINMENT TOOLS
Basic Structure of Online DIRECT- CO1,2 I-INTERNAL
Computers Class INTERNAL TEST PAPER
Machine PPTs and TEST
Instructions and Videos And Quiz
Programs

Addressing Online DIRECT- CO2,3 I-INTERNAL

Modes Class INTERNAL TEST PAPER
PPTs and TEST & Quiz
Videos
Input/Output Online DIRECT- CO1,3 II-INTERNAL
Organization Class INTERNAL TEST PAPER
PPTs and TEST & Quiz
Videos
Memory System Online DIRECT- CO1,3 III -INTERNAL
Class INTERNALS TEST PAPER
PPTs and &Quiz
Videos
Basic Processing Online DIRECT- CO1 III-INTERNAL
Unit Class INTERNALS TEST PAPER
PPTs and QUIZ
Videos
SL.NO Tools ASSESSMENT COS MAPPED
Marks
1 Assignment on Module-4 and 5 5 Marks CO4
2 Internal Assessment 30 Marks CO1,2,3
3 Quiz on Module 1 ,2 and 3 5 Marks CO1,2,3

COURSE CO-ORDINATOR PROGRAM CO-ORDINATOR HOD

 CONTENT SHEET

Module No Name of the Page No

Module
1 Basic Structures of 1-58
Computers
2 Adressing Modes 59-119
3 Input –Output Organization 120-136
4 Memory System 137-153
5 Basic Processing Unit 154-166
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 MODULE 3: MEMORY SYSTEM

BASIC CONCEPTS
• Maximum size of memory that can be used in any computer is determined by addressing mode.

• If MAR is k-bits long then

→ memory may contain upto 2K addressable-locations
• If MDR is n-bits long, then
→ n-bits of data are transferred between the memory and processor.
• The data-transfer takes place over the processor-bus (Figure 8.1).
• The processor-bus has
1) Address-Line
2) Data-line &
3) Control-Line (R/W‟, MFC – Memory Function Completed).
• The Control-Line is used for coordinating data-transfer.
• The processor reads the data from the memory by
→ loading the address of the required memory-location into MAR and
→ setting the R/W‟ line to 1.
• The memory responds by
→ placing the data from the addressed-location onto the data-lines and
→ confirms this action by asserting MFC signal.
• Upon receipt of MFC signal, the processor loads the data from the data-lines into MDR.
• The processor writes the data into the memory-location by
→ loading the address of this location into MAR &
→ setting the R/W‟ line to 0.
• Memory Access Time: It is the time that elapses between
→ initiation of an operation &
→ completion of that operation.
• Memory Cycle Time: It is the minimum time delay that required between the initiation of the two
successive memory-operations.

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RAM (Random Access Memory)
• In RAM, any location can be accessed for a Read/Write-operation in fixed amount of time,
Cache Memory
 It is a small, fast memory that is inserted between
→ larger slower main-memory and
→ processor.
 It holds the currently active segments of a program and their data.
Virtual Memory
 The address generated by the processor is referred to as a virtual/logical address.
 The virtual-address-space is mapped onto the physical-memory where data are actually stored.
 The mapping-function is implemented by MMU. (MMU = memory management unit).
 Only the active portion of the address-space is mapped into locations in the physical-memory.
 The remaining virtual-addresses are mapped onto the bulk storage devices such as magnetic disk.
 As the active portion of the virtual-address-space changes during program execution, the MMU
→ changes the mapping-function &
→ transfers the data between disk and memory.
 During every memory-cycle, MMU determines whether the addressed-page is in the memory. If
the page is in the memory.
Then, the proper word is accessed and execution proceeds.
Otherwise, a page containing desired word is transferred from disk to memory.
• Memory can be classified as follows:
1) RAM which can be further classified as follows:
i) Static RAM
ii) Dynamic RAM (DRAM) which can be further classified as synchronous & asynchronous
DRAM.
2) ROM which can be further classified as follows:
i) PROM
ii) EPROM
iii) EEPROM &
iv) Flash Memory which can be further classified as Flash Cards & Flash Drives.

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SEMI CONDUCTOR RAM MEMORIES
INTERNAL ORGANIZATION OF MEMORY-CHIPS
• Memory-cells are organized in the form of array (Figure 8.2).
• Each cell is capable of storing 1-bit of information.
• Each row of cells forms a memory-word.
• All cells of a row are connected to a common line called as Word-Line.
• The cells in each column are connected to Sense/Write circuit by 2-bit-lines.
• The Sense/Write circuits are connected to data-input or output lines of the chip.
• During a write-operation, the sense/write circuit
→ receive input information &
→ store input info in the cells of the selected word.

• The data-input and data-output of each Sense/Write circuit are connected to a single bidirectional data-
line.
• Data-line can be connected to a data-bus of the computer.
• Following 2 control lines are also used:
1) R/W’ operation.
2) CS’ -chip memory-system.

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STATIC RAM (OR MEMORY)
• Memories consist of circuits capable of retaining their state as long as power is applied are known.

• Two inverters are cross connected to form a latch (Figure 8.4).

• The latch is connected to 2-bit-lines by transistors T1 and T2.
• The transistors act as switches that can be opened/closed under the control of the word-line.
• When the word-line is at ground level, the transistors are turned off and the latch retain its state.
Read Operation
• To read the state of the cell, the word-line is activated to close switches T1 and T2.
• If the cell is in state 1, the signal on bit-line b is high and the signal on the bit-line b‟ is low.
• Thus, b and b‟ are complement of each other.
• Sense/Write circuit
→ monitors the state of b & b‟ and
→ sets the output accordingly.
Write Operation
• The state of the cell is set by
→ placing the appropriate value on bit-line b and its complement on b‟ and
→ then activating the word-line. This forces the cell into the corresponding state.
• The required signal on the bit-lines is generated by Sense/Write circuit.

CMOS Cell
• Transistor pairs (T3, T5) and (T4, T6) form the inverters in the latch (Figure 8.5).
• In state 1, the voltage at point X is high by having T 5, T6 ON and T4, T5 are OFF.
• Thus, T1 and T2 returned ON (Closed), bit-line b and b‟ will have high and low signals respectively.
• Advantages:
1) It has low power consumption „.‟ the current flows in the cell only when the cell is active.
2) Static RAM‟s can be accessed quickly. It access time is few nanoseconds.
• Disadvantage: SRAMs are said to be volatile memories „.‟ their contents are lost when power is
interrupted.

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ASYNCHRONOUS DRAM
• Less expensive RAMs can be implemented if simple cells are used.
• Such cells cannot retain their state indefinitely. Hence they are called Dynamic RAM (DRAM).
• The information stored in a dynamic memory-cell in the form of a charge on a capacitor.
• This charge can be maintained only for tens of milliseconds.
• The contents must be periodically refreshed by restoring this capacitor charge to its full value.

• In order to store information in the cell, the transistor T is turned „ON‟ (Figure 8.6).
• The appropriate voltage is applied to the bit-line which charges the capacitor.
• After the transistor is turned off, the capacitor begins to discharge.
• Hence, info. stored in cell can be retrieved correctly before threshold value of capacitor drops down.
• During a read-operation,
→ transistor is turned „ON‟
→ a sense amplifier detects whether the charge on the capacitor is above the threshold value.
 If (charge on capacitor) > (t -line will have logic value „1‟.
 -line will set to logic value „0‟.

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ASYNCHRONOUS DRAM DESCRIPTION
• The 4 bit cells in each row are divided into 512 groups of 8 (Figure 5.7).
• 21 bit address is needed to access a byte in the memory. 21 bit is divided as follows:
1) 12 address bits are needed to select a row.
i.e. A8-0 → specifies row-address of a byte.
2) 9 bits are needed to specify a group of 8 bits in the selected row.
i.e. A20-9 → specifies column-address of a byte.

• During Read/Write-operation,
→ row-address is applied first.
→ row-address is loaded into row-latch in response to a signal pulse on RAS’ input of chip. (RAS
= Row-address Strobe CAS = Column-address Strobe)
• When a Read-operation is initiated, all cells on the selected row are read and refreshed.
• Shortly after the row-address is loaded, the column-address is
→ applied to the address pins &
→ loaded into CAS’.
• The information in the latch is decoded.
• The appropriate group of 8 Sense/Write circuits is selected.
R/W’=1(read- -lines D0-D7.
R/W’=0(write- 0-D7 are transferred to the selected circuits.
• RAS‟ & CAS‟ are active-low so that they cause latching of address when they change from high to low.
• To ensure that the contents of DRAMs are maintained, each row of cells is accessed periodically.
• A special memory-circuit provides the necessary control signals RAS‟ & CAS‟ that govern the timing.
• The processor must take into account the delay in the response of the memory.
Fast Page Mode
 Transferring the bytes in sequential order is achieved by applying the consecutive sequence of
column-address under the control of successive CAS‟ signals.
 This scheme allows transferring a block of data at a faster rate.
 The block of transfer capability is called as fast page mode.

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READ ONLY MEMORY (ROM)
• Both SRAM and DRAM chips are volatile, i.e. They lose the stored information if power is turned off.
• Many application requires non-volatile memory which retains the stored information if power is turned
off.
• For ex:
OS software has to be loaded from disk to memory i.e. it requires non-volatile memory.
• Non-volatile memory is used in embedded system.
• Since the normal operation involves only reading of stored data, a memory of this type is called ROM.
 At Logic value ‘0’ (P).
Transistor switch is closed & voltage on bit-line nearly drops to zero (Figure 8.11).
 At Logic value ‘1’
The bit-line remains at high voltage.

• To read the state of the cell, the word-line is activated.

• A Sense circuit at the end of the bit-line generates the proper output value.

TYPES OF ROM
• Different types of non-volatile memory are
1) PROM
2) EPROM
3) EEPROM &
4) Flash Memory (Flash Cards & Flash Drives)

PROM (PROGRAMMABLE ROM)

• PROM allows the data to be loaded by the user.
• Programmability is achieved by inserting a „fuse‟ at point P in a ROM cell.
• Before PROM is programmed, the memory contains all 0‟s.
• User can insert 1‟s at required location by burning-out fuse using high current-pulse.
• This process is irreversible.
• Advantages:
1) It provides flexibility.
2) It is faster.
3) It is less expensive because they can be programmed directly by the user.

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EPROM (ERASABLE REPROGRAMMABLE ROM)
• EPROM allows
→ stored data to be erased and
→ new data to be loaded.
• In cell, a connection to ground is always made at „P‟ and a special transistor is used.
• The transistor has the ability to function as
→ a normal transistor or
→ a disabled transistor that is always turned „off‟.
• Transistor can be programmed to behave as a permanently open switch, by injecting charge into it.
• Erasure requires dissipating the charges trapped in the transistor of memory-cells. This
can be done by exposing the chip to ultra-violet light.
• Advantages:
1) It provides flexibility during the development-phase of digital-system.
2) It is capable of retaining the stored information for a long time.
• Disadvantages:
1) The chip must be physically removed from the circuit for reprogramming.
2) The entire contents need to be erased by UV light.

EEPROM (ELECTRICALLY ERASABLE ROM)

• Advantages:
1) It can be both programmed and erased electrically.
2) It allows the erasing of all cell contents selectively.
• Disadvantage: It requires different voltage for erasing, writing and reading the stored data.

FLASH MEMORY
• In EEPROM, it is possible to read & write the contents of a single cell.
• In Flash device, it is possible to read contents of a single cell & write entire contents of a block.
• Prior to writing, the previous contents of the block are erased.
Eg. In MP3 player, the flash memory stores the data that represents sound.
• Single flash chips cannot provide sufficient storage capacity for embedded-system.
• Advantages:
1) Flash drives have greater density which leads to higher capacity & low cost per bit.
2) It requires single power supply voltage & consumes less power.
• There are 2 methods for implementing larger memory: 1) Flash Cards & 2) Flash Drives
1) Flash Cards
 One way of constructing larger module is to mount flash-chips on a small card.
 Such flash-card have standard interface.
 The card is simply plugged into a conveniently accessible slot.
 Memory-size of the card can be 8, 32 or 64MB.
 Eg: A minute of music can be stored in 1MB of memory. Hence 64MB flash cards can store an
hour of music.
2) Flash Drives
 Larger flash memory can be developed by replacing the hard disk-drive.
 The flash drives are designed to fully emulate the hard disk.
 The flash drives are solid state electronic devices that have no movable parts.
Advantages:
1) They have shorter seek & access time which results in faster response.
2) They have low power consumption. .‟. they are attractive for battery driven
application.
3) They are insensitive to vibration.
Disadvantages:
1) The capacity of flash drive (<1GB) is less than hard disk (>1GB).
2) It leads to higher cost per bit.
3) Flash memory will weaken after it has been written a number of times (typically at
least 1 million times).

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CACHE MEMORIES
• The effectiveness of cache mechanism is based on the property of „Locality of Reference’.
Locality of Reference
• Many instructions in the localized areas of program are executed repeatedly during some time period
• Remainder of the program is accessed relatively infrequently (Figure 8.15).
• There are 2 types:
1) Temporal
 The recently executed instructions are likely to be executed again very soon.
2) Spatial
 Instructions in close proximity to recently executed instruction are also likely to be executed soon.
• If active segment of program is placed in cache-memory, then total execution time can be reduced.
• Block refers to the set of contiguous address locations of some size.
• The cache-line is used to refer to the cache-block.

• The Cache-memory stores a reasonable number of blocks at a given time.

• This number of blocks is small compared to the total number of blocks available in main-memory.
• Correspondence b/w main-memory-block & cache-memory-block is specified by mapping-function.
• Cache control hardware decides which block should be removed to create space for the new block.
• The collection of rule for making this decision is called the Replacement Algorithm.
• The cache control-circuit determines whether the requested-word currently exists in the cache.
• The write-operation is done in 2 ways: 1) Write-through protocol & 2) Write-back protocol.
Write-Through Protocol
 Here the cache-location and the main-memory-locations are updated simultaneously.
Write-Back Protocol
 This technique is to
→ update only the cache-location &
→ mark the cache-location with associated flag bit called Dirty/Modified Bit.
 The word in memory will be updated later, when the marked-block is removed from cache.
During Read-operation
• If the requested-word currently not exists in the cache, then read-miss will occur.
• To overcome the read miss, Load–through/Early restart protocol is used.
Load–Through Protocol
 The block of words that contains the requested-word is copied from the memory into cache.
 After entire block is loaded into cache, the requested-word is forwarded to processor.
During Write-operation
• If the requested-word not exists in the cache, then write-miss will occur.
1) If Write Through Protocol is used, the information is written directly into main-memory.
2) If Write Back Protocol is used,
→ then block containing the addressed word is first brought into the cache &
→ then the desired word in the cache is over-written with the new information.

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REPLACEMENT ALGORITHM
• In direct mapping method,
the position of each block is pre-determined and there is no need of replacement strategy.
• In associative & set associative method,
The block position is not pre-determined.
If the cache is full and if new blocks are brought into the cache,then the cache-controller must
decide which of the old blocks has to be replaced.
• When a block is to be overwritten, the block with longest time w/o being referenced is over-written.
• This block is called Least recently Used (LRU) block & the technique is called LRU algorithm.
• The cache-controller tracks the references to all blocks with the help of block-counter.
• Advantage: Performance of LRU is improved by randomness in deciding which block is to be over-
written.

Eg:
Consider 4 blocks/set in set associative cache.
 2 bit counter can be used for each block.
 When a ‘hit’ occurs, then block counter=0; The counter with values originally lower than the
referenced one are incremented by 1 & all others remain unchanged.
 When a ‘miss’ occurs & if the set is full, the blocks with the counter value 3 is removed, the new
block is put in its place & its counter is set to “0‟ and other block counters are incremented by 1.

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VIRTUAL MEMORY
• It refers to a technique that automatically move program/data blocks into the main-memory when they are
required for execution (Figure 8.24).
• The address generated by the processor is referred to as a virtual/logical address.
• The virtual-address is translated into physical-address by MMU (Memory Management Unit).
• During every memory-cycle, MMU determines whether the addressed-word is in the memory. If
the word is in memory.
Then, the word is accessed and execution proceeds.
Otherwise, a page containing desired word is transferred from disk to memory.
• Using DMA scheme, transfer of data between disk and memory is performed.

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VIRTUAL MEMORY ADDRESS TRANSLATION
• All programs and data are composed of fixed length units called Pages (Figure 8.25).
The Page consists of a block-of-words. The words occupy contiguous locations in the memory.
The pages are commonly range from 2K to 16K bytes in length.
• Cache Bridge speed-up the gap between main-memory and secondary-storage.
• Each virtual-address contains
1) Virtual Page number (Low order bit) and
2) Offset (High order bit).
Virtual Page number + Off
• Page-table: It contains the information about
→ memory-address where the page is stored &
→ current status of the page.
• Page-frame: An area in the main-memory that holds one page.
• Page-table Base Register: It contains the starting address of the page-table.
• Virtual Page Number + Page-table Base register
currently resides in memory.
• Control-bits in Page-table: The Control-bits is used to
1) Specify the status of the page while it is in memory.
2) Indicate the validity of the page.
3) Indicate whether the page has been modified during its stay in the memory.

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SECONDARY-STORAGE
• The semi-conductor memories do not provide all the storage capability.
• The secondary-storage devices provide larger storage requirements.
• Some of the secondary-storage devices are:
1) Magnetic Disk
2) Optical Disk &
3) Magnetic Tapes.
MAGNETIC DISK
• Magnetic Disk system consists of one or more disk mounted on a common spindle.
• A thin magnetic film is deposited on each disk (Figure 8.27).
• Disk is placed in a rotary-drive so that magnetized surfaces move in close proximity to R/W heads.
• Each R/W head consists of 1) Magnetic Yoke & 2) Magnetizing-Coil.
• Digital information is stored on magnetic film by applying current pulse to the magnetizing-coil.
• Only changes in the magnetic field under the head can be sensed during the Read-operation.
• Therefore, if the binary states 0 & 1 are represented by two opposite states,
then a voltage is induced in the head only at 0-1 and at 1-0 transition in the bit stream.
• A consecutive of 0‟s & 1‟s are determined by using the clock.
• Manchester Encoding technique is used to combine the clocking information with data.

• R/W heads are maintained at small distance from disk-surfaces in order to achieve high bit densities.
• When disk is moving at their steady state, the air pressure develops b/w disk-surfaces & head. This
air pressure forces the head away from the surface.
• The flexible spring connection between head and its arm mounting permits the head to fly at the desired
distance away from the surface.
Winchester Technology
• Read/Write heads are placed in a sealed, air–filtered enclosure called the Winchester Technology.
• The read/write heads can operate closure to magnetic track surfaces because

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 the dust particles which are a problem in unsealed assemblies are absent.

Advantages
• It has a larger capacity for a given physical size.
• The data intensity is high because
the storage medium is not exposed to contaminating elements.
• The read/write heads of a disk system are movable.
• The disk system has 3 parts: 1) Disk Platter (Usually called Disk)
2) Disk-drive (spins the disk & moves Read/write heads)
3) Disk Controller (controls the operation of the system.)

ORGANIZATION & ACCESSING OF DATA ON A DISK

• Each surface is divided into concentric Tracks (Figure 8.28).
• Each track is divided into Sectors.
• The set of corresponding tracks on all surfaces of a stack of disk form a Logical Cylinder.
• The data are accessed by specifying the surface number, track number and the sector number.
• The Read/Write-operation start at sector boundaries.
• Data bits are stored serially on each track.

• Each sector usually contains 512 bytes.

• Sector Header --> contains identification information.
It helps to find the desired sector on the selected track.
• ECC (Error checking code)- is used to detect and correct errors.
• An unformatted disk has no information on its tracks.
• The formatting process divides the disk physically into tracks and sectors.
• The formatting process may discover some defective sectors on all tracks.
• Disk Controller keeps a record of various defects.
• The disk is divided into logical partitions:
1) Primary partition
2) Secondary partition
• Each track has same number of sectors. So, all tracks have same storage capacity.
• Thus, the stored information is packed more densely on inner track than on outer track.
Access Time
• There are 2 components involved in the time-delay:
1) Seek time: Time required to move the read/write head to the proper track.
2) Latency/Rotational Delay: The amount of time that elapses after head is positioned over the
correct track until the starting position of the addressed sector passes under the R/W head. Seek time
+ Latency = Disk access time
Typical Disk
 One inch disk-weight = 1 ounce, size -> comparable to match

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 book Capacity -> 1GB
 Inch disk has the following
parameter Recording
surface=20 Tracks=15000
tracks/surface Sectors=400.
Each sector stores 512 bytes of data

Capacity of formatted disk=20x15000x400x512=60x109

=60GB Seek time=3ms
Platter rotation=10000
rev/min Latency=3ms
Internet transfer rate=34MB/s

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DATA BUFFER/CACHE
• A disk-drive that incorporates the required SCSI circuit is referred as SCSI Drive.
• The SCSI can transfer data at higher rate than the disk tracks.
• A data buffer can be used to deal with the possible difference in transfer rate b/w disk and SCSI bus
• The buffer is a semiconductor memory.
• The buffer can also provide cache mechanism for the disk.
i.e. when a read request arrives at the disk, then controller first check if the data is available in the
cache/buffer.
If data is available in cache.
Then, the data can be accessed & placed on SCSI bus.
Otherwise, the data will be retrieved from the disk.

DISK CONTROLLER
• The disk controller acts as interface between disk-drive and system-bus (Figure 8.13).
• The disk controller uses DMA scheme to transfer data between disk and memory.
• When the OS initiates the transfer by issuing R/W‟ request, the controllers register will load the following
information:
1) Memory Address: Address of first memory-location of the block of words involved in the
transfer.
2) Disk Address: Location of the sector containing the beginning of the desired block of words.
3) Word Count: Number of words in the block to be transferred.

• The disk-address issued by the OS is a logical address.

• The corresponding physical-address on the disk may be different.
• The controller's major functions are:
1) Seek - Causes disk-drive to move the R/W head from its current position to desired track.
2) Read - Initiates a Read-operation, starting at address specified in the disk-address register. Data
read serially from the disk are assembled into words and placed into the data buffer for
transfer to the main-memory.
3) Write - Transfers data to the disk.
4) Error Checking - Computes the error correcting code (ECC) value for the data read from a given
sector and compares it with the corresponding ECC value read from the disk.
In case of a mismatch, it corrects the error if possible;
Otherwise, it raises an interrupt to inform the OS that an error has occurred.

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 MODULE 4: MEMORY SYSTEM

BASIC CONCEPTS
• Maximum size of memory that can be used in any computer is determined by addressing mode.

• If MAR is k-bits long then

→ memory may contain upto 2K addressable-locations
• If MDR is n-bits long, then
→ n-bits of data are transferred between the memory and processor.
• The data-transfer takes place over the processor-bus (Figure 8.1).
• The processor-bus has
1) Address-Line
2) Data-line &
3) Control-Line (R/W‟, MFC – Memory Function Completed).
• The Control-Line is used for coordinating data-transfer.
• The processor reads the data from the memory by
→ loading the address of the required memory-location into MAR and
→ setting the R/W‟ line to 1.
• The memory responds by
→ placing the data from the addressed-location onto the data-lines and
→ confirms this action by asserting MFC signal.
• Upon receipt of MFC signal, the processor loads the data from the data-lines into MDR.
• The processor writes the data into the memory-location by
→ loading the address of this location into MAR &
→ setting the R/W‟ line to 0.
• Memory Access Time: It is the time that elapses between
→ initiation of an operation &
→ completion of that operation.
• Memory Cycle Time: It is the minimum time delay that required between the initiation of the two
successive memory-operations.

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RAM (Random Access Memory)
• In RAM, any location can be accessed for a Read/Write-operation in fixed amount of time,
Cache Memory
 It is a small, fast memory that is inserted between
→ larger slower main-memory and
→ processor.
 It holds the currently active segments of a program and their data.
Virtual Memory
 The address generated by the processor is referred to as a virtual/logical address.
 The virtual-address-space is mapped onto the physical-memory where data are actually stored.
 The mapping-function is implemented by MMU. (MMU = memory management unit).
 Only the active portion of the address-space is mapped into locations in the physical-memory.
 The remaining virtual-addresses are mapped onto the bulk storage devices such as magnetic disk.
 As the active portion of the virtual-address-space changes during program execution, the MMU
→ changes the mapping-function &
→ transfers the data between disk and memory.
 During every memory-cycle, MMU determines whether the addressed-page is in the memory. If
the page is in the memory.
Then, the proper word is accessed and execution proceeds.
Otherwise, a page containing desired word is transferred from disk to memory.
• Memory can be classified as follows:
1) RAM which can be further classified as follows:
i) Static RAM
ii) Dynamic RAM (DRAM) which can be further classified as synchronous & asynchronous
DRAM.
2) ROM which can be further classified as follows:
i) PROM
ii) EPROM
iii) EEPROM &
iv) Flash Memory which can be further classified as Flash Cards & Flash Drives.

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SEMI CONDUCTOR RAM MEMORIES
INTERNAL ORGANIZATION OF MEMORY-CHIPS
• Memory-cells are organized in the form of array (Figure 8.2).
• Each cell is capable of storing 1-bit of information.
• Each row of cells forms a memory-word.
• All cells of a row are connected to a common line called as Word-Line.
• The cells in each column are connected to Sense/Write circuit by 2-bit-lines.
• The Sense/Write circuits are connected to data-input or output lines of the chip.
• During a write-operation, the sense/write circuit
→ receive input information &
→ store input info in the cells of the selected word.

• The data-input and data-output of each Sense/Write circuit are connected to a single bidirectional data-
line.
• Data-line can be connected to a data-bus of the computer.
• Following 2 control lines are also used:
1) R/W’ operation.
2) CS’ -chip memory-system.

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STATIC RAM (OR MEMORY)
• Memories consist of circuits capable of retaining their state as long as power is applied are known.

• Two inverters are cross connected to form a latch (Figure 8.4).

• The latch is connected to 2-bit-lines by transistors T1 and T2.
• The transistors act as switches that can be opened/closed under the control of the word-line.
• When the word-line is at ground level, the transistors are turned off and the latch retain its state.
Read Operation
• To read the state of the cell, the word-line is activated to close switches T1 and T2.
• If the cell is in state 1, the signal on bit-line b is high and the signal on the bit-line b‟ is low.
• Thus, b and b‟ are complement of each other.
• Sense/Write circuit
→ monitors the state of b & b‟ and
→ sets the output accordingly.
Write Operation
• The state of the cell is set by
→ placing the appropriate value on bit-line b and its complement on b‟ and
→ then activating the word-line. This forces the cell into the corresponding state.
• The required signal on the bit-lines is generated by Sense/Write circuit.

CMOS Cell
• Transistor pairs (T3, T5) and (T4, T6) form the inverters in the latch (Figure 8.5).
• In state 1, the voltage at point X is high by having T 5, T6 ON and T4, T5 are OFF.
• Thus, T1 and T2 returned ON (Closed), bit-line b and b‟ will have high and low signals respectively.
• Advantages:
1) It has low power consumption „.‟ the current flows in the cell only when the cell is active.
2) Static RAM‟s can be accessed quickly. It access time is few nanoseconds.
• Disadvantage: SRAMs are said to be volatile memories „.‟ their contents are lost when power is
interrupted.

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ASYNCHRONOUS DRAM
• Less expensive RAMs can be implemented if simple cells are used.
• Such cells cannot retain their state indefinitely. Hence they are called Dynamic RAM (DRAM).
• The information stored in a dynamic memory-cell in the form of a charge on a capacitor.
• This charge can be maintained only for tens of milliseconds.
• The contents must be periodically refreshed by restoring this capacitor charge to its full value.

• In order to store information in the cell, the transistor T is turned „ON‟ (Figure 8.6).
• The appropriate voltage is applied to the bit-line which charges the capacitor.
• After the transistor is turned off, the capacitor begins to discharge.
• Hence, info. stored in cell can be retrieved correctly before threshold value of capacitor drops down.
• During a read-operation,
→ transistor is turned „ON‟
→ a sense amplifier detects whether the charge on the capacitor is above the threshold value.
 If (charge on capacitor) > (t -line will have logic value „1‟.
 -line will set to logic value „0‟.

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ASYNCHRONOUS DRAM DESCRIPTION
• The 4 bit cells in each row are divided into 512 groups of 8 (Figure 5.7).
• 21 bit address is needed to access a byte in the memory. 21 bit is divided as follows:
1) 12 address bits are needed to select a row.
i.e. A8-0 → specifies row-address of a byte.
2) 9 bits are needed to specify a group of 8 bits in the selected row.
i.e. A20-9 → specifies column-address of a byte.

• During Read/Write-operation,
→ row-address is applied first.
→ row-address is loaded into row-latch in response to a signal pulse on RAS’ input of chip. (RAS
= Row-address Strobe CAS = Column-address Strobe)
• When a Read-operation is initiated, all cells on the selected row are read and refreshed.
• Shortly after the row-address is loaded, the column-address is
→ applied to the address pins &
→ loaded into CAS’.
• The information in the latch is decoded.
• The appropriate group of 8 Sense/Write circuits is selected.
R/W’=1(read- -lines D0-D7.
R/W’=0(write- 0-D7 are transferred to the selected circuits.
• RAS‟ & CAS‟ are active-low so that they cause latching of address when they change from high to low.
• To ensure that the contents of DRAMs are maintained, each row of cells is accessed periodically.
• A special memory-circuit provides the necessary control signals RAS‟ & CAS‟ that govern the timing.
• The processor must take into account the delay in the response of the memory.
Fast Page Mode
 Transferring the bytes in sequential order is achieved by applying the consecutive sequence of
column-address under the control of successive CAS‟ signals.
 This scheme allows transferring a block of data at a faster rate.
 The block of transfer capability is called as fast page mode.

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READ ONLY MEMORY (ROM)
• Both SRAM and DRAM chips are volatile, i.e. They lose the stored information if power is turned off.
• Many application requires non-volatile memory which retains the stored information if power is turned
off.
• For ex:
OS software has to be loaded from disk to memory i.e. it requires non-volatile memory.
• Non-volatile memory is used in embedded system.
• Since the normal operation involves only reading of stored data, a memory of this type is called ROM.
 At Logic value ‘0’ (P).
Transistor switch is closed & voltage on bit-line nearly drops to zero (Figure 8.11).
 At Logic value ‘1’
The bit-line remains at high voltage.

• To read the state of the cell, the word-line is activated.

• A Sense circuit at the end of the bit-line generates the proper output value.

TYPES OF ROM
• Different types of non-volatile memory are
1) PROM
2) EPROM
3) EEPROM &
4) Flash Memory (Flash Cards & Flash Drives)

PROM (PROGRAMMABLE ROM)

• PROM allows the data to be loaded by the user.
• Programmability is achieved by inserting a „fuse‟ at point P in a ROM cell.
• Before PROM is programmed, the memory contains all 0‟s.
• User can insert 1‟s at required location by burning-out fuse using high current-pulse.
• This process is irreversible.
• Advantages:
1) It provides flexibility.
2) It is faster.
3) It is less expensive because they can be programmed directly by the user.

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EPROM (ERASABLE REPROGRAMMABLE ROM)
• EPROM allows
→ stored data to be erased and
→ new data to be loaded.
• In cell, a connection to ground is always made at „P‟ and a special transistor is used.
• The transistor has the ability to function as
→ a normal transistor or
→ a disabled transistor that is always turned „off‟.
• Transistor can be programmed to behave as a permanently open switch, by injecting charge into it.
• Erasure requires dissipating the charges trapped in the transistor of memory-cells. This
can be done by exposing the chip to ultra-violet light.
• Advantages:
1) It provides flexibility during the development-phase of digital-system.
2) It is capable of retaining the stored information for a long time.
• Disadvantages:
1) The chip must be physically removed from the circuit for reprogramming.
2) The entire contents need to be erased by UV light.

EEPROM (ELECTRICALLY ERASABLE ROM)

• Advantages:
1) It can be both programmed and erased electrically.
2) It allows the erasing of all cell contents selectively.
• Disadvantage: It requires different voltage for erasing, writing and reading the stored data.

FLASH MEMORY
• In EEPROM, it is possible to read & write the contents of a single cell.
• In Flash device, it is possible to read contents of a single cell & write entire contents of a block.
• Prior to writing, the previous contents of the block are erased.
Eg. In MP3 player, the flash memory stores the data that represents sound.
• Single flash chips cannot provide sufficient storage capacity for embedded-system.
• Advantages:
1) Flash drives have greater density which leads to higher capacity & low cost per bit.
2) It requires single power supply voltage & consumes less power.
• There are 2 methods for implementing larger memory: 1) Flash Cards & 2) Flash Drives
1) Flash Cards
 One way of constructing larger module is to mount flash-chips on a small card.
 Such flash-card have standard interface.
 The card is simply plugged into a conveniently accessible slot.
 Memory-size of the card can be 8, 32 or 64MB.
 Eg: A minute of music can be stored in 1MB of memory. Hence 64MB flash cards can store an
hour of music.
2) Flash Drives
 Larger flash memory can be developed by replacing the hard disk-drive.
 The flash drives are designed to fully emulate the hard disk.
 The flash drives are solid state electronic devices that have no movable parts.
Advantages:
1) They have shorter seek & access time which results in faster response.
2) They have low power consumption. .‟. they are attractive for battery driven
application.
3) They are insensitive to vibration.
Disadvantages:
1) The capacity of flash drive (<1GB) is less than hard disk (>1GB).
2) It leads to higher cost per bit.
3) Flash memory will weaken after it has been written a number of times (typically at
least 1 million times).

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CACHE MEMORIES
• The effectiveness of cache mechanism is based on the property of „Locality of Reference’.
Locality of Reference
• Many instructions in the localized areas of program are executed repeatedly during some time period
• Remainder of the program is accessed relatively infrequently (Figure 8.15).
• There are 2 types:
1) Temporal
 The recently executed instructions are likely to be executed again very soon.
2) Spatial
 Instructions in close proximity to recently executed instruction are also likely to be executed soon.
• If active segment of program is placed in cache-memory, then total execution time can be reduced.
• Block refers to the set of contiguous address locations of some size.
• The cache-line is used to refer to the cache-block.

• The Cache-memory stores a reasonable number of blocks at a given time.

• This number of blocks is small compared to the total number of blocks available in main-memory.
• Correspondence b/w main-memory-block & cache-memory-block is specified by mapping-function.
• Cache control hardware decides which block should be removed to create space for the new block.
• The collection of rule for making this decision is called the Replacement Algorithm.
• The cache control-circuit determines whether the requested-word currently exists in the cache.
• The write-operation is done in 2 ways: 1) Write-through protocol & 2) Write-back protocol.
Write-Through Protocol
 Here the cache-location and the main-memory-locations are updated simultaneously.
Write-Back Protocol
 This technique is to
→ update only the cache-location &
→ mark the cache-location with associated flag bit called Dirty/Modified Bit.
 The word in memory will be updated later, when the marked-block is removed from cache.
During Read-operation
• If the requested-word currently not exists in the cache, then read-miss will occur.
• To overcome the read miss, Load–through/Early restart protocol is used.
Load–Through Protocol
 The block of words that contains the requested-word is copied from the memory into cache.
 After entire block is loaded into cache, the requested-word is forwarded to processor.
During Write-operation
• If the requested-word not exists in the cache, then write-miss will occur.
1) If Write Through Protocol is used, the information is written directly into main-memory.
2) If Write Back Protocol is used,
→ then block containing the addressed word is first brought into the cache &
→ then the desired word in the cache is over-written with the new information.

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REPLACEMENT ALGORITHM
• In direct mapping method,
the position of each block is pre-determined and there is no need of replacement strategy.
• In associative & set associative method,
The block position is not pre-determined.
If the cache is full and if new blocks are brought into the cache,then the cache-controller must
decide which of the old blocks has to be replaced.
• When a block is to be overwritten, the block with longest time w/o being referenced is over-written.
• This block is called Least recently Used (LRU) block & the technique is called LRU algorithm.
• The cache-controller tracks the references to all blocks with the help of block-counter.
• Advantage: Performance of LRU is improved by randomness in deciding which block is to be over-
written.

Eg:
Consider 4 blocks/set in set associative cache.
 2 bit counter can be used for each block.
 When a ‘hit’ occurs, then block counter=0; The counter with values originally lower than the
referenced one are incremented by 1 & all others remain unchanged.
 When a ‘miss’ occurs & if the set is full, the blocks with the counter value 3 is removed, the new
block is put in its place & its counter is set to “0‟ and other block counters are incremented by 1.

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VIRTUAL MEMORY
• It refers to a technique that automatically move program/data blocks into the main-memory when they are
required for execution (Figure 8.24).
• The address generated by the processor is referred to as a virtual/logical address.
• The virtual-address is translated into physical-address by MMU (Memory Management Unit).
• During every memory-cycle, MMU determines whether the addressed-word is in the memory. If
the word is in memory.
Then, the word is accessed and execution proceeds.
Otherwise, a page containing desired word is transferred from disk to memory.
• Using DMA scheme, transfer of data between disk and memory is performed.

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VIRTUAL MEMORY ADDRESS TRANSLATION
• All programs and data are composed of fixed length units called Pages (Figure 8.25).
The Page consists of a block-of-words. The words occupy contiguous locations in the memory.
The pages are commonly range from 2K to 16K bytes in length.
• Cache Bridge speed-up the gap between main-memory and secondary-storage.
• Each virtual-address contains
1) Virtual Page number (Low order bit) and
2) Offset (High order bit).
Virtual Page number + Off
• Page-table: It contains the information about
→ memory-address where the page is stored &
→ current status of the page.
• Page-frame: An area in the main-memory that holds one page.
• Page-table Base Register: It contains the starting address of the page-table.
• Virtual Page Number + Page-table Base register
currently resides in memory.
• Control-bits in Page-table: The Control-bits is used to
1) Specify the status of the page while it is in memory.
2) Indicate the validity of the page.
3) Indicate whether the page has been modified during its stay in the memory.

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SECONDARY-STORAGE
• The semi-conductor memories do not provide all the storage capability.
• The secondary-storage devices provide larger storage requirements.
• Some of the secondary-storage devices are:
1) Magnetic Disk
2) Optical Disk &
3) Magnetic Tapes.
MAGNETIC DISK
• Magnetic Disk system consists of one or more disk mounted on a common spindle.
• A thin magnetic film is deposited on each disk (Figure 8.27).
• Disk is placed in a rotary-drive so that magnetized surfaces move in close proximity to R/W heads.
• Each R/W head consists of 1) Magnetic Yoke & 2) Magnetizing-Coil.
• Digital information is stored on magnetic film by applying current pulse to the magnetizing-coil.
• Only changes in the magnetic field under the head can be sensed during the Read-operation.
• Therefore, if the binary states 0 & 1 are represented by two opposite states,
then a voltage is induced in the head only at 0-1 and at 1-0 transition in the bit stream.
• A consecutive of 0‟s & 1‟s are determined by using the clock.
• Manchester Encoding technique is used to combine the clocking information with data.

• R/W heads are maintained at small distance from disk-surfaces in order to achieve high bit densities.
• When disk is moving at their steady state, the air pressure develops b/w disk-surfaces & head. This
air pressure forces the head away from the surface.
• The flexible spring connection between head and its arm mounting permits the head to fly at the desired
distance away from the surface.
Winchester Technology
• Read/Write heads are placed in a sealed, air–filtered enclosure called the Winchester Technology.
• The read/write heads can operate closure to magnetic track surfaces because

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 the dust particles which are a problem in unsealed assemblies are absent.

Advantages
• It has a larger capacity for a given physical size.
• The data intensity is high because
the storage medium is not exposed to contaminating elements.
• The read/write heads of a disk system are movable.
• The disk system has 3 parts: 1) Disk Platter (Usually called Disk)
2) Disk-drive (spins the disk & moves Read/write heads)
3) Disk Controller (controls the operation of the system.)

ORGANIZATION & ACCESSING OF DATA ON A DISK

• Each surface is divided into concentric Tracks (Figure 8.28).
• Each track is divided into Sectors.
• The set of corresponding tracks on all surfaces of a stack of disk form a Logical Cylinder.
• The data are accessed by specifying the surface number, track number and the sector number.
• The Read/Write-operation start at sector boundaries.
• Data bits are stored serially on each track.

• Each sector usually contains 512 bytes.

• Sector Header --> contains identification information.
It helps to find the desired sector on the selected track.
• ECC (Error checking code)- is used to detect and correct errors.
• An unformatted disk has no information on its tracks.
• The formatting process divides the disk physically into tracks and sectors.
• The formatting process may discover some defective sectors on all tracks.
• Disk Controller keeps a record of various defects.
• The disk is divided into logical partitions:
1) Primary partition
2) Secondary partition
• Each track has same number of sectors. So, all tracks have same storage capacity.
• Thus, the stored information is packed more densely on inner track than on outer track.
Access Time
• There are 2 components involved in the time-delay:
1) Seek time: Time required to move the read/write head to the proper track.
2) Latency/Rotational Delay: The amount of time that elapses after head is positioned over the
correct track until the starting position of the addressed sector passes under the R/W head. Seek time
+ Latency = Disk access time
Typical Disk
 One inch disk-weight = 1 ounce, size -> comparable to match

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 book Capacity -> 1GB
 Inch disk has the following
parameter Recording
surface=20 Tracks=15000
tracks/surface Sectors=400.
Each sector stores 512 bytes of data

Capacity of formatted disk=20x15000x400x512=60x109

=60GB Seek time=3ms
Platter rotation=10000
rev/min Latency=3ms
Internet transfer rate=34MB/s

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DATA BUFFER/CACHE
• A disk-drive that incorporates the required SCSI circuit is referred as SCSI Drive.
• The SCSI can transfer data at higher rate than the disk tracks.
• A data buffer can be used to deal with the possible difference in transfer rate b/w disk and SCSI bus
• The buffer is a semiconductor memory.
• The buffer can also provide cache mechanism for the disk.
i.e. when a read request arrives at the disk, then controller first check if the data is available in the
cache/buffer.
If data is available in cache.
Then, the data can be accessed & placed on SCSI bus.
Otherwise, the data will be retrieved from the disk.

DISK CONTROLLER
• The disk controller acts as interface between disk-drive and system-bus (Figure 8.13).
• The disk controller uses DMA scheme to transfer data between disk and memory.
• When the OS initiates the transfer by issuing R/W‟ request, the controllers register will load the following
information:
1) Memory Address: Address of first memory-location of the block of words involved in the
transfer.
2) Disk Address: Location of the sector containing the beginning of the desired block of words.
3) Word Count: Number of words in the block to be transferred.

• The disk-address issued by the OS is a logical address.

• The corresponding physical-address on the disk may be different.
• The controller's major functions are:
1) Seek - Causes disk-drive to move the R/W head from its current position to desired track.
2) Read - Initiates a Read-operation, starting at address specified in the disk-address register. Data
read serially from the disk are assembled into words and placed into the data buffer for
transfer to the main-memory.
3) Write - Transfers data to the disk.
4) Error Checking - Computes the error correcting code (ECC) value for the data read from a given
sector and compares it with the corresponding ECC value read from the disk.
In case of a mismatch, it corrects the error if possible;
Otherwise, it raises an interrupt to inform the OS that an error has occurred.

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 COMPUTER ORGANIZATION AND ARCHITECTURE

MODULE 5: BASIC PROCESSING UNIT

COMMON TO III SEM ECE A,B &C SECTION

SOME FUNDAMENTAL CONCEPTS

• To execute an instruction, processor has to perform following 3 steps:
1) Fetch contents of memory-location pointed to by PC. Content of this location is an instruction
to be executed. The instructions are loaded into IR, Symbolically, this operation is written as:
IR
2) Increment PC by 4.

3) Carry out the actions specified by instruction (in the IR).

• The first 2 steps are referred to as Fetch Phase.
Step 3 is referred to as Execution Phase.
• The operation specified by an instruction can be carried out by performing one or more of the
following actions:
1) Read the contents of a given memory-location and load them into a register.
2) Read data from one or more registers.
3) Perform an arithmetic or logic operation and place the result into a register.
4) Store data from a register into a given memory-location.
• The hardware-components needed to perform these actions are shown in Figure 5.1.

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SINGLE BUS ORGANIZATION
• ALU and all the registers are interconnected via a Single Common Bus (Figure 7.1).
• Data & address lines of the external memory-bus is connected to the internal processor-bus via MDR
Register).
• MDR has 2 inputs and 2 outputs. Data may be loaded
→ into MDR either from memory-bus (external) or
→ from processor-bus (internal).
• MAR‟s input is connected to internal-bus;
MAR‟s output is connected to external-
bus.
• Instruction Decoder & Control Unit is responsible for
→ issuing the control-signals to all the units inside the processor.
→ implementing the actions specified by the instruction (loaded in the IR).
• Register R0 through R(n-1) are the Processor Registers.
The programmer can access these registers for general-purpose use.
• Only processor can access 3 registers Y, Z & Temp for temporary storage during program-execution.
The programer cannot access these 3 registers.
• In ALU, 1) A input gets the operand from the output of the multiplexer (MUX).
2) B input gets the operand directly from the processor-bus.
• There are 2 options provided for „A‟ input of the ALU.
• MUX is used to select one of the 2 inputs.
• MUX selects either
→ output of Y or
→ constant-value 4( which is used to increment PC content).

• An instruction is executed by performing one or more of the following operations:

1) Transfer a word of data from one register to another or to the ALU.
2) Perform arithmetic or a logic operation and store the result in a register.
3) Fetch the contents of a given memory-location and load them into a register.
4) Store a word of data from a register into a given memory-location.
• Disadvantage: Only one data-word can be transferred over the bus in a clock cycle.
Solution: Provide multiple internal-paths. Multiple paths allow several data-transfers to take place in
parallel.

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REGISTER TRANSFERS
• Instruction execution involves a sequence of steps in which data are transferred from one register to
another.
• For each register, two control-signals are used: Riin & Riout. These are called Gating Signals.
• Riin s is loaded into Ri.
Riout
bus.
Riout
• For example, Move R1, R2; This transfers the contents of register R1 to register R2. This can be
accomplished as follows:
1) Enable the output of registers R1 by setting R1 out to 1 (Figure 7.2).
This places the contents of R1 on processor-bus.
2) Enable the input of register R2 by setting R2 out to 1.
This loads data from processor-bus into register R4.
• All operations and data transfers within the processor take place within time-periods defined by the
processor-clock.
• The control-signals that govern a particular transfer are asserted at the start of the clock cycle.

Input & Output Gating for one Register Bit

• A 2-input multiplexer is used to select the data applied to the input of an edge-triggered D flip-flop.
• Riin -flop at rising-edge of clock.
Riin -flop (Figure 7.3).
• Q output of flip-flop is connected to bus via a tri-state gate.
Riout -impedance state.
Riout

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PERFORMING AN ARITHMETIC OR LOGIC OPERATION
• The ALU performs arithmetic operations on the 2 operands applied to its A and B inputs.
• One of the operands is output of MUX;
And, the other operand is obtained directly from processor-bus.
• The result (produced by the ALU) is stored temporarily in register Z.
• The sequence of operations for [R3] follows:
1) R1out, Yin
2) R2out, SelectY, Add, Zin
3) Zout, R3in
• Instruction execution proceeds as follows:
Step 1 --> Contents from register R1 are loaded into register Y.
Step2 --> Contents from Y and from register R2 are applied to the A and B inputs of ALU;
Addition is performed &
Result is stored in the Z register.
Step 3 --> The contents of Z register is stored in the R3 register.
• The signals are activated for the duration of the clock cycle corresponding to that step. All other
signals are inactive.

CONTROL-SIGNALS OF MDR
• The MDR register has 4 control-signals (Figure 7.4):
1) MDRin & MDRout control the connection to the internal processor data bus &
2) MDRinE & MDRoutE control the connection to the memory Data bus.
• MAR register has 2 control-signals.
1) MARin controls the connection to the internal processor address bus &
2) MARout controls the connection to the memory address bus.

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FETCHING A WORD FROM MEMORY
• To fetch instruction/data from memory, processor transfers required address to MAR.
At the same time, processor issues Read signal on control-lines of memory-bus.
• When requested-data are received from memory, they are stored in MDR. From MDR, they are
transferred to other registers.
• The response time of each memory access varies (based on cache miss, memory-mapped I/O). To
Completed).
• MFC is a signal sent from addressed-device to the processor. MFC informs the processor that the
requested operation has been completed by addressed-device.
• Consider the instruction Move (R1),R2. The sequence of steps is (Figure 7.5):
1) R1out, MARin, Read ;desired address is loaded into MAR & Read command is issued.
2) MDRinE, WMFC ;load MDR from memory-bus & Wait for MFC response from memory.
3) MDRout, R2in ;load R2 from MDR.
where WMFC=control-signal that causes processor's
control. circuitry to wait for arrival of MFC signal.

Storing a Word in Memory

• Consider the instruction Move R2,(R1). This requires the following sequence:
1) R1out, MARin ;desired address is loaded into MAR.
2) R2out, MDRin, Write ;data to be written are loaded into MDR & Write command is issued.
3) MDRoutE, WMFC ;load data into memory-location pointed by R1 from MDR.

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EXECUTION OF A COMPLETE INSTRUCTION
• Consider the instruction Add (R3),R1 which adds the contents of a memory-location pointed by R3 to
register R1. Executing this instruction requires the following actions:
1) Fetch the instruction.
2) Fetch the first operand.
3) Perform the addition &
4) Load the result into R1.

• Instruction execution proceeds as follows:

Step1--> The instruction-fetch operation is initiated by
→ loading contents of PC into MAR &
→ sending a Read request to memory.
The Select signal is set to Select4, which causes the Mux to select constant 4. This value
is added to operand at input B (PC‟s content), and the result is stored in Z.
Step2--> Updated value in Z is moved to PC. This completes the PC increment operation and
PC will now point to next instruction.
Step3--> Fetched instruction is moved into MDR and then to
IR. The step 1 through 3 constitutes the Fetch Phase.
At the beginning of step 4, the instruction decoder interprets the contents of the IR. This
enables the control circuitry to activate the control-signals for steps 4 through 7.
The step 4 through 7 constitutes the Execution Phase.
Step4--> Contents of R3 are loaded into MAR & a memory read signal is
issued. Step5--> Contents of R1 are transferred to Y to prepare for addition.
Step6--> When Read operation is completed, memory-operand is available in MDR, and the
addition is performed.
Step7--> Sum is stored in Z, then transferred to R1.The End signal causes a new instruction
fetch cycle to begin by returning to step1.

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BRANCHING INSTRUCTIONS
• Control sequence for an unconditional branch instruction is as follows:

• Instruction execution proceeds as follows:

Step 1-3--> The processing starts & the fetch phase ends in step3.
Step 4--> The offset-value is extracted from IR by instruction-decoding circuit.
Since the updated value of PC is already available in register Y, the offset X is gated onto
the bus, and an addition operation is performed.
Step 5--> the result, which is the branch-address, is loaded into the PC.
• The branch instruction loads the branch target address in PC so that PC will fetch the next instruction
from the branch target address.
• The branch target address is usually obtained by adding the offset in the contents of PC.
• The offset X is usually the difference between the branch target-address and the address immediately
following the branch instruction.
• In case of conditional branch,
we have to check the status of the condition-codes before loading a new value into the PC.
e.g.: Offset-field-of-IRout, Add, Zin, If N=0 then End
If N=0, processor returns to step 1 immediately after step 4.
If N=1, step 5 is performed to load a new value into PC.

MULTIPLE BUS ORGANIZATION

• Disadvantage of Single-bus organization: Only one data-word can be transferred over the bus in a
clock cycle. This increases the steps required to complete the execution of the instruction
Solution: To reduce the number of steps, most processors provide multiple internal-paths. Multiple
paths enable several transfers to take place in parallel.
• As shown in fig 7.8, three buses can be used to connect registers and the ALU of the processor.
• All general-purpose registers are grouped into a single block called the Register File.
• Register-file has 3 ports:
1) Two output-ports allow the contents of 2 different registers to be simultaneously placed on
buses A & B.
2) Third input-port allows data on bus C to be loaded into a third register during the same clock-
cycle.
• Buses A and B are used to transfer source-operands to A & B inputs of ALU.
• The result is transferred to destination over bus C.
• Incrementer Unit is used to increment PC by 4.

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• Instruction execution proceeds as follows:
Step 1--> Contents of PC are
→ passed through ALU using R=B control-signal &
→ loaded into MAR to start memory Read operation. At the same time, PC is incremented by 4.
Step2--> Processor waits for MFC signal from memory.
Step3--> Processor loads requested-data into MDR, and then transfers them to IR.

Step4--> The instruction is decoded and add operation takes place in a single step.

COMPLETE PROCESSOR
• This has separate processing-units to deal with integer data and floating-point data.
To process integer data. (Figure 7.14).
To process floating –point data.
• Data-Cache is inserted between these processing-units & main-memory.
The integer and floating unit gets data from data cache.
• Instruction-Unit fetches instructions
→ from an instruction-cache or
→ from main-memory when desired instructions are not already in cache.
• Processor is connected to system-bus &
hence to the rest of the computer by means of a Bus Interface.
• Using separate caches for instructions & data is common practice in many processors today.
• A processor may include several units of each type to increase the potential for concurrent operations.
• The 80486 processor has 8-kbytes single cache for both instruction and data.
Whereas the Pentium processor has two separate 8 kbytes caches for instruction and data.

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Note:
To execute instructions, the processor must have some means of generating the control-signals. There
are two approaches for this purpose:
1) Hardwired control and 2) Microprogrammed control.

HARDWIRED CONTROL
• Hardwired control is a method of control unit design (Figure 7.11).
• The control-signals are generated by using logic circuits such as gates, flip-flops, decoders etc.
• Decoder/Encoder Block is a combinational-circuit that generates required control-outputs depending
on state of all its inputs.
• Instruction Decoder
 It decodes the instruction loaded in the IR.
 If IR is an 8 bit register, then instruction decoder generates 2 8(256 lines); one for each
instruction.
 It consists of a separate output-lines INS1 through INSm for each machine instruction.
 According to code in the IR, one of the output-lines INS1 through INSm is set to 1, and all
other lines are set to 0.
• Step-Decoder provides a separate signal line for each step in the control sequence.
• Encoder
 It gets the input from instruction decoder, step decoder, external inputs and condition codes.
 It uses all these inputs to generate individual control-signals: Yin, PCout, Add, End and so on.
 For example (Figure 7.12), Zin=T1+T6.ADD+T4.BR
;This signal is asserted during time-slot T1 for all instructions.
during T6 for an Add instruction.
during T4 for unconditional branch instruction
• When RUN=1, counter is incremented by 1 at the end of every clock cycle.
When RUN=0, counter stops counting.
• After execution of each instruction, end signal is generated. End signal resets step counter.
• Sequence of operations carried out by this machine is determined by wiring of logic circuits, hence

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the name “hardwired”.
• Advantage: Can operate at high speed.
• Disadvantages:
1) Since no. of instructions/control-lines is often in hundreds, the complexity of control unit is
very high.
2) It is costly and difficult to design.
3) The control unit is inflexible because it is difficult to change the design.

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HARDWIRED CONTROL VS MICROPROGRAMMED CONTROL
Attribute Hardwired Control Microprogrammed Control
Definition Hardwired control is a control Micro programmed control is a control
mechanism to generate control- mechanism to generate control-signals by
signals by using gates, flip- flops, using a memory called control store (CS),
decoders, and other which contains the control-
digital circuits. signals.
Speed Fast Slow
Control functions Implemented in hardware. Implemented in software.
Flexibility Not flexible to accommodate More flexible, to accommodate new
new system specifications or system specification or new instructions
new instructions. redesign is required.
Ability to handle large Difficult. Easier.
or complex instruction sets

Ability to support Very difficult. Easy.

operating systems
& diagnostic
features
Design process Complicated. Orderly and systematic.
Applications Mostly RISC microprocessors. Mainframes, some microprocessors.
Instructionset size Usually under 100 instructions. Usually over 100 instructions.
ROM size - 2K to 10K by 20-400 bit
microinstructions.
Chip area efficiency Uses least area. Uses more area.
Diagram

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MICROPROGRAMMED CONTROL
• Microprogramming is a method of control unit design (Figure 7.16).
• Control-signals are generated by a program similar to machine language programs.
• Control Word(CW) is a word whose individual bits represent various control-signals (like Add, PCin).
• Each of the control-steps in control sequence of an instruction defines a unique combination of 1s & 0s
in CW.
• Individual control-words in microroutine are referred to as microinstructions (Figure 7.15).
• A sequence of CWs corresponding to control-sequence of a machine instruction constitutes the
microroutine.
• The microroutines for all instructions in the instruction-set of a computer are stored in a special
memory called the Control Store (CS).
• Control-unit generates control-signals for any instruction by sequentially reading CWs of
corresponding microroutine from CS.
• µPC is used to read CWs sequentially from CS. (µPC Counter).
• Every time new instruction is loaded into IR, o/p of Starting Address Generator is loaded into µPC.
• Then, µPC is automatically incremented by clock;
causing successive microinstructions to be read from CS.
Hence, control-signals are delivered to various parts of processor in correct sequence.

Advantages
• It simplifies the design of control unit. Thus it is both, cheaper and less error prone implement.
• Control functions are implemented in software rather than hardware.
• The design process is orderly and systematic.
• More flexible, can be changed to accommodate new system specifications or to correct the design
errors quickly and cheaply.
• Complex function such as floating point arithmetic can be realized efficiently.
Disadvantages
• A microprogrammed control unit is somewhat slower than the hardwired control unit, because time is
required to access the microinstructions from CM.
• The flexibility is achieved at some extra hardware cost due to the control memory and its access
circuitry.

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ORGANIZATION OF MICROPROGRAMMED CONTROL UNIT TO SUPPORT
CONDITIONAL BRANCHING
• Drawback of previous Microprogram control:
 It cannot handle the situation when the control unit is required to check the status of the
condition codes or external inputs to choose between alternative courses of action.
Solution:
 Use conditional branch microinstruction.
• In case of conditional branching, microinstructions specify which of the external inputs, condition-
codes should be checked as a condition for branching to take place.
• Starting and Branch Address Generator Block loads a new address into µPC when a
microinstruction instructs it to do so (Figure 7.18).
• To allow implementation of a conditional branch, inputs to this block consist of
→ external inputs and condition-codes &
→ contents of IR.
• µPC is incremented every time a new microinstruction is fetched from microprogram memory except
in following situations:
1) When a new instruction is loaded into IR, µPC is loaded with starting-address of microroutine
for that instruction.
2) When a Branch microinstruction is encountered and branch condition is satisfied, µPC is
loaded with branch-address.
3) When an End microinstruction is encountered, µPC is loaded with address of first CW in
microroutine for instruction fetch cycle.

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