Ec3352 Set1

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B.E / B.Tech.

PRACTICAL END SEMESTER EXAMINATIONS, NOVEMBER/DECEMBER 2022

Third Semester

EC3352 - DIGITAL SYSTEMS DESIGN

(Regulations 2021)

Time: 3 Hours Answer any one Question Max. Marks 100

Aim/Principle/Apparatus Tabulation/Circuit/ Calculation Viva-Voce Record Total


required/Procedure Program/Drawing & Results
20 30 30 10 10 100

1. Design and implement a combinational circuit to find the 2’s complement of a number
using basic gates and verify its functionality.

2. Design and implement a BCD adder using IC 7483 and basic gates.

3. Design and implement a combinational circuit using basic gates for BCD to Excess 3
code convertor.

4. Verify the following Boolean theorem using basic gates.

(i) Consensus theorem


(ii) Commutative law
(iii) Associative law
(iv) Distributive law
(v) Idempotent law
(vi) De Morgan’s Theorem

5. Design the logic circuit and verify the truth table of the given Boolean expression,

F (A, B, C, D) = Σ (0, 1, 3, 4, 8, 9, 11)

6. Design and implement a data selector and data distributor using basic gates and verify its
truth table.

7. Design and implement a Binary to gray code converter using a multiplexer.

8. Design and implement 2 bit OR gate and 2 bit EXOR gate using NAND gates and
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implement the same using a NAND gates.

9. Design a combinational circuit for the given function F = Σm(0, 1, 4, 6, 7) using 4 x 1


Multiplexer.

10. Design and construct 3 x 8 decoder and 4 x 2 encoder using logic gates.

11. Design and implement Σm (0, 2, 4, 6, 7) using 3 x 8 decoder and basic gates.

12. Design and construct a 8 bit magnitude comparator using IC7485.

13. Design a 2 bit Magnitude comparator and implement the same using basic gates.

14. Implement a sequential circuit for a MOD 12 counter using JK flip-flop.

15. Construct and verify a 4‐bit synchronous down counter using any one of flip flops.

16. Design and construct an ripple counter using any one of the flip flops and verify its
functionality.

17. Design a 4 bit even parity generator and checker and verify its truth table.

18. Implement a 3 bit Serial Input Serial Output and Parallel Input Serial Output shift registers
using D flip flops.

19. Design and implement 3 bit Up/Down counter using any of the flip flops and verify its
functionality.

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