Single-Chip N-Channel Microcontrollers

COP410L/COP411L/COP310L/COP311L
March 1992

COP410L/COP411L/COP310L/COP311L
Single-Chip N-Channel Microcontrollers
General Description Features
The COP410L and COP411L Single-Chip N-Channel Micro- Y Low cost
controllers are members of the COPSTM family, fabricated Y Powerful instruction set
using N-channel, silicon gate MOS technology. These Con- Y 512 x 8 ROM, 32 x 4 RAM
troller Oriented Processors are complete microcomputers Y 19 I/O lines (COP410L)
containing all system timing, internal logic, ROM, RAM and Y Two-level subroutine stack
I/O necessary to implement dedicated control functions in a Y 16 ms instruction time
variety of applications. Features include single supply oper-
ation, a variety of output configuration options, with an in-
Y Single supply operation (4.5V – 6.3V)
struction set, internal architecture and I/O scheme de-
Y Low current drain (6 mA max)
signed to facilitate keyboard input, display output and BCD Y Internal binary counter register with MICROWIRETM se-
data manipulation. The COP411L is identical to the rial I/O capability
COP410L, but with 16 I/O lines instead of 19. They are an Y General purpose and TRI-STATEÉ outputs
appropriate choice for use in numerous human interface Y LSTTL/CMOS compatible in and out
control environments. Standard test procedures and reliable Y Direct drive of LED digit and segment lines
high-density fabrication techniques provide the medium to Y Software/hardware compatible with other members of
large volume customers with a customized Controller Ori- COP400 family
ented Processor at a low end-product cost. Y Extended temperature range device
The COP310L and COP311L are exact functional equiva- Ð COP310L/COP311L (b40§ C to a 85§ C)
lents but extended temperature versions of COP410L and
COP411L respectively.
The COP401L should be used for exact emulation.

Block Diagram

TL/DD/6919 – 1
FIGURE 1. COP410L
COPSTM and MICROWIRETM are trademarks of National Semiconductor Corporation.
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation TL/DD/6919 RRD-B30M105/Printed in U. S. A.

COP410L/COP411L
Absolute Maximum Ratings
If Military/Aerospace specified devices are required, Power Dissipation
please contact the National Semiconductor Sales COP410L 0.75W at 25§ C
Office/Distributors for availability and specifications. 0.4W at 70§ C
Voltage at Any Pin Relative to GND b 0.5V to a 10V COP411L 0.65W at 25§ C
0.3W at 70§ C
Ambient Operating Temperature 0§ C to a 70§ C
Total Source Current 120 mA
Ambient Storage Temperature b 65§ C to a 150§ C
Total Sink Current 100 mA
Lead Temperature
(Soldering, 10 seconds) 300§ C Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings.

DC Electrical Characteristics 0§ C s TA s a 70§ C, 4.5V s VCC s 6.3V unless otherwise noted

Parameter Conditions Min Max Units
Standard Operating Voltage (VCC) 4.5 6.3 V
Power Supply Ripple (Notes 1, 4) Peak to Peak 0.5 V
Operating Supply Current All Inputs and Outputs Open 6 mA
Input Voltage Levels
CKI Input Levels
Ceramic Resonator Input ( d 8)
Logic High (VIH) VCC e Max 3.0 V
Logic High (VIH) VCC e 5V g 5% 2.0 V
Logic Low (VIL) b 0.3 0.4 V
Schmitt Trigger Input ( d 4)
Logic High (VIH) 0.7 VCC V
Logic Low (VIL) b 0.3 0.6 V
RESET Input Levels (Schmitt Trigger Input)
Logic High 0.7 VCC V
Logic Low b 0.3 0.6 V
SO Input Level (Test Mode) (Note 2) 2.0 2.5 V
All Other Inputs
Logic High VCC e Max 3.0 V
Logic High With TTL Trip Level Options 2.0 V
Logic Low Selected, VCC e 5V g 5% b 0.3 0.8 V
Logic High With High Trip Level Options 3.6 V
Logic Low Selected b 0.3 1.2 V
Input Capacitance (Note 4) 7 pF
Hi-Z Input Leakage b1 a1 mA
Output Voltage Levels
LSTTL Operation VCC e 5V g 10%
Logic High (VOH) IOH e b25 mA 2.7 V
Logic Low (VOL) IOL e 0.36 mA 0.4 V
CMOS Operation (Note 3)
Logic High IOH e b10 mA VCC b 1 V
Logic Low IOL e a 10 mA 0.2 V
Note 1: VCC voltage change must be less than 0.5V in a 1 ms period to maintain proper operation.
Note 2: SO output ‘‘0’’ level must be less than 0.8V for normal operation.
Note 3: TRI-STATEÉ and LED configurations are excluded.
Note 4: This parameter is only sampled and not 100% tested. Variation due to the device included.

2
COP410L/COP411L
DC Electrical Characteristics 0§ C s TA s a 70§ C, 4.5V s VCC s 6.3V unless otherwise noted (Continued)
Parameter Conditions Min Max Units
Output Current Levels
Output Sink Current
SO and SK Outputs (IOL) VCC e 6.3V, VOL e 0.4V 1.2 mA
VCC e 4.5V, VOL e 0.4V 0.9 mA
L0 – L7 Outputs, G0 – G3 and VCC e 6.3V, VOL e 0.4V 0.4 mA
LSTTL D0 – D3 Outputs (IOL) VCC e 4.5V, VOL e 0.4V 0.4 mA
D0 – D3 Outputs with High VCC e 6.3V, VOL e 1.0V 11 mA
Current Options (IOL) VCC e 4.5V, VOL e 1.0V 7.5 mA
D0 – D3 Outputs with Very VCC e 6.3V, VOL e 1.0V 22 mA
High Current Options (IOL) VCC e 4.5V, VOL e 1.0V 15 mA
CKI (Single-Pin RC Oscillator) VCC e 4.5V, VIH e 3.5V 2 mA
CKO VCC e 4.5V, VOL e 0.4V 0.2 mA
Output Source Current
Standard Configuration, VCC e 6.3V, VOH e 2.0V b 75 b 480 mA
All Outputs (IOH) VCC e 4.5V, VOH e 2.0V b 30 b 250 mA
Push-Pull Configuration VCC e 6.3V, VOH e 2.4V b 1.4 mA
SO and SK Outputs (IOH) VCC e 4.5V, VOH e 1.0V b 1.2 mA
LED Configuration, L0 – L7 VCC e 6.0V, VOH e 2.0V b 1.5 b 13 mA
Outputs, Low Current
Driver Option (IOH)
LED Configuration, L0 – L7 VCC e 6.0V, VOH e 2.0V b 3.0 b 25 mA
Outputs, High Current
Driver Option (IOH)
TRI-STATE Configuration, VCC e 6.3V, VOH e 3.2V b 0.8 mA
L0 – L7 Outputs, Low VCC e 4.5V, VOH e 1.5V b 0.9 mA
Current Driver Option (IOH)
TRI-STATE Configuration, VCC e 6.3V, VOH e 3.2V b 1.6 mA
L0 – L7 Outputs, High VCC e 4.5V, VOH e 1.5V b 1.8 mA
Current Driver Option (IOH)
Input Load Source Current VCC e 5.0V, VIL e 0V b 10 b 140 mA
CKO Output
RAM Power Supply Option VR e 3.3V 1.5 mA
Power Requirement
TRI-STATE Output Leakage
b 2.5 a 2.5 mA
Current
Total Sink Current Allowed
All Outputs Combined 100 mA
D Port 100 mA
L7 – L4, G Port 4 mA
L3 – L0 4 mA
Any Other Pin 2.0 mA
Total Source Current Allowed
All I/O Combined 120 mA
L7 – L4 60 mA
L3 – L0 60 mA
Each L Pin 25 mA
Any Other Pin 1.5 mA

3
COP310L/COP311L
Absolute Maximum Ratings
If Military/Aerospace specified devices are required, Power Dissipation
please contact the National Semiconductor Sales COP310L 0.75W at 25§ C
Office/Distributors for availability and specifications. 0.25W at 85§ C
Voltage at Any Pin Relative to GND b 0.5V to a 10V COP311L 0.65W at 25§ C
0.20W at 85§ C
Ambient Operating Temperature b 40§ C to a 85§ C
Total Source Current 120 mA
Ambient Storage Temperature b 65§ C to a 150§ C
Total Sink Current 100 mA
Lead Temperature
(Soldering, 10 seconds) 300§ C Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings.

DC Electrical Characteristics b40§ C s TA s a 85§ C, 4.5V s VCC s 5.5V unless otherwise noted
Parameter Conditions Min Max Units
Standard Operating Voltage (VCC) 4.5 5.5 V
Power Supply Ripple (Notes 1, 4) Peak to Peak 0.5 V
Operating Supply Current All Inputs and Outputs Open 8 mA
Input Voltage Levels
Ceramic Resonator Input ( d 8)
Crystal Input
Logic High (VIH) VCC e Max 3.0 V
Logic High (VIH) VCC e 5V g 5% 2.2 V
Logic Low (VIL) b 0.3 0.3 V
Schmitt Trigger Input ( d 4)
Logic High (VIH) 0.7 VCC V
Logic Low (VIL) b 0.3 0.4 V
RESET Input Levels (Schmitt Trigger Input)
Logic High 0.7 VCC V
Logic Low b 0.3 0.4 V
SO Input Level (Test Mode) (Note 2) 2.2 2.5 V
All Other Inputs
Logic High VCC e Max 3.0 V
Logic High With TTL Trip Level Options 2.2 V
Logic Low Selected, VCC e 5V g 5% b 0.3 0.6 V
Logic High With High Trip Level Options 3.6 V
Logic Low Selected b 0.3 1.2 V
Input Capacitance (Note 4) 7 pF
Hi-Z Input Leakage b2 a2 mA
Output Voltage Levels
LSTTL Operation VCC e 5V g 10%
Logic High (VOH) IOH e b20 mA 2.7 V
Logic Low (VOL) IOL e 0.36 mA 0.4 V
CMOS Operation (Note 3)
Logic High IOH e b10 mA VCC b 1 V
Logic Low IOL e a 10 mA 0.2 V
Note 1: VCC voltage change must be less than 0.5V in a 1 ms period to maintain proper operation.
Note 2: SO output ‘‘0’’ level must be less than 0.6V for normal operation.
Note 3: TRI-STATE and LED configurations are excluded.
Note 4: This parameter is only sampled and not 100% tested. Variation due to the device included.

4
COP310L/COP311L
DC Electrical Characteristics (Continued)
b 40§ C s TA s a 85§ C, 4.5V s VCC s 5.5V unless othewise noted

Parameter Conditions Min Max Units

Output Current Levels
Output Sink Current
SO and SK Outputs (IOL) VCC e 5.5V, VOL e 0.4V 1.0 mA
VCC e 4.5V, VOL e 0.4V 0.8 mA
L0 – L7 Outputs, G0 – G3 and VCC e 5.5V, VOL e 0.4V 0.4 mA
LSTTL D0 – D3 Outputs (IOL) VCC e 4.5V, VOL e 0.4V 0.4 mA
D0 – D3 Outputs with High VCC e 5.5V, VOL e 1.0V 9 mA
Current Options (IOL) VCC e 4.5V, VOL e 1.0V 7 mA
D0 – D3 Outputs with Very VCC e 5.5V, VOL e 1.0V 18 mA
High Current Options (IOL) VCC e 4.5V, VOL e 1.0V 14 mA
CKI (Single-Pin RC Oscillator) VCC e 4.5V, VIH e 3.5V 1.5 mA
CKO VCC e 4.5V, VOL e 0.4V 0.2 mA
Output Source Current
Standard Configuration, VCC e 5.5V, VOH e 2.0V b 55 b 600 mA
All Outputs (IOH) VCC e 4.5V, VOH e 2.0V b 28 b 350 mA
Push-Pull Configuration VCC e 5.5V, VOH e 2.0V b 1.1 mA
SO and SK Outputs (IOH) VCC e 4.5V, VOH e 1.0V b 1.2 mA
LED Configuration, L0 – L7 VCC e 5.5V, VOH e 2.0V b 0.7 b 15 mA
Outputs, Low Current
Driver Option (IOH)
LED Configuration, L0 – L7 VCC e 5.5V, VOH e 2.0V b 1.4 b 30 mA
Outputs, High Current
Driver Option (IOH)
TRI-STATE Configuration, VCC e 5.5V, VOH e 2.7V b 0.6 mA
L0 – L7 Outputs, Low VCC e 4.5V, VOH e 1.5V b 0.9 mA
Current Driver Option (IOH)
TRI-STATE Configuration, VCC e 5.5V, VOH e 2.7V b 1.2 mA
L0 – L7 Outputs, High VCC e 4.5V, VOH e 1.5V b 1.8 mA
Current Driver Option (IOH)
Input Load Source Current VCC e 5.0V, VIL e 0V b 10 b 200 mA
CKO Output
RAM Power Supply Option VR e 3.3V 2.0 mA
Power Requirement
TRI-STATE Output Leakage
b5 a5 mA
Current
Total Sink Current Allowed
All Outputs Combined 100 mA
D Port 100 mA
L7 – L4, G Port 4 mA
L3 – L0 4 mA
Any Other Pins 1.5 mA
Total Source Current Allowed
All I/O Combined 120 mA
L7 – L4 60 mA
L3 – L0 60 mA
Each L Pin 25 mA
Any Other Pins 1.5 mA

5
AC Electrical Characteristics
COP410L/411L: 0§ C s TA s 70§ C, 4.5V s VCC s 6.3V unless otherwise noted
COP310L/311L: b40§ C s TA s a 85§ C, 4.5V s VCC s 5.5V unless otherwise noted
Parameter Conditions Min Max Units
Instruction Cycle Time Ð tC 16 40 ms
CKI
Input Frequency Ð fI d 8 Mode 0.2 0.5 MHz
d 4 Mode 0.1 0.25 MHz
Duty Cycle 30 60 %
Rise Time (Note 1) fI e 0.5 MHz 500 ns
Fall Time (Note 1) 200 ns
CKI Using RC ( d 4) R e 56 kX g 5%
(Note 1) C e 100 pF g 10%
Instruction Cycle Time 16 28 ms
CKO as SYNC Input
tSYNC 400 ns
INPUTS
G3 – G0, L7 – L0
tSETUP 8.0 ms
tHOLD 1.3 ms
SI
tSETUP 2.0 ms
tHOLD 1.0 ms
OUTPUT PROPAGATION DELAY Test Condition:
CL e 50 pF, RL e 20 kX, VOUT e 1.5V
SO, SK Outputs
tpd1, tpd0 4.0 ms
All Other Outputs
tpd1, tpd0 5.6 ms
Note 1: This parameter is only sampled and not 100% tested.

Connection Diagrams
DIP DIP

TL/DD/6919 – 3

TL/DD/6919–2
Top View
Top View Order Number COP311L-XXX/D or COP411L-XXX/D
Order Number COP310L-XXX/D or COP410L-XXX/D See NS Hermetic Package Number D20A
See NS Hermetic Package Number D24C (D Pkg.Ðfor Prototypes Only)
(D Pkg.Ðfor Prototypes Only) Order Number COP311L-XXX/N or COP411L-XXX/N
Order Number COP310L-XXX/N or COP410L-XXX/N See NS Molded Package Number N20A
See NS Molded Package Number N24A
FIGURE 2
Pin Descriptions
Pin Description Pin Description
L 7 – L0 8 bidirectional I/O ports with TRI-STATE CKI System oscillator input
G 3 – G0 4 bidirectional I/O ports (G2 – G0 for COP411L) CKO System oscillator output (or RAM power supply or
D 3 – D0 4 general purpose outputs (D1 – D0 for COP411L) SYNC input) (COP410L only)
SI Serial input (or counter input) RESET System reset input
SO Serial output (or general purpose output) VCC Power supply
SK Logic-controlled clock (or general purpose output) GND Ground

6
Timing Diagrams

TL/DD/6919 – 4
FIGURE 3. Input/Output Timing Diagrams (Ceramic Resonator Divide-by-8 Mode)

TL/DD/6919 – 5
FIGURE 3a. Synchronization Timing

Functional Description
A block diagram of the COP410L is given in Figure 1 . Data may also be loaded into the Q latches or loaded from the L
paths are illustrated in simplified form to depict how the vari- ports. RAM addressing may also be performed directly by
ous logic elements communicate with each other in imple- the XAD 3,15 instruction. The Bd register also serves as a
menting the instruction set of the device. Positive logic is source register for 4-bit data sent directly to the D outputs.
used. When a bit is set, it is a logic ‘‘1’’ (greater than 2V). The most significant bit of Bd is not used to select a RAM
When a bit is reset, it is a logic ‘‘0’’ (less than 0.8V). digit. Hence each physical digit of RAM may be selected by
All functional references to the COP410L/COP411L also two different values of Bd as shown in Figure 4 below. The
apply to the COP310L/COP311L. skip condition for XIS and XDS instructions will be true if Bd
changes between 0 and 15, but NOT between 7 and 8 (see
PROGRAM MEMORY
Table III).
Program Memory consists of a 512-byte ROM. As can be
seen by an examination of the COP410L/411L instruction
set, these words may be program instructions, program data
or ROM addressing data. Because of the special character-
istics associated with the JP, JSRP, JID and LQID instruc-
tions, ROM must often be thought of as being organized into
8 pages of 64 words each.
ROM addressing is accomplished by a 9-bit PC register. Its
binary value selects one of the 512 8-bit words contained in
ROM. A new address is loaded into the PC register during
each instruction cycle. Unless the instruction is a transfer of
control instruction, the PC register is loaded with the next
sequential 9-bit binary count value. Two levels of subroutine
nesting are implemented by the 9-bit subroutine save regis-
ters, SA and SB, providing a last-in, first-out (LIFO) hard-
ware subroutine stack.
ROM instruction words are fetched, decoded and executed
by the Instruction Decode, Control and Skip Logic circuitry.
DATA MEMORY
Data memory consists of a 128-bit RAM, organized as 4
data registers of 8 4-bit digits. RAM addressing is imple-
mented by a 6-bit B register whose upper 2 bits (Br) select 1 *Can be directly addressed by
LBI instruction (see Table III)
of 4 data registers and lower 3 bits of the 4-bit Bd select 1 of
8 4-bit digits in the selected data register. While the 4-bit
contents of the selected RAM digit (M) is usually loaded into
or from, or exchanged with, the A register (accumulator), it

TL/DD/6919 – 6
FIGURE 4. RAM Digit Address to
Physical RAM Digit Mapping

7
Functional Description (Continued)
INTERNAL LOGIC each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI
The 4-bit A register (accumulator) is the source and destina- input. Each pulse must be at least two instruction cycles
tion register for most I/O, arithmetic, logic and data memory wide. SK outputs the value of SKL. The SO output is
access operations. It can also be used to load the Bd por- equal to the value of EN3. With EN0 reset, SIO is a serial
tion of the B register, to load 4 bits of the 8-bit Q latch data, shift register shifting left each instruction cycle time. The
to input 4 bits of the 8-bit L I/O port data and to perform data present at SI goes into the least significant bit of
data exchanges with the SIO register. SIO. SO can be enabled to output the most significant bit
of SIO each cycle time. (See 4 below.) The SK output
A 4-bit adder performs the arithmetic and logic functions of
becomes a logic-controlled clock.
the COP410L/411L, storing its results in A. It also outputs a
carry bit to the 1-bit C register, most often employed to indi- 2. EN1 is not used. It has no effect on COP410L/COP411L
cate arithmetic overflow. The C register, in conjunction with operation.
the XAS instruction and the EN register, also serves to con- 3. With EN2 set, the L drivers are enabled to output the data
trol the SK output. C can be outputted directly to SK or can in Q to the L I/O ports. Resetting EN2 disables the L
enable SK to be a sync clock each instruction cycle time. drivers, placing the L I/O ports in a high-impedance input
(See XAS instruction and EN register description, below.) state.
The G register contents are outputs to 4 general-purpose 4. EN3, in conjunction with EN0, affects the SO output. With
bidirectional I/O ports. EN0 set (binary counter option selected) SO will output
The Q register is an internal, latched, 8-bit register, used to the value loaded into EN3. With EN0 reset (serial shift
hold data loaded from M and A, as well as 8-bit data from register option selected), setting EN3 enables SO as the
ROM. Its contents are output to the L I/O ports when the L output of the SIO shift register, outputting serial shifted
drivers are enabled under program control. (See LEI instruc- data each instruction time. Resetting EN3 with the serial
tion.) shift register option selected disables SO as the shift reg-
ister output; data continues to be shifted through SIO and
The 8 L drivers, when enabled, output the contents of
can be exchanged with A via an XAS instruction but SO
latched Q data to the L I/O ports. Also, the contents of L
remains reset to ‘‘0.’’ Table I provides a summary of the
may be read directly into A and M. L I/O ports can be direct-
modes associated with EN3 and EN0.
ly connected to the segments of a multiplexed LED display
(using the LED Direct Drive output configuration option) with INITIALIZATION
Q data being outputted to the Sa–Sg and decimal point The Reset Logic will initialize (clear) the device upon power-
segments of the display. up if the power supply rise time is less than 1 ms and great-
The SIO register functions as a 4-bit serial-in serial-out shift er than 1 ms. If the power supply rise time is greater than
register or as a binary counter depending on the contents of 1 ms, the user must provide an external RC network and
the EN register. (See EN register description, below.) Its diode to the RESET pin as shown below (Figure 5) . The
contents can be exchanged with A, allowing it to input or RESET pin is configured as a Schmitt trigger input. If not
output a continuous serial data stream. SIO may also be used it should be connected to VCC. Initialization will occur
used to provide additional parallel I/O by connecting SO to whenever a logic ‘‘0’’ is applied to the RESET input, provid-
external serial-in/parallel-out shift registers. ed it stays low for at least three instruction cycle times.
The XAS instruction copies C into the SKL Latch. In the
counter mode, SK is the output of SKL in the shift register
mode, SK outputs SKL ANDed with internal instruction cycle
clock.
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of each bit
of this register selects or deselects the particular feature
associated with each bit of the EN register (EN3 – EN0).
RC t 5 c Power Supply Rise Time TL/DD/6919 – 7
1. The least significant bit of the enable register, EN0, se-
lects the SIO register as either a 4-bit shift register or a FIGURE 5. Power-Up Clear Circuit
4-bit binary counter. With EN0 set, SIO is an asynchro-
nous binary counter, decrementing its value by one upon

TABLE I. Enable Register ModesÐBits EN3 and EN0

EN3 EN0 SIO SI SO SK
0 0 Shift Register Input to Shift Register 0 If SKL e 1, SK e Clock
If SKL e 0, SK e 0
1 0 Shift Register Input to Shift Register Serial Out If SKL e 1, SK e Clock
If SKL e 0, SK e 0
0 1 Binary Counter Input to Binary Counter 0 If SKL e 1, SK e 1
If SKL e 0, SK e 0
1 1 Binary Counter Input to Binary Counter 1 If SKL e 1, SK e 1
If SKL e 0, SK e 0

8
Functional Description (Continued)
Upon initialization, the PC register is cleared to 0 (ROM ad- CKO PIN OPTIONS
dress 0) and the A, B, C, D, EN, and G registers are cleared.
In a resonator controlled oscillator system, CKO is used as
The SK output is enabled as a SYNC output, providing a
an output to the resonator network. As an option, CKO can
pulse each instruction cycle time. Data Memory (RAM) is
be a RAM power supply pin (VR), allowing its connection to
not cleared upon initialization. The first instruction at ad-
a standby/backup power supply to maintain the integrity of
dress 0 must be a CLRA.
RAM data with minimum power drain when the main supply
is inoperative or shut down to conserve power. Using no
connection option is appropriate in applications where the
COP410L system timing configuration does not require use
of the CKO pin.
RAM KEEP-ALIVE OPTION
Selecting CKO as the RAM power supply (VR) allows the
user to shut off the chip power supply (VCC) and maintain
data in the RAM. To insure that RAM data integrity is main-
tained, the following conditions must be met:
1. RESET must go low before VCC goes below spec during
power-off; VCC must be within spec before RESET goes
high on power-up.
2. During normal operation, VR must be within the operating
range of the chip with (VCC b 1) s VR s VCC.
3. VR must be t 3.3V with VCC off.
I/O OPTIONS
COP410L/411L inputs and outputs have the following op-
tional configurations, illustrated in Figure 7 :
TL/DD/6919 – 8
a. StandardÐan enhancement-mode device to ground in
Ceramic Resonator Oscillator conjunction with a depletion-mode device to VCC, com-
Components Values patible with LSTTL and CMOS input requirements. Avail-
Resonator able on SO, SK, and all D and G outputs.
Value R1 (X) R2 (X) C1 (pF) C2 (pF)
b. Open-DrainÐan enhancement-mode device to ground
455 kHz 4.7k 1M 220 220 only, allowing external pull-up as required by the user’s
RC Controlled Oscillator application. Available on SO, SK, and all D and G out-
puts.
Instruction c. Push-PullÐan enhancement-mode device to ground in
R (kX) C (pF) Cycle Time conjunction with a depletion-mode device paralleled by
in ms an enhancement-mode device to VCC. This configuration
has been provided to allow for fast rise and fall times
51 100 19 g 15%
when driving capacitive loads. Available on SO and SK
82 56 19 g 13%
outputs only.
Note: 200 kX t R t 25 kX. 360 pF t C t 50 pF. Does not include tolerances. d. Standard LÐsame as a., but may be disabled. Available
FIGURE 6. COP410L/411L Oscillator on L outputs only.
e. Open Drain LÐsame as b., but may be disabled. Avail-
OSCILLATOR
able on L outputs only.
There are three basic clock oscillator configurations avail-
f. LED Direct DriveÐan enhancement mode device to
able as shown by Figure 6 .
ground and to VCC, meeting the typical current sourcing
a. Resonator Controlled Oscillator. CKI and CKO are requirements of the segments of an LED display. The
connected to an external ceramic resonator. The instruc- sourcing device is clamped to limit current flow. These
tion cycle frequency equals the resonator frequency di- devices may be turned off under program control (see
vided by 8. This is not available in the COP411L. Functional Description, EN Register), placing the outputs
b. External Oscillator. CKI is an external clock input signal. in a high-impedance state to provide required LED seg-
The external frequency is divided by 4 to give the instruc- ment blanking for a multiplexed display. Available on L
tion frequency time. CKO is now available to be used as outputs only.
the RAM power supply (VR), or no connection. Note: Series current limiting resistors must be used if LEDs are driven di-
Note: No CKO on COP411L. rectly and higher operating voltage option is selected.

c. RC Controlled Oscillator. CKI is configured as a single g. TRI-STATE Push-PullÐan enhancement-mode device

pin RC controlled Schmitt trigger oscillator. The instruc- to ground and VCC. These outputs are TRI-STATE out-
tion cycle equals the oscillation frequency divided by 4. puts, allowing for connection of these outputs to a data
CKO is available as the RAM power supply (VR) or no bus shared by other bus drivers. Available on L outputs
connection. only.

9
Functional Description (Continued)
h. An on-chip depletion load device to VCC. An important point to remember if using configuration d. or
i. A Hi-Z input which must be driven to a ‘‘1’’ or ‘‘0’’ by f. with the L drivers is that even when the L drivers are
external components. disabled, the depletion load device will source a small
amount of current. (See Figure 8 , device 2.) However, when
The above input and output configurations share common
the L port is used as input, the disabled depletion device
enhancement-mode and depletion-mode devices. Specifi-
CANNOT be relied on to source sufficient current to pull an
cally, all configurations use one or more of six devices
input to a logic ‘‘1’’.
(numbered 1 – 6, respectively). Minimum and maximum cur-
rent (IOUT and VOUT) curves are given in Figure 8 for each COP411L
of these devices to allow the designer to effectively use If the COP410L is bonded as a 20-pin device, it becomes
these I/O configurations in designing a COP410L/411L sys- the COP411L, illustrated in Figure 2, COP410L/411L Con-
tem. nection Diagrams. Note that the COP411L does not contain
The SO, SK outputs can be configured as shown in a., b., or D2, D3, G3, or CKO. Use of this option of course precludes
c. The D and G outputs can be configured as shown in a. or use of D2, D3, G3, and CKO options. All other options are
b. Note that when inputting data to the G ports, the G out- available for the COP411L.
puts should be set to ‘‘1’’. The L outputs can be configured
as in d., e., f., or g.

a. Standard Output b. Open-Drain Output c. Push-Pull Output

TL/DD/6919 – 10

TL/DD/6919–9 TL/DD/6919 – 11

d. Standard L Output e. Open-Drain L Output f. LED (L Output)

TL/DD/6919 – 13

TL/DD/6919–12

( U is depletion device) TL/DD/6919 – 14

g. TRI-STATE Push-Pull (L Output) h. Input with Load i. Hi-Z Input

TL/DD/6919 – 17

TL/DD/6919 – 16
TL/DD/6919–15
FIGURE 7. Input and Output Configurations

10
L-Bus Considerations
False states may be generated on L0 – L7 during the execu- In this program the internal Q register is enabled onto the L
tion of the CAMQ instruction. The L-ports should not be lines and a steady bit pattern of logic highs is output on L0,
used as clocks for edge sensitive devices such as flip-flops, L1, L6, L7, and logic lows on L2 –L5 via the two-byte CAMQ
counters, shift registers, etc. the following short program instruction. Timing constraints on the device are such that
that illustrates this situation. the Q register may be temporarily loaded with the second
START: byte of the CAMQ opcode (XÊ 3C) prior to receiving the valid
data pattern. If this occurs, the opcode will ripple onto the L
CLRA ;ENABLE THE Q
lines and cause negative-going glitches on L0, L1, L6, L7,
LEI 4 ;REGISTER TO L LINES and positive glitches on L2 –L5. Glitch durations are under
LBI TEST 2 ms, although the exact value may vary due to data pat-
STII 3 terns, processing parameters, and L line loading. These
AISC 12 false states are peculiar only to the CAMQ instruction and
the L lines.
LOOP:
LBI TEST ;LOAD Q WITH X’C3
CAMQ
JP LOOP

Typical Performance Characteristics

Input Current for L0 through
L7 when Output Programmed Source Current for Standard
Input Current RESET, SI Off by Software Output Configuration

Source Current for SO Source Current for L0 through Source Current for L0 through
and SK in Push-Pull L7 in TRI-STATE Configuration L7 in TRI-STATE Configuration
Configuration (High Current Option) (Low Current Option)

TL/DD/6919 – 18
FIGURE 8a. COP410L/COP411L I/O DC Current Characteristics

11
Typical Performance Characteristics (Continued)

LED Output Direct Segment

and Direct Drive High
Current Options on L0 – L7
LED Output Source Current LED Output Source Current Very High Current Options
(for High Current LED Option) (for Low Current LED Option) on D0 – D3

Output Sink Current for L0 – L7

LED Output Direct Output Sink Current for SO and Standard Drive Option for
Segment Drive and SK D0 –D3 and G0 –G3

Output Sink Current for

Output Sink Current for D0 – D3 D0 – D3 (for High Current
with Very High Current Option Option)

TL/DD/6919 – 19
FIGURE 8a. COP410L/COP411L I/O DC Current Characteristics (Continued)

12
Typical Performance Characteristics (Continued)

Input Current for L0 – L7 Source Current for

when Output Programmed Standard Output
Input Current RESET, SI Off by Software Configuration

Source Current for SO Source Current for L0 – L7 Source Current for L0 – L7

and SK in Push-Pull in TRI-STATE Configuration in TRI-STATE Configuration
Configuration (High Current Option) (Low Current Option)

LED Output Source LED Output Source

Current (for Low Current Current (for High Current Output Sink Current for
LED Option) LED Option) SO and SK

Output Sink Current for Output Sink Current Output Sink Current
L0–L7 and Standard Drive for D0 – D3 with Very High for D0 – D3 (for
Option for D0–D3 and G0–G3 Current Option High Current Option)

TL/DD/6919 – 20
FIGURE 8b. COP310L/COP311L Input/Output Characteristics

13
 COP410L/411L Instruction Set
Table II is a symbol table providing internal architecture, in- Table III provides the mnemonic, operand, machine code,
struction operand and operational symbols used in the in- data flow, skip conditions and description associated with
struction set table. each instruction in the COP410L/411L instruction set.

TABLE II. COP410L/411L Instruction Set Table Symbols

Symbol Definition Symbol Definition

INTERNAL ARCHITECTURE SYMBOLS INSTRUCTION OPERAND SYMBOLS
A 4-bit Accumulator d 4-bit Operand Field, 0 – 15 binary (RAM Digit Select)
B 6-bit RAM Address Register r 2-bit Operand Field, 0 – 3 binary (RAM Register
Br Upper 2 bits of B (register address) Select)
Bd Lower 4 bits of B (digit address) a 9-bit Operand Field, 0 – 511 binary (ROM Address)
C 1-bit Carry Register y 4-bit Operand Field, 0 – 15 binary (Immediate Data)
D 4-bit Data Output Port RAM(s) Contents of RAM location addressed by s
EN 4-bit Enable Register ROM(t) Contents of ROM location addressed by t
G 4-bit Register to latch data for G I/O Port
L 8-bit TRI-STATE I/O Port OPERATIONAL SYMBOLS
M 4-bit contents of RAM Memory pointed to by B
Register a Plus
PC 9-bit ROM Address Register (program counter) b Minus
Q 8-bit Register to latch data for L I/O Port x Replaces
SA 9-bit Subroutine Save Register A Ý Is exchanged with
SB 9-bit Subroutine Save Register B e Is equal to
SIO 4-bit Shift Register and Counter A The one’s complement of A
SK Logic-Controlled Clock Output Z Exclusive-OR
: Range of values

TABLE III. COP410L/411L Instruction Set

Machine
Hex
Mnemonic Operand Language Code Data Flow Skip Conditions Description
Code
(Binary)
ARITHMETIC INSTRUCTIONS
ASC 30 À 0011 À 0000 À A a C a RAM(B) xA Carry Add with Carry, Skip on
Carry x C Carry

ADD 31 À 0011 À 0001 À A a RAM(B) xA None Add RAM to A

AISC y 5– À 0101 À y À Aay xA Carry Add Immediate, Skip on

Carry (y i 0)

CLRA 00 À 0000 À 0000 À 0 xA None Clear A

COMP 40 À 0100 À 0000 À A xA None One’s complement of A to A

NOP 44 À 0100 À 0100 À None None No Operation

RC 32 À 0011 À 0010 À ‘‘0’’ xC None Reset C

SC 22 À 0010 À 0010 À ‘‘1’’ xC None Set C

XOR 02 À 0000 À 0010 À A Z RAM(B) xA None Exclusive-OR RAM with A

14
 Instruction Set (Continued)
TABLE III. COP410L/411L Instruction Set (Continued)
Machine
Hex
Mnemonic Operand Language Code Data Flow Skip Conditions Description
Code
(Binary)
TRANSFER OF CONTROL INSTRUCTIONS
JID FF À 1111 À 1111 À ROM (PC8,A,M) x None Jump Indirect (Note 2)
PC7:0

JMP a 6– À 0110 À 000 À a8 À a x PC None Jump

– – À a7:0 À

JP a – – À1À a6:0 À a x PC6:0 None Jump within Page

(pages 2,3 only) (Note 3)
or
– – À 11 À a5:0 À a x PC5:0
(all other pages)

JSRP a – – À 10 À a5:0 À PC a 1 x SA x SB None Jump to Subroutine Page

(Note 4)
010 x PC8:6
a x PC5:0

JSR a 6– À 0110 À 100 À a8 À PC a 1 x SA x SB None Jump to Subroutine

– – À a7:0 À a x PC

RET 48 À 0100 À 1000 À SB x SA x PC None Return from Subroutine

RETSK 49 À 0100 À 1001 À SB x SA x PC Always Skip on Return Return from Subroutine

then Skip
MEMORY REFERENCE INSTRUCTIONS
CAMQ 33 À 0011 À 0011 À A x Q7:4 None Copy A, RAM to Q
3C À 0011 À 1100 À RAM(B) x Q3:0

LD r –5 À 00 À r À 0101 À RAM(B) x A None Load RAM into A,

Br Z r x Br Exclusive-OR Br with r

LQID BF À 1011 À 1111 À ROM(PC8,A,M) xQ None Load Q Indirect (Note 2)

SA x SB

RMB 0 4C À 0100 À 1100 À 0 x RAM(B)0 None Reset RAM Bit

1 45 À 0100 À 0101 À 0 x RAM(B)1
2 42 À 0100 À 0010 À 0 x RAM(B)2
3 43 À 0100 À 0011 À 0 x RAM(B)3
SMB 0 4D À 0100 À 1101 À 1 x RAM(B)0 None Set RAM Bit
1 47 À 0100 À 0111 À 1 x RAM(B)1
2 46 À 0100 À 0110 À 1 x RAM(B)2
3 4B À 0100 À 1011 À 1 x RAM(B)3

STII y 7– À 0111 À y À y x RAM(B) None Store Memory Immediate

Bd a 1 x Bd and Increment Bd

X r –6 À 00 À r À 0110 À RAM(B) Ý A None Exchange RAM with A,

Br Z r x Br Exclusive-OR Br with r

XAD 3,15 23 À 0010 À 0011 À RAM(3,15) Ý A None Exchange A with RAM

BF À 1011 À 1111 À (3,15)

XDS r –7 À 00 À r À 0111 À RAM(B) Ý A Bd decrements past 0 Exchange RAM with A

Bd – 1 x Bd and Decrement Bd,
Br Z r x Br Exclusive-OR Br with r

XIS r –4 À 00 À r À 0100 À RAM(B) Ý A Bd increments past 15 Exchange RAM with A

Bd a 1 x Bd and Increment Bd
Br Z r x Br Exclusive-OR Br with r

15
 Instruction Set (Continued)
TABLE III. COP410L/411L Instruction Set (Continued)
Machine
Hex
Mnemonic Operand Language Code Data Flow Skip Conditions Description
Code
(Binary)
REGISTER REFERENCE INSTRUCTIONS
CAB 50 À 0101 À 0000 À A x Bd None Copy A to Bd

CBA 4E À 0100 À 1110 À Bd xA None Copy Bd to A

LBI r,d – – À 00 À r À (d b 1) À r,d xB Skip until not a LBI Load B Immediate with
(d e 0,9:15) r,d (Note 5)

LEI y 33 À 0011 À 0011 À y x EN None Load EN Immediate

6– À 0110 À y À (Note 6)
TEST INSTRUCTIONS
SKC 20 À 0010 À 0000 À C e ‘‘1’’ Skip if C is True

SKE 21 À 0010 À 0001 À A e RAM(B) Skip if A Equals RAM

SKGZ 33 À 0011 À 0011 À G3:0 e 0 Skip if G is Zero

21 À 0010 À 0001 À (all 4 bits)

SKGBZ 33 À 0011 À 0011 À 1st byte Skip if G Bit is Zero

0 01 À 0000 À 0001 À G0 e 0
1 11 À 0001 À 0001 À G1 e 0
2nd byte
*
2 03 À 0000 À 0011 À G2 e 0
3 13 À 0001 À 0011 À G3 e 0

SKMBZ 0 01 À 0000 À 0001 À RAM(B)0 e 0 Skip if RAM Bit is Zero

1 11 À 0001 À 0001 À RAM(B)1 e 0
2 03 À 0000 À 0011 À RAM(B)2 e 0
3 13 À 0001 À 0011 À RAM(B)3 e 0
INPUT/OUTPUT INSTRUCTIONS
ING 33 À 0011 À 0011 À G xA None Input G Ports to A
2A À 0010 À 1010 À

INL 33 À 0011 À 0011 À L7:4 x RAM(B) None Input L Ports to RAM, A

2E À 0010 À 1110 À L3:0 xA
OBD 33 À 0011 À 0011 À Bd xD None Output Bd to D Outputs
3E À 0011 À 1110 À

OMG 33 À 0011 À 0011 À RAM(B) xG None Output RAM to G Ports

3A À 0011 À 1010 À

XAS 4F À 0100 À 1111 À A Ý SIO, C x SKL None Exchange A with SIO

(Note 2)
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where
0 signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit A register.
Note 2: For additional information on the operation of the XAS, JID, and LQID instructions, see below.
Note 3: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 4: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
Note 5: The machine code for the lower 4 bits of the LBI instruction equals the binary value of the ‘‘d’’ data minus 1 , e.g., to load the lower four bits of B (Bd) with
the value 9 (10012), the lower 4 bits of the LBI instruction equal 8 (10002). To load 0, the lower 4 bits of the LBI instruction should equal 15 (11112).
Note 6: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a ‘‘1’’ or ‘‘0’’ in each bit of EN corresponds
with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)

16
Description of Selected Instructions Option List
The following information is provided to assist the user in The COP410L/411L mask-programmable options are as-
understanding the operation of several unique instructions signed numbers which correspond with the COP410L pins.
and to provide notes useful to programmers in writing The following is a list of COP410L options. The LED Direct
COP410L/411L programs. Drive option on the L Lines cannot be used if higher VCC
option is selected. When specifying a COP411L chip, Option
XAS INSTRUCTION
2 must be set to 3, Options 20, 21, and 22 to 0. The options
XAS (Exchange A with SIO) exchanges the 4-bit contents of are programmed at the same time as the ROM pattern to
the accumulator with the 4-bit contents of the SIO register. provide the user with the hardware flexibility to interface to
The contents of SIO will contain serial-in/serial-out shift reg- various I/O components using little or no external circuitry.
ister or binary counter data, depending on the value of the
Option 1 e 0: Ground Pin Ð no options available
EN register. An XAS instruction will also affect the SK out-
put. (See Functional Description, EN Register, above.) If Option 2: CKO Output (no option available for COP411L)
e 0: Clock output to ceramic resonator
SIO is selected as a shift register, an XAS instruction must
e 1: Pin is RAM power supply (VR) input
be performed once every 4 instruction cycles to effect a
e 3: No connection
continuous data stream.
Option 3: CKI Input
JID INSTRUCTION e 0: Oscillator input divided by 8 (500 kHz max)
JID (Jump Indirect) is an indirect addressing instruction, e 1: Single-pin RC controlled oscillator divided by 4
transferring program control to a new ROM location pointed e 2: External Schmitt trigger level clock divided by 4
to indirectly by A and M. It loads the lower 8 bits of the ROM
Option 4: RESET Input
address register PC with the contents of ROM addressed by e 0: Load device to VCC
the 9-bit word, PC8, A, M. PC8 is not affected by this instruc- e 1: Hi-Z input
tion.
Option 5: L7 Driver
Note that JID requires 2 instruction cycles to execute. e 0: Standard output
LQID INSTRUCTION e 1: Open-drain output
e 2: High current LED direct segment drive output
LQID (Load Q Indirect) loads the 8-bit Q register with the
e 3: High current TRI-STATE push-pull output
contents of ROM pointed to by the 9-bit word PC8, A, M.
e 4: Low-current LED direct segment drive output
LQID can be used for table lookup or code conversion such
e 5: Low-current TRI-STATE push-pull output
as BCD to seven-segment. The LQID instruction ‘‘pushes’’
the stack (PC a 1 x SA x SB) and replaces the least Option 6: L6 Driver
significant 8 bits of PC as follows: A x PC7:4, RAM(B) same as Option 5
x PC3:0, leaving PC8 unchanged. The ROM data pointed Option 7: L5 Driver
to by the new address is fetched and loaded into the Q same as Option 5
latches. Next, the stack is ‘‘popped’’ (SB x SA x PC), Option 8: L4 Driver
restoring the saved value of PC to continue sequential pro- same as Option 5
gram execution. Since LQID pushes SA x SB, the previ-
ous contents of SB are lost. Also, when LQID pops the Option 9: Operating voltage
stack, the previously pushed contents of SA are left in SB. COP41XL COP31XL
e 0: a 4.5V to a 6.3V a 4.5V to a 5.5V
The net result is that the contents of SA are placed in SB
(SA x SB). Note that LQID takes two instruction cycle Option 10: L3 Driver
times to execute. same as Option 5
Option 11: L2 Driver
INSTRUCTION SET NOTES
same as Option 5
a. The first word of a COP410L/411L program (ROM ad-
Option 12: L1 Driver
dress 0) must be a CLRA (Clear A) instruction.
same as Option 5
b. Although skipped instructions are not executed, one in-
Option 13: L0 Driver
struction cycle time is devoted to skipping each byte of
same as Option 5
the skipped instruction. Thus all program paths except
JID and LQID take the same number of cycle times Option 14: SI Input
whether instructions are skipped or executed. JID and e 0: load device to VCC
LQID instructions take 2 cycles if executed and 1 cycle if e 1: Hi-Z input
skipped. Option 15: SO Driver
c. The ROM is organized into 8 pages of 64 words each. e 0: Standard Output
The Program Counter is a 9-bit binary counter, and will e 1: Open-drain output
count through page boundaries. If a JP, JSRP, JID or e 2: Push-pull output
LQID instruction is located in the last word of a page, the Option 16: SK Driver
instruction operates as if it were in the next page. For same as Option 15
example: a JP located in the last word of a page will jump
to a location in the next page. Also, a LQID or JID located
in the last word of page 3 or 7 will access data in the next
group of 4 pages.

17
Option List (Continued)
Option 17: G0 I/O Port Option 25: L Input Levels
e 0: Standard output e 0: Standard TTL input levels (‘‘0’’ e 0.8V, ‘‘1’’ e 2.0V)
e 1: Open-drain output e 1: Higher voltage input levels (‘‘0’’ e 1.2V, ‘‘1’’ e 3.6V)
Option 18: G1 I/O Port Option 26: G Input Levels
same as Option 17 same as Option 25
Option 19: G2 I/O Port Option 27: SI Input Levels
same as Option 17 same as Option 25
Option 20: G3 I/O Port (no option available for COP411L) Option 28: COP Bonding
same as Option 17 e 0: COP410L (24-pin device)
Option 21: D3 Output (no option available for COP411L) e 1: COP411L (20-pin device)
e 0: Very-high sink current standard output e 2: Both 24- and 20-pin versions
e 1: Very-high sink current open-drain output
TEST MODE (NON-STANDARD OPERATION)
e 2: High sink current standard output
e 3: High sink current open-drain output The SO output has been configured to provide for standard
e 4: Standard LSTTL output (fanout e 1) test procedures for the custom-programmed COP410L.
e 5: Open-drain LSTTL output (fanout e 1) With SO forced to logic ‘‘1’’, two test modes are provided,
depending upon the value of SI:
Option 22: D2 Output (no option available for COP411L)
a. RAM and Internal Logic Test Mode (SI e 1)
same as Option 21
b. ROM Test Mode (SI e 0)
Option 23: D1 Output
same as Option 21 These special test modes should not be employed by the
user; they are intended for manufacturing test only.
Option 24: D0 Output
same as Option 21

Option Table
The following option information is to be sent to National along with the EPROM.

Option Data Option Data

OPTION 1 VALUE e 0 IS: GROUND PIN OPTION 15 VALUE e IS: SO DRIVER
OPTION 2 VALUE e IS: CKO PIN OPTION 16 VALUE e IS: SK DRIVER
OPTION 3 VALUE e IS: CKI INPUT OPTION 17 VALUE e IS: G0 I/O PORT
OPTION 4 VALUE e IS: RESET INPUT OPTION 18 VALUE e IS: G1 I/O PORT
OPTION 5 VALUE e IS: L(7) DRIVER OPTION 19 VALUE e IS: G2 I/O PORT
OPTION 6 VALUE e IS: L(6) DRIVER OPTION 20 VALUE e IS: G3 I/O PORT
OPTION 7 VALUE e IS: L(5) DRIVER OPTION 21 VALUE e IS: D3 OUTPUT
OPTION 8 VALUE e IS: L(4) DRIVER OPTION 22 VALUE e IS: D2 OUTPUT
OPTION 9 VALUE e 0 IS: VCC PIN OPTION 23 VALUE e IS: D1 OUTPUT
OPTION 10 VALUE e IS: L(3) DRIVER OPTION 24 VALUE e IS: D0 OUTPUT
OPTION 11 VALUE e IS: L(2) DRIVER OPTION 25 VALUE e IS: L INPUT LEV-
OPTION 12 VALUE e IS: L(1) DRIVER ELS
OPTION 13 VALUE e IS: L(0) DRIVER OPTION 26 VALUE e IS: G INPUT LEV-
ELS
OPTION 14 VALUE e IS: SI INPUT
OPTION 27 VALUE e IS: SI INPUT LEV-
ELS
OPTION 28 VALUE e IS: COPS BOND-
ING

18
Physical Dimensions inches (millimeters)

Hermetic Dual-In-Line Package (D)

Order Number COP311L-XXX/D or COP411L-XXX/D
NS Package Number D20A

Hermetic Package (D)

Order Number COP310L-XXX/D or COP410L-XXX/D
NS Package Number D24C

19
COP410L/COP411L/COP310L/COP311L
Single-Chip N-Channel Microcontrollers
Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N)

Order Number COP411N or COP311N
NS Package Number N20A

Molded Dual-In-Line Package (N)

Order Number COP410N or COP310N
NS Package Number N24A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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