1991 Xilinx Data Book PDF
1991 Xilinx Data Book PDF
1991 Xilinx Data Book PDF
1991
RECEiVED APR t. 5 1991
Xilinx, Logic Cell, LCA, XACT, and XACTOR, are trademarks of Xilinx,
Inc. The Programmable Gate Array Company is a Service Mark of trademarks of Mentor Graphics, Inc. ValidGED and ValidSim are
Xilinx,lnc. trademarks of Valid Logic Systems, Inc. Sun is a registered trademark
of Sun Microsystems, Inc. SCHEMA 11+ and SCHEMA III are trademarks
IBM is a registered trademark and PC/AT, PC/XT, PS/2, and Micro of Omation Corporation. OrCAD is a registered trademark of OrCAD
Channel are trademarks of International Business Machines Systems Corporation. VIEWlogic, VIEWsim, and VIEWdraw are
Corporation. ABEL is a trademark and Data 110 is a registered trademark registered trademarks of VIEWlogic Systems, Inc. CASE Technology is
of Data 110 Corporation. FutureNet is a registered trademark and DASH a trademark of CASE Technology, a division of Teradyne's Electronic
is a trademark of FutureNet Corporation, a Data 110 Company. SimuCad Design Automation Group. DECstation is a trademark of Digital
and Silos are registered trademarks and P-Silos and PIC-Silos are Equipment Corporation.
trademarks of SimuCad Corporation. Microsoft is a registered trademark
and MS-DOS is a trademark of Microsoft Corporation. Logitech is a Xilinx, Inc. does not assume any liability arising out of the application or
registered trademark of LOGITECH Inc. Lotus is a registered trademark useof any product described herein; nor does it convey any license under
of Lotus Development Corporation. AboveBoard and AboveBoardiPS its patent, copyright or maskwork rights or any rights of others. Xilinx, Inc.
are trademarks of Intel Corporation. RAMpage!, SixPakPlus and reserves the right to make changes, at any time, in order to improve
SixPakPremium are registered trademarks of AST Research, Inc. reliability, function or design and to supply the best product possible.
Mouse Systems is a trademark of Mouse Systems Corporation. Xilinx, Inc. cannot assume responsibility for the use of any Circuitry
Centronics is a registered trademark of Centronics Data Computer described other than circuitry entirely embodied in their product. No other
Corporation. PAL and PALASM are registered trademarks of Advanced circuit patent licenses are implied. Xilinx, Inc. cannot assume
Micro Devices, Inc. UNIX is a trademark of AT&T Technologies, Inc. responsibility for any circuits shown or represent that they are free from
CUPL is a trademark of Logical Devices, Inc.. Apollo and AEGIS are patent infringement or of any other third party right. Xilinx, Inc. assumes
registered trademarks of Hewlett-Packard Corporation. Mentor and no obligation to correct any errors contained herein or to advise any user
IDEA are registered trademarks and QuickSim, NETED, EXPAND are of this text of any correction if such be made.
SECTION TITLES
2 Product Specifications
4 Technical Support
5 Development Systems
6 Applications
7 Article Reprints
B Index
TABLE OF CONTENTS
2 Product Specifications
XC3000 Logic Cell Array Family 2-1
XC2064, XC2018 Logic Cell Arrays 2-61
Military Logic Cell Arrays 2-103
XC2018B Military Logic Cell Array 2-107
XC3020B Military Logic Cell Array 2-119
XC3042B Military Logic Cell Array 2-137
XC3090B Military Logic Cell Array 2-157
XC1736A11765 Serial Configuration PROM 2-175
Sockets 2-187
4 Technical Support
Technical Seminars and Users' Group Meetings 4-1
Video Tapes 4-2
Newsletter 4-3
Technical Bulletin Board 4-4
Field Applications Engineers 4-6
Training Course 4-7
Technical Literature 4-8
5 Development Systems
Overview 5-3
Automatic CAE Tools Product Overview 5-4
Product Briefs 5-19
Xilinx Development System Support Agreements 5-33
LCA Macro Library Listings 5-34
Development System Hardware Requirements 5-40
6 Applications
Introduction 6-1
Estimating Size and Performance 6-3
Designing with the XC3000 Family 6-7
Designing with the XC2000 Family 6-8
Additional Electrical Parameters 6-9
LCA Performance 6-11
Delay Tracking 6-14
Start-up and Reset 6-15
TABLE OF CONTENTS
6 Applications (Cont'dJ
Metastable Recovery 6-16
Battery Backup for Logic Cell Arrays 6-18
Compact Multiplexer and Barrel Shifter 6-19
Majority Logic, Parity 6-20
Multiple Address Decoding 6-21
Binary Adders, Subtractors, and Accumulators 6-22
Adders and Comparators 6-23
Conditional Sum Adder 6-26
Building Latches Out of Logic 6-27
Synchronous Counters, Fast and Compact 6-28
30 MHz Binary Counter Uses Less than One CLB per Bit 6-29
Up/Down Counter Uses One CLB per Bit 6-30
Loadable Up/Down Counter Uses One CLB per Bit 6-31
30 MHz Counter with Synchronous Reset/Preset 6-32
Fast Bidirectional Counters for Robotics 6-33
40 MHz Presettable Counter 6-34
Asynchronous Preset in XC3000 CLBs 6-36
Frequency/Phase Comparator for Phase-locked-Loops 6-37
Gigahertz Presettable Counter 6-38
75 MHz Frequency Counter or Programmable Delay 6-40
Serial Pattern Detectors 6-41
Serial Code Conversion Binary to BCD 6-42
Serial Code Conversion BCD to Binary 6-43
Corner Bender or 8-Bit Format Converter 6-44
100 MHz Frequency Counter 6-45
Megabit FIFO in Two Chips 6-46
State Machines 6-48
Complex State Machine in One LCA 6-49
PS/2 Micro Channel Interface 6-50
DRAM Controller with Error Correction 6-52
7 Article Reprints
Building Reconfigurable Peripheral Controllers 7-1
Accelerate FPGA Macros with One Hot Approach 7-8
Reprogrammable Missile: How an FPGA Adds Flexibility to
Navy's Tomahawk 7-13
Pivoting Monitor Increases Versatility of Workstations 7-15
Two, Two, Two Chips in One 7-19
LCA Stars in Video 7-22
Taking Advantage of Reconfigurable Logic 7-24
Faster Turnaround for a T1 Interface 7-33
Using Programmable Logic Cell Arrays In a Satellite Earthstation 7-35
Programmable Logic Betters the Odds for Bet-Slip readers 7-40
Building Tomorrow's Disk Controller Today 7-44
8 Index
Index 8-1
Sales Office Listing 8-5
The Programmable Gate Array Company
EXTENSIVE
SIMULATION
LOW
DENSITY
USER
PROGRAMMABLE
ADVANC
DEVELOPMENT
TOOLS
116201
2 Product Specifications
4 Technical Support
5 Development Systems
6 Applications
7 Article Reprints
8 Index
Programmable Gate Arrays
1-1
1-2
Introduction to
Programmable Gate Arrays
Steady advances in the level of intergration in electronic Field Programmable Gate Arrays (FPGAs), are high-
circuits have improved many equipment features, reducing density ASICs that can be configured by the user. They
costs, power consumption, and system size, while combine the logic integration benefits of custom VLSI with
increasing performance and reliability. Increasing levels of the design, production, and time-to-market advantages of
integration are most evident in microprocessor and standard products. Designers define the logic functions of
memory ICs. With each process generation, the the circuit and revise these functions as necessary. Thus
technology gap between these VLSI circuits and other
standard logic ICs has widened. To achieve comparable
densities for their proprietary logic functions, designers of
FPGAs can be designed and verified in a few days, as
opposed to several weeks for custom gate arrays; FPGA
design changes can require as little as a few hours,
II
digital equipment have been forced to consider factory- compared to several weeks for a custom array. This
programmed custom and semicustom Application Specific results in significant cost savings by reducing the risks of
Integrated Circuits (ASICs). design changes, rescheduling, and eliminating non-
recurring engineering costs.
ASIC ALTERNATIVES
Application Specific ICs are the best solution for most logic functions.
The best ASIC solution depends on density requirements and production volumes.
20,000 STANDARD
CELL AND
CUSTOM
10,000
z
0
f= 5,000
()
Z FIELD PROGRAMMABLE
:::J GATE ARRAYS
~
w 1,000
f-
<C
Cl
100
0
100 1,000 10,000 100,000
VOLUME/DESIGN 1101 01
1-3
Introduction to Programmable Gate Arrays
."." ..............!!
ji
DATAIN-.t"".d,-i -~=====t-----lj
i
~
i~
~~.x
lOOIC
VARIABLES:: -~:j::~~~C:MBINATORIAL
.d FUNCTION CLB OUTPUTS
::: .9 h-+t--'-----i+---H
ov
'O'(INHIBIT) ----l
1101 03
1-4
Input/Output Block
The periphery of the LCA device is made up of user
programmable Input/Output Blocks (lOBs). Each block
can be programmed independently to be an input, an Vo<
ollT-i---IL/
DIRECT IN -r-----t------,
III
REGISTERED IN -1-'---+--;
j}- PROGRAM
CONTROLLED
MULTIPLEXER o '" PROGRAMMABLE INTERCONNECTION POINT or PIP
110501A
D
000 000 000 00 a 00
0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 D D D D
0 0 0 0 0 0 0 0 0 0
0
00 0 0 0 0 0 0
0 0 0 0 0 0 0 0
DO 0 0 0 0 0 DO
D '"
1101 05
0 0 0 0 0
0
0
Do
DO
0
Interconnect
The flexibility of the LCA device is due to the program-
mabie resources that control the interconnection of any
0
0
0
0 0 0 0
two points on the chip. Like other gate arrays, the LCA
0 0 0
interconnection resources include a two-layer metal net-
work of lines that run horizontally and vertically in the rows 000 000 000 00 0 000 00 0 00 0
and columns between the CLBs. Programmable switches
connect the inputs and outputs of lOBs and CLBs to
1101 02
nearby metal lines. Crosspoint switches and interchanges
at the intersections of rows and columns can switch
signals from one path to another. Long lines run the entire
length or breadth of the chip, bypassing interchanges to
provide distribution of critical signals with minimum delay
or skew.
1-5
Introduction to Programmable Gate Arrays
XC2000
Programmable Logic Cell Array Family
1-6
E:XIUNX
XC3000
Logic Cell Array Family
II
1-7
Introduction to Programmable Gate Arrays
XC4000
Logic Cell Array Family
The XC4000 series, the third-generation family of CMOS achieve fully automated implementation of complex, high-
LCA devices, combines architectural versatility, on-chip performance designs. It is the first FPGA family to break
RAM, increased speed and gate complexity with abundant the 20,000-gate barrier; the first member of the XC4000
routing resources and new, sophisticated software, to family will be sampled in late 1990.
··
Hierarchy of interconnect lines Unlimited reprogrammability
Internal 3-state bus capability Six programming modes
0 Development system runs on '386-
0 Flexible array architecture based PC and on many popular
·· Programmable 110 blocks
Programmable logic blocks
workstations
· Fully automatic placement and
·· Programmable interconnects
Programmable wide decoders
routing plus optional interactive
enhancements
XC4002 4003 4004 4005 4006 4008 4010 4013 4016 4020
Appr. Gate Count 2,000 3,000 4,000 5,000 6,000 8,000 10,000 13,000 16,000 20,000
CLB Matrix 8x8 10 x 10 12 x 12 14x 14 16 x 16 18 x 18 20 x 20 24x24 26 x 26 30 x 30
Configurable Logic Blocks 64 100 144 196 256 324 400 576 676 900
Max RAM Bits 2,048 3,200 4,608 6,272 8,192 10,368 12,800 18,432 21,632 28,800
InputlOutpts 64 80 96 112 128 144 160 192 208 240
The XC4000 family of Logic Cell Arrays is not covered in this Data Book.
1-8
Development Systems
Designing with Xilinx FPGAs is similar to designing with other gate arrays.
Designers can use familiar CAE tools for design entry and simulation. The
open Xilinx development system includes a standard nellist format, the Xilinx
Nellist File (XNF), that provides a bridge between schematic editors or
simulators, and the XACT software for design implementation and real time
design verification. The Xilinx software is supported on the PC/AT and
compatibles as well as on popular engineering workstations.
Step 1
DS371
II
DESIGN
ENTRY
DESIGN EDITOR
TIMING CALCULATOR
Design Implementation Software
DOWNLOAD CABLE
BITSTREAM GENERATOR is used to convert schematic netlists and
DS21
Boolean equations into efficient designs
Step 3 for programmable gate arrays. The soft·
ware includes programs that perform par·
DESIGN
VERIFICATION
titioning, optimization, placement and
routing, and interactive design editing.
~X1l1NX
XACTOR
XC3020-70 DESIGN VERIFIER
PC68C
X9201MB730
In·circuit Design Verification Tools
DS26127/28
permit real·time verification and
debugging of a programmable gate array
design as soon as it is placed and routed.
110106B Designers benefit from faster and more
comprehensive design verification, and
from reduced requirements to generate
simulation vectors to exercise a design.
1·9
Introduction to Programmable Gate Arrays
To get up-to-speed quickly, new Xilinx users are invited to o User's Guide
attend comprehensive training classes. These classes The User's Guide is a collection of "how to" applications
are taught by factory experts and include the latest soft- notes on such subjects as getting started with an LCA
ware and hardware advances. design, Boolean equation design entry, use of the
simulator, placement and routing optimization, and
LCA configuration.
XILINX USER GROUPS
Xilinx users are invited to attend training and information
exchange sessions that are held two-to-three times per
o Reference Manuals (2 vols)
The XACT Reference Manuals include a detailed de-
year in various locations worldwide. These User Group
scription of each Xilinx software program.
meetings are intended for experienced users of Xilinx
Programmable Gate Arrays, and they emphasize the
efficient use of the XACT development system. o Macro library
The Xilinx development system includes over 100
FIELD APPLICATIONS macros, including counters, registers, and multiplex-
ENGINEERS ers. The macro library manual includes schematics
and documentation for each macro.
Xilinx provides local technical support to customers
through a network of Field Applications Engineers (FAEs).
For the name and phone number of the nearest FAE,
customers may call one of the Xilinx sales offices listed in
the back of this book.
BULLETIN BOARD
1-10
A Cost of Ownership
Comparison
1-11
A Cost of Ownership Comparison
Figure 1 shows a representative break-even graph for a Several significantfactors are omitted from Figure 1. First,
2000-gate device using 1990 data. The vertical axis the additional fixed costs (NRE, simulation) of bringing on
shows the total project cost-fixed costs plus unit costs a custom-gate-array second source are not included.
multiplied by the number of units. At lower volumes, the Second, and much more important, the cost of the longer
custom gate array is more expensive because of fixed time to market when deSigning with the mask gate array is
costs that are incurred even if no units are purchased. The not included. This factor is reviewed in the Time to Market
FPGA project cost starts at zero, but rises faster because section. Both of these factors would raise the custom gate
of a higher cost per-unit. In this case the break-even array curve and inc~ease the break-even quantity. In other
volume is between 10k and 20k units. The various words, the FPGA would be more cost effective at an even
components of this analysis are discussed in the following higher production volume.
sections. Also, guidelines are given to help the user make
a simple calculation for a specific solution. ROM VS EPROM ANALOGY
There is a relevant historical precedent for the use of a
flexible standard product instead of a custom product with
a lower direct cost perunit. While EPROMs have a cost per
TOTAL
PRQJECT
bit that is two to three times that of ROMs, they have
COST ($) consistently captured almost half the programmable
memory market, measured in bits shipped. See Figure 2.
Many of the reasons for the use of EPROMs are the same
as those for the use of programmable gate arrays: faster
time to market, lower inventory risks, easy design
changes, faster delivery, and second sources. The higher
~:Jg~~~
NRE } price per bit is offset by the elimination of inventory and
SIMULATION TIME
DESIGNING TESTABILITY
production risks.
TEST PROGRAM
DESIGN ITERAnONS L -_ _ _ _ _ _ ______ Gate arrays have even more disadvantages versus pro-
~
~
~
L
10k .ok grammable gate arrays than do ROMs versus EPROMs.
PROJECT UNITS The upfront design time, risk, and expense of ROMs is
minimal, while that of gate arrays is substantial. ROM test
- CUSTOM GATE ARRAY 1102 01A
-FPGA
tape generation is automatic, while that for gate arrays
requires extensive engineering effort. Therefore, FPGAs
Figure 1. Typical Break-even Analysis 2000 Gates-1990 may be even more widely used versus gate arrays than are
EPROMs versus ROMs.
140
120
100
TERABITS
SHIPPED
80
~
60
~
40
20
0
1983 1984 1985 1986 1987 1988 1989
EPROM Mll.¢IBlT 10.9 9.2 4.0 2.5 1.8 1.3 0.9
ROM MIL¢!BIT 4.5 3.2 1.7 1.0 0.7 0.5 0.4
RATIO 2.4 2.9 2.4 2.5 2.6 2.6 2.3
SOURCE: DATAQUEST
1102 05
1-12
WHO RECOGNIZES THE COSTS? explicitly for computer time, an estimate would be $2,500
and 2.5 man weeks of simulation effort for a 2000-gate
Many of the elements of the total cost of ownership for a
array, and $5,000 and seven man weeks for a 9000-gate
gate array do not accrue to a single department, and often
array. This compares to 0.5 and 1 week forthe FPGA, with
are not fully recognized. For example, the additional
engineering time needed to design for testability may not no simulation charge.
be seen by purchasing. The inventory costs of a custom Typically one fully burdened man week, including
product may not be recognized by the design department. computer support, costs about $2000.
However, these are real costs, and they influence the
profitability of the product and company. The person 2000 Gates 9000 Gates
making the choice between custom gate arrays and
FPGAs should consider the total costs of ownership for Gate Array
each alternative.
1-13
A Cost of Ownership Comparison
Industry data suggest that about half of all gate-array de- 2000 Gates 9000 Gates
signs are modified before they are released to production.
When a modification is required, NRE costs are incurred NRE $10k-$20k $20 k-$40 k
for the second pass. Since resimulation is likely to involve Simulation
less effort than the initial simulation, 25% (50% probability Charge $1.2Sk $2.Sk
times one half the effort) of the simulation cost is added. Man Weeks 1MW 3MW
1-14
Typical Typical Customer
2000 Gates 9000 Gates Application
1. Simulation
NRE $2,500 $5,000
Man Weeks 2MW 7MW
2. Design for Testability 1MW 2MW
3. NRE Charges $10 k-$20 k $20 k-$40 k
4. Design Iterations @ 50% probability
NRE $8,125 $16,250
Man Weeks 0.5MW 1.5MW
5. Test Program Development 2MW 4MW
6. Second Source (NRE + 50% SIM)
NRE
Man Weeks
$16,250
1MW
$32,500
3MW
II
Total Without Second Source
NRE $25,625 $51,250
Man Weeks 5.5MW 14.5MW
Total With Second Source
NRE $41,875 $83,750
Man Weeks 6.5MW 17.5 MW
VARIABLE COSTS while gate arrays are in a more mature phase of the cycle.
Production Unit Cost (Cents/Gate) Price comparisions should be based on projections over
the production life of the product.
Gate-array prices are often quoted in terms of cents per
gate. For 1.2 micron, 2000-gate arrays, at the volumes A standard product has more silicon content and less fac-
considered in this analysis (10,000 to 30,000 units), a tory overhead than a custom product. Since all customers
figure of 0.15 - 0.20 cents/gate (without package) is buy the same product, there is more of the semiconductor
typical. At similar volumes, the cost per gate (without learning curve with cumulative volume. Given the profit-
package) for an FPGA is two to three times the cost of a ability levels of array manufacturers, gate array prices may
custom gate array. For reasons explained below, this gap decline only Slightly over time and could even rise.
is expected to narrow over the next few years. All of the
cents/gate numbers are for die only. Since CMOS gate 1991 FPGA Unit Costs-
arrays and FPGAs use the same packages, the package Without Package
adders are equivalent.
2000 4000 9000
An important consideration in calculating the total cost of Gates Gates Gates
ownership is the year during which most of the production
volume will be purchased. Since FPGAs are newer 20kOty 10kOty 10 kOty
products, their cost is declining at a steeper rate than gate Programmable 0.30-0.40 0.40-0.50 0.50-0.60
arrays. They are in the introduction phase of the life cycle, (Cents/Gate)
1-15
A Cost of Ownership Comparison
Process Technology volume applications, few gate arrays are retooled to take
advantage of process advances. The time from design
There are also technology reasons for the steeper decline
start to end of production lifetime is usually several years.
in FPGA cost. Figure 3 shows that the processes used for
Overthis period, the FPGA will move to successively more
logic IGs, including gate arrays, typically lag behind those
advanced processes, resulting in steadily decreasing
used for memory IGs. Since the FPGA is a standard IG
costs. By the end of the production lifetime, the FPGA will
built on a memory process, it can take advantage of each
be several processes ahead and the cost difference will be
new process to shrink the die and reduce costs.
reduced significantly.
With a conventional gate array, the process that is avail-
Pad-Limited Die Sizes
able at the time of design is usually used throughout the
production lifetime of the product. Except for very high- As gate arrays and FPGAs grow in 110 pin count, a phe-
nomenon known as "pad-limiting" is more likely to occur.
The spacing between 1/0 pads is determined by mechani-
cal limitations of the equipment used for lead bonding. In
I/O-intensive applications the number of pads around the
outer edge of the die determines the die size, instead of the
number of gates. See Figure 4. In I/O-intensive applica-
tions, a "cost per 1/0" may be a more useful measure than
"cost per gate."
PAD-LIMITED DIE
350
300 000000000000000
o 0
o 0
250 o 0
o 0
o 0
DIE 200 o 0
WIDTH o 0
MILS 150 o 0
o 0
o 0
100 o 0
o 0
50
o 0
000000000000000
0
40 60 80 100 120 140 160 180
1102 OlA
NUMBER OF PADS
1-16
Effect of Die Cost on Total Cost mum economical wafer-lot quantity. Inventory is created
and costs are incurred. Moreover, there is the problem of
Figure 5 illustrates a third point about the capability of FP-
inventory ownership if the parts are never ordered by the
GAs to narrow the cost difference with custom gate arrays.
customer.
The chart shows the contribution to total device cost of
wafer, die, assembly and test. Wafer cost represents Although the safety stock reserve is a function of the cost of
about 20% to 40% of the total device cost, and die cost the product itself, a figure of 10% is reasonable for gate
about 30% to 50%. A 50% difference in die cost - between arrays that have unit costs under $25.00. In comparison,
a gate array and a FPGA - shown in the chart translates to since changes to FPGAs can be made in software in min-
only a 20% difference (80 vs 100) in total cost by the time utes, and since only one part type is widely stocked, the
the device has been tested. This comparison is based on comparative safety stock reserve is 0%.
production of the FPGA in a more advanced process than
the custom gate array, as discussed in the Unit Cost
(Cents/Gate) section.
Gate Array Incremental Inventory Cost II
10% Additional Unit Cost
Inventory Reserves
Inventories include extra devices ordered and stocked to
YIELD TO PRODUCTION
cover contingencies. For a custom product, this is the only
way parts can be delivered in less than the normal produc- Due to rapidly changing markets, many designs never go
tion time (2-4 months). Contingencies are often thought of into production. Sometimes a company will develop com-
in terms of negative events like a defective lot or manu- peting projects, with only one moving to production. Many
facturing shortfalls. times the market will change, or competition will emerge,
and projects will be cancelled or redirected. Of course
However, contingencies also include positive events like each design team expects that its project will succeed, but
stocking for large, upside orders or where demand is diffi- in the aggregate this is not true. If a company chooses gate
cult to estimate. This can be especially true during a arrays as the primary logic technology, and starts many
product's introduction, when design changes and demand deSigns, this factor will occur.
spikes occur simultaneously.
According to Dataquest ASIC and Standard Logic Semi-
With a custom product it is also necessary to build inven- conductor Volume 1,only 50% of gate-array designs go
tory as the product nears the end of its life cycle. Demand into production. Therefore, the true cost of the gate array
is low and difficult to forecast, and it may not be possible should recognize additional costs for simulation, design-
to reorder a small quantity. Spares and replacements ing for testability, and NRE. For 2000 gates, using the
must be stocked. A JIT(just in time) inventory system is numbers in the Summary of Fixed Development Costs
less practical. section, this would mean an additional ($2,500 + 3 MW +
$15,000). For9000 gates the number is ($5,000 +8 MW +
Since minimum manufacturing quantities for semiconduc- $30,000).
tors are determined by wafer lots, a custom product will
have excess WIP (work in process) or finished goods in- Gate Array Incremental Cost
ventory if the deSired order quantity is less than the mini-
Simulation Cost + Time to Design for Testability + NRE Cost
100
• GATE ARRAY (21')
8() 60
w
>
~
w
40
a:
20
0
WAFER DIE ASSEMBLY TEST 1102 04A
1-17
A Cost of Ownership Comparison
COST OF OWNERSHIP ANALYSIS Table 2 is a form that can be used for calculating the total
cost of ownership at various volumes. Table 2 points tothe
While gate arrays have a lower unit cost, they have incre-
"break-even quantity"-the quantity where the unit cost of
mental fixed costs that must be incurred before the first unit
the two devices is the same-of the next section.
is received. Example costs are shown in Table 1 (Sum-
mary of Fixed Development Costs). Therefore, at lower
unit volumes the FPGA is less expensive, until the gate
array can amortize the up-front fixed costs.
2. Unit cost
1-18
BREAK EVEN ANALYSIS At the 2,000 gate level, assume the gate array is used in a
$2,000 product that has 15% profit margins. For 10,000
Figure 6 is agraphic representation of the break-even
units sold:
calculation for the case of 2000 gates, 1990 pricing, and
no second source. Up to the break-even unit volume, Lost Profit = $2,000 x 10,000x 15%x 1/3= $1.0 million or
the programmable gate array solution has a lower total $100 per device
project cost.
At the 9000 gate level, assume the gate array is used in a
Similar graphs can be built for different assumptions $10,000 product that has 20% profit margins. For 2000
by filling in Table 1. For the gate array, the break-even units sold:
graph is merely line 5 or line 11 plotted versus quantity.
For the FPGA it is line 13 times the quantity plotted Lost Profit=$10,000x 2,000x 20%x 1/3=$1.33 million or
$667 per device
versus the quantity.
Note that these catastrophic costs are not included in any
II
TOTAL
PROJECT
of the previous sections. They are a quantitative estimate
COST ($) of the risk of using a custom product.
1-19
The Programmable Gate Array Company
1-20
SECTION 2
Product Specifications
2 Product Specifications
4 Technical Support
5 Development Systems
6 Applications
7 Article Reprints
8 Index
Product Specifications
Product Specification
DESCRIPTION
ARCHITECTURE
The CMOS XC3000 Logic CeWM Array (LCNM) family
provides a group of high-performance, high-density, The perimeter of configurable 1/0 Blocks (lOBs) provides
digital integrated circuits. Their regular, extendable, a programmable interface between the internal logic array
flexible, user-programmable array architecture is and the device package pins. The array of Configurable
composed of a configuration program store plus three Logic Blocks (CLBs) performs user-specified logic func-
typesofconfigurable elements: a perimeter of lOBs, acore tions. The interconnect resources are programmed to
array of CLBs and resources for interconnection. The form networks, carrying logic signals among blocks,
general structure of an LCA device is shown in Figure 1 on analogous to printed circuit board traces connecting
the next page. The XACT development system provides MSI/SSI packages.
schematic capture and auto place-and-route for design
entry. Logic and timing simulation, and in-circuit emulation The blocks' logic functions are implemented by pro-
are available as design verification alternatives. The grammed look-up tables. Functional options are imple-
design editor is used for interactive design optimization, mented by program-controlled multiplexers. Intercon-
and to compile the data pattern that represents the necting networks between blocks are implemented with
configuration program. metal segments joined by program-controlled pass tran-
2-1
XC3000 Logic Ceil Array Family
sistors. These LCA functions are established by a configu- and only read during readback. During normal operation,
ration program which is loaded into an internal, distributed the cell provides continuous control and the pass transistor
array of configuration memory cells. The configuration is "off" and does not affect cell stability. This is quite
program is loaded into the LCA device at power-up and different from the operation of conventional memory de-
may be reloaded on command. The Logic Cell Array vices, in which the cells are frequently read and re-written.
includes logic and control signals to implement automatic
or passive configuration. Program data may be either bit The memory cell outputs Q and a
use ground and Vcc
serial or byte parallel. The XACT development system levels and provide continuous, direct control. The addi-
generates the configuration program bitstream used to tional capacitive load together with the absence of address
configure the Logic Cell Array. The memory loading decoding and sense amplifiers provide high stability to the
process is independent of the user logic functions. cell. Due to the structure of the configuration memory
Configuration Memory
"J
even under adverse conditions. Compared with other DATA-!!
programming alternatives, static memory provides the
1.:. .:.:.:.:.;.:.:.:
best combination of high density, high performance, high 110512
y----------------y- ~ y-
o y-
0 y-
O y-
0 t-
4.-
o
u
p y-
o y- t-
2-2
cells, they are not affected by extreme power-supply 1/0 Block
excursions orvery high levels of alpha particle radiation. In
reliability testing, no soft errors have been observed even Each user-configurable lOB shown in Figure 3, provides
in the presence of very high doses of alpha radiation. an interface between the external package pin of the
device and the internal user logic. Each lOB includes both
The method of loading the configuration data is selectable. registered and direct input paths. Each lOB provides a
Two methods use serial data, while three use byte-wide programmable 3-state output buffer, which may be driven
data. The internal configuration logic utilizes framing by a registered or direct output signal. Configuration
information, embedded in the program data by the XACT options allow each lOB an inversion, a controlled slew rate
development system, to direct memory-cell loading. The and a high impedance pull-up. Each input circuit also
serial-data framing and length-count preamble provide provides input clamping diodes to provide electro-static
programming compatibility for mixes of various LCAs in a protection, and circuits to inhibit latch-up produced by
synchronous, serial, daisy-chain fashion. input currents.
1/0 PAD
CK1
=0- PROGRAM
CONTROLLED
MULTIPLEXER o = PROGRAMMABLE INTERCONNECTION POINT or PIP
CK2
110501C
Figure 3. Input/Output Block. Each lOB includes input and output storage elements and I/O options selected by
configuration memory cells. A choice of two clocks is available on each die edge. The polarity of each clock line (not
each flip-flop or latch) is programmable. A clock line that triggers the flip-flop on the rising edge is an active Low Latch
Enable (Latch transparent) signal and vice versa. Passive pull-up can only be enabled on inputs, not on outputs.
All user inputs are programmed for TIL or CMOS thresholds.
2-3
XC3000 Logic Cell Array Family
The input buffer portion of each lOB provides threshold buller. The 3-state control signal [lOB pin .~ can control
detection to translate external signals applied to the output activity. An open-drain-type output may be ob-
package pinto internal logic levels. The global input-buffer tained by using the same signal for driving the output and
threshold of the lOBs can be programmed to be 3-state signal nets so that the buffer output is enabled only
compatible with either TTL or CMOS levels. The buffered for a Low.
input signal drives the data input of a storage element,
which maybe configured as either a flip-flop or a latch. The Configuration program bits for each lOB control features
clocking polarity (rising/falling edge-triggered flip-flop, such as optional output register, logical signal inverSion,
High/Low transparent latch) is programmable for each of and 3-state and slew-rate control of the output.
the two clock lines on each ofthe four die edges. Note that
a clock line driving a rising edge-triggered flip-flop makes The program-controlled memory cells of Figure 3 control
any latch driven by the same line on the same edge Low- the following options:
level transparent and vice versa (falling edge, High
• Logic Inversion of the output is controlled by one
transparent). All Xilinx primitives in the supported
configuration program bit per lOB.
schematic-entry packages, however, are positive edge-
triggered flip-flops or High transparent latches. When one
clock line must drive flip-flops as well as latches, it is • Logic 3-state control of each lOB output buller is
necessary to compensate for the difference in clocking determined by the states of configuration program bits
polarities with an additional inverter either in the flip-flop which turn the buller on, or off, or select the output buffer
clock input orthe latch-enable input. I/O storage elements 3-state control interconnection [lOB pin.f]. When this
are reset during configuration or by the active-Low chip lOB output control signal is High, a logic one, the buffer
RESET input. Both direct input [from lOB pin ./] and is disabled and the package pin is high impedance.
registered input [from lOB pin .q] signals are available for When this lOB output control signal is Low, a logiC zero,
interconnect. the buffer is enabled and the package pin is active.
Inversion of the buffer 3-state control logic sense (output
For reliable operation, inputs should have transition times enable) is controlled by an additional configuration
of less than 100 ns and should not be left floating. Floating program bit.
CMOS input-pin circuits might be at threshold and produce
oscillations. This can produce additional power dissipa- • Direct or registered output is selectable for each lOB.
tion and system noise. A typical hysteresis of about The register uses a positive-edge, clocked flip-flop. The
300 mV reduces sensitivity to input noise. Each user lOB clock source may be supplied [lOB pin .ok] by either of
includes a programmable high-impedance pull-up resis- two metal lines available along each die edge. Each of
tor, which may be selected by the program to provide a these lines is driven by an invertible buffer.
constant High for otherwise undriven package pins. Al-
though the Logic Cell Array provides circuitry to provide • Increased output transition speed can be selected to
input protection for electrostatic discharge, normal CMOS improve critical timing. Slower transitions reduce
handling precautions should be observed. capacitive-load peak currents of non-critical outputs and
minimize system noise.
Flip-flop loop delays for the lOB and logic-block flip-flops
are about 3 ns. This short delay provides good perfor- • A high-impedance pull-up resistor may be used to
mance under asynchronous clock and data conditions. prevent unused inputs from floating.
Short loop delays minimize the probability of a metastable
condition that can result from assertion of the clock during Summary of 1/0 Options
data transitions. Because of the short-loop-delay charac-
teristic in the Logic Cell Array, the lOB flip-flops can be • Inputs
used to synchronize external signals applied to the device. • Direct
Once synchronized in the lOB, the signals can be used • Flip-flop/latch
internally without further consideration of their clock rela- • CMOS/TIL threshold (chip inputs)
tive timing, except as it applies to the internal logic and • Pull-up resistor/open circuit
routing-path delays. • Outputs
• Direct/registered
lOB output buffers provide CMOS-compatible 4-mA • Inverted/not
source-or-sink drive for high fan-out CMOS or TIL- • 3-state/on/off
compatible signal levels. The network driving lOB pin .0 • Full speed/slew limited
becomes the registered ordirect data source forthe output • 3-state/output enable (inverse)
2-4
~XlUNX
Configurable Logic Block Each configurable logic block has a combinatorial logic
section, two flip-flops, and an internal control section. See
The array of Configurable Logic Blocks (CLBs) provides Figure 4. There are: five logic inputs [.a, .b, .C, .dand .e];
the functional elements from which the user's logic is a common clock input [.k); an asynchronous direct reset
constructed. The logic blocks are arranged in a matrix input [.rdJ; and an enable clock [. ec]. All may be driven from
within the perimeter of lOBs. The XC3020 has 64 such the interconnect resources adjacent to the blocks. Each
blocks arranged in 8 rows and 8 columns. The XACT CLB also has two outputs [.x and .YJ which may drive in-
development system is used to compile the configuration terconnect networks.
data which are to be loaded into the internal configuration
memory to define the operation and interconnection of Data input for either flip-flop within a CLB is supplied from
each block. User definition of configurable logic blocks the function F orG outputs of the combinatorial logic, or the
and their interconnecting networks may be done byauto- block input, data-in [.d/]. Both flip-flops in each CLB share
matic translation from a schematic capture logic diagram the asynchronous reset [.rdj which, when enabled and
or optionally by installing library or user macros. High, is dominant over clocked inputs. All flip-flops are
DATA IN -i....:.:.d::,.i- - - - - - - - - - - ,
ox .x
.a
.b
F14+....-11------+-+---...11----1
VAR~~~~ -f~--:.:1:~;------fCo~~~~g~IAL CLBOUTPUTS
.e G~+~~-----+-+----~
oy
ENABLECLOCK-f-·"'ec><-------------_i
"1" (ENABLE) - - - - - - I
CLOCK-t~·~k----------~
1105 02A
Figure 4. Configurable Logic Block. Each CLB includes a combinatorial logic section.
two flip-flops and a program memory controlled multiplexer selection of function.
It has: five logic variable inputs .a, .b, .c, .d and .e.
a direct data in .di
an enable clock .ec
a clock (invertible) .k
an asynchronous reset .rd
two outputs .x and .y
2-5
XC3000 Logic Cell Array Family
ANY FUNCTION
OF UPTO 4
VARIABLES
F COUNTENABLE==1lrFr~~~~~~t=)-------
PARALLEL ENABLE i___
___,TCEORUMNITNAL
CLOCK
g::===:::!::~
E -',------------1/ DUAL FUNCTION OF 4 VARIABLES
~=~===========t~-r--------~
DO~F====~
....,..-------1
OX
00
ANY FUNCTION
OF UPTO 4 G
VARIABLES
g::===:::!::~
E-'i-------j,.) FG FG
5a MODE MODE
A-'~--------------~
B """', 'ox
O:(::::;:::======f1 F 01
ANY FUNCTION
OF 5 VARIABLES
G
F
F FUNCTION OF 5 VARIABLES MODE
5b MODE
02
FUNCTION OF 6 VARIABLES
FGM
MODE
110503A
2-6
reset by the active Low chip input, RESET, or during the (as are block outputs) they are usable only for block
configuration process. The flip-flops share the enable Input connection and not routing. Figure 8 illustrates
clock [.ee] which, when Low, recirculates the flip-flops' routing access to logic block input variables, control inputs
present states and inhibits response to the data-in or and block outputs. Three types of metal resources are
combinatorial function inputs on a CLB. The user may provided to accommodate various network interconnect
enable these control inputs and select their sources. The requirements:
user may also select the clock net input [.k], as well as its
active sense within each logic block. This programmable • General Purpose Interconnect
inversion eliminates the need to route both phases of a • Direct Connection
clock signal throughout the device. Flexible routing allows • Long Lines (multiplexed busses and wide AND gates)
use of common or individual CLB clocking.
General Purpose Interconnect
The combinatorial-logic portion of the logic block uses a 32
by 1 look-up table to implement Boolean functions. Vari- General purpose interconnect, as shown in Figure 9,
ables selected from the five logic inputs and two internal consists of a grid of five horizontal and five vertical metal
block flip-flops are used as table address inputs. The segments located between the rows and columns of logic
•
combinatorial propagation delay through the network is and lOBs. Each segment is the "height" or ''width'' of a logic
independent of the logic function generated and is spike block. Switching matrices join the ends of these segments
free for single input variable changes. This technique can and allow programmed interconnections between the
generate two independent logic functions of up to four metal grid segments of adjoining rows and columns. The
variables each as shown in Figure 5a, or a single function switches of an unprogrammed device are all non-
of five variables as shown in Figure 5b, or some functions conducting. The connections through the switch matrix
of seven variables as shown in Figure 5c. Figure 6 shows may be established by the automatic routing or by using
a modulo 8 binary counter with parallel enable. It uses one Editnet to select the desired pairs of matrix pins to be
CLB of each type. The partial functions of six or seven connected or disconnected. The legitimate switching
variables are implemented using the input variable [.e] to matrix combinations for each pin are indicated in Figure 10
dynamically select between two functions of four different and may be highlighted by the use of the Show-Matrix
variables. Forthe two functions of four variables each, the command in XACT.
independent results (F and G) may be used as data inputs
to either flip-flop or either logic block output. For the single INTERCONNECT SWITCHING
function of five variables and merged functions of six or "PIPs" MATRIX
seven variables, the F and G outputs are identical. Sym- . .....
1
/: . t-· .:.
.: ¥ - . .
metry of the F and G functions and the flip-flops allows the
interchange of CLB outputs to optimize routing efficiencies
of the networks interconnecting the logic blocks and lOBs.
0,::,',:,::0
.. . : ~- ...
PROGRAMMABLE INTERCONNECT
network from the adjacent interconnect segments. As the Figure i'. An XACT view of routing resources used to form a
switch connections to block inputs are unidirectional typical interconnection network from CLB GA.
2-7
XC3000 Logic Cell Array Family
t·.; .:
····5 .' t- ...
'::El .: t-·.: .
~
0··:·····
.. '
0·:.· : 0:.'
-4-.~.~~ ... ~- .. +-'
~":'
'\' O'
.': . : .
"0 :" • • .:: •• : -0. :" ••• :. •• :
~-":'
•••
.. ~.
: : : : :
t- . .. t· r' t- . ..
0:·
~-...
.. .
.. :0'.~
.... :
.. -4- 0':· :0'
.
...
~-
.
.. ~.
: :
: '::0 :
: '::·0 : :
: '::El : :
:
X1198
Some of the interconnect PIPs are directional. This is indicated on the XACT design editor status line:
NO is a nondirectional interconnection.
D:H->V is a PIP which drives from a horizontal to a vertical line.
D:V->H is a PIP which drives from a vertical to a horizontal line.
O:C-> T is a "T' PIP which drives from a cross of a T to the tail.
D:CW is a corner PIP which drives in the clockwise direction.
PO indicates the PIP is non-conducting, P1 is "on."
2-8
--------~- --~~-.-
E:XiUl\lX
Special buffers within the general interconnect areas pro- interconnect to drive the .d input of the block immediately
vide periodic signal isolation and restoration for improved above and the .a input of the block below. Direct intercon-
performance of lengthy nets. The interconnect buffers are
r
available to propagate signals in either direction on a given
~ ~~~
general interconnect segment. These bidirectional (bid i)
buffers are found adjacent to the switching matrices,
above and to the right and may be highlighted by the use
of the "Show BIOI" command in XACT. The other PIPs 1 2 3 4 5
adjacent to the matrices are access to or from long lines.
gz~ ~~ ~~ ~= ~~
The development system automatically defines the buffer
direction based on the location of the interconnection
network source. The delay calculator of the XACT devel-
opment system automatically calculates and displays the 6 7 8 9 10
block, interconnect and buffer delays for any paths se-
~~~~~
lected. Generation of the simulation netlist with a worst-
case delay model is provided by an XACT option.
Direct Interconnect 11 12 13 14 15
II
Direct interconnect, shown in Figure 11 , provides the most
efficient implementation of networks between adjacent
logic or I/O Blocks. Signals routed from block to block
using the direct interconnect exhibit minimum interconnect
propagation and use no general interconnect resources.
For each CLB, the .x output may be connected directly to
~~ ~ ~~
16
6 II
17
I
18
the .b input of the CLB immediately to its right and to the .c for Each Pin. Switch matrices on the edges are different.
input of the CLB to its left. The .youtput can use direct Use Show Matrix menu option in XACT
.. .. EJA :.:-:
.. .. ·:.-El
t· r·.; .: .' t
0 ······
...
.. . :
..
. . ......
~
'.
GRID OF GENERAL INTERCONNECT
METAL SEGMENTS
·:.-El a,.: : :
l:
: :
: El
X1198
Figure 9. LCA General-Purpose Interconnect. Figure 11. CLB.X and.V Outputs. The.x and.y
Composed of a grid of metal segments which may be outputs of each CLB have single contact, direct
interconnected through switch matrices to form networks access to inputs of adjacent CLBs.
for CLB and lOB inputs and outputs.
2-9
XC3000 Logic Cell Array Family
Figure 12. X3020 Die-Edge lOBs. The X3020 die-edge lOBs are provided with direct access to adjacent CLBs.
2-10
nect should be used to maximize the speed of high- A buffer in the upper left corner of the LCA chip drives a
performance portions of logic. Where logic blocks are global net which is available to all .k inputs of logic blocks.
adjacent to lOBs, direct connect is provided alternately to Using the global buffer for a clock signal provides a skew-
the lOB inputs [./] and outputs [.0] on all four edges of the free, high fan-out, synchronized clock for use at any or all
die. The right edge provides additional direct connects of the I/O and logic blocks. Configuration bits for the .k
from CLB outputs to adjacent lOBs. Direct interconnec- input to each logic block can select this global line or
tions of lOBs with CLBs are shown in Figure 12. another routing resource as the clock source for its flip-
flops. This net may also be programmed to drive the die
Long Lines edge clock lines for lOB use. An enhanced speed, CMOS
threshold, direct access to this buffer is available at the
The long lines bypass the switch matrices and are in- second pad from the top of the left die edge.
tended primarily for signals that must travel a long dis-
tance, or must have minimum skew among multiple des- A buffer in the lower right corner of the array drives a
tinations. Long lines, shown in Figure 13, run vertically and horizontal long line that can drive programmed connec-
horizontally the height or width of the interconnect area. tions to a vertical long line in each interconnection column.
Each interconnection column has three vertical long lines, This alternate buffer also has low skew and high fan-out.
and each interconnection row has two horizontal long The network formed by this alternate buffer's long lines
lines. Two additional long lines are located adjacent to the
outer sets of switching matrices. In devices larger than the
XC3020, two vertical long lines in each column are con-
can be selected to drive the .k inputs of the logic blocks.
CMOS threshold, high speed access to this buffer is
available from the third pad from the bottom of the right die
II
nectable half-length lines. On the XC3020, only the outer edge.
long lines are connectable half-length lines. Internal Busses
Long lines canbe driven by a logic block or lOB output on A pair of 3-state buffers, located adjacent to each CLB,
a cOlumn-by-column basis. This capability provides a permits logic to drive the horizontal long lines. Logic
common low skew control or clock line within each column operation of the 3-state buffer controls allows them to
of logic blocks. Interconnections of these long lines are implement wide multiplexing functions. Any 3-state buffer
shown in Figure 14. Isolation buffers are provided at each input can be selected as drive for the horizontal long-line
input to a long line and are enabled automatically by the bus by applying a Low logic level on its 3-state control line.
development system when a connection is made. See Figure 1Sa. The user is required to avoid contention
GLOBAL
BUFFER~"
. .' .
:" .••
.:.:
. ...
.. :.::
• • •• '
t:tJ
• •
0 ':'..tJ:. :b:.::0' ,:",:b.. :b"'.
. .. 0...
.. •
:.:0 b tJ:.:0.
. . . 1...
II •
.C"i."
. . .1 : .
II •
::g.;.:;: ':. ~:. :::., : . ::.:: . :':' : . :;::~: . :':' : . :;.:~.' .:.: ;.:~.
't"..... : . r.:·· . 't.:"
. . . .::.~ : .;: .'::0 .':'
Il
• • II •••
ON-CHIP
3-STATE
.....
BUFFERS
....
I" "
PULL-UP :
RESISTORS<
FOR ON-CHIP
OPEN DRAIN
~~~------~~-'~~--------~~~-------r~~--~----~~
SIGNALS
..
::0 .
e; .'. . .
2 HORIZONTAL LONG LINES
:
..~
6 ...
.':': '. .. EJA :-:':
. I.
.... '::' ....:. . ...'E1c .'::
•
.....
I":'
.j8q .... :
W.·.·
p r·.;
.! :
Figure 13. Horizontal and Vertical Long Lines. These long lines provide high fan-out, low-skew signal distribution in
each row and column. The global buffer in the upper left die corner drives a common line throughout the LeA.
2-11
XC3000 Logic Cell Array Family
which can result from multiple drivers with opposing logic 15b. Pull-up resistors are available at each end of the long
levels. Control of the 3-state input by the same signal that line to provide a High output when all connected buffers
drives the buffer input, creates an open-drain wired-AND are non-conducting. This forms fast, wide gating func-
function. A logic High on both buffer inputs creates a high tions. When data drives the inputs, and separate signals
impedance, which represents no contention. A logic Low drive the 3-state control lines, these buffers form multi-
enables the buffer to drive the long line Low. See Figure plexers (3-state busses). In this case, care must be used
o ... EO DO 00 ~fo. DO
r - l .: .:.. : :':11:- .: .: .. : :':;-'1 .: : ;
DC
.:.:.. : :':11:- .: .: .. : :.:
(2PERDIEEDGE)
'-:1' .:' .:.:
.' ...:'- :.::
" LJ... ····· .. ~LJ._:.......;·LJ·.. · .... .......... ·lJ···· ... "
eJ'.,
Figure 14. Programmable Interconnection of Long Lines. This is provided at the edges of the routing area. Three-state
buffers allow the use of horizontal long lines to form on-chip wired-AND and multiplexed buses. The left two vertical long
lines per column (except 3020) and the outer perimeter long lines may be programmed as connectible half-length.
--../\I'wr-D-A-lP---,--D-e-lP---,--D-c-lP---,----(lD-~W-~-:--....---.,.oNv-
110504
Figure 15a. 3·State Buffers Implement a Wlred·AND Function. When all the buffer
3-state lines are High, (high impedance), the pull-up resistor(s) provide the
I if"!: if"I
High output. The buffer inputs are driven by the control signals or a Low. T Of
Z = DA'A +De'8 +Dc·O+ ... +DN'N
"05 04A
2-12
to prevent contention through multiple active buffers of circuit becomes active before configuration is complete in
conflicting levels on a common line. Figure 16 shows order to allow the oscillator to stabilize. Actual internal
3-state buffers, long lines and pull-up resistors. connection is delayed until completion of configuration. In
Figure 17 the feedback resistor R1, between the output
CRYSTAL OSCILLATOR and input, biases the amplifier at threshold. The value
should be as large as practical to minimize loading of the
Figure 16 also shows the location of an internal high speed crystal. The inversion of the amplifier, together with the
inverting amplifierwhich may be used to implement an on- R-C networks and an AT-cut series resonant crystal,
chip crystal oscillator. It is associated with the auxiliary produce the 360-degree phase shift of the Pierce oscil-
buffer in the lower right corner of the die. When the lator. A series resistor R2 may be included to add to the
oscillator is configured by MAKEBITS and connected as a amplifier output impedance when needed for phase-shift
signal source, two special user lOBs are also configured to control, crystal resistance matching, orto limitthe amplifier
connect the oscillator amplifier with external crystal oscil- input swing to control clipping at large amplitudes. Excess
latorcomponents as shown in Figure 17. A divide by two feedback voltage may be corrected by the ratio of C2/C1.
option is available to assure symmetry. The oscillator The amplifier is designed to be used from 1 MHz to one-
BIDIRECTIONAL
-- II
INTERCONNECT 3 VERTICAL LONG
BUFFERS GLOBAL NET" / LINES PER COLUMN
.,....." 110 CLOCKS
111 JI '"" I II I IGH II I
:~O
.I
--J t\1 HORIZONTAL LONG LINE
JO ~u.
r:-
i!10 ,/
OSCILLATOR
AMPLIFIER OUTPUT
- - ~
A DIRECTINPUT OF P47
-:-
I
I
I
ffi
V TO AUXILIARY BUFFE R
CRYSTAL OSCILLATOR
+
I W'- r 1'llH-1 ~ VI BUFFER
--
I I
J ~ -
~3-STATE INPUT
'-n- '-n- ~~.~
-
3-STATE CONTROL
P
- A L
~'
~
~
3-STATE BUFFER
.0 '. I- .q.ak .
~-.....;
r - ALTERNATE BUFFER
000 []
r ~ I' 00 'I ti
11 00
~eJ EJeJl E:J
\ OSCILLATOR
AMPLIFIE R INPUT
X1245
2-13
XC3000 Logic Cell Array Family
half the specified CLB toggle frequency. Use at frequen- ture and power supply. As shown in Table 1, five configu-
cies below 1 MHz may require individual characterization ration mode choices are available as determined by the
with respect to a series resistance. Crystal oscillators input levels of three mode pins; MO, M1 and M2.
above 20 MHz generally require a crystal which operates
in a third overtone mode, where the fundamental fre- In Master configuration modes, the LCA device becomes
quency must be suppressed by the R-C networks. When the source of the Configuration Clock (CCLK). The begin-
the oscillator inverter is not used, these lOBs and their ning of configuration of devices using Peripheral or Slave
package pins are available for general user I/O. modes must be delayed long enough for their initialization
to be completed. An LCA with mode lines selecting a
Master configuration mode extends its initialization state
PROGRAMMING using four times the delay (43 to 130 ms) to assure that all
daisy-chained slave devices, which it may be driving, will
Initialization Phase be ready even if the master is very fast, and the slave(s)
Table 1
An internal power-on-reset circuit is triggered when power
is applied. When Vee reaches the voltage at which MO M1 M2 Clock Mode Data
portions of the LCA begin to operate (nominally 2.5 to 3 V),
the programmable I/O output buffers are disabled and a 0 0 0 activeMaster Bit Serial
high-impedance pull-up resistor is provided for the user 0 0 activeMaster Byte Wide Addr. = 0000 up
110 pins. A time-out delay is initiated to allow the power 0 1 0 reserved
supply voltage to stabilize. During this time the power- 0 1 active Master Byte Wide Addr. = FFFF down
down mode is inhibited. The Initialization state time-out 1 0 0 reserved
(about 11 to 33 ms) is determined by a 14-bit counter 0 1 passive Peripheral Byte Wide
driven by a self-generated internal timer. This nominal 0 reserved
1-MHztimeris subject to variations with process, tempera- passive Slave Bit Serial
INTERNAL'! EXTERNAL
ALTERNATE
CLOCK BUFFER
XTAL1
I
D
D
SUGGESTED COMPONENT VALUES R2
R1 0.5-1 Mn
R2 0-1 kn
(may be required for low frequency, phase
shift andlor compensation level for crystal Q)
C1,C210-40pF
I C1
44 PIN 68 PIN 84 PIN 100 PIN 132 PIN 160 PIN 164 PIN 175 PIN
PLCC PLCC PLCC PGA CQFP PQFP PGA PQFP CQFP PGA
IXTAL 1 (OUT) 30 47 57 J11 67 82 P13 82 105 T14
L XTAL 2 (IN) 26 43 53 I L11 61 I 76 M13 76 99 P15
1105t4C
Figure 17. Crystal Oscillator Inverter. When activated in the MAKEBITS program and by selecting an output network
for its buffer, the crystal oscillator inverter uses two unconfigured package pins and external components to
implement an oscillator. An optional divide-by-two mode is available to assure symmetry.
2-14
very slow. Figure 18 shows the state sequences. At the configuration program(s). The data framing is shown in
end of Initialization the LCA enters the Clear state where Figure 19. All LCAs connected in series read and shift
it clears the configuration memory. The active Low, open- preamble and length count in on positive and out on
drain initialization signal INIT indicates when the Initiali- negative configuration clock edges. An LCA which has
zation and Clear states are complete. The LCA tests for received the preamble and length count then presents a
the absence of an external active Low RESET before it High Data Out until it has intercepted the appropriate
makes a final sample of the mode lines and enters the number of data frames. When the configuration program
Configuration state. An external wired-AND of one or memory of an LCA is full and the length count does not
more INIT pins can be used to control configuration by the compare, the LCA shifts any additional data through, as it
assertion of the active low RESET of a master mode de- did for preamble and length count.
vice or to signal a processor that the LCAs are not yet
initialized. When the LCA configuration memory is full and the length
count compares, the LCA will execute a synchronous
If a configuration has begun, a re-assertion of RESET for start-up sequence and become operational. See
a minimum of three internal timer cycles will be recognized Figure 20. Three CCLK cycles after the completion of
and the LCA will initiate an abort, returning to the Clear loading configuration data the user I/O pins are enabled as
state to clear the partially loaded configuration memory
words. The LCA will then re-sample RESET and the mode
lines before re-entering the Configuration state. A re-
configured. As selected in MAKEBITS, the internal user-
logic reset is released either one clock cycle before or after
the I/O pins become active. A similar timing selection is
II
program is initiated when a configured LCA senses a High programmable for the DONE/PROG output Signal.
to Low transition on the DONE/PROG package pin. The DONEIPROG may also be programmed to be an open
LCA returns to the Clear state where the configuration drain or include a pull-up resistor to accommodate wired
memory is cleared and mode lines re-sampled, as for an ANDing. The High During Configuration (HDC) and Low
aborted configuration. The complete configuration pro- During Configuration (LDC) are two user I/O pins which
gram is cleared and loaded during each configuration are driven active when an LCA is in its Initialization, Clear
program cycle. or Configure states. They and DONE/PROG provide
signals for control of external logic signals such as reset,
Length count control allows a system of multiple Logic Cell bus enable or PROM enable during configuration. For
Arrays, of assorted sizes, to begin operation in a synchro- parallel Masterconfiguration modes these signals provide
nized fashion. The configuration program generated by PROM enable control and allow the data pins to be shared
the MakePROM program of the XACT development sys- with user logic signals.
tem begins with a preamble of 111111110010 followed by
a 24-bit 'length count' representing the total number of User I/O inputs can be programmed to be either TIL or
configuration clocks needed to complete loading of the CMOS compatible thresholds. At power-up, all inputs
POWER-ON DELAY IS
ACTIVE
/'P""'O"'WE=R."""D""'OW"'N"I
CLEAR IS
-200 CYCLES FOR THE XC3020-130 TO 400 I's
-250 CYCLES FOR THE XC3030-165 TO 500 I's
-290 CYCLES FOR THE XC3042-195TO 580 I'S 110515A
-330 CYCLES FOR THE XC3064-220 TO 660 I's
-375 CYCLES FOR THE XC3090-250 TO 750 I'S
Figure 18. A State Diagram of the Configuration Process for Power-up and Reprogram.
2-15
XC3000 Logic Cell Array Family
have TIL thresholds and can change to CMOS thresholds Configuration Data
at the completion of configuration if the user has selected
CMOS thresholds. The threshold of PWRDWN and the Configuration data to define the function and interconnec-
direct clock inputs are fixed at a CMOS level. tion within a Logic Cell Array are loaded from an external
storage at power-up and on a re-program signal. Several
If the crystal oscillator is used, it will begin operation before methods of automatic and controlled loading of the re-
configuration is complete to allow time for stabilization quired data are available. Logic levels applied to mode
before it is connected to the internal circuitry.
11111111
0010
< 24·BIT LENGTH COUNT>
1111
-
-
-
-
DUMMY BITS·
PREAMBLE CODE
CONFIGURATION PROGRAM LENGTH
DUMMY BITS (4 BITS MINIMUM) ] HEADER
1
A START BIT (0) REPEATED FOR EACH LOGIC
A 71-BIT DATA FIELD CELL ARRAY IN A DAISY CHAIN
o < DATA FRAME#196> 111 THREE STOP BITS
o < DATA FRAME#197 > 111
-THE LCA DEVICES REQUIRE FOUR DUMMY BITS MIN; XACT 2.10 GENERATES EIGHT DUMMY BITS 11050SA
TBUFsIHorizontal LL 9 11 13 15 17
Figure 19_ Internal Configuration Data Structure for an LCA. This shows the preamble, length count
and data frames which are generated by the XACT Development System.
The Length Count produced by the MAKEBIT program = [(40-bit preamble + sum of program data + 1 per daisy chain device)
rounded up to multiple of 8]- (2 :5: K :5: 4) where K is a function of DONE and RESET timing selected. An additional 8 is added
if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached.
2-16
E:XIUNX
selection pins at the start of configuration time determine supply currents. If unused blocks are not sufficient to
the method to be used. See Table 1. The data may be complete the 'tie,' the FLAGNET command of EDITLCA
either bit-serial or byte-parallel, depending on the configu- can be used to indicate nets which must not be used to
ration mode. Various Xilinx Field Programmable Gate drive the remaining unused routing, as that might affect
Arrays have different sizes and numbers of data frames. timing of user nets. NORESTORE will retain the results of
To maintain compatibility between various device types, TIE for timing analysis with QUERYNET before RE-
the Xilinx 2000 and 3000 product families use compatible STORE returns the design to the untied condition. TI E can
configuration formats. For the XC3020, configuration be omitted for quick breadboard iterations where a few
requires 14779 bits for each device, arranged in 197 data additional milliamps of Icc are acceptable.
frames. An additional 40 bits are used in the header. See
Figure 20. The specific data format for each device is The configuration bitstream begins with High preamble
produced by the MAKEBITS command of the develop- bits, a 4-bit preamble code and a 24-bit length count.
ment system and one or more of these files can then be When configuration is initiated, a counter in the LCA is set
combined and appended to a length count preamble and to zero and begins to count the total number of configu-
be transformed into a PROM format file by the 'MAKE ration clock cycles applied to the device. As each con-
PROM' command of the XACT development system. A figuration data frame is supplied to the LCA, it is internally
compatibility exception precludes the use of a 2000-series
device as the master for 3000-series devices if their DONE
or RESET are programmed to occur after their outputs
assembled into a data. word. As each data word is
completely assembled, it is loaded in parallel into one word
of the internal configuration memory array. The configura-
II
become active. The "tie"option olthe MAKEBITS program tion loading process is complete when the current length
defines output levels of unused blocks of a design and count equals the loaded length count and the required
connects these to unused routing resources. This pre- configuration program data frames have been written.
vents indeterminate levels that might produce parasitic Internal user flip-flops are held reset during configuration.
POSTAMBLE
START
LENG THCOUNT'
START
WEAK PULL·UP
nJlu..-1_---'
DOUT LEAD DEVICE
HIGH 110 ACTIVE
INTERNAL RESET \
~
* The configuration data consists of a composite Timing of the assertion of DONE and
40-bit preamble/length count, followed by one or termination of the INTERNAL RESET
more concatenated LeA programs, separated by may each be programmed to occur
4-bit postambles. An additional final postamble bit one cycle before or after the I/O outputs
is added for each slave device and the result rounded become active.
up to a byte boundary. The length count is two less
than the number of resulting bits. 1105 068
2-17
XC3000 Logic Cell Array Family
Two user-programmable pins are defined in the unconfig- portions of the system. The state diagram of Figure 18
ured Logic Ceil array. High During Configuration (HDC) illustrates the configuration process.
and Low During Configuration (LDC) as weil as
DONEIPROG may be used as external control signals Master Mode
during configuration. In Master mode configurations it is
convenient to use LDC as an active-Low EPROM Chip In Master mode, the LCA device automatically loads
Enable. After the last configuration data bit is loaded and configuration data from an external memory device. There
the length count compares, the user 1/0 pins become are three Master modes that use the internal timing source
active. Options in the MAKEBITS program ailow timing to supply the configuration clock (CCLK) to time the
choices of one clock earlier or laterfor the timing of the end incoming data. Serial Master mode uses serial configura-
of the internal logic reset and the assertion of the DONE tion data supplied to Data-in (DIN) from a synchronous
signal. The open-drain DONEIPROG output can be AND- serial source such as the Xilinx Serial Configuration
tied with multiple LCAs and used as an active-High PROM shown in Figure 21. Parallel Master Low and
READY, an active-Low PROM enable or a RESETto other Master High modes automatically use parallel data sup-
• IF READBACK IS
ACTIVATED, A
5-1<0 RESISTOR IS
. +r
REQUIRED IN
SERIES WITH M1
~ I I
MO M1 PWRDWN
DURING CONFIGURATION OPTIONAL
THE 5 kn M2 PULL-DOWN l-+ DAISY·CHAINED
RESISTOR OVERCOMES THE - DOUT LCA.WITH
INTERNAL PULL-UP.
BUT IT ALLOWS M2TO
'--- - M2 ,. g~~~~~~ATIONS
BE USER 1/0.
- HOC
--< LDC
GENERAL-
PURPOSE --< INIT
USER 110
-
),-'
PINS
110 PINS
- LCA
OPTIONAL
f--- ~~~J~~ICAL
- CONFIGURATIONS
+5V
RESET - - c RESET I IV ~
Vee pp
DIN DATA SERIAL
MEMORY
'-i
CCLK CLK '---j CASCADED
SERIAL
LDC CE CEO <1 MEMORY
DONE- I - DIP
XC1736A1XC1765
rOE L
.
" ,HIGH RESETS THE XC1736A1XC1765 ADDRESS POINTER)
"~~
(O~~
(OUTPUT) 1105166
Figure 21. Master Serial Mode. The one-time-programmable XC1736AIXC1765 Serial Configuration PROM supports
automatic loading of configuration programs up to 36K bits. Multiple devices can be cascaded to support additional
LCAs. An early DONE inhibits the XC1736A data output a CCLK cycle before the LCA II0s become active.
2-18
plied to the 00-07 pins in response to the 16-bit address internally serialized by the Configuration Clock. As each
generated by the LCA. Figure 22 shows an example ofthe data byte is read, the least significant bit of the next byte,
parallel Master mode connections required. The LCA HEX DO, becomes the next bit in the internal serial configuration
starting address is 0000 and increments for Master Low word. One Maste-mode LCA can be used to interface the
mode and it is FFFF and decrements for Master High configuration program-store and pass additional concate-
mode. These two modes provide address compatibility nated configuration data to additional LCAs in a serial
with microprocessors which begin execution from oppo- daisy-chain fashion. CCLK is provided for the slaved
site ends of memory. For Master High or Low, data bytes devices and their serialized data is supplied from DOUT to
are read in parallel by each Read Clock (RCLK) and DIN - DOUT to DIN etc.
OPTIONAL
5kn DOUT DAISY·CHAINED
LCAs WITH DIFFERENT
GENERAL·
M2
HOC
CCLK
A'5
CONFIGURAliONS
III
PURPOSE RCLK
USER 110 A14
PINS INIT A13 EPROM
A12 OR~~MER)
} OTHER
110 PINS A1'
A10 A,O
RESET RESET A9 A9
07 A8 A8
06
LeA A7 A7 07
05 A6 A6 os
04 A5 A5 05
03 A4 A4 04
02 A3 A3 03
0' A2 A2 02
DONE DiP CE
8
DATA BUS
(OUT~ca-~
'~CCLK
-{ \
I1+________~.~~~==========~.
8 CCLKs
1 \'-----
CCLK~
(OUTPUT)
Figure 22. Master Parallel Mode. Configuration data are loaded automatically from an external byte wide PROM.
An early DONE inhibits the PROM outputs a CCLK before the LCA 1/0 become active.
2-19
XC3000 Logic Cell Array Family
+5V
I~ 1
CONTROL ADDRESS DATA
SIG NALS BUS BUS
• IF READBACK IS
ACTIVATED, A
8 5 5·kn RESISTOR IS
MO M1PWR REQUIRED IN SERIES
-1 DWN WITH Ml
DO-7
DO-7 CCLK OPTIONAL
DAISY-CHAINED
LCAs WITH DIFFERENT
~
CONFIGURATIONS
DOUT - - f-
r"--- ADDRESS
DECODE
>----C CSO M2 - -
~
LOGIC HDC -
+5V LCA LDC :>-- GENERA L-
PURPOS E
CSl USER I/O
PINS
CS2 {
-
OTHER
WS ~PINS
RDY/BUSY -
INIT
REPROGRAM
~ D/P
V RESET
mz
WS
CSO
CSI
\\\\\\\\ \\\\
CS2 1IIIIlU \SSS lill
00-D7
X X
CCLK (INTERNAL) \../
1105180
-----------------------~
DOUT ~
RDY/BUSY
Figure 23. Peripheral Mode. Configuration data are loaded using a byte·wide data bus from a microprocessor.
2-20
amble, a length count for the total bitstream, multiple cycle. The internal timing generator continues to operate
concatenated data programs and a postamble plus an for general timing and synchronization of inputs in all
additional fill bit per device in the serial chain. After loading modes.
and passing-on the preamble and length count to a pos-
sible daisy-chain, a lead device will load its configuration SPECIAL CONFIGURATION FUNCTIONS
data frames while providing a High DOUT to possible
down-stream devices as shown in Figure 25. Loading The configuration data include control overseveral special
continues while the lead device has received its configura- functions in addition to the normal user logic functions and
tion program and the current length count has not reached interconnect:
the full value. The additional data are passed through the
lead device and appear on the Data Out (DOUT) pin in • Input thresholds
serial form. The lead device also generates the Con- • Readback disable
figuration Clock (CCLK) to synchronize the serial output • DONE pull-up resistor
data and data in of down-stream LCAs. Data are read in • DONE timing
on DIN of slave devices by the positive edge of CCLK and • RESET timing
shifted out the DOUT on the negative edge of CCLK. A • Oscillator frequency divided by two
parallel Master mode device uses its internal timing gen-
erator to produce an internal CCLK of 8 times its EPROM
address rate, while a Peripheral mode device produces a
Each of these functions is controlled by configuration data
bits which are selected as part of the normal XACT
II
burst of 8 CCLKs for each chip select and write-strobe development system bitstream generation process.
+5V
* IF READBACK IS
ACTIVATED, A
5·1<0 RESISTOR IS
MO M1 PWRDWN REQUIRED IN
MICRO SERIES WITH M1
COMPUTER
OPTIONAL
STRB 1----4-~ CCLK DAISY-CHAINED
LCAs WITH DIFFERENT
DO I----~DIN - CONFIGURATIONS
01
VO 02
PORT GENERAL-
+5V PURPOSE
03 LCA USER 1/0
PINS
04
05 OTHER {
1/0 PINS
06 1--+--+-' DIP
07
RESET
==xI;
~
DIN BITN BITN +1
CCLK
~ ~ I
DOUT
(OUTPUT)
BITN-1
m BITN
1105198
Figure 24_ Slave Mode_ Bit-serial configuration data are read at rising edge of the CCLK.
Data on DOUT are provided on the falling edge of CCLK.
2-21
XC3000 Logic Cell Array Family
Prior to the completion of configuration all LCA input The contents of a Logic Cell Array may be read back if it
thresholds are TTL compatible. Upon completion of con- has been programmed with a bitstream in which the
figuration the input thresholds become either TTL or Readback option has been enabled. Readback may be
CMOS compatible as programmed. The use of the TTL used for verification of configuration and as a method of
threshold option requires some additional supply current determining the state of internal logic nodes during debug-
forthreshold shifting. The exception is the threshold of the ging with the XACTOR In-Circuit debugger. There are
PWRDWN input and direct clocks which always have a three options in generating the configuration bitstream:
CMOS input. Prior to the completion of configuration the
user 110 pins each have a high impedance pull-up. The • "Never" will inhibit the Readback capability.
configuration program can be used to enable the 108 pull- • "One-time," will inhibit Readback after one Readback
up resistors in the Operational mode to act either as an has been executed to verify the configuration.
input load or to avoid a floating input on an otherwise • "On-command" will allow unrestricted use of Read-
unused pin. back.
+S V +S v
.{ M2
HOC
CCLK
DOOT
MO M1 PWRDWN
CCLK
DIN
LCA
DOUT
SLAVE #1
M2
Skll
MO M1 PWROWN
CCLK
DIN
LeA
DOOT
SLAVE lin
M2
Skll
Figure 25. Master Mode Configuration with Daisy Chained Slave Mode Devices.
All are configured from the common EPROM source. The Slave mode device 1JiJlT signals
delay the Master device configuration until they are initialized. A well defined termination
of SYSTEM RESET is needed when controlling multiple LCAs.
Any XC3000 slave driven by an XC2000 master mode device must use "early DONE and early internal RESET".
(The XC2000 master will not supply the extra clock required by a "late" programmed XC3000.)
2-22
Readback is accomplished without the use of any of the DONEIPROG Low. Once it recognizes a stable request,
user I/O pins; only MO, M1 and CCLK are used. The the Logic Cell Array will hold a Low until the new configu-
initiation of Readback is produced by a Low to High ration has been completed. Even if the re-program re-
transition of the MO/RTRIG (Read Trigger) pin. Once the quest is externally held Low beyond the configuration
Readback command has been given, the input CCLK is period, the Logic Cell Array will begin operation upon
driven by external logic to read back each data bit in a completion of configuration.
format similar to loading. After two dummy bits, the first
data frame is shifted out, in inverted sense, on the DONE Pull-up
M 1IRDATA (Read Data) pin. All data frames must be read
back to complete the process and return the Mode Select DONEIPROG is an open-drain 1/0 pin that indicates the
and CCLK pins to their normal functions. LCA is in the operational state. An optional internal pull-up
resistor can be enabled by the user of the XACT develop-
The Readback data includes the current state of each ment system when MAKE BITS is executed. The DONEI
internal logic block storage element, and the state of the PROG pins of multiple LCAs in a daisy-chain may be
[.i and .n] connection pins on each lOB. These data are connected together to indicate all are DONE or to direct
imbedded into unused configuration bit positions during them all to re-program.
Readback. This state information is used by the XACT
development system In-Circuit Verifier to provide visibility DONE Timing
into the internal operation of the logic while the system is
operating. To readback a uniform time-sample of all The timing of the DON E status signal can be controlled by
storage elements, it may be necessary to inhibit the a selection in the MAKEBITS program to occur a CCLK
system clock. cycle before, or after, the timing of outputs being activated.
See Figure 20. This facilitates control of external functions
Re-program such as a PROM enable orholdinga system in await state.
The LCA configuration memory can be re-written while the RESET Timing
device is operating in the user's system. To initiate a re-
programming cycle, the dual-function pin DONE/PROG As with DONE timing, the timing of the release of the
must be given a High-to-Low transition. To reduce sensi- internal RESET can be controlled by a selection in the
tivity to noise, the input signal is filtered for two cycles of the MAKEBITS program to occur a CCLK cycle before, or
LCA internal timing generator. When re-program begins, after, the timing of outputs being enabled. See Figure 20.
the user-programmable 1/0 output buffers are disabled This reset maintains all user programmable flip-flops and
and high-impedance pull-ups are provided forthe package latches in a zero state during configuration.
pins. The device returns to the Clear state and clears the
configuration memory before it indicates 'initialized'. Crystal OSCillator Division
Since this Clear operation uses chip-individual internal
timing, the master might complete the clear operation and A selection in the MAKEBITS program allows the user to
then start configuration before the slave has completed the incorporate a dedicated divide-by-two flip-flop in the crys-
Clearoperation. To avoidthis problem, the slave INITpins tal oscillator function. This provides higher assurance of a
are AND-wired and used to force a RESET on the master symmetrical timing signal. Although the frequency stabil-
(see Figure 25). Reprogram control is often imple- ity of crystal oscillators is high, the symmetry of the
mented using an external open-collector driver which pulls waveform can be affected by bias or feedback drive.
2-23
XC3000 Logic Cell Array Family
PERFORMANCE the flip-flop element. The delay from the clock source to
the output of the logic block is critical in the timing of signals
Device Performance produced by storage elements. Loading of a logic-block
output is limited only by the resulting propagation delay of
The LCA high performance is due in part to the manufac- the larger interconnect network. Speed performance of
turing process, which is similar to that used for high-speed the logic block is a function of supply voltage and
CMOS static memories. Performance can be measured in temperature. See Figure 29.
terms of minimum propagation times for logic elements.
Traditionally, the toggle frequency of a flip-flop has been Interconnect Performance
used to describe the overall performance of a gate array.
The configuration for determining the toggle performance Interconnect performance depends on the routing re-
of the Logic Cell Array is shown in Figure 26. The flip-flop source used to implement the signal path. As discussed
a
output is fed back through the combinatorial logic as Q earlier, direct interconnect from block to block provides a
to form the toggle flip-flop. fast path for a signal. The single metal segment used for
long lines exhibits low resistance from end to end, but
Actual LCA performance is determined by the timing of relatively high capacitance. Signals driven through a
critical paths, including both the fixed timing for the logic programmable switch will have the additional impedance
and storage elements in that path, and the timing asso- of the switch added to their normal drive impedance.
ciated with the routing of the network. Internal worst-case
timing values are included in the performance data to allow General-purpose interconnect performance depends on
the user to make the best use of the capabilities of the the number of switches and segments used, the presence
device. The XACT development system timing calculator of the bidirectional repowering buffers and the overall
or XACT generated simulation models should be used to loading on the signal path at a" points along the path. In
calculate worst case paths by using actual impedance and calculating the worst-case timing for a general intercon-
loading information. Figure 27 shows a variety of elements nect path the timing-calculator portion of the XACT devel-
which are involved in determining system performance. opment system accounts for a" of these elements. As an
Actual measurement of internal timing is not practical and approximation, interconnect timing is proportional to the
often only the sumof componenttiming is relevant as in the summation of totals of local metal segments beyond each
case of input to output. The relationship between input and programmable switch. In effect, the time is a sum of R-C
output timing is arbitrary and only the total determines time each approximated by an R times the total C it drives.
performance. Timing components of internal functions The R of the switch and the C of the interconnect is a
may be determined by measurement of differences at the function of the particular device performance grade. For a
pins of the package. A synchronous logic function which string of three local interconnects, the approximate time at
involves a clock to block-output, and a block-input to clock the first segment, after the first switch resistance would be
set-up is capable of higher speed operation than a logic three units; an additional two units after the next switch
configuration of two synchronous blocks with an extra plus an additional unit after the last switch in the chain. The
combinatorial block level between them. System clock i!lterconnect R-C chain terminates at each re-powering
rates to 60% of the toggle frequency are practical for logic buffer. The capacitance of the actual block inputs is not
in which an extra combinatorial level is located between significant; the capacitance is in the interconnect metal
synchronized blocks. This allows implementation of and switches. See Figure 28.
functions of up to 25 variables. The use of the wired-AND
is also available for wide, high-speed functions.
2-24
l::X1l1NX
CLOCK TO
OUTPUT COMBINATORiAl SETUP
I----- TCKO -I- liLO -I· liCK ~ I+-- ----I TOp
'«~'·'~~"·~'«·"«"'·'cut~~"!.~.: r.' ·"·'·~'«·'«'«CLB·"·~«I i'·""·'·~~"«=««·"·"'««««-·"~~w""«'l ["'«·'·'·'"«·'108"·'=«««_·
'. r-;'~+~~ ~~!~r'-4
~,.; l LOGIC ~!,. ~ ~
~ ~ ffi ~
~ ~ ~ X ~"~"""~~~"~'~'~~""""~"""""""""""""'NN''''''
~,.", "~'w.,...,.~~~~.,..w,,,w..J
,.. ,,~, ~J L.~w."w,,,,,.,,,"w,,,.w....."""w...,.,(~!,.,,,,w.w,,J ~
l.w",.,..,..".'w.'w.. ..
CLOCK--~----------+---------------------~~
,
~
,~
I- TOKPO -I t105 Z1A
SWITCH
._ ••••••. /MATRIX ................... .
CLB : R2 I I R3 :
,, ,,
L ••• ___ ..
TIMING: INCREMENTAL
IF Rl • R2 • R3 • RAND Cl. C2 • C3 • C
THEN CUMULATIVE TIMING
Tl =3RC T2=3RC+2RC T3. 3RC + 2RC + lRC 6RC+ BUFFER
.3RC .5RC .6RC
1105 238
Figure 28. Interconnection Timing Example. Use of the XACT timing calculator
or XACT-generated simulation model provides actual worst-case performance information.
2·25
XC3000 Logic Cell Array Family
1.00
0.80
TYPICAL COMMERCIAL
.
(+ 5.0 v, 25'C)
•
, TYPICAL MiliTARY
0.40
,
: MIN COMMERCIAL ~.~5 ~ MIN}AJIJV!\:! J.4~S_Vl_ - - ~
: IN M A__ ~ ____ - - - - - - - - - - ,
, ____ - - - - - - MIN MIJ:!V'£I:! !S}_VJ - - --'
0.20
~.-- ---------------~~~~~----------- ---------------
~--------------------
TEMPERATURE ('C)
X1045
Figure 29_ Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations.
GND
GROUND AND
VeeRING FOR
+ --+-
,, -+-- + -- + -- + --+ -- + 1/0 DRIVERS
+--+--+--+--+--
I I I I I
I I " I I LOGIC POWER GRID
+, --+, --+- -+ -- +-- + -- +-- +
, ,
+- -+ --+ --+--+- -+ -- +- -+
GND
110524
2-26
POWER In an LCA, the fraction of nodes changing on a given clock
is typically low (10-20%). For example, in a large binary
Power Distribution counter, the average clock cycle produces changes equal
to one CLB output at the clock frequency. Typical global
Power forthe LCA is distributed through a grid to achieve clock-buffer power is between 1.7 mW/MHz for the
high noise immunity and isolation between logic and I/O. XC3020 and 3.6 mW/MHz for the XC3090. The internal
Inside the LCA, a dedicated Vcc and ground ring sur- capacitive load is more a function of interconnect than fan-
rounding the logic array provides power to the I/O drivers. out. With a typical load of three general interconnect
See Figure 30. An independent matrix of V cc and ground segments, each CLB output requires about 0.4 mW per
lines supplies the interior logic of the device. This power MHz of its output frequency.
distribution grid provides a stable supply and ground for all
internal logic, providing the external package power pins
are all connected and appropriately decoupled. Typically Total Power = Vee' leeo + external (de + capacitive)
a 0.1-IlF capacitor connected near the VCC and ground + internal (elB + lOB + long line + pull-up)
pins will provide adequate decoupling.
Because the control storage of the Logic Cell Array is
Output buffers capable of driving the specified 4-mA loads CMOS static memory, its cells require a very low standby
under worst-case conditions may be capable of driving 25 current for data retention. In some systems, this low data •
to 30 times that current in a best case. Noise can be retention current characteristic can be used as a method
reduced by minimizing external load capacitance and of preserving configurations in the event of a primary
reducing simultaneous output transitions in the same power loss. The Logic Cell Array has built in power-down
direction. It may also be beneficial to locate heavily loaded logic which, when activated, will disable normal operation
output buffers near the ground pads. The I/O Block output of the device and retain only the configuration data. All
buffers have a slew-limited mode which should be used internal operation is suspended and output buffers are
where output rise and fall times are not speed critical. placed in their high-impedance state with no pull-ups.
Slew-limited outputs maintain their dc drive capability, Power-down data retention is possible with a simple bat-
but generate less external reflections and internal noise. A tery-backup circuit because the power requirement is
maximum total external capacitive load for simultaneous extremely low. For retention at 2.4 V, the required current
fast mode switching in the same direction is 500 pF per can be as low as 10 j.LA at room temperature.
power/ground pin pair. Four slew-rate limited outputs this
total is four times larger. To force the Logic Cell Array into the Power-Down state,
the user must pull the PWRDWN pin Low and continue
Power Consumption to supply a retention voltage to the VCC pins. When
normal power is restored, VCC is elevated to its normal
The Logic Cell Array exhibits the low power consumption operating voltage and PWRDWN is returned to a High.
characteristic of CMOS ICs. For any deSign, Figure 31 The Logic Cell Array resumes operation with the same
can be used to calculate the total power requirement internal sequence that occurs at the conclusion of
based on the sum of the capacitive and dc loads both configuration. Internal-I/O and logic-block storage
external and internal. The configuration option of TIL chip elements will be reset, the outputs will become enabled
inputthreshold requires powerforthe threshold reference. and the DONEIPROG pin will be released. No con-
The power required by the static memory cells that hold the figuration programming is involved.
configuration data is very low and may be maintained in a
power-down mode. When the power supply is removed from a CMOS device,
it is possible to supply some power from an input signal.
Typically, most of power dissipation is produced by exter- The conventional electro-static input protection is imple-
nal capacitive loads on the output buffers. This load and mented with diodes to the supply and ground. A positive
frequency dependent power is 25IlW/pF/MHz per output. voltage applied to an input (or output) will cause the
Another component of I/O power is the dc loading on each positive protection diode to conduct and drive the Vcc
output pin by devices driven by the Logic Cell Array. connection. This condition can produce invalid power
conditions and should be avoided. A large series resistor
Internal power dissipation is a function of the number and might be used to limit the current or a bipolar buffer may be
size of the nodes, and the frequency at which they change. used to isolate the input signal.
2-27
XC3000 Logic Cell Array Family
500 100
L 90
IL 80
70
L 60
L L 50
, 40
150 30
;'
•
/ /
100 20
• ;'
If' •if V
50
L
/
1
/
L
V 10
9
40 t.... IL L 8
7
30 L L 6
(mW) / L L 5 (mA)
20 , L 4
/
.L / 3
;'
•
50 CLB OUTPUTS 10
(18 mW/MHz)
/
,if
,
/
V
L V
.L
V 2
5
;'
/
IL
L
V
V
L
/ .9
4 .8
20 CLB OUTPUTS
(7.2 mW/MHz) / L .7
3 / / .6
L L .5
2 / V' .4
/ lL .3
/
(1.8mW/MHz)
o. 5 .1
0.5 1/ 2 3 4 5 10 20 30 40 50
FREQUENCY MHz
ONE CLB OR lOB OUTPUT /
DRIVING THREE LOCAL
INTERCONNECTS
(0.36 mW/MHz)
110509
Figure 31. LCA Power Consumption by Element. Total chip power is the sum of Vcc·lcco plus effective internal and external
values of frequency dependent capacitive charging currents and duty factor dependent resistive loads.
2-28
E:XlUNX
PWRDWN MO
A Low on this CMOS-compatible input stops all internal As Mode 0, this input and M1, M2 are sampled before the
activity, but retains configuration. All flip-flops and latches start of configuration to establish the configuration mode to
are reset, all outputs are 3-stated, and all inputs are be used.
interpreted as High, independent of their actual level.
RTRIG
While PWRDWN is Low, Vcc may be reduced to any value
>2.3 V. When PWDWN returns High, the LCA becomes
operational with DONE Low for two cycles of the internal
A Low-to-High input transition, after configuration is
complete, acts as a Read Trigger and initiates a Readback
II
1-MHz clock. During configuration, PWRDWN must be of configuration and storage-element data clocked by
High. II not used, PWRDWN must be tied to Vcc. CCLK. By selecting the appropriate Readback option
when generating the bitstream, this operation may be
RESET limited to a single Readback, or be inhibited altogether.
This is an active Low input which has three functions.
M1
Prior to the start of configuration, a Low input will delay the As Mode 1, this input and MO, M2 are sampled before the
start of the configuration process. An internal circuit start of configuration to establish the configuration mode to
senses the application of power and begins a minimal be used. If Readback is never used, M1 can betied directly
time-out cycle. When the time-out and RESET are com- to ground or Vcc. If Readback is ever used, M1 must use
plete, the levels of the M lines are sampled and configura- a 5-kQ resistor to ground or Vcc' to accommodate the
tion begins. RDATA output.
CCLK
During configuration, Configuration Clock is an output of
an LCA in Master mode or Peripheral mode, but an input
in Slave mode. During Readback, CCLK is a clock input
for shifting configuration data out of the LCA
2-29
XC3000 Logic Cell Array Family
INIT DIN
This is an active Low open-drain output which is held Low During Slave or Master Serial configuration, this pin is
during the power stabilization and internal clearing of the used as a serial-data input. In the Master or Peripheral
configuration memory. It can be used to indicate status to configuration, this is the Data 0 input.
a configuring microprocessor or, as a wired AND of several
slave mode devices, a hold-off signal for a master mode OOUT
device. After configuration this pin becomes a user pro- During configuration this pin is used to output serial-
grammable I/O pin. configuration data to the DIN pin of a daisy-chained slave.
BClKIN TClKIN
This is a direct CMOS level input to the alternate clock This is a direct CMOS level input to the global clock buffer.
buffer (Auxiliary Buffer) in the lower right corner.
XTl1
This user I/O pin can be used to operate as the output of Unrestricted User 1/0 Pins.
an amplifier driving an external crystal and bias circuitry.
1/0
XTl2 An 1/0 pin may be programmed by the user to be an Input
This user I/O pin can be used as the input of an amplifier or an Output pin following configuration. All unrestricted
connected to an external crystal and bias circuitry. The 1/0 pins, plus the special pins mentioned on the following
I/O Block is left unconfigured. The oscillator configuration page, have a weak pull-up resistor of 40 to 100 kQ that
is activated by routing a net from the oscillator buffer becomes active as soon as the device powers up, and
symbol output and by the MAKEBITS program. stays active until the end of configuration.
2-30
XC3000 Family Configuration Pin Assignments
-=
M2 llGH :{t{'M2 UW :}:(M2 IGH I \{:M2,Hi( :,:,:,:,',M2,HIGH 33 K2 56 4' <;13 44 66 C15 VO
HUG :HII HE I HI He He 34 5C 42 ~14 45 6C 014 VO
OW 36 59 44 U14 49 U16 VO
iNl 42 65 50 IG14 59 B' H15 VO
43 66 5' 112 19 83 J14 .oNe
53 76 6: ! M13 76 99 P15
RE' '(II ~'(II ~ (II 27 44 54 Kl0 78 63 P14 78101 R15
ONE 10~ ONE ONE 28 45 55 Jl0 80 65 N13 80 103 R14 I'RC
46 56 K' 81 66 I M12 81 104 N13 110
•
30 47 57 Jl 82 67 P13 82 105 f14 x: OR 110
48 58 Hl0 83 68 Nl' 86 109 P12 VO
•
49 6C FlO 8: 72 M9 92 115 VO
6' G' 88 N9 9l 16 Rl0 110
\4 \4 :::,::,::,:,:,:,:::,:, 6, G' B9 74 NB 9B 121 H9 VO
vc ve vcc 6, FI 9' 76 M8 100 123 N9 VCC
OAT A:,:,:",:,:,:,:,:,: 01 6' F' 92 N7 102 '" PB YU
;5' I 66 E: 9: 7B P6 103 126 H8 VO
DAIA I ':':",:,:I,',:,::,DI I ,:,:,:",:,:,:,:,:,:,: OAl ! (II:::,:,::: 6, E' 94 79 M6 lOB 131 H, VO
)}':'{{{DAl '(II)){ 56 70 010 98 83 M5 114 137 R5 VO
IT 57 Cl' 99 84 N4 115 138 P5 VO
I :::::,:::,:::::::::: 01 \ 0 (II :::::':::::::,:::,:::: DAl \ 0 (II :::::{: 38 58 72 B: 100 85 N2 119 143 R3 110
DOU ~ ~ ~~n~o ~~lml"~ m
LK CCLK CCLK 406074A1128C PI121145R2U;CCLK(IIWf
AD AD 6175~' 5wM2124148P2 VO
A Al ~~~69'Ml~1~~ m
A2 A2 63 A' 152 P' VO
A3 A3 64 78 A9, 94 153 N' 110
A15 15 65 8' B6 156 M' 110
A4 66 82 B7 157 ,2 va
67 A: 160 K2 VO
_.68 161 K VO
C6 164 GNe
A6 G 2 H2 vu
lB G' 142 3 Hl VO
\12 12 19 4 1-2 147 B c2 110
20 01 14B 9 0' VA
23 151 12 VO
AS AS ..2~. U2 152 13 VO
Al0 ~O 8 25 Bl 155 16 E: VO
A9 A9 9 26 C2 156 11. .(;2 110
X X X XX XC3020
II::}:}":! REPRESENTS A 5()'kn TO l00-kn PULL-UP x x x x x ,X XC3030
1105 250
Note: Pin assignments of "PGA Footprint" PLCC sockets and PGA packages are not electrically identical,
Generic I/O pins are not shown,
2-31
XC3000 Logic Cell Array Family
XC3000 FAMILY PIN ASSIGNMENTS Note that there is no perfect match between the number of
bonding pads on the chip and the number of pins on a
Xilinx offers the five different devices of the XC3000 family package. In some cases, the chip has more pads than
in a variety of surface-mount and through-hole package there are pins on the package, as indicated by the infor-
types, with pin counts from 44 to 175. mation ("unused" pads) below the line in the following
table. The lOBs of the unconnected pads can still be used
Each chip is offered in several package types to as storage elements if the specified propagation delays
accomodate the available pc board space and manufac- and set-up times are acceptable.
turing technology. Most package types are also offered
with different chips to accomodate design changes without In other cases, the chip has fewer pads than there are
the need for pc board changes. pins on the package; therefore, some package pins are
not connected (n.c.), as shown above the line in the
following table.
Peripheral mode and Master Parallel mode are not supported in the PC44 package
2-32
XC3000 Family 58-Pin PLCC, 84-Pin PLCC and PGA Pinouts
XC·3020* XC·3020*
68 PLCC XC-3030, XC·3042 84 PLCC 84PGA 68 PLCC XC·3030, XC-3042 84 PLCC 84 PGA
10 I'WRI:m 12 B2 44 m:sET 54 K10
11 TCLKIN-I/O 13 C2 45 DONE-I'G" 55 J10
1/0* 14 B1 46 D7-1/0 56 K11
12 110 15 C1 47 XTL 1(OUT)-BCLKIN-I/O 57 J11
13 110 16 D2 48 D6-1/0 58 H10
- 110 17 D1 - I/O 59 H11
14 110 18 E3 49 D5-1/0 60 F10
15 110 19 E2 50 C"SO-I/O 61 G10
16 110 20 E1 51 D4-1/0 62 G11
17 110 21 F2 - I/O 63 G9
18 VCC 22 F3 52 VCC 64 F9
19 110 23 G3 53 D3-1/0 65 F11
- I/O 24 G1 54 CST-I/O 66 E11
•
20 I/O 25 G2 55 D2-1/0 67 E10
21 I/O 26 F1 - I/O 68 E9
22 I/O 27 H1 1/0* 69 D11
- 110 28 H2 58 D1-1I0 70 D10
23 I/O 29 J1 57 RDY /1mS'i"-m:J:R"-1/0 71 C11
24 I/O 30 K1 58 DO-DIN-I/O 72 B11
25 M1-JmATA 31 J2 59 DOUT-I/O 73 C10
26 MO-RTRIG 32 L1 60 CCLK 74 A11
27 M2-1/0 33 K2 61 AO-WS-I/O 75 B10
28 HDC-I/O 34 K3 62 A1-CS2-1/0 76 B9
29 110 35 L2 63 A2-1/0 77 A10
30 roc· I/O 36 L3 64 A3-1/0 78 A9
31 110 37 K4 1/0* 79 B8
1/0* 38 L4 1/0* 80 A8
32 I/O 39 J5 65 A15-1/0 81 B6
33 I/O 40 K5 66 M-I/O 82 B7
1/0* 41 L5 67 A14-1/0 83 A7
34 1NlT-1/0 42 K6 68 AS-I/O 84 C7
35 GND 43 J6 1 GND 1 C6
36 I/O 44 J7 2 A13-1/0 2 A6
37 I/O 45 L7 3 AS-I/O 3 A5
38 I/O 46 K7 4 A12-1I0 4 B5
39 I/O 47 L6 5 A7-1/0 5 C5
40 110 48 L8 1/0* 6 A4
41 I/O 49 K8 1/0* 7 B4
1/0* 50 L9 6 A11-I/O 8 A3
1/0* 51 L10 7 AS-I/O 9 A2
42 I/O 52 K9 8 A10-1/0 10 B3
43 XTL2(1N)-1/0 53 L11 9 AS-I/O 11 A1
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
* This table describes the pinouts of three different chips in two different packages. The second column lists 84 of the 118 pads on the
XC3042 (and 84 of the 98 pads on the XC3030) that are connected to the 84 package pins. Ten pads indicated by an asterisk, do not
exist on the XC3020, which has 74 pads; therefore the corresponding pins on the B4-pin packages have no connections. Six pads,
indicated by a dash (-) in the 68 PLCC column, have no connections in the 68 PLCC package, but are connected in the 84-pin package.
(See table on page 2-32.)
2-33
XC3000 Logic Cell Array Family
PLCC PLCC
Pin Number XC3064, XC3090 Pin Number XC3064, XC3090
12 I'Wl'!IJN 54 "RESET
13 TCLKIN-1I0 55 DONE-PG"
14 1/0 56 D7-1I0
15 1/0 57 XTL 1I0UTl-8CLKIN-1I0
16 110 58 D6-1/0
17 1/0 59 110
18 1/0 61 D5-1/0
19 1/0 61 ~-I/O
20 1/0 62 D4-110
21 GND* 63 110
22 VCC 64 VCC
23 1/0 65 GN~
24 110 66 00·1/0*
25 1/0 67 CS1·1/~
26 1/0 68 D2·1/0*
27 1/0 69 110
28 1/0 70 D1·1/0
29 110 71 RDVtlroS'7·1ml:K·I/O
30 1/0 72 DO·DIN·I/O
31 M1-l1OATA 73 DOUT·1I0
32 MO·RTRIG 74 CCLK
33 M2·1I0 75 M·WS·I/O
34 HDC·1I0 76 A1·CS2·1/0
35 110 77 A2·1/0
36 roc·I/O 78 A3·1/0
37 110 79 110
38 110 80 110
39 110 81 A15·1/0
40 110 82 M·IIO
41 INITII/O* 83 A14·1/0
42 VCC* 84 A5·1/0
43 GND 1 GND
44 1/0 2 VCC*
45 110 3 A13·11O*
46 110 4 A6·1/~
47 1/0 5 A12·1/0*
48 1/0 6 A7·I/~
49 1/0 7 110
50 1/0 8 A11-1/0
51 1/0 9 AS-li~
52 1/0 10 A10-1/0
53 XTL2(IN)-1/0 11 A9-1/0
Unprogrammed lOBs have a default pull-up. This prevents an undfined pad level for unbonded or unused lOBs.
Programmed ouptuts are default slew-rate limited. DEVICE POWER MUST BE LESS THAN 1 WAn.
2-34
XC3000 Family 100-Pin QFP Pinouts
• This table describes the pinouts of three different chips in two different packges. The third column lists 100 of the 118 pads on the
XC3042 that are connected to the 100 package pins. Two pads, indicated by double asterisks, do not exist on the XC3030, which has
98 pads; therefore the corresponding pins have no connections. Twenty-six pads, indicated by single or double asterisks, do not exist
on the XC3020, which has 74 pads; therefore, the corresponding pins have no connections. (See table on page 2-33.)
2-35
XC3000 Logic Cell Array Family
Unprogrammed lOBs have a default pUll-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited .
2·36
XC3000 Family 160-Pln PQFP Pinouts
Unprogrammed lOBs have a default pull-up_ This prevents an undefined pad level for unbonded or unused 10Bs_
Programmed lOBs are default slew-rate limited.
2-37
XC3000 Logic Cell Array Family
2-38
E:XlUNX
Pins A2, A3, A15, A16, Tl, T2, T3, T15 and T16 are not connected_
Pin A1 does not exist
2-39
XC3000 Logic Cell Array Family
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings
conditions for extended periods of time may affect device reliability.
OPERATING CONDITIONS
Vee Supply voltage relative to GND Commercial O°C to +70°C 4.75 5.25 V
2-40
DC CHARACTERISTICS OVER OPERATING CONDITIONS
VOH High-level output voltage (@ 10H = -4.0 mA, Vcc min) Commercial 3.S6 V
VOL Low-level output voltage (@ IOL = 4.0 mA, Vcc max) 0.32 V
VOH High-level output voltage (@ IOH = -4.0 mA, Vcc min) Industrial 3.76 V
Military
VOL Low-level output voltage (@ IOL = 4.0 mA, Vcc max) 0.37 V
'RIN Pad pull-up (when selected) @ VIN = OV (sample tested) 0.02 0.17 mA
'RLL Horizontal long line pull-up (when selected) @ logic Low 0.2 2.5 mA
Note: 1. Devices with much lower ICCPD tested and guaranteed at Vcc =3.2 V, T =25°C can be ordered with a
Special Product Code.
XC3020: SPC011 0 ICCPD =1 ~A
XC3030: SPC0104IccPD= 2 ~A
XC3042: SPC01071ccPD = 3 ~A
XC3064: SPC0108 ICCPD = 4 ~A
XC3090: SPC01 09 ICCPD = 5 ~A
2. With no output current loads, no active input or long line pull-up resistors, all package pins at Vcc or GND,
and the LCA configured with a MAKEBITS '1ie" option. See LCA power chart for additional activity-dependent
operating component.
2-41
XC3000 Logic Cell Array Family
CLBCLOCK
@ TCl
o TOICK--+t..-
CLB INPUT
(DIRECT IN)
CLBINPUT
(ENABLE CLOCK) ------'I~-------t---_::::_--I ~_ _ _ __
CLBOUTPUT
(FLIP-FLOP)
CLBINPUT
(RESET DIRECT) _ _ _ _ _ _ _..1
CLBOUTPUT
(FLIP-FLOP)
1105 26
BUFFER (Internal) SWITCHING CHARACTERISTIC GUIDELINES
~:~t;~
on XC3020 3.2/4.5 2.9/3.9 ns
on XC3030 3.4/5.1 3.1/4.3 ns
on XC3042 3.7/5.7 3.3/4.9 3:114:4 ns
on XC3064 4.1/6.6 3.6/5.5 3;~Z§;0 ns
on XC3090 4.6/7.9 4.0/6.4 3i~t~~8 ns
~i
TON
Ti to l.l. (inactive) with single pull-up resistor Tpus 22 14 ns
with pair of pull-up resistors TpUF 11 7 ns
BIOI
Bidirectional buffer delay TBIDI 4 3 2.5
•••••••••••••••••••••
ns
.. Timing is based on the XC3020, for other devices see XACT timing calculator.
2-42
CLB SWITCHING CHARACTERISTIC GUIDELINES (Continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Combinatorial Delay
Logic Variables a, b, c, d, e, to outputs x, y 1 TllO 9 7 5.5 ns
Sequential delay
Clock k to outputs x, y 8 TCKo 8 7 6 ns
Clock k to outputs x,y when Q is returned
through function generators For G to drive x, y 15 12 10 ns
ri;:
ns
ns
ns
Clock
Clock High time'
a,b,c,d,e
di
ec
3
5
7
11
TCKI
TCKDI
TCKEC
TCH
0
4
0
7
0
2
0
5
'I
4i I
~..,•...•.
~ ....
f
ns
ns
ns
ns
~::,..:,.:
1~~ f':""'"
Clock Low time' 12 TCl 7 5 ns
Max. flip-flop toggle rate' FClK 70 100 MHz
Note: The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (TCKDI, #5) of any CLB on the same die.
2-43
XC3000 Logic Cell Array Family
-®-TPID~-t----
110 BLOCK (I)
VO PAD INPUT
t-CD-1-T-P-,C-K--------..J
VOCLOCK
(lK/OK)
1 + - - - - @ T,Ol---~----
VOBLOCK(O)
VO PAD OUTPUT
(DIRECn
__________________f0TOKPO
VO PAD OUTPUT
(REGISTERED)
J---Ir-@-~-SON----@-~-"'j I
110 PADTS
I ~----P-RO-G-R-AM-.-CO-N-T-RO-L -E-M-OR-Y-C-E-LL-S---~
..
LE-D-...
Voc
:j
3- STATE ~:;:~:..--I------=JL/--t-,
(OUTPUT ENABLE)
.,
OUT ~~---t,,-,,
DIRECT IN ........
,:-'i-----,f------,
REGISTERED IN ...-:,;-~
, -'-----if---i
2-44
lOB SWITCHING CHARACTERISTIC GUIDELINES (Continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
ns
II
same (slew rate limited) 7 TOKPO 33 27 ····'·'·'···,·.'• •·9 ns
Output (0) to Pad (fast) 10 TOPF 9 6 ,·,···.··'••••'• • • ·5 ns
same (slew-rate limited) 10 Tops 29 23 ns
3-state to Pad begin hi-Z (fast) 9 TTSHZ 8 8 ns
same (slew-rate limited) 9 TTSHZ 28 25 Ii • . •.•,'"'..··7
,·.·········.·' ns
3-state to Pad active and valid (fast) 14 12 ;, .••.•••• 1 ns
8 TTSON
same (slew -rate limited) 8 TTSON 34 29 ns
"""'"".f
Set-up and Hold Times (Output)
Output (0) to clock (ok) set-up time 10 9 ns
Output (0) to clock (ok) hold time o o ns
Clock
Clock High time 7 5 ns
Clock Low time 7 5 ns
Max. flip-flop toggle rate 70 100 MHz
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (inc!. test fixture).
For larger capacitive loads, see page 6-9.
Typical slew rate limited output riselfall times are approximately four times longer.
A maximum total external capacitive load for simultaneous fast mode switching in the same direction
is 500 pF per power/ground pin pair. For slew-rate limited outputs this total is four times larger.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured
with the internal pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (.ik)
In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value.
Input pad holdtime with respect to the internal clock (ik) is negative. This means that pad level changes immediately
before the internal clock edge (ik) will not be recognized.
For a more detailed description see the discussion on "LCA Performance" in the Applications Section.
2-45
XC3000 Logic Cell Array Family
~_ _ _-;III-I_ _( 0 T R W ) - - - - - - - -
MOIM11M2
-£®'~®'~f--------
DONEIPROG
~_®TPGW~
___J
____
- [®TPGI
INIT
(OUTPUn USER STATE ______C_LE_A~RI~S-TA-T-E--------JI' CONFIGURATION STATE
- II .
\ _____--11'
r-NOTE 3-+j
--------------------------------------------;\ lr~t------
Vee (VALID)
•\. ____ 1--,:
• VCCPD
1105 28
Notes: 1. At power-up, Vee must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be de-
layed by holding RE"SET Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vee may require. a RESET pulse (High-to-Low-to-High) of >6 j.lS duration after Vee has reached 4.0 V.
2. RE"SET timing relative to valid mode lines (MO, M1, M2) is relevant when RESET is used to delay configuration.
3. PWRDWN transitions must occur while Vcc >4.0 V.
2-46
MASTER SERIAL MODE PROGRAMMING SWITCHING CHARACTERISTICS
CCLK
(OUTPUT)
SERIAL DATA IN
SERIAL DOUT
(OUTPUT) _ _ _ _ _...1 '-_ _ _ _ _- - 1 ' - -_ _ _ _ _...1 '-_ _ _ _ _ _ __
1105 29
CCLK3
Description
Data In setup 1
Symbol
TDSCK
Min
60
Max Min
60
Max Min
60
Max
ns
II
Data In hold 2 TCKDS 0 0 0 ns
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms. If this is not possible, configuration can be de-
layed by holding RESET Low until Vcc has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vcc may require a RESET pulse (High-to-Low-to-High) of >6 ~s duration after Vcc has reached 4.0 V.
2. Configuration can be controled by holding RESET Low with or until after the TNTT of all daisy-chain slave-mode devices
is High.
3. Master-serial-mode timing is based on slave-mode testing.
2-47
XC3000 Logic Cell Array Family
DO--D7
RClK
(OUTPUn / tl4-=--=--=--=--=--_"",-il-_-7 C-C-l-KS-_-_-_-_-_-_...I-r_--
CClK
(OUTPUT)
DOUT
(OUTPUn D7
BYTE n-1
1105 30
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be de-
layed by holding RESET Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vcc may require a RESET pulse (High-to-Low-to-High) of >611S duration after Vee has reached 4.0 V.
2. Configuration can be controlled by holding11Em:T Low with or until after the lNlT of all daisy-chain slave-mode devices
is High.
This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.
2-48
E:XIUNX
•.
CS1/CSO
\ I .
)
CS2 7 \ I
I
WS
00-07
CCLK •
• I
'\ •• • 1
I •
• I
'\ •• • 1
I
II
ROYIBUSY I
I
- •••••••••••••••••••••• 1
OOUT
_--'x'--_--'x"-______--' . . . --'X. . . ____C 1105 lOA
Notes: 1. At power-up, Vee must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be de-
layed by holding RESET Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vee may require a RESET pulse (High-to-Low-to-High) of >61ls duration after Vee has reached 4.0 V.
2. Configuration must be delayed until the TfiIlT of all LCAs is High.
3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and
the phase of the internal timing generator for CCLK.
4. CCLK and DOUT timing is tested in slave mode.
2-49
XC3000 Logic Cell Array Family
~: =10'=t@'=0~~ ___-<'f*:0-'~"ro~@5
DOUT
TCCl
-----------
(OUTPUT) BIT N-1 _____B_IT_N_ __ "0531
Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the LCA device.
2. Configuration must be delayed until the TJillT of all LCAs is High.
3. At power-up, Vcc must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be de-
layed by holding RESET Low until Vcc has reached 4.0 V. A very long Vcc rise time of > 100 ms, or a non-monotonically
rising Vcc may require a RESET pulse (High-to-Low-to-High) of >61ls duration after Vee has reached 4.0 V.
4. For configuration (not Readback), CCLK frequency can be increased to 5 MHz and TCCH and Tccl min reduced to
100 ns, worst case over temperature and supply voltage. This high-speed CCLK frequency will be tested, documented
and guaranteed some time in 1991. For further information on running CCLK faster than 1 MHz, contact Xilinx Product
Marketing.
CCLK(1)
RDATA
(OUTPUT) 110532A
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be de-
layed by holding RESET Low until Vcc has reached 4.0 V. A very long Vcc rise time of > 100 ms, or a non-monotonically
rising Vcc may require a RESET pulse (High-to-Low-to-High) of >61ls duration after Vee has reached 4.0 V.
2. CCLK and DOUT timing are the same as for slave mode.
3. RETRIG (MO positive transition) shall not be done until after one clock following active 1/0 pins.
4. Readback should not be initiated until configuration is complete.
2-50
PGA PIN-OUTS
1 2 3 4 5 6 7 8 9 10 11 11 10 9 876 5 4 3 2 1
A @@@)@;)@~@)@;)@@8 A A 8@@@;)@)~@@;)@)@@ A
B @@@)@@(@@@@@@ B B @@@@@(@@@@)@@ B
c O~EB @8@ ~~ c c ~~ @8@ EB~O c
D 00 @@;) D D @@ [BOTTOM VHEW 00 D
E 000 TOP V~IEW O®~ E E ~®O 000 E
F 008 8@@ F F @@8 Solder Side 800 F
Component
G 000 O~@ G G @~O 000 G
Side O@
H 00 @O H H 00 H
J o® 080 ~@ J J @~ 080 ®O J
K
L
O@@OO~OOO~@
®O~@@OOO@@@
K
L
K
L
@@OOO(@OO@@O
@@;)@;)0001@@~0®
K
L
II
1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1
I 2 3 4 5 6 7 8 9 10 II 12 13 14 14 13 12 II 10 9 8 7 6 5 4 3 2 I
A"@@@)OOOOOOO@@@® A A ®@@)@OOOOOOO@@@ A
B @l00000000000®@ B B @®00000000000@l B
c 0@0800890080@0 c c 0@0800980080@0 c
D @>@9 90~ D D ~09 9@@) D ~9 1(0
I 2 3 4 5 6 7 8 9 10 II 12 13 14 14 13 12 II 10 9 8 7 6 5 4 3 2 I
(NC) = Pin Not Connected for XC3042. unlabeled pin _ unrestricted 110 pin
2-51
XC3000 logic Cell Array Family
I 2 3 4 5 6 7 8 9 10 II 12 13 14 15 16 16 15 14 13 12 II 10 9 8 7 6 5 4 3 2 I
A @@OOOOOOOOOOO@@ A A@@OOOOOOOOOOO@@ A
B 0r@00000000000®®0 B B O®®OOOOOOOOOOO@O B
c@@900000000009@Oc c 0@900000000009@@ c
D rw09@00099000090~ D D~09000099000@90rwD
E @O~ ~OO E E OO@) @JO@ E
~ 8~8 TOP VHEW
H @~9 Component
~ G 000
F 000 O~O F
000 G
9@0 H H 0@9 IBOTTOM V~IEW 9~@ H
888
J 009 900 J J 009 900 J
K @~O Side 000 K K 000 Solder Side O~@ K
L O@O 000 L L 000 O@O L
M @l0@ 000 M M 000 @O@l M
N @09~00099000®900 N N009®00099000~90@N
p @@90~00@000@09@0 p pO@90@OOO@OO~09@@p
R O@@O@O®~®~OOO~@)O R RO@~OOO~®~®O@O@@OR
T @@@0000000@00@l@@ T T @@@lOO@OOOOOOO@@@ T
I 2 3 4 5 6 7 B 9 10 II 12 13 14 15 16 16 15 14 13 12 11 10 9 B 7 6 5 4 3 2 I
(NC) _ Pin Not Connected. unlabeled pin. unrestricted 110 pin
2-52
PHYSICAL DIMENSIONS
PIN #1 ID LOCATION
(EITHER POS.) 0.050TYP
~~m
0.653 ± 0.003 0.690
9 JA = 40-45 °CIW
9 JC = 10-11 °CIW
II
~""'J
0.010
~
~10.015
LEAD CO-PLANARITY
± 0.002
14 0.620 - - - - - - DIMENSIONS
IN INCHES
1105428
0.045 x45'
9 61
PWRDWN CCLK
DOUT/IO
0.990
±0.005
0.94 Vee Vee
1L.1+=-=--1~27-0.954±0.004~1 IN INCHES
O.~
...
_ - - - - - 0 . 9 9 0 ± 0.005====:11
TOP VIEW
9 JA = 35-40 °eIW
9 Jc= 7-10 °eIW
110534C
2-53
XC3000 Logic Cell Array Family
0.045 x 450",-
11
L.'L,
PINNO.1
PIN NO.1 IDENTIFIER
75
0.045
~
PWRDWN CCLK
DOUT/IO
P
1 .190
± 0.005 1.000
1.154 TYP
Vee Vee
±0.004
1.120
±0.010
0.Q18
-'--
T
M1 DONE
MO RESET
0.028 *=+=~*
~01--33
-'-- JU cucaue
_ _ 1.154±0.004._ _ _5-413 41
i"~....- - - - - - - - 1 . 1 9 0 0.005-------~1.
±
LEAD PITCH
0.050 TYPICAL
TOP VIEW
DIMENSIONS IN INCHES
8 JA = 30-35 °C/W
8 Jc =3-7 °CIW 1105 36C
84-Pin PLCC Package
0.130
±O.Q10
~
1.000±0.010
1.100±0.012S
j+---t
\' 0.100 TYP
0.100
TYP
~~ ...Lb.~
~~
'-V '-V
~~
'-V '-V
IL
1-( ~ !1-
I~fhfj- b.
G -"' b D D
-"' 1.00o
±O.OI o
-"' b D-L
Y
~ JEXPIN
TYP.0.Q70
-(3--E D:l'08 MAX
\Q
i-"
c
B L ~
A ~
~
• 7 10 11
BOTTOM VIEW
NOTE: INDEX PIN MAY OR MAY NOT BE
8 JA = 30-35 °C/W ELECTRICALLY CONNECTED TO PIN C2.
DIMENSIONS IN INCHES
8 Jc = 4-7 °C/W
110535C
84-Pin PGA Package
2-54
1':XILINX
0.009 • 0.005
0.705 • 0.01 0
LEAD PITCH
1 - - - - - 0.742REF-----oj 0.0256TYP
TOP VIEW
~~
5-7.
f-...;~--------------,__r "',',
""
II
0.57.0.006
WilllilluuummD~~~~m][m[lh=i.·O~:TINGPLANE"
~
"
0.031± 0.006
. DIMENSIONS IN INCHES
1105391::
LEADFRAME
0.0045 MIN
0.0080 MAX
MIN
MAX
r'''[ MARKING
0.145 MAXJ
NOTES:
1. LEADS ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS.
TOPSIDE UP
8JA = 40-50° CIW 2. FORMING TOOL INFORMATION:
8JC = 5-80 CIW : ~f~~r%IT~I~~~~~f~~~~g7g~ ~~~ ~?WELL NJ.
1105 40C
2-55
XC3000 Logic Cell Array Family
p 0000000,000000 0
1
0.018 ± 0.002 DIAJ
N 00000000000000 TYP 0.070 DIA
± 0.005
132 PLCS
M00000000000000
L 000 r - - - - + - -_____ -'-~u.:;.L+---.-
K 000 000
J 000 000
H 000 000
+ O. 45 1.460
F 000 000
E 000 000
0000
c 000 000000
• 000 000000
000000
C±~~~ --:~~~'-P=~~:----of
0.070
±0.01 sa
I. 1<--1.
± 0.015
BOTTOM VIEW
110538B
1234567&91011121314
p 0000000,000000~
N0000000000000 0 l'-is~~gE~FFPIN)
M00000000000000
L000 000
K000 000
J000 000
£~~00 + 00~,- 1.460
G 000 I 000 ± 0.01
F 0 0 0 BLACK ANODIZED 0 0 0
E 000 ALUMINUM LID 000
o 000 000
c 00000000000000
• 00000000000000
A 0000000000000~ _ _ _ _..L
±06~tl
0.050
± 0.004
CHAMFER
0,039 X 45°
REF
I, [±-0.100±0.002
1.300±0'012------oI,I .1
1.460±O.015-------I-. 0.197
DIMENSIONS IN INCHES
BOTTOM VIEW
0.070
1105 438
132-Pin PPGA Package
2-56
PHYSICAL DIMENSIONS (Continued)
DE VITREOUS
SOLDER GLASS
r-[
II
". ~J III ~o_ ~~
~0.120MAX
0.0300 ± 0.0050 •• _
BOTTOM VIEW
(LID SIDE UP)
(DIE FACING UP)
SIDE VIEW
0.008 MIN
0.013 MAX
1105410
2-57
XC3000 Logic Cell Array Family
o INDEX (Al)
PIN KOVAR
0.005 R. TYP.
0.016 REF
,,000000000000000
010000000,00000010
15 0
M0000000000000000 0.070
± 0.005 TYP DIA
130000
0000
12 0000
110000 0000
,,0000 0000
~ 0 0.--::=0~0~o--tt---+
9
0000 0.845
± 0.009
1.660
± 0.016 sa
'0000 0000 1. 0
BOTTOM VIEW
1105 37C
2-58
PHYSICAL DIMENSIONS (Continued)
TOP VIEW
o 0 0 0 0 0 0 0 0 000 0 0 0
o 0 0 0 0 000 0 0 0 0 0 0 0 0
000 0 0 0 0 0 0 0 0 0 000 0
o 0 0 0 000 0
o 0 0 0 o 0 0 0
rt-
000 0 I 000 0
000 0 000 0
000 0 000 0 El JA =22'C/W
o 0 0 0 000 0 ElJC= 1.6'C/W
000 0 000 0
o 0 0 0 000 0
r- 0.071 ± 0.006
o 0 o 0 I 000 0
o 0 0 0 L -_ _ _ _ _ _ +-______ ~
o 0 0 0
000 000 000 000 000 0
o 0 0 0 0 0 000 000 0 000 . . 0.070 ± 0.00
o 0 000 0 0 0 0 000 0 0 0 0
1.660
± 0.01650
T R P NMLKJHGFEDCBA"'-.
1991018
2-59
Component Selection and
Ordering Information
Xll04
""';~''''
Toggle
IJ TlL
XC3020-70PC68C
,~,.••"
Range
Number of Pins
Note, however, that the XC2000 and XC3000 families
differ in the position of XTL 1 as well as three parallel
address bits (6, 7 and 11) and most of the data pins used
in parallel master mode.
XC2018 and XC3020 are not available in PGA68, since
the PGA84 is the same size and offers more 1/0.
Rate
Note that a PLCC in a socket with PGA footprint generates
Package Type a printed circuit board pin-out different from a PGA device.
2-60
XC2064/XC201 S
Logic CeW Array M
Product Specification
2-61
XC2064/2018 Logic Cell Array
The static memory cell used for the configuration memory affected by extreme power supply excursions or very high
in the Logic Cell Array has been designed specifically for levels of alpha particle radiation. In reliability testing no
high reliability and noise immunity. Based on this design, soft errors have been observed, even in the presence of
which has been patented, integrity of the LCA configura- very high doses of alpha radiation.
tion memory is assured even under adverse conditions.
Compared with other programming alternatives, static Input/Output Block
memory provides the best combination of high density,
high performance, high reliability and comprehensive Each user-configurable liD block (lOB) provides an inter-
testability. As shown in Figure 2, the basic memory cell face between the external package pin of the device and
consists oftwo CMOS inverters plus a pass transistor used the internal logic. Each I/O block includes a programmable
for writing data to the cell. The cell is only written during input path and a programmable output buffer. It also
configuration and only read during readback. During provides input clamping diodes to provide protection from
normal operation the pass transistor is "off" and does not electro-static damage, and circuits to protect the LCA from
affect the stability of the cell. This is quite different from the latch-up due to input currents. Figure 3 shows the general
normal operation of conventional memory devices, in structure of the liD block.
which the cells are continuously read and rewritten.
The input buffer portion of each liD block provides thresh-
The outputs Q and Q control pass-tranSistor gates directly. old detection to translate external signals applied to the
The absence of sense amplifiers and the output capacitive package pin to internal logic levels. The input buffer
load provide additional stability to the cell. Due to the threshold of the liD blocks can be programmed to be
structure of the configuration memory cells, they are not compatible with either TIL (1.4 V) or CMOS (2.2 V) levels.
1/0 BLOCK
¢;J Q¢;J
D CONFIGURABLE
LOGIC BLOCK~
-[}
-[}
o 0 0 0
-[} 0 01 0 0 .. INTERCONNECT AREA ~
-[}
-[} 0 OJ 0 0
-[}
-[} 0 0 0 0
110401
Figure 1. Logic Cell Array Structure
2-62
The buffered input signal drives both the data input of an the I/O block output buffer. Each 1/0 block output buffer is
edge-triggered D flip-flop and one input of a two-input controlled by the contents of two configuration memory
multiplexer. The output of the flip-flop provides the other cells which turn the buffer ON or OFF or select 3-state
input to the multiplexer. The user can select either the buffer control. The user may also select the output buffer
direct input path or the registered input, based on the 3-state control (1/0 block pin TS). When this 1/0 block
content of the memory cell controlling the multiplexer. The output control signal is High (a logic "1 "), the buffer is
1/0 Blocks along each edge of the die share common disabled and the package pin is high-impedance.
clocks. The flip-flops are reset during configuration as well
as by the active-low chip RESET input. Configurable Logic Block
Output buffers in the 1/0 blocks provide 4-mA drive for high An array of Configurable Logic Blocks (CLBs) provides the
fan-out CMOS or TTL-compatible signal levels. The functional elements from which the user's logiC is con-
output data (driving 1/0 block pin 0) is the data source for structed. The logic blocks are arranged in a matrix in the
III
READ or
WRITE
DATA
1105 12
TS (OUTPUT ENABLE)
OUT
IN
D Qf----'
-fI _ PROGRAM·CONTROLLED
~ - MULTIPLEXER
VOCLOCK
1104 03
2-63
XC206412018 Logic Cell Array
OUTPUTS
A
G
B Y
INPUTS COMB.
C LOGIC
0
F
CLOCK
1104 04
center of the device. The XC2064 has 64 such blocks logic block inputs and the storage element output "Q". A
arranged in an 8-row by 8-column matrix. The XC2018 has third form of the combinatorial logic (Option 3) is a special
100 logic blocks arranged in a 10 by 10 matrix. case ofthe 2-function form in which the B input dynamically
selects between the two function tables providing a single
Each logic block has a combinatorial logic section, a
storage element, and an internal routing and control sec-
tion. Each CLB has four general-purpose inputs: A, B, C
and D; and a special clock input (K), which may be driven
fromthe interconnect adjacentto the block. Each CLB also
has two outputs, X and Y, which may drive interconnect
networks. Figure 4 shows the resources of a Configurable
Logic Block.
C
D
each. The variabies may be selected from among the four
inputs and the block's storage element output "Q". I I G
Figure 5 shows various options which may be specified for 0
the combinatorial logic.
2-64
merged logic function output. This dynamic selection
allows some 5-variable functions to be generated from the
four block inputs and storage element Q. Combinatorial
functions are restricted in that one may not use both its
storage element output Q and the input variable of the logic
block pin "0" in the same function.
SET
F---------ID Q
If used, the storage element in each Configurable Logic
Block (Figure 6) can be programmed to be either an edge- K-':---r-.
sensitive "0" type flip-flop or a level-sensitive "0" latch. c-:O:---l
The clock or enable for each storage element can be
selected from: RES
D-;':--~
• The special-purpose clock input K
• The general-purpose input C
• The combinatorial function G
The user may also select the clock active sense within
each logic block. This programmable inversion elimi-
nates the need to route both phases of a clock signal
throughout the device. Figure 6. CLB Storage Elememt
A
A
B ANY ANY
FUNCTION FUNCTION
C OF3 F OF3 F
VARIABLES C VARIABLES
D D
M
U
X
A
A
B ANY ANY
FUNCTION FUNCTION
C OF3 G OF3 G
VARIABLES C VARIABLES
D D
OPTION 2 OPTION 3
2-65
XC206412018 Logic Cell Array
The two block outputs, X and Y, can be driven by either the and then toggling the states of the interconnect points by
combinatorial functions, F or G, or the storage element selecting them with the "mouse". In this mode, the connec-
output Q (Figure 4). Selection of the outputs is completely tions through the switch matrix may be established by
interchangeable and may be made to optimize routing selecting pairs of matrix pins. The switching matrix com-
efficiencies of the networks interconnecting the logic binations are indicated in Figure 7b.
blocks and I/O blocks.
Special buffers within the interconnect area provide peri-
PROGRAMMABLE INTERCONNECT odic signal isolation and restoration for higher general
interconnect fan-out and beUer performance. The re-
Programmable interconnection resources in the Logic Cell powering buffers are bidirectional, since signals must be
Array provide routing paths to connect inputs and outputs able to propagate in either direction on a general intercon-
of the I/O and logic blocks into desired networks. All nect segment. Direction controls are automatically estab-
interconnections are composed of metal segments, with lished by the LogiC Cell Array development system soft-
programmable switching points provided to implement the ware. Repowering buffers are provided only for the
necessary routing. Three types of resources accommo- general-purpose interconnect since the direct and long
date different types of networks: line resources do not exhibit the same R-C delay accumu-
lation. The Logic Cell Array is divided into nine sections
• General purpose interconnect with buffers automatically provided for general intercon-
• Long lines nect at the boundaries of these sections. These bound-
• Direct connection aries can be viewed with the development system. For
routing within a section, no buffers are used. The delay
General-Purpose Interconnect calculator of the XACT development system automatically
calculates and displays the block, interconnect and buffer
General-purpose interconnect, as shown in Figure 7a, is delays for any selected paths.
composed of four horizontal metal segments between the
rows and five vertical meta! segments between the col-
umns of logic and I/O blocks. Each segment is only the
"height" or ''width'' of a logic block. Where these segments
would cross at the intersections of rows and columns,
switching matrices are provided to allow interconnections
of metal segments from the adjoining rows and columns.
Switches in the switch matrices and on block outputs are
specially designed transistors, each controlled by a con-
(t ,
CLB
I
I
figuration bit. _oJ SEE FIG. 7b
A
Logic-block output switches provide contacts to adjacent
general interconnect segments and therefore to the
switching matrix at each end of those segments. A switch
matrix can connect an interconnect segment to other
segments to form a network. Figure 7a shows the general
interconnect used to route a Signal from one logic block to
three other logic blocks. As shown, combinations of
closed switches in a switch matrix allow multiple branches
B
C
K
CLB
X
Y
0
for each network. The inputs of the logic or I/O blocks are
multiplexers that can be program-med with configuration CLB
bits to select an input network from the adjacent intercon-
nect segments. Since the switch connections to block
inputs are unidirectional (as are block outputs) they are
usable only for input connection. The development sys-
tem software provides automatic routing of these intercon-
nections. Interactive routing is also available for design 110407
2-66
AVAILABLE PROGRAMMABLE
SWITCH MATRIX INTERCONNECTIONS
OF GENERAL INTERCONNECT
SEGMENTS BY PIN
,,
,,
00
Q-i
, , G 3.
•
7
• •
3
•
•
7
• •
3
4
a
0 0
~
•
·.
7
3
•
s.
•
7
• 5
3
4
a· . 0.
X
• 3 • 3
Y 7 • 7 4
,,
: • •
Q-i
, ,
-} II
{~
, , 0
00 ~ ~
_ 4 HORIZONTAL
r;Jr;J0 • 3 • 3
~ GENERAL PURPOSE
0r;J 0 INTERCONNECT
7 4 7 •
:0
,r-' • •
6 5
0 0 ,,
,
I
I
I
I I I I
5 VERTICAL
GENERAL PURPOSE \ PROGRAMMABLE
INTERCONNECT INTERCONNECT POINTS
BETWEEN SWITCH (DO NOT USE MORE THAN
MATRICES ONE PER INPUT PIN)
1104 08
Long Lines the global buffer for a clock provides a very low skew, high
fan-out synchronized clock for use at any or all of the logic
Long-lines, shown in Figure 8a, run both vertically and blocks. At each block, a configuration bit forthe K input to
horizontally the height or width of the interconnect area. the block can select this global line as the storage element
Each vertical interconnection column has two long lines; clock signal. Alternatively, other clock sources can be
each horizontal row has one, with an additional long line used.
adjacent to each set of I/O blocks. The long lines bypass
the switch matrices and are intended primarily for signals A second buffer below the bottom row of the array drives
that must travel a long distance or must have minimum a horizontal long line which, in turn, can drive a vertical long
skew among multiple destinations. line in each interconnection column. This alternate buffer
also has low skew and high fan-out capability. The
A global buffer in the Logic Cell Array is available to drive network formed by this alternate buffer's long lines can be
a single signal to all Band K inputs of logic blocks. Using selected to drive the B, Cor K inputs of the logic blocks.
2-67
XC206412018 Logic Cell Array
--.-..J
B B I
I
SWITCH
MATRIX
I
I ~
--.-..J
B
~
e B
0 CLB
X
SWITCH
MATRIX
HORIZONTAL
LONG LINE
B BTWO VERTICAL ~
GLOBAL
LONG LINES LONG LINE
110409
Alternatively, these long lines can be driven by a logic or bottom of the die. Direct interconnections of I/O blocks
I/O block on a column by column basis. This capability with CLBs are shown in Figure 8b.
provides a common, low-skew clock or control line within
each column of logic blocks. Interconnections of these CRYSTAL OSCILLATOR
long lines are shown in Figure 8b.
An internal high speed inverting amplifier is available to
Direct Interconnect implement an on-chip crystal oscillator. It is associated
with the auxiliary clock buffer in the lower right cornerof the
Direct interconnect, shown in Figure 9, provides the most die. When configured to drive the auxiliary clock buffer,
efficient implementation of networks between adjacent two special adjacent user I/O blocks are also configured to
logic or 1/0 blocks. Signals routed from block to block by connect the oscillator amplifier with external crystal oscil-
means of direct interconnect exhibit minimum intercon- lator components, as shown in Figure 10. This circuit
nect propagation and use minimum interconnect re- becomes active before configuration is complete in order
sources. For each Configurable Logic Block, the X output to allow the oscillator to stabilize. Actual internal connec-
may be connected directly to the C or D inputs of the CLB tion is delayed until completion of configuration. The
above and to the A or B inputs of the CLB below it. The Y feedback resistor R1 between output and input, biases the
output can use direct interconnect to drive the B input of the amplifier at threshold. It should be as large a value as
block immediately to its right. Where logic blocks are practical to minimize loading of the crystal. The inversion
adjacent to I/O blocks, direct connect is provided to the of the amplifier, together with the R-C networks and
I/O block input (I) on the left edge of the die, the output (0) crystal, produce the 360-degree phase shift of the Pierce
on the right edge, or both on I/O blocks at the top and oscillator. A series resistor R2 may be included to add to
2-68
GLOBAL VERTICAL LONG LINES HORIZONTAL LONG LINES
BUFFER (2 PER COLUMN) (1 PERROW)
II
X1205
Figure 8b. XC2064 Long Lines, 110 Clocks, 1/0 Direct Interconnect
2-69
XC2064/2018 Logic Cell Array
POWER
Power Distribution
2-70
Power Consumption the sum of capacitive and resistive loading of the devices
driven by the Logic Cell Array.
The Logic Cell Array exhibits the low power consumption Internal power supply dissipation is a function of clock
characteristic of CMOS ICs. Only quiescent power is frequency and the number of nodes changing on each
required for the LCA configured for CMOS input levels. clock. In an LCA the fraction of nodes changing on a given
The TTL input level configuration option requires additional clock is typically low (10-20%). For example, in a 16-bit
power for level shifting. The power required by the static binary counter, the average clock produces a change in
memory cells which hold the configuration data is very low slightly less than 2 of the 16 bits. In a 4-input AND gate
and may be maintained in a power-down mode. there will be 2 transitions in 16 states. Typical global clock
buffer power is about 3 mW / MHz for the XC2064 and 4
Typically most of power dissipation is produced by capaci- mW / MHz for the XC2018. With a "typical" load of three
tive loads on the output buffers, since the power per output general interconnect segments, each Configurable Logic
is 251lW / pF / MHz. Another component of I/O power is Block output requires about 0.4 mW / MHz of its output
the DC loading on each output pin. For any given system, frequency. Graphs of power versus operating frequency
the user can calculate the I/O power requirement based on are shown in Table 1 on page 2-83.
GND
II
GROUND AND
VeeRING FOR
+--+--+--+--+--+--+--+ 1/0 DRIVERS
+--+--+--+--+--+--+--+
I I I I I I
I I I I I
+--+--+--+--+--+--+--+
I I I ,
I ' I I
+--+--+--+--+--+--+--+
I I I ' I
Vee I I I 1 I
+--+--+--+--+--+--+--+
I I I I I I I I
I I I I I I I ~--I-H~
+--+--+--+--+-- , --+--+
, , LOGIC POWER GRID
+--+--+--+--+--+--+--+,
, ,
+--+--+--+--+--+--+--+
GND
110412
2-71
XC206412018 Logic Cell Array
HOC = HIGH
LOC = LOW
Figure 12. A State Diagram of the Configuration Process for Power-up and Re-program
11111111
0010
< 24·BIT LENGTH COUNT>
1111
CONFIGURATION PROGRAM LENGTH
DUMMY BITS (4 BITS MINIMUM)
J
DUMMY BITS (4 BITS MINIMUM), XACT 2.10 GENERATES 8 BTS
PREAMBLE CODE HEADER
I
a < DATA FRAME # 002 > 111
o < DATA FRAME #003 > 111 XC2018 XC2064
CONFIGURATION PROGRAM DATA
FRAMES 196 160
DATA BITS
PER FRAME 87 71 REPEATED FOR EACH LOGIC
CELL ARRAY IN A DAISY CHAIN
a < DATA FRAME # 159> 111
a < DATA FRAME # 160 > 111
2-72
E:XiUNX
configuration requires 12,038 bits for each device. Forthe MODE PIN
XC2018, the configuration of each device requires 17,878 MODE SELECTED
bits. The XC2064 uses 160 configuration data frames and MO Ml M2
the XC2018 uses 197.
0 0 0 MASTER SERIAL
The configuration bit stream begins with preamble bits, a 0 0 1 MASTER LOW MODE
preamble code and a length count. The length count is
loaded into the control logic of the Logic Cell Array and is 0 1 1 MASTER HIGH MODE
used to determine the completion of the configuration 1 0 1 PERIPHERAL MODE
process. When configuration is initiated, a 24-bit length
counter is set to 0 and begins to count the total number of 1 1 1 SLAVE MODE
configuration clock cycles applied to the device. When the
MASTER LOW ADDRESSES BEGIN AT 0000 AND INCREMENT
current length count equals the loaded length count, the MASTER HIGH ADDRESSES BEGIN AT FFFF AND DECREMENT
configuration process is complete. Two clocks before 110413
completion, the internal logic becomes active and is reset.
On the next clock, the inputs and outputs become active as FIgure 14. ConfIguration Mode Selection
configured and consideration should be given to avoid
configuration signal contention. (Attention must be paid to
avoid contention on pins which are used as inputs during
configuration and become outputs in operation.) On the Initialization Phase
last configuration clock, the completion of configuration is
signalled by the release of the DONE I PROG pin of the When power is applied, an internal power-on-reset circuit
device as the device begins operation. This open-drain is triggered. When Vcc reaches the voltage at which the
output can be AND-tied with multiple Logic Cell Arrays and LCA begins to operate (nominally 2.5 to 3 V), the chip is
used as an active-High READY or active-Low, RESET, to initialized, outputs are made high-impedance and a time-
other portions of the system. High during configuration out is initiated to allow time for power to stabilize. This
(HOC) and low during configuration (LDC), are released time-out (11 to 33 ms) is determined by a counter driven
one CCLK cycle before DONE is asserted. In master by a self-generated, internal sampling clock that drives the
mode configurations, it is convenient to use LDC as an configuration clock (CCLK) in master configuration mode.
active-Low EPROM chip enable. This internal sampling clock will vary with process,
temperature and power supply over the range of 0.5 to
As each data bit is supplied to the LCA, it is intemally 1.5 MHz. LCAs with mode lines set for master mode will
assembled into a data word. As each data word is time-out of their initialization using a longer counter (43 to
completely assembled, it is loaded in parallel into one word 130 ms) to assure that all devices, which it may be driving
of the internal configuration memory array. The last word in a daisy chain, will be ready. Configuration using
must be loaded before the current length count compare peripheral or slave modes must be delayed long enough
is true. If the configuration data are in error, e.g., PROM for this initialization to be completed.
address lines swapped, the LCA will not be ready at the
length count and the counter will cycle through an addi- The initialization phase may be extended by asserting the
tional complete count prior to configuration being "done". active-Low external RESET. If a configuration has begun,
an assertion of RESET will initiate an abort, including an
Figure 14 shows the selection of the configuration mode orderly clearing of partially loaded configuration memory
based on the state of the mode pins MO and M1. These bits. After about three clock cycles for synchronization,
package pins are sampled prior to the start of the initialization will require about 160 additional cycles of the
configuration process to determine the mode to be used. internal sampling clock (197 for the XC2018) to clear the
Once configuration is DONE and subsequent operation internal memory before another configuration may begin.
has begun, the mode pins may be used to perform data Reprogramming is initialized by a High-to-Low transition
readback, as discussed later. An additional mode pin, on RESET (after RESET has been High for at least 6~)
M2, must be defined at the start of configuration. This followed by a Low level (for at least 6 ~) on both the
package pin is a user-configurable 110 after configuration RESET and the .open-drain DONEIPROG pins. This re-
is complete. turns the LCA to the CLE~R state, as shown in Fig. 12.
2-73
XC206412018 Logic Cell Array
Master Mode significant bit of each byte, normally DO, is the next bit in the
serial stream.
In Master mode, the Logic Cell Array automatically loads
the configuration program from an external memory de- Addresses supplied by the Logic Cell Array can be se-
vice. Figure 15a shows an example of the Master mode lected by the mode lines to begin at address 0 and
connections required. The Logic Cell Array provides 16 incremented to reach the memory (master Low mode), or
address outputs and the control signals RCLK (Read they can begin at address FFFF Hex and be decremented
Clock), HOC (High during configuration) and LOC (Low (master High mode). This capability is provided to allow
during configuration) to execute Read cycles from the the Logic Cell Array to share external memory with another
external memory. ParallelS-bit data words are read and device, such as a microprocessor. For example, if the
internally serialized. As each data word is read, the least processor begins its execution from Low memory, the
OPTIONAL
5kll DoUT DAISY-CHAINED
LCAs WITH DIFFERENT
M2 CCLK CONFIGURATIONS
HOC
GENERAL- A15
PURPOSE RCLK AU
USER 110
PINS
A13 EPROM
A12 OR~~G6ER)
} OTHER A11
VO PINS
A1a A1a
RESET A9 A9
07 A6 A8
LeA
D6 A7 A7
D5 AS A6
D4 A5 A5
03 A4 A4
02 A3 A3
D1 A2 A2
DO A1 A1 01
AO AO
LDC OE
DONE Dip CE
cd
DATA BUS
Figure 15a. Master Parallel Mode. Configuration data are loaded automaticaly from an external byte wide PROM.
An XC2000 LDC signal can provide a PROM inhibit as the user lias become active.
2-74
Logic Cell Array can load itself from High memory and Figure 16 shows the peripheral mode connections.
enable the processor to begin execution once configura- Processor Write cycles are decoded from the common
tion is completed. The Done/PROG output pin can be assertion of the active-Low write strobe (IOWRT), and two
used to hold the processor in a Reset state until the Logic active-Low and of the active-High chip selects (CSO CS1
Cell Array has completed the configuration process CS2). If all these signals are not available, the unused
inputs should be driven to their respective active levels.
The Master Serial mode uses serial configuration data, The Logic Cell Array will accept one bit of the configuration
synchronized by the rising edge of CCLK, as shown in program on the data input (DIN) pin for each processor
Figure 15b. Write cycle. Data is supplied in the serial sequence
described earlier.
Peripheral Mode (Bit Serial) Since only a single bit from the processor data bus is
loaded per cycle, the loading process involves the pro-
Peripheral mode provides a simplified interface through cessor reading a byte or word of data, writing a bit of the
which the device may be loaded as a processor peripheral. data to the Logic cell Array, shifting the word and writing a
• IF READBACK IS
ACTIVATED, A
5·kO RES ISTOR IS
REOUIRED IN -=i::-
.
I I +r II
SERIES WITH M1 MO M1 PWRDWN
DURING CONFIGURATION
THE 5 kO M2 PULL·DOWN
RESISTOR OVERCOMES THE
. '-- - DOUT
OPTIONAL
___ DAISY·CHAINED
LCA.WITH
INTERNAL PULL·UP.
BUT IT ALLOWS M2 TO - M2 --- 8~~~[i,EJlJATIONS
BE USER 110.
- HOC
--< LDC
GENERAL·
PURPOSE
USER VO
PINS -
-
}~"
110 PINS
LCA
OPTIONAL
- Wfr~1~~:~ICAL
--- CONFIGURATIONS
+5V
r
CCLK
SERIAL
LDC CE CEO P---~ MEMORY
r- DIP
~C1736A1XC1765
DONE-
:
....
.... (HIGH RESETS THE XC1736A1XC1765 ADDRESS POINTER)
"~~
'~~
(OUTPUT)
X1013
Figure 15b. Master Serial Mode. The one time programmable XC1736A Serial Configuration PROM
supports automatic loading of configuration programs up to 36 Kbits. Multiple XC1736As can be cascaded to
support additional LCAs. An XC2000 LOC signal can provide an XC1736A inhibit as the user IIOs become active.
2-75
XC206412018 Logic Cen Array
bit until all bits of the word are written, then continuing in LCA in the chain, and the clock is supplied by the lead
the same fashion with the next word, etc. After the device, which is configured in master or peripheral mode.
configuration program has been loaded, an additional After the configuration program has been loaded, an
three clocks (a total of three more than the length count) additional three clocks (a total of three more than the
must be supplied in order to complete the configuration length count) must be supplied in order to complete the
process. When more than one device is being used in the configuration process.
system, each device can be assigned a different bit in the
processor data bus, and multiple devices can be loaded on Daisy Chain
each processor write cycle. This "broadside" loading
method provides a very easy and time-efficient method of The daisy-chain programming mode is supported by Logic
loading several devices. Cell Arrays in all programming modes. In master mode
and peripheral mode, the LCA can act as a source of data
Slave Mode and control for slave devices. For example, Figure 18
shows a single device in master mode, with 2 devices in
Slave mode, Figure 17, provides the simplest interface for slave mode. The master mode device reads the external
loading the Logic Cell Array configuration. Data is sup- memory and begins the configuration loading process for
plied in conjunction with a synchronizing clock. For each all of the devices.
Low-to-High input transition of configuration clock (CCLK),
the data present on the data input (DIN) pin is loaded into The data begin with a preamble and a length count which
the internal shift register. Data may be supplied by a are supplied to all devices at the beginning of the configu-
processor or by other special circuits. Slave mode is used ration. The length count represents the total number of
for downstream devices in a daisy-chain configuration. cycles required to load all oft he devices in the daisy chain.
The data for each slave LCA are supplied by the preceding After loading the length count, the lead device will load its
:"1
PURPOSE
USER 110
PINS
CSl
va PINS
CS2
DONE DIP
RESET RESET
WRT
CSO
CSI
CS2
CCLK
(OUTPUT)
DIN
DOUT
(OUTPUT)
1104 1SA
Figure 16. Peripheral Mode. Configuration data are loaded using serialized data from a microprocessor.
2-76
E:XJUNX
configuration data while providing a High DOUT to down- tion is complete to allow time for stabilization before it is
stream devices. When the lead device has been loaded connected to the internal circuitry.
and the current length count has not reached the full value,
memory access continues. Data bytes are read and SPECIAL CONFIGURATION FUNCTIONS
serialized by the lead device. The data are passed through
In addition to the normal user logic functions and inter-
the lead device and appear on the data out (DOUT) pin in
connect, the configuration data include control for several
serial form. The lead device also generates the configura-
special functions:
tion clock (CCLK) to synchronize the serial output data. A
master mode device generates an internal CCLK of
• Input thresholds
8 times the EPROM address rate, while a peripheral mode
• Readback disable
device produces CCLK from the chip select and write
strobe timing. • Reprogram
• DONE pull-up resistor
Operation
Each of these functions is controlled by a portion of the
configuration program generated by the XACT Develop-
When all of the devices have been loaded and the length
ment System.
count is complete, a synchronous start-up of operation is
performed. On the clock cycle following the end of loading,
the internal logic begins functioning in the reset state. On
the next CCLK, the configured output buffers become
Input Thresholds
During configuration, all input thresholds are TTL level.
II
active to allow signals to stabilize. The next CCLK cycle During configuration input thresholds are established as
produces the DONE condition. The length count control of specified, either TTL or CMOS. The PWRDWN input
operation allows a system of multiple Logic Cell Arrays to threshold is an exception; it is always a CMOS level input.
begin operation in a synchronized fashion. If the crystal The TTL threshold option requires additional power for
oscillator is used, it will begin operation before configura- threshold shifting.
+5V • IF READBACK IS
ACTIVATED. A
5-kn RESISTOR IS
REQUIRED IN SERIES
wrrHM1
MICRO 5kn
COMPUTER
OPTIONAL
STRB CCLK M2 DAISY-CHANED
_ LCAs WITH DIFFERENT
DO DIN DOUT CONFIGURATIONS
D1 HDC
YO LDC GENERAL-
D2 PURPOSE
PORT
USER 1/0
D3 LCA PINS
D4
D5 OTHER {
1/0 PINS
D6 DIP
D7
RESET
11041SA
Figure 17. Slave Mode. Bit-serial configuration data are read at rising edge of the CCLK. Data on DOUr are
provided on the falling edge of CCLK. Identically configured non-master mode LCAs can be configured in parallel
by connecting DINs and CCLKs.
2-77
XC206412018 Logic Cell Array
Readback guarantees that the LCA will return to the Clear state.
Either of these methods may be needed in the event of an
After a Logic Cell Array has been programmed, the con- incomplete voltage interruption. They are not needed for a
figuration program may be read back from the device. normal application of power from an off condition.
Readback may be used for verification of configuration,
and as a method of determining the state of intemallogic DONE Pull-up
nodes during debugging. Three readback options are
provided: on command, only once, and never. The DONE I PROG pin is an open drain I/O that indicates
programming status. As an input, it initiates a reprogram
An initiation of readback is produced by a Low-to-High operation. An optional internal pull-up resistor maybe
transition of the MO I RTRIG (read trigger) pin. Once the enabled.
readback command has been given, CCLK is cycled to
read back each data bit in a format similar to loading. After Battery Backup
two dummy bits, the first data frame is shifted out, in
inverted sense, on the M11 RDATA (read data) pin. All Because the control store of the Logic Cell Array is a
data frames must be read back to complete the process CMOS static memory, its cells require only a very low
and return the mode select and CCLK pins to their normal standby current for data retention. In some systems, this
functions. Readback data includes the state of all internal low data retention current characteristic facilitates pre-
storage elements. This information is used by the Logic serving configurations in the event of a primary power loss.
Cell Array development system In-Circuit Debugger to The Logic Cell Array has built in power-down logic which,
provide visibility into the internal operation of the logic when activated, will disable normal operation of the device
while the system is operating. To read back a uniform time and retain only the configuration data. All internal opera-
sample of all storage elements, it may be necessary to tion is suspended and all output buffers are placed in their
inhibit the system clock. high impedance state.
2-78
-H-
. . .
T
+5V
+5V +5V
5kil l+ - M2
1 I
MO M1 PWRDWN
CCLK
DOUT
!---- ~
I I !
MO M1 PWRDWN
CCLK
DIN
LCA
DOUT
5kil
-il
...
-
I I
CCLK
DIN
LCA
L
MO r,.t1 PWRDWN
DOUT
5kil
I-
SLAVE #1 SLAVE #n
- HDC M2 .... M2 ~
~ D7
MASTER
A9
AS
A9
AS
- r<
DIP
RESET
-
r<
DIP
RESET
V-- D6 A7 A7 D7
"
V--
V--
D5
D4
AS
AS
AS
AS
D6
S
OPEN
,--+5 V
5kil
Figure 18. Master Mode Configuration with Daisy.Chained Slave Mode Devices.
All are configured from the common EPROM source. A well defined termination of
SYSTEM RESET is needed when controlling multiple LCAs.
Any XC3000 slave driven by an XC2000 master mode device must use "early DONE and early internal reset".
(The XC2000 master will not supply the extra clock required by a "late" programmed XC3000_)
2-79
XC206412018 Logic Cell Array
the clock during data transitions. Because of the short Logic Block Performance
loop delay characteristic in the LCA device, the I/O block
flip-flops can be used very effectively to synchronize Logic block propagation times are measured from the
external signals applied to the device. Once synchronized interconnect point at the input of the combinatorial logic to
in the I/O block, the signals can be used internally without the output of the block in the interconnect area. Com-
further consideration of their clock relative timing, except binatorial performance is independent of logic function
as it applies to the internal logic and routing path delays. because of the table look-up based implementation.
Timing is different when the combinatorial logic is used in
Device Performance conjunction with the storage element. Forthe combinato-
rial logic function driving the data input of the storage
The single parameter which most accurately describes the element, the critical timing is data set-up relative to the
overall performance of the Logic Cell Array is the maxi- clock edge provided to the storage element. The delay
mum toggle rate for a logic block storage element config- from the clock source to the output of the logic block is
ured as a toggle flip-flop. The configuration for determin- critical in the timing of signals produced by storage ele-
ing the toggle performance of the Logic Cell Array is shown ments. The loading on a logic block output is limited only
in Figure 19. The clock forthe storage elementis provided by the additional propagation delay of the interconnect
by the global clock buffer and the flip-flop output Q is fed network. Performance of the logic block is a function of
back through the combinatorial logic to form the data input supply voltage and temperature, as shown in Figure 22 .
forthe next clock edge. USing this arrangement, flip-flops
in the Logic Cell Array can be toggled at clock rates from Interconnect Performance
33-70 MHz, depending on the speed grade used.
Interconnect performance depends on the routing re-
Actual Logic Cell Array performance is determined by the source used to implement the signal path. As discussed
critical path speed, including both the speed of the logic earlier, direct interconnect from block to block provides a
and storage elements in that path, and the speed of the minimum delay path for a signal.
particular network routing. Figure 20 shows a typical
system logic configuration of two flip-flops with an extra The single metal segment used for long lines exhibits low
combinatorial level between them. Depending on speed resistance from end to end, but relatively high capa-
grade, system clock rates to 35 MHz are practical for this citance. Signals driven through a programmable switch
logic. To allow the user to make the best use of the will have the additional impedance of the switch added to
capabilities of the device, the delay calculator in the XACT their normal drive impedance.
Development System determines worst-case path delays
using actual impedance and loading information. General-purpose interconnect performance depends on
the numberof switches and segments used, the pre-sence
of the bidirectional repowering buffers and the overall
loading on the signal path at all points along the path. In
calculating the worst-case delay for a general interconnect
path, the delay calculator portion of the XACT develop-
ment system accounts for all of these elements. As an
approximation, interconnect delay is proportional to the
summation of totals of local metal segments beyond each
programmable switch. In effect, the delay is a sum of
R-C delays each approximated by an R times the total C
it drives. The R of the switch and the C of the interconnect
are functions of the particular device performance grade.
For a string of three local interconnects, the approximate
o Q 1--_-:'-_ X,V delay at the first segment, after the first switch resistance,
K-4·:-----------~ would be three units; an additional two delay units after the
next switch plus an additional delay after the last switch in
the chain. The interconnect R-C chain terminates at each
repowering buffer. Nearly all of the capacitance is in the
110421 interconnect metal and switches; the capacitance of the
block inputs is not significant. Figure 21 shows an esti-
Figure 19. Logic Block Configuration for mation of this delay.
Toggle Rate Measurement
2-80
~XIIJNX
COMBINATORIAL CLB
DESTINATION CLB
0···················_·-
INPUTS o D
GLOBAL
II
CLOCK
1104 22
SWITCH
• ___ . ___ /MATRIX ........... ___ . __ _
CLB R1 I : R3
TIMING: INCREMENTAL
~
IF R1 = R2 = R3 = RAND C1 = C2 = C3 = C +R3C3
THEN CUMULATIVE TIMING
T1 =3RC T2 = 3RC + 2RC T3 = 3RC + 2RC + 1RC 6AC + BUFFER
=3RC =5RC =6RC
110523B
Figure 21. Interconnection Timing Example. Use of the XACT timing calculator
or XACT-generated simulation model provides actual worst-case performance information.
2-81
XC206412018 Logic Cell Array
1.00
0.80
TYPICAL COMMERCIAL
(+ 5.0 v, 25'C)
•
TYPICAL MILITARY
0.40 •
MIN COMMERCIAL ~.~; ~ •• llIttl.M!IJ1.AFY i 4X'l ••• -:
N MME IAL· ••• ---.
MI ••• _ _ ••• - - -. MIN MII;!'0£lY i 5"S}2 -. -.'
I
.--- ---------------
____ - - - - - - - - - - - - - ---------------
0.20
t:::~~:·-·-·--········-
TEMPERATURE ('G)
X1045
Figure 22. Relative Delay as a function of Temperature, Supply Voltage and Processing Variations.
2-82
100
90
80
L 70
60
/ 50
/ 40
150
/ 30
V
10 0 / / 20
V /
0
V
/
/ ./
/
/ /
/ 10
9
40
./ ./ ./
0 / ./
(mW)
20 ./
/
./
/
/
/ (rnA)
II
/ V L /
V V
/
0
/ / /
V
/ 2
V V
/ /
V }/ /
/ / / / .9
L ./ .8
20 CLB OUTPUTS 4
3 LOCAL SEGMENTS
I ./ L ./ .7
EACH 3 ./ V ./ .6
./ ./ L .5
/ / V
2 .4
/ / V .3
.I
(3mWIMHz)
V
GLOBAL CLOCK
BUFFER
/ V
/ .2
/
(1.25 mWIMHz)
1110 OUTPUT
(50pF) 0.5
.I
0.5 "
1
/ 2 10 20 30 40 50
.1
FREQUENCY MHz
(0.4 mWIMHz) /
1 CLB OUTPUT
3 LOCAL 110427
INTERCONNECT
2-83
XC2064/2018 Logic Cell Array
DEVELOPMENT SYSTEMS
PIN DESCRIPTIONS
To accomplish hardware development support for the
Logic Cell Array, Xilinx provides a development system Permanently Dedicated Pins.
with several options to support added capabilities. The
Vee
XACT system provides the following: One or two (depending on package type) connections to
the nominal +5 V supply voltage. All must be connected.
• Schematic entry
• Automatic place and route GND
• Interactive design editing for optimization One or two (depending on package type) connections to
• Interactive timing calculations ground. All must be connected.
• Macro library support, both for standard Xilinx
supplied functions and user defined functions PWRDWN
• Design entry checking for consistency and A Low on this CMOS-compatible input stops all internal
completeness activity, but retains configuration. All flip-flops and latches
are reset, all outputs are 3-stated, and all inputs are
• Automatic design documentation generation
interpreted as High, independent of their actual level.
• PROM programmer format output capabilities
While PWRDWN is Low, Vcc may be reduced to any value
• Simulation interface support including automatic
>2.3 V. When PWDWN returns High, the LCA becomes
nellist (circuit description) and timing extraction operational with DONE Low for two cycles of the internal
• Logic and timing simulation 1-MHz clock. During configuration, PWRDWN must be
• In-circuit design verification for multiple devices High. If not used, PWRDWN must be tied to Vcc'
2-84
l::XIUNX
DONE XTL1
DON E is an open-drain output, configurable with or with- This user 1/0 pin can be used to operate as the output of
out an internal pull-up resistor. At the completion of an amplifier driving an external crystal and bias circuitry.
configuration, the LCA circuitry becomes active in a syn-
chronous order, and DONE is programmed to go active XTL2
High either one cycle before or after the outputs go active. This user 1/0 pin can be used as the input of an amplifier
connected to an external crystal and bias circuitry. The
PROG
1/0 Block is left unconfigured. The oscillator configuration
Once configuration is done, a High-to-Low transition of
is activated by routing a net from the oscillator buffer
this pin will cause an initialization of the LCA and start a
symbol output and by the MAKEBITS program.
reconfiguration.
MO
CSO,CS1,CS2,VVRT
These four inputs represent a set of signals, three active
As Mode 0, this input and M1, M2 are sampled before the
Low and one active High, that are used to control
start of configuration to establish the configuration mode to
configuration-data ehtry in the Peripheral mode.
be used.
Simultaneous assertion of all four inputs generates a
RTRIG
A Low-to-High input transition, aiter configuration is com-
plete, acts as a Read Trigger and initiates a Readback of
Write to the internal data buffer. The removal of any
assertion clocks in the 00-07 data. In Master mode,these
pins become part of the parallel configuration byte, 04,03,
II
configuration and storage-element data clocked by CCLK. 02, 01. After configuration, these pins are user-
By selecting the appropriate Readback option when gen- programmable 1/0 pins.
erating the bitstream, this operation may be limited to a
single Readback, or be inhibited altogether.
RCLK
During Master parallel mode configuration RCLK repre-
sents a "read" of an external dynamic memory device
M1
(normally not used).
As Mode 1, this input and MO, M2 are sampled before the
start of configuration to establish the configuration mode to
00-07
beused. If Readback isneverused, M1 can be tied directly
This set of eight pins represents the parallel configuration
to ground or Vee' If Readback is ever used, M1 must use
byte for the parallel Master mode. After configuration is
a 5-kQ resistor to ground or Vee' to accommodate the
complete they are user programmed 1/0 pins.
RDATA output.
AO-A15
ROATA
During Master Parallel mode, these 16 pins present an
As an active Low Read Data, after configuration is
address output for a configuration EPROM. After configu-
complete, this pin is the output of the Readback data.
ration, they are user-programmable 1/0 pins.
User 1/0 Pins that can have special functions.
DIN
M2 During Slave or Master Serial configuration, this pin is
During configuration, this input has a weak pull-up resistor. used as a serial-data input. In the Master or Peripheral
Together with MO and M1, it is sampled before the start of configuration, this is the Data 0 input.
configuration to establish the configuration mode to be
used. After configuration, this pin is a user-programmable OOUT
1/0 pin. During configuration this pin is used to output serial-
configuration data to the DIN pin of a daisy-chained slave.
HOC
During configuration, this output is held at a High level to
TCLKIN
This is a direct CMOS level input to the global clock buffer.
indicate that configuration is not yet complete. After
configuration, this pin is a user-programmable 1/0 pin.
Unrestricted User 1/0 Pins.
1/0
LOC
An I/O pin may be programmed by the user to be an Input
During Configuration, this output is held at a Low level to
or an Output pin following configuration. All unrestricted
indicate that the configuration is not yet complete. After
1/0 pins, plus the special pins mentioned on the following
configuration, this pin is a user-programmable 1/0 pin.
page, have a weak pull-up resistor of 40 to 100 kQ that
LDC is particularly useful in Master mode as a Low enable
becomes active as soon as the device powers up, and
foran EPROM, but it must then be programmed as a High
stays active until the end of configuration.
after configuration.
2-85
XC206412018 Logic Cell Array
GNC B6 GND
A6
A6 (Ol 3 B5
A12 (0) 4 AS
..<~~IGH~~. 5 B4 VO
A; 0) 6 A4
A8 (0) B3
A10 (0) A3
A9 (D)
PWRDWI'I B2 PWRDWN
C2
9 13 C1
~~~:~~~~.
D2
110
••••••••••••••••••• 16 E2
E'
VC 12 F2 VC
13 F1
G2
14 G1
. ~<H.I.GH>.~. H2
110
15 23 H'
16 24 J2
,:M1(LO""
MO (HIGH MO 18 26 RTRIGiIl
:::::::::.M2 .ow 19 27 K2
HOC HIG 20 2B L2
,<HII lH»' : 110
lOlo LVW)
22
. «HIGH»
23
GND 24 GND
. «H.I.GH~~.
DONE,
.. :. . :,.: .•••••·I •••••. j :
25
26
27
31
32
34
38
39
40
41
42
43
44
45
47
48
K8
L8
K9
L9
L10
K10
J1'
110
<TL2 OR lie
RESEl
!'ROOiIl
DAlia
49 110
I 35 50
36 51
52 vce
53
.<.<HI(j.H>~. 0< 37 54 010
55 E1
11.0
I I
m: 39 57
I ',". 40 58 C11
~~HiGH A3 46 64 A9 va
A15 65 B8
A4 47 66 A8
A14 6) Bl
AS
11042M
2-86
USER
OPERATION
••••••••••••••••••••••••••••• 3 5 1 C5
I/O
• 1 A2
10 1 B3
(0) • 1 Al
1012 1 B2
13 1 C2
15 1 Dl I/O
,. 1 E3
26
,HIGH» I/O
26 ~~~~~:~I
II
I 27 33 1K2
2. ~34 1 K3
112_
11O
I ··.~~HIG~~' 3. 1J5
35 43 IJ6 GND
«HIGfb, 3• • 47 1L6
1L6 I/O
110
51 . 63 1G9
52~ ~M 1 F9
! D1 I/O
60
I/O
A4 " 80 ,AS
A14 67 ., 'B6
, B7.
••••••••••••••••••••••
«HIGH» IS HIGH IMPEDANCE WITH A 20-50 kn INTERNAL PULL-UP DURING CONFIGUJ'lATION
110429A
2-87
XC206412018 Logic Cell Array
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings
conditions for extended periods of time may affect device reliability.
OPERATING CONDITIONS
Vec Supply voltage relative to GND Commercial O°C to +70°C 4.75 5.25 V
2-88
DC CHARACTERISTICS OVER OPERATING CONDITIONS
VOH High-level output voltage (@ IOH =-4.0 ma Vcc min) Commercial 3.86 V
VOH High-level output voltage (@ IOH =-4.0 ma Vcc min) Industrial 3.76 V
Military
VOL Low-level output voltage (@ h =4.0 ma Vcc max) 0.37 V
2-89
XC206412018 Logic Cell Array
INPUT (A,B,C,D)
x x
~G)TILO~
OUTPUT (X,Y)
(COMBINATORIAL) XX
OUTPUT (X,V)
(TRANSPARENT LATCH)
I--- CD
® TITO
TICK
ruo TCKI4
CLOCK(K)
J
1---0 Tlcc CD TCCI--II
CLOCK (C)
CLOCK (G)
J 1+-0 TCKO~
@Tcco~
@ TCIO----to
t:=@TCH
110430
2-90
CLB SWITCHING CHARACTERISTIC GUIDELINES (Continued)
•
TCKI
C Clock To output 10 Tcco 19 13 9 ns
Logic-input setup 5 Tlcc 8 6 5 ns
Logic-input hold 6 TCCI 0 0 0 ns
Notes: 1. All switching characteristics apply to all valid combinations of process, temperature and supply with a
nominal chip power dissipation of 250 mW.
• These parameters are for clock pulses generated within a CLB. For an externally generated pulse, derate these
parameters by 20%.
2-91
XC206412018 Logic Cell Array
PAD
(PACKAGE PIN) (IN) J ~ (OUT) )00
0 Top:j
OUTPUT SIGNAL ~
I+- (DTPIO-1 0- TTHZ J.-
INPUT
(DIRECT) XXX 1 3-STATE
0 TpL 0 TLP
~
J
L
(1/0 CLOCK)
1
- XX @TLlr,::
• IG)TLW
INPUT
(REGISTERED) \\~
2-92
GENERAL LCA SWITCHING CHARACTERISTIC
__--II
Vee (VALID)
MOIM11M2
OONEIPROG
~_0TPGW=r
USERVO ~'-IN_IT_IA_l_IZA
=1__
USER STATE __Tl_ON__
ST_A_TE_________________
J=@TeLH ~ @TeLL
CLOCK
110432
Notes: 1. At power-up, Vee must rise from 2.0 Volts to Vee min in less than 25 ms. If this is not possible, configuration
can be delayed by holding ~ Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a
non-monotonically rising Vee may require a RJ:SET pulse (High-to-Low-to-High) of >6 ~s duration after Vee has
reached 4.0 V.
2. ~ timing relative to power-on and valid mode lines (MO, M1, M2) is relevant
only when RESET is used to delay configuration.
3. Minimum CLOCK widths for the auxiliary buffer are 1.25 times the TeLH. Tell.
4. After RESET is High, RESET = DIP = Low for 6 ~ will abort to CLEAR.
2-93
XC206412018 Logic Cell Array
CCLK
(OUTPlJT)
SERIAL DATA IN
SERIAL DOUT
(OUTPUT) _ _ _ _ _- 1 ' - - _ _ _ _ _...1 ' -_ _ _ _ _- - ' ' - -_ _ _ _ _ _ __
110529
Notes: 1. At power-up, Vee must rise from 2.0 Volts to Vee min in less than 25 ms. If this is not possible, configuration ean be de-
layed by holding RESET Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vee may require a I1:ESI:T pulse (High-to-Low-to-High) of >6 fls duration after Vee has reached 4.0 V.
2. Master-serial-mode timing is based on slave-mode testing.
2-94
MASTER PARALLEL MODE PROGRAMMING SWITCHING CHARACTERISTICS
AO-A15 WWVW
(OUTPUT) ~_ _ _ _ _ _ _ _ _ _ _ _ _--J 14----14---~
00-D7
RClK
(OUTPUT)
CClK
(OUTPUT)
OOUT
(OUTPUT)
BYTE n-1
II
1104 33
Note: 1. CCLK and DOUT timing are the same as for slave mode.
2. At power-up, Vee must rise from 2.0 Volts to Vee min in less than 25 ms. If this is not possible, configuration can be de-
layed by holding RESET Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vee may require a RESET pulse (High-to-Low-to-High) of >6 !J,S duration after Vee has reached 4.0 V.
This timing diagram shows that the EPROM requirements are extremely relaxed: EPROM access time can be longer than
4000 ns, EPROM data output has no hold time requirement
2-95
XC2064/2018 Logic Cell Array
CSO
CS2
CCLK (2)
(OUTPUl)
DIN
DOUT(2)
(OUTPUl)
1104 34
Controls 1 Active (last active 1 TeA 0.25 5.0 0.25 5.0 0.25 5.0 Ils
(CSO, CS1, input to first inactive)
CS2, WRT)
Inactive (first inactive 2 Tel 0.25 0.25 0.25 !lS
input to last active)
CCLK2 3 Tccc 75 75 75 ns
DIN setup 4 T De 50 50 50 ns
DIN hold 5 TeD 0 0 0 ns
Notes: 1. Peripheral mode timing determined from last control signal of the logical AND of (GSO, CST, GS2, WFiT) to transition to
active or inactive state.
2. GGLK and DOUT timing are the same as for slave mode.
3. At power-up, Vee must rise from 2.0 Volts to Vee min in less than 25 ms. If this is not possible, configuration can be de-
layed by holding RESET Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vee may require a RESET pulse (High-to-Low-to-High) of >6 j.J.s duration after Vee has reached 4.0 V.
2-96
SLAVE MODE PROGRAMMING SWITCHING CHARACTERISTICS
CCLK To DOUT
DIN setup
DIN hold
High time
Low time
Frequency
3
1
2
4
5
Tcco
T Dcc
TCCD
TCCH
TCCl
Fcc
10
40
0.25
0.25
65
5.0
2
10
40
0.25
65
0.25 5.0
2
10
40
0.25
0.25
65
5.0
2
Note: At power-up, Vec must rise from 2.0 Volts to Vec min in less than 25 ms. If this is not possible, configuration can be de-
ns
ns
ns
/-ts
/-ts
MHz
•
layed by holding RESET Low until Vec has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vec may require a RESET pulse (High-to-Low-to-High) of >6 f1S duration after Vee has reached 4.0 V.
DONE/PROG
(OUTPUn
----~------------------------------------
CD TORT ~....-@ TRTH
Ir-~~--~h-~------------------
RTRIG
CCLK(1)
RDATA
(OUTPUn
1104 36
Notes: 1. CCLK and DOUT timing are the same as for slave mode.
2. DON ElPROO output/input must be HIGH (device programmed) prior to a positive transition of RTRIG (MO).
2-97
Component Selection,
Ordering Information,
& Physical Dimensions
XC2064
XC201a
XC3020
XC3030 1--'-'+-"";;';"_
XC3042
XC3064
XC3090
X1104
JTTL
Note, however, that the XC2000 and XC3000 families
Example: XC2064-70PC68C
differ in the position of XTL 1 as weil as three parallel
" '.. T,~ T T...
Range
_w. address bits (6, 7 and 11) and most of the data pins used
in parallel master mode.
XC2018 and XC3020 are not available in PGA68, since
Toggle Number of Pins
Rate the PGA84 is the same size and offers more I/O.
Note that a PLCC in a socket with PGA footprint generates
Package Type a printed circuit board pin-out differentfrom a PGA device.
2-98
l:XlUNX
PGA PIN-OUTS
I 2 3 4 5 6 7 8 9 10 II II 10 9 8 7 6 5 4 3 2 1
A (Ag \ rAlO\ rAm rAm rAiS\ rA5\ rM\ 1A3'\ fAi\ A A fAi\ iA3\ rM\ rA5\ rAiS\ rAm rAm rAIO\ fA9\
~~~~~~~~~
"A
~~~~~~~~~
B 0@@@@S(@@)@@8 B B 8@@@)(@S@@@@0 B
c OOEB ®@ c c @@ EBOO c
D 00 ®~ D D ~® 00 D
E 0 0 uOlP V~l§:W ~
0 E OOI/D02 E 0 ~ 18l0uuOM V~l§:W 00
00/02 E
FOE; 80 F F 08 80 F
G 00
Oomponent ®@ G G ®® Solder Side 00 G
H 00
Side @O H H O@ 00 H
J CIDC) @O J J O@ OCID J
K
L
®~~OC)OSOO@@~ K
~~~OOOOO®~ L
K
L
~@@OOSOOO@® K
~®OOOOO~@ L
II
2 3 4 5 6 7 8 9 10 II 11 10 9 8 7 6 5 4 3 2
PG68 Pln-outs-XC2064
2 3 4 5 6 7 8 9 10 11 II 10 9 8 7 6 5 4 3 2 I
A"@@@D®O(@O@@@€~ A A 8@@@0(@0®@D@@ A
B O@@@O@)O~@@@ B B @@@@)O(@O@@@O B
c OOEB @8@ ~~ c c ~~ @8@ EBOO c
D 00 ®O D D o ® 18l0uuOM V~IEW 00 D
E 000 uOP V~[EW OO@ E E @OO 000 E
F 008 800 F F 008 Solder Side 800 F
GOOO Oomponent @O@) G G @O@ 000 G
H 00 Side ®O H H O@ 00 H
J OCID OSO ~O J J O~ 080 (IDO J
K O@@OOOOO®@@ K K @@®OOOOO@@O K
L ®()~OOOOOO@~ L L ~@OOOOOO~O® L
I 2 3 4 5 6 7 8 9 10 II II 10 9 8 7 6 5 4 3 2 I
EEl • Index pin which mayor may not be electrically connected to pin C2
unlabeled pin - unrestricted VO pin
PG84 Pln-outs-XC2018
2-99
XC206412018 Logic Cell Array
PHYSICAL DIMENSIONS
I~ 0.550 ~I
~~~~~~~~~
L r-
t:::J*
160
0.130
f
~0.070
<1.
DIMENSIONS IN INCHES
1'04 39
PIN1~
o.o~±~
I- 2.400 ± 0.24 1 0.100 ± 0.025
,
0.610 ± 0.010
1'04 40
DIMENSIONS IN INCHES
2-100
PHYSICAL DIMENSIONS (Continued)
61
0.045
PWRDWN CCLK
DOUT/IO
0.990
±0.005
0.954 Vcc Vcc 0.20
±0.004 ±0.010
1~: ,'~ i
0.Q18
--.i.. LEAD PITCH
T 0.050 TYPICAL
LEAD CO-PLANARITY
0.028 =!==t:=I!:::::l=.--L-
±0.002
III
[t
DIMENSIONS
11·~0.954±0.004 ~I IN INCHES
~0.990±0.005===:J1
o.045
0.100±0.010
TOP VIEW
0.175±o.o10
SJA= 35-40 °CIW
1.000± 0.12
1+--------1.100±O'012SO. -------~
I---- O.100TYP
0.100
t"\ r. TVP
G
t\ rt\
V
r. 1.000
±O.Ot
r
\.
INDEX PIN
'- \. '+' \.
10 11
DIMENSIONS IN INCHES
1104 42
2-101
XC206412018 Logic Cell Array
0.045 x 45'",,-
11
L
I'L.
PIN NO. 1
PIN NO.1 IDENTIFIER
75
~
PWRDWN CCLK
DOUT/IO
P
1 .190
~
±O.005
r14----1.154±0.004_~53·!11
I14.~-------1.190
33
JUUUUULJU
± 0.005--------+1-·
LEAD PITCH
0.050 TYPICAL
TOP VIEW
DIMENSIONS IN INCHES
El JA = 30-35 °eIW
El Jc= 3-7 °eIW
'105360
84-Pin PLCC Package
0.100
!I'~ r: rhr:l:\ th ffi TYP
~~ ~~ I
'-V '-V '-V '-V
I-E~ 3-
l-E~ 7
"-
1.00o
V ± 0.01 o
"-
r: f::\
'-J
'-'
/t:>. \J
10 11
BOTTOM VIEW
NOTE: INDEX PIN MAY OR MAY NOT BE
ElJA = 30-35 °cm ELECTRICALLY CONNECTED TO PIN C2.
DIMENSIONS IN INCHES
ElJC= 4-7 °cm 1105350
2-102
----------------------------------.
XC2018B 1800 100 74 17,878 DESC has assigned the XC2016B device SMD# 5962-
88638, the XC3020B device SMD# 5962-89948, the
XC3020B 2000 64 64 14,779
XC3042B device SMD# 5962-89713 and the XC3090B
XC3042B 4200 144 96 30,784 device SMD# 5962-89823. Contact your Xilinx
XC3090B 9000 320 144 64,160 representative or DESC for more information.
2-103
Military Logic Cell Arrays
Because Xilinx FPGA's are standard parts, they can be • Standard Product
stocked in inventory at Xilinx, at Xilinx distributors or at the - Reliability of hi-volume memory product
user site. One part can be stocked for multiple applica-
tions, minimizing inventory costs. Another benefit of being • Fully tested by Xilinx
a standard product is the inherent high reliability of a high - Fault coverage assured by vendor
volume memory product rather than a low volume custom
circuit. Non-recurring engineering costs (NRE) are never Security
required for a FPGA thereby providing cost effective
solutions in military volumes and allowing very inexpen- • No design information needed by manufacturer
sive design iterations. - Secure design process. Design data held to
vendor at user site.
For maximum security the configuration data may be
"down-loaded" from a remote site thereby eliminating the • Remote configuration
potential of tampering with the configuration data locally. - Ensures secure design data capability
The FPGA can be made non-volatile in this instance with
the addition of a small battery backup. Flexibility
One of the most effective advantages of the Xilinx FPGA • Standard product
is the ability to reconfigure some or all of the deviCe while - An ASIC where one spec can be used for multiple
it remains in the circuit. This opens up entirely new applications
possibilities allowing the same gates to be used by differ- - An ASIC stocked by distribution
ent functions at different times.
• Reprogrammable
IMPORTANT BENEFITS FOR MILITARY DESIGNS - Logic can be changed "on the fly"
2-104
MIL-STD-883 CLASS 8 COMPLIANCE MIL-STD-883 CLASS 8-METHOD 5005 QUALITY
CONFORMANCE INSPECTION (QCI) TESTING
Xilinx is now serving military customers in accordance with
MIL-STD-883 Class B paragraph 1.2.1 together wnh the Every lot of devices shipped to the requirements of
attendant requirements of MIL-M-3851 O. This includes fUll MIL-STD-883C is required to be qualified by four kinds of
compliance with all processing requirements of Method Quality Conformance Inspection (QCI) Tests. The QCI
5004 and all Quality Conformance Inspection (QCI) requirements specified by the Defense Electronics Supply
requirements of Method 5005 (Groups A,B,C,D). Center (DESC) undergo regular revisions. Xilinx rigor-
ously incorporates these revisions into our QCI testing in
MIL-M-38510 (as invoked by MIL-STD-883) conformance with the requirements of MIL-STD-883C.
Military Specification Microcircuits-General Specifica- These are:
tion (describes the design, processing and assembly
workmanship guidelines) Group A-Electrical tests done to data sheet limits at all
three temperatures of the military temperature range, -
MIL-STD-883 55°C to +125°C. These are performed on a sample from
Military Standards-Test Methods and Procedures for the same lot being shipped.
Microelectronics (delineates the detailed testing and
inspection methods for military integrated circuits) Group 8-Mechanical tests performed on a sample of
devices of the same device/package type assembled
II
MIL-STO-B83 Class B-Method 5004 Processing Flow within the same 6 week widow of the lot being shipped.
This group consists of upto 8 subgroups including physical
METHOD CONDo dimensions, mark permanency, solderability, internal vis-
FULL TRACEABILITY ual/mechanical, bond strength, internal water vapor con-
tent, fine & gross leak, and ESD sensitivity.
XILINX SPECIFICATION
Group c-Package related reliability tests performed on
a sample of devices made with die from the same 1 year
20 1OIB window. This group consists of up to 2 subgroups includ-
ing (1) life testing (1000 hr at 125°C) and (2) temperature
cycling, constant acceleration, fine & gross leak, and a
10101C visual examination.
2001/E
Group D-Package related reliability tests performed on
a sample of devices made in the same package within the
same 1 year window. This group consists of up to 8
1014 subgroups: physical dimensions; lead integrity and seal;
thermal shockltemperature cycling/moisture resistance/
seallvisual; mechanical shock vibration (variable fre-
25'C
quency)/constant acceleration/seallvisual; salt atmo-
sphere/seallvisual; internal water-vapor content; adhe-
1015 sion of lead finish; lid torque.
2009
SODS
1637 01
2-105
Military Logic Cell Arrays
2-106
XC20188
Military Logic CeWMArray
The LogiC Cell™ Array (LCA) is a high density CMOS The XACT development system allows the user to define
programmable gate array. Its patented array architecture the logic functions of the device. Schematic capture is
consists of three types of configurable elements: InpuV available for design entry. while logic and timing simula-
Output Blocks, Configurable Logic Blocks and Intercon- tion, and in-circuit debugging are available for design
nect. The designer can define individual I/O blocks for verification. XACT is used to compile the data pattern
interface to external circuitry, define logic blocks to imple- which represents the configuration program. This data
ment logic functions and define interconnection networks can then be converted to a PROM programmer format file
to compose larger scale logic functions. to create the configuration program storage.
The Logic Cell Array's logic functions and interconnec- See the XC2018 Commercial data sheet for a full descrip-
tions are determined by the configuration program stored tion.
ORDERING INFORMATION
XC2018 - 50 PG84 B
. TT~ B.MIL.STD.883,CLASSB,FULLYCOMPLIANT
TSC0026
2-107
XC2018B Military Logic Cell Array
PIN ASSIGNMENTS
I/O
I/O
I/O
2-108
E:XIUNX
t o l · - - - - - - l . l 0 0 ± 0.012 SQI-------->l'1
-- 0.100TYP
ffiffi
1.ooo± 0.01
ffirh
0.100
TVP
~~ ~~ I
'V 'V '+''+'
I-E~ fr
I-(~ fr
G I. L
1.000
±O.O1 o
./''l:!.
r.L
r:
_L
i":'.
'-'
i":'.
III
'-'
5 6 7 10 11
BOTTOM VIEW
NOTE: INDEX PIN MAYOR MAY NOT BE
ELECTRICALLY CONNECTED TO PIN C2.
DIMENSIONS IN INCHES
30 1.15k 1.5 k
715
H1
H2
J1
K1
J2
L1
NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
4.99 k RATED FOR 1/8 WATT AT1500C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LIFE.
~ CAPACITOR HAS 10% TOLERANCE.
50 V RATING WITH AN X7R
1k TEMPERATURE CHARACTERISTIC.
[!) 30 n RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 W AT 1500C WITH A
TOLERANCE OF 5%.
.01 ~F []]
TSC0026 1637 OM
2-109
XC2018B MIlHary Logic Cell Array
TEST SPECIFICATION
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Conditions
-55°C S TeS +125°C Group A
Test Symbol Vee = 5.0 V ±10% Subgroups Min Max Units
High Level Output Voltage VOH Vee = 4.5 V, IOH = -4.0 mA 1,2,3 3.7 V
Low Level Output Voltage VOL Vee = 5.5 V, IOL = 4.0 mA 1,2,3 0.4 V
Quiescent Operating leeo CMOS Inputs, Vin = Vcc = 5.5 V 1,2,3 10 mA
Power Supply Current TTL Inputs, Vin = Vcc = 5.5 V 1,2,3 15 mA
Power-Down Supply Current ICCPD Vin=~5.5V, 1,2,3 0.5 mA
PWR OW =OV
Leakage Current IlL Vee = 5.5 V, Vin = Vec and 0 V 1,2,3 -10 10 ~
Input High Level TTL VIHT Guaranteed Input High 1,2,3 2.0 V
Input Low Level TTL VILT Guaranteed Input Low 1,2,3 0.8 V
Input High Level CMOS VIHC Guaranteed Input High 1,2,3 .7Vcc V
Input Low Level CMOS VILC Guaranteed Input Low 1,2,3 .2Vcc V
DONEIPROG
Program Width (Low) TPGW 4 See Fig. 3 9,10,11 6 ~
Initialization TPGI 5 9,10,11 7 ~
PWR DWN2
Power Down Supply VpD 1,2,3 3.5 V
2-110
Conditions -33 -50 -70
-55°C ~TC ~+ 125°C Group A
Test I I
Sym Vee = 5.0 V ±10% Subgroups Min Max Min Max Min Max Units I
Switching Characteristics, Peripheral Mode Programming
CCLK5 3 9,10,11 75 75 ns
DIN Setup 4 9,10,11 50 50 ns
DIN Hold 5 9,10,11 5 5 ns
......}...••..•....
l°l~
CCLK,
RTRIG Setup TRTCC 2 9,10,11 100 100 ".,." ns
RDATA Delay TCCRO 3 9,10,11 100 100 •...11 ns
Benchmark Patterns7
T88
9,10,11
9,10,11
318
274
269
204
5
..•.••" .•.
i83
;:::::;::
141
:::;:::::
ns
ns
TSC0026
2-111
XC2018B Military Logic Cell Array
K Clock,
To Output TCKO 9 N/A 20 15 ns
~t
I;,;,)
Logic-Input Setup TICK 3 N/A 12 8 ns
Logic-Input Hold N/A Ii';'"
TCKI 4 1 1 ns
C Clock,
To Output
Logic- Input Setup
Tcco 10
Tlcc 5
N/A
N/A 12
25
9
19
~. •••.•• ~3 ns
ns
Logic-Input Hold TCCI 6 N/A 6 1 I· ns
1:; I'
I:~o
Logic Input to G Clock, ";';';';'
To Output TclO 11 N/A 37 27 ns
N/A
~
Logic-Input Setup TICI 7 6 4 ns
Logic-Input Hold TCII 8 N/A 9 5 ; ns
TSC0026
2-112
Conditions -33 -50 -70
-55°C ~TC ~+ 125°C Group A
Test I
Sym Vee = 5.0 V ±10% Subgroups Min Max Min Max Min Max UnitsI I
Application Guidelines, Switching, IOB7
I/O Clock
To Input (Storage) N/A 20 15 ns
To Pad-Input Setup N/A 12 8 ns
To Pad Input Hold N/A o o ns
Pulse Width N/A 12 9 ns
Frequency N/A 33 50 MHz
Output,
To Pad (Output Enable) N/A 15 12 ns
II
Three-State,
To Pad Begin hi-Z N/A 25 20 ns
To Pad End hi-Z N/A 25 20 ns
RESET,
To Input (Storage) N/A 40 30 25 ns
To Input Clock N/A 35 25 20 ns
CCLK,
To DOUT N/A 100 100 100 ns
DIN Setup N/A 10 10 10 ns
DIN Hold N/A 40 40 40 ns
High Time N/A 0.5 0.5 0.5..\> f-Ls
Low Time N/A 0.5 1.0 0.5 1.0 0.$. J.O f-Ls
Frequency N/A 1 1 1 MHz
RCLK,
From Address Invalid TARC 1 See Fig. 5 N/A o 0 ns
To Address Valid T RAC 2 N/A 200 200 ns
To Data Setup TDRC 3 N/A 60 60 ns
To Data Hold T RCD 4 N/A o 0 ns
RCLK High T RCH 5 N/A 600 600 ns
RCLKLow T RCL 6 N/A 4.0 4.0 f-LS
-'-
Application Guidelines, Switching, General LCA7
RESET'O
::\.,.,: .,.....
M2, M1, MO Setup TMR 1 See Fig. 3 N/A 1 1 1 f-Ls
M2, M1, MO Hold TRM 2 N/A 1 1 1 f-Ls
Width (Low) TMRW 3 N/A 150 150 150 ns
2-113
XC2018B Military Logic Cell Array
INPUT (A,B,C,D)
x x
~CDTllO~
OUTPUT (X,V)
(COMBINATORIAL) XXX
® TITO
OUTPUT (X,V)
(TRANSPARENT LATCH)
~0TICK
xx:CD TCKI -
CLOCK(K) Jr-
~®TICC ® Tccl -
CLOCK (C) ~
~0TICI ®TclI -
CLOCK (G) Jf- ~®TCKO-
@Tcco--
@ TclO
@ TCl
CLOCK (ANV SOURCE)
Input signal conditioning: Rise and fail times,; 6 ns, Amplitude = 0 and 3V 1637 06
TSC0026
2-114
PAD
(IN)
(PACKAGE PIN)
OUTPUT SIGNAL
INPUT
(DIRECT)
L
(110 CLOCK)
INPUT
(REGISTERED)
II
14--~ (]) TRG
163707
______I
\---_---11
Voc(VALlD) __---II \
• p
'- ____ ' -
J ,
- - . V PD
MOIM11M2
~GTPGW=,
DONEIPROG
------~------.~
(OUTPUT)
USER VO
USER STATE
.----------------------------
~'-I_N_IT_IA_Ll-ZA-T-IO-N-S-T-A-TE----------
TSC0026
2-115
XC2018B Military Logic Cell Array
CS2
CCLK (2)
(OUTPUl)
DIN
DOUT
(OUTPUT)
1637 oe
Figure 4. Peripheral Mode Programming Characteristics
AG-A15
(OUTPUn
00-07
RCiX
(OUTPUn
CCLK
(OUTPUn
DOur
(OUTPUn
BYTE n-l
CCLK and DOUT timing are the same as for slave mode.
At power-up, Vee must rise from 2.0 V 10 Vee min. in less than 10 ms.
163710
TSC0026
2-116
l::XILINX
DIN~ BITN
~ CD TDCC"I-@ TCCD ~
xxx BITN+1
@TCCL J
CCLK
G)TCCH @ TCCO"",1;::::.
DOur
(OUTPUT) BITN-1 xxx' - - - - - BITN
DONEIPROG
(OUTPUT)
_----1- __________________________________ _
RTRIG
III
CCLK(l)
RDATA
(OUTPUT) VALID
163112
Figure 7. Program Readback Characteristics
Notes: 1. Xilinx maintains this specification as a controlled document. To comply with the intent of MIL-STD-883, and to assure
that you are using the most recently released device performance parameters, please request a copy of the current
revision of this Test Specification from Xilinx.
2. PWR OWN must be active before Vce goes below specified range, and inactive after Vcc reaches specified range.
3. Peripheral mode timing determined from last control signal of the logical AND of (CSO, CST, CS2, WRT) to transition
to active or inactive state.
4. Configuration must be delayed at least 40 ms after Vee min.
5. CCLK and DOUT timing are the same as for slave mode.
6. DIP' must be high before RTRIG goes High.
7. Testing of the Applications Guidelines is modeled after testing specified by MIL-M-38510/605. Devices are first 100%
functionally tested. Benchmark patterns are then used to measure the Application Guidelines. Characterization data
are taken at initial device qualification, prior to introduction of significant changes, and at least twice yearly to monitor
correlation between benchmark patterns, device performance, XACT software timings, and the data sheet.
fuE
8. Minimum CLOCK widths for the auxiliary buffer are 1.25 times the TelH, TelL.
9. Vee must rise from 2.0 V to Vce minimum in less than 10 ms for master k1% vee
mode. PAD
10. RESET timing relative to power-on and valid mode lines (MO, Ml, M2) is
relevant only when RESET is used to delay configuration.
II.AII timings except TTSHZ and TTSON are measured at 1.5 Vcc level with
50 pF MIN Ilk 1% GND
50 pF minimum load output. For input signals, rise and fall times are
less than 6 ns, with low amplitude =0 V, and high = 3 V. TTHZ is 163713
determined when the output shifts 10% (of the output voltage swing)
from VOL level or VOH level. The following circuit is used: ~VIN
TTON is measured at 0.5 Vcc level with VIN = 0 for 3-,State to active
High, and VIN = Vcc for 3-State to active Low. The following load circuit
~ . . I1
50pF MIN
1k1%
is used:
TSC0026 163714
2-117
XC2018B Military Logic Cell Array
TSC0026
2-118
XC3020B
Military Logic Celr Array
M
The Logic Cell™ Array (LCA) is a high density CMOS The XACT development system allows the user to define
programmable gate array. Its patented array architecture the logic functions of the device. Schematic capture is
consists of three types of configurable elements: Input! available for design entry, while logic and timing simula-
Output Blocks, Configurable Logic Blocks and Intercon- tion, and in-circuit debugging are available for design
nect. The designer can define individual 1/0 blocks for verification. XACT is used to compile the data pattern
interface to external circuitry, define logic blocks to imple- which represents the configuration program. This data
ment logic functions and define interconnection networks can then be converted to a PROM programmer format file
to compose larger scale logic functions. to create the configuration program storage.
The Logic Cell Array's logic functions and interconnec- See the XC3000 Commercial data sheet for a full descrip-
tions are determined by the configuration program stored tion.
ORDERING INFORMATION
TIL
XC3020 - 50 PG84 B
50 (50 MHz TOGGLE) - - - - - - - - ' PG84 = CERAMIC PIN GRID ARRAY PACKAGE.
70 (70 MHz TOGGLE) 84-LEAD
cal 00 = CERAMIC QUAD FLAT PACKAGE.
100 LEAD
TSC0085 1637156
2-119
XC3020B Military Logic Cell Array
USER
OPERATION
TSC0085
2-120
PIN ASSIGNMENTS (Continued)
PGAPin PGAPin
Number XC3020 Number XC3020
82 l'WRDI'l K10 "RESET
C2 TCLKIN-I/O J10 OONE-l'G"
81 NC K11 07-1/0
C1 1/0 J11 XTL 1(OUT)-8LCKIN-VO
02 1/0 H10 OS-VO
01 1/0 H11 1/0
E3 1/0 F10 05-1/0
E2 VO G10 CSO-I/O
E1 I/O G11 04-1/0
F2 I/O G9 1/0
F3 vee F9 vee
G3 1/0 F11 03-110
•
G1 1/0 E11 C"ST-1I0
G2 1/0 E10 02-110
F1 1/0 E9 110
H1 1/0 011 NC
H2 1/0 010 01-VO
J1 I/O C11 ROY/BOSV-ncrR'-1I0
K1 110 811 DO-OIN-I/O
J2 M1-Jmi!\TA C10 DOUT-I/O
L1 MO-RTRIG A11 CCLK
K2 M2-VO 810 AO-m-I/O
K3 HOC-I/O 89 A1-CS2-1/0
L2 110 A10 A2-1/0
L3 IIlC"-1I0 A9 A3-1/0
K4 110 88 NC
L4 NC A8 NC
JS 110 86 A1S-1/0
KS 110 B7 M-I/O
LS NC A7 A14-1I0
K6 1N1T-1/0 C7 AS-liD
J6 GNO C6 GNO
J7 1/0 AS A13-1/0
L7 1/0 AS A6-1I0
K7 1/0 BS A12-1/0
L6 liD CS A7-1/0
L8 110 M NC
KS 110 B4 NC
L9 NC A3 A11-1I0
L10 NC A2 AS-liD
K9 110 B3 A10-1/0
L11 XTL2(IN)-1/0 A1 A9-1/0
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
TSC0085
2-121
XC3020B Military Logic Call Array
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
TSC0085
2-122
E:XIUNX
1.100±o.o12
sa
0.095
± 0.015 *I
TOP"'EW
•
f.r.f i Ti iii iT MI.:;"
.018.....J I.....-
± 0.002 DIA 11-·· I 0.OS5DIA
A B C D G H J M~ L 0.100TYP
(i ( 1"1'\
"-
I" 1'\ I" 1'\ I" 1'\
"-
(
"-I-' "-I-' "-
1"1'\ (t\ !
'I-' "-...,
( L ,t> ( D.L D.L (t> ( t\1D.
"- "-I-' "- V "- V "- 'I-' 'V T
, ,
LD.1 t\ (t\ LD.L D.LD.
"-I-' , V "-V
1:D.1D.
'V 'V
(1'\ ( (t\ (1:\
, INDEX PIN 'I-'
(t\ ( t\ (
,
LD.1 D.1 D.
'V ' V ' 1.000 ± o.010
, ,
1:D.1 b.1b.
(t\ ( t\ (
V .070 DIAI.08 MAX
1D.1D.1D.
'V ' V '
1D.1D.1D.
'V ' V 'V
(t\ ( 1:D....L
'V 'V 'V
L D.L:D.& (t\ (
CD CD "-'" '- V '-v I-'
('1'\ I. 1.1'\ ('t'\ (' t'\ I" t'\ (' t'\ (' 1'\ ('
10
"-v "- "-v '-I-' '- I-' '- "-I-' "- V "-
fi'~ I. I'.D.L ('tlL: tlL (' I'.t'\
11
~ '- '-I-' '\. '\.'" '- V '- V '- I-' '-I-' "-I-'
0.100TYP
~
1.000 30- 35'C1W
±0.010 9JA=
BOTTOM VIEW eJC= 4 -7'CIW
NOTE: INDEX PIN MAY OR MAY NOT BE
ELECTRICALLY CONNECTED TO PIN C2. DIMENSIONS IN INCHES
X1t28
2-123
XC3020B Military Logic Cell Array
LEADFRAME
0.0045 MIN
0.0080 MAX
~[
r MARKING
... J il
0.0300.0.0050 ~ 0.0500 OO.OOSO
0.120 MAX
BOTTOM VIEW
(LID SIDE UP) 81DEVIEW
(DIE FACING UP)
1--------1.275.0.02080.---------1
0.680. 0.020 8 0 " - - - 1
DIMENSIONS IN INCHES
LEAD PITCH 0.025 TYPICAL
TOP VIEW
PIN SPACING 0.025 TYPICAL
(DIE FACING DOWN)
NOTES:
8JA = 40-50' om 1. LEADS ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS,
TOPSIDE UP
8JO =5-80 om 2. FORMING TDOlINFORMATION:
- FANCORT INDUSTRIES.- (201) 575-0610 WEST CALDWELL NJ.
- RISIINDUSTRIES (619) 425-3970 CHULA VISTA, Cil
1t0540-'
2-124
STATIC BURN-IN CIRCUITS
Vee
1
30 :- 8.06k • 1.15 k 1.5 k ~
'>
1.3 k
: @]
:.;:l&l~~Q'j:: 131ll~~ l3 O<al '" a~ l'"a~I
......... 18 co< 18 « l : 1.3 k
: 1.5k
1.3 k
B2 All
~~ PWRDWN c CCLK
z Cl0
f1 <!l DOUT
DIN
Bll
~
f--&- ~
~ ~
~ ~
E9
f--E2
rrr-
rm-
f-f,T
~ rnt-
>-;:;;-
~~
~
G3
Vee
XC3042
PG84
Vee
~
~
G9
II
~ I Gl0
715
'-if" Fa
'"irj- rmt-
~ ~
'J1 rJ11
'K1 rt<1T
>--:i2 IJio
'IT
~
Ml
MO 0
DONEIPROG
RESET
Kl0
",8
::E:z: I§ liS-z
C
~C!l
.
~IQ ~~ ...... -,>:: ~~ -, -, !:i{;2 ~~ ~~ ~~::
>::..J "''''
<0 ...
..J ..J 4.99k
1k •
.~ [gJ
-b
NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 1/6 WAn AT 150·C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LIFE.
[ ] CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
~ 30 n RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 WAT lSO·C WITH A
TOLERANCE OF 5%.
163718
TSC0085
2-125
.XC3020B Military Logic Cell Array
Vee
~
1 300
.3 k 1.3 k 300 8.0Sk
[II 1.3k 1.5 k
MN ~ g ~Im J~U~UN ~ ~1~lml&;I$I:!lI~lgll~lo;I8 g) 1.15 k Uk 300
14 0 88
PWRDWN z 87
~
~ " CCLK
DOUT
88
~ DIN 85
~ #-
~ ~
~ ~
~ at-
>--'23 7Q-
~ Ts-
>----fs" F-
>--26 Vee Vee
76
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~~='~} 1T-
~ F- 7150
'""37 0 "65
~ MI
0 NO" I§ I~<;"~ 64
I
1k 4.99 k
m~' ,l,.
1637188
NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 1/8 WAT 150·C WITH A
BUILD TOLERANCE OF 1% AND 5%
TOLERANCE OVER LIFE.
@] CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTICS.
[!] 30-0 RESISTOR IS METAL OXIDE
AND IS RATED FOR 1 W AT
150·C WITH A TOLERANCE OF 5%.
4. USE ON: XC3020-XXCQI00X
5. UNLESS OTHERWISE SPECIFIED,
SOCKET SHALL BE:
ENPLAS
PART NUMBER FPQI32-0.635-01
OR
WELLS
PART NUMBER CP-10582
XC3020-CQ100
TSC0085
2-126
~_ _ _ 0_00 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
TEST SPECIFICATION
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Conditions
-55°C ~ Te ~ +125°C Group A Limits
Test Symbol Vee = 5.0 V ±1 0% Subgroups Min Max Units
High Level Output Voltage VOH Vee = 4.5 V, IOH = -4.0 mA 1,2,3 3.7 V
Low Level Output Voltage VOL Vee = 5.5 V, IOL = 4.0 mA 1,2,3 0.4 V
Quiescent Operating2 leeo CMOS Mode, VIN = Vee = 5.5 V 1,2,3 1 mA
Power Supply Current
TTL Mode, VIN = Vee = 5.5 V 1,2,3 15 mA
Power-Down Supply Current leePD VIN = Vee = 5.5 V, 1,2,3 0.5 mA
PWR OWN =OV
Leakage Current IlL Vee = 5.5 V, VIN = Vee and 0 V 1,2,3 -20 20 flA
Horizontal Long Line IRLL Measured as an average 1,2,3 2.4 mA
Pull-up Current
Input High Level TIL VIHT Guaranteed Input High 1,2,3 2.0 V
Input Low Level TIL V ILT Guaranteed Input Low 1,2,3 0.8 V
Input High Level CMOS V1He Guaranteed Input High 1,2,3 .7 Vee V
Input Low Level CMOS VILe Guaranteed Input Low 1,2,3 .2 Vee V
TSC0085
2-127
XC3020B MIlitary Logic Cell Array
DONEIPROG
Program Width (Low) T pGW 5 See Fig. 1 9,10,11 6 6 Ils
Initialization TpGI 6 9,10,11 7 7 IlS
PWR DWN3
Power Down Supply VCCPD 1,2,3 3.5 3.5 V
RESET4
M2,M1,MO Setup TMR 2 9,10,11 1 1 IlS
M2,M1 ,MO Hold TRM 3 9,10,11 1 1 IlS
Width (low) abort TMRW 4 9,10,11 6 6 Ils
Switching Characteristics, Peripheral Mode Programming 5
CCLK,
To DOUT TCCD 3 See Fig. 5 9,10,11 100 100 ns
DIN Setup Tocc 1 9,10,11 60 60 ns
DIN Hold TCCD 2 9,10,11 0 0 ns
High Time TCCH 4 9,10,11 0.5 0.5 Ils
Low Time TCCL 5 9,10,11 0.5 1.0 0.5 1.0 IlS
Frequency Fcc 9,10,11 1 1 MHz
TSC0085
2-128
E:XIUNX
CCLK,
RTRIG Setup TRTCC 2 9,10,11 200 200 ns
RDATA Delay TCCRO 3 9,10,11 100 100 ns
Clock Low TCCLR 4 9,10,11 0.5 1.0 0.5 1.0 ns
Clock High TCCHR 5 9,10,11 0.5 0.5 ns
Benchmark Patterns8
TS2
TS3
TS4
Tested on all CLBs
9,10,11
9,10,11
9,10,11
135
32
53
35
86
21
34
23
ns
ns
ns
ns
•
TOK PO + Tops - TOPF + TPICK Tss Tested on all CLBs 9,10,11 73 53 ns
TCKO + TOLO + Tpus + TICK + TS6 One long line pull-up 9,10,11 73 48 ns
interconnect
TCKO + TOlO + Tpus + TICK + TS7 The other long line 9,10,11 83 55 ns
interconnect pull-up
TCKO + TOLO + TIO + TICK + TB6 No pull-up, lower 9,10,11 47 31 ns
interconnect long lines
TCKO + TOLO + T IO + TICK + TSg No pull-up, upper 9,10,11 57 38 ns
interconnect long lines
TSC0085
2-129
XC3020B Military Logic Cell Array
K Clock9
To CLB output TCKO 8 N/A 12 8 ns
Additional for Q returning TQLO N/A 11 7 ns
through F or G to CLB out
Logic-input setup TICK 2 N/A 12 8 ns
Logic-input hold TCKI 3 N/A 1 1 ns
Data In setup TDICK 4 N/A 8 5 ns
Data In hold (1) TCKDI 5 N/A 6 4 ns
Enable Clock setup TECCK 6 N/A 10 7 ns
Enable Clock hold TCKEC 7 N/A 0 0 ns
'Clock (High) TCH 11 N/A 9 7 ns
'Clock (Low) TCl 12 N/A 9 7 ns
'These parameters are for clock pulses within an LCA device. For externally applied clock, increase values by 20%.
TBUF
Data to Output TIO N/A 8 5 ns
Three-state to Output
Single Pull-up Tpus N/A 34 22 ns
Pair of Pull-ups TpUF N/A 17 11 ns
TSC0085
2-130
Conditions -50 -70
-55°C::; Tc::; +125°C Group A
Test Sym Vcc =5.0 V ±1 0% Subgroups Min I Max Min I Max Units
110 Clock
To 110 RI input (FF) TIKRI 4 N/A 11 7 ns
110 pad-input setup TplCK 1 N/A 30 20 ns
110 pad-input hold TIKP1 2 N/A 0 0 ns
To 110 pad (fast) ToKPo 7 N/A 18 13 ns
110 pad output setup TOOK 5 N/A 15 10 ns
I/O pad output hold ToKO 6 N/A 0 0 ns
'Clock (High) TIOH 11 N/A 9 8 ns
'Clock (low) Tlol 12 N/A 9 8 ns
Output
To pad (enabled fast) TOPF 10 N/A 15 9 ns
To pad (enabled slow) Tops 10 N/A 40 29 ns
Three-State
To pad begin hi-Z (fast) TrsHz 9 N/A 18 12 ns
To pad valid (fast) TrsoN 8 N/A 20 14 ns
Master Reset
To input RI TRRI 13 N/A 35 23 ns
To output (FF) TRPO 14 N/A 50 33 ns
'These parameters are for clock pulses within an lCA device. For externally applied clock, increase values by 20%.
TSC0085
2-131
XC3020B Military Logic Cell Array
RCLK,
To Address Valid T RAC 1 See Fig.6 N/A 0 200 0 200 ns
To Data Setup TORC 2 N/A 60 60 ns
To Data Hold T RCO 3 N/A 0 0 ns
RCLK High T RCH 4 N/A 600 600 ns
RCLKLow T RCL 5 N/A 4.0 4.0 Ils
TSC0085
2·132
...-------tllI- _---.(GTMRW)________
MO/M1/M2
-f®'~®'~f--------
DONE/PROO
(OUTPUn
t®T
PGW
=1
INIT
__J_----,[0
USER STATE
TPG1
______________________________________________--{r-NOTE3~
\'--_-----1
Vcc(VAlID)
\ ,r"":'t-v-----
~ ____ .I~ CCPD
163719
Figure 1_ General LCA Waveforms
_FGl,,~J
ClB OUTPUT (X,V)
(COMBINATORIAL)
®TCKI~""""'-----
ClB INPUT (A,B,C,D,E)
t=®T1CK .'..
ClBClOCK
11""""=-----------""'"
I+----@ TCl --~~
o TDICK ---4;"""
ClBINPUT
(DIRECT IN)
ClBINPUT
(ENABLE CLOCK)
° TECCK
ClBOUTPUT
(FLIP-FLOP)
ClB INPUT
(RESET DIRECn
ClBOUTPUT
(FLIP-FLOP)
163720
Figure 2_ CLB Waveforms
TSC0085
2-133
XC3020B Military Logic Cell Array
-0-TPID~-f----
I/O BLOCK (I)
VO PAD INPUT
~-G)-l--"-PI-CK--------------
VOCLOCK ------~I r~~----------~I
(lK/OK)
io'----- @ TIOl ---'14----
110 BLOCK (RI)
VOBLOCK(O)
VO PAD OUTPUT
(DIRECT)
VO PAD OUTPUT
-------------------£0 TOKPO
(REGISTERED)
J~Ir-@-8r-TSON--@-9TT-,",1r-
I/O PAD TS
•.
CSllCSO
\ I .
CS2
I \~--------------------~!--------
WS
..
00-07
CCLK .. . ..,,_ ,.
,,_ • • 1 ..
GROUP
OF8 CCLKs
RDYIBUSY .
-----------------------,
DOUT
_--'x'--_--'x'--____________________-' '-----'X'--_____C 163722A
Figure 4. Peripheral Mode Waveforms
TSC0085
2-134
l:XlUNX
163723
AO-A15
(OUTPUT) ADDRESS n ADDRESS n+ 1
CD TRAC
DO-D7 BYTE n
II
RClK
(OUTPUT)
14------7CCLKs------~I----
CCLK
(OUTPUT)
DOUT
(OUTPUT) 07
BYTE n-1
163724A
TSC0085
2-135
XC3020B Military Logic Cell Array
----~/_-----------------------------------
DONEIPROO
(OUTPUT)
RTRIG
v-------~t~CVT~~--~r-------
eeLl<
RDATA
(OUTPUT)
183725
fuC:
PAD
1k
vco
50pF MIN
J 1k
GND
163713
12. (continued)
TTSON is measured at 0.5 Vpc level with VIN • 0 for 3-State to active High, and VIN =Vee for 3-State to active Low. The
following load circuit is usea:
~VIN
~ ... 1 1 k
50pF MIN J
163714
TSC0085
2-136
XC30428
~XILINX Military Logic CeW Array M
The Logic Cell™ Array (LCA) is a high density CMOS The XACT development system allows the user to define
programmable gate array. Its patented array architecture the logic functions of the device. Schematic capture is
consists of three types of configurable elements: InpuU available for design entry, while logic and timing simula-
Output Blocks, Configurable Logic Blocks and Intercon- tion, and in-circuit debugging are available for design
nect. The designer can define individual 1/0 blocks for verification. XACT is used to compile the data pattern
interface to external Circuitry, define logic blocks to imple- which represents the configuration program. This data
ment logic functions and define interconnection networks can then be converted to a PROM programmer format file
to compose larger scale logic functions. to create the configuration program storage.
The Logic Cell Array's logic functions and interconnec- See the XC3000 Commercial data sheet for a full descrip-
tions are determined by the configuration program stored tion.
ORDERING INFORMATION
T8C0117 183726
2-137
XC3042B Military Logic Cell Array
PIN ASSIGNMENTS
USER
OPERATION
.... ;
I/O
I/O
I/O
I/O
I/O
TSC0117
2-138
l':XIUNX
84PGAPln 84PGAPln
Number XC3042 Number XC3042
B2 I'WRlm Kl0 "RESET
C2 TCLKIN-11O Jl0 OONE-PG
Bl VO Kll 07-VO
Cl VO Jll XTL I(OUT)-BLCKIN-VO
02 VO Hl0 D6-VO
01 110 Hll 110
E3 VO FlO 05-110
E2 VO Gl0 CSlJ-VO
El VO GIl 04-VO
F2 1/0 G9 110
F3 vee F9 vee
G3 110 Fll D3-VO
Gl 110 Ell m-II0
G2 VO El0 02-110
Fl VO E9 110
HI
H2
Jl
VO
VO
110
011
010
Cll
VO
01-VO
ROYIBUSY-RC[R'-1I0
II
Kl 110 911 DO-OIN·II0
J2 Ml-R'OAT)( Cl0 DOUT-II0
11 MO-RTRIG All CCLK
K2 M2-1/0 910 AO-WS-VO
K3 HOC-flO 99 Al-CS2-VO
L2 110 Al0 A2-1/0
L3 I:OC"-vo A9 AS-VO
K4 VO B8 VO
L4 VO AS VO
J5 VO B8 AI5-VO
K5 VO B7 M-VO
L5 VO A7 AI4-VO
K6 m-VO C7 AS-I/O
J6 GND C6 GND
J7 VO AS AI3-VO
L7 VO AS AS-VO
K7 VO B5 AI2-liO
Ls 110 C5 A7-VO
LB 110 A4 I/O
KB I/O B4 110
L9 VO AS AlI-liO
LIO I/O A2 AB-VO
K9 VO B3 Ala-liO
Lll XTL2(IN)-VO AI A9-1I0
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
TSC0117
2-139
XC3042B Military Logic Cell Array
14 Al PWRON 46 F14 VO 82 P3 VO
15 C3 VO 49 G13 VO 83 M5 01-VO
18 C5 VO 52 H14 VO 85 N2 Do-OIN-VO
19 M VO 53 H13 va 66 M3 DOUT-va
20 B5 VO 54 J14 VO 87 PI eeLK
21 C6 VO 55 J13 va 88 M4 VCC
22 AS VO 66 K14 VO 89 L3 GNO
23 B5 VO 57 J12 VO 90 M2 ACl-WS-11O
25 B7 VO L13 110' 92 Ml va
27 A7 VO 60 N14 VO 94 Ll A3-va
28 B6 VO 61 M13 XTAL2-VO 85 K2 VO
29 AS VO 62 L12 GNO 96 J3 VO
34 va VO' G3 vee •
Cl0 N12
35 Bll VO P12 VO' 2 G2 AI3-1/O
45 F12 VO 78 Me D2-VO
46 E14 VO 60 N5 va
X',01A
Unprogrammed lOBs have a default pull-up_ This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
• Indicates unconnected bond pads for the CQFP-1 00 package
TSC0117
2-140
l:XJUNX
0.130
±0.010
1-------l.l00±0'012 50------1'1 , I--' 0.100lYP 1.000 ± 0.010
0.100
11'\ 11'\ 11'\ 11'\ lYP
;t ;to ~~ 1
'Y'Y
fJ- 'Y 'Y
I-Efj-E
fEfj-E ~
G
io."lf,
fJ- INDEX PIN TYI'.O.070
/'6.
..LA
T
~
f.:\
'-".
II
-u~
0.018 1 I 6 7 10 11
± 0.002 DIA
BOTTOMYIEW
0.050
NOTE: INOEX PIN MAY OR MAY NOT BE
8 JA - 3O-35°CIW ±0.010
ELECTRICALLY CONNECTED TO PIN C2.
DIMENSIONS IN INCHES
1--------l.27StO.020SO.--------I
LEADFRAME
0.0045 MIN
O.ooaoMAX
r"'[ MARKING
0.0300 .0.0050
LEAD PITCH O.025lYPICAL 0.0500 .0.0050
DIMENSIONS IN INCHES 0.120 MAX
SIDE VIEW
NOTES:
1. LEADS ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS.
TOPSIDE UP
8JA = 40-50° CIW 2. FORMING TOOL INFORMATION:
- FANCORT INDUSTRIES - (201) 57!H1610 WEST CALDWELL NJ.
8JC = 5-8° eIW - RISI INDUSTRIES (819) 425-3970 CHULA VISTA, CA.
2-141
XC3042B Military Logic Cell Array
p 0000000,000000 0
1
0,O18± 0.002 DIA.J
N00000000000000 TYP 0.070 DIA
± 0.005
132 PLCS
M00000000000000
L 000
K 000 000
J 000 000
H 000 + 000 O. 45 1.460
~ G 000 008 ± 0.006 ± 0.015
F 000 000
E 000 000
0000
c 008 000000
B 000 000000
000000
U
0.070
± 0.01 SO
1-----±°iJ.gg7'--~
i+------1.300TYP------>i
1---------±104J,~5------->I
1105388
TSC0117
2-142
STATIC BURN-IN CIRCUITS
Vee
1
30 > 8.06k ~ 1.15 k 1.5k ~
<1ti3 ~ ~ ~ =t l3 :£ ~ ~ 13 ~ !< ~ 18 ~ 18 ~ ~ ~ ~I
~> @)
1.3 k 1.5k
1.3 k 1.3 k ~.
~~ PWRDWN c
z CCLI<
All
~ Cl DOUT
Cl0
~
Bll
DIN
~ ~
~ ~
~ ~
~
E9
E2 ~
~ ~
~ ~
'Fa XC3042 I-j:g
Ta
~
f-&-
Vee
PG84 Vee
~
G9
I Gl0 715
• II
~ Fa
~ f-i:ffi""
~ I Hl0
'-'f1""" fjff-
'Itr" tr
"J2' Ml DONEIPROO
fJiO
--:t1
--=- MO 0 RESeT Kl0
Ng
::E:z: I§ J~C
-2
;i;Cl
1 k.,.
~
.~( [[I
-:!:-
NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 118 WATT AT 150'C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LIFE.
[gJ CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
iII 30 n RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 W AT 150'C WITH A
TOLERANCE OF 5%.
1637t8
XC3042-PG84
TSC0117
2-143
XC3042B Military Logic Cell Array
Vee
~
1
30n
.3k 1.3 k 30n 8.(16k
rn ~1.3k 1.Sk
14
~~ ~ ~ Jm JJJJJN -~JJJ~JJJ8m BB
1.15k 1.5k 30n
PWRDWN ~ 87
~ Cl CCLK
~ DOUT 88
r--H- DIN BS
~ ~
~ ~
~ ~ ~
~ ~
~ ~
~ ~
'25
~
rn-
~
Vee Vee
~ ~
~ ~
,
~
~
~
I~
rn-
'7ii""""
~ ~
~
'"35
res-
~~~~} t"67""
~ ~ 71sn
~ tF-
'"38 Ml
0
::E
Ng
::El:
18
....
0
liS~~0 64
rn~' ~
NOTES:
1. UNLESS OTHERWISE SPECIFIED, AlL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 1/8 W AT 150'C WITH A
BUILD TOLERANCE OF 1% AND 5%
TOLERANCE OVER LIFE.
~ CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTICS.
~ 30-0 RESISTOR IS METAL OXIDE
AND IS RATED FOR 1 W AT
150'C WITH A TOLERANCE OF 5%.
4. USE ON: XC3020-XXC0100X
5. UNLESS OTHERWISE SPECIFIED,
SOCKET SHALL BE:
ENPLAS
PART NUMBER FPC.1 32-0.635-01
OR
WELLS
PART NUMBER CP-l0582
1637188
XC3042-CQ100
TSC0117
2-144
£XllINX
Vee
I
V•• ~~I--~
4.111 •
•01""
N....
Xt129
NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL RESISTORS ARE METAL FILM
AND ARE RATED FOR 1/8 W AT 150"0 WITH A BUILD TOLERANCE OF
1% AND 5% TOLERANCE OVER LIFE.
2. CAPACITOR HAS 10% TOLERANCE, 50 V RATING WITH AN X7R.
TEMPERATURE CHARACTERISTICS.
3. 30-0 RESISTOR IS METAL OXIDE AND IS RATED FOR 1 W AT
150'C WITH A TOLERANCE OF 5%.
XC3042-PG132
TSC0117
2-145
XC3042B Military Logic Cell Array
TEST SPECIFICATION
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress retings only, and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions Is not implied. Exposure
to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Conditions
-55°C s; Te s; +125°C Group A Limits
Test Symbol Vee =5.0 V±10% Subgroups Min Max Units
High Level Output Voltage VOH Vee = 4.5 V, IOH = -4.0 mA 1,2,3 3.7 V
Low Level Output Voltage VOL Vee= 5.5 V, IOL = 4.0 mA 1,2,3 0.4 V
Quiescent Operating2 leeo CMOS Mode, Vin = Vcc = 5.5 V 1,2,3 1.650 mA
Power Supply Current
TTL Mode, Vi" = Vee = 5.5 V 1,2,3 11.15 mA
Power-Down Supply Current leePD Vln = Vee = 5.5 V, 1,2,3 1150 ItA
PWRDWN=OV
Leakage Current IlL Vee = 5.5 V, Vin = Vee and 0 V 1,2,3 -20 20 ItA
Horizontal Long Line IRLL Measured as an average @ 1,2,3 2.4 mA
Pull-up Current Vee =5.5V
Input High Level TTL VIHT Guaranteed Input High 1,2,3 2.0 V
Input Low Level TTL VILT Guaranteed Input Low 1,2,3 0.8 V
Input High Level CMOS VIHC Guaranteed Input High 1,2,3 .7 Vee V
Input Low Level CMOS VILe Guaranteed Input Low 1,2,3 .2 Vee V
TSC0117
2-146
Conditions -50 -70
Test Sym
-55°C ~ Tc ~ +125°C
Vcc = 5.0 V ±10%
Group A
Subgroup Min 1 Max Min 1 Max Units
DONEIPROG
Program Width (Low) T pGW 5 See Fig. 1 9,10,11 6 6 Jls
Initialization TpGI 6 9,10,11 7 7 Jls
PWR OWN"
Power Down Supply VCCPD 1,2,3 3.5 3./? V
RESEP ::::::::
~
M2,M1 ,MO Setup TMR 2 9,10,11 1 :::::::: JlS
M2,M1 ,MO Hold TRM 3 9,10,11 1 Jls
Width (low) abort TMRW 4 9,10,11 6 I:: JlS
TSC0117
2-147
XC3042B Military Logic Cell Array
CCLK.
RTRIG Setup TRTCC 2 9,10,11 200 200 ns
RDATA Delay TCCRO 3 !'I, 10, 11 100 100 ns
Clock Low TCClR 4 9,10,11 1.2 2.0 1.2 2.0 IlS
Clock High TCCHR 5 9,10,11 0.5 O'<it.~ '~ J.1S
'P'
Benchmark PatternsB
TCKO + TOLO + Tpus + TICK + Tes One long line pull-up 9,10,11 73 48 ns
interconnect
TCKO + TOlO + Tpus + TICK + Te7 The other long line 9,10,11 83 55 ns
interconnect pull-up
TCKO + TOLO + T10 + TICK + TeB No pull-up, lower 9,10,11 47 31 ns
interconnect long lines
TCKO + TOlO + TIO + TICK + TeB No pull-up, upper 9,10,11 57 38 ns
interconnect long lines
TSC0117
2-148
- - - - - -- -------------- ---------------
K Clock9
To ClB output TCKO 8 N/A 12 8 ns
Additional for Q returning TOlO N/A 11 7 ns
through F or G to CLB out '"""",
N/A
Logic-input setup
Logic-input hold
TICK
TCKI
2
3 N/A
N/A
12
1 E i"""
ns
ns
ns
II
'~
Data In setup TOICK 4 8
Data In hold (1) TCKOI 5 N/A 6 .•. ns
Enable Clock setup TECCK 6 N/A 10 .••.•"'•.
••••••••••
ns
Enable Clock hold TCKEC 7 N/A 0 j ; ns
'Clock (High) TCH 11 N/A 9 j ns
"Clock (Low) TCl 12 N/A 9 ns
!-. '
"These parameters are for clock pulses within an LCA device. For externally applied clock, increa~,~,x~lues by 20%.
A r t " G"d
pplcalon UI e rmes, SWIC
't h"mg, Int erna I Bu ffers
,C.'"
Clock Buffer TGCK N/A 9 6 ns
TBUF
Data to Output TIO N/A 8 5 ns
Three-state to Output
Single Pull-up Tpus N/A 42 36 ns
Pair of Pull-ups TpUF N/A 22 16 ns
TSC0117
2-149
XC3042B Military Logic Cell Array
I/O Clock
To 1/0 RI input (FF) TIKRI 4 N/A 11 7 ns
I/O pad-input setup
I/O pad-input hold
T plCK
T IKPI
1
2
N/A
N/A
30
0
2~ f:::::::
ns
ns
To I/O pad (fast) TOKPO 7 N/A 18 i ::i::::':' 13 ns
I/O pad output setup TOOK 5 N/A 15 1Q"", }:::::: ns
I/O pad output hold T OKO 6 N/A 0 Q :.;.: .... , ns
'Clock (High) T IOH 11 N/A 9 8',',' ::::.;.:.: ns
:.::::::::
'Clock (low) T IOL 12 N/A 9 IF ns
Output
To pad (enabled fast) TOPF 10 N/A 15 9 ns
To pad (enabled slow) Tops 10 N/A 40 t 29 ns
.:::::::::.::::::::;
Three-Slate it . .: ',.",.",
To pad begin hi-Z (fast) 9 N/A 14 12 ns
TTSHZ
To pad valid (fast) TTSON 8 N/A 20 1!:::::;:: '•.,. ,., 14 ns
Master Reset
To input RI TRRI 13 N/A 37 33 ns
To output (FF) T RPO 14 N/A 55 43 ns
'These parameters are for clock pulses within an lCA device. For externally applied clock, increase values by 20%.
TSC0117
2-150
Conditions -50 -70
-55°C:;; Tc:;; +125°C Group A
Test Sym Vee = 5.0 V ±10% Subgroups Min Max I Min I Max Units
RCLK,
To Address Valid TRAC 1 See Fig.S N/A 0 200 0 200 ns
To Data Setup TORC 2 N/A SO SO ns
To Data Hold TRco 3 N/A 0 0 ns
RCLK High TRCH 4 N/A 600 SOO ns
RCLKLow TRCL 5 N/A 4.0 4.0 J..lS
II
TSC0117
2-151
XC3042B Military logic Cell Array
,..-----ofll.. --....,C0™RW)---------
MOIM11M2 ---f®'g®'~f------
~®TPGW~
DONEIPROG
(OUTPUT)
iNii'
___J__
USER STATE
--.[®TPGI
\1...-_---11
j+-NOTE3-j
--------------------------~\.; I~t------
Vee (VALID)
c,w3
(COMBINATORIAL)
o TCKI~
CLB INPUT (A,B,C,D,E)
® TICK .,~
CLBCLOCK
@ TCL
o TOICK
CLB INPUT
(DIRECT IN)
® TECCK
CLB INPUT
(ENABLE CLOCK)
CLBOUTPUT
(FLIP-FLOP)
CLBINPUT
(RESET DIRECT)
@TRPW
®TRIO
CLBOUTPUT
(FLIP-FLOp)
183720
TSC0117
2-152
l:XILINX
-®-TPID~-r----
VO BLOCK (I)
I/O CLOCK
---""'\
t CD TpICK ---t·*"41- ® TIKPI]~-----
(lK/OK)
~--- @ T1oL ---i4----
0;----.....--
I/O BLOCK (RI)
@TOp
I/O PAD OUTPUT
(DIRECT)
VO PAD OUTPUT
-----------------....,£0 TOKPO
(REGISTERED)
J---1r-0-~-SON----@-~-'"'J
VO PAD TS
I
I/O PAD OUTPUT ----------!( 'j-
163721
Figure 3. lOB Waveforms
\ I
(
.
CS2 __-.-oJ! \~----------~!----
DO-D7
RDY/BUSY ,,
_ •••••••••••••••••••••• 1
163722
TSC0117
Figure 4. Peripheral Mode Waveforms
2-153
XC3042B Military Logic Cell Array
DIN
CCLK
DOUT
(OUTPUT)
163123
AO-A15
(OUTPUT) ADDRESS n ADDRESS n + 1
\:
00-07
------------------j~----~~~------
n BYTE
Rc5iJ<
(OUTPUT)
_-----7CCLKs------~_--
CCLK
(OUTPUT)
DOUT
(OUTPUT) 07
BYTE n-1
163724A
TSCOl17
2-154
E:XIUNX
DONEIPROG
(OUTPUT)
_-1-1___________________________________ _
RTRIG
RDATA VALID
(OUTPUT)
163725
vcc
~ PAD
1k
1637 '3
12. (continued)
TTSON is measured at 0.5 Vpc level with VIN ~ 0 for 3-State to active High, and VIN = Vec for 3-State to active Low. The
following load circuit is usee:
~VIN
~
50pF
..1
MIN
1 '1k
TSC0117 163714
2-155
XC30428 Military Logic Cell Array
TSC0117
2-156
XC3090B
Military Logic Celf Array M
The Logic CeJITM Array (LCA) is a high density CMOS The XACT development system allows the user to define
programmable gate array. Its patented array architecture the logic functions of the device. Schematic capture is
consists of three types of configurable elements: InpuV available for design entry, while logic and timing simula-
Output Blocks, Configurable Logic Blocks and Intercon- tion, and in-circuit debugging are available for design
nect. The designer can define individual 1/0 blocks for verification. XACT is used to compile the data pattern
interface to external circuitry, define logic blocks to imple- which represents the configuration program. This data
ment logic functions and define interconnection networks can then be converted to a PROM programmer format file
to compose larger scale logic functions. to create the configuration program storage.
The Logic Cell Array's logic functions and interconnec- See the XC3000 Commercial data sheet for a full descrip-
tions are determined by the configuration program stored tion.
ORDERING INFORMATION
TIT
50 (50 MHz TOGGLE) - - - - - - - - ' - ~
-
XC3090 - 50 PG175 B
163728A
TSCOO97
2-157
XC3090B Military Logic Cell Array
PIN ASSIGNMENTS
TSC0097
2-158
PG175 PIN ASSIGNMENTS
•
A6 1/0 E16 110 T11 D5-110 M1 A15-110
67 110 F15 110 R10 ~-IIO l2 M-IIO
C7 110 F16 110 P10 110 l1 110
D7 VO G14 110 Nl0 VO K3 110
A7 110 G15 VO Tl0 110 K2 A14-110
A8 110 G16 110 T9 110 K1 AS-IIO
68 110 H16 110 R9 04-/10 J1 110
C8 110 H1S lI'JlT-IIO P9 VO J2 110
D8 GND H14 vee N9 vee J3 GND
D9 vee J14 GND N8 GND H3 vee
C9 110 J15 VO P8 D3-VO H2 A13-110
69 110 J16 110 R8 CST-IIO H1 AS-IIO
A9 VO K16 110 T8 VO G1 110
Al0 VO K15 1/0 T7 VO G2 110
D10 VO K14 110 N7 110 G3 VO
Cl0 110 l16 110 P7 110 F1 110
B10 110 l15 VO R7 D2-110 F2 A12-110
All 110 M16 110 T6 VO E1 A7-110
611 110 M15 110 R6 110 E2 1/0
Dll 110 l14 110 N6 110 F3 1/0
Cll 110 N16 110 P6 VO Dl All-IIO
A12 110 P16 VO T5 110 C1 A8-VO
612 110 N1S 110 RS Dl-VO D2 110
C12 110 R16 110 P5 RDYfSOSV-RcrK-IIO 61 VO
D12 110 M14 110 N5 110 E3 Al0-110
A13 110 P15 XTAl2(IN)-VO T4 110 C2 A9-110
613 VO N14 GND R4 110 D3 vee
C13 110 R15 RESET P4 110 C3 GND
A14 110 P14 vee
Unprogrammed lOBs have a default pUll-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
Pins A2, A3, A 15, A 16, T1, T2, T3, T15 and T16 are not connected.
Pin A1 does not exist.
TSC0097
2-159
XC3090B Military Logic Cell Array
TSC0097
2·160
PHYSICAL DIMENSIONS - Conforms to MIL-M-3851 0 Appendix C, Case P-8C.
TOP VIEW
o INDEX (Al)
•
WE10 METALIC HEATS INK 0.025 REF
ELECTRICALLY CONNECTED TO VCC
PIN KOVAR
0.005 R. TYP.
0.Q16 REF
16000000000000000
00000000,0000000
15 0
N0000000000000000 0.070
t 0.005 TYP DIA
.30000
0000
12 0000
110000 0000
100000 0000
It' 0 ~-::0~0~o-+-_ _ + 0000 0.845
± 0.009
1.660
± 0.016 SO
'0000 0000 1.500
to.0'5
70000 0000
'0000 0000
'0000 0000
40000
30000 DIELECTRIC
COAT
,0000 STAND·OFF PIN
4 PLACES
'0000
T R P N B A
1.-.1-- 0.'00 TYP
110537C
2-161
XC3090B Military Logic Cell Array
DEVITREOUS
SOLDER GLASS
.~[
L.
BOTTOM VIEW
(LID SIDE UP)
(DIE FACING UP)
oo:·:1~ ~~0.120MAX_..-
SIDE VIEW
TSCOO97
2·162
------~---' ~-' -''-"-" ,~-'-~-'- ' -' ,--~--
Vee
30 4.02 k
1.15 k
~\1
~
~ 715
~, H N4
R3
> > 1.5 k
~
~
~
~
PWRDWN
~
CCLK1
~
~
~
DOUT
~ rm--
~
fTs--
~
em-
~
~ r-rs-
~
~ r-m-
fTs-
~ r-rs-
~
~
~
~
f-i&-
I-'p'T-
rm-
fir
III
~ rra--
~ f-fr-
~ r-w-
~
08
Vso
XC3090
Vos
r-m-
~
N9
Vee Vee
PG 175 ~
I-fg-
~ ~
f-ffo- ~
rmt- rrm-
~ I-ffo-
I-fi'ifl f-jifo-
fjIT-
~
rm-
"1ttt
f-5'ji- r-mT
~ f-j5ti-
~ 'tit
hITt ~
~ iiit
~ ~
~ r-:m=-
~ ~
fiIT" '-j;'fa-
r-m- jMl
DONE/PGM\
""'i';t-
fim-
~
f-&'
~ ~I§
' (;,',.8
>:;:t
It:~~~
0 (I)
R~
VCC\ f-i:m-
~
P14
R15
1.3 k
4.99 k
00
~ ~l~rr ~n~nl'~lf,l~lil~ ~ ~ ~l~l~l~l~l~rl~lil~l~l~l~l~l~tr
"'''' WCDOOO LLWWU.u..(!)C!'''r:r :r~~'~~~~~~~~z~z~~~z
1k 1.3 k 1.3 k
,01~Ft
I]]
.1
NOTES:
1. UNLESS OTHERWISE SPECIFIED. ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 1/8 WAT 150"C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LIFE.
ill CAPACITOR HAS 10% TOLERANCE.
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
III 30" RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 WAT 150'CWITHA 1637 31A
TOLERANCE OF 5%.
TSC0097
2-163
XC3090B Military Logic Cell Array
Vee
30 4.02 k
!]]
NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR liB W AT 150°C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LIFE.
[b] CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
[IJ 30 Sl RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 W AT 150°C WITH A
TOLERANCE OF 5%.
TSC0097
2-164
E:XJUNX
TEST SPECIFICATION
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Conditions
-55°C s Te s +125°C Group A Limits
Test Symbol Vee = 5.0 V ±10% Subgroups Min Max Unit~
High Level Output Voltage VOH Vee = 4.5 V,I OH = -4.0 rnA 1,2,3 3.7 V
Low Level Output Voltage VOL Vee = 5.5 V, IOL = 4.0 rnA 1,2,3 0.4 V
Quiescent Operating2 leeo CMOS Mode, Yin = Vee = 5.5 V 1,2,3 3 rnA
Power Supply Current
TTL Mode, Yin = Vee = 5.5 V 1,2,3 15 rnA
Power-Down Supply Current leePD Vln=~5.5V, 1,2,3 2.5 rnA
PWRDWN=OV
Leakage Current IlL Vee = 5.5 V, Yin = Vee and 0 V 1,2,3 -20 20 jJA
Horizontal Long Line IRLL Measured as an average 1,2,3 2.4 rnA
Pull-up Current
Input High Level TTL VIHT Guaranteed Input High 1,2,3 2.0 V
Input Low Level TTL VILT Guaranteed Input Low 1,2,3 0.8 V
Input High Level CMOS VIHe Guaranteed Input High 1,2,3 .7 Vee V
Input Low Level CMOS VILe Guaranteed Input Low 1,2,3 .2 Vee V
TSCOO97
2-165
XC3090B Military Logic Cell Array
DONEIPROG
Program Width (Low) T pGW 5 See Fig. 1 9,10,11 6 6 Il s
Initialization TpGI 6 9,10,11 7 7 IlS
PWR DWN3
Power Down Supply V CCPD 1,2,3 3.5 3.5 V
RESET4
M2,M1 ,MO Setup TMR 2 9,10,11 1 1 IlS
M2,M1 ,MO Hold TRM 3 9,10,11 1 1 Ils
Width (low) abort TMRW 4 9,10,11 6 6 itS
CCLK,
To DOUT Tcco 3 See Fig. 5 9,10,11 100 100 ns
DIN Setup TDCC 1 9,10,11 60 60 ns
DIN Hold 2 9,10,11 ns
High Time
Low Time
TCCD
TCCH 4
5
9,10,11
9,10,11
°
0.5
0.5 1.0
°
0.5
0.5 1.0
itS
itS
TCCl
Frequency Fcc 9,10,11 1 1 MHz
TSC0097
2-166
E:XllINX
CCLK,
RTRIGSetup TRTCC 2 9,10,11 200 200 ns
RDATA Delay TCCRO 3 9,10,11 100 100 ns
Clock Low TCClR 4 9,10,11 1.2 1.2 2.0 I1S
Clock High TCCHR 5 9,10,11 0.5 0.5 !1S
Benchmark Patterns8
TCKO + TOlO + Tpus + TICK + Too One long line pull-up 9,10,11 73 48 ns
interconnect
TeKO + TOlO + Tpus + TICK + TS7 The other long line 9,10,11 83 55 ns
interconnect pull-up
TCKO + TOlO + TIO + TICK + TBB No pull-up, lower 9,10,11 47 31 ns
interconnect long lines
TCKO + TOLO + TIO +TICK + Tag No pull-up, upper 9,10,11 57 38 ns
interconnect long lines
TSCOO97
2-167
XC3090B Military Logic Cell Array
K Clock9
To CLB output TCKO 8 N/A 12 8 ns
Additional for Q returning TOLO N/A 11 7 ns
through F or G to CLB out
Logic-input setup TICK 2 N/A 12 8 ns
Logic-input hold TCKI 3 N/A 1 1 ns
Data In setup TOICK 4 N/A 8 5 ns
Data In hold (1) TCKOI 5 N/A 6 4 ns
Enable Clock setup TECCK 6 N/A 10 7 ns
Enable Clock hold TCKEC 7 N/A 0 0 ns
'Clock (High) TCH 11 N/A 9 7 ns
'Clock (Low) TCl 12 N/A 9 7 ns
'These parameters are for clock pulses within an LCA device. For externally applied clock, increase values by 20%.
TBUF
Data to Output TIO N/A 8 5 ns
Three-state to Output
Single Pull-up Tpus N/A 46 38 ns
Pair of Pull-ups TpUF N/A 22 16 ns
TSCOO97
2-168
Conditions -50 -70
-55°C:s; Tc:S; +125°C Group A
Test Sym Vcc = 5.0 V ±10% Subgroups Min I Max Min \ Max Units
1/0 Clock
To 1/0 RI input (FF) TIKAI 4 N/A 11 7 ns
1/0 pad-input setup TplCK 1 N/A 30 20 ns
1/0 pad-input hold TIKPI 2 N/A 0 0 ns
To 1/0 pad (fast) TOKPO 7 N/A 18 13 ns
110 pad output setup
110 pad output hold
'Clock (High)
TOOK
TOKO
T IOH
5
6
11
N/A
N/A
N/A
15
0
9
10
0
8
ns
ns
ns
II
'Clock (low) T lol 12 N/A 9 8 ns
Output
To pad (enabled fast) TOPF 10 N/A 15 9 ns
To pad (enabled slow) Tops 10 N/A 40 29 ns
Three-State
To pad begin hi-Z (fast) TTSHZ 9 N/A 14 12 ns
To pad valid (fast) TTSON 8 N/A 20 14 ns
Master Reset
To input RI TAAI 13 N/A 37 33 ns
To output (FF) T APO 14 N/A 53 47 ns
'These parameters are for clock pulses within an lCA device. For externally applied clock, increase values by 20%.
RClK,
To Address Valid T AAC 1 See Fig.6 N/A 0 200 0 200 ns
To Data Setup T OAC 2 N/A 60 60 ns
To Data Hold TACO 3 N/A 0 0 ns
RClK High TACH 4 N/A 600 600 ns
RClK low T ACl 5 N/A 4.0 4.0 .JlS
TSC0097
2-169
XC3090B MIIHary Logic Cell Array
.--________I '---(8)T
... MRW) - - - - - - - - - -
MOIM11M2
---f®'~®'~f--------
DONEli5'ROO
~0TPGW=-1
(OUTPUT)
jjijj'f
__J__-,[0 TPG1 .
..I/
(OUTPUT)
USER STATE
..
""-_ _ _ _ _ _C_LE_A...Ri!-S_TA_T_E_ _ _ _ _ _ _
- .
CONFIGURE
,'--_ _-oJ/
j+-NOTE 3-+j
Vrx (VALID)
--------------------------~\ Ir~t---
.. :v V
'-----1, CCPD
16371t
_F®,~3
CLB OUTPUT (X,V)
(COMBINATORIAL)
CLBCLOCK
t® TICK-~'",,....::"'------'1
@ TCL
8) T01CK
CLBINPUT
(DIRECT IN)
® TECCK
CLB INPUT
(ENABLE CLOCK)
CLBOUTPUT
(FLIP-FLOP)
CLB INPUT
(RESET DIRECn
CLBOUTPUT
(FLIP· FLOP)
183720
Figure 2. CLB Waveforms
TSCOO97
2-170
E:XIU~~X
®"Dt t
1/0 BLOCK (I)
CD TPICK ~ .. CD TIKPI;a:
1/0 CLOCK
(lK/OK)
@ TIOl
VO BLOCK (RI)
RESET
VO PAD OUTPUT
(DIRECT)
@TOp
III
f0TOKPO
1/0 PAD OUTPUT
(REGISTERED)
VO PADTS
J ir@
f-
TTSON @TTSHz:f
,
CSi/CSO \ I .•
)
CS2
I \ I
•
Ws .~
---------
00-07
CCLK • I • I GROUP
•
\. .... .. I
I •
\, ...... ,
I
OF8 CCLKs
RDY/BUSY
- ............................... 1
.
I
DOUT
_--"x'--_--'x'-_____ -----I '------'X"-_--"C 163722
2-171
XC3090B Military Logic Cell Array
CCLK
DIN
=t o 'OC'f@""]
l-14--~~ 0 TCCH
'J'" @'=
---_1i44~ (l)Tcco l---------
r-
DOUT
(OUTPUT) BITN~ ~ BITN
1637 23
Ao-A15
(OUTPUT) ADDRESS n ADDRESS n + 1
\:
00-07
------------------~j~----~~~------
BYTE n
RCLK
(OUTPUT)
14--------7CCLKs------~~----
CCLK
(OUTPUT)
DOUT
(OUTPUT) 07
BYTE n-1
1637 24A
Figure 6. Master Parallel Mode Waveforms
TSCOO97
2-172
E:XIUNX
DONEIPROG
(OUTPUn _--£..1. _._. _._. ___ ._._. _.___ ._._._._.___ ._
RTRIG
CVT~~--~r--------
CCLK
RDATA
(OUTPun
1G37 25
~
vcc
1k
PAD
1637 13
12. (continued)
TTSON is measured at 0.5 Vr:.c level with VIN = 0 for 3-State to active High, and VIN = VCC for 3-State to active Low. The
following load circuit is usea:
~VIN
~ . . I1
50pF MIN
lk
1637 14
TSCOO97
2-173
XC3090B Military logic Cell Array
TSCOO97
2-174
XC1736A/XC1765 Serial
Configuration PROM
Product Specification
vpp
FEATURES
• One-Time Programmable (OTP) 36,288 x 1 bit and
65,536 x 1 bit serial memories designed to store
configuration programs for Programmable Gate Arrays PROGRAMMING
DATA SHIFT
• Simple interface to Logic Cell™ Arrays (LCA) requires REGISTER
only one user 1/0 pin
• Daisy chain configuration support for multiple XC2000
or XC3000 LCAs
• Cascadable to support additional configurations or
future higher-density arrays
II
• Military XC1765R screening and quality conformance
inspection is patterned after the requirements of
MIL-STD-883, methods 5004 and 5005.
• Low-power CMOS EPROM process
• Programmable reset polarity for the XC 1765
• Available in the space-efficient 8-pin plastic or ceramic
DIP, or in 20-pin surface-mount PLCC package
• PC-based programming supported by the XILINX
DS112 and other leading programmer manufacturers
DESCRIPTION
LCA can also be loaded from the XC17XX family .. Using a XC1736A/XC1765 S-Pln DIP Pin Assignments
speCial feature of the XC1765, the user can select the
polarity of the reset function by programming a special
EPROM bit. r vee
2-175
XC1736A/XC1765 Serial Configuration PROM
PlCCDIP
Pin Pin Name I/O Description DOUT ADDITIONAL
} SLAVE MODE
M2 CClK lCAs (OPTIONAL)
2 DATA 0 Three-state DATA output for HDC
reading. InpuUOutput pin for pro-
LDC
gramming.
GENERAL·
PURPOSE
4 2 ClK Clock input. Used to increment
the internal address and bit
counters for reading and pro-
gramming.
USER 1/0
PNS
jALl
OTHER
PINS
2-176
XC1736A1XC1765 does not reset its address counter, Master Serial Mode provides a simple configuration inter-
since it never saw a High level on its OE input. The new face. Only a serial data line and two control lines are
configuration will, therefore, read whatever data is required to configure an LCA. Data from the Serial Con-
stored at the higher address locations inthe PROM and figuration PROM is read sequentially, accessed via the
re-configuration will fail. internal address and bit counters which are incremented
2. The LDC output from the LCA drives the CE input of the on every valid rising edge of CCLK.
XC1736A1XC1765, while its OE input is driven by the
inversion of the LCA RESET input. This connection Programming the LCA With Counters Reset Upon
works under all normal circumstances, even when the Completion
user aborts a configuration before Dip has gone High.
The High level on the OE input during RESET clears Figure 2 shows the connections between an LCA and its
the PROM internal address pointer, so that the SCP. The DATA line from the SCP is connected to the DIN
reconfiguration starts at the beginning. Most designs input of the LCA. CCLK is connected to the CLK input of
have a "spare" inverter or inverting gate that can be the SCPo At power-up or upon reconfiguration, the Dip
used for this purpose. signal goes Low (pulled Low by the LCA at reset, or by
external circuitry for reconfiguration), enabling the SCP
LCA MASTER SERIAL MODE SUMMARY
The 1/0 and logic functions of the Logic Cell Array and their
and its DATA output. During the configuration process,
CCLK clocks data out of the SCP on every rising clock
edge. At the completion of configuration, the DONEI
II
associated interconnections, are established by a configu- PROG signal goes High and resets the internal address
ration program. The program is loaded either automati- counters of the SCPo
cally upon power up, or on com-mand, depending on the
state of the three LCA mode pins. In Master Mode, the If the user-programmable, dual-function DIN pin is used
Logic Cell Array automatically loads the configuration only for configuration, it must still be held at a defined level
program from an external memory. The Serial Configu- during normal operation. The XC3000 family takes care of
ration PROM has been designed for compatibility with the this automatically with an on-Chip default pull-up resistor.
Master Serial Mode. On XC2000-family devices, the user must either configure
DIN as an active output, or somehow provide a defined
Upon power-up or upon reconfiguration, an LCA device level, e.g., by using an external pull-up resistor, if DIN is
will enter Master Serial Mode whenever all three of the configured as an inputs.
LCA mode-select pins are Low (MO=O, M1=O, M2=O).
Data are read from the Serial Configuration PROM se- If the LCA is to be reprogrammed after initial power-up,
quentially on a single data line. Synchronization is pro- note that the LCA requires several microseconds to re-
vided by the rising edge of the temporary signal CCLK, spond after the Dip pin is pulled Low. In this case, the LDC
which is generated during configuration. pin can be used instead of the DIP pin to control the SCPo
- -- 110607A
2-177
XC1736A/XC1765 Sarlal Configuration PROM
Programming the LCA With Counters Unchanged Extremely large, cascaded memories in some systems
Upon Completion may require additional logic if the rippled chip enable is too
slow to activate successive SCPs.
When multiple LCA configurations for a Single LCA are
stored in a Serial Configuration PROM, the DE pin should STANDBY MODE
be tied Low as shown in Figure 3. Upon power-up, the
internal address counters are reset and configuration The XC17XX enters a low-power standby mode whenever
begins with the first program stored in memory. Since the CE is asserted High. In this mode, the SCP consumes less
OE in is held Low, the address counters are left unchanged than 0.5 mA of current. The output remains in a high-
after configuration is complete. Therefore, to reprogram impedance state regardless of the state of the OE input.
the LCA with another program, the DONE/PROG line is
pulled Low and configuration begins at the last value ofthe
address counters. PROGRAMMING MODE
Cascading Serial Configuration PROMs Figures 5 and 6 show the programming algorithm for the
XC1736NXC1765. Note that programming mode is en-
For multiple LCAs configured as a daisy-chain, orforfuture tered by holding Vpp High for at least two clock edges and
LCAs requiring larger configuration memories, cascaded is exited by removing power from the device or by a Low
SCPs provide additional memory. on both CE and OE.
Afterthe last bit from the first SCP is read, the SCP asserts XC1765 RESET POLARITY
its CEO output Low and disables its DATA line. The next
SCP recognizes the Low level on its CE input and enables The XC1765 lets the user choose the reset polarity as
its DATA output. See Figure 4. either RESET/OE or OE/RESET. The Xilinx DS112 pro-
grammer and its XPP software prompt the user for the
Afterconliguration is complete, the address counters 01 all desired reset polarity. Any third-party commercial pro-
cascaded SCPs are reset when DONEIPROG goes High, grammer should do the same.
lorcing the RESET/OE on each SCP to go High.
(The polarity is programmed into the firstfouroverflow byte
II the address counters are not to be reset upon comple- locations, 2000H through 2003H. 00000000 in these
tion, then the OE inputs can be tied to ground, as shown in locations makes the reset active Low, FFFFFFFF in these
Figure 3. To reprogram the LCA with another program, the locations makes the reset active High. The programming
DONEIPROG line goes Low and configuration begins of these overflow bytes should be handled transparently
where the address counters had stopped. In this case, by the PROM programmer; it is mentioned here only as
avoid contention between DATA and the configured I/O additional information.)
use of DIN.
DAISY·CHAIN _ DOUT
TO OTHER lCAs _ CClK
DIN -
CClK -
SCP SCP
'-- DATA ' - - DATA
r
L.-- ClK ' - - - - ClK
LCA CEO CEO - TO MORE SCPs
r-" CE ~ CE
AS NEEDED
-'-
REPR~GRAM 1106 08A
2-178
ABSOLUTE MAXIMUM RATINGS
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
OPERATING CONDITIONS
Vcc Commercial Supply voltage relative to GND -O°C to +70°C 4.75 5.25 V
2-179
XC1736A/XC1765 Serial Configuration PROM
o TSCE .o TSCE
®
f4- THCE
RESET/OE
\
- TLC -- f4- 0 THC ~@ THOE -1
ClK ® ~
DATA f4-
.. TOE
® TCE
f4- G) .. 0
TCAC •
71 0
+l TOH ~ . .® TDF
) K
.. ~0 TOH
1106 10
Limits
Symbol Description Min Max Units
"'j
6 \c ClK low Time4 200
7 THc ClK High Time 200 ns
8 TSCE CE Setup Time to ClK (to guarantee proper ODunting) 100 ns
9 THCE CE Hold Time to ClK (to guarantee proper counting)4 0 ns
10 THOE OE High Time (Guarantees Counters Are Reset) 100 ns
RESET/OE
ClK
Limits
Symbol Min Max Units
1 TCDF ClK to Data Float Delay 50 ns
2 TacK ClK to CEO Delay 100 ns
3 TacE CE to CEO Delay 100 ns
4 TOOE RESET/OE to CEO Delay 100 ns
2-180
PROGRAMMING SPECIFICATIONS (Guaranteed by design, but not fully tested)
vpp
ClK
DATA
RESET/OE
______________ __ ~_2 ~_IC_~-~~13~~-IC--------------------- II
110S 13A
DC PROGRAMMING SPECIFICATIONS
Limits
Symbol Description Min Max Units
*No overshoot is permitted on this signal. Vpp must not be allowed to exceed V pP1 max
AC PROGRAMMING SPECIFICATIONS
Limits
Symbol Description Min Max Units
*During programming, CE should only be changed while elK is High and has been High for 200 ns.
2-181
XC1736A/XC1765 Serial Configuration PROM
INCREMENT ADDRESS
COUNTER. RESETIOE
HELD LOW FOR ONE
CLOCK CYCLE
DEVICE PASSED
,'0609A
2-182
ENTER PROGRAMMING MODE
1.Vcc-VPP'" 6V CEm.0E_5V
2. Vpp. 15V FOR AT lEAST 2 ClK RISING EDGES
3. Vpp. BV FOR 1 CLOCK RISING EDGE
D3 _ FFFFFFFFHI>'-Y"ES"------------,
II
INCREMENT ADDRESS
COUNTER, RESETiOE
HELD lOW FOR ONE
CLOCK CYCLE
2-183
XC1736AIXC1765 Serial Configuration PROM
2-184
PHYSICAL DIMENSIONS
8 5
rr O.313 ± 0.0111
0.018
0.009
0.520 ± 0.010
0.470 ± 0.010
5
I
1II.::.=e:=;==C====:;='E;;=~J 0.010
0.018 -t--'II~
0.110 0.010 ± 0.002
0.054---+--+1
0.100 - - - + I
0.032 - - - - - - - + 1 DIMENSIONS IN INCHES
X1OG7
2-185
XC1736A/XC1765 Serial Configuration PROM
± 0.002 LEAD
COPLANARITY
brouujf.''''J
I I
0.005
0.015
~0.320~
1106 15A
0.025 R
8 5l 0.285
PIN II 1
INDEX MARK
'--fT-'--'--'--'--'--M J'
~0.005MIN
0.025
MIN
---i
---p
,~Jl
0.125 MIN
~ X1187
-.l1.--0.018±0.002
0.056 ± 0.005 -.I I.-
8-Pin CerOIP (008)
DEVICE NUMBER
XC1736A
----.-J L OPERATING RANGE/PROCESSING
C = COMMERCIAUINDUSTRIAL (-40° TO +85OC)
XC1765 M =MILITARY (-55° TO +125°)
R = MILITARY (-55° TO+125°C) WITH X1188
PACKAGE TYPE MIL-STD-883 LEVEL B EOUWALENT PROCESSING
PC8 = 8-PIN PLASTIC DIP
DD8 = 8-PIN CERDIP XC 1736A-PD8C XC1765-PD8C
CD8 = 8-PIN CERAMIC SIDE-BRAZED DIP
PC20 =20-PIN PLASTIC LEADED CHIP CARRIER XC 1736A-PC20C XC1765-PC20C
XC1736A-CD8M XC1765-CD8M
XC1765-DD8M
XC1765-DD8R
2-186
Sockets
Below are two lists of manufactures known to offer sockets a compatible PGA socket with wire-wrap pins. Note that
for Xilinx package types. This list does not imply an the board-layout then differs from a PGA board layout.
endorsement by Xilinx. Each user must evaluate the
Zero Insertion Force (ZIF) sockets, recommended for
particular socket type.
prototyping with 132 and 175 pin PGA devices, also lack
There are no wire-wrap sockets for PLCCs. One solution the wire-wrap option. Piggy-back the ZIF socket in a
is to piggy-back a through-hole PLCC socket mounted in normal PGA wire-wrap socket.
PLCC Sockets
AMP Inc.
Harrisburg, PA 17105
(717) 564-0100
Burndy Corp.
Richards Ave.
Norwalk, CT 06856
Mill-Max Mfg. Corp.
190 Pine Hollow Road
Oyster Bay, N.Y. 11771-0300
(516) 922-6000
Precicontact Inc.
835 Wheeler Way
PGA Sockets
Advanced Interconnections
5 Energy Way
West Warwick, RI 02893
(401) 823-5200
AMP Inc.
Harrisburg, PA 17105
McKenzie Technology
44370 Old Warm Springs Blvd.
Fremont CA 94538
(415) 651-2700
2-187
XC1736A/XC1765 Serial Configuration PROM
2-188
SECTION 3
2 Product Specifications
4 Technical Support
5 Development Systems
6 Applications
7 Article Reprints
8 Index
Quality, Testing, and
Packaging
Xilinx utilizes the world-class wafer fabrication facilities of This report describes the nature and purpose of the
Seiko-Epson's plant in Fujimi, Suwa, Japan and the high- various reliability tests performed on finished devices.
volume assembly resources of AN AM in Seoul, the Updated summaries are available upon request from the
•
Republic of Korea. Periodic quality assurance audits of Quality Assurance and Reliability Department at Xilinx.
these facilities to the full requirements of MIL-STD-883 are
routinely performed.
OUTLINE OF TESTING
Xilinx calculates its outgoing component quality level,
expressed in PPM (defective parts per million devices Qualification testing of devices is performed to demon-
shipped), using the industry-standard methods now strate the reliability of the die used in the device, and the
adopted by JEDEC and published in JEDEC Standard 16. materials and methods used in the assembly of the device.
These figures of merit are revised and published quarterly Testing methods are derived from and patterned after the
by Xilinx Quality Assurance and are available from local methods specified in MIL-STO-883.
manufacturer's representatives or from Xilinx. These
summary data are available for downloading from the Referral to the test methods of MIL-STO-883 is not in-
Xilinx Electronic Bulletin Board at (408) 559-9327 [1200/ tended to imply that non hermetic products comply with the
2400 baud; 8 data bits; no parity; 1 stop bit) supporting all requirements of MIL-STO-883. These test methods are
of the following communications protocols: ASCII, Kermit, recognized industry-wide as stringent tests of reliability
XModem, -CRC, and Telink. and are commonly used for nonmilitary-grade semicon-
ductordevices, as well as forfullycompliant military-grade
products.
RELIABILITY INTRODUCTION
Hermetic packages are qualified using the test methods
From its inception, Xilinx has been committed to deliver- specified in MIL-STO-883. The Group 0 package qualifi-
ing the highest quality, most reliable programmable gate cation tests are performed on one lot of each package type
arrays available. A strong Quality Assurance and Reliabil- from each assembly facility every twelve months.
ity program begins at the initial design stages and is carried
through to final shipment. The final proof of our success is A summary of the reliability demonstration tests used at
in the performance of the Logic Cell™ Array (LCA) in our Xilinx is contained in Table 1.
3-1
Quality Assurance and Reliability
1. High Temperature Life 1000 hr min equivalent at temperature = 125°C LTPO = 5, s = 105, c = 2
Actual test temperature = 145°C
Max. rated operating voltage.
Life test circuit equivalent to MIL-STO-883
Table 1A. Reliability Testing Sequence for Non-Hermetic Logic Cell Arrays
3-2
HERMETIC PACKAGE INTEGRITY and ASSEMBL Y QUALIFICATION
6. Subgroup 06:
Internal Water Vapor Content MIL-STO-883, Method 1018,5000 ppm s = 3; c = 0 or
water at 100°C s = 5; c = 1
7. Subgroup 07: LTPO = 15, s = 34 leads,
Lead Finish Adhesion MIL-STO-883, Method 2025 (3 device min) c = 0
8. Subgroup 08:
Lid Torque MIL-STO-883, Method 2024 LTPO = 5, S = 5, c = 0
(for ceramic quad flat pack, CQFP only)
3-3
Quality Assurance and Reliability
4. Thermal Shock This test is performed to evaluate Tables 2 and 3 testing data show the actual performance
the resistance of the package to cracking and resis- of the Logic Cell Arrays during the initial qualification tests
tance of the bonding wires and lead frame to separa- to which they have been subjected. These test results
tion or damage. It involves nearly instantaneous demonstrate the reliability and expected long life inherent
change in temperature from -65°C to +150°C. in the non-hermetic product line. This series of tests is
ongoing as a part of the Quality Conformance Program on
5. Temperature Cycling This test is performed to non-hermetic devices.
evaluate the long-term resistance of the package to
3-4
Table 2. Xilinx Reliability Testing Summary
Device Types: XC2018, XC2064, XC3020, XC3030, XC3042 Processrrechnology: 1.2 Micron Double-Layer Metal CMOS
Die Attach Method: Silver Epoxy Package Type: 68- & 84-Pin PLCC
Molding Compound: Sumitomo 6300H Date: lQ 1990
Equivalent Equivalent
Mean Total Failure Rate
Combined Hrs/Device Device Hrs in FIT
Test Sample Failures at TA = 125°C at TA = 125°C at TJ = 70°C
Solderability Test 12 0
MIL-STD-883, Method 2003
3-5
Quality Assurance and Reliability
Equivalent Equivalent
Mean Total Failure Rate
Combined Devices HrsfCycie Device Hrs in FIT
Test No. Lots Failures on Test at TA = 125°C atTA= 125°C at TJ = 70°C
3-6
E:XllJt~X.
Dl Physical Dimension 45 0 15 0 40 0 15 0
D2 Lead Integrity 55 0 15 0 40 0 15 0
Seal
D3 Thermal Shock 75 0 25 0 59 0 25 0
Mean Hrs/ Total Mean Hrs/ Total Mean Hrs/ Total Mean Hrs/ Total
Cycle/Device Device Cycle/Device Device Cycle/Device Device Cycle/Device Device
Hours Hours Hours Hours
Thermal Shock 15 1,125 15 375 15 885 15 375
Temperature Cycle 100 7,500 100 2,500 100 5,900 100 2,500
Seal
Visual
End-Point Electrical
Parameters
D4 Mechanical Shock
Vibration, Var. Freqency
75 0 25 0 69 1 25 0
II
Constant Acceleration
Seal
Visual Examination
End-Point Electrical
Parameters
D5 Salt Atmosphere 55 0 25 0 40 0 15 0
Seal
Visual
D6 Internal Water-Vapor Content 9 0 5 0 10 0 5 0
D7 Adhesion of Lead Finish 13 0 3 0 6 0 3 0
D8 Lead Torque 10 0
3-7
Quality Assurance and Reliability
DATA INTEGRITY This explains the basic cell, but how is the LCA user
assured of high data integrity in a noisy environment?
Memory Cell Design Consider three different situations: normal operation, a
Write operation and a Read operation. In the normal
An important aspect ofthe LCA reliability is the robustness operation, the data in the basic memory element is not
of the static memory cells used to store the configuration changed. Since the two circularly linked inverters that hold
program. the data are physically adjacent, supply transients result in
only small relative differences in voltages. Each inverter is
The basic cell is a single-ended five-transistor memory
truly a complementary pair of transistors. Therefore,
element (Figure 1). By eliminating a sixth transistor, which
whether the output is High or Low, a low-impedance path
would have been used as a pass transistor for the comple-
exists to the supply rail, resulting in extremely high noise
mentary bit line, a higher circuit density is achieved.
immunity. Power supply or ground transients of several
During normal operation, the outputs of these cells are
volts have no effect on stored data.
fixed, since they determine the user configuration. Write
and readback times, which have no relation to the device The transistor driving the bit line has been carefully de-
performance during normal operation, will be slower with- signed so that whenever the data to be written is opposite
out the extra transistor. In return, the user receives more the data stored, it can easily override the output of the
functionality per unit area. feedback inverter. The reliability of the Write operation is
v'"
CONFIGURATION DATA SHIFT REGISTER
DR DR
CK CK
SEl SEL
W~Ro-------+---~~_+-+---~~_+-- I
CLOCK I
o
CK
PRECHARGE - - -------''-----_+---''-----_+--
WORoN - - ---------t--_+---~--_+--
CONFIGURATION
MEMORY CELL ADDRESS
CIRCUIT SHIFT REGISTER
o 0
WORD LINE
DRIVER CK
WORDN + 1 - --------~---+---~---+--
BITM+ 1 110901A
3-8
E:XIUNX
guaranteed within the tolerances of the manufacturing 0.5 cm2, so less than 0.0015 alpha particles per hou r will be
process. captured by the XC2064in normal operation. The error rate
acceleration in this test is therefore equal to:
In the Read mode, the bit line, which has a significant
amount of parasitic capacitance, is precharged to a logic 5.3 x 107 particles/hour
one. The pass transistor is then enabled by driving the = 3.6 X 10'0
0.0015 particles/hour
word line High. If the stored value is a zero, the line is
then discharged to ground. Reliable reading of the The 0.61 hours of error-free test time thus is equivalent to
memory cell is achieved by reducing the word line High 2.2xl 0'0 hours or 2.5 million years of error-free operation.
level during reading to a level that insures that the cell will
not be disturbed. Most ceramic packages are specified to emit less than 0.01
alpha particles/cm2/hrwhich is about three times morethan
Alpha Particle (Soft Error) Sensitivity
the plastic compound. For an XC2064 in a ceramic pack-
The CMOS static memory cell was designed to be insensi- age, this still results in error-free operation for almost a
tive to alpha particle emissions. To verify that this design million years.
goal was achieved, the following tests were performed. The highest rate of alpha-particle emission comes from the
sealing glass used in cerdip packages and some ceramic
A one-microcurie alpha-particle source (Americum 241) packages (frit lids). For instance, KCIM glass emits about
was placed in direct contact with the top surface of an 24 alpha particles/cm2/hr. Low-alphaglasses are specified
XC2064 die. This allows the die to capture at least 40% of at 0.8 alpha particles/crn2/hr.
the emissions from the radiation source. The following
sequence of tests was performed: Because these glasses are used onlyforthe package seal,
they present a relatively small emitting cross section to the
1. A complex pattern containing roughly 50% logic ones die (less than 0.1 cm 2 ). A low-alpha glass would therefore
was loaded into the XC2064. The operating conditions
were 25°C and 5.0 V.
cause fewer than 0.8 alpha particle hits per hour. The
acceleration factor is then 6.6 x 108 , which translates to
II
about 46,000 years without an error.
2. A pause of variable duration was permitted.
The LCA memory cell has been designed sothat soft errors
3. The entire contents of the XC2064 were read back and caused by alpha particles can safely be ignored.
compared with the original data.
Validation tests to ensure that the test setup would detect ELECTROSTATIC DISCHARGE
errors were performed before and after the alpha-particle Electrostatic-discharge (ESD) protection for each pad is
tests. The results are as follows: provided by a circuit that uses forward and reverse-biased
distributed resistor-diodes (Figure 2). In addition, inherent
Time Readback Total Time Number capacitance integrates any cu rrent spikes. This give suffi-
Test Duration Time Exposed of Errors cient time for the diode and breakdown protections to
1 105 705 805 0 provide a low-impedance path to the power-supply rail.
2 1205 705 1905 0 Geometries and doping levels are optimized to provide
3 3005 705 3705 0 sufficient ESD protection for both positive and negative
4 15005 70s 1570s 0 discharge pulses.
3-9
Quality Assurance and Reliability
Latchup is a condition in which parasitic bipolar transistors Although Xilinx guarantees parts to perform only within the
form a positive feedback loop (Figure 3), which quickly specifications of the data sheet, extensive high tempera-
reaches current levels that permanently damage the de- ture life testing has been been done at 145°C with excellent
vice. Xilinx uses techniques based on doping levels and results. In plastic packages, the maximum junction tem-
circuit placement to avoid this phenomenon. The cross perature is 125°C.
section of a typical transistor (Figure 4) shows several
features. The beta of each parasitic transistor is minimized
Vee
by increasing the base width. This is achieved with large
physical spacings. The butting contacts effectively short
the n+ and p+ regions for both wells, which makes the VBE
of each parasitic very close to zero. This also makes the
PAD
parasitic transistors very hard to forward bias. Finally, each
well is surrounded by a dummy collector, which forces the
VCE of each parasitic almost to zero and creates a structure
in which the base width of each parasitic is large, thus
making latchup extremely difficult to induce.
PAD
110904
3-10
RADIATION HARDNESS-GAMMA TOTAL DOSE TEST
Gamma System
Device Exposure Functional Tester
Number Level Test Results
3-11
Test Methodology
Xilinx is committed to providing the highest level of quality time-consuming and expensive iterations in order to reach
and reliability forthe Logic Cell (LCA) Array . Quality is best even 80% fauH coverage. The cost of greater coverage is
assured by taking the necessary steps to achieve zero often prohibitive. In production, many gate array vendors
defects. Comprehensive testing confirms that every LCA either limit the number of vectors allowed or charge for
device is free from defects and conforms to the data sheet using additional vectors.
specifications. The memory-cell design assures integrity
of the configuration program. The replacement of all storage elements with testable
storage elements, known as scan cells, improves testabil-
ity. AHhough this technique can reduce the production
TESTING testing costs, it can add about 30% more circuitry, de-
crease performance by up to 20%, and increase design
As quality consciousness has grown among semicon- time.
ductor users, awareness of the importance of testability
has also increased. Testing for standard components, Logic Cell Arrays: The testability of the LCA device is
including memories and microprocessors, is accom- similartoother standard products, including micro-proces-
plished with carefully developed programs which exhaus- sors and memories. This is the resuH of the design and the
tively test the function and performance of each part. For test strategies:
reasons explained below, most application specific ICs
cannot be comprehensively tested. Without complete Design strategy:
testing, defective devices might escape detection and be
installed into a system. In the best case, the failure will be • Incorporates testability features because each func-
detected during system testing at a higher cost. In the tional node can be configured and routed to outside
worst case, the failure will be detected only after shipment pads
of the system to a customer. • Permits repeated exercise of the part without removing
it from the tester because of the short time to load a new
Testing advantages of the Logic Cell Array can be illus- configuration program
trated through comparison with two other application • Produces a standard product which guarantees that
specific ICs: Erasable Programmable Logic Devices every valid configuration will work.
(EPLDs) and gate arrays.
Test strategy:
EPLDs: In order to test all memory cells and logic paths of
programmable logic devices controlled by EPROM mem- • Performs Reads and Writes of all bits in the configura-
ory cells, the part must be programmed with many different tion memory, as in memory testing
patterns. This in turn requires expensive quartz lid pack- • Uses an efficient parallel testing scheme in which
ages and many lengthy programltestlerase cycles. To multiple configurable logic blocks are fully tested
save time and reduce costs, this process is typically simultaneously
abbreviated. • Is exhaustive since the circuits in every block are
identical
Gate Arrays: Since each part is programmed with metal
masks, the part can only be tested with a program tailored The Logic Cell Array user can better appreciate the LCA
to the specific design. This in turn requires that the test procedure by examining each of the testing
designer provide sufficient controllability and observability requirements:
for comprehensive testability. The design schedule must
also include time for the development of test vectors and • All configuration-memory bits must be exercised and
a test program specification. If the gate array user requires then verified. This is performed using read back mode.
a comprehensive test program, then he must perform • All possible process-related lauHs, such as short cir-
exhaustive and extensive fault simulation and test grad- cuits, must be detected. The Logic Cell Array is config-
ing. This requires substantial amounts of expensive ured such that every metal line can be driven and
computertime. Additionally, it typically requires a series of observed directly from the input/output pads.
3-12
• Alltesting configurations must provide good controllabil- Memory Cell Testing
ity and observability. This is possible since all configur-
able logic blocks can be connected to inpuUoutput pads. The static memory cells have been designed specifically
This makes them easy to control by testing different for high reliability and noise immunity. The basic memory
combinations of inputs and easy to observe by compar- cell consists of two CMOS inverters and a pass transistor
ing the actual outputs with expected values. used for both writing and reading the memory cell data
(See Figure 1). The cell is only written during configura-
These points bring out an important issue: the Logic Cell tion. Writing is accomplished by raising the gate of the
Array was carefully designed to achieve 100% fault cover- pass transistorto Vcc and forcing the two CMOS inverters
age. With the Xilinx testing strategy, the number of design to conform to the data on the word line. During normal
configurations needed to fully test the Logic Cell Array is operation, the memory-cell provides continuous control of
minimized and the test fault coverage of the test patterns the logic, and the pass transistor is "off" and does not affect
is maximized. In addition, the user's deSign time is memory-cell stability. The output capacitive load and the
reduced because the designer does not have to be con- CMOS levels of the inverters provide high stability. The
cerned about testability requirements during the design memory cells are not affected by extreme power-supply
cycle. The LCA concept not only removes the burden of excursions.
the test-program and test-vector generation from the user,
ty:
but also removes the question of fault coverage and
eliminates the need for fault grading. The Logic Cell Array
. . ',' . . . . . . . . . . . . . .,. .,. . . . . . . . . . . . . . . . . . . . . . . . . ~!--'" a
r'
CONFIGURATION
work. These issues are critically important in quality- :; CONTROl
3-13
Test Methodology
Print World: PATNll.LCA (2018PC84-70), XACT 2.0Sb Eng, Wed Mar 02 16:28:18 198€Print World: PATN11.LCA (2018PC84-7
rn U rn U rn
1= r-'II
* '- 1---1 1---1'- ~'- r----.J L--
UJ---, U iLl u U U ID
AH
,-- ~
ru f--J U U U U U U U U U L)L- ID
lD m r--
[}
1D
{U
tro u u u u u u u u U 1D
[}
[}
1n ~ U rrf1 U rft U rrf1 U rrf1 U ro ..........
j[J
lU
~U U U U U
---,
U U U 0 ~
~ r I~
~ ~
~ CJ U U U U
-f--,
0 0 U 0 rbJ c:::. ~ L-
ID UL]
n U bf1 lJ {1 U ~ U ~ ~
ID -- -- ~ r-
ID
1D ~ U U U U U U U U CJ tL- til
1[1
G
ID ~U 1i
U U U U U U U U L~
lU rID
lq
r-
3-14
I/O Block Testing TESTING THE SPEED OF THE LOGIC CELL ARRAY
Each I/O block includes registered and direct input paths LCA speed is checked with configuration/test patterns
and a programmable 3-state output buffer. The testing of that have been correlated to data sheet ac values.
these functions is accomplished by several configuration/
test patterns that implement and test each option that is Most of these patterns are shift registers with interconnect,
available to the user. One method used to test the I/O lOBs and CLBs in the data path (See Figure 4). They are
blocks is to configure them as a shift register that has a 3- designed with the idea that all elements inthe path must be
state control (See Figure 3). This allows a test pattern to fast enough for the proper data to get to the next input of
check the ability of each I/O block to latch and to output the shift register before the next clock occurs. If any
data that is derived from either the previous I/O block or element doesn't meet the specified ac value, then the shift
from the tester. Several of these patterns are used to register will clock in the wrong data and fail the test. The
exercise different input and output combinations allowed complexity of the logic between two shift register cells
for each I/O block. Configuration/test patterns are also determines the maximum frequency required for the clock
used to precondition the device to test dc parameters such pulse input ofthe shift register. This can be used to reduce
as V 1H , V 1L , V OH' VOL' TTL standby current, CMOS standby the performance requirement of the tester in use. The
current and input/output leakage. The V OH/VOL Test is done patterns used consist of a TCKO + TllO + INTERCON-
while all outputs are either all Low or all High. NECT + TICK for each shift register. This increases the
shift register clock pulse separation time to 30 to 40 ns.
Configurable logic Block Testing The configuration of each pattern is varied so that all of the
interconnect, lOBs, and ClBs are tested at speed.
Each configurable logic block has a combinatorial-logic
section, a flip-flop section, and an internal-control section.
The combinatorial-logic section of the logic block uses an
array of RAM cells (16x1 in or 32X1 in) as a look-up table
HARDWARE TESTING CONSIDERATIONS FOR THE
LCADEVICE
II
to implement the Boolean functions. This section is tested
as an array of memory cells. Configuration/test patterns Currently the logic Cell Array is being tested on Sentry
are used to verify that each RAM cell can be logically testers. The 68 and 84 pin versions can be tested on a 60-
decoded as the output of the array. The flip-flop section of pin tester with 256K of extended local memory. The 3000
the logic block is tested with configuration/test patterns series products are being tested on a 120-pin Sentry
that configure the lCA device as shift registers. Each shift Series 21 tester with 1 million vectors required for 3042 -
register pattern will have different data in the look-up 3090, 512K vectors required for3020 - 3030 and multiple
tables and will have a different pin used as the input to PMU measurement systems.
each shift register. Other configuration/test patterns are
used to implement and test the internal-control section.
3-15
Test Methodology
Print World: patnOl.lca (2018PC84-70), XACT 2.05b Eng, Wed Mar 02 16:02:02 1988 '~int World: patnOl.lca (2018PC84
~ ~
U U U U U U U U U U
U U U U U U rl U U
U U U U U 0 El U U
U U U U U U U U U
U U U U U U U U
U U U U U U U LJ 0 U
U U U U U LJ U U U 0
U U U U U U U U U U
U U U U U U U U U
3-16
1:XIUNX
3-17
Packaging
48 PIN 68 PIN 84 PIN 100 PIN 132 PIN 160 PIN 164 PIN 175 PIN
XC2064 40 58
XC2018 58 74
XC3020 58 64 64
XC3030 74 80
XC3042 74 82 96
XC3064 110
XC3090 135 142 144
1112028
PACKAGE/SPEED/TEMPERATURE SELECTIONS
XC2064
XC2018
XC3020
XC3030
XC3042
XC3064
XC3090
xn04
3-18
PACKAGE THERMAL CHARACTERIZATION Junction-to-Ambient Measurement - 9JA
3-19
Packaging
'Surface mounted
3-20
PACKAGE CHARACTERISTICS For more Information on SMT
Component Average Mass by Package Type and The following organizations provide SMT consulting and
Lead Count training, component part lists, and related services:
3-21
Packaging
3-22
SECTION 4
Technical Support
2 Product Specifications
4 Technical Support
5 Development Systems
6 Applications
7 Article Reprints
8 Index
Technical Support
Beyond the technical data in this book, Xilinx provides a material, beginning with Technical Seminars and ending
wealth of additional technical information to LeA users. with detailed Technical Manuals.
The following pages give an overview of the existing
Technical Seminars and
Users' Group Meetings
£,el~\(\
~i)I(\'Oelc:l
.(.:O.I\'5IU'(\e ~i)(\C~e(\
'Oe'3.\~e 'O\'V~c:l'3.(I.
?o(l.\'3.(\O 7..i)(\C~
eG\\~
'0'3.\\ \--J!' ",,"'3.(\0
£,'3.\\\((\Ole
",~'3.(\\'3.
-'\ 01\(\0
?'3.00-l'3.
\-1'3.\\'3.
II
0 1\'3.(\00
Xilinx sponsors technical seminars at locations throughout Users' Group meetings are intended for experienced us-
North America, Europe, and Asia. ers of Xilinx Field Programmable Gate Arrays, and empha-
size the use of the various development system tools to
Product-oriented seminars are directed toward new and generate LCA-based designs.
potential users of Field Programmable Gate Arrays.
These seminars include a basic description of the Logic Contact your local Xilinx sales office, sales representative,
Cell Array architecture and the benefits of this technology. or distributor for information about seminars in your area.
Experienced users will also find these seminars useful for
learning about newly released products from Xilinx.
4-1
Video Tapes
A one-hour video tape, entitled "Programmable Gate Ar- speed, density, and cost. Development systems and the
rays: The Ideal Logic Device," is available from Xilinx. The deSign methodology are discussed in the last third of the
presentation is divided into three main sections. The first presentation, including on-screen demonstrations of
portion of the video tape is an overview of the Logic Cell some of the software tools. Additional video tapes cover-
Array architecture and the development system, including ing specific details are in preparation.
some example applications. The second section contains
a description of the XiUnx product families, a more detailed VHS copies are available in NTSC, PAL, and SECAM
description of the XC3000 series architecture, a descrip- formats; contact your local Xilinx sales office, sales repre-
tion of the LCA configuration modes, and a brief discussion sentative, or distributor.
of programmable gate array performance in terms of
4-2
Newsletter
II
In September '88, Xilinx started a quarterly technical bugs and work-a rounds. Applications ideas and user tips
newsletter to supply up-to-date information to registered and a list of relevant magazine articles make this a valu-
Xilinx customers. This newsletter gives updates on hard- able source of information for the systems designer using
ware and software availability and revision levels. It also LCA devices.
carries information on PC-clone compatibility, software
4-3
Xilinx Technical
Bulletin Board
TYPE:
F<CR> [F)ILESJ
To display the available files,
the size of each file in bytes
~g~t:~~~df ~~~'i:'if;I~~n of the
.............
:.. :.:..:...... :.:.: ........ .
D~CR>,JDiqWN~qADJ
R<CR> [R)EPLYJ 'fodQwni9ad\:ine Q(!noreflies
1[Om l~.I:lUlietin board: ... ..
To reply to a mesage you've
just read.
L<CR> [L)ISTJ
To locate a file in any acces-
sable area
:'TeCH:';':':
To provide customers with up-tO-date information and an customers. Users with full privilege can read files on the
immediate response to questions, Xilinx provides a 24- bulletin board, download those of interest to their own
hour electronic bulletin board. The Xilinx Technical Bulle- systems or upload files to the XTBB. They can also leave
tin Board (XTBB) is available to all registered XACT messages for other XTBB users.
4-4
New bulletin board users must answer a questionnaire The XTBB is based on a bulletin board system called
when they first access the XTBB. After answering the FIDO. FIDO is a menu-driven system-you choose com-
questionnaire callers can browse through the bulletin and mands from menus to decide what happens next. To
general information file areas. Before exiting, they should choose a menu command, simply type the first letter of the
leave a message for the system operator requesting full command and press return <CR>. Listed below are some
access. A caller with a valid XACT protection key will be helpful hints for using the XTBB.
given full user privileges within 24 hours.
• To perform a sequence of commands, type the first letter
The software and hardware requirements for accessing of each command, followed by a space, and press
the Xilinx Technical Bulletin Board are: return. For example, typing F A 1 F <CR> [F)i1e A)rea
1 F)i1es] from the main menu will list all of the files
Baud Rate 1200 or 2400 contained in file area 1.
Character Format 8 data bits, no parity, 1 stop bit
Phone Number (408) 559-9327 • Often the user is asked a question and promped to
Transfer Protocols ASCII, Kermit, Xmodem, choose between two options (e.g. [yes NO]). The option
- CRC, Telink displayed in all capital letters is the default choice. To
select this option, simply press return. Otherwise, type
Information contained on the XTBB is divided into three your choice and hit return.
general categories: 1. Bulletins, 2. Files and 3. Messages.
• The XTBB has an extensive help section. To get help,
1. Bulletins contain tidbits of up-to-date information; they type ?<CR>. If you have questions about a specific
can be displayed on screen but cannot be downloaded. command, type the first.letter of the command followed
by a question mark and a carriage return (e.g.F?<CR».
2. Files can contain just about anything (text, user pro- A short explanation of the command will be displayed.
grams, etc.). XTBB users can download files to their
own systems or upload files to the bulletin board. • For more information, read the XTBBHLP.TXT file lo-
cated in the GENINFO file area (file area 1).
3. Messages are used to communicate with other XTBB
•
users; they can be general-available to everyone-or
private.
4-5
Field Applications Engineers
3235 Kifer Rd. 919 N. Plum Grove Rd. 61 Spit Brook Rd.
Suite 320 Suite A Suite 403
Santa Clara, CA 95054 Schaumburg, IL 60173 Nashua, NH 03060
Tel: 408-245-1361 Tel: 708-605-1972 Tel: 603-891-1096
3100 Arapahoe Rd.
Suite 404 93 Willow Glen Dr.
Boulder, CO 80303 Kanata Ontario
Tel: 303-443-4780 Canada K2M H8
Tel: 613-592-5522
4-6
Programmable Gate Array
Training Courses
The Xilinx Programmable Gate Array Training Courses XC3000 COURSE OUTLINE
are comprehensive classes covering the Logic Cell Array
component architecture and Xilinx development systems. DAY 1: I. BASIC ARCHITECTURE
These courses are intended for design engineers using
II. DESIGN METHODOLOGY AND THE XACT
Programmable Gate Arrays in their applications who want
DESIGN MANAGER
to get "up-to-speed" as quickly as possible. Two courses
are offered: a four-day course on the XC3000 series, and III. DESIGN ENTRY TOOLS
a two-day course on the XC4000 series.
DAY 2: IV. DESIGN IMPLEMENTATION
LOGIC PARTITIONING
A substantial amount of the class time will be spent AUTOMATIC PLACE AND ROUTE
performing lab exercises on the Xilinx Development System
(two students per development system). These V. LCA CONFIGURATION
development systems will be available to the students on
DAY 3: VI. DESIGN VERIFICATION
the day following the class for optional individual work and SIMULATION
consultations with the instructor(s). XACTOR2 IN-CIRCUIT DEBUGGER
There will be a 25% cancellation fee if you cancel within VI. ROM/RAM MEMORY COMPILER (MEMGEN)
two weeks of your scheduled course date. Failure to
VII. DESIGN IMPLEMENTATION (PPR)
cancel at least one week in advance of the scheduled
course date will result in forfeiture of the full course tuition. DAY 2: VIII. CONFIGURATION
PREREQUISITES: Students are assumed to have a IX. XACT DESIGN EDITOR AND MAKEBITS
background in digital logic design.
X. MAKEPROM
LOCATION: All courses are held at Xilinx corporate XI. DESIGN VERIFICATION
headquarters in San Jose, CA. A detailed map, including
a list of nearby hotels, will be included with the enrollment XII. DOWNLOAD CABLE
confirmation letter. For regional and international classes, XIII. READ BACK
contact your local sales office.
XIV. XACT DESIGN EDITOR (XDE)
4-7
Technical Literature
The first two binders of this 3-volume set are the LCA The Xilinx User's Guide, included with every system, is a
Development System Manuals, providing exhaustive ref- binder with several self-contained application notes giving
erence information on: practical and tutorial information. The following notes are
currently available:
• Executive Program
• LCA Editor • Introduction
• Macros Basic DeSign Flow
• Simulator (SILOS) Hierarchical Design and Merging
• PROM Formatter
• Bit-stream Generator • Getting Started
Programmable Gate Array Design Flow 1990
• Demo Board
Xilinx Tutorial Using Schema 11+
• Place and Route
Xilinx Tutorial Using FutureNet DASH-LCA 1990
• XNF to LCA
Xilinx Tutorial Using OrCAD/SDT
and information on schematic capture
XACT Design Editor Tutorial
The third volume provides detailed information on each of
the 2000 and 3000 series XACT macros, including sche- • Design Entry
Designing LCAs with Boolean Equations
matics, block count, and examples of typical placements.
• Design Implementation
Advanced Design Methodology
Fundamentals of Placement and Routing
LCA Configuration and Debugging Hints
Automatic Design Translation with Xilinx DeSign
Manager
• Design Verification
Verification by Readback and Signature Analysis
Simulating Bidirectional I/O Using SILOS
4-8
SECTIONS
Development Systems
2 Product Specifications
4 Technical Support
5 Development Systems
6 Applications
7 Article Reprints
8 Index
Development Systems
Step
1 Design Entry
~,
Step
2 Design Implementation
~,
Step
3 Design Verification
1955 OtA
5-1
Development System Overview
STEP 1
5-2
Logic Cell Array Design Flow
STEP 2 STEP 3
195503
o Complete system translates design into program- o Interfaces available from Xilinx to popular simulators
mable gate arrays for logic and full timing simulations
o Partitions gate-level design logic into LCA architec- - Mentor Graphics
ture (CLB/IOB) - VIEWlogic
- SILOS
o Automatic logic reduction and partitioning removes
- OrCAD VST
unused logic, e.g. unused counter outputs
o LCA user-programmability permits real time, in-circuit
o Logic synthesis software optimizes design for LCA debugging
architecture
o Download cable allows the LCA to be programmed
o All programs run on PC/AT*-compatible personal in-circuit during debugging
computers and Apollo, Sun-4, Sun-3, and
DECstation engineering workstations
o XC-DS28 XACTOR or MESA" In-Circuit Design
Verifier provides additional hardware debugging
capabilities
II
5-3
Design Flow
X1248
5-4
Design
Processing Sequence Design Manager Menu Description
Create your design by running your schematic editor
Design Entry while inside the Design Manager
STEP 1
STEP 2
Place Route I Run Automatic Place and Route (APR) program and/
or XACT Design Editor to place/route design
The Xilinx Design Manager provides a highly automated environment for convening your designs Into
working field-programmable gate-array designs.
This sequence is illustrated - for a very simple design - on the following pages ...
5-5
Design Flow
XMAKE
Schematics
PAL
Designs
State Xilinx
Machine State Machine
Language
Designs
1954 038
END CASE;
END STATE MACHINE.
5-6
Step 2: Optimization and Mapping
XMAKE
Xilinx Mapping
Program
(XNFMAP)
CLOCK
co
HM---/DO
•
Place-holder
for PAL1 logic
NOT2
OUT
at
t---+--jDl OUTPUT LOW
WHEN
COUNT=2
DECODECLB
1954 06 1954 07
A graphic representation of the top-level MAP file. Unused A graphic representation of the CLB containing
logic (if any) has been deleted and the remaining logic has the PAL logic. In a typical PAL design, of course,
been grouped (mapped) into Configurable Logie Blocks several CLBs would be used.
and I/O Blocks.
5-7
Design Flow
Step 2: Merging
XMAKE
..
?i
,."", .. CLOCK
... ,.., ::
77 ao »
<>r
i} i/
'i >
,
Q1
NOT2
;;il "~ <
I Ci ii
<:-
} OUTPUT LOW
.. , it WHEN
COUNT =2
<»}'<>} i> i
DECODECLB
1954 09
The merged design contains the CLBs and lOBs for the entire design.
5-8
Step 2: Translating to an LeA File
XMAKE
Shaded area indicates commands automatically
invoked by execution of XMAKE in the Design
Manager.
To Place
} - - - - - , - - -.. and Route
Page 5-10
Unrouted
Logic Cell Array
File
To Simulator
' - - - - _ (Unit-delay Simulation)
Page 5-12
1954 lOB
{J 0 0 0 oa
{) a 0 0 0 0 a 0
{)
{) 0 0 [l o 0 0 0 [l {}
{I
a 0 0 Q0 0
aa tJtJ O[
iJ 0 Q [}
~
{]
{] 0 0 Q 0 0 QG [} ao III
iJ [}
{] 0 0 0 0 0 0 0 0 [}
[
11
~
0 0 0 0 a o0 0
[}
0
0
~ 00 co o;::J OOC:OO 00 co o;j ·0 1954 11
195402
5-9
Design Flow
1954 128
1954 18
5-10
Step 2: Bitstream Generation
DS501
1954 14B
1111111100100000000000111001111001001111 The BIT file contains the binary configuration data that
programs an LCA to perlorm the design function.
0011111111011111111111000101111011111101
0111111010110111011110111011111110111111
0111011101101111011111110111111101111111
0011111111111111111111111111011111111111
0111001101110111011101111011111110111111
1111111100100000000000111001110001001111
0011100011110111110111111111111111111111
0011111110111111111101111110111111111111
II
0011111111111101111111111111101111101111
0111111011101110111111101111111011111110
0111111010110111011 ...
5-11
Design Flow
....
J
•.••.•••••••••••••••• CLOCK CLOCK
..•..
.....
01
>t2···················
NOT2>1"
1<
::·K<
...................................................................
OUTPUT LOW
WHEN
COUNT 2
DECODECLB
1954 09
LCA designs are simulated at the physical CLB and lOB level with worst-case
liming.
5-12
E:XIUNX
CLOCK
'--_-----'I
01
NOT2
LJ
195421
II
5-13
Design Flow
BIT HEX
Xilinx PROM PROM
Format Generation Pr08rammer
(MAKEPROM) (Xilinx, ata 1/0, etc.)
Configuration
Bitstream File
DS501
DS501
DS28 or MESA
1954158
5-14
In-circuit verification lets you immediately see
how your LeA designs function ...
Program a PROM ...
TARGET SYSTEM
O Serial or Parallel
PROM
Programmed with
Configuration
OataforLCA
1954 lSA
Download Cable
connects to
Raralle I port of
PC or serial port
of workstation
D 1...-_ _
LCA o
1954 17A
... Or use the Xilinx XACTOR or Data 1/0 MESA Design Verifier III
5-15
Xilinx Automatic CAE Tools
Product Overview
5-16
r----------,
I OTHER I
I SCHEMATIC ENTRY I
I SYSTEMS I
FUTURENET VlEWd raw-
STEP 1 DESIGN MACRO DASH-LCA LCA
I MENTOR DS343-AP11
& I OrCAD DS35-PC1 I
I I
ENTRY MSI
LIBRARIES
DS390-PC1
I
I
L ___ _
r-- ---,
I PALASM I--~-"J
I TRANSLATOR 1----.--,/1
~..J-=~====~
L ______
LOGIC REDUCTION
PARTITIONING
& OPTIMIZATION
TRANSLA TlON INTO
CLBS&IOBS
STEP 2 DESIGN
IMPLEMENTATION
08501
II
GATE LEVEL
SIMULATION
LOGIC
CELL
ARRAY
LOGIC &
STEP 3 DESIGN TIMING
VERIFICATION SIMULATION
IN-CIRCUIT DESIGN
VERIFIER
1956 01C
5-17
Xilinx Automatic CAE Tools Product Overview
"
Step • SILOS Simulator and Interface OS22
• VIEWsim Simulator and Interface OS290
3 • OrCAO VST Interface OS351
• Serial Configuration PROM Programmer OS112
• XACTOR In-Circuit Oesign Verifier OS28
5-18
XC-DS310 DASH-LCA
Schematic Editor, Interface
and Library
Step 1 Option Product Brief
FEATURES
DASH-LCA supports unlimited levels of hierarchy. The
• Xilinx only FutureNet DASH-LCA schematic editor Xilinx DASH-LCA Schematic Library provides the symbol
provides easy-to-use hierarchical LCA design library and conversion utility to permit designers to enter
capability LCA designs with the DASH-LCA Schematic Editor. The
• Macro library of over 100 standard logic family Xilinx library provides the logic, I/O, and macro symbols to
equivalents derived from the XACT Macro Library be used in the schematic. A Xilinx conversion utility
• Library of logic symbols including all two-input, three- converts the schematic into an XNF output file.
input and four-input AND, OR and XOR gates plus
storage, inpuVoutput and clock elements Once partitioned, the design may be placed and routed
• Additional 100 7400 TTL library elements. See with the XC-DS501 XACT Design Implementation
page 5-34 for a listing of TTL macros System. The Xilinx symbol library includes symbols to flag
critical data and clock signals which the Automatic
• User control for flagging critical paths for the Placement and Routing Program uses to prioritize those
Automated Placement and Routing program signals for minimum delay.
• Converts schematic drawings to a Xilinx Netlist
Format (XNF) output file
• Output compatibility with XC-DS501 XACT Design
Implementation System
• Runs on PC/AT or compatible personal computers
GENERAL
3002
5-19
XC-DS31 DASH
~xnJXX Schematic Interface and
Library
Step 1 Option Product Brief
FEATURES GENERAL
• Library and translator for users of the DASH Schematic Schematic entry and automatic partitioning of LCA
Designer designs shortens logic reduction and product
• Macro library of over 100 standard logic family development times. Complex designs can be specified
equivalents derived from the XACT Macro Library schematically and quickly implemented for in-circuit
design verification.
• Library of logic symbols including all two-input, three-
input and four-input AND, OR and XOR gates pius
The Xilinx DASH Schematic Designer Library provides the
storage, inpuVoutput and clock elements
symbol library and conversion utility to permit designers to
• Additional one hundred 7400 MSllibrary elements. See enter LCA deSigns with the DASH Schematic Designer.
page 5-34 for a listing of all macros. The Xilinx library provides the logic, 110, and macro
• User control for flagging critical paths for the symbols to be used in the schematic. A Xilinx conversion
Automated Placement and Routing program utility converts the schematic into an XNF output file.
• Converts schematic drawings to a Xilinx Nellist Format
(XNF) output file Once partitioned, the design may be placed and routed
with the XC-DS501 XACT Design Implementation
• Output compatibility with XC-DS501 XACT Design
System. The Xilinx symbol library includes symbols to flag
Implementation System
critical data and clock signals which the Automatic
• Runs on PC/AT or compatible personal computers, Placement and Routing Program uses to prioritize those
Sun 3 and Sun 4 signals for minimum delay.
1964
5-20
XC-DS343 Mentor Graphics
Schematic and Simulation
Interfaces and Library
Step 1 Option Product Brief
FEATURES GENERAL
• Mentor Graphics certified interfaces Schematic entry and automatic partitioning of LCA
• The IDEA" Interface Station can be used for designs shorten logic reduction and product-development
schematic entry and simulation of programmable- times. Complex designs can be specified schematically
gate-array designs and quickly implemented for full timing simulation and
in-circuit design verification.
• Full timing simulation with post placement/routing
information
The Xilinx DS343 package provides the symbol library
• Primitive library includes flip-flops, latches, AND, OR, and conversion utility to permit designers to enter LCA
XOR, NAND, NOR gates designs with the Mentor Graphics NetED Schematic
• Macro library includes over 100 standard logic Editor. The Xilinx library provides the logic, I/O, macro,
elements (counters, multiplexers, registers, etc.) and TTL symbols to be used in the schematic. A Xilinx
• Additional one hundred 7400 MSllibrary elements conversion utility converts the schematic into an XNF
included at no charge. See page 5-34 for a listing of output file.
all macros (available 1H91).
Once partitioned, the design may be placed and routed
• Xilinx Nellist Format (XNF) output is compatible with
with the Apollo-based XC-DS501 XACT Design
XC-DS501 Design Implementation System
Implementation System. The Xilinx symbol library
• Available on Apollo SR10.1 and Mentor IDEA V7.0 includes symbols to flag critical data and clock signals
which the Automatic Placement and Routing Program
uses to prioritize those signals for minimum delay.
'IDEA is a registered trademark of Mentor Graphics
DESIGN
DESIGN ENTRY VERIACATON
~
II
-------,
I
I
I
I
I
I
_______ .1
DESIGN
IMPLEMENTATION
XC.I)S501 XACT
DESIGN IMPLEMENTATION
SYSTEM
I
I
I
I
I
I
______________________________________ .1 1958026
5-21
XC-DS35 OrCAD* SDT
Schematic Entry Interface
and Design Library
Step 1 Option Product Brief
FEATURES Xilinx library provides the logic, I/O, and macro symbols to
be used in the schematic. A Xilinx conversion utility
• Library and translator for users of the OrCAD* SDT converts the schematic into an XNF output file.
Schematic Editor
Once partitioned, the design may be placed and routed
• Library of over 100 standard logic macros with the PC-based XACT Automated Design
• Library of logic symbol primitives includes AND, OR, Implementation Program. The Xilinx symbol library
NAND, NOR, and XOR gates plus storage, input/output includes symbols to flag critical data and clock signals
and clock elements which the Automatic Placement and Routing Program
• Additional one hundred 7400 MSllibrary elements uses to prioritize those signals for minimum delay.
included at no charge. See page 5-34 for a listing of
all macros (available 1 H91).
• User control for flagging critical paths for the
r------------------,
I OrCAD SOT III I
Automated Placement and Routing Program I I
• Converts schematic drawings to a Xilinx Netlist Format I
(XNF) output file I
I I
• Output compatibility with XACT Design Implementation I
L ______ _ _________ ...JI
System
• Runs on a PC/AT or compatible personal computer r-- ----- ---------,
I I
I LCA XNF XC-DS35 I
GENERAL I LIBRARY TRANSLATOR OrCAD
I INTERFACE I
5-22
ADVANCE INFORMATION
XC-DS361 EDIF
Netlist Interface
5-23
XC-OS390 VIEWdraw-LCA
Schematic Editor, Interface
and Library
Step 1 Option Product Brief
GENERAL
5-24
XC-DS391 VIEWlogic
VIEWdraw and VIEWsim
Interfaces and Library
Step 1 and Step 3 Options Product Brief
FEATURES GENERAL
• Library and translator for userll of the VIEWlogic Schematic entry and automatic partitioning of LCA
VIEWdraw Schematic Editor and VIEWsim Simulator designs shorten logic-reduction and product -development
• Macro library of over 100 standard logic family times. Complex designs can be specified schematically
equivalents derived from the XACT Macro Library and quickly implemented for in-circuit design verification.
• Library of logic symbols including all 2-input, 3-input
The Xilinx VIEWdraw Library provides the symbol library
and 4-input AND, OR and XOR gates plus storage,
and conversion utility to permit designers to enter LCA
inpuVoutput and clock elements
designs with the VIEWdraw Schematic Designer. The
• Additional 100 7400 TTL library elements. See Xilinx library provides the logic, I/O, and macro symbols to
page 5-34 for listing of the TTL macros. be used in the schematic. A Xilinx conversion utility
• User control for flagging critical paths for the converts the schematic into an XNF output file.
Automated Placement and Routing
• Converts schematic drawings to a Xilinx Nellist Once partitioned, the design may be placed and routed
Format (XNF) output file with the PC- or workstation-based XC-DS501 XACT
Design Implementation System. The Xilinx symbol library
• Converts XNF files to format accepted by VIEWsim
includes symbols to flag critical data and clock signals
Simulator for logic and timing simulation
which the Automatic Placement and Routing Program
• Output compatibility with XC-DS501 XACT Design uses to prioritize those signals for minimum delay.
Implementation System
• Runs on PC/AT-compatible personal computers, With the Xilinx VIEWsim Simulation Interface, designers
Sun-3, Sun-4 and DECstation 3100 can use the VI EWlogic Simulation environment to perform
post-layout simulation. All post-layout timing information,
including pin-to-pin delays, is back annotated into the
VIEWlogic environment for full timing simulation.
188.8ns 11111118888881888888
112.8ns 11111111888881888888
II
123.8ns 11111111818881888888
133.8ns 1111111181888BBBBBBB
15B.8ns B1111111B18888888888
28B.Bns 11111111818888888888
212.8ns 11111111118888888888
221. 8ns 111111111118BBBBBBB81"YI.T"·~""
258.8ns 8111111111188888B888
3BB. 8ns 1111111111188B8888881!~!~!::~S!
312.8ns 1111111181188B88BB881;
321. 8ns 1111111181818B888888IsYINTH'Dt.
358.8n8 8111111181818B888888
48B.8n811111111818188888B88
X125f
5-25
ADVANCE INFORMATION
5-26
XC-DS501 XACT
Design Implementation
System
Step 2 Product Brief
•
designers to merge multiple modes of design entry into a
single design.
The figure on page 5-17 illustrates the design flow from a
design schematic with some glue logic, a 7400-M81 macro,
and a PLD symbol. The design files are merged and
partitioned into CLBs and lOBs.
The Automatic Placement and Routing software, APR, is
very flexible. Routing resources can be specified to
eliminate clock skews and minimize routing delays for
critical paths.
5-27
XC-OS22 PC-SILOS*
Simulators
GENERAL r-------------------,
I I
PIC-SILOS is a powerful PC-based simulator that I I
I I
provides event-driven logic and timing simulation of LCA I XC-DS22 I
designs. Simulation is particularly useful for testing I PC-SILOS I
designs or design segments as well as for verifying critical I SIMULATOR I
timing over worst-case power supply, temperature and I I
process conditions. L _________ ~_______ -'_.
5-28
XC-DS290 VIEWlogic
VIEWsim Simulator
III
X1252
5-29
XC-DS3S1 OrCAD VST
Simulator Interface
FEATURES
been placed, routed and then fully debugged using
• Model library and netlist translator for users of the in-circuit emulation, worst case timing may be verified.
DrCAD VST Simulator This enables the user to select the correct LCA speed
grade for a particular application.
• Supports full timing simulation of routed LCA designs,
and unit-delay simulation of unrouted designs
Network inputs for LCA designs are automatically created
• Permits simulation of schematics which include PAL by the XNF2VST utility from the XNF output of the XACT
logic defined with PALASM, ABEL, CUPL, Log/IC, or Design Implementation System. The network includes
PLDesigner. logic and routing delay parameters and setup and hold
• Input compatible with XACT Design Implementation times based upon the selected speed grade operating
System under worst case conditions.
• Runs on a PC/AT or compatible personal computer
GENERAL
1970
5-30
XC-DS112 and XC-DS113
Serial Configuration PROM
Programmer and Adapter
Step 3 Option Product Brief
FEATURES GENERAL
• Programs XC1736, XC1736A, XC1765 Serial When using Xilinx Serial Configuration PROMs to
Configuration PROMs configure programmable gate arrays, the designer can
• Connects to serial port of PC/AT or compatibles program them with XC-DS112 Configuration PROM
Programmer.
• Operates from PC via software provided with
program-ming unit
The programming unit connects to a serial port of a PC/AT
• Accepts HEX-format data files created by the DS501 or workstation and is controlled using the software
XACT Design Implementation System included with the XC-DS112.
• Supports a-pin mini-DIPs directly
• Supports 20-pin PLCC packages with optional DS113 Designers compile their LCA designs into a standard HEX
adapters format file using the XACT development system. The
programming software provided with the XC-DS112 is
• Runs on PC/AT-compatible personal computers
then used to download the HEX file into the programming
Apollo, Sun-4, Sun-3, DECstation engineering
unit and to program a serial PROM.
workstations
XC-DS112
PROGRAMMER PC
(DB25 RECEPTACLE) (DB25 PLUG)
•
+V----S ~ S DSR
GND 7 ... 7 GND
[ 8 ~ 8 DCD
20 .. 20 DTR
196001
XC-DS112 Interface to pc
1960
5-31
XC-DS28, XC-DS27, XC-DS26
XACTOR™ln-Circuit
Design Verifier
Step 3 Option Product Brief
5-32
Xilinx Development System
Support Agreements
All Xilinx development systems come with free software • Free use of the Xilinx Technical Bulletin Board. To
support for one year. To receive software updates, the provide customers with up-to-date information and an
customer must become a registered customer by return- immediate response to questions, Xilinx provides a 24-
ing the registration card. Registering your software also hour electronic bulletin board. The customers who are
places you on the mailing list for XCELL, the Xilinx cus- current with their support agreements and have full
tomer newsletter. privileges, can read files on the bulletin board,
download those of interest to their own systems or
Benefits include:
upload files to the bulletin board.
• Free software updates. Customer will receive new
releases of the software programs covered by the • Free quarterly technical newsletter. This newsletter
agreement. Customer can enjoy enhanced function- gives updates on hardware and software availability
alities, performance and bug fixes free of charge. Xilinx and revision levels, as well as known software bugs and
typically provides about two new update releases per work-arounds. In addition, application ideas and user
year that include the necessary diskettes and tips and a list of relevant magazine articles make this a
documentation required to implement each update. valuable source of information.
• Toll free applications hot line and local field application
engineering support. Customers can receive expert After the first year, the above benefits are available
help instantly by calling our application hot-line: (408) through Xilinx annual software support agreements. The
897-5199 or (800) 225-7778 and ask for cost of the agreements are typically 12% to 15% of the
Applications Engineering. original price per year.
1998
5-33
~XIUNX LeA Macro Library Listings
XC 3000 XC2000
PADS #CLBs #CLBs
BPAD Bidirectional Package Pin Symbol ........................................ . o o
IPAD Input Package Pin Symbol ................................................... . o o
OPAD Output Package Pin Symbol ................................................ . o o
UPAD Unbonded Die Pad Symbol ................................................... o o
lOB SCHEMATIC ELEMENTS
TBUF Internal 3-State Buffer ........................................................... 0
ACLK Auxiliary Buffer ..................................................................... . o o
GCLK Global Buffer ........................................................................ . o o
IBUF Input Buffer ............................................................................ o o
INFF Input Flip-Flop ....................................................................... o o
INLAT Input Latch ............................................................................. o
OBUF Output Buffer ......................................................................... o o
OBUFZ Output Buffer with Output Enable .......................................... o o
OUTFF Output Flip-Flop ..................................................................... o
OUTFFZ Output Flip-Flop with OBUFZ ............................................... . o
BUF Internal non-inverting Buffer ................................................ .. o o
INV Inverter .................................................................................. 1
PULLUP Input pull-up Resistor ............................................................ 0
OINV Inverting Output Buffer .......................................................... 0
GENERAL
5-34
~XlUNX
XC 3000 XC2000
GENERAL (Continued) # CLBs #CLBs
HX83 4-Bit Binary Adder With Fast Carry ............. ........... ................. 6
HX85 4-Bit Magnitude Comparator ................................................... 7
HX280 9-Bit Parity Checker / Generator ............................................. 3
HX283 4-Bit Binary Full Adder6 ............................................ .............. 6
HX518 8-Bit Identity Comparator ........................................................ 5
HX521 8-Bit Identity Comparator .................... .............. ...................... 5
HX125 3-State Bus Buffer ............................................................ ....... 0
HX240 Octal Inverting Buffer, 3-State Outputs .................................. . 4
HX241 Octal Non-inverting Buffer, 3-State Outputs ................. :........ . 1
HX244 Octal Non-inverting Buffer, 3-State Outputs .......................... . o
HX245 Octal Bidirectional Transceiver .............................................. . 1
HX540 Octal Inverting, 3-State Outputs .............................................. o
HX541 Octal Non-inverting, 3-State Outputs .................................... .. o
MCOMP Magnitude Comparator ........................................................... 4
PHFRCOMP Phase/Frequency Comparator .............................................. .. 2
SAR Successive Approximation Register ....................................... 9
LATCHES
LD Data Latch ...............................................................................
LDRD Data Latch with Reset Direct ................................................ ..
LDSD Data Latch with Set Direct ......................................................
LRS Set-Reset Data Latch with Reset Dominant .......................... .
LDM Data Latch with 2-lnput Data Mux ...........................................
LDMRD Data Latch with 2-lnput Data Mux with Reset Direct ............ ..
LDMSD Data Latch with 2-lnput Data Mux with Set Direct ................ ..
LDSRD Data Latch with Set Direct, Reset Direct ................................ .
HX77 2-Bit Latch ............................... ........................ ............ ............ 1
HX259 8-Bit Addressable Latch ............... .......... ................................. 8
HX373
FLIP-FLOPS
Octal Latch with 3-State Outputs .... .................... .............. ...... 4
III
FD D Flip-Flop ..............................................................................
FDRD D Flip-Flop with Reset Direct ................................................ ..
FDSD D Flip-Flop with Set Direct ......................................................
FDSRD D Flip-Flop with Set Direct, Reset Direct ................................
FDC D Flip-Flop with Clock Enable ................................................. 1
FDCRD D Flip-Flop with Clock Enable, Reset Direct .......................... .
FDCR D Flip-Flop with Clock Enable, Reset .....................................
FDCS D Flip-Flop with Clock Enable, Set ....................................... ..
FDR D Flip~Flop with Reset .............................................................
FDS D Flip-Flop with Set ................................................................ .
FRS Set-Reset Flip-Flop with Reset Dominant ............................. ..
FSR Set-Reset Flip-Flop with Set Dominant ...................................
FDM D Flip-Flop with 2-lnput Data Mux ..........................................
FDMRD D Flip-Flop with 2-lnput Data Mux with Reset Direct ............ ..
FDMSD D Flip-Flop with 2-lnput Data Mux with Set Direct ................ ..
5-35
Macro Lists
XC 3000 XC2000
F.LIP-FLOPS (Continued) #CLBs #CLBs
FDMR D Flip-Flop with 2-lnput Data Mux with Reset ............................ .
FD\MS D Flip-Flop with 2-lnput Data Mux with Set ................................ .
FJK J-K Flip-Flop ................................................................................
FJKRD J-K Flip-Flop with Reset Direct ....... .............................................
FJKSD J-K Flip-Flop with Set Direct ....................................................... .
FJKSRD J-K Flip-Flop with Set Direct, Reset Direct ..................................
FJKS J-K Flip-Flop with Set ..................................................................
FTO Self Toggle Flip-Flop ...................................................................
FTORD SeH Toggle Flip-Flop with Reset Direct ...................................... .
FTOR Self Toggle Flip-Flop with Reset ................................................ .
FT Toggle Flip-Flop ..........................................................................
FTRD Toggle Flip-Flop with Reset Direct ..............................................
FTP Toggle Flip-Flop with Parallel Enable ......................................... .
FTPRD Toggle Flip-Flop with Parallel Enable, Reset Direct ................... .
FTR Toggle Flip-Flop with Reset ... ..................................................... .
FTS Toggle Flip-Flop with Set ............................................................
FT2 2-lnput Toggle Flip-Flop ............................................................. .
FT2R 2-lnput Toggle Flip-Flop with Reset ........................................... .
NDFF Negative Edge Flip-Flop Primitive ............................................. ..
PDFF Positive Edge Flip-Flop Primitive ............................................... .
DECODERS/ENCODERS
D2-4 1-of-4 Decoder ........................................................................... . 2 2
D2-4E 1-of-4 Decoder with Enable ........................................................ . 2 2
74-139 1-of-4 Single Decoder with Enable, Low Output ........................ . 2 2
5-36
XC 3000 XC2000
MULTIPLEXERS (Continued) #CLBs #CLBs
RD4 4-Bit Data Register..... ..... ..... ....... ..... ..... ..... ....... ..... ....... ..... ......... 2 4
RD4RD 4-Bit Data Register. ......... ..... ....... .......... ......... ........ ...... ............... 2
RD8 8-Bit Data Register ..... ..... ..... ....... ..... ..... ..... ....... ..... ...... ...... ...... ... 4 8
RD8RD 8-Bit Data Register with Reset Direct.......................................... 4
RD8CR 8-Bit Data Register with Clock Enable, Reset ............................. 4 8
HX174 Hex 0 Register with Master Reset ... ..... ......... ... ..... ...... ...... ...... ... 4
HX273 Octal 0 Flip-flop........................................................................... 4
HX298 Quad 2 Input Flip-flop ............................................................... '" 4
HX374 Octal 0 Flip-flops with 3-State Outputs ............ ............ .......... ..... 4
HX377 Octal 0 Flip-flops with Clock Enable ............ ....... ............ ............ 4
HX577 Octal 0 Flip-flops with Reset and 3-State Outputs ........ .............. 4
Serial to Parallel
RS4 4-Bit Shift Register ...................................................................... 2 4
II
RS4RD 4-Bit Shift Register with Reset Direct .......................................... 2
RS4C 4-Bit Shift Register with Clock Enable ....................................... .. 2
RS4CRD 4-Bit Shift Register with Clock Enable, Reset Direct ................. .. 2
RS4CR 4-Bit Shift Register with Clock Enable, Reset ............................ . 2
74-195 4-Bit Serial to Parallel SR with ParEna, MRLow ....................... .. 3 5
74-194 4-Bit Bi-Directional SR with ClkEna, ParEna, MRLow ............. .. 5 12
RS8 8-Bit Shift Register .................................................................... .. 4 8
RS8RD 8-Bit Shift Register with Reset Direct .......................................... 4
RS8R 8-Bit Shift Register with Rese!.. .................................................. . 4 8
RS8C 8-Bit Shift Register with Clock Enable ....................................... .. 4
RS8CRD 8-Bit Shift Register with Clock Enable, Reset Direct ................. .. 4
RS8CR 8-Bit Shift Register with Clock Enable, Reset ............................ . 4 8
RS8PR 8-Bit Shift Register with Parallel Enable, Reset ......................... . 4 8
74-164 8-Bit Serial to Parallel SR with Master Reset Low ............ ......... . 5 8
HX164 8-Bit Serial In-Parallel Out Shift Register .................................... 5
HX166 Parallel Load 8-Bit Shift Register ............ ........................... ......... 6
5-37
Macro Lists
XC 3000 XC2000
REGISTERS (Continued) #CLBs #CLBs
HX179 4-Bit Parallel Access Shift Register...................... ..... ......... ......... 5
HX194 4-Bit Bidirectional Universal Shift Register. ....... ..... ....... .... .......... 7
HX195 4-Bit Parallel Access Shift Register. ...... ...... ...... ..... ....... ... ........... 3
HX198 8-Bit Bidirectional Shift Register ....... ...... ...... ..... ..... ....... ..... ... ...... 14
HX199 8-Bit Shift Register with Clock Inhibit .......................................... 7
HX595 8-Bit Shift Register with 3-State Register Output........ ............ .... 9
COUNTERS
Modulo 2
C2BCP 1-Bit Binary Counter wI Clock Enable, Parallel Enable .............. .
C2BCPRD 1-Bit Binary Counter wI ClkEna, ParEna, Reset Direct .............. .
C2BCR 1-Bit Binary Counter with Clock Enable, Reset ...........................
C2BCRD 1-Bit Binary Counter with Clock Enable, Reset Direct... ............. .
C6JCR 3-Blt Johnson Counter with Clock Enable, Reset... ..................... 2 ......................... 3
Modulo 8
5-38
XC 3000 XC2000
COUNTERS (COntinued) #CLBs #CLBs
C12JCR 6-Bit Johnson Counter with Clock Enable, Reset ....................... . 3 ......................... 6
Modulo 16
C16BARD 4-Bit Binary Ripple Counter with Reset Direct... ......................... . 2 ......................... 4
C16BCRD 4-Bit Binary Counter w/ ClkEna, Reset Direct ............................ . 3 ......................... 4
C16BCP 4-Bit Binary Counter w/ ClkEna, Parallel Enable ....................... .. 5 .........................
C16BCPRD 4-Bit Binary Counter w/ ClkEna, ParEna, Reset Direct ............... 5 ......................... 6
74-161 4-Bit Binary Counter w/ ClkEna, ParEna, MRLow ...................... . 6 ., ....................... 8
C16BCPR 4-Bit Binary Counter w/ Clock Enable, ParEna, Reset ............... . 6 ......................... 10
74-163 4-Bit Binary Counter w/ ClkEna, ParEnaL, Reset Low ............... . 7 .........................
C16BPRD 4-Bit Binary Counter w/ Parallel Enable, Reset Direct ............... . 4 ......................... 5
C16BUDRD 4-Bit Binary Up-Down Cntrw/ ParEna, ResetDir ....................... . 5 ......................... 8
C16JCR 8-Bit Johnson Counter with Clock Enable, Reset ....................... . 4 .......................... 8
HX161 Presettable Binary Counter ......................................................... 6 .........................
HX163 Synchronous Binary Counter with Sync Clear ....... ,.................. .. 8 . . . . . . . . . . 0' ••••••••••••••
C256BCRD 8-Bit Binary Counter with Clock Enable, Reset Direct ................ . 7 .........................
C256BCR 8-Bit Binary Counter with Clock Enable, Reset ......................... .. 7 .........................
C256BCP 8-Bit Binary Counter w/ ClkEna, Parallel Enable ........................ . 8 ••• e . . . . . . . . . . . . . . . . . . . . .
C256BCPRD 8-Bit Counter wI. ClkEna, ParEna, Reset Direct ........................ .. 8 .........................
C256FCRD 8-Bit. Mod 256 Feedback SR w/ ClkEna, ResetDir .................... .. 6 ......................... 9
C8UDlD 8-Bit loadable Up/Down Counter .............................................. .. 9 .........................
C16UDlD 16-Bit loadable Up/Down Counter .............................................. 18 .........................
5-39
Development System
Hardware Requirements
Xilinx provid&s an integrated Development System for To assure integrity, all Xilinx software is tested on IBM
design and implementation of LCA devices. The XACT systems and several compatible systems. LCA
Development System operates on an PC/AT or PS/2 development software includes some of the first DOS-
model 60 or 80, Apollo, Sun-3, Sun-4, and DECstation based programs to make extensive use of the "protected"
3100 and provides a range of support features. This mode of the processor. This has exposed protected mode
provides the user with an effective, convenient, low-risk IBM-incompatibilities of some clones, usually in the BIOS
method of logic-design entry, Simulation, LCA generation or Keyboard Controller. Xilinx software includes system
and verification for single-chip logic designs of up to 9000 exercises called PMTEST and PMINFO to help test IBM
gates. In addition, several popular PC and workstation compatibility and measure relative performance.
CAE vendors have developed and offer design-entry and Note that this amount of memory must be available to
simulation programs compatible with the XACT XACT, Le., it does not include the memory used for other
Development System resident programs.
PC REQUIREMENTS Note also that the Compaq 386 has only 640 Kbytes of its
first megabyte available to any user.
The recommend&d PC-system configuration needed to
run the XC2000 and XC3000 Series XACT Development PC I/O Ports
System consists of:
• A 20-MHz "386" PC/AT or PS/2 model 60 or better The LCA Development System requires several I/O ports.
• 40 M byte hard disk drive plus a 1.2 Mbyte high-density A parallel port is needed for the software execution
floppy disk drive protection key. The key must be in place to allow Xilinx
software to execute but is virtually transparent, and the
• Two RS-232-C serial ports
port can be used simultaneously for a parallel printer orthe
• One parallel port Xilinx download cable. Several printer types are supported
• EGA or VGA Graphics Display for text or graphic hard copy. Serial COM ports are used for
• Mouse a mouse, the XACTOR In-Circuit Design Verifier and the
• MS-DOS version 3.0 or higher Configuration PROM Programmer.
• IBM-compatible BIOS and keyboard
PC Mouse
• A math co-processor can enhance performance of APR
by 10 or 20% The Xilinx Development System programs are compatible
• Extended memor as follows. with several varieties of mice offered for the PC. These
include Mouse Systems PC Mouse (no device driver
Total Memory Required for required), Microsoft (serial or parallel), LogiTech C7 and
LCAGates XACT3.0 the FutureNet mouse. The Xilinx software supports any
2000 or less 2.50 Mbyles mouse directly that emulates the PC mouse or has a
3000 3.25 Mbyles device driver that provides Microsoft compatibility and
4200 4.00 Mbyles defines the PC COM port.
6400 5.25 Mbyles
9000 6.50 Mbyles Please note however, only the Mouse System M4 and the
LogiTech C7 will work with the VIEWlogic software,
VIEWdraw-LCA and VIEWsim.
It..
5-40
E:XIUNX
When the system is powered up it uses commands from The workstation system requirements needed to run Xilinx
the DOS CONFIG.SYS file to install selected device software are:
driver-programs (such as Mouse driver) in memory
and define buffer and file sizes. Exampls of these ApOllO Requirements
statements are: DN4000 Series
• Apollo Operating System SR10.1
device=C:\lib\msmouse.sys /1
• Mentor Graphics Version 7.0
fi1es=10
buffers=20 • 60 Mbytes allocated for Xilinx designs
• 16 Mbyes of RAM
After CONFIG.SYS functions are implemented the system • Color Monitor
executes the commands found in the AUTOEXEC.BAT • DOMAIN XII VI
file. This file contains DOS commands such s:
Sun-3 Requirements
path=c:\; ... c:\xact;c:\dash-1ca; ...
set xact=c:\xact Series 960 and above
set grmode=ega • Sun Operating System OS4.0
set swmode=9 • 60 Mbytes allocated for Xilinx designs
set minbytes=65000 • 16 Mbytes of RAM
• Color Monitor
The first line shows the portion of the path established by
• X-Windows
the XACT and DASH-LCA installation procedures. These
are the default directories created and used in the Xilinx
installation procedures. The SET SWMODE= sets a Sun-4 Requirements
parameter defining one of several alternative ways of Sun-4 & SparcStation Series
switching the processor from protected to real mode. • Sun Operating System OS4.0
Several alternatives are made available in order to • 60 Mbytes allocated for Xilinx designs
accommodate various "clone" idiosyncrasies. Possible
• 16 Mbytes of RAM
values are 9 (default), 10, 7, 4, and for 80386 based
systems, 3. • Color Monitor
• X-Windows
Seethe Xilinx installation instructions and PC manuals for
additional information. DECStation Requirements
DECstation 3100 Series
• Worksystem V2.2
• 60 Mbytes allocated for Xilinx deSigns
III
• 16 Mbytes of RAM
• Color Monitor
5-41
The Programmable Gate Array Company
5-42
SECTION 6
Applications
2 Product Specifications
4 Technical Support
5 Development Systems
6 Applications
7 Article Reprints
8 Index
Applications
TIL-MSI was originally defined to fit into a 16-pin package Most designers want to estimate density and performance
and to provide maximum flexibility, so that each standard
part could be used in a myriad of applications. Some
before they begin an LCA deSign, and some want to know
the definition of equivalent gates. While the data sheets
provide worst-case guaranteed parameters, many
II
functions are therefore overdesigned (counters and shift
registers have parallel inputs and outputs, when few designers need additional information about input and
applications need both) and some are crippled by the 16- output characteristics, power consumption, crystal
pin limitation (notably the up-down counters). oscillator design, and the exact interpretation or certain ac
parameters. CLB flip-flops show excellent recovery from
PAL devices suffer from the rigidity of the AND-OR metastable problems, an important concern with
architecture and from the fixed assignment of flip-flops to asynchronous interfaces.
output pins. While the number of inputs is generous, ideal
forwide decoding, the limited numberof product terms that
can be ORed together makes many designs inefficient
and slow. The number of flip-flops available in PALs is
very limited.
6-1
Applications
COMBINATORIAL FUNCTIONS Using the fast flip-flops and distributed logic in the LCA to
their best advantages, a synchronous presettable counter
The 5-input function generator of the XC3000 family CLBs of arbitrary length has been demonstrated to run at
offers unlimited flexibility to implement anyone of the more 40 MHz. This is much faster than any available popular
than 4 billion (2 32) possible functions of up to five variables microprocessor peripheral counter/timer.
in one CLB, all with the same combinatorial delay. The
4-input function generator in the XC2000 family can State-machine design is another example in which the
implement anyone of the 64K (216) possible functions of creative use of CLB resources can result in a straightfor-
four variables. The logic designer should take advantage ward and easily understood solution.
of this flexibility while avoiding the possible speed penalty
imposed by the limitation to only five or four inputs. This As explained in the beginning of this chapter, the CLB flip-
may lead to logic partitioning that is different from flops are "metastable-resistant;" they resolve metastable
traditional design or from MSI or PAL implementation. situations typically within a few nanoseconds. Designers
are nevertheless encouraged to avoid asynchronous
Majority logic is just one example in which the CLB excels: designs whenever possible. The combination of very fast
A 5-input majority function would use 29 gates when CLB flip-flops with relatively slow and layout-dependent
implemented with 2-input NANOs and inverters, but it fits interconnects can lead to internal decoding spikes and
into the combinatorial portion of one XC3000-series CLB. glitches that cannot be observed with an oscilloscope.
However, they can play havoc with internal asynchronous
Address decoding is the classical strength of PAL devices. logic. The high-speed, low-skew global clock lines and the
It is done efficiently in LCA devices if the complete function individual Clock Enable inputs on each CLB favor synchro-
includes the combination of several addresses or groups nous design approaches that are inherently safer and
of addresses. more predictable.
ALUs consume many LCA-device resources, but adders SYSTEM DESCRIPTIONS
or subtractors can be implemented quite efficiently, even
using carry-look-ahead for functions that exceed a width LCA devices are universal programming building blocks
of eight bits. that are used in a wide variety of systems. An 8-digit
frequency counter implemented in a XC2064 is a simple
SEQUENTIAL FUNCTIONS illustration. A PS/2 Micro Channel Controller and a DRAM
Controller/Error Corrector demonstrate the versatility of
LCA devices offer an abundance of flip-flops, from 119 in the LCA in speed-critical applications. Some of the de-
the XC2064 to 928 in the XC3090. Each CLB flip-flop signs are available, as indicated, from Xilinx and may be
(64 in the XC2064, 128 in the XC3020, 640 in the XC3090) obtained by calling the applications hot line.
has a ''free'' combinatorial function generator available as
its input. This simplifies the design of shift registers The purpose of this applications chapter is not to provide
and counters. cookbook solutions, but rather to stimulate the imagina-
tion, convey ideas and demonstrate that LCA devices offer
The "Corner Bender" serial-parallel or parallel-serial a better solution for a large variety of digital designs.
converter deSign, is a two-dimensional shift register array
that fits very efficiently into an XC2064 or half of an
XC3020, with 100% utilization of the CLB flip-flops.
6-2
l:XIIJNX
BY DAVE LAUTZENHEISER
INTRODUCTION If the desired LCA device has enough I/O pins, the next
step is to count the required storage elements. Table 1
Fileld Programmable Gate Arrays are available in a range shows both logic-block storage elements and 1I0-block
of densities and speed grades. Before committing re- storage elements. Logic-block storage elements should
sources to design implementation, the user should make be considered first, since they are the most flexible. If the
an estimate to determine which FPGA best fits the specific required number of storage elements is less than the
application. Size and performance estimates cannot be number of logiC storage elements, the desired functions
expected to provide exact details, but they provide useful can probably be performed in the chosen LCA device.
guidelines for device selection and cost estimates. A
complete design is always the final test for both density In some cases, the I/O-block storage elements can also be
and performance. used to meet storage-element requirements. In particular,
if the number of additional storage elements required
Design-fit estimates can be done in two steps. The first is beyond the available logiC storage elements is less than
a quick I/O and storage element count, with no regard for the number of unused I/O pins, then the desired functions
performance. The second step counts logic blocks based may still fit into the chosen device.
on details of the intended circuit, and includes gross
performance estimates, still without regard for routing The following two examples illustrate the Step One quick
delays. Performance estimates should always be estimation procedure:
considered "best-case," recognizing that actual system
performance can only be verified on a completed design. Example 1. An B-blt microprocessor peripheral.
Function 1/0 requirements
STEP 1 : I/O and Storage Element Fit
8·bit data bus 8
A quick initial estimate of how a system fits a specific LCA 5 bus-control signals 5
device can be made by counting the required input and 16 bits of output 16
4 bits of output control 4
output pins and internal storage elements. Table 1 lists the 2 internal control registers
Xilinx XC2000- and XC3000-series Logic Cell Array Interrupt control logic
devices and their respective I/O and storage element
counts. To estimate a fit, first countthe required inputs and TOTAL 33
outputs and compare the total with the I/O pin count of the
desired device. If the desired functions require more I/O Even the smallest Logic Cell Array, the XC2064, passes
than listed for a device, the designer must either select a the 1I0tes!. It has 58 user I/O in its 68-pin PLCC package.
larger device or package, or reduce the I/O requirements.
Function Storage Elements
Logic 1/0
Control regist9l's (assume 8 bits) 16
I
Buffered input shift register 16
Maximum Block Block Miscellaneous control logic 10
Device 1/0 Storage Storage
TOTAL 42
XC2064 58 58 58
XC2018 74 100 100
XC3020 64 128 128 All of the storage elements can be put into logic storage in
XC3030 80 200 160 the XC2064. The XC2064 should fit this application,
XC3042 96 288 192
XC3064 120
provided the desired performance can be aChieved.
448 240
XC3090 144 640 288
6-3
Estimating Size and Performance
Example 2. A memory controller for a 32·blt hIgh With two storage elements per logic block, the XC3042
performance processor. can provide up to 288 storage elements. Based on this
estimate, the desired functions should fit into the device.
Function 1/0 Requirements Some caution is indicated for two reasons. First, the 1/0
count is very near the limit of the device. This could cause
32-bit processor data bus 32 some routing congestion in the 1/0 area, making a higher
32-bit processor memory bus 32
pin-count device a better choice. Second, high
32-bit memory bus 16 (muxed)
32-bit control register performance requires making the best use of device
32-bit DMA control features. The 32-bit bus may impose critical performance
Address multiplexing control requirements. Only the XC3064 and XC3090 permit a
RAS/CAS/Refresh generation 3 32-bit internal bus, based on the number of available Long
Memory error check and correct Lines. Choosing the XC3064 could address the 1/0
Processor and memory timing 10 requirements as well as the performance needs.
VO SERIAL DATA
cpu
CONTROL REGISTER RD4 2CLBs
AO
A1 DECODER HX138 SCLBs
READIWRITE REGISTER ROB 4CLBs
SHIFT REGISTER OUT RS8PR 4CLBs
DECODER
SHIFT REGISTER IN RS8 4CLBs
REGISTER IN 3-STATE HX374 4CLBs
TOTAL 23 CLBs
6-4
In many schematics there are collections of random gates Estimating the block count for integrating PLD devices is
that need to be considered, along with the higher level more difficult. Each PLD output should be counted as at
functions such as counters, decoders and multiplexers. least one block. PLD devices using five or fewer of the
The following technique can be used to estimate the logic inputs, will require only one block per output for the
blocks required for random logic. Begin at an output point XC3000 family (four inputs for the XC2000 family). For
and move back along the path collecting gates until the complex equations using more than five (or four) inputs, a
number of inputs is four for XC2000-family devices, orfive conservative estimate is to use th ree blocks per output pin.
for XC3000-family devices. These gates can be marked in
some way to show that they occupy a single logic block. Decisions about the appropriate device can be reviewed
Blocks identified by this method are added to the block as more information is collected. Block count estimates
count from the macro list analysis. Figure 2 shows an which are near the limit of a device, either in block count or
example of this gate-collecting technique. in 1/0 and storage element count, may suggest use of the
next higher density device.
8~=:C::J-_
TC
86
CET--~----------------------------------~~=+~~
CEP
~~~--------~-I
~ ,~,.".'*".".".,."' ' ' '.,.'".", ,.»' ' '.' ' , ,' ' ' ' ' '.' ' ' "'t·",~" " "·" " ", ·, ,",·~
II
D 0
D 0 00
113302C
6-5
Estimating Size and Performance
ESTIMATING PERFORMANCE for routing (10 ns) and 8 ns for setup gives a total delay of
48 ns. This should permit operation at a system clock rate
After selecting the right LCA device based on logic of up to 20 MHz.
resources, an estimation of performance is often the next
step. If the system clock rate is less than 20% of the flip- SUMMARY
flop toggle rate of the selected device, then the The final determination whether a logic device meets the
performance goals can usually be met easily. In cases of goals for integration and performance can come only after
higher system clock rates or very complex functions, a the design has been completed. For Field Programmable
more detailed analysis may be required. Gate Arrays, estimating logiC capacity and performance
should precede device selection. If the design fits,
The macro library for each device family includes the the XACT development system and the simplicity of in-
number of logic-block levels used for each listed function; system design verification assures cost-effective and
the LCA data sheet specifies the block delay for each level. rapid design implementation.
Some routing delay, which can add 25 - 50%, must be
added to the block delay. Of course, specifications sometimes change during
execution of a design. LogiC changes may result
As an example, a circuit might have three levels of blocks in different requirements for 1/0 and logic blocks. In
in the path from one clock edge to another. For a device such cases, the Xilinx product line simplifies the migration
with 10 ns block delays, this gives 30 ns delay from the first to a compatible array that meets the new requirements.
clock to the setup required forthe next clock. Allowing 30%
6-6
Designing with the
XC3000 Family
Global and Alternate Clocks Buffers Active High 3-state is the same as active Low enable.
There are two high-fan-out, low-skew clock resources.
In other words: Aone onthe Tpinof a TBUF or an OBUFZ
The global clock originates from the GCLK buffer in the
3-states the output, and a zero enables it.
upper left corner of the chip and the alternate clock
originates from the ACLK buffer in the lower right corner of
the chip. InputlOutput Blocks (lOBs)
Unused lOBs should be left unconfigured. They default to
These resources drive nothing but the K pins (clock pins) inputs pulled High with an internal resistor.
of every register in the device. They cannot drive logic
inputs. In the rare case where this connection is required, lOB pull-up resistors cannot be used with lOB outputs,
tap a signal off the input to the clock buffer and route it to only on pins that are inputs exclusively.
the logic inputs.
Configurable Logic Blocks (CLBS)
The global and alternate clocks each have fast CMOS
inputs, called TCLKIN and BCLKIN respectively. Using CLBs have two flip-flops (not latches). They share a
these inputs provides the fastest path from the PC board common clock, a common reset, and a common clock.
to internal flip-flops and latches because the signal by- enable signal.
passes the input buffer. CMOS levels on the input clock
signal must be guaranteed. Asynchronous preset can be achieved by the asynchro-
nous reset, by just inverting D and Q of the flip-flops.
To specify the use of TCLKIN or BCLKIN in a schematic,
connect an IPAD symbol directly to a GCLK or ACLK
symbol. Placing an IBUF between the IPAD and ROUTING RESOURCES
GCLK or ACLK will prevent the TCLKIN and BCLKIN from
Horizontal Long Lines
being used.
The number of Horizontal Long Lines (HLL) per device is
Always use GCLK and ACLK for the highest fan-out double the number of rows of CLBs.
clocks.
1/0 Clocks
The number of TBUFs that drive each Horizontal Long
Line is one higher than the number of columns on the
device.
II
There are a total of eight different 1/0 clocks, two per edge
on each of the four edges. Part Rows x TBUFs
Name Columns CLBs HLL per HLL
1/0 storage elements can be configured to be latches or
flip-flops. Clocking polarity is programmable perclock line, 3020 8x8 64 16 9
not per lOB. A clock line that triggers a flip-flop on the rising 3030 10 x 10 100 20 11
edge can be an active Low Latch Enable (latch transpar- 3042 12 x 12 144 24 13
ent) and vice versa. 3064 16 x 14 224 32 15
3090 20 x 16 320 40 17
Crystal Oscillator
Connects to alternate clock buffer, ACLK, not to GCLK. Continued at the bottom of next page
6-7
Designing with the
XC2000 Family
Global and Alternate Clocks Buffers CLBs have one storage element that can be configured as
a flip-flop or a latch.
There are two high-fan-out, low-skew clock resources.
The global clock originates from the GCLK buffer in the CLB storage elements have both an asynchronous set and
upper left corner of the chip and the alternate clock an asynchronous reset.
originates from the ACLK buffer in the lower right corner of
the chip.
ROUTING RESOURCES
The global clock buffer, GCLK, drives the Band K pins of
the Configurable Logic Block (CLB). Horizontal Long Lines
There is one Horizontal Long Line per routing channel.
The alternate clock buffer, ACLK, drives the B, C, and K
pins of the Configurable Logic Block (CLB). The crystal There are no internal 3-state buffers on the chip.
oscillator drives the ACLK.
Vertical Long Lines
Always use GCLK and ACLK for the highest fan-out
clocks. There are three Vertical Long Lines per routing channel,
one general purpose, one for the global clock net and one
I/O Clocks for the alternate clock net.
There are four different I/O clocks, one per edge. CLB pins with Direct Access to Long Lines
I/O flip-flops are positive-edged triggered. A- Horizontal Long Line above the CLB.
B- Global clock buffer, Middle and Left Vertical Long
Line.
INPUT/OUTPUT BLOCKS (lOBS) C- Middle and Left Vertical Long Line.
D- Horizontal Long Line below the CLB.
Unconfigured lOB outputs must not be left floating. Con- X- To Left Vertical Long Line.
figure them as outputs and drive them from internal logic y- To Middle Vertical Long Line.
or leave them unconfigured and pull them up with an
external resistor.
T and I pins of TBUFs have limited interconnect resources, CLB Pins with Direct Access to Long Lines
A- Lower Horizontal Long Line.
Never use fewer than four TBUFs per Horizontal Long
EC- Left Middle Vertical Long Line.
Line. When using TBUFs for multiplexing applications,
B- Left Middle Vertical Long Line.
using fewer than four wastes resources. Use CLBs for
C- Right Middle Vertical Long Line
multiplexing instead.
K- Rightmost and Leftmost Vertical Long Lines
(ACLK and GCLK).
Vertical Long Lines
E- Right Middle Vertical Long Line.
There are four Vertical Long Lines per routing channel, two D- Upper Horizontal Long Line.
general purpose, one for the global clock net and one for RD- Left Middle Vertical and Lower Horizontal
the alternate clock net. Long line.
1976
6-8
Additional
Electrical Parameters
Application Brief
Output Impedance
PULL·UP RESISTOR VALUES
Sinking, near ground: 25n
Sourcing, near Vcc: son
lOB Pull-ups 40 to 150 kn
DONE Pull-up 2to 8 kn Output Short Circuit Current
Long line Pull-up (each) 3t010kn Sinking current by the LCA 96mA
Sourcing current by the LCA 60mA
All inputs, except PWRDN, and XTL2 when configured as AC Parameters Fast' Slow'
the crystal oscillator input, have limited hysteresis,
typically in excess of 200 mV for TTL input thresholds, in Unloaded Output Slew Rate 2.8 V/ns 0.5 V/ns
excess of 100 mV for CMOS thresholds. Unloaded Transition Time 1.45 ns 7.9 ns
Additional rise time for 812 pF 100 ns 100 ns
Required Input Rise and Fall Times normalized 0.12 ns/pF 0.12 ns/pF
Additional fall time for 812 pF 50 ns 64 ns
For unambiguous operation, the input rise time should not normalized 0.06 ns/pF 0.08 ns/pF
exceed 200 ns; the input fall time should not exceed 80 ns.
, "Fast" and "Slow" refer to the output programming option.
These values were established through a worst-case test
with internal ring oscillators driving all 110 pins except two, There is good agreement between output impedance and
thus generating a maximum of on-Chip noise. One of the
remaining 110 pins was then tested as an input for single-
edge response, the other one was the output monitoring
loaded output rise and fall time, since the rise and fall time
is slightly longer than two time constants. II
the response. This specification may, therefore, be overly
pessimistic, but, on the other hand, it assumes negligible
PC board ground noise and good Vcc decoupling.
6-9
Additional Electrical Parameters
LCA power dissipation is largely dynamic, due to the 4.5 V 25°C 687 kHz
charging and discharging of internal capacitances. The 5.0 V 25°C 691 kHz
dynamic power, expressed in mW per MHz of actual node 5.5 V 25°C 695 kHz
4.5 V -30°C 966 kHz
or line activity is given below.
4.5 V +130°C 457 kHz
Clock line frequency is easy to specify, but the designerwill
usually have great difficulty estimating the average fre- CRYSTAL OSCILLATOR
quency on other nodes.
The on-chip oscillator circuit consists of a high-speed, high
Two extreme cases are: gain inverting amplifier between two device pins, requiring
an external biasing resistor R1 of 0.5 to 1 Mil.
1. Binary counter, where halfthe total power is dissipated
in the first flip-flop. A series-resonant crystal Y1 and additional phase-shift-
ing components R2, C1, C2 complete the circuit.
2. A shift register with alternating zeros and ones, where
the whole circuit is excercised at the clocking speed. Fundamental Frequency Operation up to 24 MHz:
Dynamic Power C1 = C2 =34pF
(mW/MHz) R2 = 1 kn up to 12 MHz, 800 n to 520 n for 15 to 24 MHz
Output with 50 pF load" 1.9 Third Ovenone Operation from 20 MHz to 72 MHz:
Global Clock (XC3020) 1.7
Global Clock (XC3090) 3.6 Replace C2 with a parallel resonant LC tank circuit tuned
CLB with Local Interconnect 0.36 to '" 213 of the desired frequency, I.e., twice the crystal
Horizontal Long Line (XC3020) 0.09 fundamental frequency.
Horizontal Long Line (XC3090) 0.15
Vertical Long Line (XC3020) 0.08 Frequency LCTank
Vertical Long Line (XC3090) 0.19 (MHz) L(~H) C(pF) Freq (MHz) R2(n) C1 (pF)
Input without Pull-up 0.075
32 60 20.6 430 23
35 44 24.0 310 23
"Add 2.5 mW/MHz for every 100 pF of additional load 49 31 28.6 190 23
72 18 37.5 150 12
3 outputs at 5 MHz 28
20 outputs at 0.1 MHz 4
Global Clock at 20 MHz 34
10 CLBs at 5 MHz 18
40 CLBs at 0.2 MHz 3
16 Vertical Long Lines at 1 MHz 1
20 Inputs at 4 MHz 6 R1
Total 94mW R2
1158028
CCLK frequency is fairly stable over Vcc' varying only
0.6% for a 10% change in VcC' but is very temperature
dependent, increasing 40% when the temperature drops
from 25°C to -30°C. Crystal Oscillator
6-10
LeA Performance
Application Brief
Still, most designer want to evaluate the possible perform- ·50 ·70 ·100 ·125
ance, well before they have finished the design. clock-to-output 12 ns 8 ns 7 ns 6 ns
routing 12 ns 8 ns 6 ns 6 ns
Here are some guidelines for XC3000 family devices: logic delay 14 ns 9 ns 7 ns 6 ns
routing 1 ns 1 ns 1 ns 1 ns
1. A simple synchronous design-like a shift register, logic set-up 12 ns 8 ns 7 ns 6 ns
where a flip-flop feeds a flip-flop in the next vertical or clock period 51 ns 34 ns 28 ns 25 ns
horizontal CLB through the one level of combinatorial clock frequency 20 MHz 29 MHz 36 MHz 40 MHz
logic in front of the target flip-flop:
Therefore, as a rule of thumb, the system clock rate should
·50 ·70 ·100 -125
not exceed one third to one half of the specified toggle rate.
clock-la-output 12 ns 8 ns 7 ns 6 ns
routing 1 ns 1 ns 1 ns 1 ns
Simple designs, like shift registers and simple counters, can
logic set-up 12 ns 8 ns 7 ns 6 ns run faster, approximately two thirds of the specified toggle
rate.
clock period 25 ns 17 ns 15 ns 13 ns
clock frequency 40 MHz 59 MHz 67 MHz 77 MHz
These numbers assume synchronous clocking from the
2. A similar design with flip-flops several rows or columns global clock lines. Remember, these are all worst-case
apart would add routing delay: numbers, guaranteed over temperature and supply volt-
age. Nobody should design with typical numbers.
I- SINGLE LEVEL
~-
TWO·LEVEL
·1
I-
CLOCK TO OUTPUT
TCKO ~ I+--
seTUP
T,CK --I+-
CLOCK TO OUTPUT
TCKO --..j
COMBINATORIAL
T,CK
-+I II
CLB CLB CLB
INTERCONNECT
0 0 0 0 0 0
CLOCK-4--______________________________~------------------------------~ 115904
Figure 1. Critical Timing Parameters for Clocked CLB Driving Clocked CLB Directly (Single Level)
, and Driving it Through Additional Combinational Logic (Two-Level)
6-11
LCA Performance
DESIGNING FOR HIGHEST DATA TRANSFER RATE 16 - 2 - 3.5 = 10.5 ns for the 3020-125
BETWEEN XC3000-FAMIL Y LCAs 17 - 2 - 3.9 = 11.1 ns for the 3020-100
20 - 3 - 4.5 = 12.5 ns for the 3020-70
Worst-case analysis of a synchronous data transfer be-
tween XC3000-family devices postulates that the sum of Under these assumptions, the worst case (shortest) value
clock-to-output propagation delay of the sending device, for the clock period is:
plus the input-to-clock set-up time of the receiving device,
must be less than the clock period. 14.5 + 10.5 = 25 ns, i.e. max 40 MHz for the 3020-125
15.9 + 11.1 = 27 ns, i.e. max 37 MHz forthe 3020-100
The inherent freedom in clock and signal routing makes it 20.5 + 12.5 = 33 ns, Le. max 30 MHz for the 3020-70
impossible to give exact values for an unprogrammed lCA
without specifying certain restrictions: Bypassing the input flip-flop in the lOB and going directly
to the 01 input of the closest CLB is another, non-obvious,
On the transmitting lCA, the clock-pin to output-pin propa- way of improving performance by 8 ns for the 3020-125
gation delay is minimized ifTClKIN or BClKIN are chosen device, by 9 ns forthe 3020-100 device and by 10 ns for
as clock inputs. They are CMOS-level only, and offer the the 3020-70 device.
shortest on-chip clock delay.
If this is notlast enough, there are design methods that can
The clock-pin to output delay is then improve the performance. let us assume a -100 device.
The easiest and safest method is to increase the clock
2 + 3.5 + 9 = 14.5 ns for the 3020-125
delay on the receiving lCA, thus reducing the apparent
2 + 3.9 + 10= 15.9 ns for the 3020-100
input set-up time. Changing to a direct input (instead of
3 + 4.5 + 13 = 20.5 ns for the 3020-70
TClKIN) adds 2 ns to the clock delay and subtracts it from
the input set-up time.
On the receiving lCA, the input-pin to clock-pin set-up time
is the specified 1/0 pad input set-up time (parameter TPICK More aggressive methods of increasing clock delay inside
in the lOB switching characteristic table of the XC3000 or outside the receiving LCA must be used with care, since
family data sheet) minus the actual delay for clock buffer- they might reduce the ''best case" set-up time (fast proc-
ing and routing. ess, low temperature, high VCC) to a value of less than
zero, Le., make it a hold time requirement, which, in
Assuming the same clock buffer choice on the receiver as conjunction with a best case very fast transmitting device,
on the transmitter, the longest input-pin to clock-pin set-up
can lead to problems.
time is:
T OKPO ----I
CLOCK
115903
6-12
INPUT SET-UP TIME ON A XC3000-FAMILY LCA IS WHY ARE THERE NO GUARANTEED MIN DELAY
BETTER THAN THE SPECIFICATION. SPECIFICATIONS?
The Xilinx XC3000-Family data sheet specifies a worst- IC manufacturers do not usually guarantee minimum
case input set-up time of 17 ns for the -100 speed grade propagation delay values, though some specify a token
(parameter#1 on page 2-46), but this is the data input pad min delay of 1 ns. There are compelling reasons:
set-up time with respect to the Internal lOB clock, not with
respect to the clock input pad. These short delays are extremely difficult to measure on a
production tester. Even if it were possible, the necessary
Any delay from clock pad to lOB clock must be subtracted tester guard-banding might make the result
from the specified set-up value in orderto arrive at the true meaningless.The spread between a conservative worst-
systems set-up time as seen on the device package pins case maximum value and a similarly conservative worst-
(pads) for data and clock. Since the internal clock delay case (best-case?) minimum value would be surprisingly
can be manipulated by the user, Xilinx cannot specify the large. There are five reasons:
systems set-up time.
1. Temperature. CMOS propagation delays decrease
The shortest possible clock delay from the package pin to approximately 0.3% per degree C.
the lOB clock is achieved by selecting the CMOS
compatible clock inputs TClK or BClK. The guaranteed 2. Supply Voltage. CMOS propagation delays are just
max value for their delay is 4.9 ns (XC3020-1 OO), the sum about inversely proportional to Vee'
of 2 ns forpad-to-ClKIN plus 2.9 ns forthe clock buffer and
clock distribution. 3. Test Guardband. The max delay test is performed at
a temperature well above TMAX and a supply voltage
Xilinx does not guarantee any shortest values for all these well below Vee MIN. The accepted max delay is also
parameters. An unrealistic worst-worst case analysis less than the data sheet value. Equally conservative
might, therefore, assume two extreme values: methods applied at the opposite extremes would give
very short values.
17 ns set-up time for a slow data input with an infinitely
fast clock path 4. Process Variations. lCAs are sorted into a few speed
4.9 ns hold time for an infinitely fast data input com- classes. A part marked -50 might have barely missed
bined with a slow clock path. the -70 specification in only a few or perhaps only one
parameter. IC manufacturers may sometimes mark
That is a meaningless mathematical exercise. In reality, all down (call a -70 part a -50 part) in order to adjust
these delays track very well over temperature, supply production yield to market demand. This increases the
voltage and processing variations, never deviating more spread even more.
than 30% from each other's normalized value. When one
parameter is at its absolute max value, any otherparame- 5. Process Evolution. As IC technology improves,
ter will be between 54% and 100% of its max value smaller geometries reduce not only device size and
(54 = 100 x 0.7/ 1.3). The longest required set-up time for cost, but also propagation delay. Tight minimum
the data input with respect to the CMOS compatible clock specifications would be a hindrance to progress.
input is, therefore, 14.4 ns (17 ns minus 54% of 4.9 ns).
The shortest data set-up time with respect to the CMOS In the past, designers have faced far greater uncertainties
compatible clock input is, therefore, 1.2 ns (10% of 17 ns when they populated PC boards with a variety of SSI, MSI
minus 4.9 ns). This is still a positive value, sometimes and PAL devices, each from a different production run,
called a negative hold time. each with different power dissipation and junction tem-
perature. Such problems do not exist inside the lCA
There will never be a hold time requirement if the user where delays track, and the temperature is the same for all
selects the CMOS-compatible clock-input option. elements.
6-13
Delay Tracking
0% A 100%
For a clear description of these delay variations, see Figure 29 on page 2-26. It shows that the ''typical'' delay, exhibited
by an average device at 25°C and 5.0 V, is slightly more than half the worst case delay for a commercial temperature
range product, and is less than half of the worst case military value.
Designers should regard ''typical'' values as meaningless averages, taken under favorable operating conditions. Nobody
should base a design on ''typical'' values, but some manufacturers still use this misleading way to specify device
performance. It should have died 25 years ago.
6-14
~~~---~-- - - - - -
Application Brief
During configuration, all I/O pins not used for configuration After configuration is completed, the LCA becomes active
are 3-stated and all internal flip-flops and latches are held in response to a rising edge of CCLK. All outputs that go
reset until the chip goes active. Even multiple LCAs active will do so simultaneously, but they are obviously not
hooked up in a daisy chain will go active simultaneously as synchronized to the system clock. Some designs might
a result of the same CCLK edge. This is well documented. require a reset pulse synchronous with the system clock to
avoid start-up problems due to asynchronous timing be-
Not documented is how the internal combinatorial logic tween the end of internal reset and the system clock.
comes alive during configuration: As configuration data is
shifted in and reaches its destination, it activates the logic The circuit below generates a short global reset pulse in
and also "looks at" the inputs. Even the crystal oscillator response to the first system clock after the end of configu-
starts operating as soon as it sees its configuration data. ration. It consumes one CLB plus one output pin, and it
Since all flip-flops and latches are being held reset, and all also precludes the use of the LDC pin as I/O.
outputs are being held 3-stated, there is no danger in this
"staged awakening" of the Chip. The user can take
During Configuration:
advantage of this to make sure that the chip comes to life
with the internal output 3-state control signal on the output LDC (Low) holds D High, but Q is held Low by internal
driver already active before the end of configuration, so reset.
that there is no chance of any output glitch. RESET is pulled High by internal and external resis-
tors.
FAST RECOVERY FROM RESET
End of Configuration before first System Clock:
Recovery from Reset is not specified in our data sheets
LDC pin goes active High, Q stays Low, D stays High.
because it is very difficult to measure in a production
RESET is still pulled High by external resistor.
environment.
Result of first System Clock after end of Configuration:
Here are benchmark values:
The CLB can be clocked immediately, i.e. within 0.2 ns, Q is clocked High, which forces D Low.
after the end of the internal direct reset (rd). Output driver goes active Low and forces RES ET Low.
This resets the whole chip until the Low on Q
The CLB can be clocked no earlie r than (wo rst case) 25 ns causes RESET to be pulled High again
after the release (rising edge) of the externally applied The whole chip has thus been reset by a short pulse •
Global Reset (acting Low) signal. instigated by System Clock.
SYSTEM CLOCK
CLB
LOC
6-15
E:XIUNX Metastable Recovery
CLB FLIP-FLOPS RECOVER SURPRISINGLY FAST When an asynchronous event frequency of approxi-
FROM METASTABLE PROBLEMS mately 1 MHz is being synch ronlzed by a 10 MHz clock,
the CLB flip-flop will suffer an additional delay of
A specter is haunting digital design, the specter of metas-
tability. From a poorly understood phenomenon in the 4.2 ns statistically once per hour
seventies, it has developed into a scary subject for every
designer of asynchronous interfaces. Now Xilinx offers 6.6 ns statistically once per year
data and a demonstration kit to help users analyze and
predict the metastable behavior of LCAs. 8.4 ns statistically once per 1000 years
Whenever a clocked flip-flop synchronizes a truly asyn- The frequency of occurrence of these metastable delays is
chronous input, there is a small but finite probability that proportional to the product of the asynchronous event
the flip-flop output will exhibit an unpredictable delay. This frequency and the clock frequency.
happens when the input transition not only violates the
If, for example, a 100 kHz event is synchronized by a 2
setup and hold-time specification, but actually occurs
MHz clock, the above mentioned delays (besides being far
within the tiny timing window where the flip-flop "decides"
more tolerable) will occur 50 times less often.
to accept the new input. Under these circumstances the
flip-flop enters a symmetrically balanced state, called The mean time between metastable events lasting longer
metastable, (meta = between) that is only conditionally than a specified duration is an exponential function of that
stable. The slightest deviation from perfect balance will duration. Two points measured on that line, allow extrapo-
eventually cause the outputs to revert to one of the two lation to any desired MTBF (mean time between failure).
stable states, butthe delay in doing so depends not only on
the gain bandwidth product of the circuit, but also on the
original balance and the noise level of the circuit; it can, MTBF
6-16
I':XILINX
,
II
,,
.J ,,
D D 00 D 0, 00 //////./. ,,
,,
CLB NONMETASTABLE
CLOCK
0,
if METASTAIIl.E if
,
o.
II ,,,
D
°2 I
CLOCK
- ,, ,,
.
REPEATED EIGHT TIMES 10_17
COUNT PU.8E IFMETASTMLE
11.0 .. "8003
Metasable Delay Measuring Circuit Metasable Detection
6-17
Battery Backup for
Logic Cell Arrays
Application Brief
Logic Cell Arrays use a high performance low power Figure 1 shows a circuit developed by Shel Epstein of
CMOS process. They can, therefore, preserve the pro- Epstein Associates in Wilmette, IL. Two 1N5817 Schottky
gram contents stored in the internal static memory cells diodes power the LCA from either the 5.2-V supply or a
even during a loss of primary power. This is accomplished 3-V Lithium battery. A SEIKO S8054 3-terminal power
by forcing the device into a low-power non-operational monitor circuit measures Vcc and pulls PWRDWN Low
state while supplying Vcc from a battery.
6-18
- - - - -----------
Application Brief
FOUR·INPUT MULTIPLEXER IN ONE CLB FOUR·BIT BARREL SHIFTER IN ONLY FOUR CLBs
Since the function generator in the XC3000 series CLB A four-input barrel shifter has four data inputs, four data
has only five inputs, it cannot directly implement a four- outputs and two control inputs that specify rotation by 0, 1,
input multiplexer, which requires four data inputs and two 2 or 3 positions, A brute force design would use four four-
select inputs, input multiplexers, since each output can receive data
from any input. Each four-input multiplexer requires two
Registering one of the select inputs in the same CLB frees XC3000 family CLBs, for a total of eight CLBs,
up one input and puts a complete four-input multi-
plexer into one CLB, It is even possible to register the There is, however, a smarter method that reduces the
multiplexer output. design to only four CLBs, The key to this approach lies in
the signal crossovers at the input and output of the second
This non-obvious trick increases the apparent delay of the level CLBs,
registered select input, but that will be acceptable in the
majority of applications, Since it reduces not only the size Eight·Bit Barrel Shifter in 12 CLBs
but also the through-delay of the four-input multiplexer by
50%, this approach is definitely worth considering, The 4-Bit Barrel Shifter design can be extended to eight
bits, A first-level shifter consisting of four CLBs rotates the
eight inputs by one position, controlled by the least-
significant control input. Two interleaved 4-Bit Barrel
o Q Shifters then take the eight outputs from the first level and
rotate them by 0, 2, 4 or 6 positions,
l'
2'
13 d
Sl~·~--------------~
% dl
197801
3'
•
4'
197802A
6-19
Majority Logic, Parity
Application Brief
MajOrity logic has interesting mathematical features, but Two CLBs can generate the parity for nine inputs, or can
has not become popular because its traditional logic check a 9-bit input for odd or even parity with a through-
implementation is quite complicated and expensive. delay of two cascaded CLBs. Three CLBs can check
Since LCAs can generate any function of five variables at 13 inputs; four CLBs can check 17 inputs; five CLBs can
the same cost and the same delay, they can easily decode check 21 inputs; six CLBs can check 25 inputs; all with the
majority logic. The output F, G is Low when none, one, same delay of two cascaded CLBs.
or two inputs are High; it is High when three, four, or five
inputs are High.
=:
Majority logic is a special case of "N-of-X Decoding." An
XC3000-series CLB can directly encode any "N of 5"
inputs active. This concept can be cascaded so that three
-
=:
t--
r- ODD OR EVEN
113902
NOF7
113901
The first-level blocks can only have three inputs, since the
two outputs can only encode four different states: none,
one, two, or three active.
113903
6-20
Multiple Address Decoding
An XC3000-series CLB can decode a 5-bit address in any Address Block Detection
conceivable way, or it can decode a 4-bit address in two
different ways, each without any restrictions. The idea mentioned above is not restricted to detecting
three specific addresses, it can also detect three groups of
8 0
addresses, as long .as none of them straddles the bounda-
I I W/Y/fI'/Z01 I ries defined by the individual CLBs. If they do, this circuit
cannot detect three address blocks, but can still detect any
one address block in an 8-bit address.
114002
Figure 2.
6-21
Binary Adders, Subtractors
and Accumulators
Application Brief
There are many different ways to implement binary dents. These signals can reduce the ripple carry delay.
adders, subtractors and accumulators with LCAs, using Both CP and CG are outputs from an arithmetic block
different trade-offs between size and speed. (often of four bits). Both these outputs can be generated
immediately since they are not affected by any incoming
Most compact, but slowest, is the bit-serial function that carry that might arrive late. As the names imply, Carry
operates on one bit pair per clock cycle, generating sum Generate is active if the block creates an overflow (carry),
and carry. The sum is fed back into the shift register, the e.g. if the 4-bit sum, regardless of incoming carry, exceeds
carry is stored for the subsequent bit time. F. Carry Propagate is active if the block does not generate
a carry by itself, but would generate a carry as a result of
The most compact combinatorial (parallel) adder, an incoming carry. In our 4-bit example this occurs when
subtractor, or accumulator consists of cascaded CLBs. the sum is exactly F.
Each CLB (XC2000 or XC3000 family) is a full adder,
accepting one operator bit pair (A, B) and an incoming There is an even faster algorithm. As originally described
carry. The CLB generates the sum and the outgoing carry. by J. Sklansky in the June 1960 issue of the IRE Transac-
A 16-bit function requires 16 CLBs. It performs an tion on Electronic Computers, Conditional-Sum Addition
operation in 16 combinatorial delays. can save time at the expense of higher logic complexity.
Matt Klein of Hewlett Packard recently modified this algo-
The 5-input function generator of the XC3000 family can rithmto fitthe XC3000 architecture. His design requires 41
add a carry to two operator pairs. Three CLBs can thus CLBs to add or accumulate two 16-bit numbers in only
handle two input bit pairs, generating two sum outputs and three(!) combinatorial delays. With careful layout, such an
the outgoing carry. A 16-bit function requires 24 CLBs. It adder/ accumulator can run at 30 MHz.
performs an operation in eight combinatorial delays.
Note that all Xilinx adder structures can also be accumu-
Carry Propagate and Carry Generate are intermediate lators without any size or speed penalty. Conventional
signals that can speed up the operation as shown on gate arrays and other gate-array-like structures usually
pages 6-27 and 6-28. Such a 16-bit function requires 30 configure flip-flops out of gates. The flip-flop set-up time
CLBs. It performs an operation in six combinatorial delays. must then be added to the combinatorial propagation
delay. LCAs hide the flip-flop set-up time in the combina-
The concept of Carry Propagate and Carry Generate has torial propagation delay of the CLB. Adders and accumu-
been made popular by the 74181 ALU and its descen- lators thus operate at the same speed.
2000
6-22
Adders and Comparators
The LCA-structure accommodates 1-bH and 2-bit adders For eight bHs, this look-ahead carry scheme is of marginal
very efficiently. A 1-bH adderwHh three inputs (A ,B, C1N) use, it reduces only the carry delay, and only by one CLB
generating two outputs (S, Cwr) fits exactly in one delay. For this small speed improvement it uses
XC2000- series CLB, where the flip-flop might be used for two additional CLBs (14 instead of 12). See truth table on
storing the carry in a bit serial adder. A XC3000-series page 6-25.
CLB can even include an additional control input, either
ADD/SUBTRACT or ADD ENABLE.
C'N
Ao
Bo
s,
So
CP
1---'" C OUT
II
A, c.
B, 6 CLBs
2 Delays
C2
A. H--+s.
B. 1-+---S7
A7
I--I---S, B7
HHf--+cOUT
'141 01 1141 02
6-23
Adders and Comparators
A 16-bit adder benefits from carry-Iookahead. Simply A look-ahead carry scheme uses 30 CLB at a max prop
cascading di-bit adders uses 24 CLBs at a max propaga- delay of five CLBs from CIN to COUT (six delays to S14,
tion delay of eight CLBs from CIN to COUT or to S14, 15. 15).This design is available from Xilinx. Call the
applications hot line 408-559-7778 or 1-800-255-7778.
e.
-
C'N
Ao
Bo
'=! So I r--
A, =! "-
5, I I-
B, ---J - A.
4
_ s.
e2 B. _ i- 5.
A. _
B, _ f--
~ f-
f- ~ I-
~ 52
~
~ l-
=:
~ l-
f-
53
e,o
e. I
I l-
4
I
I I-
f- A,o ---J
B,o ---J
r--
5"
5'0
A" ---J
B" ---J I--
Y 5.
-
=!
- --J
-
~
~
~
5,
l-
f--
I
C'2
-
~ l- I I-
C. 4
A'2-
B'2- - 5'2
5"
I A,,_
B,,- ~
--t
I - ~ f.---
4 - ~ -
-
=:
I--
57
5.
C,.
~
~ -
30 CLBs I
J
I-
5 Delays to COUT
4 f-
6 Delays to S14' S15 5,.
f-
A,:=:
B,. 5"
A,~=: r--
B" 1141 03
6-24
E:XILINX
Adder Logic Truth Tables Bit·Serial Adder, Subtractor, Comparator
After adjusting the subscripts appropriately, the truth table The ClB architecture is ideally suited for bit-serial arithme-
for the three CLBs generating S2 and S3 is identical with tic, where the function generator performs the serial arith-
thattorthe CLBs generating So and S1; and the truth table metic (lSB first), and the associated flip-flop stores the
for the bottom three ClBs is identical to that of the three carry or borrow.
ClBs generating S4 and Ss.
1 1 1 x x
S,=1 x 1 1 0 0 Figure 4. Serial Adder/Subtractor
1 x 1 0 0
1 1 x 0 0 A bit-serial identity comparator detects only whether the
x 0 0 1 0
0 x 0 1 0 two operands are equal or not, without determining which
0 0 x 1 0 one (if any) is larger. The bit stream can come in lSB or
x 0 0 0 1 MSB first, the flip-flop gets set for any difference between
0 x 0 0 1
0 0 x 0 1 A and B, and stays set until the end of the word, then gets
x 1 1 1 1 reset before the beginning of the next word. This "differ-
1 x 1 1 1 ence detector" can also be implemented as a latch and
1 1 x 1 1
folded into the combinatorial logic.
C.=1 x x x 1 1
x 1 1 1 0
1 x 1 1 0 A bit-serial magnitude comparator distinguishes between
1 1 x 1 0 A = B, A > B and A < B. It can operate lSB first or MSB first.
x 1 1 0 1 if the logic is adjusted:
1 x 1 0 1
1 1 x 0 1 lSB first: Start with both flip-flops reset
Inputs if A > B set Ox, reset Oy
Outputs C, A, B, A. B. if A < B set Oy, reset Ox
S.=1 1 0 0 x x
0 1 0 x x MSB first: Start with both flip-flops reset
0 0 1 x x if A > Band Oy = 0: set Ox
1 1 1 x x
S,=1 x 1 1 0 0 if A < B and Ox = 0: set Oy
1 x 1 0 0
Result in both cases:
1 1 x 0 0
x 0 0 1 0 Qx Qy
0 x 0 1 0
0 0 x 1 0 o o A=B
x 0 0 0 1
0 x 0 0 1 o 1 A<B
0 0 x 0 1 1 o A>B
x 1 1 1 1 1 1 Impossible
CG.=1
1
1
x
x
x
1
x
1
x
x
1
1
1
1
1
1
II
1 1 1 0
x 1 1 0 1
x A Ox
CP.=1 0 1 1 0
x 1 0 1 0
x 0 1 0 1
x 1 0 0 1 B
Inputs
Lower Higher Ox Oy
Outputs CIN CPn CG n CPn+2 CG n+2
Carryn x x 1 x x Oy
1 1 x x x
CLOCK _ _ _ _---I 114105
Carryn+2 x x x x 1
x 0 1 1 x
1 1 0 1 x Figure 5. Serial Magnitude Comparator
6-25
Conditional Sum Adder
Adds 16 Bits in 33 ns
This circuit is based on a 1960 paper by J. Sklansky (see subscripts denote the binary position (weight), and super-
page 6-22). With careful placement and routing the total scripts describe the assumed input condition:
delay can be kept below 33 ns.
0: carrry into this position is assumed inactive
The block diagram below shows each CLB and its inputs '0: carry into the position one lower is assumed inactive
and outputs. 1: carrry into this position is assumed inactive
'1: carry into the position one lower is assumed inactive
27 of the CLBs each generate one function of up to five
variables, 14 of the CLBs each generate two functions of This design is available from Xilinx. Call the applications
four variables. In accordance with the original paper all hot line 408-559-7778 or 1-800-255-7778.
r:::l _ A,B,
CoAoBo ~
~-=~----------1-~~-----------------'
CoAoBoA'B'~
Co A, BoA, B,
A,B,A, B,
A,B,A,B,
AlOBlO AllBll
1988 01
6-26
Building Latches
Out of Logic
Application Brief
Since the XC3000-series, unlike the XC2000-series, can- can also have two D inputs, each with its own Enable; or
not configure its CLB flip-flops into latches, there must be we can have two D inputs, a Select input and an Enable
other ways to design latches. Obviously, the I/O block can input; orwecan have an Enable and three D inputs defined
be configured with latches on either the input, the output, in any arbitrary way. Majority gating could be one way: if
or both. Beyond that, every CLB can form a latch. none or one is active, reset the latch; if two or three are
active, setthe latch. Or, if none is active, reset; ifoneortwo
The 5-input logic structure permits an amazing diversity of
are active, hold; if three are active; set. Or we can assign
latch designs; here are several ideas:
positive or negative weights to the D inputs.
With F fed back to close the feedback path, there are four
control inputs left. They might be called Set, Reset, Data Since there are 65,536 different functions of four
and Enable, defined such that Sand R are independent of variables, there are many different ways to define a
Enable, but D is activated by it. Any of these four inputs latch, not counting pin rotations and active-High/active-
can be defined as active High or active Low. This results Low variations.
in 16 different latch designs, all with the same basic
characteristics and the same timing.
All these latches have the same timing characteristics:
We can also eliminate D and have two Enables, affecting propagation delay from input to output = 14/9 ns for the
Sand R (again 16 different flavors) or we use multiple S 50/70 MHz part. Set-up time to the end of Enable, or min.
and multiple R, either ORed, or ANDed, or XORed. We
D SET SET1
END EN SET SET2
SET RESET RES 1
RESET ENRES RES2
D1
EN D1
D1
D2
D1
D2
II
D2 SEL D3
END2 EN EN
1142 01A
6-27
Synchronous Counters,
Fast and Compact
FULLY SYNCHRONOUS 4-BIT COUNTER USES FULLY SYNCHRONOUS 5-BIT COUNTER USES
ONLY TWO CLBS TO COUNT ANY CODE ONLY THREE CLBS
This 4-bit counter operates synchronously and has a Three XC3000-series CLBs can implement a modified
Count Enable (Clock Enable) input. Count length, count shift-register counter with the following features:
direction, and even the code sequence can be selected
through configuration. There are 15!, i.e. more than 1012 • Fully synchronous operation
different possible sequences. All four outputs are avail-
able. This counter cannot be preset to an arbitrary value, • Count Enable Asynchronous clear
but it can be cleared by an asynchronous input.
• Count-Modulus defined during configuration: 2 ... 32
~~~ ~::
ANY SEQUENCE:
• Only one meaningful output, 0 s, but with complete
BINARY freedom to define its waveform
GRAY
BCD 00 through 04 form a linear shift register counter. The 5-
X3 input combinatorial function FO determines the modulus
X3·GRAY (there are no illegal or hang-up states). The 5-input
~:~ ~:
BIQUINARY combinatorial function Fl decodes the counter in any
ETC.
conceivable way, as synchronizes and de-glitches Fl.
,.430t Examples:
Figure 1. Synchronous 4-Blt Counter in 2 ClBs
+ 28 counter with output High at times
T2, 3, Tl0, T22 through T27
The advantage of a Gray code is its glitch-less decoding,
since only one bit changes on any code transition. A Gray
+ 19 counter with output Low at times
counter can also be read "on-the-f1y'~ without the well-
T9, T12, T15, T18.
known problems of reading a binary counter e.g., on its
transition between 7 and 8, where any code might be read.
6-28
30 MHz Binary Counter Uses
Less Than One CLB per Bit
Borrowing the concept of Count-Enable Trickle/Count- The least-significant tri-bit thus stops the remaining
Enable Parallel that was pioneered in the popular 74160 counter chain for seven out of eight incoming clock pulses,
TTL-MSI counter, a fast non-Ioadable synchronous binary allowing ample time forthe CEO-CET ripple-carry chain to
counter of arbitrary length can be implemented efficiently stabilize. Max clock rate is determined by the first tri-bit's
in the XC3000 series CLBs. For best partitioning into Clock-to-CEO delay (TcKO + T ILO)' plus the CEP input set-
CLBs, the counter is segmented into a series of tri-bits. up time for all other tri-bits (TICK)' plus the routing delay of
the CEP net. In a-70 device this sum can be below 32 ns.
The least significant, i.e. the fastest changing, tri-bit has a The higher tri-bits are not speed critical if they propagate
Count-Enable Output (CEO) that is routed to all the Count- the CET signal in less than eight clock periods, easily
Enable-Parallel (CEP) inputs of the whole counter. achievable for counters as long as 20 tri-bits, i.e. 60 bits.
Each Count-Enable Output from any othertri-bit drives the The two least-significant tri-bits each have a single CE
next more significant Count-Enable Trickle (CET) input. input; they fit, therefore, in only two CLBs each. The higher
The clock causes any tri-bit to increment if all its Count- tri-bits have two Count-Enable inputs (CEP and CET) and
Enable (CE) inputs are active. CEO is active when all three require three CLBs.
bits are set and CET is High. CEP does not affect CEO.
ETC
1980 OtA
30-MHz Non-Loadable Binary Counter, Expandable up to 60 Bits
I£%-'"~.-'
......:•.""....»:<";.:.:<";.»...:.:.:........~•.,...........,..........,.;..<";•••,•••,•••••
~:-""''''''''''''''''''''''''':''':':'''''''''''»''''~:':':':'''''Y''''''''''''''''"
~ I
,
Ig~
~
I,
j
j II
~ ~
......................................................................................""............................................................................u ....... ~..................................................................................................................................................................................................~
~ ~ ~ ~
~~
I 0 QA I
l
~
~
~
eel Q °A
~
i
l
~ ~: CEP
~ ~
I
~
I ~
I
~
I
I
~
1= ~I
I :l
! ~
~ CEP
!::t...,............... !
~
First and Second Trl-Bits Use Two CLBs Each All More Significant Tri-Bits Use Three CLBs
6-29
Up/Down Counter Uses
One CLB per Bit
A fully synchronous resettable but non-Ioadable up/down not suited for high-speed clocking, but it generates
counter of arbitrary length can be implemented with only fully synchronous outputs, i.e., all flip-flops clock on the
one XC2000 CLB per bit. This design cascades the toggle same edge.
information from the least-significant toward the most-
The better functionality of the XC3000 CLBs can cut the
significant position. Such an architecture reduces the
cascaded toggle-control delay in half by looking at two
maximum clock rate for longer counters, from 30 MHz
counter bits in parallel. This doubles the max frequency for
for 2 bits, to 10 MHz for 8 bits, down to 5 MHz for 16 bits,
assuming a -70 part. This simple design is, therefore, a given counter size. A 16-bit counter in a -70 part can
count 10 MHz, guaranteed worst case.
COUNT
J--_ _ _---'x"---+-__ ENABLE
COUNT OUT
ENABLE - - - 4 _ - I f - - - - - - l
IN
D Q !--'V.......-t--,
1981 OtA
r-------------------~CEO
CEI -+--r+----.----4-----~-+_~
108t 02A
6-30
Loadable Up/Down Counter
Uses One CLB per Bit
The 5-input function generator of the XC3000 family CLBs two counter bits simultaneously. This cuts the effective
makes it possible to build expandable fully synchronous ripple delay in half. A 16-bit counter in a -70 part can count
loadable up/down counters of arbitrary length using only 10 MHz, guaranteed worst case.
two CLBs per two bits, i.e. one CLB per bit.
The CEP/CET speed enhancement cannot be used on up-
The basic concept is similar to the non-Ioadable up/down down counters that might reverse their direction of count in
counter described on the previous page. The function any position. They can, the.refore, not guarantee a defined
generator driving the counter flip-flop has two additional number of clock periods for the ripple-carry chain to
inputs (Parallel Enable and Data). The cascaded toggle stabilize.
control circuit is moved to a separate CLB which serves
CEI--~~-----------------------.
UP/DOWN ---t----t----t-----i
}-+-- CEO
~--------------------------~--------------------------~QB
II
Q Q
PE----~--~----------------------------~
198201A
6-31
30 MHz Binary Counter with
Synchronous Reset/Preset
In many applications, design modularity is more important A shorter counter (six bits or less) drives the CEP net from
than highest clock speed and best space efficiency. A the 00 output, achieving a 40-MHz speed. A longer
counter design is described here that uses identical CLB counter generates a 1-in-4 duty cycle on CEP and runs at
primitives, one CLB per bit. The Count-Enable Trickle/ 30 MHz up to 12 bits long, or at 25 MHz up to 18 bits long
Count-Enable Parallel concept, introduced by the 74160 as shown below. To achieve this performance, CEP and
family, is changed here to a 1-bit block size. Any block R must be driven by long lines.
increments only if both Count Enables are High, but the
outgoing Carry (C OUT) is not a function of CEP. The CEP Figure 3 shows a variation of the circuit in Figure 2, where
input thus prevents erroneous counts while the ripple carry the synchronous Reset input (R) is changed to a synchro-
chain is settling. nous Preset (p). Any counter chain can use a mixture of
these two circuits to preset the counter to an arbitrary
predetermined value.
ETC TO 017
RESET--~------+++-----~~-------H~------~r------+~
CLOCK--~------+-~----~~------~~------~~-----+~
00 0,
1983 01
CEP CEP
....
~:.:-:.:-:-~:-:-:.:.:. :-:-:·:-:-:·:·:.:·:.:-.~:·:-:-:-:·x-:·:·:·:·:·:·:·:·:..:·:·:·:·:·;.:·:.:.:.;.:.:.:.:.:.;.:-:.:.;.:.;.;.:.:.:.:.:-:.;.:.:-:.;.: :.:.:.:.:.:-:.:.:-:.:.:.:.:.:.:.:.:.~~~
COUT Cw I
I
COUT
i
:~
P~-------4>---~
CLOCK - - ; j r - - - - - - - - - - - - - - - - - - - - i > CLOCK~r--------------------I>
Q Q
198302 1983 03
Figure 2. CLB Primitive with Reset, One per Bit Figure 3. CLB Primitive with Preset, One per Bit
6-32
Fast Bidirectional Counters
for Robotics
The position of a robotics arm is usually determined by Communication between these two parts of the counter is
three shaft encoders consisting of up/down pulse genera- through a carefully controlled mailbox. Whenever the 4-bit
tors and counters. At a maximum speed of 5 meters per up/down counter reaches plus or minus 8, it sets a carry or
second and a resolution of 1 micron, these counters must a borrow flip-flop. The shift register counter accepts these
resolve 0.2-J.IS pulses and should have a capacity of at inputs synchronously, with a max delay of 1 J.IS.
least 2 million steps. The counters must have an easy
When the microprocessor wants to read the counter, it first
interface to the microprocessor so thatthe count value can
disables the interaction between the two parts of the
be read on-the-fly, without ambiguity.
counter. Then both parts are transferred into 24 output
The established microprocessor peripheral counters have registers and the counter interaction is enabled again.
severe limitations. They are too short, lack up/down con- This mechanism insures reliable read-out, even if the
trol or quadrature clock inputs, and cannot be read easily. counter is oscillating around certain critical values.
Now Xilinx suggests a design that packs three 22-bit The problem of a traditional up/down counter is that it can
counters into one LCA, the XC3020. Max count rate is oscillate between two values where all (or most) counter
8 MHz, and the count values can easily be read on-the-fly. bits change at the incoming count rate. This makes a reli-
The counter architecture is somewhat unconventional. able microprocessor interface virtually impossible.
Each counter consists of two parts:
In this deSign, the most significant 20 bits of the counter do
1. A conventional up/down 4-bit Grey-code counter with a not have this problem, and the least-significant four bits
capacity from -8 to +7. This counter is asynchronous to count in a Grey code, where only one bit changes on any
the system clock, affected only by the incoming clocks. clock transition. Such counters can safely be read on-the-
fly. This safe and compact design puts one additional
2. A 20-bit up/down counter in the form of a 20-bit recircu-
burden on the microprocessor: The two parts of the
lating shift register, a serial adderlsubtractor, and a
counter must be added in software, since they have in-
carry/borrow flip-flop. This shift register forms the most
dependent signs.
significant part of the counter. Synchronous with the
LCA clock, it is easily synchronized to the microproces- Speed can be increased to 20 MHz by changing the parti-
sor clock. At a 20-MHz clock rate, it recirculates once tioning from 4/20 bits to 8/16 bits. The up/down count con-
and can be incremented, decremented, and also read trol can be implemented in several different ways.
or preset, once per microsecond.
II
HANDSHAKE
ADDRESS
1984019
Figure 1. Triple 22-Blt Up/Down Counter with Microprocessor Interface
6-33
40 MHz Presettable Counter
Traditional counter designs always represent a compro- The counter is divided into a number of small sections,
mise between two conflicting goals: highest clock speed! each two bits (a di-bit) long, implemented as a synchro-
event resolution on one hand, sophisticated features (like nous presettable down-counter, with carry-in (=count en-
preset to any arbitrary value, or decode any state) on the able), parallel enable and two data inputs. Terminal count
other hand. (0.0) is decoded with an additional input coming from the
next higher section. The least-significant section decodes
Asynchronous ripple counters offer highest speed, but the state priorto TC; its output activates the parallel enable
cannot be decoded in one clock period, thus cannot be for all counters. The carry function between sections is
made programmable. pipelined. The carry flip-flop is set when carry-in is active
and the di-bit is in state 00. The carry flip-flop stays set for
Synchronous counters permit decoding and presetting in only one clock period; its output drives the carry-in function
one clock period, but pay for this with complex carry logic. of the next higher section. As a result of this pipelining, the
Carry propagation is always the limiting factor in the counter can be made arbitrarily long without any speed
traditional design of presettable synchronous counters, penalty. Note that each di-bit, except the first, makes its
since the complete carry chain must reach a steady state transition n clock pulses later than required by the binary
before the next incoming clock edge. Brute force parallel code sequence (n is the relative position of the di-bit, n=O
decoding of all previous states becomes unmanageable for the input di-bit). This code violation has no impact on
beyond eight stages, but cascaded decoding introduces TC decoding. This counter can be four times faster than
additional delays. Either approach reduces the inherent presently available standard microprocessor peripherals
resolution of the counter. like the 8254 and 9513. Typical applications are in
instrumentation and communications, for example, as the
Decoding Terminal Count (TC) to presetthe counter again frequency-determining counter in a phase-locked-loop
poses a similar problem. The design described here frequency synthesizer.
separates the two functions of the carry chain as follows:
SUMMARY
• One propagates the carry signal from the less-signifi-
cant to the more-significant bit positions, and causes the Unlike the speed of conventional synchronous counters,
appropriate flip-flop to toggle. the speed of this design is independent of its length. All
• One cascades the decoding of the terminal count of the speed-critical paths are single level; their interconnect
whole counter and generates a Parallel Enable signal delay can be kept below 9 ns, which means that even a
-70 device can count at a 40-MHz rate (worst case).
CASCADED TC DECODING
MSB 4-- LSB
The TC decoder must receive inputs from all counter bits,
but only the LSB timing is critical; the more-significant bits "=2 "=1 "=0
1 1
have been stable for many clock periods. TC can, there-
o 4) 00 00 •.• .• .•. ~ • •. • 01 01
fore, be decoded in a slow gating chain that starts at the 0:0'0) "
!~~"'"
most-significant end of the counter.
PE
c~~ ;r II40 BITS ~ TC 1145 01 1145 02
6-34
E:XILINX
CI-4r---------------------------~~--~--------------------------------+_~
o,H-t~~[) o
CARRY
CO
PE-----.p--J
I
Do------------LJ
,,--=-=__=
ro ___=_=,,==,__=,_=«_=__==1========'='-=-:j~I'E~~8:::===:- n
o
CI- CARRY IN TERM.
CO_ CARRY OUT COUNT
PE _ PARALLa ENABLE (ACTIVE LOW)
TI_ TERMINAL COUNT IN
TO - TERMINAL COUNT OUT
1145048
f~~~~~~---'~-'---~~--~--
I l
I'E----.,....J 0 0 1-----.1---+----<1/ 0, 0
Do.-----------LJ
0,------,__"
t~--"J
l
'~~~-'~'~~~="'·=·--''''=~-~-l '-...J-----t-------------TI
PE~ro~A~~~OI~~~~~----------------------------------------------------~~--------~-------------,
o
CE _ CLOCK ENABLE TEAM.
COUNT I
PRaET-------____________ ~ ________________________________________ ~---------------------+-----J
RO
~-~~.~-
1145 05B
PRESET
STARTtS'i'OP
HIGH
6-35
40 MHz Presettable Counter
Since this circuit was first published in mid 1988, several In the unlikely case where this might cause a problem,
designers have used it to create fast counters. most TC pipeline flip-flops can be eliminated. They were
inserted to simplify modeling and because they are
What is the function of the TC pipeline flip-flop, available for free.
formerly called Q3?
Why is the least significant dl-bit different?
The unconventional idea behind this counter design is that
Terminal Count decoding can be "rippled" from the MSB to To achieve a 40-MHz clock rate, the PE signal must be
the LSB, i.e. against the direction of carries. This is made as fast as possible. It has to come directly from a flip-
possible because the high order bits reached their TC long flop output so that the sum of clock-to-output delay, routing
before the LSB does. delay, and input set-up time is kept below 25 ns.
There is, however, a potential problem when the counter The position of the LSB TC pipeline flip-flop is, therefore,
is being preset to a value with a string of LSB zeros. Let's changed, so that it detects the TC-1 state (in a down-
assume the worst case where the preset value is all zeros counter, that is state 1).
except a single one in the MSB position:
The flip-flop output is made active Low PE so that the
When this counter reaches the all-zero Terminal Count, asynchronous clear input can be used to force the counter
PE is activated and the counter is preset. --This action into loading.
should obviously de-activate the TC decoding, but in the
given example a simple ripple decoder would have a very For operation below 30 MHz the least significant di-bit can
long delay. It might take 400 ns for the MSB =1 condition be like all the other dibits, but PE must be excluded from
to ripple down through a 40-bit decoding chain. Such a the AND gate generating PE, and the user may want to
delay would defeat the concept ofthe counter, reducing its adjust the polarity of the last TC pipeline flip-flop to
max clock rate to 2.5 MHz. A better way must be found to facilitate the preset function mentioned above.
de-activate TC within 25 ns.
, Where should this design be used?
The TC pipeline flip-flop and the inclusion of PE in the AN D
gate that detects TC, reliably de-activate TC and thus PE This counter design achieves high performance by using
one clock after they have been activated. This has one several logic "tricks". It generates incorrect outputs when
side effect, however: It makes it illegal to preset the counter undigested carries sit in the carry flip-flops. That makes
to very small numbers (less than 10 for a 20-bit counter), this design useless for any parallel application like DMA
since the TC-pipeline takes that many clock pulses to counters.
become active again.
For the intended application, timebase counters or
frequency synthesizers, this design offers the highest
possible count speed.
6-36
Frequency/Phase
Comparator for
Phase-Locked-Loops
Application Brief BY PETER ALFKE
A Phase-Locked-Loop (PLL) manipulates a local voltage- not only to pull in a small phase error, but also to correct a
controlled oscillator (VCO) so that it is in phase with a large frequency error. It may not generate false outputs
reference signal. One popular application is a program- when the input is at a multiple or fraction of the desired
mable frequency synthesizer for radio communications. frequency. The well-known circuit shown in Figure 1
Here a crystal oscillator is divided down to a low reference performs this function. It generates "pump-up" pulse when
frequency of 5 kHz, for example. the VCO frequency is too low, "pump-down" when its too
high. The multiple feedback network assures proper
A programmable divider scales the VCO frequency down operation even at large frequency errors.
to the same reference frequency. The two counter outputs
are compared to generate a signal that, when required, Figure 2 shows this circuit implemented in two CLBs plus
modifies the VCO frequency up or down until the two two lOBs, directly driving the integrator (low pass filter)
comparator inputs are not only of the same frequency, but controlling the VCO. The LCA solution has been
also in phase. breadboarded at 10 MHz. It achieved a phase error of less
than 2 ns.
This frequency/phase comparator must have a wide
capture range, i.e. it must generate the appropriate output,
FROMVCO
DIVIDED BVN
FROM
DIVI~g+--t-j--~
BYN
~:........£~~JN""""""""~"~"""~""""~""''''''..............:......................................................J
FROM
REFERENCE
FREQUENCY
II
1985011\
I
!L.:.:.~2.k!.:~»~:«*:-..... :-:.;.x.:-.»:...;.»»}»;.:...:.»:.;.;.;.:....:.;.;.;.:.:-»;.:.:.;.;.........:.:.:-:..M Tovca
+2.5V
INTEGRATOR
1985 02A
6-37
Gigahertz
Presettable Counter
Some frequency synthesizers for communications, e.g., smart but slow counter (in the LCA) to achieve the perfor-
cellular telephone networks, require a clock frequency of mance of a fast and smart, fully presettable counter.
hundreds of megahertz, up to a gigahertz. Obviously, the
LCA cannot operate quite that fast, but with the help of a The prescaler divides by either n or n + 1, depending on
2-modulus prescaler, the LCA can implement a fully pre- the state of the control input. In other words, it "swallows"
settable ultra-fast counter, resolving time in increments of one additional clock pulse if told so by the control input. By
one clock period, as small as 1 ns at 1 GHz. keeping the control input active forthe appropriate number
of prescaler output periods, the LCA can fine tune the total
Prescaling is the obvious method to adapt a slow device to divide ratio to any integer number.
a high clock rate. Simple pre scaling by a fixed number,
e.g. 8,16, or64, however, reduces not only the clock rate, Well, there are some impossible numbers:
but also the resolution. If, for example, the GHz clock of a When the prescaler divides by either n or n + 1, then the
phase-locked-loop synthesizer is first divided by 64, then system cannot divide by certain numbers below n (n-1).
the whole presettable counter is clocked at this lower rate.
For a 25 kHz channel spacing, the PLL must, therefore, An 8/9 prescaler has blind spots below 56
operate at 25 kHz + 64, i.e. less than 400 Hz. This results A 64/65 prescaler has blind spots below 4,032
in slow response and might produce excessive phase A 128/129 prescaler has blind spots below 16,256
jitter.
This limitation is usually of no practical consequence in a
A "Pulse Swallowing" 2-modulus prescaler, originally de- real design.
scribed in 1970 by John Nichols of Fairchild Semiconduc-
tor Applications, avoids this drawback. Pulse swallowing The prescaler-LCA combination can divide by any integer
combines a fast but dumb counter (the prescaler) with a number higher than the values above.
INPUT
200 MHz OUTPUT
0.280 ~s
0.285 ~s
0.290 ~s
200-MHz Counter
200 MHz clock, l2-bit
20.475 ~s
presettable time base generator 20.480 ~s
achieves 5 ns output resolution.
INPUT
450 TO OUTPUT
1000 MHz TO 25 kHz
PHASE·LOCKED·
LOOP
Gigahertz Counter
450 to 1000 MHz clock, l6-bit
presettable counter achieves
25 kHz channel spacing with a
25 kHz phase comparator frequency.
198803A
6-38
I:XilJNX
o ori--------------------------------- TC • PE
TC
00 °2
PE
01
CLBn
°1
II
PE
198802
198801
3·Blt Presettable Down Counter with 9·Blt Presettable Down Counter with
Pipelined Terminal Count, Locking Up on TC Decoded Terminal Count (TC)
6-39
75 MHz Presettable Counter
or Programmable Delay
FEATURES
I
The +8/9 prescaler described on page 6-42 can also be
implemented inside an LCA. The nighest clock frequency
for a -100 part is 75 MHz, i.e. the output delay can be
JJ-;=D-D a 1 aA
To
ENABLE
CLOCK
programmed with a granularity of 13 ns. The +8/9
prescaler consists of a +2/3 counter followed by a +4 I>
counter with one decoded state. Each of these counters
fits into a single CLB. The +2/3 counter divides by 2 unless
the 3-input AND is true, in which case it divides by 3. When
the DIV9 input is Low,the two counters together divide by
2+2+2+2=8. When the DIV9 input is High, the two =L)-D a U.B
+3
counters divide by 2+2+2+3=9. See page 2-42/43 for a
j
more detailed description of such a pulse-swallowing
counter.
This design demonstrates the high performance possible
l + 213 COUNTER
I>
with Xilinx LCAs when the user is willing to optimize the ,.. , QilililliiililiiiiQiili;·i"i~"«",;
DIV9
system design to fit the available logic. The high clock +3' I
~
resolution of 75 M Hz is partly due to a system '1rick" (pulse-
swallowing), partly due to the inherent flexibility, and high
speed of the CLB function generators.
A conventional 24-bit presettable counterwould be limited DIN D
a~
to a clock rate of 13 MHz. This pulse-swallowing design is
six times faster.
a A ENABLE CLOCK
I>
~D
CLOCK
aD OUT
a (RISING
Os _ _ _ _ ---InL-______ EDGE)
I>
Oc~ L- +4COUNTER
00 J I '--_-!r
~I.--- +9 ---~.I+.- - - +8 .1 X1194
X119S
Divide by Pulse-Swallowing Prescaler
DIV9
PARALLEL ENABLE
21·BIT TERMINAL
CLOCK COUNTER COUNT
75 MHz
+81+9 X1196
6-40
Serial Pattern Detectors
FIXED PATTERN DETECTOR ously shifted-in pattern, using only one XC3000-series-
CLB per pattern bit. The output of the comparators are
This circuit compares a serial bit-stream against a prede- ANDed with 3-state buffers on a long line. The desired pat-
termined (configured) pattem. Two bits are compared in tern is first shifted through the DIN input into the Y-flip-flop,
each XC3000-series CLB. The outputs of the comparator and then routed to the DIN input of the next CLB.
are ANDed in with 3-state buffers on a long line.
When the complete pattern has been shifted in, it is trans-
Data is shifted through DIN into the Y-flip-flop, then shifted ferred with one clock pulse to the X-flip-flops, using the
through the upper hail of the combinatorial array into the lower half of the function generator. Data to be detected is
X-flip-flop of the same CLB. From there it is routed to the then shifted inthroughthe DIN input into the Y-flip-f1op, and
DIN input of the next CLB. from there to the DIN inputofthe next CLB. The upper half
of the function generator compares the content of Ox and
The lower hail of the combinatorial array compares the Oy, and indicates a match on the CLB output. For identity
content of the two flip-flops against data supplied on the A comparison, these outputs are ANDed through 3-state
and D inputs. A match is indicated on the G output and buffers driving a long line.
routed to a 3-state buffer driving a long line.
DYNAMIC PATTERN DETECTOR OR CORRELATOR This circuit can also be used as a correlator, in which case
the outputs must be summed in a Wallace-type adder.
This circuit compares a serial bit stream against a previ-
r"'. . . . . '. . . .
··~ Y,..'NhY-'N~·VA"NNo"NU>."""""V.-=y..... y,... "'1
..v.........y,..................
LONG
j ~---. LINE
1
~ ax
}
~ Qy
LONG
}
UNE
,}
~
[
~
II
~
114702
114701
Figure 1. Fixed Pattern Detector Figure 2. Serial Comparator Finds Pattern Match or
Correlates Patterns
6-41
Serial Code Conversion
Binary to BCD
CONVERT/S"Hi"F't
Q'
3
114603
Figure 1, Binary to BCD (MSB First)
in a converted format. °2
°3
A binary-to-BCD converter requires three CLBs for every
four bits of BCD output i.e" for every digit. Data is shifted
in serially, most significant bit first. Each shift thus doubles
the content of the register, 1----10 °3
MODIFY: 5 - - 0,6-- 2, 7 _ _ 4, 8 _ _ 6, 9 - - 8
SHIFT MODIFY
0 2 - 0 3 - 0 0 '03
O,-02-00XNORO,
° _°,-°
0
0'3-°3-°3
0
X1246
114601A
6-42
Serial Code Conversion
BCD to Binary
CONVERT/SHIFT
o·
o
1146 04
Figure 1. BCD to Binary (lSB First)
~U
well to serial code conversion, where data is shifted into a r-
register in one format, and shifted out of the same register
in a converted format.
CONVERT
process begins, shifting out binary data, LSB first. MODIFY
~U
conversion before the most significant BCD digit is being r-
shifted in. Since these converters can be laid out with very
0,--<
short interconnect delays, they can operate at up to 60% °2--<
of the specified toggle frequency, I.e. 42 MHz for the -70
parts.
,---<
"-
- II
MODIFY: 0 - 5,2_6,4_7,6_8,8_9
J;---4'--
0, ....
°2 .... ~U
'---- ~
SHIFT MODIFY
0 , - °0 -0,
° 2 _ ° , - ° , XOR0 2
° 3 - ° 2 - 0 3 AND(O,OR0 2 )
0 ' 0 - 0 3 - 0 3 OR(O,' 02)
-:J
-
114602A
X1247
6-43
"Corner Bender" or
8-Bit Format Converter
For the first eight clock pulses, the array is in mode A, PHASE A
receiving eight bit streams and right-shifting them into the
array. Forthe next eight clock pulses, the array is in mode
B, down-shifting the previously received 64 bits.
PHASEB
1122 02
6-44
100 MHz Frequency Counter
The block diagram below describes a complete 100-MHz The high resolution of 100 MHz or 10ns is achieved by
frequency counter in an XC3020 PC84. using the divide-by-two flip flop driven by the alternate
clock buffer. This is the simplest and therefore fastest flip-
A 32,768-kHz crystal oscillator generates a time base of flop on the device.
two seconds. The frequency to be measured clocks an 8-
digit BCD counter. At the end of the measuring period of The whole frequency counter uses 60 of the 64 CLBs in an
two seconds the counter content is transferred into four XC3020:
shift registers, and the counter is then reset before the
Time Base 8 CLBs
beginning of the next measuring period. The shift register
drives a 7-segment encoderthatfeeds into the LCD driving BCD Counter 16 CLBs
logic, which in turn drives seven 8-bit shift registers nestled 4 Shift Registers 16 CLBs
in the lOBs. 7-Segment Encoder 4 CLBs
Leading Zero Suppressor 2 CLBs
The oscillator uses three lOBs, since the dedicated crystal Control 2 CLBs
oscillator input is already used as signal input. Segment Conversion/
LCD Driving Logic 4 CLBs
The time base is generated by a 16-bit-binary counter Special Clock Generation 6 CLBs
consisting of four asynchronously cascaded 4-bit synchro- Miscellaneous 2 CLBs
nous counters. The control unit eliminates the clock ripple
delay by re-synchronizing the time base output. The eight This design is available from Xilinx. Call the applications
counter decades are cascaded asynchronously, each hot line 408-559-7778 or 1-800-255-7778.
decade consisting of a synchronous BCD counter.
XC3020
fin
(0 ... 100 MHz)
BDIGIT
LCD
DISPLAY
P-I-_~_~~_T'~_E~-l~
~
LCD
B·BITSR
DRIVING
FDR'F"
LOGIC
I------j ~
}
112901B
Figure 1. Block Diagram
6-45
Megabit FIFO in Two Chips:
One LCA and One DRAM
A bit-serial FIFO buffer is a general-purpose tool to relieve This FIFO DRAM controller consists of:
system bottlenecks, e.g., in LANs, in communications, and
in the interface between computers and peripherals. • An inpuVoutput buffer with synchronizing logic
Small FIFOs are usually designed as asynchronous shift
registers, but a larger FIFO with more than 256 locations • A 20-bit Write pointer (counter)
is better implemented as a controller plus a two-port RAM, • A 20-bit Read pOinter (counter)
or as a controller plus a single-port RAM, either SRAM or
DRAM. • A 20-bit full/empty comparator
SRAMs are fast and easy to use, but at least four times • A 4-to-1, 1O-bit address multiplexer
more expensive than DRAMs of equivalent size. Dynamic
RAMs offer low-cost data storage, but require complex • Control and arbitration logic
timing and address multiplexing, which makes them unat- The Write pointer defines the memory location where the
tractive in small designs. For FIFOs with more than 256K incoming data is being written, the Read pointer defines
capacity, a DRAM offers the lowest cost solution, if the the memory location where the next data can be read. The
controller can be implemented in a compact and cost- identity comparator signals when the FIFO is full or empty.
effective way. An XC3020 Logic Cell Array can easily
perform all the control and addressing functions with many
gates left over for additional features.
DIN
IClK I/O
.. n"
7
Q
DOUT BUFFER
OClK
D
RDRB
(Read Ready/Busy)
WRRB
(Write ReadylBusy)
FUll
CONTROL
EMPTY DRAM
10
WRE MUX AO-9
RDE
7~
3 R7iS
.~
wr
j
1130 01A
Figure 1. Megabit FIFO Controller in an XC3020
6-46
When the Write and Read pointers become identical as a
result of a Write operation, the FIFO is full, and further
)D--\ SHIFT-REGISTER-COUNTER
This design fits two shift register counter bits in one This design can easily be modified for 256K DRAMs.
XC3000-series CLB and the identity comparator uses the Other variations are: multiple para"el bits, e.g., byte-
combinatorial portion of the same CLB. para"el operation, interrupt-driven control, multiplexed
data for multiple para"el-bit storage,and byte para"el
The RAS/CAS multiplexing of the 20-bit address is per- storage with bit-serial 110. The latter case requires special
formed without any logic by tapping every other bit of the attention when the FIFO is emptied after a non-integer
shift register counter and using the 10 outputs before the number of bytes had been entered, requiring direct com-
incrementing shift as Row address, after the incrementing munication between the input Serial-to-Para"el con-
shift as Column address. (The Column address of any verter and the output PIS converter.
position is thus identical with the Row address of the
following pOSition, but since the binary sequence of a shift This applications brief shows that the XC3020 can be
register counter is pseudo-random anyhOW, this is no programmed to control one or a few DRAMs as a large
problem. It's an elegant and efficient trick). FIFO of up to a megabyte, with data rates up to 16 Mbps
serially or 2 Mbytes per second byte-para"el.
The FIFO controller permits the user to perform totally
asynchronous Read and Write operations, while it syn- This design is available from Xilinx. Call the applications
chronizes communication with the DRAM. The design hot line 408-559-7778 or 1-800-255-7778 .
DIN DIN
6-47
State Machines
State-machine design is a methodology that defines the SIMPLE STATE MACHINE RUNS AT 30 MHz
contents of all flip-flops for any possible state of the design,
then defines all possible paths that can cause the design This simple state machine uses only 11 CLBs. It has up to
to go from one state to another. In its simplest form this is 16 states, and eight outputs, each decoding/encoding any
just a rigorous way of designing synchronous logic, like combination of states. It performs a 2-way branch from
4-bit counters. For complex designs, the state-machine any state to anyone of two freely assigned states,
approach gives the designer a tool to investigate all (possibly including the present state) determined by
possible operating conditions and avoid overlooked hang- control input C. (AVOid the branch by making both
up states or undesired transitions. LeA devices with their destination states equal).
abundance of flip-flops lend themselves well to state-
machine designs. This design can also perform an 8-way branch from any
state so programmed to either one of two selected
quadrants (0 .. 3, 4... 7, 8 ... 11 or 12... 15). Control inputs A,B
SIMPLE, FAST STATE MACHINES then determine the location within the quadrant.
~ ~
00
For a smaller number of states, some inputs can be used 10 13
as conditional jump inputs. Encoding these condition
codes may require an additional level of logic which
01 @ ®
reduces the maximum clock rate to 30 MHz.
11 @ ®
6ClBs 4 CLBs
WITH WITH 8
COMMON COMMON
INPUTS INPUTS
1986 01
6-48
Complex State Machine
in One LCA
Simple and fast state machines can easily be implemented 128 arbitrarily defined next states, controlled by the 7-bit
in an LCA, as shown on the previous page. This page condition code.
shows how an external EPROM can be the source of the
This basic design uses no CLBs in the LCA, just lOBs; but
next address in a complex state machine. This look-up
it allows a number of states and a mUlti-way branch
table can easily be hidden in the EPROM required to store
complexity far in excess of any normal need. The user will
the LCA configuration data.
usually reduce the mUlti-way branch complexity by
assigning identical values to many of the 128 possible next
Assume that an XC3020 is configured in the Master
states.
Parallel mode, where it reads its configuration data out of
a 256K (32K x 8) EPROM, starting at the top address The user has the logic resources of the LCA available to
location 7FFF (32K) through 77FF (about 30K). The re- add features like:
maining 94% of the EPROM can be used as a next-state
look-up table with a capacity of 240 states. • State decoding/encoding
• Stack registers
The state address is read out of the EPROM, then manipu- • Loop counters
lated (decoded, encoded, etc.) in the XC3020 LCA. The • More sophisticated branch logic, etc.
result is combined with incoming-control information to
generate a new EPROM address. The EPROM can be This design is straightforward, inexpensive, compact and
considered as having 240 locations, each 128 bytes wide. very flexible. Its speed is limited by the EPROM access
Each byte is a potential next-state value, only one of which time, which can be less than 100 ns. For higher speed-
will be chosen by the 7-bit condition code. at a higher cost-the EPROM can be shadowed by fast
SRAMS.
In the simplest case, the EPROM output data is just
latched in the LCA and is fed back as the most-significant
part of the new EPROM address. Since the top 16 address
locations are used for configuration data, the state codes
are limited to 240 different values, 0 ... 239. STATE
OUTPUTS
The seven control inputs form the seven least-significant
EPROM address bits. For reliable operation with asyn- CONDITION
CODES
chronous control inputs, they must be synchronized in an
input register.
198701
6-49
PS/2 Micro Channel Interface
IBM's general-purpose microcomputer, the Personal bus adapter cards. Defined with System Configuration
System 2, is available in several models, from the low-end Utilities, an add-on card's addressing and other optional
Model 25 to the high-end Model 80. These third- configuration data are established and stored in CMOS
generation PCs have several innovative features, battery-backed memory on the main board. Upon power-
including 3-1/2 inch floppy-disk drives, high-resolution up, this information is loaded into Programmable Option
VGA graphics, and a 20-MHz 80386 processor as Select (PaS) registers residing on the adapter cards.
the main engine for the Model 80. Among the
most interesting features is the Micro Channel interface, Figure 1 indicates one way in which a Logic Cell Array can
the bus specification for the interface between the be used for the PaS-register section of a Micro-Channel
system and adapter cards. The Micro Channel's adapter card. The Micro-Channel interface includes logic
streamlined characteristics and flexibility provide PS/2 to decode the address, status, and control signals asso-
designers and users with many advantages over previous ciated with the bus to identify the appropriate pas register
PC architectures. to be accessed. These signals determine if the card is
being addressed, and whether the current operation is a
One key aspect of this architecture is the ability to config- Read or Write.
ure the system without the need for DIP switches on the
CONTROL
READ
ENABLE
--
RD EN -
~
III III
~
READ! GATED POS
STATUS WE
LINES ~
WRITE LATCHES WRITE REGISTERS
DECODE STROBES
r
(UP TO 8) SYSTEM
CARD BIDIRECTIONAL
SELECT
- ..-.- f- f- DATA BUS
1
N
ADDRESS REGISTER
INPUTS ~ DECODES
111901A
6-50
The Micro Channel specification reserves two POS regis- logic must be very fast in order to grant control of the bus
ters for the upper and lower bytes of the Adapter Identifi- to the adapter with the highest priority.
cation (10). Six other byte-wide POS registers can hold
additional configuration information; some of the bits As can be seen by the logic in Figure 2, this priority level
within these are specifically dedicated to channel status (ARB 10 0-3) is driven onto the bus via an open-collector
information. Some applications will require the use of only driver. The logic then turns around and accepts the driven
portions of these six registers. bus as input. The cycle may repeat a few times before the
adapter with the highest priority level actually gains control
A second key aspect of the Micro Channel architecture is of the bus. For properoperation each half of the cycle must
its ability to arbitrate the bus access of multiple adapters. complete in 50 ns, a performance that can be achieved in
The Micro Channel specification clearly defines the 10gJc the 70-MHz LCA devices.
required for this arbitration. Each adapter in the system IS
assigned a priority level. These levels vary from the Implementation of the POS registers, arbitration, logic and
highest priority "-2" to the lowest priority "F". This "-2, -1, control sections typically requires only 1/3 to 2/3 of a single
0, 1, 2 ... A, B, ... F" scheme defines unique priority levels. XC2018 or XC3020; the remainder of the LCA is available
The higher levels are primarily used for memory refresh or for implementing the unique functionality of the specific
error recovery. The lower levels are reserved for the adapter card. Some Xilinx users have developed the
System Board processor and spares. The middle levels standard interface and stored it as a recallable macro
are used for DNA Ports 0-7, typically used for high speed function in the Xilinx development system. Applications
transfers. The priority level assigned to any adapter is including hard disk controllers, communication control-
stored in one of its POS register nibbles. The arbitration lers, and specialized memory controllers have been devel-
oped for the PS/2 using Xilinx FPGAs.
COMPLETE LATCH
ARBBUS3
ARB ID-3
ARB ID-2
ARB ID-1
~~~~==========~~==~~b-~--ARBBUS1
ARB ID-O
>c~L~:~~:I~~~~=)
')
ARB BUSO
,---- - - FOR
WONCHANNEL
COMPETITION
•
ARBI-ENT
1119 02A
6-51
DRAM Controller
with Error Correction and
Detection
Application Note BY TOM WAUGH
AN INTRODUCTION TO MEMORY CONTROL AND to incorporate error detection and correction into the
ERROR CORRECTION memory system. This solution decreases system perform-
ance and adds the cost of redundant memory, but pre-
The need to design memory controllers for systems that vents parity errors from causing system failures.
have a large amount of memory is a common design
challenge that engineers must deal with today. Almost all
large memory systems use dynamic random access OPTIONS FOR DRAM CONTROLLER DESIGN
memory (DRAM) because of its density and low cost.
While designing large memory systems with static random There are a number of options available to the engineer
access memory (SRAM), would make the design task designing a memory system that requires DRAM control.
easier, the drive to produce more cost effective products (The following options apply to the design of error detec-
forces the engineer to deSign with DRAMs, despite their tion and correction circuits as welL) The simplest option is
inherent drawbacks. The memory cell of a DRAM is a a standard off-the-shelf LSI memory controller. The manu-
capacitor that holds achargecorresponding to the value of facturers of these devices provide an integrated solution to
the data bij. Since all capacitors leak charge, a DRAM cell DRAM control by combining CPU interface logic with the
will gradually lose its charge, and its stored value, unless necessary memory access/memory refresh arbitration on
it is recharged. This recharging, known as refreshing, a single Chip. However, each memory system has unique
must typically be performed once every 2 to 4 ms depend- timing and protocol requirements, and it is extremely
ing on the DRAM. Refreshing is one of the DRAM difficult for these standard parts to accommodate the
controller's two primary functions. The other function is to requirements of every system. This realization has driven
arbitrate between requests for memory read and write many DRAM controller manufacturers to incorporate
accesses from the system's central processing unit and some degree of programmability into their parts to make
requirements for memory refreshes. them more flexible. Unfortunately, this has made the parts
more complex, hungrier for power, and more expensive.
In addition to its need for periodic refreshing, the DRAM Even so, they simply cannot meet every system's re-
exhibits another problem that SRAM and other memory quirements without employing external "glue logic."
devices do not-greater susceptibility to soft errors. A soft
error is the loss of a data bit in a memory cell in which the The need to match the DRAM controller to the specific
memory cell is not physically damaged. Rewriting the data requirements of the system has forced many engineers to
in the cell corrects the error. This type of error is different consider two options for creating their own controllers:
from a hard errorwhich is caused by a memory cell that has SSI/MSI packages or custom gate arrays. The use of SSI/
failed permanently. Soft errors in DRAMs are usually MSI is low risk, but wastes space and power; while the use
caused by alpha particles (helium nUClei), which are nor- of the custom gate array provides a highly integrated
mally present in the atmosphere, but which are more often solution, but at considerable risk and expense. Non-
emitted by radioactive impurities in the IC packages of the recurring engineering costs (NRE), testing and simulation
DRAMs themselves. If an alpha particle hits a memory costs, inventory risk, and a long design cycle make the
cell, it can corrupt the cell's charge, causing adata bit error. custom gate array option unattractive for most designs.
Most people believe that the likelihood of such an error is Recent architectural advances in high-density Field
so low that it can be safely ignored. While this may have Programmable Logic Arrays have created a third option.
been true for the smaller memory systems of the past, it Xilinx's 3000 family of FPGAs brings unprecedented
may no longer be so. The size of some memory systems density to programmable logic, with devices containihg as
today can make the likelihood of soft errors unacceptably many as 9000 gates. The 3000-family architecture makes
high. The probability of a soft error can be reduced by the devices particularly well-suited to memory-controller
device and packaging improvements and by reduction in applications.
signal noise. Another method of dealing with soft errors is
6-52
WHY IMPLEMENT A DRAM CONTROLLER WITH A comprising 44 256K DRAMs: 32 for data and 12 for the
FIELD PROGRAMMABLE GATE ARRAY? correction bits. A single LCA device can serve as both the
DRAM controller and the ECC, which performs single- bit
There are several reasons why one would want to design
error correction and double-bit error detection. There are
a DRAM controller with a Logic Cell Array. First, the true
several features of the 3000-family architecture that make
programmability of the LCA device gives the designer the
this design possible. These include five input-
freedom to design the DRAM controller to the exact
configurable logic blocks (CLBs) with two storage
specifications of the memory system. There is no need for
elements, internal buses, and flexible input/output
the external "glue logic" often necessary with standard
blocks (lOBs).
solutions, because any necessary design tweaking is
implemented internally. The LCA solution has the
advantage of the SSIIMSI or custom gate array solution in DESIGN OVERVIEW
that it can be configured to meet unique system The DRAM Controller/ECC uses a 16- MHz clock
requirements. There is no loss in integration as with the synchronized with the processor clock, and sits between
SSIIMSI solution, and the cost and risks of the custom gate the 8086 microprocessor with its 8288 bus controller and
array solution can be avoided. Second, the density of the the system memory (Figure 1). The 8288 decodes the
3000 family of LCAs makes it possible to implement DRAM processor status lines (S2' S1' So) and tells the DRAM
control and error detection/correction in a single LCA Controller whether it is to perform a Read or Write access
device. This is traditionally a two-chip solution using to the memory. (It is also possible to incorporate the bus
standard parts: a DRAM controller and a separate error controller logic into the larger LCAs). The DRAM
correction and detection unit. It can of course be Controller then performs the appropriate access issuing
implemented in a single custom gate array, but again with Row Address Strobe (RAS), Column Address Strobe
the earlier caveats. Finally, the CMOS LCA consumes (CAS), and Write, if necessary. The Error Checker and
less power than traditional standard "programmable" Corrector generates check bits on each Write, and checks
controllers which are typically implemented in NMOS or for and corrects errors on each Read. The controller also
bipolar processes. signals the 8086 if the memory access requires a Wait
state or if a non-correctable error is detected.
DESIGN EXAMPLE
SYSTEM TIMING
The following deSign example shows the implementation
of a DRAM controller and an error checker/corrector Figures 2a -2c show the timing involved in some of the
(ECC) with an LCA. The example is an 8-MHz 8086-based different memory cycles. The Word Write (Figure 2a)
system that directly addresses 1 Mbyte of memory requires no wait states as shown. The check bits from
the ECC are written to memory along with the data. The
8284
CLOCK
GENERATOR
READY
II
r--
~
ClK
READY
RESET
So t -
51 I--
8288
BUS
CONTROLLER
LeA W
CAS H,l
RASO,1 ~
~ 6+16=22
256KDRAMS
BANKO
(512 KBYTES)
BANK 1
(512 KBYTES)
52 t - MRDC READ
OUT 0-8 ~ AO-8
•
AMWC I : WRITE
CEN I-- HOLD I'
8086 CHECK DATA
DEN BITS BITS
J:f
BANK SELECT DATA
A19 BITS BITS
A16-18 A16-18
CBO-5
(CHECK BITS) k'=
ADO-15
~
--'--
ENABLE
r-- ,..ADO-15
MULTI-BIT r- TO 8086 NMI
ERROR
J
WAIT r--
-
74LS245
DATA BUS 16
1127 09A
Figure 1. System Overview of DRAM Controller with Error Correction and Detection.
6-53
DRAM Controller with Error Correction and Detection
T1 T2 T3 T4
8086
CLOCK
ALE ~~_________________________________________
CONTROLLER
CLOCK
RAS
CAS
------~<~----------------~)~----
OATAFROM
8086
112703
T2 T3 TW TW TW T4
8066
CLOCK
CONTROLLER
CLOCK
MS~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
'----------'I
CAS
l...--_~I
W
~
WAIT ~L.__________________________________~
ERROR DETECTED CORRECTED DATA LATCHED CORRECTED DATA RELEASED
112704
u I n I TW I ~ I
8086
CLOCK
~---'
n '-----'
n ~--'
n '-----'
n '---
RAS ~L-____________________________________~
CAS
--------~<~--------------~)~--
DATA FROM
DRAM
112705
6-54
Read cycle (Figures 2b & 2c) requires a minimum of one design, the address is latched into the lOB input flip-flop
wait state. The insertion of a wait state is unavoidable with the 8086 ALE. The data from the 8086 can enter the
because of the time it takes the 120-ns DRAMs to output same input pin andgo directly to the ECCcircuit via the lOB
the data. If the ECC detects no errors inthe data, the WAIT direct input-there is no need for external latches.
signal is released and the Read operation is completed. If
an error is detected, the insertion of two more wait states Another feature of the lOBs is the output flip-flops with
is required to provide time to correct the error. The three-state buffer enables. This feature permits bit error
insertion of the two additional wait states affects system correction using only one I/O pin. Figure 4 shows a bit-
performance, but this is the trade-off for having error sliced view of how the ECC is accomplished. A memory
correction, which avoids the fatal system errors that occur Read cycle provides the best example for showing the
with parity-checking-only solutions. capabilities of the lOB structure. During a Read, the lOB
output is 3-stated, permitting the DRAM data on the data
DESIGN FOCUS bus to enter the ECC via the lOB direct input. II the ECC
detects a data bit error, it corrects the error and latches the
The 3000-family LCA architecture has a number of fea- corrected data word into the output flip-flops of the lOBs.
tures that are essentialto the DRAM controller design. The The data bus is then 3-stated by turning off the DRAM
first such feature is the dual data input paths in the lOBs, outputs. The corrected word, latched in the outputs of the
one registered and one direct. This structure permits the flip-flops, is then released onto the data bus by enabling
address and data on a multiplexed bus to be latched from the 3-state buffer. This permits the corrected data to be
the same 110 pin. Figure 3 is a bit-sliced view of an lOB read by the 8086 at the same time it is being written back
used to latch the multiplexed Address/Data bus. In this to the DRAM.
:
,
,
r-------------------- ----
J.., r---,
r-"J-'O
I
r1>
I
0,...------------
L. ___
I
I
:
~
, - - - - - - j - - OUTPUT ENABLE
FROM ERROR
DIRECT NPUT
REGISTERED INPUT
DATA TO ERROR
CHECKEFVCORRECTOR
ADDRESS TO INTERNAL
r------I-.
r---,
g~~~~~~~~ECTOR
BUS VIA 3·STATE
BUFFER 10 OL __ -
I I
I I
I I
IL ___ .J~--
'---------
L _______________________ _
ALE
Figure 3. Address and Data Latching Figure 4. Data In and Out Through ECC
Latching Data off a Multiplexed Address and Data Bus. The data from the bus goes into the LCA, where it is
The Input/Output block configuration shown above corrected in the ECC. The corrected data is then put
illustrates how the direct and registered inputs in the back onto the bus via the lOB output flip-flop.
lOBs can be used to latch a multiplexed address/data
bus into the LCA. The address is latched into the lOB
II
flip-flop; the data flows directly into the ECC logic.
6-55
DRAM Controller with Error Correction and Detection
Figure 5 is a block level diagram of the DRAM Controller by this block include the row address and column address
and ECC that reside in the LCA. A functional description strobes (RAS and CAS), the WR ITE Signal, the WAIT-state
of each block follows: signal for the processor, the HOLD signal that isolates the
processor from the memory, the clock for the refresh
The refresh timer is driven by the 16-MHz clock to provide address counter, and the select control for the address
a signal that tells the DRAM controller that the memory select.
needs refreshing. Each of the 256 rows of memory in this
system must be refreshed every 4 ms. The controller The refresh address counter is an 8-bit counter that pro-
attempts to refresh eight rows every 1251JS, so that all 256 vides the 8-bit addresses necessary to refresh the DRAMs.
rows are refreshed in 4 ms. The refreshing technique
employed in this design is a unique combination of burst The address selector selects which address is sent to the
and hidden refreshing to show the flexibility of the DRAM. During a Read or Write cycle, the timing generator
LCA-based solution. There is no need to force a system to select control signal tells the address selector to select
conform to the constraints of an off-the-shelf part. The the DRAM row address, strobe it with the RAS, and then
Hidden Refresh is performed when the 8086 is doing a select the column address and strobe it with the CAS.
Read from or Write to somewhere other than memory, like During a refresh, the address selector selects the address
an I/O port. This involves giving the DRAM a refresh from the refresh address selector and strobes it into the
address from the refresh address counter via the address DRAM with RAS.
selector and a RAS pulse Low from the timing generator.
The Burst Refresh is performed only if it has not received During a Write cycle, the error checker/corrector (ECC)
its eight required refreshes during the 125-1JS refresh generates six check bits using a modified Hamming code
period. When a Burst Refresh is required, the co ntroller will for each 16-bit data word and writes them to memory along
isolate the memory from the 8086, insert wait states, and with the data. Use of a modified Hamming code permits
provide the number of refreshes it needs to complete the single-bit data correction and double-bit error detection.
eight refreshes required during the refresh period. During a Read cycle, the ECC compares the check bits
read back from memory with new check bits generated
The timing generator, a state machine triggered by Address from the data read back. If the comparison yields a
Latch Enable (ALE) at the beginning of the processor correctable error, the ECC will correct it. If the error is not
cycle, produces all the timing required to perform the correctable, it will flag the NMI on the processor.
memory accesses and refreshes. The signals generated
REFRESH TIMER
TIMING
GENERATOR 00·'5 CBO-5I===~ TO DRAM DATA
ECC ERROR CHECKER/
BURST REaUES'TL.--~ CONTROLS CORRECTOR
HIDDEN REaUES'TL.--~
MULTI·Brr ERROR TOSOS6 NMI
RESET
A '9 BANK SELECT W
RASo,' TODMM
CASH,L
FROM
BUS CONTROLLER WArr TOS088
HOLD TO BUS CONTROLLER
INCREMENT
COUNTER
1127 02A
6-56
E:X1l1NX
Perhaps the most important feature of the LCA architec- CONCLUSION
ture for implementing a DRAM Controller is Hs internal
three-state bus capability. The three-state buffer enables Although the bottom-up design of a DRAM controller is a
onto the horizontallonglines allow the designer to imple- complex task, it is necessary in cases in which off-the-shelf
ment an internal bus in the LCA. This feature permits the controllers do not meet the requirements of the system.
implementation of the Addre"'ss Selector without using any SSIlMSI and custom gate array solutions involve trade-
CLBs. Figure 6 shows a bH slice view. The row, column, offs and compromises. Designing a DRAM controller and
and refresh addresses all have access onto the internal ECC with an LCA is a straightforward application and a
bus, and to the outputs that lead to the DRAMs. By good fit for the 3000 family architecture. The Field Pro-
controlling the three-state enables, only one address is grammable Gate Array offers the flexibility necessary to
allowed onto the bus at a time. This feature is essential to match the many different memory systems,the integration
this design, and has many other applications including desirable for board level designs today, and the cost
performing wired-AND functions and address decoding. effectiveness required to make a competitive product.
112708
6-57
The Programmable Gate Array Company
6-58
SECTION 7
Article Reprints
2 Product Specifications
4 Technical Support
5 Development Systems
6 Applications
7 Article Reprints
8 Index
Article Reprints
BUILD RECONFIGURABLE
PERIPHERAL CONTROLLERS
uring the design of a computer peripheral, such
as a printer, CRT terminal, disk drive, or other
complex subsystem, decisions are often made
regarding control logic partitioning. In some in-
stances, the peripheral contains all of the control
circuits, and the interface to a host system is
over a standard port, such as an RS-232 or a Centronics link. However, the
limited data-transfer speed and signal-control flexibility of those ports often
causes a bottleneck when very large amounts of data must be transferred or
complex operations must be controlled.
One solution is to keep the data-intensive portion of the logic in an adapter
board that plugs into the host computer's bus and supply a custom high-speed
link to the peripheral. But using hardwired logic to implement the adapter card
limits the card's flexibility if updated versions ofthe peripherals are released, or
if a second, relatively different model is developed. Ideally, one adapter card
should be all that's needed. Simple software updates (device drivers) that can be
loaded into the card for the specific model peripheral can provide an optimized
interface.
Such a peripheral-control card can readily be developed by taking advantage
of RAM-based programmable logic circuits, such as the logic cell arrays from
Xilinx (see "RAM-based Programmable Logic''). And the card's function can
be altered in the field with just a new software driver that's loaded when the sys-
tem boots.
Furthermore, if the data is RAM -based, it can be altered during system opera-
tion as well. Consequently, if the same card must control multiple printer types,
the card can be switched between printer drivers in just milliseconds by reload-
ing the RAM-based programmable logic circuits to reconfigure the interface on-
the-fly. Such a controller can be easily modified to support new peripheral de-
vices, and it will never have to be removed from the computer system.
Programmable logic devices based on static RAM memory cells make it possi-
ble to implement "soft" hardware-that is, hardware whose functions can be
KENNETH K. HILLEN
Tektronix Inc., Mail Stop 63-356, P.O. Box 1000, Wilsonville, OR 97070;
(503) 685-3904.
BRADLY FAWCETT
Xilinx Inc., 2100 Logic Dr., San Jose, CA 95124; (408) 559-7778.
7-1
Article Reprints
FLEXIBLE PRINTER
CONTROLLER
serCard printer controller from the
r:-- Graphics Printing and Imaging Divi-
IBM Pc bus
~~ ~
Bus sion of Tektronix. By implementing
.
...
inte~ace the system architecture in that fash-
68020 chip ion, the card helps designers make
'--- r:-- printer changes or add new printers,
~ Printer still keeping the design cycle very
t . <:]r- short because there are less circuits
WIII..1ate ~ Prlnter-
IIIdpUlchip - ~
in the printer to deal with.
generalor
8·bHdalabus XC2018
- A key ease-of-use feature for laser
and color thermal printers would be
~
decoder 1-
24-bil
H 512.byIe
FIFO buffer
to have them emulate Adobe Sys-
tem's Postscript and Hewlett-Pack-
ard's HPGL graphics-description
32·bH dill bus addraaabus languages. To do that, the host sys-
tem plug-in board includes the emu-
Pixel lation capability along with a 68000-
coprocessor ROM family microprocessor and a custom
~ ~ chip that accelerates the computa-
tions needed to prepare an image for
r-- printing. Furthermore, the PCI ATI
Mtmary t--- XT bus-compatible card uses one of
RAM and
~ CPUragiater r--- EEPROM
~
-EPROM the smaller Xilinx programmable
gate arrays for the printer interface
7-2
i,l,i1 ftl·,tg;iI9,jiUilhj
FLEXIBLE PRINTER
CONTROLLER
converting the page description into the configuration programs for the one holds program code, another
the raster image, a custom graphics programmable logic chip reside in serves as a data buffer, and the third
coprocessor tackles all of the compu- on-board RAM. That RAM would holds the bit map for A-size, 150-dpi
tations. The chip is a full-custom I C, typically be loaded from the host sys- (dots per inch) printers. The addition-
and assists in image generation dur- tem's hard disk. Code updates could al memory is required for A- or B-
ing line drawing, area filling, and thus be distributed on diskettes, size, 300-dpi printers. Power-up diag-
half-toning operations. Lines can be eliminating the need for a technician nostics and the bootstrap routine for
drawn at 6 million pixels/so or service person to replace a nonvol- downloading from the hard disk are
During operation, the CPU ac- atile memory chip from the control held in 64 kbytes of EPROM, while a
cepts image description input board to upgrade the card. To hold 512-byte electrically-erasable memo-
streams from the host bus, raster- the control code and the page de- ry holds several parameters that pro-
izes the image into bit-map memory scription, 3 Mbytes of dynamic RAM cess Postscript files and provide
(with assistance from the coproces- are included on the control card, and printer identification information.
sor), and then transfers the bit map an additional 5 to 8 Mbytes can be A bus interface circuit (BIF), im-
to the printer interface logic. All tim- added through a memory-expansion plemented with a 5000-gate mask-
ing signals are derived from a 24.23 connector and a daughterboard. programmed gate array, connects
MHz oscillator. The on-board memory is parti- the controller to the PC bus. The BIF
The processor's code and data, and tioned into three I-Mbyte blocks- chip emulates standard LPT (paral-
;~'bWi 0 0 0
and control logic. Programmable
interconnection resources pro-
vide the routing paths that con-
nect the 110 and logic blocks in
the desired configuration.
Similar to a microprocessor, the
LCA is a program-driven device.
The configuration program is
loaded automatically from an ex-
ternal memory on power-up or on
D 01-00 0
7-3
Article Reprints
',IM!H'·,jijij!!q.liUl ~,
FLEXIBLE PRINTER
CONTROLLER
other tasks while the printer re-
ceives the data at its own pace.
Output Signal buffers external to the LCA
connectort
are used to isolate the LCA from the
CPU output connectors, as well as give ad-
ditional drive capability and electro-
static protection for the CMOS chip.
The output signals are buffered with
dual byte-wide transparent latches.
Output Typically, only one byte-wide set of
connector 2 latches will be transparent at one
time; the other will be left holding a
7-4
E:XIUNX
lu£iiH ',qgIlR·lllu.tt
FLEXIBLE PRINTER
CONTROLLER
The configuration program is then ed to a serial data stream for the serial-out shift register that con-
downloaded to the LCA as a serial bit Phaser CP printer. verts the byte-wide data from the
stream using one clock and one data Logic in the LCA generates all of FIFO buffer to a serial format. The
line. The LCA drives the Done/Pro· the required handshaking and tim- remaining logic configured in the
gram line back to the high state to ing signals. CPU interrupts are gen- LCA includes a clock divider to con-
signal the end of the configuration erated as needed, based on the status trol the shift register, a divider to
process. Downloading a configura· of the printers, FIFO buffer, and the generate the data clock to the print-
tion program takes less than 60 ms. LCA's internal state machine. Con- er, a clock divider and state machine
When two printers are connected trol and status registers that can be to generate the horizontal synchroni-
to the card, selection of the correct accessed by the CPU also are imple- zation (Hsync) signal, and the pro-
configuration program is controlled mented in the LCA. cessor interface and interrupt regis-
by the processor; when a printer is to To show how the LCA can be con- ters (Fig. 3). All of that logic employs
be accessed, the LCA is configured figured for various printers, three 78 of the 100 logic blocks available in
for that particular interface. If two specific configurations that each use theXC2018.
different printers are connected, the about 2/3 of the 74 user-programma- The data-clock generator divides
LCA is reconfigured frequently duro ble I/O pins in the LCA must be ex- the 24.23-MHz board clock by 10 to
ing idle (non-printing) periods to amined. The first configuration create the 50%-duty-cycle 2.4-MHz
check each printer's status. looks at the interface to the Phaser clock that sends the serial data
In general, the operation of the CP, a 300-dpi wax-transfer color stream to the printer. This data clock
configured LCA chip is similar for all printer with a serial interface; the is further divided by 8 to control the
printer types. The CPU writes data second examines a parallel interface shift register. On every eighth data
to the FIFO buffer, and a state ma- to the 4693D/DX color printer; and clock, the next byte in the FIFO buff-
chine created in the LCA reads the the third shows a raw video interface er is loaded into the shift register.
data from the buffer and sends it to to a bare-bones laser printer. A small state machine composed
the printer. Any necessary data for- To control a serial-input printer, of four flip-flops generates the
matting is performed in the LCA. such as the Phaser CP, part of the Hsync signal and enables clocks and
For example, data bytes are convert- LCA must implement a parallel-inl data to be sent to the printer. After
being enabled by the CPU, the state
Data input-------. machine waits for a 400-Hz signal
from FIFO buffer from the bus interface chip. A 12.5-
kHz clock is used to sequence the
state machine, which generates an 8
/Ls Hsync pulse, followed by an 8 /Ls
delay. Then the state machine can
start the data stream. The data stops
when the EOL flag (the ninth bit in
the FIFO memory word) is read from
the FIFO buffer.
With six 8-bit processor interface
registers, the CPU can write control
information and read status infor-
mation. These registers are mapped
Data to into the CPU's I/O address space;
~;==;;=::;:;:;tT- 4693D/DX four are write-only and two are read"
only (see the table). The three inter-
Data strobe rupt registers share the same bit as-
signments; bits 4 and 5 of the chip-
control register control the transpar-
~~~~~~------- Externalcontroi ent latches for the two printer
r signals
connectors.
Topr_sor .....---+----1 Because both connectors are driv-
+----_ Statusfrom en by the same pins of the LCA de-
4693D/DX vice, these bits force one connector's
outputs to a static state (by disabling
7-5
Article Reprints
,utiiA l,jijillhf.ilUl$'
FLEXIBLE PRINTER
CONTROLLER
control, 16 bits of status information, binatoriallogic. cludes controls to clear the FIFO
identifying such conditions as paper A simple six-state state machine buffer, start the output state ma-
jams, out-of-paper, and out-of-rib- combined with a 3-bit counter con- chine, enable the command mode, en-
bon, can be read back one at a time trols the data flow and commands to able the transparent latches associ-
through bit 2 of the printer status the printer. The 24.23-MHz clock is ated with the two printer connectors,
register. divided to supply a clock of approxi- and enable the CMYB-to-RGB con-
The parallel interface of the mately 5 MHz to the state machine. verter. The printer-command regis-
4693DIDX printer requires 79 of the The state machine sends data to the ter holds commands to be sent to the
LCA's logic blocks. To implement printer by reading it from the FIFO printer, and the printer-status regis-
that interface, the main functional buffer, then stores it in the input reg- ter contains status information
blocks that must be configured in the ister, converts it to the RGB format about the printer and the FIFO buff-
LCA include an input-data register, a (if required, as determined by a bit in er. Interrupt-clear, mask, and read
data converter, a state machine to the chip control register), and as- registers control the generation of
control the data transfer between serts the Data Strobe signal. interrupts to the CPU.
the LCA and the printer, and the pro- Data is sent in a streaming mode-
cessor interface and interrupt regis- the machine will keep sending data HANDLING VIDEO DATA
ters (Fig. 4). to the printer until a byte marked When configuring the LCA chip to
An 8-bit register is used to latch with an EOL indicator is read from deliver the video data stream to the
the data as it comes in from the FIFO the FIFO buffer. The transfer of a Canon LBP8 laser printer, the data
buffer. The ninth bit, which indicates command byte to the printer is trig- from the controller card must be pre-
the EOL condition, goes to the state gered by loading the printer-com- cisely synchronized with the laser
machine and interrupt registers. Op- mand register and setting a bit in the mechanism to ensure image accura-
tionally, the data can be converted chip-control register. The state ma- cy. Major circuit elements in this con-
from the cyan-magenta-yellow-black chine controls the command sent to figuration include clock dividers that
(CMYB) format generated by the the printer and waits for the acknow- produce the data clock and control
controller card to the red-green-blue ledgement. FIFO-buffer read operations, a par-
(RGB) format (some early versions The six 8-bit processor interface allel-to-serial shift register to serial-
of the 4693DIDX printer accept only registers are similar in function to ize the data, a simple state machine
the RGB format). This straightfor- those described for the Phaser CP to control data flow, a serial-to-paral-
ward conversion requires only com- printer. The chip-control register in- leI shift register to collect printer
status information, and the proces-
Datakom-----------;:===l_ _ _--, sor interface and status registers
FIFO buffer (Fig. 5). This configuration uses 97 of
FIFO buffer _-:=====-I'1I--:/>_LP-=ar=all=el-=.to-~se=ri:::al=Sh::.:ifl~re:gi:::ste::.rJ Video data
toLBP8 the 100 logic blocks in the LCA.
read clock r4>r---:::-,:,:",:-:--~' T The 24.23-MHz clock is first divid-
I L- Divideby8 r ed by 13 to produce the 1.863-MHz
data clock needed for the data trans-
fer to the parallel-to-serial shift reg-
24.23 MHz Divide by 13 f-- Beam Detect signal ister. The data clock is further divid-
CIOC~ I
ed by eight to generate the signal
that's used to read a new byte from
M
and the FIFO buffer and load it into the
slate machine, Serial clock output
shift register as the transmission of
Shiftregisler Command/Status to/ the previous byte to the printer is
from LBP8 completed.
1 To ensure that the data is properly
positioned on the page, the data clock
}l
---1 Control registers External control signals
isn't started until a Beam Detect sig-
nal is received from the printer. This
signal is sent at the start of each scan
To processor I Status register line. Data clocks will continue to be
I
Status from LBP8 generated and data sent to the print-
er until an EOL mark is read from
---l tnterruptregisters
the FIFO buffer. The controller then
1 5. CONTROLLING Alaser engine directly on the Canon LBP8 requires that the LCA
supply precise data and control signals. Data input still requires a parallel·to-serial shift
register, and several divider chains are needed to aoliust the clock rate. Asmall state
machine controls the data transfer and a simple bidirectional shift register.
waits for the next Beam Detect to
start again. The state machine is just
one flip-flop that's enabled by a bit in
the chip-control register, set by a
Beam Detect, and cleared when the
7-6
E:XIUNX
FLEXIBLE PRINTER
CONTROLLER
quest for verti- editor from Xilinx, a development
REGISTER BIT cal synchroniza- tool that allows users to manipUlate
ASSIGNMENTS FOR PHASER CP tion. Interrupt- a graphics image of the internal LCA
Register Read/write Bit assignments clear, mask, and architecture. About three weeks are
Chip control write bit 0 - Clear FIFO buffer read registers usually needed for LCA newcomers
bit 4 - Control transparent latch to color printer control the gen- to enter and debug the first circuit.
bit 5 - Control transparent latch to monochrome printer
bit 6 - Reset the printer eration of inter- Each subsequent configuration
Printer control write bit 1- Start printer output state machine
rupts to the that's generated may typically re-
bit 2 - Output enable CPU. quire less than one week's develop-
bit 3 - Command synchronization As with most menttime.
bit 4 - Double the vertical resolution
bit 5 - Skip to next ribbon color
logic technolo- The placement and routing of the
bit 6 -load sheet of paper gies, the control- circuitry can be a major area of con-
bit 7 - Get next bit of printer status ler card's design cern because a limited amount of
Printer status read bit 0 - Printer status state machine at start was originally routing resources are available near
bit 1 - Printer ready for current pass conceived as each CLB. That was a key concern
bit 2 - Serial status data read back
bit 3 - On·line indicator block diagrams for the XC2018 because a large num-
bit 4 - Cable disconnected indicator and schematic ber of CLBs had to be interconnected
bit5 - Power·off indicator drawings. Early to create the next-state equations.
Interrupt clear write bit 0 - FIFO buffer empty in the system de- The net routings using the LCA's
Interrupt mask write bit 1 - FIFO buffer lull
Interrupt read read bit 2 - Printer ready slate change
sign cycle, the general-purpose interconnections
bit 3 - On·line state change portions of the sometimes result in surprisingly
bit 4 - Printer power off design to be im- long propagation delays. To mini-
bit 5- EOL (End·ol-line)
plemented in the mize the delays, the CLBs were clus-
LCA were deter- tered so that the time-critical paths
EOL mark is encountered. mined. State machine designs can be were kept as short as possible. The
The LBP8 printer uses a serial done with Mealy/Moore diagrams, reprogrammable nature of the array
path to receive certain commands which can be translated into a set of makes it possible for multiple what-
and send back its status. These mes- reduced next-state equations using if scenarios to be evaluated.
sages are clocked through a serial- the Abel software package from Because LCAs can be quickly and
to-parallel! paralle !'to-serial shift Data I/O Corp., Redmond, Wash. easily reconfigured, special configu-
register in the LCA, making it possi- Designing large state machines in rations can be generated for test pur-
ble for the CPU to write commands the LCA can use up numerous inter- poses during system development.
and read status information as one nal configurable logic blocks (CLBs) During prototyping, a number of in-
byte. very quickly because many state ma- ternal signals can be routed to the
The interface to the CPU consists chines can have a dozen or more in- otherwise unused 1/ 0 pins to aid in
of eight 8-bit control, status, and in- puts to the next-state equations. the debugging process. A special di-
terrupt registers. The chip-control However, by applying automata the- agnostic configuration can also be in-
register and printer-control register oryto find common terms that can be cluded in the final production design
include controls to clear the FIFO shared by more than one equation, to ease the power-up diagnostic rou-
buffer, start the output state ma- the number of inputs to each CLB tines and servicing.D
chine, control the transparent latch- was kept to four or less.
es of the printer connectors, reset Furthermore, because the XC2018 Reprinted with pennission from Elec-
the printer, synchronize the image LCAs don't have three-state out- tronic Design March 8,1990. © Penton
vertically, request the start of a new puts, CLBi had to be used to imple- Publications.
page, and notify the printer that the ment 2:1 mUltiplexers to handle in-
controller is ready. ternal-register readback. The multi-
One bidirectional shift register plexers would then select which of
constitutes both the printer-com- several registers would be connect-
mand register and the printer-re- ed to the processor's data bus during
sponse register. The printer-com- a read operation. In most cases, the
mand register holds commands to be CLB that contained the register had
sent to the printer serially; the print- enough unused logic to implement
er responds by sending the request- the multiplexer. As a result, the need
II
ed information to the printer-re- for the mUltiplexers doesn't have an
sponse register. The printer-status impact on the number of CLBs avail-
register holds additional status in- able for the main control logic.
formation from the printer, such as The design can now be mapped
the Beam Detect signal status, into the logic and I/O blocks of the
ready-to-print indicator, and a re- LeA device using the XACT design
7-7
Article Reprints
DESIGN APPLICATIONS
STEVEN K. KNAPP
Xilinx Inc., 2100 Logic Dr.,
San Jose, CA 95124;
(408) 879-5172.
7-8
STATE MACHINE
DESIGN
many-input logic function in one lev-
el of logic, an FPGA might require
mUltiple logic layers due to the limit-
ed number of inputs.
The OHE scheme is named so be-
cause only one state flip-flop is as-
serted, or "hot," ata time. Using the
one-hot-encoding method for FPGAs
State! was originally conceived by High-
Slate 7 I Gate Design-a Saratoga, Calif.-
I
I based consulting firm specializing in
IL __________ ...JI FPGA designs.
The OHE state machine's basic
1 2. INVERTERS ARE REQUIRED althe D iDput and the Q output of the state
flip-fiop to eDsure that it powers ... iD the proper state. CombiDatoriallogio decodes the
operations based OD the iDput oonditi...s and the state feedbaok signals. The flip-fiop will
remaiD in State l .. loDC .. the oonditi...al paths out of the state are not valid.
structure is simple-first assign an
individual flip-flop to each state, and
then permit only one state to be ac-
tive at any time. A state machine
with 16 states would require 16 flip-
flops using the OHE approach; a
generally have many, wide-input log- as for small state machines. It's up to highly encoded state machine would
ic functions to interpret the inputs the designer to evaluate all ap- need just 4 flip-flops. At first glance,
and decode the states. Furthermore, proaches before settling on one for a OHE may seem counter-intuitive.
incorporating a highly encoded state particular application. For designers accustomed to using
machine in an FPGA requires sever- FPGAs are high-density program- PLDs, more flip-flops typically indi-
allevels of logic between clock edges mable chips that contain a large ar- cates either using a larger PLD or
because mUltiple logic blocks will be ray of user-configurable logic blocks even multiple devices.
needed for decoding the states. A surrounded by user-programmable In an FPGA, however, OHE yields
better way to implement state ma- interconnects. Generally, the logic a state machine that generally re-
chines in FPGAs is to match the blocks in an FPGA have a limited quires fewer resources and has high-
state-machine architecture to the de- number of inputs. The logic block in er performance than a binary-en-
vice architecture. the Xilinx XC-3000 series, for in- coded implementation. OHE has def-
stance, can implement any function inite advantages for FPGA designs
LIMITING FAN·IN of five or less inputs. In contrast, a because it exploits the strengths of
A good state-machine approach PAL macrocell is fed by each input to the FPGA architecture. It usually re-
for FPGAs limits the amount of fan- the chip and all of the flip-flops. This quires two or less levels of logic be-
in into one logic block. While the one- difference in logic structure be- tween clock edges than binary en-
hot method is best for most FPGA tween PALs and FPGAs is impor- coding. That translates into faster
applications, binary encoding is still tant for functions with many inputs: operation. Logic circuits are also
more efficient in certain cases, such Where a PAL could implement a simplified because OHE removes
much of the state-decoding logic-a
one-hot-encoded state machine is al-
ready fully decoded.
OHE requires only one input to de-
code a state, making the next-state
logic simple and well-suited to the
limited fan-in architecture of
State 4 FPGAs. In addition, the resulting
collection of flip-flops is similar to a
shift-register-like structure, which
RD can placed and routed efficiently in-
side an FPGA device. The speed of an
State 3 OHE state machine remains fairly
constant even as the number of
states grows. In contrast, a highly
encoded state machine's perfor- I
1 3. OF THE SEVEN STATES, thestate-tra..iti... Iocio required for State (is the
most oomplex, requiring inputs from three other state outputs .. "ell .. four of the five
COnditiOD signals (A - D).
mance drops as the states grow be-
cause of the wider and deeper decod-
ing logic that's required.
To build the next-state logic for
DESIGN
7-9
Article Reprints
STATE MACHINE
DESIGN
count the number of condi- leading away from State 4 is
tional paths leading into the State 2 Cantig valid whenever the product,
state and add an extra path A'B 'C, is true. Consequent·
if the default condition is to State 7 ly, State 4 must be ANDed
remain in the same state. E with the inverse of the prod-
Second. build an OR'gate uct, A'B'C. In other words,
Clocl<
with the number of inputs "keep loading the flip·flop
equal to the number of con· with a high until a valid
1
ditional paths that were de- transfer to the next state oc-
termined in the first step. 6. 8-R FLIP-FLOPS OFFER ANOTHER curs." The default path log-
Third. for each input of approach to decoding the Contig output. They can also save ic uses AND-7 and shares
the OR-gate. build an AND- logic blocks. especially when an output is asserted for a long the output of AND-6.
gate of the previous state sequence of contiguous states. Configuring the logic to
and its conditional logic. Fi- handle the remaining states
nally. if the default should remain in logic to perform this function is im- is very simple. State 2, for example,
the same state. build an AND-gate of plemented in the gate labeled AND-3 has only one conditional path, which
the present state and the inverse of and the logic elements that feed into comes from State 1 whenever the
all possible conditional paths leav- the inverting input of AND·3 (Fig. 2, product A'B'C is true. However, the
ing the present state. again). state machine will immediately
To determine the number of condi· State 4 is the most complex state in branch in one of two ways from State
tional paths feeding State 1, examine the state-machine example. Howev· 2, depending on the value of D.
the state diagram-State 1 has one er, creating the logic for its next· There's no default logic to remain in
path from State 7 whenever the vari- state control follows the same basic State 2 (Fig. 4, top). State 3, like
able E is true. Another path is the method as described earlier. To be- States 1 and 4, has a default state,
default condition, which stays in gin with, State 4 isn't the initial state, and combines the A, D, State 2, and
State 1. As a result, there are two so it uses a normal D-type flip-flop State·3 feedback to control the flip-
conditional paths feeding State 1. without the inverters. It does, how- flop's D input (Fig. 4, bottom).
Next, build a 2-input OR-gate-one ever, have an asynchronous reset in- State 5 feeds State 6 uncondition-
input for the conditional path from put, three paths into the state, and a ally. Note that the state machine
State 7, the other for the default path default condition that stays in State waits until variable E is low in State 6
to stay in State 1 (shown as OR·1 in 4. Therefore, a four-input OR-gate before proceeding to State 7. Again,
Fig. 2). feeds the flip-flop (OR-1 in Fig. 3). while in State 7, the state machine
The next step is to build the condi- The first conditional path comes waits for variable E to return to true
tional logic feeding the OR-gate. from State 3. Following the methods before moving to State 1 (Fig. 5).
Each input into the OR-gate is the established earlier, an AND of State
logical AND of the previous state 3 and the conditional logic, which is A OUTPUT DEFINITIONS
and its conditional logic feeding into ORed with D, must be implemented After defining all of the state tran-
State 1. State 7, for example, feeds (AND-2 and OR-3 in Fig. 3). The sition logic, the next step is to define
State 1 whenever E is true and is im- next conditional path is from State 2, the output logic. The three output
pie men ted using the gate called which requires an AND of State 2 signals-Single, Multi, and Contig-
AND-2(Fig.2,again).Thesecondin- and variable D (AND-4 in Fig. 3). each fall into one of three primary
put into the OR-gate is the default Lastly, the final conditional path output types:
transition that's to remain in State 1. leading into State 4 is from State 1. 1. Outputs asserted during one
In other words, if the current state is Again, the State-1 output must be state, which is the simplest case. The
State 1, and no conditional paths ANDed with its conditional path los:: output signal Single, asserted only
leaving State 1 are valid, then the ie-the logical product, A 'B'C during State 6, is an example.
state machine should remain in State (AND-5 and AND·6 in Fig. 3). 2. Outputs asserted during multi-
1. Note in the state diagram that two Now/, all that must be done is to ple, contiguous states. This appears
conditional paths are leaving State 1 build the logic that remains in State 4 simple at first glance, but a few tech-
(Fig. 1, again). Iwhen none of the conditional paths niques exist that reduce logic com-
The first path is valid whenever away from State 4 are true. The path plexity. One example is Contig. It's
(A 'B'C) is true, which leads asserted from State 3 to
into State 2. The second path ONE-STATE VS. State 7, even though there's
is valid whenever (A 'B '0 is BINARY ENCODING METHODS a branch at State 2.
true, leading into State 4. To Hamberot wont.... 3. Outputs asserted dur-
build the default logic, State Method Ioglcbl..... potfamI... ing multiple, non-contigu-
1 is ANDed with the inverse One-hot 7.5 40MHz ous states, The best solution
of all of the conditional is usually brute-force decod-
Binary encoding 7.0 34 MHz
paths leaving State 1. The ing of the active states. One
I~E~E:BE~IL9~ 0 N I C DESIGN
7-10
lu'iiH!lliijijl!h'l1i!~j
STATE MACHINE
DESIGN
OHE state machines is simple, lend-
ing itself to a "cookbook" approach.
At first glance, designers familiar
with PAL-type devices may be con- State 2
cerned by the number of potential il-
legal states due to the sparse state State 1
encoding. This issue, to be discussed
later, can be solved easily. RD
A typical, simple state machine
might contain seven distinct states
that can be described with the com-
monly used circle-and-arc bubble dia-
grams (Fig. 1). The label above the
line in each "bubble" is the state's
name, the labels below the line are
the outputs asserted while the state
is active. In the example, there are State 3
seven states labeled State 1-7. The
"arcs" that feed back into the same
state are the default paths. These Stata2
will be true only if no other condition-
al paths are true.
Each conditional path is labeled
with the appropriate logical condi-
1
tion that must exist before moving to
the next state. All of the logic inputs 4. ONLY AFEW GATES are required by Stales 2 IDd 3 to form simple slate-
are labeled as variables A through E. tr...iti.. logic deeodilll. Just two ptes are Deeded by Slale 2 (top), while four simple gates
The outputs from the state machine are used by State 3 (bottom).
are called Single, Multi, and Contig.
For this example, State 1, which faster (see the table). Intuitively, the coded design had three. For other
must be asserted at power-on, has a one-hot method might seem to em- applications, the results can be far
doubly-inverted flip-flop structure ploy many more logic blocks than the more dramatic. In many cases, the
(shaded region ofFig. 2). highly encoded approach .. But the one-hot method yields a state ma-
The state machine in the example highly encoded state machine needs chine with one layer of logic between
was built twice, once using OHE and more combinatorial logic to decode clock edges. With one layer of logic,
again with· the highly encoded ap- the encoded state values. a one-hot state machine can operate
proach employed in most PAL de- The OHE approach produces a at 50 to 60 MHz.
signs. A XilinxXC3020-1002000-gate state machine with a shift-register The initial or power-on condition in
FPGA was the target for both imple- structure that almost always outper- a state machine must be examined
mentations. Though the OHE circuit forms a highly encoded state ma- carefully. At power-on, a state ma-
required slightly more logic than the chine in FPGAs. The one-state de- chine should always enter an initial,
highly-encoded state machine, the sign had only two layers of logic be- known state. For the Xilinx FPGA
one-hot state machine operated 17% tween flip-flops, while the highly en- family, all flip-flops are reset at pow-
er-on automatically. To assert an ini-
tial state at power·on, the output
from the initial-state flip-flop is in-
verted. To maintain logical consis-
tency, the input to flip-flop also is in-
verted.
All other states use a standard, D-
type flip-flop with an asynchronous
reset input. The purpose of the asyn-
chronous reset input will be dis-
cussed later when illegal states are
covered. III
1
Once the start-up conditions are
6. LOOKING NEARLY THE SAME .. a simple ahilt recister, the logic for set up, the next-state transition logic
Stales 6, 6, aod 7 is very limple. This il because the OBE scheme e1imiDates almo.1 all can be configured. To do that, first
deeodllllioliclhal precedes eaeh flipoflop. examine an individual state. Then
DESIGN
7-11
Article ReprInts
STATE MACHINE
DESIGN
such example is Multi, which is as- Contig isn't asserted as it traverses flip-flop-rich architecture of an
serted during State 2 and State 4. from State 3 or 4 to State 7. Other- FPGA is ideal.
OHE makes defining outputs wise, these states would not be con- Even off-chip inputs can be syn-
easy. In many cases, the state flip- tiguous for the Contig output. chronized in the available input flip-
flop is the output. For example, the The Contig output logic, built from flops. And internal signals can be
Single output also is the flip-flop out- an S-R flip-flop, will be set with State synchronized using the logic block's
put for State 6; no additional logic is 2 and reset when leaving State 7 flip-flops (in the case of the Xilinx
required. The Contig output is as- (Fig. 6). As an added benefit, the LCAs). The extra synchronization
serted throughout States 3 through Contig output is synchronized to the logic is free, especially in the Xilinx
7. Though the paths between these master clock. Obvious logic reduc- FPGA family where every block has
states may vary, the state machine tion techniques shouldn't be over- an optional flip-flop in the logic path.
will always traverse from State 2 to a looked either. For example, the Con-
point where Contig is active in either tig output is active in all states ex- RESETTING STATE BITS
State 3 or State 4. cept for States 1 and 2. Decoding the Resetting the state machine to a
There are many ways to imple- states where Contig isn't true, and legal state, either periodically or
ment the output logic for the Contig then asserting the inverse, is anoth- when an illegal state is detected,
output. The easiest method is to de- er way to specify Contig. gives designers yet another choice.
code States 3, 4, 5, 6, and 7 with a 5- The Multi output is asserted dur- The Reset Direct (RD) inputs to the
input OR gate. Any time the state ing multiple, non-contiguous flip-flops are useful in this case .. Be-
machine is in one of these states, states-exclusively during States 2 cause only one state bit should be set
Contig will be active. Simple decod- and 4. Though States 2 and 4 are con- at any time, the output of a state can
ing works best for this state machine tiguous in some cases, the state ma- reset other state bits. For example,
example. Decoding five states won't chine may traverse from State 2 to State 4 can reset State 3.
exceed the input capability of the State 4 via State 3, where the Multi If the state machine did fall into an
FPGA logic block. output is unasserted. Simple decod- illegal condition, eventually State 4
ing of the active states is generally would be asserted, clearing State 3.
ADDITIONAL LOGIC best for non-contiguous states. If the However, State 4 can't be used to re-
However, when an output must be output is active during multiple, non- set State 5, otherwise the state ma-
asserted over a longer sequence of contiguous states over long se- chine won't operate correctly. To be
states (six or more), additional layers quences, the S-R flip-flop approach specific, it will never transfer to
of decoding logic would be required. described earlier may be useful. State 5; it will always be held reset by
Those additional logic layers reduce One common issue in state-ma- State 4. Likewise, State 3 can reset
the state machine's performance. chine construction deals with pre- State 2, State 5 can reset State 4,
Employing S-R flip-flops gives de- venting illegal states from corrupt- etc.-as long as one state doesn't re-
signers another option when decod- ing system operation. Illegal states set a state that it feeds.
ing outputs over multiple, contigu- exist in areas where the state ma- This technique guarantees a peri-
ous states. Though the basic FPGA chine's functionality is undefined or odic, valid condition for the state ma-
architecture may not have physical invalid. For state machines imple- chine with little additional overhead.
S-R flip-flops, most macrocelllibrar- mented in PAL devices, the state-ma- Notice, however, that State 1 is nev-
ies contain one built from logic and chine compiler software usually gen- er reset. If State 1 were "reset," it
D-type flip-flops. Using S-R flip- erates logic to prevent or to recover would force the output of State 1
flops is especially valuable when an from illegal conditions. high, causing two states to be active
output is active for six or more con- In the OHE approach, an illegal simultaneously (which, by defini-
tiguous states. condition will occur whenever two or tion, is illegal).o
The S-R flip-flop is set when enter- more states are active simultaneous-
ing the contiguous states, and reset ly. By definition, the one-hot method Reprinted with pennission from Elec-
when leaving. It usually requires ex- makes it possible for the state ma- tronic Design September 13, 1990.
tra logic to look at the state just prior chine to be in only one state at a time. © Penton Publications.
to the beginning and ending state. The logic must either prevent multi-
This approach is handy when an out- ple, simultaneous states or avoid the
put covers multiple, non-contiguous situation entirely.
states, assuming there are enough Synchronizing all of the state-ma-
logic savings to justify its use. chine inputs to the master clock sig-
In the example, States 3 through 7 nal is one way to prevent illegal
can be considered contiguous. Con- states. "Strange" transitions won't
tig is set after leaving State 2 for ei- occur when an asynchronous input
ther States 3 or 4, and is reset after changes too closely to a clock edge.
leaving State 7 for State 1. There are Though extra synchronization
no conditional jumps to states where would be costly in PAL devices, the
E LEe T RON I C
7-12
E:XlLlNX
Design In
Reprogrammable Missile:
How an FPGA Adds Flexibility
to the Navy's Tomahawk
By Kent Tallyn
Design Engineer
McDonnell Douglas
Electronic Systems Co.
St. Louis, Mo.
worry about the expense and time which first determines the proper But rather than designing aeparate I/O blocks, and programmable
involved with redoing the chip's scan ~ate and passes this informa~ logic for each mode, McDonnell interconnection resources. Config-
mask layer - change$ could be tion to a set of counters which gen- engineers drew on the pro· uration is established by program·
III
made in software alone. erate the timing signals for the digi- grammable gate array technology min,g intemal static memory cells
The conventional land-attack tizer. The video image is passed and designed the system so the that determine the lOgic functiona
Tomahawk is a long~range Navy through a set of digital filters, operating snltware for each mode and interconnectiona. The conligu-
AprillSl90
7-13
Article Reprints
_ _ Design In _ _
ration programs can be and lOBs to nearby inter- capture systems. Entry gration can be achieved. cost, and rapid turn around.
loaded automatically at connect and long lines run through Boolean equations After the design has been The field programmable
power-up or upon com- the length of the part to or from a variety of state mapped, an automatic gate array, selected in a 25·
mand at any time. provide low skew paths for machine languages is also placement and routing pro· mil ceramic gull-wing sur·
The functions of the critical signals. supported. gram determines the opti· face-mount package, solved
LeA's configurable logic A knowledge of the archi- mal placement for the logic these problems. In addition,
and input/output blocks - tecture, although helpful, is Simulation blocks and routes the inter- the Xilinx LCA reconfig-
eLBs and lOBs, for short - not necessary for designing Once the design is connecting nets. A manual urable architecture allows
and their interconnections, with LCAs. Design imple. entered, unit delay simula· design editor can be used for future upgrades with no
are controlled by a program mentation software provid. tion can be performed to here to pre-reroute or hardware impact. ...
stored in an on-chip memo- ed with the system auto· verify the design's function· reroute critical signals to
ry. Each eLB contains com· matically translates a ality. Next, the design gets ensure that timing specifi.
binatorial logic and storage design into a working part, partitioned into CLBs and cations are met. When
registers. The logic section enabling the engineer to lOBs using a translation that's done, the part can be
of the block uses its inputs, work at a PC or worksta· program that lets the user simulated to show potential
outputs, or hi-directional tion. select the way the part is performance data and then
pins. Inputs can be pro- The first step in design. mapped: designs can be par· implemented in a system.
grammed to either TTL or ing with programmable titioned for performance -
CMOS thresholds. The pro- gate arrays is schematic so that only related logic is Solution
Reprinted with permission from
grammable interconnect entry. Interfaces and put together on a given cell Critical issues facing the MUirary and A61fJspac. Electron-
switches connect the libraries are available for - or for density - so that DSMAC II design team ics April 1990. a:a990 Sentry Pub-
inputs and outputs of eLBs the most popular schematic the maximum level of inte· included size, development lishingCo.,lnc.,Westborough,MA.
7-14
1': XiliNX
Pivoting Monitor
Increases Versatility
Of Workstations
7-15
Article Reprints
HORIZ~~
and (w-I)n become (n-I)w.
VERTICAL The rotation circuitry is part of
LINES PIXELS the interface board which contains the
memory to store the frame buffers
....•
(Video RAM} It also contains the con-
~
i _ 90" ROTATlON 11
FAST SCAN
trol circuitry to the interface with the
data bus (1st Translation Xilinx PGA),
~ - - - ri~~~c~7t~ ----.
....
• OIRECTlON the control circuitry to the interface
II
with the video circuitry which builds
~ HORIZONTAL
PIXELS up the video stream (2nd Translation
Xilinx PGA), and the digital to analog
converter which sends the signal to the
monitor (VDAC) (Fig 2} Part of the ro-
tation is performed when the pixels are
sent to memory, and the rotation is
completed when the pixels are sent to
the monitor. The final bit stream sent
to the monitor is at 50 MHz. The bit-
stream is split into two 25 MHz
Fig lin the Macintosh software graphics format the pixels are accessible along a horizontal line substreams in the Translation circuitry.
and are numbered from left to right. There are six modes of oper-
ation -I, 2 and 4 bits/pixels for the var-
However, the better solution would ics interface the pixels are accessible ious shades of gray in a portrait
be to rotate the entire display housing. along a horizontal line and are num- orientation and I, 2 and 4 bits/pixels in
The display electronics do not change bered from left to rillht 0, I, 2, 3, etc. a landscape orientation. The pixel ad-
from one orientation to another. The (Fig I} In the landscape mode the pix- dressing for each mode is different.
electron beam scans from left to right els are arranged in the same direction The interface board must contain the
in landscape orientation and bottom to as the beam scans. In the portrait circuitry required to translate each of
top in portrait orientation. The de- mode the pixels are also accessed the six modes. This circuitry, if imple-
flection circuitry and the picture tube along the horizontal lines and num- mented in a classical gate array, would
rotate as a single component causing bered from left to right 0, I, 2, 3- require around 6000 gates.
the picture geometry to remain the however, the fast scan direction is now The solution to high density and
same. This ensures the best possible changed to bottom to top. high speed requirements was a Field
picture quality in both orientations. Therefore, pixel addresses need to Programmable Gate Array (FPGA). The
The pixel data is stored in Video be renumbered in the portrait mode. logic for each of the six modes fits into
RAM on the display controller in the This renumbering corresponds to a 90° an 1800-gate device. The monitor oper-
computer. The display controller sends rotation of the pixel addresses. To be ates in one mode at a time and only
the data through the serial port in in- compatible with the Macintosh applica- 1800 gates of logic were needed for
creasing address from left to right for tions this rotation must be transparent each mode. The reprogrammability
the landscape mode. The desired effect to the software graphics interface and feature of the Xilinx Logic Cell Array
is to keep the serial port along the fast- performed in real time. In a 90° rota- (leA) allowed the monitor to operate
est scan direction, meaning left to right tion the top left and bottom right pixel in these six different modes while using
in the landscape mode and bottom to addresses (e.g. 0 and nw -I) are pre- only one logic device. The leA being a
top in the portrait mode. served while the rest of the pixel reprogrammable logic device, configu-
In the Macintosh software graph- addresses are rotated. In other words ration bitstream determin~s the
7-16
C~O~M~P~U~T~ER~T~E:C~H~N~O~LO~G~Y~R~EV~I~E~W~===============:;-_ _ _ _ _ _ _ _ _ _ Fall 1990
Software Development
--
BEFORE ROTATION
HOAIZONTALPIXELS
Once the monitor is rotated, the
software needs to tell the system that
~ =j
0 1 2 '-3 '-2 '-1 the shape of the desktop has changed.
•
3.
'+1
3H+1
'+2
3H+2
2H-3
3H-3
2H-2
3'-2
2H-1
3H-1 The desktop is the graphical metaphor
FAST SCAN DIRECTION used by Apple to represent the com-
puter display.. On the desktop there
(V-1)H I IV;~)H I (V;~)H I VH-3 VH-2 VH-1
are windows with applications, and
icons representing these applications
windows which are closed. Any appli-
AFTER ROTATION cation running on the desktop can
query the system as to the size of the
VERTICAL PIXELS new desktop.
SLOW DOWN SCAN DIRECTION In addition, a cleanup is per-
formed moving the icons on the
desktop to a location where they Can
be accessed. When the display is ro-
tated the shape of the desktop is
changed. The system icons in the com-
HORIZONlAL
mon area of rotation remain the same.
PIXELS However, the system icons in the re-
moved area must be relocated. In Fig 3
the system icon is illustrated with the
Macintosh Trashcan icon. For example,
if the monitor is in the portrait mode
and a system icon is located in the bot·
tom right of the desktop, it will be
Fig 2 The rotation circuitry is part of the interface board which contains memory to store the vid-
eo RAM. rqpved to the upper right hand of the
screen when the monitor is rotated to
functionality of the device. A position Earth's Magnetic Field
sensitive device (somewhat like a mer-
cury switch) is used to detect which When designing a monitor, the
direction the monitor is in, either por- earth's magnetic field has an influence
trait or landscape. An interrupt is sent on the quality of the picture. The de-
to the system software to tell it that the flection inside the picture tube is based
monitor is changing direction. The sys- on an AC magnetic field. On top of the
tem software determines which of the AC magnetic field is the earth's DC
six configuration bitstreams should be magnetic field. When the monitor is
loaded and then automatically loads it turned on its side the DC noise can
into the FPGA. The FPGA is repro- cause the picture to shift and tilt
grammed in one msec while the soft- slightly. The DC component is normally
ware is updated to the new mode. compensated for before the monitor
The LCA reduced the amount of leaves the factory. To alleviate this
gates which needed to be used. In ad- problem a silicon steel magnetic shield
dition the FPGA made the developing of is placed around the front face of the
the hardware much easier. Each of the picture tube. This shield also contains
six modes of operation could be devel- the deflection field inside the display,
oped separately eliminating fringe therefore minimizing radiation leakage.
effects from the clock loading from the As a consequence, interference from
other modes which allowed the circuit other displays will also be reduced.
to run at the required 25 MHz. In color monitors the probiems
caused by the earth's magnetic field are
more complicated because there are Fig 3 When the display is rotated, the system
more electron beams traveling with a icons in the common area of rotation remain'
higher energy. the same.
II
7-17
Article Reprints
~CO,:M~PU~T':ER':.T~E::C::H~N~O,,=lO~G~Y~R~E~V~IE~W:,=================;--=:=====-=-=-==
scrambled mess on the screen.
Fall 1990
(OxO) (0)(640) (OxO) (Ox 884) The goal is to work with the soft-
ware development community to take
advantage of the new orientation by au-
-
tomatically adjusting the window. This
means that when the display is rotated
FL1P the application detects the pivot,
moves and resizes the windows to take
advantage of the new screen size.
Utilizing hooks installed in the op-
(863x839) (863)(1219) (863)(1503) erating system, applications can query
the status of the display to detect a piv-
Fig 4 Global coordinates of the other displays may also need to be updated to maintain overlap- ot. For each of its windows, the
ping, nOA-contiguous characters. application can then request a hint, a
message returned to the application
the landscape position allowing it to nates of the other displays may also containing a location and size for the
be accessed. need to be updated to insure that the window which makes optimum use of
display maintains their contiguous, the new desktop shape.
Multiple Screen Support non-overlapping nature (Fig 4). However, a vast majority of the ap-
Another complication to the soft- The rotation of the left-hand dis- plications work with the pivot monitor
ware is that the Macintosh supports a play causes the local and global without any modifications. The hooks
multiple monitor display mode. This is coordinates to change from (top: 0, available from the operating system
where two or more monitors can be left: 0) and (bottom: 863, right: 639) to will allow these applications to have
placed side by side in order to provide (0,0) and (639,863). The right-hand additional functionalities.
a contiguous drawing area (Le. there display's global coordinates change Creating a pivot display monitor
are no gaps between the monitors al- from (0,640) and (863,1279) to (0,864) was made possible only through the
lowing the user to move the mouse and (863,1503). tight and seamless integration of the
freely between the displays). Each The window on the desktop's co- mechanical design, the hardware and
screen has its own local coordinate ordinates change from (100,800) and the software. The mechanics of the
system which is translated into global (700,1100) to (100,1024) and (700,1324) monitor make rotation a simple one-
coordinates for drawing. When the op- after the flip. hand operation. The reprogram-
erating system builds the desktop from mability feature of the Xilinx LCA
the available display, it assigns their Software Application Support allowed the monitor to operate in six
global coordinates such that the dis- When the monitor pivots, most ap- different modes using only one re-
plays do not overlap and the drawing plications will truncate the portion of programmable logic device. The
space is continuous. the window that no longer exists in the software made the desktop dynamic,
When the monitor is rotated, some new orientation. A small number of ap- allowing applications to take full ad-
desktop area is added and some is re- plications which bypass the systems vantage of the display space. •
moved. Not only do the local coor- software graphics interface, Quick- Reprinted with permission from the Publisher
dinate systems of the display change, Draw, and directly manipulate the from the Fa1l1990 Computer Technology
the assignment of the global coordi- display's video frame buffer, render a Review.
7-18
FJeOO'onic Engineering
By Tom Liehe, Principal Design Engineer, Test Instrument Division, Honeywell Inc., Denver, Colo.
Designers at Honeywell picked the RAM·based Xilinx Errors on tape typically are caused by tape defects, dirt,
LCA for Its short development cycle, and realized head clogs, etc. Because these error bursts can be
savings In board real estate through its dynamic thousands of bits long, sophisticated EGC techniques are
reprog rammabillty. required. Initially, two basic circuits, using Reed-Solomon
algorithms and TTL technology, were designed. These
Advances in one technology often lead to improvements in were the ECC encoder and decoder.
other, more dated design and manufacturing practices. A
recent example of this occurred at Honeywell during the The write portion of the circuitry (the encoder) uses a byte-
development of a high-capacity digital tape recorder. wide linear feed-back shift register (LFSR) to create a
68-byte code word form each 64-byte incoming message
Honeywell's original objective was to design the VLDS block. During operation, parity check bits are computed
(very large data storage) recorder, taking maximum ad- based on the data within a block of the message to be
vantage of the available analog technology currently being encoded. These check bits are appended to the block to
used in standard VCRs for home use. The recorder create the code word.
developed under this program uses digital rotary technol-
ogy to record large amounts of data on a standard VHS During decoding, the code words are checked for errors by
video cassette. It transfers data at a rate of 4 Mbauds, and regenerating the parity bits which are then compared with
is able to store 5.2 Gbauds of information on a single BHS the check bits. If they match, it is assumed that no errors
tape. Its major planned application is in capturing and have occurred. If they do not, the pattern of mis-matches
storing digital medical images, such as those produced by (called the syndrome of the error) is used to compute the
a CAT scanner. corrected form of the message block.
When this recorder was in the prototype stage, it became The ECG decoder (the read circuit) required a partial
apparent that the addition of an error-correction circuit syndrome generator and the solution of a set of simultane-
would significantly enhance system performance. This ous non-linear equations to determine error locations and
requirement dictated the design of an entirely new and values. This error-determination step is performed by a
major logic circuit to accomplish the desired error correc- special-purpose processor with a microinstruction se-
tion. quencer, a finite field arithmetic unit, two discrete registers
and an eight-word memory. The correction step is then
Design of this circuitry would not normally be a problem, accomplished in circuitry whereby the error values are
but at this stage of development, there were several exclusive-ORed with the message atthe address given by
challenges. First, the design allowed almost no circuit the previously computed error locations.
board space for addition olthe error correction code (ECC)
circuitry. Second, very tight deadlines were being faced if Using wrapped-wire techniques, a working prototype of
the promised delivery date was to be met. the ECG circuitry was developed. However, it was quickly
recognized that the long lead time required to design and
The entire system was housed in a 19-inch-wide by fabricate a factory-programmed gate array to replace this
20-inch-deep rack-mounted cabinet. The cabinet already prototype TTL circuit was not practical with the tight
contained eight separate circuit boards, and there was delivery schedule.
room enough for only one additional board to incorporate
the ECC circuitry. Space was at a premium. The goal was
to design and manufacture a 10-12 corrected bit error rate
An option considered, but not chosen, was to design and
fabricate a conventional gate array. The considerable
II
circuit that could be contained on one circuit card. The design time required, together with the inherent risks
targeted time for completion of this work was three aSSOCiated with masking and manufacturing a custom
months. logic circuit, made this an unattractive alternative.
7-19
Article Reprints
Finally, the search for an alternative solution led to the Another significant benefit derived from the use of the
discovery of a programmable gate array known as the Xilinx LCA was reduced power consumption. The original
logic cell array (LCA) , designed and manufactured by bipolar IC design consumed approximately 12 W of power.
Xilinx Inc. (San Jose, Calif.). The LCA is a standard, off- Through the use of CMOS technology, the replacement
the-shelf device that is custom configured to the LCA consumes only 50 mW of power. It should be pointed
customer's requirements by means of the Xilinx develop- out that the bipolar version was capable of operating at
ment system. This development package consists of a a much higher clock rate than the LCA. However, the clock
personal-computer-based software system combined rate used this particular design was only.2 MHz. The
with an in-circuit emulator. speed of the LCA was, therefore, adequate for the VLDS
application.
Use of the LCA seemed to be the ideal solution to the time
constraints. So, a Xilinx XC2064 LCA was sected. In this Because the required logic circuitry was already designed
device, any logic function having up to four variables can and tested, the development of the configuration program
be implemented in anyone of the 64 configurable logic for the LCA went very smoothly. It took only two days to
blocks (CLBs). Optionally, results can be stored in either configure the circuit using the Xilinx XACT LCA develop-
a latch or a flip-flop. Thus, implementation of the design ment system running on a standard, IBM-compatible per-
can be constrained by a fixed set of standard logic ele- sonal computer. The primary effort involved was the
ments. partitioning olthe logic to match the capabilities olthe LCA.
The 1/0 pins of this device also can be configured as For a regular, repetitive design, a small portion of the logic
registered inputs. The large number of flip-flops, plus the was defined. This portion was then copied and minor
ability of each CLB to function as four-input exclusive- modifications were made to complete the design. The
ORs, made this LCA ideal for ECC circuit implementation. byte-oriented nature of the RS ECC circuitry lent itself to
easy entry. Starting with tables showing the bits to be
exclusive-ORed, the entire circuit was entered in a few
MULTIFUNCTION CAPABILITY hours.
One of the real benefits of this LCA is its multifunction The software simulation capability, which enabled the
capability. The capability of performing a number of modeling of physical delays and logic functions, resulted
functions with the same device provides optimum utiliza- in a very high design confidence factor before the first
tion of circuit board space. This was a real bonus with the hardware checkout. The simulator provided both tabular
VLDS recorder. At any given time, the VLDS operates in output and logic analyzer style waveforms, which aided
only the read or the write mode-it is never required to do considerably in the visualization of the circuit perform-
both simultaneously. Consequently, the same LCA could ance. A high-level language program was used to gen-
be reconfigured electronically to perform one function in erate expected results of the encoder, and to perform
the write mode, and a completely different function in the partial syndrome generator simulations. This greatly
read mode. This versatility eliminated the need for two aided the evaluation of the simulation output.
separate circuits, and thereby conserved space.
By using the in-system emulation feature, configurations
The LCA has a usable density of 1,000- to 1,500-gate were loaded directly from the PC to an LCA mounted in
equivalents, and is capable of replacing up to 75 SSI/MSI the target system. Thus, the usual step of programming
devices, five to 15 PAL-type devices, or some combination an EPROM from which the LCA can boot itself was elimi-
of both. In the VLDS, the entire ECC encoder and the nated. Initial design checkout of the ECC circuitry was
partial syndrome generator portion of the ECC decoder performed using the emulator connected to the wrapped-
were replaced by the LCA. The initial encoder circuit used wire board containing the discrete IC version.
eight identical PALs, each of which implemented a 1-bit
slice of the shift register, and four PROMs. The original There was a problem with the encoder circuit that was
partial syndrome generator design used six PALs and four delaying data for an extra byte. Correcting this problem
74LS374 tri-state octal flip-flops to store the four syn- required removing the input flip-flops on the LCA. The
dromes. Thus, the LCA replaced a total of 14 PALs, four entire process of reentering the LCA editor, removing the
256k x 8 PROMs and four 74LS374s, or a total of 22 mouse and reloading the new configuration took no more
20-pin DIPs. than five minutes.
7-20
Compared with the time required to rework any other type using equivalent discrete ICs. And finally, the ability to
of hardware, the LCA is the only way to go. Also, taking into perform design entry, simulation, emulation and in-system
consideration the high costs associated with reworking a testing through the software development system facili-
factory-programmed gate array, or even a semi-custom tated quick and easy implementation of the user's ideas.
PLD, the LCA technology is an extremely cost-effective
alternative. Today, the Honeywell VLDS offer error correction as
powerful as most major computer tape subsystems. It is
In summary, the Xilinx part was well suited for our applica- ideally suited for the newly developing imaging technolo-
tion because of its high flip-flop count and its ability to be gies used in electronic office documents, advanced geo-
configured in exclusive-OR trees. Additionally, its capabil- physical analysis and computer-aided graphic arts. With-
ityof being electronically reconfigured while in the system out the Xilinx logic cell array however, Honeywell could still
(when switching from write to read) offered significant be waiting for a custom gate array.
savings.
Reprinted with permission from Electronic Engineering
Further, power consumption was much lower than when Times.
II
7-21
ESD:
THE ElectroniC System Design Magazine
LeA Stars in Video
Reprinted with permission from ESD: The Electrical Sys- mines how to increment the counter. All of these functions,
tem Design Magazine. plus logic to generate the read/modifylwrite cycle timing,
are implemented in a single LCA that replaces nine MSI
The market for tools and overlay products for video pic- parts, four of which are PLDs.
tures generated from laser disks is in its infancy. Appli-
cations for this emerging video-based technology can re- Two more LCAs implement a three-bit ALU. This tech-
quire high resolution and high performance, and the wide nique achieves ultra-high-speed screen writes for both
variety of video disk players employed means that prob- horizontal and vertical lines. For many applications, these
lems associated with varied noise characteristics must be are the most common lines drawn, so a special control bit
overcome. What works with one particular brand and is used to simultaneously modify pixels. Horizontal lines
model in the factory may falter with another brand in the can be written at 14 Mpixels/sec instead of the normal
field. 2 Mpixels/sec-a seven-fold improvement. Though more
logic could be placed in these two devices, a bit-sliced logic
The Xilinx Logic Cell Array (LCA) helps to solve the approach permits continuous enhancements. Moreover,
problem of meeting different system requirements be- a board layout can be defined at the beginning of the
cause the device elevates hardware to the same level of product cycle while logic enhancements are made inter-
programmability as software. Before the LCA, once a nally in the LCA. Nearly 30 SSIIMSI devices were inte-
design had been committed to hardware, revisions to the grated into the LCAs.
design could only be implemented via software changes.
A fourth LCA fully implements the graphics engine. To
Interactive Educational Video (lEV) has implemented read out data to the screen, scan counters point to mem-
three separate designs and logic replacements with the ory. A shift register serializes at a rate of 14 Mpixels/sec.
LCA. These functions reside on IBM PC expansion cards, Using traditional MSI devices, these functions require
where space limitations would ordinarily preclude such a about 10 chips.
design. Although application-specific video ICs could
perform similar functions, they cost more than the LCA and The second design fabricated by lEV is a graphics con-
offer lower performance. troller (Figure 6). Using an external genlock IC, the LCA
relies on an NTSC composite sync signal to generate
The first application is a graphics engine that uses four timing signals forthe CRT display. Instead of using PLDs,
LCAs. Here, the LCAs replace over 50 SSI/MSI chips, lEV uses the LCA to implement digital counter and timers.
including four traditional programmable logic devices The result is higher performance and reduced complexity.
(PLDs). The previous generation board has only half the function-
ality and demands four times the board space. To further
One LCA functions as the address generatorforthe video reduce complexity, the same hardware can be used with
memory. By relying on a pair of high-speed counters to a different configuration program to match a particular
locate horizontal and vertical coordinates, memory write video disk player's noise characteristics. Without the LCA,
functions (which implement line drawing) can perform at this design needs eight PALs plus 12 to 15 MSI devices.
high rates. Given the slope, starting point and length of
a line, the logic simply increments counters that point to In another I EV design, a PC serial port emulator integrates
video memory locations. Scanning and writing to the a subset of the IBM PC serial port functions onto the
screen are interleaved. The data written to memory graphics card, making an IBM serial card unnecessary.
corresponds to a particular color and, by simple incre- With the given space restrictions, this implementation
mental additions to the slope of the address pOinter count- proves particularly cost-effective. Seven PLDs are re-
ers, powerful line drawing functions are easily imple- quired to match this design.
mented.
Reprinted with permission from ESD: The Electronic Sys-
Important to the design is the decision logic, which deter- tem Design Magazine.
7-22
XC2064 LOGIC CELL ARRAY
GRAPHICS
ADDRESS
AND --7-.-1 OVERLAY
CONTROL VIDEO
DOT
CLOCK
COMPOSITE
SYNC TV
INPUT CAMERA
EXTERNAL SYNC
COMP~~I~~ ---=------.-----.-1 GENERATOR
INPUT
VD HD
14.318 MHZ
INPUT
1---7-_BFW
1 - - - - - - . ; . -.... GVB
DATA
BUS 1---;-_ GHB
1148 13
II
Figure 6. lEV implementated an itelligent Graphics Overlay Controller microprocessor peripheral with one XC2064 Logic Cell
Array, replacing eight PALs and 12 MSI devices. The controller generates all timing for a video graphics overlay by deriving the
necessary timing from the underlying video disk signal.
7-23
Taking Advantage of
Reconfigurable Logic
An abbreviated version of this paper was published in the High
by Bradly K. Fawcett, Xilinx Inc., San Jose, CA Performance Systems Programmable Logic Guide, 1989.
The availability of programmable logic devices based on suit is smaller, more powerful, less expensive, and more
static memory cells now allows the implementation of reliable systems. As an added benefit, use of reconfig-
"soft" hardware-hardware whose functions can be urable LCAs simplifies hardware design and shortens a
changed while resident in the system. When using most product's time-to-market.
current IC component technologies, hardware is indeed
"hard"; once a given logic function is implemented in
hardware, changing that logic is difficult, requiring modifi- RECONFIGURING FOR SYSTEM DIAGNOSTICS
cations to printed circuit board traces, the addition or
replacement of components, and other costly measures. System self-diagnostics can be implemented by using
However, with static-memory-based programmable logic, programmable gate array configurations dedicated to test-
changes can be made to a system's logic functions simply ing functions. When the system is powered-up or placed in
by reconfiguring the programmable logic in the system. a test mode, its programmable gate arrays are configured
This capability can lead to significant advantages for the with logiC functions dedicated to testing other circuitry in
system designer. These include both product-related ben- the system. Once the testing is successfully completed,
efits, in the form of smaller, less expensive, and more another configuration program is loaded into the program-
reliable systems, and design-related benefits, such as mable gate array to implement the actual logic of the
increased design flexibility, decreased risk, and faster particular end application intended for that system. Typi-
design cycles. cally, very little additional logic is required to. add self-
diagnostic functions in this manner (usually Just some
Programmable logic devices capable of being reconfig- additional memory to hold the extra configuration pro-
ured in the system are available to system designers in the grams). Such self-diagnostic capabilities make products
form of programmable gate arrays from Xilinx, Inc. The easier to manufacture, increase system reliability, and
Xilinx Logic Cell Array (LCA) architecture features three simplify system maintenance, with little, if any, additional
types of user-configurable elements: an interior array of cost.
logic blocks, a perimeter of 1/0 blocks, and programmable
interconnection resources. Configuration is established Designers at Tellabs Inc. (Lisle, IL) used this strategy in a
by programming internal static memory cells that deter- voice compression module, an optional unit for the
mine the logic functions and interconnections. The coh- Crossnet 440 T1 multiplexer. The design includes two
figuration programs can be loaded automatically at power- XC2018 devices, 1800-gate programmable gate arrays
up or upon command at any time. Several available (Figure 1). During normal operation, one LCA provides all
configuration loading modes accommodate various sys- the interface logic for the board's microcontroller, RAM,
tem requirements. The benefits of a static-memory-based and system backplane, arbitrating accesses to the RAM
device include high density, high performance, testability, from the controller and the main system. The second LCA
and the flexibility inherent to a device that can be pro- contains most of the "glue logic" for the data compression
grammed while resident in a system. Designers have operation. However, both LCAs can be loaded with special
taken advantage of this capability in a wide range of diagnostic configurations. In the test mode, the first LCA
applications. connects the microcontroller to the RAM for memory
testing, and monitors controls on the system backplane.
The flexibility inherent in reconfigurable Logic Cell Arrays The second LCA can receive timing information from the
(LCAs) can be used to create systems that are also more microcontroller instead of the system backplane, verify the
flexible and, therefore, more powerful. Often systems will data paths, and check the contents of the 32K-bit EPROM
include multiple configuration programs for their LCAs, used to implement the code converter's companding algo-
allowing varying operations to be efficiently performed rithm. Actually, two different test configurations have been
with a minimal amount of hardware. For example, recon- generated, and other diagnostic LCA configurations are
figurable logic can be used to implement system self- planned for a future upgrade. All the configurations are
diagnostics, create systems capable of being reconfigured present in memory on the board; the microcontroller
for different environments or operations, or implement handles the downloading of LCA configuration programs.
"dual-purpose" hardware for a given application. The re-
7-24
ADAPTABLE SYSTEM DESIGNS system with logic that selects the appropriate configura-
tion at the appropriate time. Many different types of appli-
A similar use of reconfigurable logic is the implementation cations benefit from this approach.
of a single hardware design that can be adapted for varying
tasks or environments. In such systems, any of a number The Freeland Medical DiviSion of Good Technologies Inc.
of potential configuration programs can be downloaded (Indianapolis, IN) used reconfigurable LCAs in this man-
into a system's LCAs to alter the logic for particular ner when designing a "frame grabber" board for the Cine'
applications or operations as needed. Hence, more func- View family of digital imaging systems. A mix of seven
tions are implemented with fewer components, hardware XC2064, XC2018, and XC3020 LCAs are used on this
design costs can be amortized over a greater number of AT-format board, providing graphics control and interfac-
systems, and design cycle times are greatly reduced. The ing a PC-compatible computer to the video output of
manufacturer could select the configuration program to be medical eqUipment such as ultrasound scanners and
included in the system dependent on the intended end magnetic resonance imaging systems. In order to support
application or customer, or, alternatively, all the different different video formats from the varying types of medical
LCA configuration programs could be included in the instruments, several different LCAconfiguration programs
MICROCONTROLLER
"-
ti ADDRESS + CONTROL
XC2018 256 x 4
v
" DATA
LCA "- RAM
CHANNEL
1953 01 SIGNALING
An LeA contains interface logic for the micro-controller, memory, and system backplane.
MICROCONTROLLER
rt
XC2018 LCA
TIMING NIBBLEI
A
TIMESLOT
AND '" TIMESLOT
INTERCHANGE
CONVERSION
CONTROL
" LOGIC
f1 1
1953 02
I'LAW
DATA CODE
CONVERTER
ROM
LINEAR DATA
A second LeA implements the glue logic for the data compression circuit.
DSP
•
Figure 1. LeAs in a voice compression system can be reconfigured to implement internal system diagnostics.
7-25
Taking Advantage of Reconfigurable Logic
are available for the LCA devices in the system. When logic consists of an 8051 microcontroller and a 3000-gate
system operation begins, the user selects the desired XC3030 LCA; four channels are implemented on each
video format (monochrome or RGB color, for example); card. Using a keyboard, the user can select from among
the appropriate LCA configuration program is then loaded three communication protocols for each channel: a Data
to match that format. Thus, one hardware design can Service Unit (DSU) interface, an Office Channel Unit
support virtually any video format, without having to in- (OCU) interface, or a secondary-mode OCU interface
clude customized hardware for each one. (Figure 2). A fifth 8051 processor controls the user inter-
face and the downloading of the appropriate LCA configu-
A similar scheme was used on Tellabs' channel interface ration programs.
cards for the Cross net 440 T1 muHiplexer. Each channel's
1953 03
~
PARALLEL-TO- BIPOLAR
VIOLATION
RETURN-TO-
ZERO
r----- DATA +
SERIAL SIR
GENERATOR GENERATOR r----- DATA -
I+---DATA+
i4-- SERIAL-TO- TRANSPARENT DATA AND 3-BIT
I-- CONTROL CODE TRANSLATER I-- FIFO !---DATA-
PARALLEL SIR
I+----CLOCK
1953 04
OCU mode block diagram
--., PARALLEL-TO·
SERIAL SIR
RETURN·TO·
ZERO
GENERATOR
f-
f- =: DATA +
DATA-
T I
8051
PROCESSOR
I
FRAME BIT
GENERATOR
I XC3030 LCA
I
~
FRAME SYNC
RECOVERY
- SERIAL·TO·
PARALLEL SIR
3·BIT
FIFO ~ --
~
- DATA +
DATA-
CLOCK
7-26
Reconfigurable logic can be used to adapt add-in circuit Several other applications involving the use of Xilinx LCAs
boards to the environment of a particular computer. In to implement adaptable hardware have been described in
such systems, configuration programs can be down- recent articles:
loaded by the host processor (from a floppy disk or
modem, for example), allowing simple installation proce- • Tektronix Inc. (Wilsonville, OR) employed an XC2018
dures and easy field upgrades. Several recently an- LCA for the printer interface logic in their Phaser Card
nounced personal computer products illustrate this capa- printer controller.l Interfaces to several different types
bility. Buffalo Product's (Salem, OR) More Memory mem- of printers can be implemented through reconfiguration
ory expansion card for PC/XT or PC/AT compatible sys- of the LCA.
tems employs a 1200-gate XC2064 LCA for the bus and
memory interface and control logic. An installation pro- • The FASTPACKET data multiplexer from Stratacom
gram analyzes system parameters (bus width, type of card Inc. (Campbell, CAl uses LCAs to incorporate its four
slot, available address spaces, etc.) and then loads the serial channel interfaces.2 Different communication
appropriate configuration program to match the system's protocols can be accommodated through reconfigura-
requirements. Similarly, the Mach II/SE (Figure 3), an tion of the LCAs. A special configuration of the LCAs
accelerator board for the Macintosh II from Dove Comput- also provides for bit error rate testing without the use of
ers (Wilmington, NC), uses an XC2018 LCA for all its external test equipment.
interface logic; different LCA configurations are used to
support different memory sizes and speeds. The • Reconfiguring an LCA in a graphics controller for a
MultiScreen card from Mobius Technologies Inc. (Oak- laser disk system from Interactive Educational Video
land, CAl, a monitor interface board, includes an XC2018 (Salt Lake City, UT) allowed a single hardware design
LCA for controlling the video output. Different LCA configu- to be matched with various video disk players' noise
rations support different monitor types, allowing for varia- characteristics. 3
tions in timing requirements and screen resolution. As new
monitors are introduced in the market, additional LCA • GTECH Corp. (Providence, RI) designed a lottery bet-
configuration programs will be developed and distributed slip reader using LCA technology that can be reconfig-
on floppy disks. ured to accommodate variations in bet-slip size and
format without hardware alterations. 4
II
Figure 3. The Dove Computer Mach IIISE includes a micro-processor, floating-point co-processor, memory, bus drivers, and an
LCA that holds all the interface logic.
7-27
Taking Advantage of Reconfigurable Logic
CONFIGURABLE TEST EQUIPMENT the test patterns and the pins of the memory device being
tested. Different LCA configurations are used for testing
In a similar manner, programmable gate arrays often are different types of memory devices. An extended vector
used to implement configurable test equipment, wherein memory option uses an XC2018 LCA as a FIFO buffer
different LCAconfigurations are used to program the same between the extended memory and the pattern control
hardware to perform varying types of tests. logic. Upon command, this LCA can be reconfigured to
create a cyclic redundancy code (CRC) checker used to
Innovage Microsystems (Calgary, Alberta) chose pro- verify the test patterns stored in the extended memory.
grammable gate arrays for test circuitry used in the Fluke
90 Series (John Fluke Mfg. Co., Everett, WA) and Inno- Designers of telecommunications test equipment have
vage Microsystems' own Tracer-4 series of microproces- also discovered the advantages of reconfigurable logic.
sor board testers. These portable test instruments facili- Three LCAs are used in the PC-based TC2000-B1
tate the trouble-shooting of microprocessor-based T1/PCM tester from LP Com, a Tektronix subsidiary
boards; testers are available for a number of popular (Mountain View, CAl. The LCAs provide clock and timing
microprocessor types (Z80, 8086, etc.). As shown in generationforthe receiverltransmitter, interface logic, and
Figure 4, an LCA provides interface and control logic bit error generation logic. The logic can be altered by
between a resident microcontroller and the unit-under-test downloading different LCA configuration programs to
interface card. An 1800-gate XC2018 LCA is used in the support several user-selected operating modes. When
8-bit series, and a 2000-gate XC3020 is used in the analyzing DS1 lines, any standard framing mode can be
16/32-bit series of testers. Different configuration pro- selected (D1 D, D2, D3/4, or ESF). In DS1 bit error testing
grams are stored in the system's ROM during production, (BERT) mode, any AT&T standard or user-defined test bit
dependent on the type of microprocessor targeted for that pattern can be specified. The use of reconfigurable LCAs
tester, allowing the same basic hardware configuration for allowed the logic to be packed into just two boards; LP
all tester types. A keypad allows the user to choose from Com engineers estimate that the design would be at least
a variety of pre-programmed trouble-shooting modes; the twice as complex with traditional logic devices.
microcontroller downloads one of seven different available
configuration programs to the LCA, dependent on the type Sage Instruments (Freedom, CAl used a similar strategy
of test selected. Use of the LCA allowed Innovage in their Model 930A Communication Test Set, a general
Microsystems to increase the functionality of their testers purpose channel access test system. Four LCAs are used
while reducing the number of components by 49%, as to implement data interface, channel signalling, diagnos-
compared to previous models. tic, and microprocessor interface functions, respectively.
The LCA that handles channel signalling has two possible
Semiconductor Test Solutions (Santa Clara, CAl included configurations to support two different signaling formats,
reconfigurable logic in several optional units for their STS RBS (robbed-bit signalling) and DMI (digital multiplex
6000 and 8000 series of Sentry-compatible IC testers. For interface). The data interface and channel signalling LCAs
example, an optional memory test unit uses the XC2018 are both reconfigured to support bit error rate testing.
LCA to interface between the internal memory that holds
XC2018 UNIT·UNDER·
" r'-'
~ ~
A
SYSTEM 01'1 TEST
PROCESSOR XC3020 INTERFACE
LCA CARD " TEST CLIP v
.t. ?-
'---
UNIT UNDER TEST
,I
j\
(ROM)
II I I
CONFIGURATION CONFIGURATION CONFIGURATION
FILE #1 FILE #2 ••• FILE #7
Figure 4. In Innovage Microsystem's microprocessor board tester, an LeA is configured for the appropriate
microprocessor type and selected diagnostic test.
7-28
E:X!lINX.
By reconfiguring a 3000-gate XC3030 LCA, an error- when writing data to the tape, and then reprogrammed to
correction channel designed by Wiltron Co. (Morgan Hill, perform a different function when reading from the tape.
CAl can support either of two error checking and correc- Honeywell's Test Instruments Division (Denver, CO) in-
tion (ECC) formats, one for Digital Data System (DDS) and corporated this scheme in their VLDS (Very Large Data
one for Adaptive Data Port (ADP) network configurations. Storage) recorder.5 An XC2064 LCA is configured to per-
The circuit is incorporated into several products, including form error code generation in write mode, and then
Wiltron's Model 9966 Digital Services Test Unit for testing reconfigured to perform error code checking and correc-
DDS-like services. Use ofthe LCA also provides insurance tion in read mode. This type of application is especially
against evolving standards; new LCA configuration pro- cost-effective; about twice the logic would be required to
grams can be developed if standards for ECC formats and implement the same functions with traditional logic de-
network configurations change. vices.
ADDRESS '"
y
DATA
... DATA
TRIGGER
MEMORY '"
y
TRACE
MEMORY
INPUT ADDRESS
SYSTEM AND GENERATION
CAPTURE BREAKPOINT
UNDER LOGIC + CONTROL",
TEST LOGIC CONTROL
... CONTROL
y
CONTROL ...
CONTROLLER
y
PGA
'"
ACQUISITION MODE
ADDRESS '"
DATA
'"
y
... DATA
TRACE
MEMORY MEMORY
SYSTEM
UNDER
TEST
CONTROL
USER
INTERFACE
CONTROL
PGA
ADDRESS
GENERATION
+
CONTROL
'"
CONTROL '" II
...
'" A
CONTROL J>.
CONTROLLER
...
195307
ANALYSIS MODE
Figure 5. An LeA can be reconfigured to support both acquisition mode and analysis mode operations in a logic analyzer.
7-29
Taking Advantage of Reconflgurable Logic
ured to control reading trace memory and displaying its RECONFIGURABLE LOGIC EASES DESIGN
contents when in the analysis mode (Figure 5). For ex-
ample, Data I/O's MESA-1, an in-circuit verifier for LCA While not every system requires reconfigurable logiC to
designs, uses LCAs exclusively to implement its logic implement its digital functions, the design-related benefits
(Figure 6). of static-memory-based programmable logic apply to all
designs. The ability to reconfigure programmable gate
Intel's Development Tools Operation (Hillsboro, OR) used arrays resident in the target system significantly eases the
a slightly different tactic when designing a series of in- debugging process, reducing overall development time
circuit emulators for derivatives of the 80386 processor. and shortening the product's time-to-market. A download
The emulators contain six LCAs. Four of them comprise cable provided with the basic development system allows
the bus event recognition circuitry used to define and configuration programs to be downloaded directly from a
detect triggers and breakpoints; three of these are largely PC to an LCA device resident in the target system; the
filled with comparators, and the fourth holds the breakpoint actual download operation requires less than 100 millisec-
state machine. When preparing for an emulation, these onds. Thus, the designer can immediately check the
four LCAs can be reconfigured in the system, dependent results of design changes in the target system. Often,
on the type of breakpoints and triggers being specified. A design changes can be implemented and tested in just a
DMA channel is used to download the LCA configuration few minutes time.
programs. A fifth LCA holds the bus interface state ma-
chines; as a future product upgrade, Intel designers may In essence, Xilinx programmable gate arrays provide a
generate another optional configuration program for that flexible means of "breadboarding" logic designs, as well as
LCA to add additional tracing capabilities. a cost-effective means of implementing the logic in the
final product. Temporary modifications to the logic, such
as routing an internal node to an otherwise unused I/O pad,
THE ULTIMATE RECONFIGURABLE SYSTEM can be quickly implemented for debugging purposes and
then removed from the production design. Devices are
A system composed entirely of programmable gate arrays reusable simply by downloading a new configuration.
could be configured to implement any given logic func- There is no lengthy wait for a custom device to be manu-
tions. This concept has been incorporated into a new ASIC factured, and no waste of components as with one-time-
design tool that provides real-time in-circuit emulation of
complex ASIC designs. The RPM Emulation System, from
Quickturn Systems Inc. (Mountain View, CAl, is a worksta-
tion-based design verification tool that combines auto-
matic ASIC nellist conversion software with emulation
hardware based on 9000-gate XC3090 LCAs (See
Figure 6). The RPM Emulation System can be configured
with up to four emulation modules with over thirty XC3090
LCAs each, allowing emulation of ASIC designs of up to
100,000 gates. Once the ASIC design is converted for
emulation, existing complex VLSI devices may be
internally connected to the emulation logic with
Component Adapter boards, orthe design may be plugged
into a target system with an In-Circuit Interface consisting
of cables, an active Pod, and ASIC Plug Adapters. The
nellist conversion software reads the nellist (a variety of
popular formats and libraries are supported), partitions the
design for programming each XC3090 LCA, places and
routes the design into the matrix of XC3090 LCAs, and
checks the timing to determine the maximum speed of
correct functional operation. The Control Panel user
interface on the workstation guides the deSigner through
the emulation set-up and provides the controls for the
integral Logic Analyzer and Stimulus Generator, allowing
quick access to any node in the design during debugging.
Thus, using the RPM Emulation System, a designer can Figure 6. The internal logic of Data I/O's MESA-! in-circuit
emulate and debug the logic operation of any large digital debugger is implemented entirely in Xilinx programmable
design before committing to a custom implementation. gate arrays.
7-30
programmable solutions; there is not even the inconven- Buffalo Products' design of the More Memory board men-
ience of long erase times using ultraviolet lights, as with tioned above. During testing of the board using various
EPROM-based logic. The designer receives nearly instan- manufacturers' PC clones, problems caused by incom-
taneous feedback on the effects of design modifications. patibilities in some PC models were corrected as they
Furthermore, since the LCA's configuration can be verified were found through reconfiguration of the LCA device.
in the target system, extensive simulation is not required;
typically, simulation is used only for critical timing path
analysis under worst-case conditions. FIELD UPGRADES SIMPLIFIED
The ability to implement easily modifications to the logic Similarly, field upgrades can be easily implemented
enables and encourages experimentation during the de- through changes to LCA configuration programs.
sign cycle, resulting in better designs. For example, the Andromeda Systems (Canoga Park, CAl took foil
use of Xilinx LCAs allowed GTECH Corp. to evaluate advantage of this capability in their Storage Module Device
different image sensors during the design of a bet-slip Controller, a disk controller for LSI-11 and MicroNAX
readerforthe lottery industry" Since there are no standard systems. s The configuration programs for three XC2064
architectures or interfaces for image sensors, different devices are stored in EEPROM that can be altered using
interface logic was required for each sensor type. By a service port that connects directly to terminals or
incorporating the sensor interface logic in LCAs, a single modems. The interfaces to the disk, processor bus,
hardware implementation could be reconfigured for each service port, and cache memory are implemented in the
sensortype, allowing the sensitivity and resolution of each LCAs (Figure 7). Modifications to the logic, such as
to be measured under identical conditions. adjusting the caching algorithm to match the requirements
of a particular application, can be made without removing
The flexibility of in-circuit reconfiguration greatly reduces the disk controllerfrom the system; new LCA configuration
design risks. The inevitable last-minute bug fixes and programs can be sent to the controller using a modem.
specification changes can be implemented by changing
an LCA's configuration program rather than altering the In many cases, compatible programmable gate arrays
hardware. MIA-Com Telecommunications (Germantown, with a range of densities are available in identical pack-
MD), for example, was able to correct an error in the PCB ages. (For example, the 2000-gate XC3020, 3000-gate
layout without changing the board by reconfiguring an LCA XC3030, and 4200-gate XC3042 are all available in 84-pin
used to implement the channel interface logic within a PLCC and PGA packages.) So if logic needs exceed the
satellite earthstation. 7 This flexibility proved critical during current LCA device, during either initial design or a product
PERIPHERAL
CACHE MEMORY EXPANSION
1M BYTE DRAM PORT
DISK
CACHE CONTROLLER
ADDRESS
MAPPER
Q·BUS
INTERFACE SMD
INTERFACE
USER
III
SERVICE
PORT
STATIC EEPROM
RAM
1953 08
7-31
Taking Advantage of Reconflgurable Logic
Figure 8. The reconfigurability of LeAs allows for the design 9. John Novellino, "Development Tool Trouble-Shoots
of their own in-circuit verification tools, such as the MESA-1 PGAs in the Target System," Electronic Design, Jan. 26,
from Data VO. 1989.
7-32
Faster Turnaround
for a T1 Interface
THE ElectronIC System Design MagaZlne
Important design considerations for an interface system to design requirements-high integration, high density, high
a digital T1 network (which carries voice, data, video and performance, low cost, low risk and quick time-to-market.
fax traffic at rates up to 56 Kbytes/sec) include conserving
board space, improving throughput and reducing power The Xilinx devices implement a digital phase-locked loop,
consumption. The user interface is achieved via a conven- as well as the T1 transmitter and receiver. A Hitachi
tional four-wire loop providing independent transmit and microprocessor provides overall intelligence to handle T1
receive capabilities. In designs that Teletrend Inc. initially controls, network code manipulation and other tasks.
considered for a single-user T1 interface, 5000 gates of
conventional SSI/MSI glue logic were to be integrated The dual digital phase-lock loop provides the key function
using two custom gate arrays. However, a short develop- of the system. Data on the user interface is encoded with
ment cycle and low market risks were also desired. This the clock Signals, a process that may occur at various
led to a search for an alternative to th time-consuming send/receive data rates. Data extraction from the user
process of casting two gate arrays. interface must be phase-locked and, at the same time,
data must by synchronized with the T1 network clock. A
Upon completing the initial circuit design, a breadboard Xilinx LCA implements the phase-locked loop that syn-
was built using CMOS SSI/MSI logic components. After chronizes both the interface and the T1 network.
the breadboard was working, integration path decisions
were needed. Instead of hard-tooling two custom gate The second LCA transmits data onto the T1 network.
arrays, designers determined that three standard, pro- Here, data transmits serially at 1.544 Mbits/sec in one of
grammable Xilinx Logic Cell Arrays (LCAs) met all of the the 24 assigned time slots. A unique data word to be
RECEIVE
DATA
AT 1.544
CONTROL
MICRO-
f---
T1 RECEIVER
WITH8·BIT
CRCERROR
CORRECTION
MBITs/SEC
I
I
II
PROCESSOR L ___ _
T1 SWITCH
WITH ONE
1148 12
ASSIGNED
TIME SLOT
Figure 7. Teltrend's digital TI interface is built around three user-programmable Xilinx Logic Cell Arrays in lieu of two conventional
gate arrays. One LCA implements a dual digital phase-lock loop around four-wire loop; other LCAs form both the transmitter and
reciever logic circuits, including error correction.
7-33
Article Reprints
transmitted is held in the LCA while logic synchronization higher performance in critical timing paths and higher
determines the start of the first time slot or the beginning overall device utilization. In all three designs, LCA logic
of the data frame. The assigned time slot is found by resource utilization exceeded 95%.
counting time slots from the start of a complete frame.
After locating the assigned time slot, data is transmitted All three designs are flip-flop intensive, involving multiple
onto the T1 network. counters, shifters, registers and other memory-oriented
functions. The LCAs provide more flip-flops per device
A third LCA, complementary to the transmitter function, than any other programmable logic alternative. Only a few
receives data. It also furnishes complete error correction simple 8-bit registers were implemented externally with
for incoming data. Time-slot detection logic determines octal devices. Next-generation deSigns will use Xilinx's
the start of data for the assigned channel. Serial data compatible higher density devices to achieve greater logic
comes from the T1 network. After the LCA performs 8-bit density in the same socket.
error correction, the data passes to the processor and user
Overall, the ability to enter the original design using the
interface.
Xilinx LCA XACT design· system ensured that all the
The first iteration of the design was extracted directly form integrated logic functioned as desired before the part was
the CMOS breadboard schematics using the Xilinx XACT placed in the system. With a conventional gate array, the
system running on an IBM PCIAT. The working design for design might still be waiting for silicon, since turnaround
the first device was completed in two weeks, with some times for production quantity gate arrays typically range
time-critical elements moved off the Chip. Designs for the from 8 to 16 weeks (production quantities).
second and third parts took about the same time, but Reprinted with permission from ESD: The Electronic Sys-
additional interaction during the design process resulted in tem Design Magazine.
7-34
Using Programmable Logic
Cell Arrays In a Satellite
Earthstation
Dave Farrow, MIA-Com Telecommunications, Germantown, MD
Conventional programmable logic devices (PLDs) include 3 Mbls transmission rate. The earthstation product, called
several interesting variations of latch-based AND-OR an OPT (for On-Premises Terminal) is a "small-aperture"
plane architectures in various technologies, all of which satellite earthstation, permitting efficient employment in a
are useful for low-gate-density applications. Typically, a large number of remote locations, as illustrated in
PLD can replace five to ten SSI/MSI parts. Figure 1.
A newer digital logic technology with an array architecture Two main components comprise the OPT: an indoor unit
and flexible interconnection offers the programming flexi- and an outdoor unit. The outdoor unit includes the antenna
bility of PLDs plus the gate density of low-end gate arrays. and associated radio-frequency equipment.
Architecturally, these devices have some similarities to
gate arrays: they contain an internal matrix of logic blocks At the outset of the design process, the indoor unit was
and a ring of configurable 1/0 interface blocks. Unlike intended to be contained in a small chassis that could
conventional gate arrays, each part is a standard off-the- support three standard-size boards. The boards originally
shelf unit that can be programmed by the user. The planned for the system included one board each for
configuration program is automatically loaded into an on- controlling data traffiC, transmit functions, receive func-
chip static memory at power-up from either an on-board tions, and demodulation. However, the chassis provided
EPROM or an external source such as a floppy disk. space for only three boards.
Project goals included the use of an existing proprietary
THE EARTHSTATION SYSTEM custom chip design from a previous application. MIA-Com
also investigated whether the design could be fit on only
MIA-Com recently employed one of these "programmable two boards, by using a gate array. Board design itself was
gate arrays" in the design of a satellite earthstation, in- driven by three primary factors: resource availability, cost,
tended to network commercial faCSimile operations. The and schedule. Since reducing the number of required
network handles traffic at 56 kbls, multiplexed into 26 boards would reduce design time and keep product costs
channels and convolution ally encoded, yielding an overall lower, MIA-Com decided to go with the gate array.
II
7-35
QTY. DESCRIPTION ITEM port controller and handles base-band X.25 data. Due to
8·BIT SHIFT REGISTER
the use of semicustom and programmable technology, the
3 74HCT164
remaining three functions were all merged onto the other
6 4·BIT COUNTERS 74HCT163 board, which we call a "sate"ite channel interface" (see
4 DUAL D FLlp·FLOP 74HCT74
Figure 2).
2 QUAD 2:1 MULTIPLEXER 74HCT157 We used a gate array for the transmit function, which
othelWise would have required about 70 chips. For the
1 QUADXOR 74HCT86
receive function, we originally planned to use an existing
1 HEX INVERTER 74HCT04 full-custom ASIC (previously designed by MIA-Com) for
fOlWard error correction, and an additional 25 SSIIMSI
1 QUAD NOR 74HCT02
parts for the receive logic. However, due to chassis
2 QUAD OR 74HCT32 constraints, the high density of components would have
necessitated a multi-layer board for the initial design.
3 QUAD AND 74HCT08
Furthermore, based on previous experience, the likeli-
1 OCTAL LATCH 74HCT374 hood of changes in the design specification was too high
to risk a custom or semicustom solution for the initial
1 OCTAL BUFFER 74HCT244
design. Therefore, we originally planned to produce the
251Cs
high-density boards in quantity and to reduce the cost of
the system at a later date, by first transferring the receive
Table 1. Standard Off·the·Shelf Equivalents to the Logic logic into a gate array and then replacing the expensive
114808 Contained in the LCA. high-density four-layer board with a two-layer board.
TRANSMIITER
ADDRESS ADDRESS
MICRO-
PROCESSOR DATA
~{;illlllrTJ-____________~:lm:ER:FAC:E~----
§
§ ... .....: ..
12
'~~
.,....
) .. : ,:.
7-36
Article Reprints
SGN=:J~::LE=~
g DATA
::;:5
O::l
<1:0
!LO {
::; MAG
W DATA
o
{ WR
RD
DEMUX-SGN DATA
DEMUX-MAG DATA
KEY: DEMULTIPLEXER
o DESCRAMBLER
fill TIME-DIVISION MULTIPLEXER
DEMUX-CLK
(SYNCRONIZATION CIRCUITS)
1148 10
is architectu rally similar to a gate array and is supported by in-circuit emulator for debugging.
a PC/AT-based workstation.
Our original schematic was based on conventional LS and
We determined that the internal organization of the LCA HCT parts; it included JK flip-flops and large counters
fitted the design requirements of the receive function. (implemented by cascading common 4-bit counters),
Specifically, the LCA provides many more flip-flops than rather than gate-level elements. Since that method of
other programmable logic devices, so that one chip con- design was inefficient for the LCA, we redesigned the
tained enough functionality for our needs. Further, the receive circuit at the gate level and then implemented it in
LCA provided the required density savings, and its repro- software via the cell array editor.
grammability obviated the risks associated with late engi-
neering changes. When engineering management was Using an LCA reduced the amount of hardware overhead
presented with the design alternatives, we decided to normally associated withLKS and HCTtechnology. It was
not necessary to waste control inputs, to cascade count-
prototype a reduced portion of the receive circuit and thus
evaluate the reconfigurable chip. ers, or to determine what to do with unused bits of multi-
plexers. In our design, 25 SSI/MSI gate-equivalents did
II
To implement the design, MIA-Com acquired the Xilinx not even use up all the resources available in one LCA.
XACT PC-based LCA development system. The system Table 1 indicates the parts that we actually employed in the
includes a macro library, with some of the required logic present design. Putting these functions in the LCA re-
already defined. After several days of experimenting with sulted in an 88% utilization of the internal cells, and a 60%
the design tools, it took us one day to enter and only two utilization of the I/O cells. Thus it still remains feasible to
hours to debug the design. We uses Xilinx's XACTOR add further functionality to the system, with no PCB
7-37
changes. We plan to do so in the future. Figure 3 is a The fourth state is entered every time a unique word is
schematic of the circuit placed in the LCA. Since the missed; the system stays in the fourth state until the unique
design is not 1/0 limited, there was no necessity to multi- word is found or is missed 11 consecutive times. If the
plex any of the input or output lines; but additional logic unique word is found, the system returns to state three; if
could have been added, should 1/0 multiplexing been it is not found after 11 attempts, then the first state (the
needed. Note also that the descrambling circuit can easily search mode) is initiated again. This method of operation
be reconfigured, or made more complex. Changing the ensures that the demultiplexer will remain locked even in
descrambler can be achieved merely by reprogramming the presence of random bit errors in the data stream.
the LCA.
After the unique word is detected, the receiver locks onto
One criticism leveled againstthe LCA is that it requires 12K the data. The LCA chip then descrambles the data stream.
bits of storage space to program the part during power-up. The data is originally scrambled by the transmitter to place
However, in our design, a 27C64 EPROM (used for a look- a fairly equal number of ones and zeros into the transmit-
up table) was already on the board. A portion of this ted carrier. If this is not done, the transmitted carrier may
EPROM was available to store the LCA configuration not contain an even distribution of spectral components,
program at no additional cost. Since the 12K bits of which makes it difficult for a demodulator to acquire the
storage space are used to program all the RAM cell carrier. The descrambling process is merely the reverse
locations in the LCA, adding further functionality to the of the 9-bit scrambling procedure.
LCA would not require more storage space.
A single channel is isolated from the others by demultiplex-
ing the descrambled data stream. The demultiplexing
ARCHITECTURE function is performed through a pair of counters that count
the bits between unique words and tell the demultiplexer
From the OPT, transmission is executed in the SCPC when data is available.
(single channel per carrier) mode. All scrambling, encod-
ing, and error-code generation are performed by Once the incoming data stream has been descrambled
MIA-Com's proprietary transmit gate array. The gate array and demultiplexed, it moves on to the MIA-Com proprie-
contains registers, allowing it to be programmed to trans- tary convolutional decoder, a custom chip where error
mit in different schemes and protocols, including SCPC detection and correction is done on a per-channel basis.
mode. Decoded data is passed on to a microprocessor for data
extraction.
The OPT receives a TDM (time division multiplexed)
bitstream composed of 56 kb/s data channels in a modu-
TESTING THE LCA
lated 3-MHz carrier. The bitstream contains a UW (unique
word), and data and parity bits for each channel in each To test the TDM synchronizer, the LCA was loaded via the
frame. The received carrier is demodulated by analog Xilinx in-circuit emulator and set into the test bed. We
circuitry on the SCI, which passes the digital bitstream to tested with a satellite simulator and found one design
the LCA. error. Both isolation and remedy of the fault were simple
to perform, due to the reconfigurability of the part. Fault
To isolate the UW and lock onto the data, the LCAcontains location was eased by chOOSing internal test nodes and
several counters and a state machine, configured in TDM connecting them to 110 pads. This technique made it
synchronizer. The state machine controls he synchron- possible to find the fault very quickly.
iztion algorithm, which manipulates the frames.
By using a satellite Simulator we were able to insert errors
The TDM synchronizer moves between four states (see into the datastream. We measured the time to lose sync
Figure 4). The first state entails acquiring "sync" by and the time to acquire sync, and determined that the
recognizing the unique word in the unsynchronized data ripple counterwas a little too slow forthe required function.
stream. Once the unique word is acquired without errors, Since we were using an in-circuit emulator, it was very
the second state occurs. The circuit verifies "sync" by easy to reprogram the device. After the design was
detecting the unique word again one frame later in the debugged, we left the simulator on-line for a week to
bitstream. Upon second detection, the circuit is consid- ensure a thorough test of the Xilinx part under operational
ered in sync, and the synchronizer shifts to the third state- conditions. Our concern was how well the LCA would
the sync state-where data are allowed to proceed as long retain its configuration, since this information is stored by
as the system detects at least one unique word in every 11 RAM cells. However, in our environment, it performed
frames. flawlessly.
7-38
Article Reprints
UNIQUE
WORD MISS
UNIQUE
WORD DETECT
UNIQUE UNIQUE
WORD MISS WORD DETECT
114811
Normally this time would have been used to design a test Rather than packing complete design into the front end of
fixture. Instead, another LCA design was created to an ASIC development, as is required for conventional gate
support a test implementation. Before the PCB was arrays, the LCA offers the flexibility to indicate roles forthe
delivered, the test fixture simulating the system was built, part. Designers can specify the I/O pins for the LCA then
primarily around the second Xilinx part. In the process of send the PC board to fabrication. While the board is in
building the fixture, we discovered an error in the PCB fabrication, designers can build into the LCA the gate-level
layout, even before it was delivered. It was possible to fix logic they want and continue to make changes up until, and
the error by reconfiguring the LCA. even after, the PCB is delivered.
When the board was delivered, a new version of our logic After final product delivery, the on-board logic can still be
design had been implemented in the Xilinx LCA, including reconfigured to match specific customer needs-without
the demultiplexing and descrambling functions. having to cast custom silicon for a few dozen units or
changing the PC artwork. Great NRE savings are passed
II
back to the customer. In summary, the LCA has proved to
CONCLUSIONS
be an extremely effiCient, useful, and cost-effective exten-
The flexibility of the Xilinx LCA lowers design costs, sion to our semicustom design capabilities.
reduces project schedule risks, and reduces inventory
risks. Using the LCA does not require much design Reprinted with permission from VLSI System Design.
sophistication, but rather a good general knowledge of
7-39
Programmable. Logic
Betters the Odds for
THE ElectronIC System Design Magazme
Bet-Slip Readers
by Cliff Dutton, GTECH Corp., Providence, RI
In countries throughout the world, the vitality of the on-line the sensor interface. Similar difficulties hindered direct
lottery industry is enhanced by seasonal and special comparison of achieved resolution. To accurately evalu-
promotional games. But new games require new bet-slips, ate these parameters, each sensor had to be designed into
and bet-slip readers must be able to accommodate fre- prototype readers. This involved driver and frame acqui-
quent changes in format. To accomplish this, program- sition clock signal generation.
mable gate arrays are replacing older, less flexible archi-
tectures. Because lotteries have no standard bet-slip size, as many
"standards" as possible need to be accommodated. Thus,
In the development of GTECH's Solid State Reader, many it was necessary to maintain flexibility in the format of the
existing technologies were evaluated, but they imposed target image.
unacceptable limitations on bet-slip processing, restricting
bet-slip formats to rows and columns. Moreover, the
process of reading the coupons was dependent on com- PROTOTYPING A SYSTEM
plex moving parts, and the reading elements were ex-
The implementation of a prototype system had one goal:
posed to the external environment.
to prove the feasibility of recognizing handmade marks in
To maximize flexibility and minimize board space, Xilinx's an imaging system. Because the volume of readers is
(San Jose, CAl Logic Cell Array (LCA) was chosen for the potentially high, component costs were a serious issue.
Solid State Reader. The LCA, touted by the company as
a "programmable gate array," represents a novel program- BOARD 1 MAIN CPU
mable logic device that is notable for its reprogrammable COMMUNICATIONS
PROCESSOR LINK
architecture. This architecture provides flexibility through- MEMORY
out the product's life span, which allows on-line bet-slips to CONTROL LOGIC
7-40
First, a working model was developed. To balance devel- In the initial design, flexibility did not exist. Even though
opment costs, a set of printed circuit boards based on TTL modularity protected the design from becoming obsolete,
logic devices was manufactured. Partitioned functionally, significant design alterations were required to accommo-
the board set supported modular design changes. Four pc date different sensors. Because sensor clock signals are
boards were initially developed: a CPU/memory board, a multiphase, new clock generators would be needed for
clock-driver board, an analog amplifier board, and a sen- new sensors. Also, bugs were difficult to find, and circuit
sor mounting board (Figure 2). board modifications were required to eradicate such bugs.
Kup!lfl{jfndellager
i5avbolagel 1fllljd
anordnadelipsom-
""GO
VlUj7nummer
aw3S
In!l81&per
SJ'elfiiIt7:50kf
Inlamningsdag 1 I
......./. ..... 19.......
• ··~I_,..G··'§I
~8 3 81
•
000
L8
36
L9
120
llO •
I~"", : : : : : , : : : : ,
08 1988 [::.::::
~.,
,v.
:u.~un;r.: Al1 ~r III I
Vgte.ta
"
(a)
• I
•
iil [i]~HHl [i]~HHl [i]~HHl [i][l[ii][ii] I
~ [i]~~§ [i][1l§§ [i]~§§ [i]~§§
B [jI[il[2l@] [jI[ilIil@] [jI[il[2l@] [jI[il[ii]@]
III
(e)
Figure 1. Betting slips for lotteries come in varied shapes and sizes. (a) Shown here are lotto slips from Europe
and (b and c) the United States. Such variety in slip design must be accommodated in the developement of bet-slip readers.
7-41
Article Reprints
Finally, the target image aspect ratio was fixed because Semicustom and full-custom technologies would have
the clock generation circuits were implemented in hard- solved all the functional problems, but they lack flexibility.
ware. Because the development of the reader was ongoing, the
commitment to custom implementations was out of the
Aspect ratios of target images are important because only question. In addition, nonrecurring engineering (NRE)
necessary information on the image needs to be proc- costs were prohibitive and the devices could not be
essed. If the target image is 2:1 and the imaging format is adapted to changing sensor technologies or changing bet-
1:1, for example, then half the image is useless. A better slip reading requirements.
solution would mirror the aspect ratio of the target image
in the Image format. Xilinx's LCAs permit a two-board set to be designed
without sacrificing functional modularity. In addition,
To overcome the limitations of hardwired logic and reduce counting algorithms can be implemented in the LCAs.
board space, several technologies were evaluated. These Finally, LeAs allow for a multiple-iteration development
included programmable logic arrays (PLAs), field pro- cycle.
grammable logic devices (FPLDs), semlcustom and
fullcustom devices, and Xilinx's Logic Cell Array (LCA).
PUTIING A BUG TO REST
Size constraints Indicated the necessity for semicustom of
full-custom integration, but traditional LSI technologies Initially, the TIL-based system was implemented infourpc
violated the flexibility constraint. Although full-custom was boards. However, it contained a bug. For every horizontal
attractive, design costs were prohibitive and did not permit line, an extra pixel pulse was be ing supplied. Although this
Iterative development. Standard PLDs did not allowforthe was confusing to the eye, it was compensated for in
variety of register-like functions that the clock generation firmware. Because the redesign of the clock driver board
logic required. was a significant task, the bug was allowed to live through
many Iterations of the development cycle. When the
Programmable logic arrays were attractive for some logic design of the clock generation circuit was translated into
functions and would have been the least costly. However, the LCA, it was a trivial matter to delete a single horizontal
PLAs did not allow the multiple register implementation clock pulse and put the bug to rest in an aftemoon.
necessary for clock generation. Thus, the counting algo-
rithms would have remained external to any integration of Using the LCA also provided the ability to vary the clock
the combinatorial logic. Also, although the PLA architec- generation circuitry to evaluate different sensors. Be-
ture would have saved board space, it would not have cause there is no standard architecture for solid-state
preserved the functional modularity achieved in the first digital imaging devices, clock requirements vary for differ-
implementation. Thus, it would have been impossible to ent sensors. In a standard imaging application, It might be
evolve a PLA-based system in response to changes in possible to source the appropriate support chips for each
sensor technology. Finally, any required changes would sensor from the manufacturer. But because development
have to be performed by field replacement. With over of the reader involved nonstandard video speeds in a
35,000 lottery terminals installed on five continents, this noninterlaced mode, it was impossible to use standard
was unacceptable. support chips. If It had been necessary to develop a clock
driver pc board for every sensor evaluated, it would have
Field programmable logic devices, an update of the been impossible to evaluate more than one sensor in the
PLA-style architecture allowing limited reprogrammability, development time. Because LCAs were used, varying
appeared to provide some of the flexibility needed. If the multiphase clocks could be generated for different sensors
problem were merely a straight combinatorial one, FPLDs under evaluation. Thus, the turnaround time for a design
could have been used. However, the difficulty in support- change in the clock generation circuits was reduced from
ing both registers and counting algorithms ruled out their one to six weeks to one day.
use.
7-42
SINGLE MAIN BOARD
The Solid State Reader does not rely on standard video
COMMUNICATIONS
PROCESSOR LINK output. Thus, the 4:3 standard aspect ratio for broadcast
MEMORY
television is not a requirement. All image processing is
internal to the system. Real-time display of the image is
ANALOG never required. Therefore, only those areas of the sensor
CIRCUITS
that may contain relevant information need to be required.
Information-bearing areas of a bet-slip vary with the bet-
slip deSign, so it is helpful to redefine the area of the sensor
that is acquired for processing.
SENSOR
Because the clock driver circuitry, the memory addressing
BOARD logic, and the frame-grabber logic are all implemented in
IMAGE SENSOR BOARD the reconfigurable LeA, it is possible to acquire only
certain areas of the image. As each sensor has different
horizontal and vertical clock pulses, this flexibility cannot
PRECISION OPTICS
be achieved in hardwired logic.
II
7-43
Electronic
Products
",,,",,,",",,,,,j,,,,,,,,,.,,, """,',,.
Building Tomorrow's Disk
Controller Today
Jim Reynolds, President, Dave Randall, Chief Engineer, Andromeda Systems, Canoga Park, CA
Reprogrammable logic with a flexible architecture could be surface mounted onto a 35-in.2 dual-width board.
enables a controller to keep up with today's high- The only answer appeared to be VLSI custom or semicus-
capacity, high-speed disk drives tom devices like gate arrays. But gate array definition
requires absolute design accuracy, and so a prototype
Computer manufacturers historically have relied on ad- must be constructed long before custom-tooled ICs can be
vances in CPU and semiconductor memory technology for specified and manufactured. Paradoxically, the prototype
increasing system throughput. At the same time, they itself required highly integrated logic.
accepted as inevitable the hardware-bound I/O bottle-
neck. This position is becoming untenable with recent To break thatfrustrating circle, it was necessary to convert
advances in magnetic di sk tech nologi es, which have led to directly from schematic capture to a silicon breadboard of
a proliferation of high-capacity, high-speed drives. multiple electrically programmable logic devices (EPLDs).
Because many logic functions would be added to the
Full performance from these drives needs sophisticated
prototype after the initial test, EPROM-based PALs were
controllers like Andromeda Systems' new Storage Module
considered, like the EP1200 from Altera, which licenses
Device Controller (SMDC). With a 1-Mbyte data cache
the technology from Monolithic Memories.
and dynamic read-ahead algorithms, the SMDC dramati-
cally reduces average disk access time and significantly
improves overall system performance (see box, ''The The EP1200 could provide the minimum functionality on
Storage Module Device ContrOller"). The design and the silicon breadboard, but not the level of device integra-
performance benefitted greatly from using Xilinx's Logic tion for the production circuit board. To implement the
Cell Arrays (LCAs). various state machines and other logic of the design, each
target gate array would need three EP1200s. The result-
Very early in the design, it was clear that its high-perform- ing schematic capture and simulation would then be used
ance caching scheme needed more SSI/MSI logic than to fabricate the gate arrays for the final product.
CACHE MEMORY
1-MBYTE DRAM PERIPHERAL
EXPANSION
.... PORT
i
CACHE DISK
~
I ADDRESS
MAPPER
r
I f-- CONTROLLER
Q-BUS
INTERFACE
I I ... STORAGE
MODULE
DEVICE
INTERFACE
LCA3
LCA.1 LCA2
Q-BUS AND DMA CACHE S~~~~~~5~1~~fAL ..
CONTROLLER CONTROLLER CONTROLLER
i I T
~ USER
65C802 MICROPROCESSOR SERVICE
I
PORT
STATIC EEPROM
RAM
1148 01
Figure 1_ On Andromeda Systems' new Storage Module Device Controller, Xilinx Logic Cell Arrays handle the Q-bus interface
and direct memory access (DMA) Control, RAM/data-cache control, and SMD and peripheral expansion port control.
7-44
Fortunately, this circuitous design path was bypassed by
using Xilinx's LCA (see box, "Xilinx's programmable gate
array"). There are two basic differences between LCAs
and other EPLDs. First, the LCA has the flexible archile(:-
ture of a gate array. Second, LCAs employ static memory
to hold the logic configuration data.
The LCAs brought several significant advantages to the
controller design. Since the Xilinx 2064 LCA has 64
configurable logic blocks and the EP1200 only 20, a single
LCA could replace the three target gate arrays, elimination
the fabrication delays and costs of custom tooling.
Furthermore, the position of the LCAs on the board could Figure 2. The user service port can create color bar graphs
be determined before their internal logic configuration was that dynamically show various attributes of the data cache,
designed. Other than dedication input and output pins, such as read times, forward block reads, and 1/0
completion rates.
only a general idea of the function of each LCA was
needed. The board layout and the internal LCA logic
design could proceed in parallel, greatly reducing develop- Aside from the LSI circuitry, the only other logic on the
ment time. Most design changes could be implemented SMDC board are TTL bus transceivers, SMD interface
merely by reprogramming the LCAs. Thus, use of the drivers, and a few PALs.
LCAs allowed the design to go directly from schematic
capture to a production board, skipping the wire-wrapped
prototype. The RAM of the data cache is in ZIPs. Most of the interface
logic was surface mounted to the board. Despite the
The first LCA on the SMDC is the Q-bus interface and board's small size, these VLSI devices permit several
direct memory access (DMA) controller (see Fig. 1). All but advanced features.
5 of the 64 internal logic blocks were used. The LCA holds
the DMA addressing logic, the bus registers, and the The SMDC's user service port connects directly to termi-
interrupt logic. nals or moderns. No special test programs for specific
system environments are needed to communicate with the
RAM/data-cache control is the job of the second LCA. It controller. Users can define drives, assign logical units,
controls the cache and has the interface between the disk format drives, and do other more esoteric functions.
controll.er IC and the DMA logic. It signals cache-write
enables, multiplexes memory addresses, and enable
This port can monitor the operation of the controller while
DMA reads and writes.
the drive is in operation. The user can display color bar
The third LCA controls the SMD port and peripheral graphs that dynamically show various attributes of the data
expansion port. The expansion port is just a group of cache, such as read times, forward block reads, and I/O
programmable 1/0 connections. Since the LCA is pro- completion rates. Caching parameters can be adjusted,
grammable, the control logic forthe expansion port can be letting the user tune the system for optimum performance.
reconfigured for any desired 1/0 interface. Thus, this port
provides for future expansions (like adding a tape drive, Firmware can alter the configuration data for the LCAs,
optical disk, or extra cache memory) at a fraction of the modifying the circuit schematic and not the board. Since
cost of a separate controller. Unused logic in this LCA will the firmware is in EEPROMs, the service port can accept
permit on-board functions to be added in future microcode microcode upgrades in the field via modem. PROM set
revisions to the controller. replacement and on-shelf obsolescence are.avoided.
II
7-45
Article Reprints
THE STORAGE MODULE DEVICE CONTROLLER a 1-Mbyte data cache and unique caching algorithms.
Andromeda divides the cache into 1,024 granules. The
Designed for LSI-11 and MicroNAX II systems, An- information kept for each 1-Kbyte granule depends on
dromeda Systems' Storage Module Device Controller select criteria, which include:
(SMDC) for Winchester drives supports two SMD or
SMDE drives at data rates up to 25 Mbits/s. Another The time data is first accessed
Andromeda controller, the ESDC, works with the En- The number of times data is read
hanced Small Device Interface, the ESDI, for Winches- The time of the most recent read
ters or floppy-disk drives. Both controllers use the stan- The size of the read.
dard DU device driver and work with such operation sys-
tems as RT-11, TSX+, RSX, RSX-11M, MicroRSX, This information is then entered into an equation that ap-
RSTS, MicroRSTS, Ultrix, DSM, Unix, and MicroVMS. proximates how probable it is that the granule will be re-
quested again soon. Those granules with low probabili-
The SMDC achieves more performance and flexibility ties are designated to be overwritten by the next disk-
than did previous generations of disk controllers. It in- read operation. During cache accesses, a memory map-
cludes data caching, high datactransfer rates, a periph- per translates logical memory addresses into the physi-
eral expansion port, field-Ioadable microcode, and a cal addresses of the appropriate granule in much the
user service port. State-of-the-art VLSI components same way that the Micro-Vax II memory management
and packaging techniques fit the entire controller within unit would.
the 35 sq in. of a dual-width Q-bus board (see figure).
PREDICTIVE CACHING
Using Digital Equipment'S Mass Storage Control Proto-
col (MSCP), the SMDC can partition two drives into as In a novel departure from most caching schemes, the
many as 16 logical units with up to 32 Gbytes each. On- SM DC caching mechanism not only looks at the past, but
board intelligence comes from a 65C802 microproces- tries to gaze into the future as well. As the system re-
sor, and all the processor's code resides in just two quests the data that has been pre-fetched into the cache,
EEPROMs. The majority of the remaining logic is imple- the controller retrieves not only the requested data, but
mented with Xilinx programmable Logic Cell Arrays also preemptively reads extra sequential blocks when
(LCAs). Data integrity is ensured by 48-bit error detec- specific probability conditions are met. As a result, the
tion and correction logic. An expansion port can be con- on-board cache's typical hit rate is over 80%. In other
nected to accessory modules, allowing control of de- words, the data being sought by the application will be
vices like tape drives, optical disks, or extra cache ready and waiting in the cache over 80% of the time.
memory.
Approximately 90% of the disk access time is due more
The performance of the SM DC is greatly enhanced with to average seek times and rotational latency than to the
actual data transfer rate. However, when a cache hit
occurs, the access time depends only on the speed of
the DMA channel responsible for sending the data to the
Q-bus.
$$$$$
Andromeda Systems' Storage Module Device Control-
ler is available now for $2,195. (The company's ESDI
controller is available for $1 ,995.) For more information,
call Don Talmadge at 818-709-7600, orcircle 336 forthe
SMDC and 337 for the ESDC.
7-46
1/0 BLOCK
XILlNX'S PROGRAMMABLE GATE ARRAY
o
products. Elements of the array include three categories
of configurable elements: I/O blocks, configurable logic
blocks, and programmable interconnections (see figure).
-{} 0 0 0
0 oro 0
I/O blocks provide an interface between the external
package pin and the internal logic. Each block includes a
-{}
programmable input path and output buffer. The array of
configurable logic blocks contains the functional elements
-{} ~ INTERCONNECT AREA---+
from which the user's logic is constructed. Each array
-{}
includes a combinatorial section, storage elements, and
internal routing and control logic. Programmable intercon-
nection resources connect the inputs and outputs of the
{I: 0 010 0
110 blocks and configurable logic blocks into the desire
{I:
networks.
II
7-47
Article Reprints
7-48
SECTIONS
Index
2 Product Specifications
4 Technical Support
5 Development Systems
6 Applications
7 Article Reprints
8 Index
Index
alpha particles ............................................. 2-3, -64; 3-9 counter ........... 6-28, -29, -30, -31, -32, -33, -34, -38, -40
alternate buffer ........................................................ 2-42 crystal oscillator ............................... 2-13, -23, -70; 6-10
applications ............................................................... 6-1 daisy chain ....................................................... 2-20, -76
APR ......................................................................... 5-10 DASH ...................................................................... 5-19
8-1
ESD ........................................................................... 3-9
•
Index
interconnect delay ............................................ 2-25, -80 net list interface ........................................................ 5-23
MAKEBITS .............................................. 2-17, -72, 5-11 performance ............................................ 2-24, -SO; 6-11
MAKEPROM ........................................................... 5-14 peripheral mode .................. 2-14, -20, -49, -75, -77, -96
master mode ...................................... 2-14, -18, -74, -76 physical dimension .................................................. 2-53
master parallel mode ....................................... 2-48, -95 pin assignment ................................................. 2-31, -86
master serial mode .......................................... 2-47, -94 pin description .................................................. 2-29, -S4
memory cell ................................................ 2-2, -64; 3-8 pinouts ...................................................... 2-32, -51, -S6
S-2
~XIUNX
PLL .......................................................................... 6-37 slave mode .......................... 2-14, -20, -50, -76, -78, -97
power distribution ...................................... 2-26, -27, -71 speed ............................................................... 2-24, -80
power down ............................................ 2-15, -27; 6-18 standby .................................................................. 2-178
prescaler .......................................................... 6-38, -40 state machine ................ :.................................. 6-48, 7-8
pull-up resistors ........................................ 2-12, -80; 6-9 test specifications ...................... 2-110, -127, -146, -165
readback ............................. 2-21, -22, -50, -77, -78, -97 tracking .................................................................... 6-14
reconfigurable logic ................................................. 7-24 training courses ........................................................ .4-7
reconfigure ....................................................... 7-15, -19 typical delays ........................................................... 6-14
reliability .................................................................... 3-1 up/down counter ....................................... 6-30, -31, -33
XC3000 design .......................................................... 6-7 xtal oscillator .................................... 2-13. -23, -70; 6-10
8-4
Sales
Offices
•
FAX: 408-986-1947 (404) 263-0320 (317) 882'4407
Tel: (49) 89-6110851
Fax: (49) 89-6112246 404-263-8946 FAX: 317-888-8416 Advanced Technical Sales
1810 Craig Road, Suite 213
51. Louis, MO 63146
(314) 878-2921
FAX: 314-878-1994
8-5
Sales Offices
'Activates Fax
8-6
~
CANADA (QUEBEC) R.T.F. Rhone-Alpes INDIA Dia Semicon Systems, Inc. THE NETHERLANDS
Electro Source Mini Parc - Zac des Beali~res Flower-Hill Shin-Machi
Malhar Corporation Rodelco BV Electronics
6600 TransCanada Hwy 23, Avenue de Granier 924 County Line Road East Bldg. Takkebijsters 2
Suite 420 Point Claire 38240 Ebbens Bryn Mawr, PA 19010 1-23-9 Shin-machi, P.O. Box 6824
Quebec H9R 4S2 Tel: (33) 76-90 11 88 (215) 527-5020 Setagaya-ku, 4802 HV Breda
(514) 630-7486 FAX: (33)76-41 04 09 FAX: (215) 525-7805 Tokyo, 154 Japan The Netherlands
FAX: 514-630-7421 Tel: (03) 3439-2700 Tel: (31) 76-784911
GERMANY FAX: (03) 3439-2701 FAX: (31) 76-710029
IRELAND
DENMARK Metronik Memec Ireland ltd. New Japan Radio Trading NORWAY
Dana Tech KS Leonhardsweg 2 Innovation Centre Co., Ltd.
PO Box 1361 8025 Unterhaching Enterprise House Shiba-Eitaro Bldg. 8.I.T. Elektronikk SA
Smedeland 8 MOnchen, Germany Plassey Technological Park 4-14 Shiba-Daimon l-chome, P.O. Box 36 Lerbyen
2800 Glostrup Tel: (49) 89-611080 Limerick Minato-ku, N-3401 Lier, Norway
Denmark FAX: (49) 89-6116468 Ireland Tokyo, 105 Japan Tel: (47) 3-8470 99
Tel: (45) 2-4345 47 Tel: (03) 3459-1521 FAX: (47) 3-84 55 10
Tel: (353) 61-330742/5
FAX: (45) 2-4345 67 Metronik FAX: (353) 61-3318-88 FAX: (03) 3459-1520
Semerteichstrasse 92
SOUTHEAST ASIA
FINLAND 4600 Dortmund 30 Okura Electronics Co., ltd.
Dortmund, Germany ISRAEL Excel Associates, ltd.
Field OY Instrumentarium 3-6, Ginza Nichome,
Tel: (49) 231-423037/38 1502 Austin Tower
Niittylanpolku 10 E.I.M International ltd. Chuo-ku, Tokyo, 104 Japan
TLX: (49) 8227082 8 Emil ZolaSt. 22-26A Austin Avenue
SF -00620 Tel: (03) 3564-6871 TSimshatsui, Kowloon
Helsinki, Finland P.O. Box 4000 FAX: (03) 3564-6870
Metronik Petach Tiqva Hong Kong
Tel: (358) 0-7571011 Tel: (852) 3-7210900
FAX: (358) 0-798853 Osterbrooksweg 61 Israel 49130 Okura Electronics Service
2000 Schenefeld FAX: (852) 3-696826
Tel: (972) 3-92 33257 Co., ltd.
FRANCE Hamburg, Germany FAX: (972) 3-9244857 Kyoei Bldg.
Tel: (49) 40-8304061 5-3, Kyobashi 3-chome, SPAIN
Reptronic TLX: (49) 2162488 ITALY ADM Electronica SA
1 Bis, rue Marcel Paul Chuo-ku, Tokyo, 104 Japan
Tel: (03) 3567-6501 Menorea No.3 Entreplants
Batimen R ACSIS S.R.L.
Metronik Via Alberto Mario. 26 FAX: (03) 3567-7800 Madrid 28009
Z.1. de la Bonde Siemensstrasse 4-6 Spain
F-91300 Massy 20149 Milano, Italy
6805 Heddesheim Tokyo Electron Limited Tel: (34) 1-4094725
Tel: (33) 1-60139300 Mannheim, Germany Tel: (39) 2-4390832
FAX: (39) 2-4697607 P. O. Box 7006 FAX: (34) 1-4096903
FAX: (33) 1-60139198 Tel: (49) 62-034701-03 Shinjuku Monolith
TLX: (49) 465053 3-1 Nishi-Shinjuku 2-chome, SWEDEN
R.T.F. Composant Celdis Italiana S.PA
81, Rue Pierre Semard Via F.ill Gracchi N36 Shinjuku-ku, DJ.P. Electronics AB
Metronik 20092 Cinisello Balsamo Tokyo, 163 Japan Danvik Centre
92320 Chatillon sis Bagneux Laufamholzstr.118
France Milano, Italy Tel: (03) 3340-8193 P.O. Box 15046
8500 NDrnberg 30 FAX: (03) 3340-8408 S-104 65 Stockholm, Sweden
Tel: (33) 1-49652700 NDrnberg, Germany Tel: (39) 2-61 8391
FAX: (33) 1-49652738 FAX: (39) 2-61 73513 Tel: (46) 8-4491 90
Tel: (49) 911-590061/62 Towa Elex Co., ltd. FAX: (46) 8-430047
TLX: (49) 626205 Lapore Shinjuku
R.T.F. Sud-Ouest Celdis Italiana S.P.A.
Avenue de la Mairie Via Massarenti 219/4 2-15-2 Yoyogi, SWITZERLAND
Metronik 40138 Bologna, Italy Shibuya-ku, Tokyo, 151
31320 Escalquens, France Lbwenstr. 37 Data Comp AG
Tel: (39) 51-533336 Japan
Tel: (33) 61-8151 57 7000 Stuttgart 70 Silbernstrasse 10
FAX: (33) 61-81 5157 Tel: (03) 5371-3411 CH-8953 Dietikon
Stuttgart, Germany FAX: (03) 5371-4760
Celdis Italiana S.PA Zurich, Switzerland
Tel: (49) 711-764033/35 Via Savelli 15
R.T.F. Aquitaine TLX: (49) 7255228 Tel: (41) 1-7405140
13, Rue I'Hote 351 00 Padova, Italy Varex Co., Ltd. FAX: (41) 1-7413423
33000 Bordeaux, France Tel: (39) 49-77 209 9 Nippo Shin-Osaka No.2 Bldg.
GREECE 1-8-33, Nishimiyahara,
Tel: (33) 56-52 99 59 TAIWAN
FAX: (33) 56-48 1783 Peter Caritato and Assoc. S. A. Celdis italiana S.P.A. Yodogawa-ku,
Ilia Iliot, 31 Via G. Pitre' 11 Osaka, 532 Japan Molecatex, Inc.
Athens 11743 Greece 00162 Roma, Italy Tel: (06) 394-5201 21F 258 Sec3
R.T.F. Rhone-Auvergne Nanking East Road
Parc Club du Moulin a Vent Tel: (30) 1-9020165 Tel: (39) 6-428971 FAX: (06) 394-5449
FAX: (30) 1-9017024 Taipei, Taiwan R.O.C.
BAt G.33, Rue du Doeteur
Levy Celdis ltaliana S.PA KOREA Tel: (886) 2-7410400
HONG KONG Via Mombarcaro 96 FAX: (886) 2-7217461
69200 Venissieux, France Excel-Tech
Tel: (33) 78-000726 Excel Associates, Ltd. 10136 Torino,italy 410-5 Hapjeong-Dong
FAX: (33) 78-01 2057 Tel: (39) 11-3299388 Mapo-Gu Jeritron Ltd.
1502 Austin Tower SlF Fu San Building
22-26A Austin Avenue Seoul, Korea
JAPAN 1182 Cheng-Teh Road
R.T.F Provence Cote D'Azur Tsimshatsui, Kowloon Tel: (82) 2-3357823 Taipei, Taiwan, R.O.C.
Residence du Petit Bosquet Hong Kong Okura & Co., Ltd. FAX: (82) 2-3357825
BAt. C-18 Tel: (886) 2-8823154
Tel: (852) 3-7210900 6-12, Ginza Nichome FAX: (886) 2-8820710
Avenue du Petit Bosquet FAX: (852) 3-696826 Chuo-Ku
13012 Marseilles, France Tokyo, 104 Japan
UK
Tel: (33) 91-060218 Tel: (03) 3566 6361
FAX: (33) 91-06 4782 FAX: (03) 35635447 Memec
17 Thame Park Road
R.T.F. Ouest Thame
3, rue de Paris Oxon OX93XD
35510 Cesson Sevigne, England
France Tel: (44) 84-4261939
FAX: (44) 84-4261678
•
Tel: (33) 99-83 84 85
FAX: (33) 99-83 80 83
151<9190
8-7
Sales Offices
Marshall Industries
locations throughout
the U.S. and Canada.
(818) 459-5500
FAX: 818-459-5660
8-8
For Further Information .. .Please check the appropriate box
o Please have a Sales Representative call me.
o I would like to borrow a copy of your Logic Cell Array
Technical Demonstration Video.
o Please add my name to your mailing list.
My application is _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Company _ _ _ _ _ _ _ _ _ _ N V S - - - - - - - - - - -
Street Adilless _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
City _ _ _ _ _ _ _ _ _ __
State _ _ _ _ _ _ Zip _ _ __
Phone ( ____ ) _ _ _ _ _ __ The Programmable Gate Array Company
XILINX
2100 Logic Drive
SanJose, CA 95124-9920
NO POSTAGE
NECESSARY
IF MAILED
IN THE
UNITED STATES
XILINX
2100 Logic Drive
San Jose, CA 95124-9920
Ildllllllllllllldlllllllllllllllllllllllllllllllll
1:XILINX
The Programmable Gate Array Company.
2100 Logic Drive, San Jose, CA 95124.
Printed in U.
Tel: (408) 559-7778 EasyLink 629 16309 1WX: 5106008750 X1L1NX UQ FAX: (408) 559-7114 PIN 0010048