Multiple Choice Question (Topic 1 part 1) 6. Tens of thousands of chips embed.

a. Small scale integration

1. The following are VLSI circuit
b. Medium scale integration
advantage EXCEPT.
c. Large scale integration
a. Low bandwidth
d. Very large scale integration
b. Low power
7. Millions of chips and millions of
c. Faster
transition.
d. Embedded design
a. Small scale integration
2. Putting millions of transistor on a single
b. Medium scale integration
chip is also called.
c. Large scale integration
a. System on chip
d. Very large scale integration
b. Systems of chip
8. Which of the following consumes much
c. Networks on chip
more time in VLSI design?
d. All
a. Design
3. Tens scale of transistor in a single chip.
b. Testing
a. Small scale integration
c. Verification
b. Medium scale integration
d. All
c. Large scale integration
9. Process of which it includes placement
d. Very large scale integration
of gates, flip flop etc.
4. hundreds scale of transistor in a single
a. Placement
chip.
b. Floorplan
a. Small scale integration
c. Routing
b. Medium scale integration
d. All
c. Large scale integration
d. Very large scale integration
5. Thousands of chips and hundreds of
10. Exact location in the die when the
transitions of chip.
circuit components are place.
a. Small scale integration
a. placement
b. Medium scale integration
b. floor plan
c. Large scale integration
c. routing
d. Very large scale integration
d. all

Topic 1 part 2

1. Almost all steps of VLSI design are automated.

 a. True
b. False
c. Maybe
2. HDL means?
a. High definition language
b. Hardware definition language
c. Hybrid definition language
d. None of the above
3. All the following are example of CDFG except.
a. Operational nodes
b. Control nodes
c. Storage nodes
d. Register nodes
4. Edge of CDFG in which variables are change due to processing in operational and
storage nodes.
a. Control flow
b. Variable flow
c. Transfer of values
d. Control of values
5. CDFG stands for
a. Control and data flow diagram
b. Control and data flow diagram
c. Counter and data flow diagram
d. Counter and data free diagram
6. Which of the following are true.
a. Speed of ripple carry adder is lower than carry look ahead adder
b. Speed of ripple carry adder is higher than carry look ahead adder
c. Area of the look ahead adder is lower than ripple carry adder
d. None of the above
7. What are the two types of CDFG?
a. Control flow and segment flow
b. Control flow and data flow
c. Carry flow and segment flow
d. Carry flow and data flow
8. Which of the following CDFG types provides parallel evaluation?
a. Control flow
b. Segment flow
c. Data flow
d. Carry flow
9. +, -, * and / are known as ______
a. Variable
b. Register
c. Sub computation
d. Values
10. Optimization steps of HLS is more suitable to be performin
a. Control flow
b. Segment flow
 c. Data flow
d. Carry flow

Topic 1 part 3 a. HDR

b. CDFG
1. First step for VLSI design
c. RTL
a. HDR
d. HLS
b. CDFG
3. Process of transforming human
c. RTL
written codes such as HDL to much
d. HLS
more efficient codes for HLS.
2. Widely accepted modelling paradigm
a. Reprocessing
for specification in VLSI.
 b. Transformation d. None
c. Reduction 10. Type of elimination where
d. Filtration computation has no effect on the
4. All of the following are output.
transformation process of CDFG a. Flow graph based transformation
except. b. Tree height reduction based
a. Compiler based transformation transformation
b. Flow graph transformation c. Dead computation elimination
c. All of the above d. None of the above
d. None
5. Process in compiling where it
improves the quality of a program in
terms of runtime
a. Code optimization
b. Code transformation
c. Proving codes
d. Proving transformation
6. Process of change of instruction
sequence, elimination of instruction
while retaining the meaning.
a. Code optimization
b. Code transformation
c. Proving codes
d. Proving transformation
7. An expression evaluated inside a loop
that uses operands whose values do
not change from iteration to iteration. Topic 2 part 1
a. Hardware for computing 1. Second step of HLS
b. Body execution a. Operation
c. Loop variant computation b. Scheduling
d. Code variation c. Operation –
8. Conditions required to determine loop scheduling
variant computation except d. All of the above
a. All operands are constant 2. 3rd step for HLS
b. All the computations that assign a. Operation
values to the operands are located b. Scheduling
outside the loop c. Allocation
c. All the computations that assign d. None
values to the operands are 3. 4th step of HLS
themselves loop variant a. Binding
d. All operands are variable b. Scheduling
9. Process of eliminating varying codes c. Allocation
yet same results d. Operation
a. Verilog reduction 4. Final step for HLS
b. Redundant computation a. Scheduling
elimination b. Data path and
c. VHDL reduction controller regulation
 c. Control flow data path b. Interconnection
d. Operation c. Time
5. RCS stand for? d. connection
a. Resource constrained
scheduling
b. Received constrained
scheduling
c. Received console
scheduling
d. None of the above
6. Clock in which it will run
from logic zero to logic 1
transition.
a. Negative edge
b. Positive edge
c. All
d. n/a
7. among the 3 sub step of
HLS scheduling allocation
and binding what can be
done without information
regarding design library.
a. Scheduling
b. Allocation Topic 2 part 2
c. Binding 1. what are the 2 types of
d. All algorithm
8. Other term for binding a. heuristics and exact
task. b. integer and exact
a. Resource sharing c. heuristics and
b. Mutually exclusive comprise
task d. heuristics and exact
c. Sub function task 2. what ASAP stands for in
d. All HLS algorithm
9. The binding step assigns a. As Soon As Possible
operation to operational b. All Secondary
modules. Algorithm Pair
a. Storage binding c. Both
b. Interconnection d. None
binding 3. What is ALAP stands for
c. Functional unit in HLS algorithm.
binding a. As late As Possible
d. All b. All Late Algorithm
10. Binding steps that assign Pair
input, output and c. Both
temporary variables to d. None
register unit.
a. Storage
4. Finding ALSP and ALAP b. Late scheduling
scheduling first starts c. List scheduling
what scheduling process. d. List scheduling
a. Heuristics scheduling 10. All are type of scheduling
b. Force directed except
scheduling a. Unconstrained
c. Integrated scheduling b. Time constrained
d. All c. Resource constrained
5. FDS stand for d. Low constrained
a. Follow directed source
b. Force directed
scheduling
c. Few distance schedule
d. All
6. Type of scheduling except
of scheduling operation to
early control steps in
determining maximum
number of control step hat
are allowed.
a. ALSP
b. ALAP
c. CDFG
d. All
7. Algorithm that produce
close to optimal result yet
quickly produce.
a. FDS
b. Heuristics
c. Exact
d. All
8. Algorithm that provides
optimal schedule but
consumes high processing
time
a. FDS
b. Heuristics
c. Exact
d. All
9. LS stands for
a. Low scheduling