NATIONAL UNIVERSITY OF SCIENCE AND

TECHNOLOGY

Digital System Design (EE-421)

Assignment #1

Instructor: Dr. Rehan Ahmed Section: BEE-12C

Dated: 07-03-2023 Semester: Sixth (6th)

Group Members
Name CMS ID
Tariq Umar 334943
Danial Ahmed 331388
Table of Contents
• Introduction
• Structure
• Modules
I. ROM
II. Counter
III. MUX
IV. Decoder
V. Registers
VI. ALU
VII. Binary to HEX
VIII. Clock
• Fibonacci File
• Simulations
i) Hardware Simulation
ii) RTL Viewer
iii) Test bench Simulation
• Conclusion

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Introduction
This report outlines the process of building a 4-bit microprocessor using
Verilog HDL (Hardware Description Language). A microprocessor is a fundamental
component of modern digital electronics, used in everything from smartphones to
supercomputers. The aim of this project was to design and implement a simple yet
functional microprocessor capable of executing basic instructions such as arithmetic
and logic operations.
The project involved several stages, including designing the architecture of
the microprocessor, writing Verilog code to describe its behavior, simulating the
design to test its functionality, and finally synthesizing the design to generate a
physical implementation. We performed the code onto an FPGA available in Lab, to
perform the number crunching machine as required in Assignment.

Structure
We were given the main structure of the Number crunching machine to perform the
Fibonacci sequence. We started by making separate modules for each portion which
includes ALU, Registers, MUX, Decoder, Counter and ROM. In the end, we stitched
it all up together in the Top Module which we have named as ‘Assignment’.

Our process starts from the ROM, to which we have stored all the instructions at the
beginning. We will be using a 4-bit counter connected to address line of instruction
memory, such that initially the value of counter is zero. As soon as the positive edge
of clock comes, zeroth instruction is executed by our design as well as the counter
gets incremented.

The 8-bit wide instruction will then control the ALU and registers to perform our
Arithmetic operations accordingly.

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Modules
We used multiple modules for each block shown in the diagram above, and then
used the top module ‘Assignment’ to instantiate each module as required. Each
module has its own RTL Netlist and Code attached.

Top Module:
We have named our top module as ‘Assignment’ and we have instantiated all other
modules in this. This is our Top level entity and stiches all the other modules
together.

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 module Assignment1(
input CLOCK_50,
input [3:0]KEY,
output [6:0]HEX0,
output [6:0]HEX1,
output [6:0]HEX2,
output [6:0]HEX3,
output [6:0]HEX4,
output [6:0]HEX5
);
/// Wires ///
wire [3:0]Counter_out;
wire [7:0] Code;
wire clk;
wire [4:0] ALU_out;
wire [3:0]Ro_out;
wire [3:0]Ra_out;
wire [3:0]Rb_out;

wire Reset;
wire Load;
wire [3:0]Custom_in;
wire s_cin;
wire J;
wire C;
wire Sreg;

wire [3:0]Mux_out;
wire Ra_en;
wire Rb_en;
wire Ro_en;

wire Carry_out;
wire [1:0]Dec_in;
wire [3:0]Dec_out;
/// Assignments ///

assign Reset = KEY[0];

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 assign J = Code[7];
assign C = Code[6];
assign Load = (C & Carry_out) | J;

assign Dec_in = Code[5:4];

assign Sreg = Code[3];
assign s_cin = Code[2];

assign Custom_in[2:0] = Code[2:0];

assign Custom_in[3] = 1'b0;

assign Ra_en = Dec_out[0];

assign Rb_en = Dec_out[1];
assign Ro_en = Dec_out[2];

assign HEX2 = 7'b1111111;

assign HEX3 = 7'b1111111;
assign HEX4 = 7'b1111111;
assign HEX5 = 7'b1111111;

//////////////// Custom Clock //////////////////

Clock Clock1 ( .clk_50in(CLOCK_50),
.clk(clk)
);
/////////////// Counter /////////////////////////
Counter C1 (
//.clk(clk),
.clk(CLOCK_50), //For Simulation Purpose
.Custom_input(Custom_in),
.Load(Load),
.Reset(Reset),
.Counter_out(Counter_out)
);
//////////////// ROM /////////////////////////////

rom r1(
//.clk(clk),
.clk(CLOCK_50), //For Simulation Purpose
.addr(Counter_out),
.q(Code)

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 ////////////// ALU //////////////////////////
Fourbitadder mod1 (
.s_cin(s_cin),
.a(Ra_out),
.b(Rb_out),
.s(ALU_out)
);
/////// Output to Hex //////////////////////////
Binary2HEX B1 (
.Bin(Ro_out),
.HEX0(HEX0),
.HEX1(HEX1)
);
/////////////// Registers ///////////////////////

flop4e Ra (
// .clk(clk),
.clk(CLOCK_50), //For Simulation Purpose
.d(Mux_out),
.q(Ra_out),
.enable(Ra_en),
.Reset(Reset)
);

flop4e Rb (
// .clk(clk),
.clk(CLOCK_50), //For Simulation Purpose
.d(Mux_out),
.q(Rb_out) ,
.enable(Rb_en),
.Reset(Reset)
);
flop4e Ro (
// .clk(clk),
.clk(CLOCK_50), //For Simulation Purpose
.d(Ra_out),
.q(Ro_out) ,
.enable(Ro_en),
.Reset(Reset)
);

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 ////////////// ALU //////////////////////////
Fourbitadder mod1 (
.s_cin(s_cin),
.a(Ra_out),
.b(Rb_out),
.s(ALU_out)
);
/////// Output to Hex //////////////////////////
Binary2HEX B1 (
.Bin(Ro_out),
.HEX0(HEX0),
.HEX1(HEX1)
);
/////////////// Registers ///////////////////////

flop4e Ra (
// .clk(clk),
.clk(CLOCK_50), //For Simulation Purpose
.d(Mux_out),
.q(Ra_out),
.enable(Ra_en),
.Reset(Reset)
);

flop4e Rb (
// .clk(clk),
.clk(CLOCK_50), //For Simulation Purpose
.d(Mux_out),
.q(Rb_out) ,
.enable(Rb_en),
.Reset(Reset)
);
flop4e Ro (
// .clk(clk),
.clk(CLOCK_50), //For Simulation Purpose
.d(Ra_out),
.q(Ro_out) ,
.enable(Ro_en),
.Reset(Reset)
);

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 /////////////// Output Carry ///////////////////////

flop f1(
// .clk(clk),
.clk(CLOCK_50), //For Simulation Purpose
.d(ALU_out[4]),
.Reset(Reset),
.q(Carry_out)
);

////////////// DECODER ///////////////////////

dec_2to4 dec1 (
.D(Dec_in),
.O(Dec_out)
);

////////////// MUX ///////////////////////

mux_4b_2to1 m1 (
.s(Sreg),
.u(ALU_out[3:0]),
.v(Custom_in),
.m(Mux_out)
);
endmodule

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ROM:
The part that drives the entire microprocessor is the ROM, we give it certain
instructions that we have given in the Fibonacci .txt file in this case. After each clock
cycle, the counter is incremented by 1 and the next instruction is given by the ROM.

module rom
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=4)
(
input clk,
input [(ADDR_WIDTH-1):0] addr,
output [(DATA_WIDTH-1):0] q
);

// Declare the ROM variable

reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0];

initial
begin
$readmemb("C:/intelFPGA_lite/20.1/projects/Assignment1/Fibonacci.txt", rom);
end

assign q = rom[addr];
endmodule

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Counter:
The counter stores the memory address of the next instruction to be executed. After
every clock cycle, it is incremented by 1. However, if a reset is given to it, the value
goes back to the initial one.

module Counter (
input clk,
input [3:0] Custom_input,
input Load,
input Reset,
output reg [3:0] Counter_out
);
always @ (posedge clk, negedge Reset) begin
if(Reset == 0)
Counter_out <= 4'b0000;
else if (Load)
Counter_out <= Custom_input;
else
Counter_out <= Counter_out + 1;
end
endmodule

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MUX:
MUX is a digital logic circuit that selects one of several input signals and forwards
it to a single output line based on the control inputs. In our case, it will let us choose
which Register to send the value to.

module mux_4b_2to1 (
input s,
input [3:0] u,
input [3:0] v,
output reg [3:0] m
);
always @(*) begin
case (s)
1'b0: begin
m = u;
end
1'b1: begin
m = v;
end

default: begin
m = 4'b0000;
end
endcase
end
endmodule

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Decoder:
A decoder is a digital logic circuit that converts a binary code into a specific output
state. It has multiple input lines and multiple output lines. In our case, it will help
us choose which register’s enable is given value 1.
module dec_2to4 (
input [1:0] D,
output reg [3:0] O
);
always @(*) begin
case (D)
2'b00: begin
O = 4'b0001;
end
2'b01: begin
O = 4'b0010;
end
2'b10: begin
O = 4'b0100;
end
2'b11: begin
O = 4'b1000;
end
default: begin
O = 4'b0000;
end
endcase
end
endmodule

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Registers A, B, Output:
A 4-bit register is a digital circuit that stores 4 bits of binary data. It is a type of
sequential logic circuit that is used to hold data that is being actively processed or
temporarily stored for future use.

module flop4e (input clk,

input [3:0] d,
output reg [3:0] q,
input wire enable,
input wire Reset
);
always @ (posedge clk, negedge Reset) begin

if (Reset == 0) begin
q <= 4'b0000;
end else if(enable == 1)begin
q <= d;
end else begin
q <= q;
end
end
endmodule

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ALU:
All the Arithmetic calculations are performed by the ALU. This includes addition
and subtraction in our case. The ALU decides to perform either addition or
subtraction based on the selection input S.

module Fourbitadder(
input s_cin,
input [3:0]a,
input [3:0]b,
output reg [4:0]s
);
always@(*)
begin
if(s_cin==0)
s = a + b;
else
s = a - b;
end
endmodule

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Binary to HEX:
We convert binary values to a more suitable type in order to display our results on
a 7-segment LED. The 7-segment is active low. This module lets us display our
value on LED, by reading binary values as decimal numbers.

module Binary2HEX (
input [3:0]Bin,
output reg [6:0]HEX0,
output reg [6:0]HEX1
);
reg [3:0]OUT;
always @(Bin)
begin
OUT = Bin;
if (Bin < 4'b1010) begin
HEX1 = 7'b1000000;
end else begin
HEX1 = 7'b1111001;
OUT = Bin - 10;
end
case (OUT)
0 : HEX0 = 7'b1000000;
1 : HEX0 = 7'b1111001;
2 : HEX0 = 7'b0100100;
3 : HEX0 = 7'b0110000;
4 : HEX0 = 7'b0011001;
5 : HEX0 = 7'b0010010;
6 : HEX0 = 7'b0000010;
7 : HEX0 = 7'b1111000;
8 : HEX0 = 7'b0000000;
9 : HEX0 = 7'b0010000;
default : HEX0 = 7'b1111111;
endcase
end
endmodule

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Custom Clock:
The internal clock of the FPGA we are using is 50MHz, and the issue faced when
using that clock is that it is too fast for a human. So in order to make it user-
friendly, we divided the clock in such a way that one period is of one second.

module Clock( input clk_50in,

output reg clk
);
reg [23:0] count_reg = 23'd0000000;
always @(posedge clk_50in) begin
count_reg <= count_reg + 1;
if (count_reg == 23'd4999999) begin
count_reg <= 23'd0000000;
clk <= ~clk;
end
end
endmodule

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Fibonacci File
We created a Fibonacci file that would be given be read and executed by the ROM.
The .txt file has also been attached to the submission in LMS. These are the
instructions in the .txt file and also what they perform:

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Complete Netlist:

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Simulations
The hardware simulation Video is attached to the LMS submission. We have shown
the screenshots of that video below. The following hardware was done on the
DE-10 FPGA board.

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Test Bench Simulation:
Before performing on FPGA, we checked out the code on the software using the
Test bench. We have attached the Screenshot of the output of the testbench below:

Conclusion:
In this assignment, we made a 4-bit Microprocessor that can perform Addition as
well as Subtraction. It uses an 8-bit Opcode that tells the microprocessor what to do.
It also has one of the basic functions like performing a number of instruction multiple
by jumping the flow of commands from one point to another within the memory of
the ROM.
In this assignment, we used this microprocessor to display the Fibonacci series from
0-13 in a loop, with an option to reset to 0 at any point. The results were displayed
on 7-Segment. This was implemented on Intel’s DE10-Standard FPGA board.

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