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    CV2 Anweshan NX

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    Shounak Das
    This document contains the resume of Anweshan Goswami which includes his education, work experience, projects and skills. He has an MTech in Electronics and Communications from IIIT Allahabad with a CGPA of 7.87 and a BE in Power Plant Engineering from Jadavpur University with a CGPA of 7.99. He has worked as a teaching assistant at IIIT Allahabad and has completed projects involving designing a 32-bit RISC processor using Verilog, static timing analysis using LT-Spice, and verification methodology using System Verilog. His skills include Verilog HDL, System Verilog, computer architecture and C programming.

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    CV2 Anweshan NX

    Uploaded by

    Shounak Das
    23 views1 page
    This document contains the resume of Anweshan Goswami which includes his education, work experience, projects and skills. He has an MTech in Electronics and Communications from IIIT Allahabad with a CGPA of 7.87 and a BE in Power Plant Engineering from Jadavpur University with a CGPA of 7.99. He has worked as a teaching assistant at IIIT Allahabad and has completed projects involving designing a 32-bit RISC processor using Verilog, static timing analysis using LT-Spice, and verification methodology using System Verilog. His skills include Verilog HDL, System Verilog, computer architecture and C programming.

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    This document contains the resume of Anweshan Goswami which includes his education, work experience, projects and skills. He has an MTech in Electronics and Communications from IIIT Allahabad with a CGPA of 7.87 and a BE in Power Plant Engineering from Jadavpur University with a CGPA of 7.99. He has worked as a teaching assistant at IIIT Allahabad and has completed projects involving designing a 32-bit RISC processor using Verilog, static timing analysis using LT-Spice, and verification methodology using System Verilog. His skills include Verilog HDL, System Verilog, computer architecture and C programming.

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    © All Rights Reserved
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    23 views1 page

    CV2 Anweshan NX

    Uploaded by

    Shounak Das
    This document contains the resume of Anweshan Goswami which includes his education, work experience, projects and skills. He has an MTech in Electronics and Communications from IIIT Allahabad with a CGPA of 7.87 and a BE in Power Plant Engineering from Jadavpur University with a CGPA of 7.99. He has worked as a teaching assistant at IIIT Allahabad and has completed projects involving designing a 32-bit RISC processor using Verilog, static timing analysis using LT-Spice, and verification methodology using System Verilog. His skills include Verilog HDL, System Verilog, computer architecture and C programming.

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    Anweshan Goswami

    IIIT ALLAHABAD

    EDUCATION
    MTech in Electronics and Communications
    Indian Institute of Information Technology, CGPA: 7.87
    Allahabad |
    2021 – 2023 | Prayagraj, India

    B.E in Power Plant Engineering


    Jadavpur University, Kolkata | CGPA- 7.99
    2017 – 2021 | Kolkata, India

    WORK EXPERIENCE
    Higher Secondary Education, KV JNU Percentage-87.6%
    2016 | New Delhi, India
    Worked as Mtech Teaching
    Assistant at IIIT Allahabad High School, KV JNU CGPA - 10.0
    2014 |New Delhi, India
    (2021-22)

    Former Summer Trainee at MTPS PROJECTS


    (07/2019)
    1) Design of a 32-bit RISC (MIPS32) pipelined processor
    using Verilog HDL
    SKILLS Understanding of R-Type, J-Type and I-Type Instruction Set
    Architecture(ISA)
    Verilog HDL Implementation of all five stages i.e Instruction Fetch,
    Instruction Decode, Execution, Memory Write and Write back
    System Verilog stage.
    Computer Architecture
    C Programming 2) Static timing Analysis and design of Master Slave D flip-
    flop in LT- Spice using PTM 180 nm CMOS Technology
    Static Timing Analysis
    LT-Spice Computed setup and hold time of the circuit and maximum
    operating frequency at which circuit can work
    CMOS Understood the concept of setup and hold time violation and
    methods to remove it
    Data Structures
    ASIC Design Flow 3) Verification methodology for a combinational and
    sequential circuit using System Verilog

    COURSES Used mailbox as an Inter Process Communication for data


    exchange between the classes
    Implemented all the five classes i.e. Generator, Driver, Monitor,
    Digital CMOS design from Scoreboard, Environment and used an interface to connect the
    NPTEL DUT with the testbench

    Computer Architecture from 4) Design of a 32 bit Booth’s Multiplier using Verilog


    NPTEL
    Understanding the Booth’s Algorithm, Data Path design and the
    Control Path design.
    Verilog HDL From NPTEL
    5) Low Power System Design using LT Spice
    Static Timing Analysis from
    Udemy Designing of 3-Input NAND gate by using 90nm PTM technology
    library file & compute the input pattern-dependent delay and
    leakage power (gate leakage, subthreshold leakage),compute
    C/C++ from Geeks for Geeks the net power consumption, and optimize the circuit in LTSpice.

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