Cable de Dos Puertos Transceverarbiter Tsb41ab2

TSB41AB2, TSB41AB2I
IEEE 13R4a-2000 TWO-PORT CABLE

TRANSCEIVER/ARBITER
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004
• Fully Supports Provisions of IEEE

1394-1995 Standard for High Performance • Fail-Safe Circuitry Senses Sudden Loss of
Serial Bus† and IEEE 1394a-2000 Power to the Device and Disables the Port
to Ensure That the Device Does Not Load
• Fully Interoperable With FireWire and TPBIAS of the Connected Device and
i.LINK Implementation of IEEE Std 1394 Blocks Any Leakage Path From the Port
• Fully Compliant With Back to the Device Power Plane
OpenHCI Requirements • Software Device Reset (SWR)
• Provides Two IEEE 1394a-2000 Fully • Industry Leading Low Power Consumption
Compliant Cable Ports at
100/200/400 Megabits Per Second • Ultralow-Power Sleep Mode
(Mbits/s) • Cable Power Presence Monitoring
• Full IEEE 1394a-2000 Support Includes: • Cable Ports Monitor Line Conditions for
Connection Debounce, Arbitrated Short Active Connection to Remote Node
Reset, Multispeed Concatenation, • Data Interface to Link Layer Controller
Arbitration Acceleration, Fly-By Through 2/4/8 Parallel Lines at 49.152 MHz
Concatenation, Port
• Interface to Link Layer Controller
Disable/Suspend/Resume
Supports Low-Cost TI Bus-Holder
• Register Bits Give Software Control of Isolation and Optional Annex J Electrical
Contender Bit, Power Class Bits, Link Isolation
Active Control Bit and IEEE 1394a- • Interoperable With Link Layer
2000 Features
Controllers Using 3.3 V
• IEEE 1394a-2000 Compliant Common
• Single 3.3-V Supply Operation
Mode Noise Filter on Incoming TPBIAS
• Low-Cost 24.576-MHz Crystal Provides
• Extended Resume Signaling for
Transmit, Receive Data at 100/200/400
Compatibility With Legacy DV Devices, Mbits/s, and Link-Layer Controller Clock at
and Terminal- and Register-Compatibility 49.152 MHz
With TSB41LV02A, Allow Direct
Isochronous Transmit to Legacy DV • Low-Cost High-Performance 64-Pin TQFP
Devices With Any Link Layer Even When Thermally Enhanced PowerPAD
Root Package Increases Thermal Performance
by up to 210%
• Power-Down Features to Conserve Energy
in Battery Powered Applications Include: • Meets Intel Mobile Power Guideline 2000
Automatic Device Power Down During
Suspend, Device Power-Down Terminal,
Link Interface Disable via LPS, and
Inactive Ports Powered Down
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
Intel is a trademark of Intel Corporation
FireWire is a trademark of Apple Computer, Incorporated. Other trademarks are the property of their
i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation. respective owners.
POST OFFICE BOX 655303  DALLAS, TEXAS 1

TSB41AB2, TSB41AB2I
IEEE 13R4a-2000 TWO-PORT
CABLE TRANSCEIVER/ARBITER
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright  2003 − 2004 Texas Instruments Incorporated
2 POST OFFICE BOX 655303  DALLAS, TEXAS

TSB41AB2, TSB41AB2I
IEEE 13R4a-2000 TWO-PORT CABLE
TRANSCEIVER/ARBITER
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004
description
The TSB41AB2 provides the digital and analog transceiver functions needed to implement a two-port node
in a cable-based IEEE 1394 network. The cable ports incorporate two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41AB2 is designed to
interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26,
TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A.
The TSB41AB2 requires only an external 24.576-MHz crystal as a reference. An external clock may be
provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which
generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide
the clock signals used to control transmission of the outbound encoded strobe and data information. A
49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used
for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD
terminal high, stops operation of the PLL.
The TSB41AB2 supports an optional isolation barrier between itself and its LLC. When the ISO input
terminal is tied high, the LLC interface outputs behave normally. When the ISO terminal is tied low, internal
differentiating logic is enabled, and the outputs are driven such that they can be coupled through a
capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in
IEEE 1394a-2000 (section 5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus
holder isolation, the ISO terminal on the PHY must be high.
Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel
paths (depending on the requested transmission speed) and are latched internally in the TSB41AB2 in
synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and
transmitted at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speed
respectively) as the outbound data-strobe information stream. During transmission, the encoded data
information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is
transmitted differentially on the TPA cable pair(s).
During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the
receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the
encoded strobe information is received on the TPB cable pair. The received data-strobe information is
decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two-,
four-, or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local
49.152-MHz system clock and sent to the associated LLC.
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine
the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of
this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In
addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the
presence of the remotely supplied twisted-pair bias voltage.
The TSB41AB2 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. This
bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active
connection. This bias voltage source must be stabilized by an external filter capacitor of 1 F. TPBIAS is
close to VDD when an active port is not connected to another node.
The line drivers in the TSB41AB2 operate in a high-impedance current mode, and are designed to work with
external 112- line-termination resistor networks in order to match the 110- cable impedance. One
network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-
connected 56- resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair-A
terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors
that is directly

TSB41AB2,
TSB41AB2I IEEE 13R4a-2000 TWO-
PORT CABLE
TRANSCEIVER/ARBITER
description (continued)
connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with
recommended values of 5 k and 220 pF. The values of the external line termination resistors are designed
to meet the standard specifications when connected in parallel with the internal receiver circuits. An external
resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal
operating currents. This current setting resistor has a value of 6.34 k 1.0%.
When the power supply of the TSB41AB2 is off while the twisted-pair cables are connected, the TSB41AB2
transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS
voltage at the other end of the cable. Fail-safe circuitry blocks any leakage path from the port back to the
device power plane.
When the TSB41AB2 is used with one of the ports not brought out to a connector, the twisted-pair terminals
of the unused port must be terminated for reliable operation. For each unused port, the TPB+ and TPB−
terminals should be tied together and then pulled to ground through a 1-k resistor, or the TPB+ and TPB−
terminals should be connected to the suggested termination network. The TPA+ and TPA− terminals of an
unused port may be left unconnected. The TPBIAS terminal should be connected to a 1-F capacitor to
ground or left floating.
The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal
operation, the TESTM terminal should be connected to VDD through a 1-k resistor, SE should be tied to
ground through a 1-k resistor, and SM should be connected directly to ground.
Four package terminals are used as inputs to set the default value for four configuration status bits in the
self-ID packet, and are tied high through a 1-k resistor or hardwired low as a function of the equipment
design. The PC0 – PC2 terminals are used to indicate the default power-class status for the node (the need
for power from the cable or the ability to supply power to the cable). See Table 9 for power-class encoding.
The C/LKON terminal is used as an input to indicate that the node is a contender for either isochronous
resource manager (IRM) or bus manager (BM).
The TSB41AB2 supports suspend/resume as defined in IEEE 1394a-2000 specification. The suspend
mechanism allows pairs of directly-connected ports to be placed into a low-power state (suspended state)
while maintaining a port-to-port connection between bus segments. While in the suspended state, a port is
unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of
detecting connection status changes and detecting incoming TPBIAS. When ports of the TSB41AB2 are
suspended, all circuits except the band gap reference generator and bias detection circuits are powered
down, resulting in significant power savings. For additional details of suspend/resume operation see IEEE
1394a-2000. The use of suspend/resume is recommended for new designs.
The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is
asserted high), during reset (when the RESET input terminal is asserted low), when no active cable is
connected to the port, or when controlled by the internal arbitration logic. The TPBIAS output is disabled
during power down, during reset, or when the port is disabled as commanded by the LLC.
The cable-not-active (CNA) output terminal is asserted high when there are no twisted-pair cable ports
receiving incoming bias (that is, they are either disconnected or suspended), and can be used along with LPS
to determine when to power down the TSB41AB2. The CNA output is not debounced. When the PD terminal
is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a
pulldown is activated on the RESET terminal to force a reset of the TSB41AB2 internal logic.
The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the
node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the
Application Information section) to indicate the active/power status of the LLC. The LPS signal is also used to
reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LLC interface is controlled solely by
the LPS input regardless of the state of the LCtrl bit).

TSB41AB2, TSB41AB2I
description (continued)
The LPS input is considered inactive if it remains low for more than 2.6 s and is considered active
otherwise. When the TSB41AB2 detects that LPS is inactive, it places the PHY-LLC interface into a low-
power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is
ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 s, the
PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive.
The PHY-LLC interface is also held in the disabled state during hardware reset. The TSB41AB2 continues
the necessary repeater functions required for normal network operation regardless of the state of the PHY-
LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the
PHY initializes the interface and returns it to normal operation.
When the PHY-LLC interface is in the low-power disabled state, the TSB41AB2 automatically enters a low-
power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB41AB2 disables its internal clock generators and also disables various voltage and current reference
circuits depending on the state of the port (some reference circuitry must remain active in order to detect
new cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption
(the ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port
interrupt enable bit cleared. The TSB41AB2 exits the low-power mode when the LPS input is asserted high
or when a port event occurs. This requires that the TSB41AB2 become active in order to respond to the
event or to notify the LLC of the event (for example, incoming bias is detected on a suspended port, a
disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.).
The SYSCLK output becomes active (and the PHY-LLC interface is initialized and become operative) within
7.3 ms after LPS is asserted high when the TSB41AB2 is in the low-power mode.
The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the
C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output
when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS
input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on
PHY packet addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the
C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also
deasserts the C/LKON output when a bus reset occurs unless a PHY interrupt condition exists which would
otherwise cause C/LKON to be active.

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
PAP package terminal diagram
PAP PACKAGE
(TOP VIEW)
TPA1+
TPA1−
TPB1+
TPB1−
AGND
TPBIA
AGND
TPBIA
AVDD
S1
S0
R
R
1
0
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
AGND 49 32 AGND
AGND 50 31 AVDD
AVDD 51 30 AVDD
AVDD 52 29 SM
RESET 53 28 SE
FILTER0 54 27 TESTM
FILTER1 55 26 DVDD
PLLVDD 56 25 DVDD
TSB41AB2
PLLGND 57 24 CPS
PLLGND 58 23 ISO
XI 59 22 PC2
XO 60 21 PC1
DVDD 61 20 PC0
DVDD 62 19 C/LKON
DGND 63 18 DGND
DGND 64 17 DGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D
LR
EQ
SYSC
LK
CNA
CTL0
CTL1
D
0
NOTE: Pin 16 (NC) could be tied to VDD for backward compatibility with the TSB41LV02A device.

TSB41AB2, TSB41AB2I
functional block diagram
CPS
LPS Received Data Decoder/Retimer
ISO
CNA
SYSCLK
LREQ TPA0+
CTL0 Link Interface I/O TPA0−
CTL1
D0
D1
D2
D3 Cable Port 0
D4 TPB0+
D5 Arbitration and Control State Machine Logic
TPB0−
D6
D7
PC0
PC1
TPA1+
PC2
C/LKON TPA1−
Cable Port 1
TPB1+
TPB1−
R0 Bias Voltage and

R1 Current Generator
TPBIAS0
TPBIAS1
Crystal Oscillator, PLL System, and Clock Generator

XI
Transmit Data Encoder XO
PD FILTER0
RESET FILTER1

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
Terminal Functions
TERMINAL
TYPE I/O DESCRIPTION
NAME NO.
AGND 32, 33, 39, Supply − Analog circuit ground terminals. These terminals should be tied together to the low
48, 49, 50 impedance circuit board ground plane.
AVDD 30, 31, 42, Supply − Analog circuit power terminals. A combination of high-frequency decoupling capacitors near
51, 52 each terminal are suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10-F
filtering capacitors are also recommended. These supply terminals are separated from
PLLVDD and
DVDD inside the device to provide noise isolation. They should be tied at a low-impedance
point
on the circuit board.
C/LKON 19 CMOS I/O Bus manager contender programming input and link-on output. On hardware reset, this
terminal is used to set the default value of the contender status indicated during self-ID.
Programming is done by tying the terminal through a 10-k resistor to a high (contender) or
low (not contender). The resistor allows the link-on output to override the input. However, it is
recommended that this terminal should be programmed low, and that the contender status be
set via the C register bit.
If the TSB41AB2 is used with an LLC that has a dedicated terminal for monitoring LKON and
also setting the contender status, then a 1-k series resistor should be placed on the LKON
line between the PHY and LLC to prevent bus contention.
Following hardware reset, this terminal is the link-on output, which is used to notify the LLC to
power up and become active. The link-on output is a square-wave signal with a period of
approximately 163 ns (8 SYSCLK cycles) when active. The link-on output is otherwise driven
low, except during hardware reset when it is high-impedance.
The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit cleared) and
when:
a) the PHY receives a link-on PHY packet addressed to this node, or
b) the PEI (port-event interrupt) register bit is 1, or
c) any of the CTOI (configuration-time-out interrupt), CPSI
(cable-power-status interrupt), or STOI (state-time-out interrupt)
register bits are 1 and the RPIE (resuming-port interrupt
enable) register bit is also 1.
Once activated, the link-on output continues active until the LLC becomes active (both LPS
active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus reset
occurs unless the link-on output would otherwise be active because one of the interrupt bits is
set (that is, the link-on output is active due solely to the reception of a link-on PHY packet).
NOTE: If an interrupt condition exists which would otherwise cause the link-on output to be
activated if the LLC were inactive, the link-on output is activated when the LLC subsequently
becomes inactive.
CNA 3 CMOS O Cable-not-active output. This terminal is asserted high when there are no ports receiving
incoming bias voltage. CNA is not valid at initial power up, until a device hard reset is
performed.
CPS 24 CMOS I Cable power status input. This terminal is normally connected to cable power through a 400-
k resistor. This circuit drives an internal comparator that is used to detect the presence of
cable power. This terminal should be tied directly to DGND through a 1-k resistor if
application does
not require it to be used.
CTL0 4 CMOS I/O Control I/Os. These bidirectional signals control communication between the TSB41AB2 and
CTL1 5 the LLC. Bus holders are built into these terminals.
D0 6 CMOS I/O Data I/Os. These are bidirectional data signals between the TSB41AB2 and the LLC. Bus
D1 7 holders are built into these terminals.
D2 8
D3 9
D4 10
D5 11
D6 12
D7 13

TSB41AB2, TSB41AB2I
DGND 17, 18, 63, Supply − Digital circuit ground terminals. These terminals should be tied together to the low-impedance
64 circuit board ground plane.

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
Terminal Functions (Continued)
TERMINAL
NAME NO.
DVDD 25, 26, 61, Supply − Digital circuit power terminals. A combination of high frequency decoupling capacitors near
62 each terminal is suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10-F
filtering capacitors are also recommended. These supply terminals are separated from PLLVDD
and AVDD
inside the device to provide noise isolation. They should be tied at a low-impedance point on
the
circuit board.
FILTER0 54 CMOS I/O PLL filter terminals. These terminals are connected to an external capacitor to form a lag-lead
FILTER1 55 filter required for stable operation of the internal frequency multiplier PLL running from the
crystal oscillator. A 0.1-F 10% capacitor is the only external component required to complete
this filter.
ISO 23 CMOS I Link interface isolation control input. This terminal controls the operation of output
differentiation logic on the CTL and D terminals. If an optional Annex J type isolation barrier is
implemented between the TSB41AB2 and LLC, the ISO terminal should be tied low to enable
the differentiation logic. If no isolation barrier is implemented (direct connection), or TI bus
holder isolation is implemented, the ISO terminal should be tied high through a pullup to
disable the differentiation logic. For additional information refer to TI application note Galvanic
Isolation of the IEEE 1394−1995 Serial Bus, literature number SLLA011.
LPS 15 CMOS I Link power status input. This terminal is used to monitor the active/power status of the link
layer controller and to control the state of the PHY−LLC interface. This terminal should be
connected through a 10-k resistor either to the VDD supplying the LLC, or to a pulsed output
which is active
when the LLC is powered (see Figure 8). A pulsed signal should be used when an isolation
barrier
exists between the LLC and PHY (see Figure 9).
The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6 s (128
SYSCLK cycles), and is considered active otherwise (that is, asserted steady high or an
oscillating signal with a low time less than 2.6 s). The LPS input must be high for at least 21
ns to assure that a high is observed by the PHY.
When the TSB41AB2 detects that LPS is inactive, it places the PHY-LLC interface into a low-
power reset state. In the reset state, the CTL and D outputs are held in the logic zero state
and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input
remains low for more than 26 s (1280 SYSCLK cycles), the PHY-LLC interface is put into a
low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC
interface is placed into the disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the LCtrl register bit is
set to 1, and is considered inactive if either the LPS input is inactive or the LCtrl register bit is
cleared to 0.
LREQ 1 CMOS I LLC request input. The LLC uses this input to initiate a service request to the TSB41AB2. Bus
holder is built into this terminal.
PC0 20 CMOS I Power class programming inputs. On hardware reset, these inputs set the default value of the
PC1 21 power class indicated during self-ID. Programming is done by tying these terminals high or
PC2 22 low. See Table 9 for encoding.
PD 14 CMOS I Power-down input. A high on this terminal turns off all internal circuitry except the cable-active
monitor circuits, which control the CNA output. Asserting the PD input high also activates an
internal pulldown on the RESET terminal so as to force a reset of the internal control logic.
(PD is provided for legacy compatibility and is not recommended power management in place
of IEEE 1394a-2000 suspend/resume LPS and C/LKON features.)
PLLGND 57, 58 Supply − PLL circuit ground terminals. These terminals should be tied together to the low-impedance
circuit board ground plane.
PLLVDD 56 Supply − PLL circuit power terminals. A combination of high-frequency decoupling capacitors near
each terminal is suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10-F
filtering capacitors are also recommended. This supply terminal is separated from DVDD and
AVDD inside
the device to provide noise isolation. It should be tied at a low-impedance point on the circuit
board.

TSB41AB2, TSB41AB2I
Terminal Functions (Continued)
TERMINAL
NAME NO.
R0 40 Bias − Current setting resistor terminals. These terminals are connected through an external resistor
R1 41 to set the internal operating currents and cable driver output currents. A resistance of 6.34 k
1.0% is required to meet the IEEE Std 1394-1995 output voltage limits.
RESET 53 CMOS I Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup
resistor
to VDD is provided so only an external delay capacitor is required for proper power-up
operation (see power-up reset in the Application Information section). The RESET
terminal also
incorporates an internal pulldown which is activated when the PD input is asserted high. This
input is otherwise a standard logic input, and may also be driven by an open-drain type driver.
SE 28 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB2. For normal use
this terminal may be tied to GND through a 1-k pulldown resistor or it may be tied to GND
directly.
SM 29 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB2. For normal use
this terminal should be tied to GND.
SYSCLK 2 CMOS O System clock output. Provides a 49.152-MHz clock signal, synchronized with data transfers,
to the LLC.
TESTM 27 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB2. For normal use
this terminal should be tied to VDD through a 1-k resistor.
TPA0+ 37 Cable I/O Twisted-pair cable A differential signal terminals. Board traces from each pair of positive and
TPA1+ 46 negative differential signal terminals should be kept matched and as short as possible to the
TPA0− 36 Cable I/O external load resistors and to the cable connector. For an unused port, TPA+ and TPA− can
TPA1− 45 be left open.
TPB0+ 35 Cable I/O Twisted-pair cable B differential signal terminals. Board traces from each pair of positive and
TPB1+ 44 negative differential signal terminals should be kept matched and as short as possible to the
external load resistors and to the cable connector. For each unused port, TPB+ and TPB−
TPB0− 34 Cable I/O
terminals can be tied together and then connected to ground through a 1-k resistor or the
TPB1− 43
TPB+ and TPB− terminals can be connected to the suggested termination network.
TPBIAS0 38 Cable I/O Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper
TPBIAS1 47 operation of the twisted-pair cable drivers and receivers, and for signaling to the remote
nodes that there is an active cable connection. Each of these terminals, except for an unused
port, must be decoupled with a 1-F capacitor to ground. For the unused port, this terminal
can be left unconnected.
XI 59 Crystal − Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant
XO 60 fundamental mode crystal. The optimum values for the external shunt capacitors are
dependent on the specifications of the crystal used (see crystal selection in the Application
Information section). When an external clock source is used, XI should be the input and XO
should be left open, and
the clock must be supplied before the device is taken out of reset.
NOTE: It is strongly recommended that signals tied to VDD use a 1-k resistor (minimum). Tying signals directly to VCC may result in ESD
failures.
Signals tied to ground may be tied directly.

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VDD (see Note 1)......................................................................................−0.3 V to 4 V
Input voltage range, VI................................................................................................................ −0.5 V to VDD + 0.5 V
Output voltage range at any output, VO.................................................................................... −0.5 V to VDD + 0.5V
Continuous total power dissipation......................................................................See Dissipation Rating Table
Operating free air temperature, TA, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C
TSB41AB2
TSB41AB2I.........................................................................−40C to 85C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to 150C
......
Lead temperature 1,6 mm (1/16 inch) from case for 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
seconds
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground.
DISSIPATION RATING TABLE

TA  25C DERATING FACTOR‡ TA = 70C TA = 85C
PACKAGE POWER RATING POWER RATING POWER RATING
ABOVE TA = 25C
PAP§ 4.78 W 38 mW/°C 3.06 W 2.5 W
PAP¶ 2.13 W 17 mW/°C 1.36 W 1.11 W
PAP# 2.08 W 16 mW/°C 1.33 W 1.1 W
‡ This is the inverse of the traditional junction-to-ambient thermal resistance (R
JA).
§ 1 oz. trace and copper pad with solder.
¶ 1 oz. trace and copper pad without solder.
# Standard JEDEC low-K board.
For more information, refer to TI technical brief PowerPAD  Thermally Enhanced Package, TI literature
number SLMA002.

TSB41AB2, TSB41AB2I
recommended operating conditions
MIN TYP† MAX UNIT
Source power node 3 3.3 3.6
Supply voltage, VDD TSB41AB2 2.7‡ 3 3.6 V
Nonsource power node
TSB41AB2I 3‡ 3.3 3.6
LREQ, CTL0, CTL1, D0 −D7 2.6 V
High-level input voltage, VIH C/LKON, PC0, PC1, PC2, ISO, PD 0.7 VDD V
RESET 0.6 VDD V
LREQ, CTL0, CTL1, D0 −D7 1.2 V
Low-level input voltage, VIL C/LKON, PC0, PC1, PC2, ISO, PD 0.2 VDD V
RESET 0.3 VDD V
Output current, IO TPBIAS outputs − 5.6 1.3 mA
TA = 70C 82.2
RJA = 26.10C/W
TA = 85C 97.2
Maximum junction temperature, TA = 70C 97.4
TJ (see RJA values listed in RJA = 58.57C/W C
TA = 85C 112.3
thermal characteristics table)
TA = 70C 98.2
RJA = 60.08C/W
TA = 85C 113.1
Cable inputs, during data reception 118 260
Differential input voltage, VID mV
Cable inputs, during arbitration 168 265
TPB cable inputs, source power node 0.4706 2.515
Common-mode input voltage, VIC V
TPB cable inputs, nonsource power node 0.4706 2.015‡
Power-up reset time, t(pu) RESET input 2 ms
TPA, TPB cable inputs, S100 operation  1.08
Receive input jitter TPA, TPB cable inputs, S200 operation  0.5 ns
TPA, TPB cable inputs, S400 operation  0.315
Between TPA and TPB cable inputs, S100 operation  0.8
Receive input skew Between TPA and TPB cable inputs, S200 operation  0.55 ns
Between TPA and TPB cable inputs, S400 operation  0.5
† All typical values are at VDD = 3.3 V and TA = 25C.
‡ For a node that does not source power; see Section 4.2.2.2 in IEEE 1394a-2000.

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
electrical characteristics over recommended ranges of operating conditions (unless otherwise
noted)
driver
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOD Differential output voltage 56 , see Figure 1 172 265 mV
Drivers enabled, speed
IDIFF Driver difference current, TPA+, TPA−, TPB+, TPB− − 1.05† 1.05† mA
signaling off
ISP200 Common mode speed signaling current, TPB+, TPB− S200 speed signaling enabled − 4.84‡ − 2.53‡ mA
ISP400 Common mode speed signaling current, TPB+, TPB− S400 speed signaling enabled − 12.4‡ − 8.1‡ mA
VOFF Off state differential voltage Drivers disabled, See Figure 1 20 mV
† Limits defined as algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− algebraic sum of driver currents.
‡ Limits defined as absolute limit of each of TPB+ and TPB− driver currents
receiver
4 7 k
zid Differential impedance Drivers disabled
4 pF
20 k
zic Common-mode impedance Drivers disabled
24 pF
VTH−R Receiver input threshold voltage Drivers disabled −30 30 mV
VTH−CB Cable bias detect threshold, TPB cable inputs Drivers disabled 0.6 1 V
VTH+ Positive arbitration comparator threshold voltage Drivers disabled 89 168 mV
Negative arbitration comparator threshold
VTH− Drivers disabled − 168 −89 mV
voltage
TPBIAS−TPA common-mode
VTH−SP200 Speed signal threshold 49 131 mV
voltage, drivers disabled
TPBIAS−TPA common-mode
VTH−SP400 Speed signal threshold 314 396 mV
voltage, drivers disabled

TSB41AB2, TSB41AB2I
electrical characteristics over recommended ranges of operating conditions (unless otherwise
noted) (continued)
device
See Note 2 71
IDD Supply current See Note 3 69 mA
See Note 4 59
VDD = 3.3 V, TA = 25C,
IDD(ULP) Supply current, ultralow-power mode Port disabled, PD = 0 V, 150 A
LPS = 0 V
PD = VDD, VDD = 3.3
IDD(PD) Supply current, power-down mode 150 A
V, TA = 25C
V(TH) Power status threshold, CPS input† 400-k resistor† 4.7 7.5 V
VDD = 2.7 V, IOH = − 4 mA 2.2
High-level output voltage, CTL0, CTL1,
VOH VDD = 3 V to 3.6 V
D0 − D7, CNA, C/LKON, SYSCLK 2.8
V, IOH = − 4 mA
outputs
Low-level output voltage, CTL0, CTL1,
VOL IOL = 4 mA 0.4 V
D0 − D7, CNA, C/LKON, SYSCLK
outputs
High-level Annex J output voltage, CTL0, Annex J: IOH = − 9 mA,
VOH(AJ) VDD−0.4 V
CTL1, D0 − D7, C/LKON, SYSCLK outputs ISO = 0 V, VDD  3 V
Low-level Annex J output voltage, CTL0, Annex J: IOL = 9 mA,
VOL(AJ) 0.4 V
CTL1, D0−D7, C/LKON, SYSCLK ISO = 0 V, VDD  3 V
outputs
Positive peak bus holder current, D0 − D7, ISO = 3.6 V, VDD = 3.6 V,
I(BH+) 0.05 1 mA
CTL0 − CTL1, LREQ VI = 0 V to VDD
Negative peak bus holder current, ISO = 3.6 V, VDD = 3.6 V,
I(BH−) −1.0 −0.05 mA
D0 − D7, CTL0 − CTL1, LREQ VI = 0 V to VDD
Input current, LREQ, LPS, PD, TESTM,
II ISO = 0 V, VDD = 3.6 V 5 A
SM, PC0 – PC2 inputs
Off-state output current, CTL0, CTL1,
IOZ VO = VDD or 0 V 5 A
D0 – D7, C/LKON I/Os
I(IRST) Pullup current, RESET input VI = 1.5 V or 0 V −90 −20 A
I(SE_Pd) Pulldown current, SE input VI = VDD/2 or VDD 5 50 A
Positive input threshold voltage, LREQ,
ISO = 0 V, VDD = 3V to 3.6 V VDD/2+0.3 VDD/2+0.9
CTL0, CTL1, D0 – D7 inputs
VIT+ V
Positive input threshold voltage, LPS ISO = 0 V, VDD = 3 V to 3.6 V
VREF+1
inputs Vref = 0.42 VDD
Negative input threshold voltage, LREQ,
ISO= 0 V, VDD = 3 V to 3.6 V VDD/2−0.9 VDD/2−0.3
CTL0, CTL1, D0 – D7 inputs
VIT − V
Negative input threshold voltage, LPS ISO= 0 V, Vref = 0.42
Vref+0.2
inputs VDD, VDD = 3 V to 3.6 V
VO TPBIAS output voltage‡ At rated IO current 1.665 2.015 V
† Measured at cable power side of resistor
‡ TPBIAS is close to VDD when the port is not connected.
NOTES: 2. Transmit maximum packet (all ports transmitting maximum size isochronous packet – 4096 bytes, sent on every isochronous
interval, S400, data value of CCCCCCCCh), VDD = 3.3 V, TA = 25C.
3. Repeat typical packet (receiving on one port DV packets on every isochronous interval, S100, and transmitting on the other port),
VDD = 3.3 V, TA = 25C.
4. Idle (one port receiving and one port transmitting cycle starts), VDD = 3.3 V, TA = 25C.

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
thermal characteristics
PARAMETER TEST CONDITIONS† MIN TYP MAX UNIT
RJA Junction-to-ambient thermal resistance Board mounted, no air flow, high conductivity TI- 26
recommended test board, chip soldered or greased  C/W
RJC Junction-to-case-thermal resistance to thermal land with 1 oz. copper 5.9
Board mounted, no air flow, high conductivity TI- 58.57
RJA Junction-to-ambient thermal resistance
recommended test board with thermal land, but no
 C/W
solder or grease thermal connection to thermal land
RJC Junction-to-case thermal resistance 5.9
with 1 oz. copper
RJA Junction-to-ambient thermal resistance Board mounted, no air flow, low conductivity JEDEC 60.08
 C/W
RJC Junction-to-case thermal resistance test board with 1 oz. copper 5.9
† Use of thermally enhanced PowerPad PAP package is assumed in all three test conditions.
switching characteristics
Jitter, transmit Between TPA and TPB  0.15 ns
Skew, transmit Between TPA and TPB  0.1 ns
th Hold time, CTL0, CTL1, D0 – D7, LREQ after SYSCLK 50% to 50%, See Figure 2 2 ns
tsu Setup time, CTL0, CTL1, D0 – D7, LREQ to SYSCLK 50% to 50%, See Figure 2 5 ns
td Delay time, SYSCLK to CTL0, CTL1, D0 – D7 50% to 50%, See Figure 3 2‡ ns
tr TP differential rise time, transmit 10% to 90%, at 1394 connector 0.5 1.2 ns
tf TP differential fall time, transmit 90% to 10%, at 1394 connector 0.5 1.2 ns
‡ Test Conditions: 3.3 VCC, TA = 25C

TSB41AB2, TSB41AB2I
PARAMETER MEASUREMENT INFORMATION
TPA+
TPB+
56 
TPA−
TPB−
Figure 1. Test Load Diagram
SYSCLK
tsu th
Dx, CTLx,
LREQ
Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms
SYSCLK
td
Dx, CTLx
Figure 3. Dx and CTLx Output Delay Relative to SYSCLK Waveforms

TSB41AB2, TSB41AB2I
APPLICATION
component connection
Details regarding connection of components to the various terminals of the TSB41AB2 are discussed
primarily in entries for each terminal in the terminal functions table. Figure 4 is a diagrammatic view showing
the connections for all required external components.
1 F
6.34 k
F F 1 % TPBIAS
VDD
TP Cables TP Cables
Interface Interface
1 F Connection † Connection †
TPBIAS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
+
AG
ND
AS1
TPBI
TPA1
TP
TP
B1
A1
B0−
TPBIA
S0
TP
A0
−
TP
49
AGND 32
AGND
50
AGND 0.001 F
0.1 0.001 0.001 31 0.1 F
51 AVDD
F F F AVDD 0.01 F
30
VDD 52
AVDD VDD
AVDD
SM 29
0.1 F
53
RESET 1 k (Optional)
28
SE
54
FILTER0 27 1 k VDD
TESTM
0.1 F 55
FILTER1 0.001 0.001 0.1
26 F F F
56
PLLVDD DVDD
VDD DVDD
25
0.1 0.001 F 400 k
57
PLLGND 24
F CPS Cable Power DGND
58
PLLGND
23
ISO ISO
22
59 XI PC2
24.576 MHz 21 Power-Class
12 60 XO PC1
pF Programming
12 61 DVDD 20
VDD PC0 LKON
62 19
p
0.1 DVDD C/LKON Bus Manager
F 0.001 F 63 10 k
DGND 18
DGND
64 17
DGND DGND
LREQ
SYSC
CTL0
CTL1
CNA
LK
D
D
D
P
L
1
7
1 2 3 4
5 6 7 8 9 10 11 12 13 14 15 16
‡
CNA
POWER
† See Figure 5, Figure 6, and Figure 7.

‡ See Figure 8 and Figure 9.
Figure 4. External Component Connections

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
APPLICATION
Outer Shield Termination
TSB41AB2
CPS 400 k
1 F Cable Power Pair

TPBIAS
56 ‡ 56 ‡
TPA+ TPA−
Cable Pair A
Cable Port
TPB+ Cable Pair B
TPB−
56 ‡ 56 ‡
220 pF† 5 k
† The IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 220-pF capacitor is recommended.
‡  0.5% to meet 1394−1995 specification.
Figure 5. TP Cable Connections
Outer Cable Shield
1 M
0.01 F 0.001 F
Chassis GND
Figure 6. Compliant DC Isolated Outer Shield Termination

TSB41AB2, TSB41AB2I
APPLICATION
Outer Shield Termination
Chassis GND
Figure 7. Nonisolated Outer Shield Termination
10 k
Link Power LPS
LPS
Square Wave Input
10 k
Figure 8. Nonisolated Circuit Connection Variations for LPS
PHY VDD
13.7 k
LPS
Square Wave Signal
0.033 F
10 k
PHY GND
NOTE: As long as the resistance ratio is maintained between 1.61:1 and

1.33:1, any values of resistors may be used.
Figure 9. Isolated Circuit Connection for LPS
crystal selection
The TSB41AB2 and other TI PHY devices are designed to use an external 24.576-MHz crystal connected
between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in
turn drives a PLL circuit that generates the various clocks required for transmission and resynchronization
of data at the S100 through S400 media data rates.
A variation of less than  100 ppm from nominal for the media data rates is required by IEEE Std 1394.
Adjacent PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks,
and PHYs must be able to compensate for this difference over the maximum packet length. Larger clock
variations may cause resynchronization overflows or underflows, resulting in corrupted packet data.
For the TSB41AB2, the SYSCLK output may be used to measure the frequency accuracy and stability of
the internal oscillator and PLL from which it is derived. The frequency of the SYSCLK output must be
within
 100 ppm of the nominal frequency of 49.152 MHz.

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
APPLICATION
crystal selection (continued)

The following are some typical specifications for crystals used with the physical layers from TI in order to achieve
the required frequency accuracy and stability:
• Crystal mode of operation: Fundamental
• Frequency tolerance at 25C: Total frequency variation for the complete circuit is 100 ppm. A crystal with
 30-ppm frequency tolerance is recommended for adequate margin.
• Frequency stability (over temperature and age): A crystal with 30-ppm frequency stability is
recommended for adequate margin.
NOTE: The total frequency variation must be kept below  100 ppm from nominal with some allowance for
error introduced by board and device variations. Trade-offs between frequency tolerance and stability
may be made as long as the total frequency variation is less than  100 ppm. For example, the
frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be
specified at 30 ppm to give a total of 80 ppm possible variation due to the crystal alone. Crystal aging also
contributes to the frequency variation.
• Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent
upon the load capacitance specified for the crystal. Total load capacitance (CL) is a function of not only
the discrete load capacitors, but also board layout and circuit. It may be necessary to intermittently
select discrete load capacitors until the SYSCLK output is within specification. It is recommended that
load capacitors with a maximum of  5% tolerance be used.
As an example, for the OHCI + 41LV02 + evaluation module (EVM), which uses a crystal specified for 12-
pF loading, load capacitors (C9 and C10 in Figure 10) of 16 pF each were appropriate for the layout of that
particular board. The load specified for the crystal includes the load capacitors (C9, C10), the loading of the
PHY terminals [C(PHY)] and the loading of the board itself [C (BD)]. The value of C(PHY) is typically about 1
pF, and C(BD) is typically 0.8 pF per centimeter of board etch; a typical board can have 3 pF to 6 pF or more.
The load capacitors C9 and C10 combine as capacitors in series so that the total load capacitance is:
(C9 × C10 ) (1)

C =
L [(C9 + C10) ] +C
(PHY)
+C
(BD)
C9
XI
24.576 MHz X1 C(PHY) + C(BD)

XO
C10
Figure 10. Load Capacitance for the TSB41AB2 PHY

TSB41AB2, TSB41AB2I
APPLICATION
crystal selection (continued)

The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency,
minimizing noise introduced into the PHY phase-lock loop, and minimizing any emissions from the circuit.
The crystal and two load capacitors should be considered as a unit during layout. The crystal and load
capacitors should be placed as close as possible to one another while minimizing the loop area created by
the combination of the three components. Varying the size of the capacitors may help in this. Minimizing the
loop area minimizes the effect of the resonant current (Is) that flows in this resonant circuit. This layout unit
(crystal and load capacitors) should then be placed as close as possible to the PHY XI and XO terminals to
minimize trace lengths. Figure 11 depicts a layout that meets these guidelines.
C C10
X1
Figure 11. Recommended Crystal and Capacitor Layout
It is strongly recommended that part of the verification process for the design be to measure the frequency
of the SYSCLK output of the PHY. This should be done with a frequency counter with an accuracy of six
digits or better. If the SYSCLK frequency is more than the crystal tolerance from 49.152 MHz, the load
capacitance of the crystal may be varied to improve frequency accuracy. If the frequency is too high, add
more load capacitance; if the frequency is too low, decrease load capacitance. Typically, changes should be
done to both load capacitors (C9 and C10 above) at the same time, and both should be of the same value.
Additional design details and requirements may be provided by the crystal vendor. For more information,
see Selection and Specification of Crystals for Texas Instruments IEEE 1394 Physical Layers, TI literature
number SLLA051.
EMI guidelines
For electromagnetic interference (EMI) guidelines and recommendations, send a request via email
to: 1394-EMI@list.ti.com
designing with the PowerPAD package

The TSB41AB2 is housed in a high performance, thermally enhanced, 64-terminal PAP PowerPAD
package. Use of the PowerPAD package does not require any special considerations except to note that the
PowerPAD, which is an exposed metallic pad on the bottom of the device, is a thermal and electrical
conductor. This exposed pad is connected inside the package to the substrate of the silicon die, it is not
connected to any terminal of the package. Therefore, if not implementing PowerPAD PCB features, the use of
solder masks (or other assembly techniques) may be required to prevent any inadvertent shorting by the
exposed PowerPAD of connection etches or vias under the package. The recommended option, however, is
to not run any etches or signal vias under the device, but to have only a grounded thermal land as
explained below. Although the actual size of the exposed die pad may vary, the minimum size required for
the keep-out area of the 64-terminal PAP PowerPAD package is 8 mm  8 mm.
It is recommended that there be a thermal land, which is an area of solder-tinned-copper (see Figure 12),
underneath the PowerPAD package. The thermal land varies in size depending on the PowerPAD package
being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the
thermal land may or may not contain numerous thermal vias depending on PCB construction.

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
APPLICATION INFORMATION
designing with the PowerPAD package (continued)
Other requirements for thermal lands and thermal vias are detailed in PowerPAD Thermally Enhanced
Package Technical Brief, TI literature number SLMA002, available via the TI Web pages beginning at URL
http://www.ti.com.
Figure 12. Example of a Thermal Land for the TSB41AB2PAP PHY

For the TSB41AB2, this thermal land should be grounded to the low impedance ground plane of the device.
This improves not only thermal performance but also the electrical grounding of the device. It is also
recommended that the device ground terminal landing pads be connected directly to the grounded thermal
land. The land size should be as large as possible without shorting device signal terminals. The thermal
land may be soldered to the exposed PowerPAD using standard reflow soldering techniques.
While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it
is recommended that the thermal land be connected to the low-impedance ground plane for the device.
More information may be obtained from the TI application report Recommendations for PHY Layout, TI
literature number SLLA020.
internal register configuration
There are 16 accessible internal registers in the TSB41AB2. The configuration of the registers at addresses
0h through 7h (the base registers) is fixed, while the configuration of the registers at addresses 8h through
Fh (the paged registers) is dependent upon which one of eight pages, numbered 0 through 7, is currently
selected. The selected page is set in base register 7.
The configuration of the base registers is shown in Table 1, and corresponding field descriptions are given
in Table 2. The base register field definitions are unaffected by the selected page number.
A reserved register or register field (marked as Reserved or Rsvd in register configuration tables) is read as
0, but is subject to future usage. All registers in pages 2 through 6 are reserved.
Table 1. Base Register Configuration
ADDRESS BIT POSITION
0 1 2 3 4 5 6 7
0000 Physical ID R CPS
0001 RHB IBR Gap_Count
0010 Extended (111b) Num_Ports (00010b)
0011 PHY_Speed (010b) Rsvd Delay (0000b)
0100 LCtrl C Jitter (000b) Pwr_Class
0101 RPIE ISBR CTOI CPSI STOI PEI EAA EMC
0110 Reserved
0111 Page_Select Rsvd Port_Select

TSB41AB2, TSB41AB2I
APPLICATION
Table 2. Base Register Field Descriptions

FIELD SIZE TYPE DESCRIPTION
Physical ID 6 Rd This field contains the physical address ID of this node determined during self-ID. The physical ID is
invalid after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status
transfer.
R 1 Rd Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is set to
1 during tree-ID if this node becomes root.
CPS 1 Rd Cable-power status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally
tied to serial bus cable power through a 400-k resistor. A 0 in this bit indicates that the cable power
voltage has dropped below its threshold for assured reliable operation.
RHB 1 Rd/Wr Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB
bit is reset to 0 by hardware reset and is unaffected by bus reset.
IBR 1 Rd/Wr Initiate bus-reset. This bit instructs the PHY to initiate a long (166 s) bus reset at the next opportunity.
Any receive or transmit operation in progress when this bit is set completes before the bus reset is
initiated. The IBR bit is reset to 0 by hardware reset or bus reset.
Gap_Count 6 Rd/Wr Arbitration gap count. This value is used to set the subaction (fair) gap, arb-reset gap, and arb-delay
times. The gap count may be set either by a write to this register or by reception or transmission of a
PHY_CONFIG packet. The gap count is set to 3Fh by hardware reset or after two consecutive bus
resets without an intervening write to the gap count register (either by a write to the PHY register or by a
PHY_CONFIG packet).
Extended 3 Rd Extended register definition. For the TSB41AB2 this field is 111b, indicating that the extended register
set is implemented.
Num_Ports 5 Rd Number of ports. This field indicates the number of ports implemented in the PHY. For the TSB41AB2
this field is 2.
PHY_Speed 3 Rd PHY speed capability. For the TSB441AB2 PHY this field is 010b, indicating S400 speed capability.
Delay 4 Rd PHY repeater data delay. This field indicates the worst case repeater data delay of the PHY, expressed
as 144+(delay  20) ns. For the TSB41AB2 this field is 0.
LCtrl 1 Rd/Wr Link-active status control. This bit is used to control the active status of the LLC as indicated during self-
ID. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID
packet. The LLC is considered active only if both the LPS input is active and the LCtrl bit is set.
The LCtrl bit provides a software controllable means to indicate the LLC active status in lieu of using the
LPS input. The LCtrl bit is set to 1 by hardware reset and is unaffected by bus reset.
NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state
of the LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active,
then received packets and status information continues to be presented on the interface, and any
requests indicated on the LREQ input is processed, even if the LCtrl bit is cleared to 0.
C 1 Rd/Wr Contender status. This bit indicates that this node is a contender for the bus or isochronous resource
manager. This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to the state
specified by the C/LKON input terminal upon hardware reset and is unaffected by bus reset.
Jitter 3 Rd PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest
repeater data delay, expressed as (JITTER+1)  20 ns. For the TSB41AB2 this field is 0.
Pwr_Class 3 Rd/Wr Node power class. This field indicates this node’s power consumption and source characteristics, and is
replicated in the pwr field (bits 21– 23) of the self-ID packet. This field is set to the state specified by
the PC0– PC2 input terminals upon hardware reset and is unaffected by bus reset (see Table 9).

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
APPLICATION
Table 2. Base Register Field Descriptions (Continued)
RPIE 1 Rd/Wr Resuming port interrupt enable. This bit, if set to 1, enables the port event interrupt (PEI) bit to be set
whenever resume operations begin on any port. This bit also enables the C/LKON output signal to be
activated whenever the LLC is inactive and any of the CTOI, CPSI, or STOI interrupt bits are set. This bit
is
reset to 0 by hardware reset and is unaffected by bus reset.
ISBR 1 Rd/Wr Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3 s)
arbitrated bus reset at the next opportunity. This bit is reset to 0 by bus reset.
NOTE: Legacy IEEE Std 1394-1995 compliant PHYs may not be capable of performing short bus resets.
Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long
bus reset being performed.
CTOI 1 Rd/Wr Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times out during tree-ID
start, and may indicate that the bus is configured in a loop. This bit is reset to 0 by hardware reset, or by
writing a 1 to this register bit.
If the CTOI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the
C/LKON output to notify the LLC to service the interrupt.
NOTE: If the network is configured in a loop, only those nodes that are part of the loop generate a
configuration time-out interrupt. All other nodes instead time out waiting for the tree-ID and/or self-ID
process to complete and then generate a state time-out interrupt and bus reset.
CPSI 1 Rd/Wr Cable power status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low
indicating that cable power may be too low for reliable operation. This bit is reset to 1 by hardware reset.
It can be cleared by writing a 1 to this register bit.
If the CPSI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the
C/LKON output to notify the LLC to service the interrupt.
STOI 1 Rd/Wr State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus
reset to occur). This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. If the STOI
and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON output to
notify the LLC
to service the interrupt.
PEI 1 Rd/Wr Port event interrupt. This bit is set to 1 upon a change in the bias, connected, disabled, or fault bits for
any port for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt enable
(RPIE) bit is set, the PEI bit is set to 1 at the start of resume operations on any port. This bit is reset to 0
by hardware reset, or by writing a 1 to this register bit.
If the PEI bit is set (regardless of the state of the RPEI bit) and the LLC is or becomes inactive, the PHY
activates the C/LKON output to notify the LLC to service the interrupt.
EAA 1 Rd/Wr Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration acceleration
enhancements defined in IEEE 1394a-2000 (ACK-accelerated arbitration, asynchronous fly-by
concatenation, and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is
unaffected by bus reset.
NOTE: The EAA bit should be set only if the attached LLC is IEEE 1394a-2000 compliant. If the LLC is
not IEEE 1394a-2000 compliant, use of the arbitration acceleration enhancements may interfere with
isochronous traffic by excessively delaying the transmission of cycle-start packets.
EMC 1 Rd/Wr Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of
differing speeds in accordance with the protocols defined in IEEE 1394a-2000. This bit is reset to 0 by
hardware reset and is unaffected by bus reset.
NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy
IEEE Std 1394-1995 PHYs. However, use of multispeed concatenation requires that the attached LLC
be IEEE 1394a-2000 compliant.
Page_Select 3 Rd/Wr Page select. This field selects the register page to use when accessing register addresses 8 through 15.
This field is reset to 0 by hardware reset and is unaffected by bus reset.
Port_Select 4 Rd/Wr Port select. This field selects the port when accessing per-port status or control (for example, when one of
the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is
reset to 0 by hardware reset and is unaffected by bus reset.

TSB41AB2, TSB41AB2I
APPLICATION
The port status page provides access to configuration and status information for each of the ports. The port
is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base
register 7. The configuration of the port status page registers is shown in Table 3, and corresponding field
descriptions are given in Table 4. If the selected port is unimplemented, all registers in the port status page
are read as 0.
Table 3. Page 0 (Port Status) Register Configuration

BIT POSITION
ADDRESS
0 1 2 3 4 5 6 7
1000 Astat Bstat Ch Con Bias Dis
1001 Peer_Speed PIE Fault Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
APPLICATION
Table 4. Page 0 (Port Status) Register Field Descriptions

Astat 2 Rd TPA line state. This field indicates the TPA line state of the selected port, encoded as follows:
Code Line State
11 Z
01 1
10 0
00 invalid
Bstat 2 Rd TPB line state. This field indicates the TPB line state of the selected port. This field has the same
encoding as the Astat field.
Ch 1 Rd Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected
port is the parent port. A disconnected, disabled, or suspended port is reported as a child port. The
Ch bit is invalid after a bus reset until tree-ID has completed.
Con 1 Rd Debounced port connection status. This bit indicates that the selected port is connected. The
connection must be stable for the debounce time of approximately 341 ms for the con bit to be set to
1. The con bit is reset to 0 by hardware reset and is unaffected by bus reset.
NOTE: The con bit indicates that the port is physically connected to a peer PHY, but the port is not
necessarily active.
Bias 1 Rd Debounced incoming cable bias status. A 1 indicates that the selected port is detecting incoming
cable bias. The incoming cable bias must be stable for the debounce time of 52 s for the bias bit to
be set to 1.
Dis 1 Rd/Wr Port disabled control. If 1, the selected port is disabled. The dis bit is reset to 0 by hardware reset (all
ports are enabled for normal operation following hardware reset). The dis bit is not affected by bus
reset.
Peer_Speed 3 Rd Port peer speed. This field indicates the highest speed capability of the peer PHY connected to the
selected port, encoded as follows:
Code Peer Speed
000 S100
001 S200
010 S400
011–111 invalid
The Peer_Speed field is invalid after a bus-reset until self-ID has completed.
NOTE: Peer speed codes higher than 010b (S400) are defined in IEEE 1394a-2000. However, the
TSB41AB2 is only capable of detecting peer speeds up to S400.
PIE 1 Rd/Wr Port event interrupt enable. When set to 1, a port event on the selected port sets the port event
interrupt (PEI) bit and notify the link. This bit is reset to 0 by hardware reset and is unaffected by bus
reset.
Fault 1 Rd/Wr Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port and
that the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect
incoming cable bias from its attached peer. A suspend-fault occurs when a suspending port
continues to detect incoming cable bias from its attached peer. Writing 1 to this bit clears the bit to 0.
This bit is reset to 0
by hardware reset and is unaffected by bus reset.

TSB41AB2, TSB41AB2I
APPLICATION INFORMATION
The vendor identification page is used to identify the vendor/manufacturer and compliance level. The page
is selected by writing 1 to the Page_Select field in base register 7. The configuration of the vendor
identification page is shown in Table 5, and corresponding field descriptions are given in Table 6.
Table 5. Page 1 (Vendor ID) Register Configuration

BIT POSITION
ADDRESS
0 1 2 3 4 5 6 7
1000 Compliance
1001 Reserved
1010 Vendor_ID[0]
1011 Vendor_ID[1]
1100 Vendor_ID[2]
1101 Product_ID[0]
1110 Product_ID[1]
1111 Product_ID[2]
Table 6. Page 1 (Vendor ID) Register Field Descriptions

Compliance 8 Rd Compliance level. For the TSB41AB2 this field is 01h, indicating compliance with IEEE
1394a-2000.
Vendor_ID 24 Rd Manufacturer’s organizationally unique identifier (OUI). For the TSB41AB2 this field is 08
0028h (Texas Instruments) (the MSB is at register address 1010b).
Product_ID 24 Rd Product identifier. For the TSB41AB2 this field is 42 XXXXh (the MSB is at register address
1101b).
The vendor-dependent page provides access to the special control features of the TSB41AB2, as well as
configuration and status information used in manufacturing test and debug. This page is selected by writing
7 to the Page_Select field in base register 7. The configuration of the vendor-dependent page is shown in
Table 7, and corresponding field descriptions are given in Table 8.
Table 7. Page 7 (Vendor-Dependent) Register Configuration

BIT POSITION
ADDRESS
0 1 2 3 4 5 6 7
1000 NPA Reserved Link_Speed
1001 Reserved for test
1110 SWR Reserved for test

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
APPLICATION
Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions

NPA 1 Rd/Wr Null-packet actions flag. This bit instructs the PHY to not clear fair and priority requests when a null
packet is received with arbitration acceleration enabled. If 1, then fair and priority requests are cleared
only when a packet of more than 8 bits is received; ACK packets (exactly 8 data bits), null packets (no
data bits), and malformed packets (less than 8 data bits) do not clear fair and priority requests. If 0,
then fair and priority requests are cleared when any non-ACK packet is received, including null packets
or malformed packets of less than 8 bits. This bit is cleared to 0 by hardware reset and is unaffected
by bus reset.
Link_Speed 2 Rd/Wr Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows:
Code Speed
00 S100
01 S200
10 S400
11 illegal
This field is replicated in the sp field of the self-ID packet to indicate the speed capability of the node
(PHY and LLC in combination). However, this field does not affect the PHY speed capability indicated
to peer PHYs during self-ID; the TSB41AB2 PHY identifies itself as S400 capable to its peers
regardless of the value in this field. This field is set to 10b (S400) by hardware reset and is unaffected
by bus reset.
SWR 1 Rd/Wr Software hard reset. Writing a 1 to this bit forces a hard reset of the PHY (just as momentarily asserting
the RESET terminal low). This bit is always read as a 0.
power-class programming
The PC0 – PC2 terminals are programmed to set the default value of the power class indicated in the pwr
field (bits 21 – 23) of the transmitted self-ID packet. Descriptions of the various power classes are given in
Table 9. The default power-class value is loaded following a hardware reset, but is overridden by any value
subsequently loaded into the Pwr_Class field in register 4.
Table 9. Power Class Descriptions

PC0 – PC2 DESCRIPTION
000 Node does not need power and does not repeat power.
001 Node is self-powered and provides a minimum of 15 W to the bus.
100 Node may be powered from the bus for the PHY only using up to 3 W and may also provide power to the bus. The amount
of bus power that it provides can be found in the configuration ROM.
101 Reserved
110 Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link.
111 Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.

TSB41AB2, TSB41AB2I
APPLICATION
using the TSB41AB2 with a non-IEEE 1394a-2000 link layer
The TSB41AB2 implements the PHY-LLC interface specified in IEEE 1394a-2000. This interface is based
upon the interface described in informative Annex J of IEEE Std 1394-1995, which is the interface used in
older TI PHY devices. The PHY-LLC interface specified in IEEE 1394a-2000 is completely compatible with
the older Annex J interface.
IEEE 1394a-2000 includes enhancements to the Annex J interface that must be comprehended when using
the TSB41AB2 with a non-IEEE 1394a-2000 LLC device.
• A new LLC service request was added which allows the LLC to temporarily enable and disable
asynchronous arbitration accelerations. If the LLC does not implement this new service request, the
arbitration enhancements should not be enabled (see the EAA bit in PHY register 5).
• The capability to perform multispeed concatenation (the concatenation of packets of differing speeds)
was added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC
does not support multispeed concatenation, multispeed concatenation should not be enabled in the
PHY (see the EMC bit in PHY register 5).
• In order to accommodate the higher transmission speeds expected in future revisions of the standard,
IEEE 1394a-2000 extended the speed code in bus requests from 2 bits to 3 bits, increasing the length
of the bus request from 7 bits to 8 bits. The new speed codes were carefully selected so that new IEEE
1394a-2000 PHY and LLC devices would be compatible, for speeds from S100 to S400, with legacy
PHY and LLC devices that use the 2-bit speed codes. The TSB41AB2 correctly interprets both 7-bit bus
requests (with 2-bit speed codes) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit
bus request is immediately followed by another request (for example, a register read or write request),
the TSB41AB2 correctly interprets both requests. Although the TSB41AB2 correctly interprets 8-bit bus
requests, a request with a speed code exceeding S400 results in the TSB41AB2 transmitting a null
packet (data-prefix followed by data-end, with no data in the packet).
More explanation is included in the TI application note IEEE 1394a Features Supported by TI TSB41LV0X
Physical Layer Devices, TI literature number SLLA019.
using the TSB41AB2 with a lower-speed link layer
Although the TSB41AB2 is an S400 capable PHY, it may be used with lower speed LLCs, such as the S200
capable TSB12LV31. In such a case, the LLC has fewer data terminals than the PHY, and some Dn
terminals on the TSB41AB2 remain unused. Unused Dn terminals should be pulled to ground through 10-
k resistors.
The TSB41AB2 transfers all received packet data to the LLC, even if the speed of the packet exceeds the
capability of the LLC to accept it. Some lower speed LLC designs do not properly ignore packet data in such
cases. On the rare occasions that the first 16 bits of partial data accepted by such an LLC match the bus ID
and node ID for that node, spurious header CRC or tcode errors may result.
During bus initialization following a bus reset, each PHY transmits a self-ID packet that indicates, among
other information, the speed capability of the PHY. The bus manager (if one exists) builds a speed map
from the collected self-ID packets. This speed map gives the highest possible speed that can be used on
the node-to-node communication paths between every pair of nodes in the network.

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
APPLICATION
using the TSB41AB2 with a lower-speed link layer (continued)
In the case of a node consisting of a higher-speed PHY and a lower-speed LLC, the speed capability of the
node (PHY and LLC in combination) is that of the lower-speed LLC. A sophisticated bus manager may be
able to determine the LLC speed capability by reading the configuration ROM Bus_Info_Block, or by
sending asynchronous request packets at different speeds to the node and checking for an acknowledge; the
speed map may then be adjusted accordingly. The speed map should reflect that communication to such a
node must be done at the lower speed of the LLC, instead of the higher speed of the PHY. However,
speed-map entries for paths that merely pass through the node PHY, but do not terminate at that node,
should not be restricted by the lower speed of the LLC.
To assist in building an accurate speed map, the TSB41AB2 has the capability of indicating a speed
capability other than S400 in its transmitted self-ID packet. This is controlled by the Link_Speed field in
register 8 of the vendor-dependent page (page 7). Setting the Link_Speed field affects only the speed
indicated in the self-ID packet; it has no effect on the speed signaled to peer PHYs during self-ID. The
TSB41AB2 identifies itself as S400 capable to its peers regardless of the value in the Link_Speed field.
Generally, the Link_Speed field should not be changed from its power-on default value of S400 unless it is
determined that the speed map (if one exists) is incorrect for path entries terminating in the local node. If the
speed map is incorrect, it can be assumed that the bus manager has used only the self-ID packet
information to build the speed map. In this case, the node may update the Link_Speed field to reflect the
lower speed capability of the LLC and then initiate another bus reset to cause the speed map to be rebuilt.
Note that in this scenario any speed map entries for node-to-node communication paths that pass through
the local node’s PHY are restricted by the lower speed.
In the case of a leaf node (which has only one active port) the Link_Speed field may be set to indicate the
speed of the LLC without first checking the speed map. Changing the Link_Speed field in a leaf node can
only affect those paths that terminate at that node; because no other paths can pass through a leaf node it
can have no effect on other paths in the speed map. For hardware configurations, which can only be a leaf
node (all ports but one are unimplemented), it is recommended that the Link_Speed field be updated
immediately after power-on or hardware reset.
power-up reset
To ensure proper operation of the TSB41AB2 the RESET terminal must be asserted low for a minimum of 2
ms from the time that PHY power reaches the minimum required supply voltage. When using a passive
capacitor on the RESET terminal to generate a power-on reset signal, the minimum reset time is assured if
the capacitor has a minimum value of 0.1 F and also satisfies the following equation:
C = 0.0077 × T + (2)
min
0.085
where Cmin is the minimum capacitance on the RESET terminal in F, and T is the VDD ramp time, 10% –
90%, in milliseconds.
bus reset
In the TSB41AB2, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus reset and
initialization sequence. The IBR bit is located in PHY register 1, along with the root-holdoff bit (RHB) and
gap-count register, as required by IEEE 1394a-2000 (this configuration also maintains compatibility with
older TI PHY designs which were based upon the suggested register set defined in Annex J of IEEE Std
1394-1995). Therefore, whenever the IBR bit is written, the RHB and gap count are also necessarily written.

TSB41AB2, TSB41AB2I
APPLICATION
bus reset (continued)

The RHB and gap count may also be updated by PHY-config packets. The TSB41AB2 is IEEE 1394a-2000
compliant, and therefore both the reception and transmission of PHY-config packets cause the RHB and
gap count to be loaded, unlike older IEEE Std 1394-1995 compliant PHYs which decode only received
PHY-config packets.
The gap count is set to the maximum value of 63 after two consecutive bus resets without an intervening
write to the gap count, either by a write to PHY register 1 or by a PHY-config packet. This mechanism
allows a PHY-config packet to be transmitted and then a bus reset initiated so as to verify that all nodes on
the bus have updated their RHBs and gap-count values, without having the gap count set back to 63 by the
bus reset. The subsequent connection of a new node to the bus, which initiates a bus reset, then causes the
gap count of each node to be set to 63. Note, however, that if a subsequent bus reset is instead initiated by
a write to register 1 to set the IBR bit, all other nodes on the bus have their gap-count values set to 63,
while this node gap count remains set to the value just loaded by the write to PHY register 1.
Therefore, in order to maintain consistent gap counts throughout the bus, the following rules apply to the
use of the IBR bit, RHB, and gap-count in PHY register 1:
• Following the transmission of a PHY-config packet, a bus reset must be initiated in order to verify that
all nodes have correctly updated their RHBs and gap-count values, and to ensure that a subsequent
new connection to the bus causes the gap count to be set to 63 on all nodes in the bus. If this bus reset is
initiated by setting the IBR bit to 1, the RHB and gap-count register must also be loaded with the correct
values consistent with the just transmitted PHY-config packet. In the TSB41AB2, the RHB and gap
count are updated to their correct values upon the transmission of the PHY-config packet, and so these
values may first be read from register 1 and then rewritten.
• Other than to initiate the bus reset which must follow the transmission of a PHY-config packet,
whenever the IBR bit is set to 1 in order to initiate a bus reset, the gap-count value must also be set to
63 so as to be consistent with other nodes on the bus, and the RHB should be maintained with its
current value.
• The PHY register 1 should not be written to except to set the IBR bit. The RHB and gap count should
not be written without also setting the IBR bit to 1.

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
PRINCIPLES OF
PHY-Link layer interface

The TSB41AB2 is designed to operate with an LLC such as the Texas Instruments TSB12LV21,
TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42 or TSB12LV01A. Details of
operation for the
Texas Instruments LLC devices are found in the respective LLC data sheets. The following paragraphs describe
the operation of the PHY-LLC interface.
The interface to the LLC consists of the SYSCLK, CTL0 – CTL1, D0 – D7, LREQ, LPS, C/LKON, and ISO
terminals on the TSB41AB2, as shown in Figure 13.
Link TSB41AB2
Layer
Controller SYSCLK
CTL0−CTL1
D1−D7
LREQ
LPS
C/LKON
ISO ISO
ISO
Figure 13. PHY-LLC Interface
The SYSCLK terminal provides a 49.152-MHz interface clock. All control and data signals are synchronized to,
and sampled on, the rising edge of SYSCLK.
The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data
between the TSB41AB2 and LLC.
The D0 – D7 terminals form a bidirectional data bus, which is used to transfer status information, control
information, or packet data between the devices. The TSB41AB2 supports S100, S200, and S400 data
transfers over the D0 – D7 data bus. In S100 operation only the D0 and D1 terminals are used; in S200
operation only the D0 – D3 terminals are used; and in S400 operation all D0 – D7 terminals are used for
data transfer. When the TSB41AB2 is in control of the D0 – D7 bus, unused Dn terminals are driven low during
S100 and S200 operations. When the LLC is in control of the D0 – D7 bus, unused Dn terminals are ignored
by the TSB41AB2.
The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request
access to the serial bus for packet transmission, read or write PHY registers, or control arbitration
acceleration.
The LPS and C/LKON terminals are used for power management of the PHY and LLC. The LPS terminal
indicates the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable
SYSCLK. The C/LKON terminal is used to send a wake-up notification to the LLC and to indicate an
interrupt to the LLC either when LPS is inactive or when the PHY register LCtrl bit is zero.
The ISO terminal is used to enable the output differentiation logic on the CTL0 – CTL1 and D0 – D7 terminals.
Output differentiation is required when an Annex J type isolation barrier is implemented between the PHY and
LLC.
The TSB41AB2 normally controls the CTL0 – CTL1 and D0 – D7 bidirectional buses. The LLC is allowed to
drive these buses only after the LLC has been granted permission to do so by the PHY.
There are four operations that may occur on the PHY-LLC interface: link service request, status transfer,
data transmit, and data receive. The LLC issues a service request to read or write a PHY register, to request

TSB41AB2, TSB41AB2I
the PHY to gain control of the serial bus in order to transmit a packet, or to control arbitration acceleration.
PRINCIPLES OF

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
PRINCIPLES OF
PHY-Link layer interface (continued)

The PHY may initiate a status transfer either autonomously or in response to a register read request from the
LLC.
The PHY initiates a receive operation whenever a packet is received from the serial bus.
The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC.
The transmit operation is initiated when the PHY grants control of the interface to the LLC.
The encoding of the CTL0 −CTL1 bus is shown in Table 10 and Table 11.
Table 10. CTL Encoding When PHY Has Control of the Bus
CTL0 CTL1 NAME DESCRIPTION
0 0 Idle No activity (this is the default mode)
0 1 Status Status information is being sent from the PHY to the LLC.
1 0 Receive An incoming packet is being sent from the PHY to the LLC.
1 1 Grant The LLC has been given control of the bus to send an outgoing packet.
Table 11. CTL Encoding When LLC Has Control of the Bus
CTL0 CTL1 NAME DESCRIPTION
0 0 Idle The LLC releases the bus (transmission has been completed).
0 1 Hold The LLC is holding the bus while data is being prepared for transmission, or indicating that another
packet is to be transmitted (concatenated) without arbitrating.
1 0 Transmit An outgoing packet is being sent from the LLC to the PHY.
1 1 Reserved None
output differentiation
When an Annex J type isolation barrier is implemented between the PHY and LLC, the CTL0 – CTL1, D0 – D7,
and LREQ signals must be digitally differentiated so that the isolation circuits function correctly. Digital
differentiation is enabled on the TSB41AB2 when the ISO terminal is low.
The differentiation operates such that the output is driven either low or high for one clock period whenever
the signal changes logic state, but otherwise places the output in a high-impedance state for as long as the
signal logic state remains constant. On input, hysteresis buffers are used to convert the signal to the correct
logic state when the signal is high impedance; the biasing network of the Annex J type isolation circuit pulls
the signal voltage level between the hysteresis thresholds of the input buffer so that the previous logic state
is maintained.
The correspondence between the output logic state and the output signal level is shown in Figure 14.
Logic State
0 1 1 0 0 0 1 0 0
Signal Level
L H Z O Z Z H L Z
Figure 14. Signal Transformation for Digital Differentiation

TSB41AB2, TSB41AB2I
PRINCIPLES OF
output differentiation (continued)

The TSB41AB2 implements differentiation circuitry functionally equivalent to that shown in Figure 15 on the
bidirectional CTL0 – CTL1and D0 – D7 terminals. The TSB41AB2 also implements an input hysteresis buffer
on the LREQ input to convert this signal to the correct logic level when differentiated. The LLC must also
implement similar output differentiation and input hysteresis circuitry on its CTL and D terminals, and output
differentiation circuitry on its LREQ terminal.
Input Buffer With
Hysteresis
DIN
Q D
D Terminal
DOUT
D
To/From 3- State Output
Internal Q Driver
Device Logic
ISO
D
OUTEN
Q
INIT
SYSCLK
Figure 15. Input/Output Differentiation Logic
LLC service request

To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the LLC
sends a serial bit stream on the LREQ terminal as shown in Figure 16.
LR0 LR1 LR2 LR3 LR(n-2)LR(n-1)
NOTE: Each cell represents one clock sample time, and n is the number of bits in the request stream.
Figure 16. LREQ Request Stream
The length of the stream varies depending on the type of request as shown in Table 12.
Table 12. Request Stream Bit Length

REQUEST TYPE NUMBER OF BITS
Bus request 7 or 8
Read register request 9
Write register request 17
Acceleration control request 6

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
PRINCIPLES OF
LLC service request (continued)

Regardless of the type of request, a start bit of 1 is required at the beginning of the stream, and a stop bit of
0 is required at the end of the stream. The second through fourth bits of the request stream indicate the
type of the request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request
bit stream. The LREQ terminal is normally low.
Encoding for the request type is shown in Table 13.
Table 13. Request Type Encoding

LR1 – LR3 NAME DESCRIPTION
000 ImmReq Immediate bus request. Upon detection of idle, the PHY takes control of the bus immediately without arbitration.
001 IsoReq Isochronous bus request. Upon detection of idle, the PHY arbitrates for the bus without waiting for a subaction
gap.
010 PriReq Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol.
011 FairReq Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol.
100 RdReg The PHY returns the specified register contents through a status transfer.
101 WrReg Write to the specified register.
110 AccelCtl Enable or disable asynchronous arbitration acceleration.
111 Reserved Reserved.
For a bus request the length of the LREQ bit stream is 7 or 8 bits as shown in Table 14.
Table 14. Bus Request

BIT(S) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1).
1−3 Request type Indicates the type of bus request. See Table 13.
4−6 Request speed Indicates the speed at which the PHY sends the data for this request. See Table 15 for the encoding of this
field.
7 Stop bit Indicates the end of the transfer (always 0). If bit 6 is 0, this bit may be omitted.
The 3-bit request speed field used in bus requests is shown in Table 15.
Table 15. Bus Request

LR4 – LR6 DATA RATE
000 S100
010 S200
100 S400
All Others Invalid
NOTE: The TSB41AB2 does accept a bus request with
an invalid speed code and process the bus
request normally. However, during packet
transmission for such a request, the
TSB41AB2 ignores any data presented by the
LLC and transmits a null packet.

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
PRINCIPLES OF

For a read register request the length of the LREQ bit stream is 9 bits as shown in Table 16.
Table 16. Read Register Request

0 Start bit Indicates the beginning of the transfer (always 1)
1− 3 Request type A 100 indicating this is a read register request
4− 7 Address Identifies the address of the PHY register to be read
8 Stop bit Indicates the end of the transfer (always 0)
For a write register request the length of the LREQ bit stream is 17 bits as shown in Table 17.
Table 17. Write Register Request

1− 3 Request type A 101 indicating this is a write register request
4− 7 Address Identifies the address of the PHY register to be written to
8−15 Data Gives the data that is to be written to the specified register address
For an acceleration control request the length of the LREQ bit stream is 6 bits as shown in Table 18.
Table 18. Acceleration Control Request

1− 3 Request type A 110 indicating this is an acceleration control request
4 Control Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0.
5 Stop bit Indicates the end of the transfer (always 0)
For fair or priority access, the LLC sends the bus request (FairReq or PriReq) at least one clock after the
PHY-LLC interface becomes idle. If the CTL terminals are asserted receive (10b) by the PHY, then any
pending fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or priority requests if
receive is asserted while the LLC is sending the request. The LLC may then reissue the request one clock
after the next interface idle.
The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or
transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY
clears an isochronous request only when the serial bus has been won.
To send an acknowledge packet, the LLC must issue an immediate bus request (ImmReq) during the
reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of
the received packet and the start of the transmitted acknowledge packet. As soon as the receive packet
ends, the PHY immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the
sender unless the header CRC of the received packet is corrupted. In this case, the LLC does not transmit
an acknowledge, but instead cancels the transmit operation and releases the interface immediately; the LLC
must not use this grant to send another type of packet. After the interface is released the LLC may proceed
with another request.

TSB41AB2, TSB41AB2I
PRINCIPLES OF

The LLC may make only one bus request at a time. Once the LLC issues any request for bus access
(ImmReq, IsoReq, FairReq, or PriReq), it cannot issue another bus request until the PHY indicates that the
bus request was lost (bus arbitration lost and another packet received), or won (bus arbitration won and the
LLC granted control). The PHY ignores new bus requests while a previous bus request is pending. All bus
requests are cleared upon a bus reset.
For write register requests, the PHY loads the specified data into the addressed register as soon as the
request transfer is complete. For read register requests, the PHY returns the contents of the addressed
register to the LLC at the next opportunity through a status transfer. If a received packet interrupts the status
transfer, then the PHY continues to attempt the transfer of the requested register until it is successful. A
write or read register request may be made at any time, including while a bus request is pending. Once a
read register request is made, the PHY ignores further read register requests until the register contents are
successfully transferred to the LLC. A bus reset does not clear a pending read register request.
The TSB41AB2 includes several arbitration acceleration enhancements, which allow the PHY to improve
bus performance and throughput by reducing the number and length of interpacket gaps. These
enhancements include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority
packet concatenation onto acknowledge packets, and accelerated fair and priority request arbitration
following acknowledge packets. The enhancements are enabled when the EAA bit in PHY register 5 is set.
The arbitration acceleration enhancements may interfere with the ability of the cycle master node to transmit
the cycle start message under certain circumstances. The acceleration control request is therefore provided
to allow the LLC to temporarily enable or disable the arbitration acceleration enhancements of the
TSB41AB2 during the asynchronous period. The LLC typically disables the enhancements when its internal
cycle counter rolls over indicating that a cycle start message is imminent, and then reenables the
enhancements when it receives a cycle start message. The acceleration control request may be made at
any time, however, and is immediately serviced by the PHY. Additionally, a bus reset or isochronous bus
request causes the enhancements to be reenabled, if the EAA bit is set.
status transfer
A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. The
PHY waits until the interface is idle before starting the transfer. The transfer is initiated by the PHY asserting
status (01b) on the CTL terminals, along with the first two bits of status information on the D[0:1] terminals.
The PHY maintains CTL = status for the duration of the status transfer. The PHY may prematurely end a
status transfer by asserting something other than status on the CTL terminals. This occurs if a packet is
received before the status transfer completes. The PHY continues to attempt to complete the transfer until all
status information has been successfully transmitted. There is at least one idle cycle between consecutive
status transfers.
The PHY normally sends just the first four bits of status to the LLC. These bits are status flags that are
needed by the LLC state machines. The PHY sends an entire 16-bit status packet to the LLC after a read
register request, or when the PHY has pertinent information to send to the LLC or transaction layers. The
only defined condition where the PHY automatically sends a register to the LLC is after self-ID, where the
PHY sends the physical-ID register that contains the new node address. All status transfers are either 4 or
16 bits unless interrupted by a received packet. The status flags are considered to have been successfully
transmitted to the LLC immediately upon being sent, even if a received packet subsequently interrupts the
status transfer. Register contents are considered to have been successfully transmitted only when all 8 bits
of the register have been sent. A status transfer is retried after being interrupted only if any status flags
remain to be sent, or if a register transfer has not yet completed.
The definition of the bits in the status transfer is shown in Table 19, and the timing is shown in Figure 17.

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
PRINCIPLES OF
status transfer (continued)
Table 19. Status Bits

0 Arbitration reset gap Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as
defined in IEEE Std 1394-1995). This bit is used by the LLC in the busy/retry state machine.
1 Subaction gap Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in
IEEE Std 1394-1995). This bit is used by the LLC to detect the completion of an isochronous cycle.
2 Bus reset Indicates that the PHY has entered the bus reset start state
3 Interrupt Indicates that a PHY interrupt event has occurred. An interrupt event may be a configuration time-out,
cable-power voltage falling too low, a state time-out, or a port status change.
4− 7 Address This field holds the address of the PHY register whose contents are being transferred to the LLC.
8− 15 Data This field holds the register contents.
SYSCLK
(1) (2)
CTL0, CTL1
00 01 00
D0, D1 00 S[0:1] S[14:15] 00
Figure 17. Status Transfer Timing
The sequence of events for a status transfer is as follows:

1. Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines along
with the status data on the D0 and D1 lines (only two bits of status are transferred per cycle). Normally
(unless interrupted by a receive operation), a status transfer is either two or eight cycles long. A 2-cycle
(4 bit) transfer occurs when only status information is to be sent. An 8-cycle (16 bit) transfer occurs
when register data is to be sent in addition to any status information.
2. Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL
lines. The PHY may also interrupt a status transfer at any cycle by asserting receive on the CTL lines to
begin a receive operation. The PHY asserts at least one cycle of idle between consecutive status
transfers.
receive
Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by
asserting receive on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The
PHY indicates the start of a packet by placing the speed code (encoded as shown in Table 20) on the D
terminals, followed by packet data. The PHY holds the CTL terminals in receive until the last symbol of the
packet has been transferred. The PHY indicates the end of packet data by asserting idle on the CTL
terminals. All received packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC
protocol and is not included in the calculation of CRC or any other data protection mechanisms.

TSB41AB2, TSB41AB2I
PRINCIPLES OF
receive (continued)
It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus
followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet
speed exceeds the capability of the receiving PHY, or whenever the LLC immediately releases the bus
without transmitting any data. In this case, the PHY asserts receive on the CTL terminals with the data-on
indication (all 1s) on the D terminals, followed by idle on the CTL terminals, without any speed code or data
being transferred. In all cases, the TSB41AB2 sends at least one data-on indication before sending the
speed code or terminating the receive operation.
The TSB41AB2 also transfers its own self-ID packet, transmitted during the self-ID phase of bus
initialization, to the LLC. This packet is transferred to the LLC just as any other received self-ID packet.
Figure 18 is the reception timing diagram for normal packets, and Figure 19 is the reception timing diagram
for null packets.
SYSCLK
(1)
CTL0, CTL1 00 10 00
01
(2) (3) (4) (5)
D0–D7 XX FF (Data-On) SPD d0 dn 00
Figure 18. Normal Packet Reception Timing
The sequence of events for a normal packet reception is as follows:

1. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL
lines. Normally, the interface is Idle until receive is asserted. However, the receive operation may interrupt
a status transfer operation that is in progress so that the CTL lines may change from status to receive
without an intervening idle.
2. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles
preceding the speed code.
3. Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D
lines for one cycle immediately preceding packet data. The link decodes the speed code on the first
receive cycle for which the D lines are not the data-on code. If the speed code is invalid, or indicates a
speed higher than that which the link is capable of handling, the link should ignore the subsequent data.
4. Receive data. Following the data-on indication (if any) and the speed code, the PHY asserts packet
data on the D lines with receive on the CTL lines for the remainder of the receive operation.
5. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL
lines. The PHY asserts at least one cycle of idle following a receive operation.
SYSCLK
(1)
00
CTL0, CTL1 10 00
01
(2) (3)
D0–D7 XX FF (Data-On) 00

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
Figure 19.PRINCIPLES OF
Null Packet Reception Timing

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
PRINCIPLES OF
receive (continued)
The sequence of events for a null packet reception is as follows:
1. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL
lines. Normally, the interface is idle until receive is asserted. However, the receive operation may interrupt
a status transfer operation that is in progress so that the CTL lines may change from status to receive
without an intervening idle.
2. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.
3. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL
lines. The PHY asserts at least one cycle of idle following a receive operation.
Table 20. Receive Speed Codes

D0 −D7 DATA RATE
00XX XXXX S100
0100 XXXX S200
0101 0000 S400
1YYY YYYY data-on indication
NOTE: X = Output as 0 by PHY, ignored by LLC.
Y = Output as 1 by PHY, ignored by
LLC.
transmit
When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the
bus. If the PHY wins arbitration for the serial bus, the PHY-LLC interface bus is granted to the LLC by
asserting the grant state (11b) on the CTL terminals for one SYSCLK cycle, followed by idle for one clock
cycle. The LLC then takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the
CTL terminals. Unless the LLC is immediately releasing the interface, the LLC may assert Idle for at most one
clock before it must assert either hold or transmit on the CTL terminals. The hold state is used by the LLC to
retain control of the bus while it prepares data for transmission. The LLC may assert hold for zero or more
clock cycles (that is, the LLC need not assert hold before transmit). The PHY asserts data prefix on the
serial bus during this time.
When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the
first bits of packet data on the D lines. A transmit is held on the CTL terminals until the last bits of data have
been sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle, and then
asserts idle for one additional cycle before releasing the interface bus and placing its CTL and D terminals
in a high- impedance state. The PHY then regains control of the interface bus.
The hold asserted at the end of packet transmission indicates to the PHY that the LLC requests to send
another packet (concatenated packet) without releasing the serial bus. The PHY responds to this
concatenation request by waiting the required minimum packet separation time and then asserting grant as
before. This function may be used to send a unified response after sending an acknowledge, or to send
consecutive isochronous packets during a single isochronous period. Unless multispeed concatenation is
enabled, all packets transmitted during a single bus ownership must be of the same speed (since the speed
of the packet is set before the first packet). If multi-speed concatenation is enabled (when the EMSC bit of
PHY register 5 is set), the LLC must specify the speed code of the next concatenated packet on the D
terminals when it asserts hold on the CTL terminals at the end of a packet. The encoding for this speed
code is the same as the speed code that precedes received packet data as given in Table 20.

TSB41AB2, TSB41AB2I
PRINCIPLES OF
transmit (continued)
After sending the last packet for the current bus ownership, the LLC releases the bus by asserting idle on
the CTL terminals for two clock cycles. The PHY begins asserting idle on the CTL terminals one clock after
sampling idle from the link. Note that whenever the D and CTL terminals change direction between the PHY
and the LLC, there is an extra clock period allowed so that both sides of the interface can operate on
registered versions of the interface signals. Figure 20 is the transmission timing diagram for normal packets,
and Figure 21 is the transmission timing diagram for cancelled or null packets.
SYSCLK
(1) (2) (3) (4) (5) (7)

CTL0, CTL1 00 11 000001 01
10 00 00
00
(6)
SPD 00
D0–D7 00 00 d0 dn 0000
Link Controls CTL and D

PHY CTL and D Outputs Are High Impedance
NOTE: SPD = Speed code, see Table 20
d0 − dn = Packet data
Figure 20. Normal Packet Transmission Timing
The sequence of events for a normal packet transmission is as follows:

1. Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over
control of the interface to the link so that the link may transmit a packet. The PHY releases control of
the interface (that is, it places its CTL and D outputs in a high-impedance state) following the idle cycle.
2. Optional idle cycle. The link may assert at most one idle cycle preceding assertion of either hold or
transmit. This idle cycle is optional; the link is not required to assert idle preceding either hold or
transmit.
3. Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of transmit.
These hold cycle(s) are optional; the link is not required to assert hold preceding transmit.
4. Transmit data. When data is ready to be transmitted, the link asserts transmit on the CTL lines along
with the data on the D lines.
5. Transmit operation terminated. The transmit operation is terminated by the link asserting hold or idle on
the CTL lines. The link asserts hold to indicate that the PHY is to retain control of the serial bus in order
to transmit a concatenated packet. The link asserts idle to indicate that packet transmission is complete
and the PHY may release the serial bus. The link then asserts idle for one more cycle following this cycle
of hold or idle before releasing the interface and returning control to the PHY.
6. Concatenated packet speed code. If multispeed concatenation is enabled in the PHY, the link asserts a
speed code on the D lines when it asserts hold to terminate packet transmission. This speed code
indicates the transmission speed for the concatenated packet that is to follow. The encoding for this
concatenated packet speed code is the same as the encoding for the received packet speed code (see
Table 20). The link may not concatenate an S100 packet onto any higher-speed packet.
7. After regaining control of the interface, the PHY asserts at least one cycle of idle before any subsequent
status transfer, receive operation, or transmit operation.

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
PRINCIPLES OF
transmit (continued)
SYSCLK
(1) (2) (3) (4) (5)
CTL0, CTL1 0 1 00 0 0 0 0
0 1 0 1 0 0
D0–D7 00 00 00
Link Controls CTL and D

PHY CTL and D Outputs Are High Impedance
Figure 21. Cancelled/Null Packet Transmission
The sequence of events for a cancelled/null packet transmission is as follows:

1. Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of
the interface to the link.
2. Optional idle cycle. The link may assert at most one idle cycle preceding assertion of hold. This idle
cycle is optional; the link is not required to assert idle preceding hold.
3. Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of idle. These
hold cycle(s) are optional; the link is not required to assert hold preceding Idle.
4. Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of
idle on the CTL lines and then releasing the interface and returning control to the PHY. Note that the
link may assert idle for a total of three consecutive cycles if it asserts the optional first idle but does not
assert hold. (It is recommended that the link assert three cycles of idle to cancel a packet transmission
if no cycles of hold are asserted. This ensures that either the link or PHY controls the interface in all
cycles.)
5. After regaining control of the interface, the PHY asserts at least one cycle of idle before any subsequent
status transfer, receive operation, or transmit operation.
interface reset and disable

The LLC controls the state of the PHY-LLC interface using the LPS signal. The interface may be placed into
a reset state, a disabled state, or be made to initialize and then return to normal operation. When the
interface is not operational (whether reset, disabled, or in the process of initialization) the PHY cancels any
outstanding bus request or register read request, and ignores any requests made via the LREQ line.
Additionally, any status information generated by the PHY is not queued, and thus does not cause a status
transfer upon restoration of the interface to normal operation.
The LPS signal may be either a level signal or a pulsed signal, depending upon whether the PHY-LLC
interface is a direct connection or is made across an isolation barrier. When an isolation barrier exists
between the PHY and LLC (whether of the TI bus-holder type or Annex J type) the LPS signal must be
pulsed. In a direct connection, the LPS signal may be either a pulsed or a level signal. Timing parameters
for the LPS signal are given in Table 21.

TSB41AB2, TSB41AB2I
PRINCIPLES OF
interface reset and disable (continued)
Table 21. LPS Timing Parameters

PARAMETER DESCRIPTION MIN MAX UNIT
TLPSL LPS low time (when pulsed)† 0.09 2.6 s
TLPSH LPS high time (when pulsed)† 0.021 2.6 s
TLPS_DUTY LPS duty cycle (when pulsed)‡ 20 55 %
TLPS_RESET Time for PHY to recognize LPS deasserted and reset the interface 2.6 2.68 s
TLPS_DISABLE Time for PHY to recognize LPS deasserted and disable the interface 26.03 26.11 s
TRESTORE Time to permit optional isolation circuits to restore during an interface reset 15 23§ s
PHY not in low-power state 60 ns
TCLK_ACTIVATE Time for SYSCLK to be activated from reassertion of LPS
PHY in low-power state 5.3 7.3 ms
† The specified TLPSL and TLPSH times are worst-case values appropriate for operation with the TSB41AB2. These values are broader than
those specified for the same parameters in IEEE 1394a-2000 (that is, an implementation of LPS that meets the requirements of IEEE
1394a-2000 operates correctly with the TSB41AB2).
‡ A pulsed LPS signal must have a duty cycle (ratio of TLPSH to cycle period) in the specified range to ensure proper operation when using an
isolation barrier on the LPS signal (for example, as shown in Figure 9).
§ The maximum value for TRESTORE does not apply when the PHY-LLC interface is disabled, in which case an indefinite time may elapse before
LPS is reasserted. Otherwise, in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is deasserted for
less
than TLPS_DISABLE.
The LLC requests that the interface be reset by deasserting the LPS signal and terminating all bus and
request activity. When the PHY observes that LPS has been deasserted for TLPS_RESET, it resets the
interface. When the interface is in the reset state, the PHY sets its CTL and D outputs in the logic 0 state and
ignores any activity on the LREQ signal. The timing for interface reset is shown in Figure 22 and Figure 23.
ISO
(low)
(1) (3)
SYSCLK
CTL0, CTL1
D0−D7
(2)
LREQ
(4)
LPS
TLPSL TLPS_RESET TRESTORE

TLPSH
Figure 22. Interface Reset, ISO Low

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER
PRINCIPLES OF OPERATION

The sequence of events for resetting the PHY-LLC interface when it is in the differentiated mode of
operation (ISO terminal is low) is as follows:
1. Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet
data reception and transmission via the CTL and D lines, and request activity via the LREQ line.
2. LPS deasserted. The LLC deasserts the LPS signal and, within 1 s, terminates any request or
interface bus activity, and places its LREQ, CTL, and D outputs into a high-impedance state (the LLC
should terminate any output signal activity such that signals end in a logic 0 state).
3. Interface reset. After TLPS_RESET time, the PHY determines that LPS is inactive, terminates any
interface bus activity, and places its CTL and D outputs into a high-impedance state (the PHY
terminates any output signal activity such that signals end in a logic 0 state). The PHY-LLC interface is
now in the reset state.
4. Interface restored. After the minimum TRESTORE time, the LLC may again assert LPS active. (The
minimum TRESTORE interval provides sufficient time for the biasing networks used in Annex J type
isolation barrier circuits to stabilize and reach a quiescent state if the isolation barrier has somehow
become unbalanced.) When LPS is asserted, the interface is initialized.
ISO
(high
) (1) (3)
SYSCLK
CTL0, CTL1
D0−D7
(2)
LREQ
(4)
LPS
TLPS_RESET TRESTORE
Figure 23. Interface Reset, ISO High
The sequence of events for resetting the PHY-LLC interface when it is in the nondifferentiated mode of
operation (ISO terminal is high) is as follows:
1. Normal operation. Interface is operating normally, with LPS asserted, SYSCLK active, status and
packet data reception and transmission via the CTL and D lines, and request activity via the LREQ line.
In Figure 23, the LPS signal is shown as a nonpulsed level signal. However, it is permissible to use a
pulsed signal for LPS in a direct connection between the PHY and LLC; a pulsed signal is required
when using an isolation barrier (whether of the TI bus-holder type or Annex J type).
interface bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ
output low.
interface bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset
state.

TSB41AB2, TSB41AB2I
4. Interface restored. After the minimum TRESTORE time, the LLC may again assert LPS active. When
LPS is asserted, the interface is initialized.

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER

If the LLC continues to keep the LPS signal deasserted, it requests that the interface be disabled. The PHY
disables the interface when it observes that LPS has been deasserted for TLPS_DISABLE. When the
interface is disabled, the PHY sets its CTL and D outputs as stated above for interface reset, but also stops
SYSCLK activity. The interface is also placed into the disabled condition upon a hardware reset of the PHY.
The timing for interface disable is shown in Figure 24 and Figure 25.
When the interface is disabled, the PHY enters a low-power state if none of its ports is active.
ISO (low)
(1) (3) (4)
SYSCLK
CTL0, CTL1
D0−D7
(2)
LREQ
LPS
TLPSL TLPS_RESET
TLPSH
TLPS_DISABLE
Figure 24. Interface Disable, ISO Low
The sequence of events for disabling the PHY-LLC interface when it is in the differentiated mode of operation
(ISO terminal is low) is as follows:
interface bus activity, and places its LREQ, CTL, and D outputs into a high-impedance state (the LLC
should terminate any output signal activity such that signals end in a logic 0 state).
interface bus activity, and places its CTL and D outputs into a high-impedance state (the PHY
terminates any output signal activity such that signals end in a logic 0 state). The PHY-LLC interface is
now in the reset state.
4. Interface disabled. If the LPS signal remains inactive for TLPS_DISABLE time, the PHY terminates
SYSCLK activity by placing the SYSCLK output into a high-impedance state. The PHY-LLC interface is
now in the disabled state.

TSB41AB2, TSB41AB2I
ISO (high)
(1) (3) (4)
SYSCLK
CTL0, CTL1
D0− D7
(2)
LREQ
LPS
TLPS_RESET
TLPS_DISABLE
Figure 25. Interface Disable, ISO High
The sequence of events for disabling the PHY-LLC interface when it is in the nondifferentiated mode of
operation (ISO terminal is high) is as follows:
interface bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ
output low.
interface bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset
state.
4. Interface disabled. If the LPS signal remains inactive for TLPS_DISABLE time, the PHY terminates
SYSCLK activity by driving the SYSCLK output low. The PHY-LLC interface is now in the disabled
state.
After the interface has been reset, or reset and then disabled, the interface is initialized and restored to
normal operation when LPS is reasserted by the LLC. The timing for interface initialization is shown in
Figure 26 and Figure 27.

TSB41AB2,
PORT CABLE
TRANSCEIVER/ARBITER

ISO (low)
7 Cycles
SYSCLK
5 ns, Min (3)

10 ns, Max
CTL0
(2) (4)
CTL1
D0−D7
LREQ
(1)
LPS
TCLK_ACTIVE
Figure 26. Interface Initialization, ISO Low
The sequence of events for initialization of the PHY-LLC interface when the interface is in the differentiated
mode of operation (ISO terminal is low) is as follows:
1. LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum
TRESTORE time, the LLC causes the interface to be initialized and restored to normal operation by
reactivating the LPS signal. In Figure 26 the interface is shown in the disabled state with SYSCLK high-
impedance inactive. However, the interface initialization sequence described here is also executed if the
interface is merely reset but not yet disabled.
2. SYSCLK activated. If the interface is disabled, the PHY reactivates its SYSCLK output when it detects
that LPS has been reasserted. If the PHY has entered a low-power state, it takes between 5.3 ms to 7.3
ms for SYSCLK to be restored; if the PHY is not in a low-power state, SYSCLK is restored within 60 ns.
The PHY commences SYSCLK activity by driving the SYSCLK output low for half a cycle. Thereafter,
the SYSCLK output is a 50% duty cycle square wave with a frequency of 49.152 MHz 100 ppm (period
of 20.345 ns). Upon the first full cycle of SYSCLK, the PHY drives the CTL and D terminals low for one
cycle. The LLC is also required to drive its CTL, D, and LREQ outputs low during one of the first six
cycles of SYSCLK (shown in Figure 26 as occurring in the first SYSCLK cycle).
3. Receive indicated. Upon the eighth SYSCLK cycle following reassertion of LPS, the PHY asserts the
Receive state on the CTL lines and the data-on indication (all ones) on the D lines for one or more
cycles (because the interface is in the differentiated mode of operation, the CTL and D lines are in the
high-impedance state after the first cycle).
4. Initialization complete. The PHY asserts the idle state on the CTL lines and logic 0 on the D lines. This
indicates that the PHY-LLC interface initialization is complete and normal operation may commence.
The PHY now accepts requests from the LLC via the LREQ line.

TSB41AB2, TSB41AB2I
ISO (high)
7 Cycles
SYSCLK
(2) (3)
CTL0
(4)
CTL1
D0−D7
LREQ
(1)
LPS
TCLK_ACTIVE
Figure 27. Interface Initialization, ISO High
The sequence of events for initialization of the PHY-LLC interface when the interface is in the
nondifferentiated mode of operation (ISO terminal is high) is as follows:
1. LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum
TRESTORE time, the LLC causes the interface to be initialized and restored to normal operation by
reasserting the LPS signal. In Figure 27, the interface is shown in the disabled state with SYSCLK low
inactive. However, the interface initialization sequence described here is also executed if the interface is
merely reset but not yet disabled.
2. SYSCLK activated. If the interface is disabled, the PHY reactivates its SYSCLK output when it detects
that LPS has been reasserted. If the PHY has entered a low-power state, it takes between 5.3 ms to 7.3
ms for SYSCLK to be restored; if the PHY is not in a low-power state, SYSCLK is restored within 60 ns.
The SYSCLK output is a 50% duty cycle square wave with a frequency of 49.152 MHz  100 ppm
(period of
20.345 ns). During the first seven cycles of SYSCLK, the PHY continues to drive the CTL and D
terminals low. The LLC is also required to drive its CTL and D outputs low for one of the first six cycles
of SYSCLK but to otherwise place its CTL and D outputs in a high-impedance state. The LLC continues to
drive its LREQ output low during this time.
3. Receive indicated. Upon the eighth SYSCLK cycle following reassertion of LPS, the PHY asserts the
Receive state on the CTL lines and the data-on indication (all ones) on the D lines for one or more
cycles.
4. Initialization complete. The PHY asserts the idle state on the CTL lines and logic 0 on the D lines. This
indicates that the PHY-LLC interface initialization is complete and normal operation may commence.
The PHY now accepts requests from the LLC via the LREQ line.

TSB41AB2,
PACKAGE
TSB41AB2IOPTION ADDENDUM
IEEE 13R4a-2000 TWO-
www.ti.com
PORT CABLE
4-Mar-2005
TRANSCEIVER/ARBITER
PACKAGING INFORMATION
Orderable Device Status (1)

Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty

TSB41AB2IPAP ACTIVE HTQFP PAP 64 160 None Call TI Level-3-235C-168 HR
TSB41AB2PAP ACTIVE HTQFP PAP 64 160 None CU NIPDAU Level-3-235C-168 HR
TSB41AB2PAPR ACTIVE HTQFP PAP 64 1000 None CU NIPDAU Level-3-235C-168 HR
The marketing status values are defined as follows:

(1)
ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS
requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed
to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1

MECHANICAL DATA
PAP (S—PQFP—G64) PowerPAD T’ PLAS1C QUAD FLATPACK
0,50 +|+ 0,08

017
48
53
49
Thermal Pod (See Note D)
O
0,13 N09
1 16
7,50 TYP
10,20 SD Goqe Plone
9,80
12,20 SO
11,80 015
0‘—7‘
0,05
0,75
0,45
Seating Plane
1,20 MAX O 0,08
4147702/C 08/03
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. This package is designed to be soldered to a thermal pad on the board. Refer to Technical Brief, PowerPad
Thermolly Enhanced Packoqe, Texos Instruments Literature No. SLMA002 for information regarding
recommended board layout. This document is available at vxv.ti.com ¢http: //own.ti.comb.
E. Falls within JEDEC MS—026
PowerPAD is a trademark of Texas Instruments.
TEXAS
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections,
modifications, enhancements, improvements, and other changes to its products and services at any time
and to discontinue any product or service without notice. Customers should obtain the latest relevant
information before placing orders and should verify that such information is current and complete. All products
are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent
TI deems necessary to support this warranty. Except where mandated by government requirements, testing
of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible
for their products and applications using TI components. To minimize the risks associated with customer
products and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent
right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or
process in which TI products or services are used. Information published by TI regarding third-party products
or services does not constitute a license from TI to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or
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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
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Wireless www.ti.com/wireless
Mailing Address: Texas Instruments

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Copyright  2005, Texas Instruments Incorporated

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TSB41AB2, TSB41AB2I

IEEE 13R4a-2000 TWO-PORT CABLE

• Fully Supports Provisions of IEEE

POST OFFICE BOX 655303  DALLAS, TEXAS 1

Copyright  2003 − 2004 Texas Instruments Incorporated

2 POST OFFICE BOX 655303  DALLAS, TEXAS

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R0 Bias Voltage and

Crystal Oscillator, PLL System, and Clock Generator

6 POST OFFICE BOX 655303  DALLAS, TEXAS

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8 POST OFFICE BOX 655303  DALLAS, TEXAS

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DISSIPATION RATING TABLE

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1 POST OFFICE BOX 655303  DALLAS, TEXAS

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Figure 1. Test Load Diagram

Figure 3. Dx and CTLx Output Delay Relative to SYSCLK Waveforms

1 POST OFFICE BOX 655303  DALLAS, TEXAS

† See Figure 5, Figure 6, and Figure 7.

1 POST OFFICE BOX 655303  DALLAS, TEXAS

1 F Cable Power Pair

Figure 5. TP Cable Connections

Outer Cable Shield

Figure 6. Compliant DC Isolated Outer Shield Termination

POST OFFICE BOX 655303  DALLAS, TEXAS 1

Outer Shield Termination

Figure 7. Nonisolated Outer Shield Termination

Figure 8. Nonisolated Circuit Connection Variations for LPS

NOTE: As long as the resistance ratio is maintained between 1.61:1 and

Figure 9. Isolated Circuit Connection for LPS

1 POST OFFICE BOX 655303  DALLAS, TEXAS

crystal selection (continued)

(C9 × C10 ) (1)

24.576 MHz X1 C(PHY) + C(BD)

Figure 10. Load Capacitance for the TSB41AB2 PHY

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crystal selection (continued)

Figure 11. Recommended Crystal and Capacitor Layout

designing with the PowerPAD package

2 POST OFFICE BOX 655303  DALLAS, TEXAS

Figure 12. Example of a Thermal Land for the TSB41AB2PAP PHY

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Table 2. Base Register Field Descriptions

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Table 3. Page 0 (Port Status) Register Configuration

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Table 4. Page 0 (Port Status) Register Field Descriptions

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