3490 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO.

9, SEPTEMBER 2022

Modeling and Signal Integrity Analysis of

RRAM-Based Neuromorphic Chip Crossbar Array
Using Partial Equivalent Element
Circuit (PEEC) Method
Yan Li , Senior Member, IEEE, Lidan Fang , Tuomin Tao , Graduate Student Member, IEEE,
Da Li , Member, IEEE, En-Xiao Liu , Senior Member, IEEE, Ning Jin ,
Manareldeen Ahmed , Member, IEEE, and Er-Ping Li , Fellow, IEEE

Abstract— This paper provides a comprehensive study of signal Index Terms— Neuromorphic chip, RRAM-based cross bar
integrity issues in RRAM-based neuromorphic chip crossbar array, partial equivalent element circuit (PEEC), Izhikevich
arrays due to interconnect parasitic. First, the parasitic para- neuron model, signal integrity (SI).
meters of the crossbar array are calculated by the partial equiv-
alent element circuit (PEEC) method with an efficient unit-cell
I. I NTRODUCTION
approach. Numerical experiments show that for a 50 × 50 array
scale, this method consumes only 1.5% of the calculation time
of the commercial software based 3D model, which translates
to a calculation speed up of 72 times. Moreover, the PEEC
P RESENTLY the spiking neural network (SNN) is hailed
as the third-generation neural network model and the
neuromorphic chip is the preliminary realization of SNN
circuit simulation results match well with those of the 3D model.
Then, we investigate the effects of parasitic parameters such in hardware. Its storage-calculation integration solves the
as capacitance and inductance, as well as the feature size of “storage wall” problem caused by the separation of calcula-
the crossbar array on signal integrity. All of them will lead to tion and storage units in the von Neumann architecture [1].
corresponding changes in parasitic effects, which in turn result The neuromorphic chip is designed to accelerate artificial
in the most common signal integrity issues such as crosstalk, intelligence algorithms [2] and emulate the structure of bio-
time delay and mutual capacitive coupling induced sneak path
problem. Different from other studies, the excitation used in this logical neural networks through circuits [3]. It has the advan-
paper is the neural spike signal generated by the Izhikevich tages of low power consumption and high efficiency [4], [5].
neuron model, which is both rich in dynamic characteristics and The neuromorphic chip uses spiking signals to simulate bio-
high in computational efficiency. Finally, based on the study we logically spiking neurons. There are several well-known and
propose a simple but effective design scheme for reduction of representative neuron models, mainly Hodgkin-Huxley (HH)
signal distortion, which can provide valuable design guidance
for neuromorphic systems to achieve high performance and high model [6], the integrate-and-fire (IF) model [7], the leaky
computational accuracy. integrate-and-fire (LIF) model [8], and the Izhikevich neuron
model [9]. Compared with traditional digital signal, the spiking
Manuscript received 8 March 2022; revised 20 May 2022; accepted signal has an extremely short duration with narrow rising and
31 May 2022. Date of publication 9 June 2022; date of current version
30 August 2022. This work was supported in part by the National Natural falling edges that contains infinite high-frequency harmonic
Science Foundation of China (NSFC) under Grant 62071424 and Grant components. Therefore, it inevitably leads to a series of
62027805 and in part by the Zhejiang Provincial Natural Science Foun- electromagnetic integrity problems, such as more severe signal
dation of China (ZPNSFC) under Grant LD21F010002. This article was
recommended by Associate Editor R. Joshi. (Corresponding authors: Yan Li; noise, transmission crosstalk, and signal leakage [10].
Er-Ping Li.) The emerging resistive random access memory (RRAM)
Yan Li, Lidan Fang, and Ning Jin are with the Key Laboratory of Electro- [11], also known as memristor, is a variable resistor [12].
magnetic Wave Information Technology and Metrology of Zhejiang Province,
College of Information Engineering, China Jiliang University, Hangzhou It is a neuromorphic device that is widely used as artificial
310018, China (e-mail: liyan@cjlu.edu.cn; s20030810005@cjlu.edu.cn; synapses [13]in various fields of neuromorphic systems. The
jinning1117@cjlu.edu.cn). RRAM-based crossbar array emulates the structure of a bio-
Tuomin Tao, Da Li, Manareldeen Ahmed, and Er-Ping Li are with the
Key Laboratory of Advanced Micro/Nano Electronic Devices and Smart logical neural network which can be stacked up as a three-
System, Zhejiang University, Hangzhou 310027, China, and also with the dimensional model to achieve a high-density structure [14].
Zhejiang University–University of Illinois at Urbana–Champaign Institute, However, the reliability of crossbar arrays will deteriorate due
Zhejiang University, Haining 314400, China (e-mail: tuomin@zju.edu.cn;
li-da@zju.edu.cn; ahmed@intl.zju.edu.cn; liep@zju.edu.cn). to the high interconnect density, unstable device performance,
En-Xiao Liu is with the A*STAR Institute of High Performance Computing, and complex circuit structures [15], [16]. Therefore, it is
Singapore 138632 (e-mail: liuex@ihpc.a-star.edu.sg). imperative to study the influence of the parasitic effects and
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TCSI.2022.3180199. investigate signal integrity (SI) issues so as to improve the
Digital Object Identifier 10.1109/TCSI.2022.3180199 performance of neuromorphic chips.
1549-8328 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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LI et al.: MODELING AND SI ANALYSIS OF RRAM-BASED NEUROMORPHIC CHIP CROSSBAR ARRAY USING PEEC METHOD 3491

The main factors affecting the performance of the neuromor- TABLE I

phic system can be classified into two groups (see [17]–[21]): C ORRESPONDING PARAMETERS OF F OUR S PIKING B EHAVIORS
One is the effect caused by the non-linearity of RRAM, and
the other is the IR drop caused by the line resistance. In [17],
a neural network-based calculation paradigm for crossbar
arrays is proposed to evaluate the effects of device changes
and nonlinearities. In [21], the influence of line resistance in
the crossbar array is analyzed, and a simple scaling method is
proposed to reduce the error. In [22], signal integrity issues, use in the numerical simulation of large-scale neural networks
i.e., crosstalk are studied, circuit elements, are calculated [9]. Therefore, it is chosen in this paper as the neuron model.
in three parallel long wires, and the coupled voltages are The Izhikevich model is described by:
simulated when the pulses are excited on adjacent wires.
A parasitic circuit model including resistance, inductance, and dv
= 0.04v2 + 5v + 140 − u + I
capacitance is proposed in [23] by ANSYS Q3D. And a dt
complete circuit model is established in [24], where the PEEC du
= a(bv − u) (1)
method is used to solve the whole large-scale array structure dt
that is complicated and time consuming. instead of a unit-cell with the auxiliary after-spike resetting
structure. 
At present, widely used numerical calculation methods of v ←c
ifv ≥ 30mV, then (2)
electromagnetic fields mainly include the finite difference u ←u+d
method (FDM), finite element method (FEM), and partial
where v denotes the neuron membrane potential, and u is
element equivalent circuit (PEEC) method [25]–[27]. The
the recovery variable of v that provides negative feedback to
PEEC method is a circuit based approach, which can be
v. I is the externally applied input current. Upon the spike
directly combined with resistance, capacitance, inductance,
reaching its apex (+30 mV), the membrane voltage v and the
and transmission lines in traditional circuit theory for calcu-
recovery variable u are reset following (2). What needs to
lation. The PEEC method only requires the discretization of
be emphasized here is that +30mV is a peak value of the
conductors, not the space medium, thereby greatly simplifying
spike. The neuron model actually has a threshold between
the model and reducing the calculation time.
−70mV and −50mV, which makes it as dynamic as biological
In this paper, the unit-cell based PEEC method is used to
neurons. In addition, a is the time scale of u, b is the degree
analyze the parasitic elements in the RRAM-based crossbar
of dependence of u on v, c is the reset value, and d is the
array, which can greatly reduce model complexity and improve
change amount of u for each pulse.
computational efficiency. To demonstrate the effectiveness
With the above formulas and by collectively adjusting the
of the proposed PEEC circuit model, transient simulations
four parameters: a, b, c and d, we obtain the spiking behavioral
are performed by combining it with the Modified Nodal
patterns of four different types of cortical neurons defined by
Analysis (MNA) method, and the results are compared with
the Izhikevich neuron model, as shown in Fig. 1. The values of
ANSYS HFSS. The Izhikevich neuron model is exploited to
the corresponding parameters in these four cases are shown in
simulate the transmission characteristics of the neuron spiking
Table I. RS (Regular spiking) neurons are of the most typical
signal to better analyze the signal integrity (SI) issues in the
neuron type. They fire a couple of spikes with a brief inter-
crossbar array. Through simulation and analysis based on the
spike period, and afterward the period will gradually increase
PEEC circuit model, the main SI problems are thoroughly
if it is subject to a prolonged stimulus. IB (Intrinsically
investigated. In addition, we propose a simple but effective
bursting) neurons fire a stereotyped bursting spike followed
design scheme for reducing signal distortion
by repeated single spikes. FS (Fast spiking) neurons can fire
The paper is organized as follows: Section II introduces
periodic action potential sequences at extremely high frequen-
and builds four different spiking behavioral patterns of the
cies with little or no adaptation (slowing). CH (Chattering)
Izhikevich neuron model. In Section III, the unit-cell parasitic
neurons can fire stereotyped, densely burst-spaced spikes.
model of the RRAM-based crossbar array is presented. The
In this paper, the spiking signals defined by the Izhikevich
PEEC circuit model is validated and compared with the 3D
neuron model serve as the excitation of the RRAM based
model in Section IV. Section V analyzes the factors that affect
crossbar array circuit. It is advantageous to use four different
the reliability of the circuit. Section VI summarizes the paper.
spiking behaviors as input when designing the Neuromor-
phic circuit, because it provides significant assurance that
II. I ZHIKEVICH N EURON M ODEL C ONSTRUCTION the designed circuit will be robust for different operational
scenarios.
Among the many neuron models, the Izhikevich neuron
model was proposed in 2003 to simulate the discharge char-
acteristics of cortical neurons. It outperforms all other neuron III. B UILDING U NIT-C ELL PARASITIC C IRCUIT
models in terms of rich dynamic characteristics and high BY THE PEEC M ETHOD
computational efficiency, because it combines the advantages The crossbar array is a dense but periodic structure, and
of both the HH model and the LIF model. It is most suitable for it can be divided into multiple basic units, which will greatly

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3492 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 9, SEPTEMBER 2022

Fig. 3. A unit-cell parasitic model with RRAM.

as an output to each row, converting the analog signal to an

n-bit digital signal. In this paper, the detailed circuit model
of the ADC is not considered, because the focus is placed on
understanding the electromagnetic parasitic effects associated
with the crossbar array. For this purpose, only simplified
Fig. 1. Four different types of cortical neurons defined by the Izhikevich circuit model of the ADC is used, i.e., it is considered as
neuron model: (a) RS, (b) IB, (c) FS, (d) CH.
an equivalent 5 load resistance.

A. Unit-Cell Resistance Model

The unit resistance R of the crossbar array can be directly
calculated by:
ρl
R= (3)
s
where ρ is the conductor resistivity, l and s are unit wire
length and cross-sectional area separately. The skin effect will
cause uneven current in the conductor at high frequency or fast
transient changes [28]. Skin depth δ = √π 1f μσ , where f is the
frequency, μ is the permeability which is usually replaced by
Fig. 2. A large-scale RRAM-based crossbar array. μ0 for non-magnetic material, and σ is the conductivity of the
conductor. The skin effect appears after a certain frequency.
reduce the workload of extracting parasitic circuits. Due to the The cut-off frequency can be obtained according to the skin
numerous input attributes and training weights, a larger-scale effect that occurs at the skin depth. Thus, the cut-off frequency
RRAM-based crossbar array is usually required to implement f = (πh 24μσ ) is 7 THz if the feature size of the crossbar is
the corresponding functions, as shown in Fig.2. h = 5 nm, and 70 GHz if h = 500 nm, which are both much
The electromagnetic effects in dense interconnects like higher than our applicable range, so the skin effect is ignored
crossbar arrays can cause severe SI problems. Therefore, it is in this paper.
necessary to build the corresponding parasitic circuit model
in order to study their influences. In this paper, a unit-cell
equivalent circuit model proposed in [18] is used for analysis. B. Unit-Cell Inductance Model
We combine the PEEC method to build a circuit model. The In the circuit model, since the currents between the upper
unit-cell parasitic circuit model with RRAM is shown in Fig.3. and lower metal lines are perpendicular to each other, there
The crossbar array is divided into two parts: word line (WL) is no mutual inductance between the word line and the bit
and bit line (BL). The word line is the signal input terminal, line. Thus, we only consider the mutual inductance between
the bit line is the signal output terminal, and the RRAM is two adjacent lines. The analytical formulas for self-inductance
connected in the middle. and mutual inductance are obtained in [28].
Rline represents the unit resistance, and RRAM is regarded Fig.4. (a) shows the crossbar array self-inductance model,
as a variable resistor. Lwl and Lbl represent the self-inductance where l, t, and w are the length, width, and height of the
of the word line and the bit line respectively, L1 and L2 rectangular bar respectively.
represent the mutual inductance between two adjacent word The calculation for this case is obtained by (4), as shown
lines and bit lines. C1 and C2 represent the mutual capacitance at the bottom of the next page, and u = wl , k = wt , with
between two adjacent word lines and bit lines, Cwl and Cbl   
represent the self-capacitance of the word and the bit line, and a1 = 1 + u 2 , a2 = 1 + k 2 , a3 = k 2 + u 2
 l + a4
Cm represents the capacitance between the word line and the a4 = l + k 2 + u 2 , a5 = log (5)
bit line. An analog-to-digital converter (ADC) is connected a3

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LI et al.: MODELING AND SI ANALYSIS OF RRAM-BASED NEUROMORPHIC CHIP CROSSBAR ARRAY USING PEEC METHOD 3493

Fig. 4. (a) Self-inductance model and (b) mutual inductance model of a

unit-cell crossbar array.

Another case happens when two rectangular bars are paral-

lel, as shown in Fig.4(b). xs1 , ys1 , zs1 , xe1 , ye1 , ze1 and xs2 ,
ys2 , zs2 , xe2 , ye2 , ze2 represent the coordinates of cuboid 1 and
cuboid 2 respectively. The formula is given as (6), shown at
the bottom of the page, with

a1 = x s2 − x e1 , a2 = x e2 − x e1 Fig. 5. (a) Node and numbering of capacitive surface mesh cells for three
a3 = x e2 − x s1 , a4 = x s2 − x s1 cuboids. (b) Quasistatic PEEC model for simple conductor geometry.

b1 = ys2 − ye1 , b2 = ye2 − ye1

C. Unit-Cell Capacitance Model
b3 = ye2 − ys1 , b4 = ys2 − ys1
The unit capacitance model is built by the PEEC method.
c1 = z s2 − z e1 , c2 = z e2 − z e1
The grid discretization of three cuboids and the quasistatic
c3 = z e2 − z s1 , c4 = z s2 − z s1 (7) PEEC model for simple conductor geometry is shown in Fig.5.
To further reduce the complexity of the circuit model,
and we assume that each surface cell is assigned a uniform charge
density, incorporating the partial potential coefficients of each
A1 = (ye1 − ys1 ) ∗ (z e1 − z s1 ) , plane into the partial potential coefficients of each cuboid. The
A2 = (ye2 − ys2 ) ∗ (z e2 − z s2 ) (8) relationship between the potential and the charge is as follows:

R = ai2 + b 2j + ck2 (9) [Q] = [Cs ] [V ] (10)

     
μ0lk 2 1 + a2 u + a3
L 11 = ∗ log + log + log (u + a1 ) − a5 − 2a7
24πu k k
μ0 l

+ ∗ k 4
(a 4 − a 3 − a 2 + k) + u 2
(u + a 4 − a 1 − a 3 ) + 1 + a 4 − a 1 − a 2
30k 2 πu⎧     ⎫
⎨ u log k+a3
− a   ⎬
μ0 l log (k + a2 ) − a6 u 6 1 + a1
+ ∗ + + log − a5
12π ⎩ uk k u ⎭
  
μ0 l a2 − a4 u (a1 + a3 − 2a4 ) ua5 1 uk
+ ∗ + + − tan−1 (4)
π 10u 10k 2 2 3k a4

⎧       
⎪
⎪ b j ck ai 2 −1 b j ck −1 ck ai −1 b j ai
⎪
⎪ − a tan + b 2
tan + c 2
tan
⎪
⎪ 6 i
 2 2 ai R  j bj R k
ck R
⎪
⎪
⎪
⎪ b c b 4
c 4
⎪
⎪ +
j k
−
j
− k
4  4  4 ⎪⎨ 4 24 24
μ0 ⎡ ⎛ ⎞ ⎛ ⎞ ⎛ ⎞⎤
L 12 = ∗ (6)
4π A1 A2 ⎪
⎪ a + R b + R c + R
⎪ ∗ ⎣a log ⎝ 
i=1 j =1 k=1 ⎪ i ⎠ + bi log ⎝  i ⎠ + ck log ⎝  k ⎠⎦
⎪
⎪ i
⎪
⎪ b 2 + c2
ck + a i
2 2 a 2 + b2
⎪
⎪ j k i j
⎪
⎪
⎪ 1  4 
⎩ + b + ck + ai − 3b j ck − 3ck ai − 3b j ai R
4 4 2 2 2 2 2 2
60 j

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3494 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 9, SEPTEMBER 2022

The two parallel rectangular conductor model is shown in

Fig. 6(a). xs1 , ys1 , zs1 , xe1 , ye1 , ze1 and xs2 , ys2 , zs2 , xe2 ,
ye2 , ze2 represent the coordinates of cuboid 1 and cuboid
2 respectively. Pi j represents the mutual potential coefficient of
conductors i and j. The formula for this case is given by (15),
where the capacitance between adjacent signal lines can be
obtained. Note that e is a very small number (e.g., 10−37) to
prevent singularities due to machine errors.

P12
m+k
1 
Fig. 6. (a) The two parallel rectangular conductor (cuboid) model and (b) The 4 4 2 − Z2
1 bm
two orthogonal rectangular conductor (cuboid) model. = (−1) [ ak log(ak + rkm + e)
4πe S1 S2 2
k=1 m=1
Among them, [Q] and [V ] are the charge vector and a2 − Z 2 1 2
potential of each plane unit. [Cs ] is short-circuit capacitance + k bm log(bm + rkm + e) − (bm − 2Z 2 + ak2 )rkm
2 6
matrix. Assuming that the electric potential of each cuboid is ak bm
Va , Vb and Vc respectively. The surface capacitance at both −bm Z ak tan−1 ( )] (15)
rkm Z
ends of the cuboid is ignored. Then (11) can be converted to:
⎡ ⎤ ⎡ ⎤⎡ ⎤ where
Qa Csaa Csab Csac Va
⎣ Q b ⎦ = ⎣ Csba Csbb Csbc ⎦ ⎣ Vb ⎦ (11) a1 = x s2 − x e1 , a2 = x e2 − x e1
Qc Csca Cscb Cscc Vc a1 = x e2 − x s1 , a4 = x s2 − x s1
where Q a , Q b , Q c represent the sum of the surface charges b1 = ys2 − ye1 , b2 = ye2 − ye1
of each cuboid. The short-circuit capacitance of each cuboid b3 = ye2 − ys1 , b4 = ys2 − ys1 (16)
can be expressed as:
⎡ ⎤ and
Csaa Csab Csac
⎣ Csba Csbb Csbc ⎦
S1 = (x e1 − x s1)(ye1 − ys1 )
Csca Cscb Cscc
⎡ ⎤ S2 = (x e2 − x s2 )(z e2 − z s2 ) (17)
$ 4 $ 4 $ 4 $ 8 $ 4 $12
⎢ C si j C si j C si j ⎥ Z = z2 − z1 + e (18)
⎢ i=1 j =1 i=1 j =5 i=1 j =9 ⎥ 
⎢ 8 4 ⎥ rkm = ak2 + bm2 + Z2
⎢$ $ $ $
8 8 $ $
8 12 ⎥ (19)
=⎢ ⎢ C C C si j ⎥
si j si j ⎥ (12)
⎢ i=5 j =1 i=5 j =5 i=5 j =9 ⎥ The other model is made of two rectangular conductors
⎢$ ⎥
⎣ 12 $ 4 $12 $ 8 $12 $12
⎦ perpendicular to each other, as shown in Fig. 7(b). For this
C si j C si j C si j
i=9 j =1 i=9 j =5 i=9 j =9 case, the parasitic capacitance due to the upper and lower
vertical signal lines can be obtained by the following formula:
Therefore, the self-capacitance and mutual capacitance Ca ,
Cb , Cc , Cab , Cbc , Cca in the circuit model are: P12
(1+m+k+L)

4 
12 
8 
12 
12 
12

4 
2 
2
Ca = C si j , C b = C si j , C c = C si j = (−1) [ak bm c L log(ak + rkm L + e)
i=1 j =1 i=4 j =1 i=8 j =1 k=1 m=1 L=1

4 
8 
8 
12 ak2 c2L bm c L ak bm
Cab = − Csi j , Cbc = − C si j , +( − )c L log(bm +rkm L +e) − tan −1 ( )
2 6 3 c L rkm L
i=1 j =5 i=5 j =9
a2 b2 ak c2L ak bm

12 
4 +bm ( k − m ) log(c L +rkm L +e) − tan −1 ( )
Cca = − C si j (13) 2 6 2 c L rkm L
a3 bm c L b 2 ak ak c L
i=9 j =1 − k tan −1 ( ) − m tan −1 ( )] (20)
6 ak rkm L 2 bm rkm L
And the short circuit capacitance matrix [Cs ] is also repre-
sented as: with

[Cs ] = [P]−1 (14) b1 = y2 − ys1 , b2 = y2 − ye1

where [P] is the potential coefficient matrix. Two general c1 = z e2 − z 1 , c2 = z s2 − z 1 (21)

cases (see Fig. 6) are considered here for the calculation of rkm = ak2 + bm 2 + c2
L (22)
the potential coefficients. Combining (15), (20) below ([26])
and (14), we can finally obtain the corresponding parasitic The above process of extracting capacitances for two typical
capacitance. cases is applicable to other crossbar array structures.

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LI et al.: MODELING AND SI ANALYSIS OF RRAM-BASED NEUROMORPHIC CHIP CROSSBAR ARRAY USING PEEC METHOD 3495

TABLE II
D IMENSIONS OF THE U NIT-C ELL S TRUCTURE

TABLE III
PARASITIC PARAMETERS OF THE U NIT-C ELL

Fig. 8. Comparison of PEEC circuit model simulation and 3D model in

ANSYS HFSS under four spiking behaviors. (a) RS. (b) IB. (c) FS. (d) CH.
TABLE IV
E FFICIENCY C OMPARISON OF PEEC C IRCUIT M ODEL AND
3D M ODEL IN ANSYS HFSS

Fig. 7. A unit-cell of the RRAM-based crossbar array.

IV. V ERIFICATION OF THE PEEC C IRCUIT M ODEL

The PEEC circuit model derived in the previous section is
compared with the 3D model in ANSYS HFSS [29]. HFSS is
resistance, inductance, and short-circuit capacitance matrices.
a simulation software based on the full-wave Finite Element
V and I are the node voltage and branch current to be solved.
Method (FEM) which divides air and other materials into
The transient simulation results of the PEEC circuit and the
electrically small elements [30]. In contrast, the PEEC method
ANSYS HFSS 3D model under the four spike behaviors are
starts from the Electric Field Integral Equation (EFIE) and
shown in Fig.8. The overall curve trends and values of both
converts the wave fields into corresponding equivalent circuit
output currents are well matched, which validates the ability
models [31]. The EFIE describes the electromagnetic fields
and accuracy of the PEEC circuit model in simulating the
in open and closed volumes by establishing corresponding
transmission characteristics of the crossbar array.
equations with boundary conditions.
Table IV compares their computation time and power con-
J (r, t) ∂ A(r, t) sumption in the case of 50×50 array scale. It shows obviously
E(r, t) = − − ∇(r, t) (23)
σ ∂t that the calculation efficiency of the PEEC circuit model is
The unit-cell interconnect used in the simulation is shown in much higher than that of the 3D full-wave model in ANSYS
Fig. 7 with corresponding dimensions listed in Table II. HFSS, and its calculation time is only 1.5% of the 3D model.
Table III shows the parasitic parameters in the circuit This is because ANSYS HFSS is more suitable for small
extracted by the PEEC method. Additionally, we set the objects with wavelengths within 2λ in full-wave simulations.
RRAM in High resistance state (HRS) to 100 K and Low It is not recommended for large models as it will result in long
resistance state (LRS) to 1 K. simulation time with high consumption of computer resource.
The parasitic circuit is modeled using a modified nodal In contrast, the PEEC method can greatly reduce the model
analysis (MNA) method [32], which underpinned by Kirch- complexity and improve the efficiency for simulating large
hoff’s voltage law (KVL) and current law (KCL). The circuit structures.
equation takes the following form: In all the experiments, a personal computer with 32 GB of
 & '    RAM and 2.9-GHz CPU is used.
−A − R + L dt d
V VS
= (24)
d
C dt −A T I 0 V. SI A NALYSIS OF THE C ROSSBAR A RRAY
where A represents the connectivity matrix, Vs represents At present, there have been many related researches on
the voltage source excitation. R, L, and C are the obtained RRAM. However, there are few researches on the SI problems

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3496 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 9, SEPTEMBER 2022

TABLE V
PARASITIC PARAMETERS OF D IFFERENT M ODELS

Fig. 9. Equivalent circuit diagram of a large-scale crossbar array.

caused by dense interconnects in RRAM-based crossbar array,

especially on the transmission of the spiking signal in crossbar
arrays. When the feature dimensions of crossbar interconnec-
tion expand into the nanometer regime, the impact of coupling
capacitance, coupling inductance, and the physical size of the
crossbar array on the circuit becomes critical, which require Fig. 10. The output currents of different models with and without considering
inductance. (a) Model A. (b) Model B. (c) Model C.
further study. Therefore, we perform circuit simulation for the
above analysis, and the representative circuit model is shown
in Fig. 9. inductance is considered or not. Conversely when the model
The information transmitted in the neuromorphic chip is is enlarged to the micrometer scale in Model C, the two
expressed in a spike sequence format. The RS neuron model curves are significantly different as shown in Fig.10 (c).
introduced in Section II is applied to the circuit model as the Furthermore, in the case of a complete circuit, the output
voltage source. And we monitor the output current of the signal current of Model C exhibits significant ripples compared with
line farthest from the input terminal. The complete circuit Model A and Model B, and the crosstalk in Model C increases.
model is implemented in the MATLAB platform. Therefore, the effect of parasitic inductance on the circuit
We set the base model mentioned in Fig. 7 as Model A cannot be ignored in this situation. Table V shows that the
(l=200nm, w=100nm, t=50nm). The other models are real- parasitic inductance increases by an order of magnitude with
ized by scaling Model A. Model B is scaled down by ten times the increase in dimension, and the signal is distorted due to
(l=20nm, w=10nm, t=5nm), whereas Model C is scaled up tangible parasitic effect. Therefore, it can be concluded that for
by 10 times (l=2um, w=1unm, t=0.5um), as compared to crossbars with small dimensions, the parasitic inductance can
Model A. Consequently, the total number of inductance and be ignored for the benefit of reducing circuit complexity and
capacitance volume grid cells in the crossbar structure remains simulation time. However, in the case of large interconnect
unchanged. The parasitic elements for the different models are dimension, inductance must be considered when parasitic
summarized in Table V. Subsequent simulations and analyses circuits are constructed because of the large impact.
are based on these three models.
B. The Impact of Capacitance on the Circuit
A. The Impact of Inductance on the Circuit The sneak path is a common issue in the crossbar array.
The influence of parasitic inductance is analyzed by tran- Analysis of mutual capacitance (Cm ) can shed light on the
sient simulation, and the simulation results are shown in cause of the issue due to the effect of parasitic capacitance.
Fig. 10. As the interconnect dimension in Models A and B Under a 50 × 50 array scale, the read current of low resistance
is small, their output current curves are almost identical state (LRS) and high resistance state (HRS) with different
(see Fig. 10(a) and (b)), regardless of whether the parasitic capacitance values are shown in Fig. 11.

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LI et al.: MODELING AND SI ANALYSIS OF RRAM-BASED NEUROMORPHIC CHIP CROSSBAR ARRAY USING PEEC METHOD 3497

Fig. 12. Sneak path problem.

Fig. 11. The LRS and HRS read currents with different coupling capacitance
(a) Cm = 0.02 fF, (b) Cm = 0.2 fF, (c) Cm = 2 fF, (d) Cm = 20 fF, Fig. 13. The output currents of the four models at different crossbar array
(e) Cm = 200 fF. scales (50 × 50 and 100 × 100): (a) Model A (b) Model B and (c) Model C.

to Table III, as the interconnection dimension increases,

To study the impact of Cm , it is set to be 0.02 fF, 0.2 fF,
the coupling capacitance value will also increase. Therefore,
2 fF, 20 fF, and 200 fF. Note that Cm = 0.02 fF is the actual
an appropriate size of the interconnect structure should be
value of Model A. Fig.11 (a) clearly shows the read currents
selected to reduce misreading. In practical applications, it is
of the LRS and HRS are relatively stable, and the current
difficult for the unit structure of the array to generate a
amplitude of LRS is much larger than that of HRS. When Cm
coupling capacitance of 200 fF, but the previous analysis tells
increases to 0.2 fF, the HRS reading current increases, while
us that the coupling capacitance will increase with the increase
the reading current in LRS does not change significantly as
in the interconnection dimension. This may eventually lead to
shown in Fig.11. (b). However, as the value of Cm increases,
the emergence of potential sneak paths.
the gap between the read currents of HRS and LRS decreases,
such as in Fig. 11(c) and (d). Finally, when Cm increases to
200 fF, the HRS read current completely exceeds the LRS read C. The Impact of the Crossbar Array Feature Size
current during the entire pulse width (seeFig.11(e)), which Changes in the feature size of the crossbar array can result
leads to the generation of the sneak path and reading failure in changes in parasitics. We mainly analyze the influence of
for the whole period. feature size from two aspects: one is the scale of the crossbar
The comparison between the ideal current path and the array, and the other is the interconnection dimension.
sneak path is shown in Fig.12. When the value of Cm is The output currents of Model A, Model B, and Model C
increased, the crossbar interconnection will generate a higher under different array scales are shown in Fig. 13. The outputs
transient sneak current, which may lead to misreading of infor- of Model A and Model B are close to the original input curve,
mation and affect the accuracy of the device. The above exper- and there is no obvious ripple as shown in Fig. 13(a) and (b).
iment clearly emphasizes that the high-density RRAM-based However, as the dimension and array scale increase, crosstalk
crossbar array will face serious reading challenges due to and signal distortion become more severe, and time delay
the large coupling capacitance. During the read operation, occurs. As shown in Fig.13(c), Model C has a 7ns delay at
the large charging current will also change the state of the the 100 × 100 array compared to the 50 × 50 array. Simulation
RRAM, which is unavoidable and the worst case. According results reveal that when the interconnection dimension is

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3498 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 9, SEPTEMBER 2022

Fig. 14. Output currents for different line length to width ratios at Fig. 15. Output current curves with different distances between bit line and
50 × 50 array scale. ground (the waveform ripple is circled in the figure).

small, the parasitic effect has less influence at different array the capacitance significantly. As a result, it reduces crosstalk,
scales. But as the dimension increases, the effect of the array avoids signal distortion and improves device performance.
scale also increases.
Then, the effect of the length (L) to width (W) ratio VI. C ONCLUSION
is discussed by changing the L to W ratio of Model C This paper is devoted to the study and analysis of the signal
while maintaining its width as 1um. Fig. 14 presents the integrity (SI) issues due to densely interconnected crossbar
simulation result of the interconnection line with different L arrays in RRAM-based neuromorphic chip. The parasitic para-
to W ratios under the 50 × 50 array scale. When the ratio meters are calculated by the PEEC method with a unit-cell
increases, the time delay becomes visible. In particular, when approach, and the transient simulation is carried out in com-
the ratio of L to W increases to 10, a 15-ns delay occurs bination with the MNA method. For an array size of 50 × 50,
as a consequence. This result is in line with the previous this method only consumes 1.5% of the calculation time of the
analysis, as the increase in dimension will lead to an increase 3D model based on ANSYS HFSS, and the calculation speed
in the value of parasitic parameters. And the parasitic effects is increased by 72 times, greatly improving the calculation
associated with larger-scale array structures will naturally efficiency. Furthermore, the transient simulation results of the
increase. Neuromorphic systems that perform more complex PEEC circuit model match well with those of the 3D model.
tasks will be more complex with a larger-scale crossbar array. The SI analysis is conducted by changing the parasitic
Then electromagnetic noise coupling at the crossbar array can capacitance, parasitic inductance, and feature size of the
significantly affect system performance. Therefore, a small- crossbar array. With the increase of array scale, the increase
dimension interconnect should be used to reduce the impact in parasitic effects leads to a series of SI problems, such as
induced by the array scale. crosstalk, time delay and sneak path. As the interconnect width
increases from 10nm to 1um and the array scale increases from
50 × 50 to 100 × 100, the parasitic effect between the signal
D. Crosstalk Reduction Method lines increases by an order of magnitude. Consequently, the
As process technology becomes finer, the density of RRAM ripple of the output becomes prominent and a significant delay
will increase, interconnect lines will be spaced closer together, occurs. Besides, when the coupling capacitance increases,
and parasitic capacitance will increase. According to the additional potential sneak paths are generated between differ-
results in previous sub-sections, crosstalk and delay are the ent lines that lead to misreading as well as loss of the operation
main SI issues. The fundamental solution to these problems accuracy of the RRAM. Therefore, it is effective to reduce
is to reduce parasitic inductance and parasitic capacitance. parasitics by increasing the distance between the bit line and
We choose Model C with the most severe signal distortion ground, which in turn reduces signal distortion and avoids
in the above experiments for further simulation by increasing device misreading. In addition, it is worth mentioning that the
the distance between the bit line and the ground from 50nm Izhikevich neuron model is used to mimic the spiking signal
to 5um. The simulation results are shown in Fig. 15. as the voltage source of the circuit, because of its superior
When d is 50nm, the output current has obvious ripples. dynamic characteristic and calculation efficiency.
For this case, there will be relatively large jitter between the In conclusion, crossbar array design requires trade-off
intervals generated by each spike. However, as the distance among density, space, and dimension to ensure signal integrity.
between the interconnect and ground increases from 50nm It is a good practice to use small-dimension and small-scale
to 5um, the jitter slowly disappears and flattens out (see the array structures. The parasitic effects decrease with an increase
circled portion in Fig. 15). As can be seen in the figure, in the spacing between interconnects and ground or a reduction
when d is 5um, the line-to-line crosstalk decreases obviously. in the interconnect length to width (L/W) ratio, which leads
The increase in the distance between the bit line and the to improved accuracy and reduced error rate of neuromorphic
ground changes little the parasitic inductance, but it decreases crossbar array circuitry.

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LI et al.: MODELING AND SI ANALYSIS OF RRAM-BASED NEUROMORPHIC CHIP CROSSBAR ARRAY USING PEEC METHOD 3499

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3500 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 69, NO. 9, SEPTEMBER 2022

Da Li (Member, IEEE) received the B.S. and Ph.D. Manareldeen Ahmed (Member, IEEE) received
degrees in electrical engineering from Zhejiang Uni- the Ph.D. degree in electrical engineering from the
versity, Hangzhou, China, in 2014 and 2019, respec- Hebei University of Technology, Tianjin, China,
tively. From 2017 to 2018, he worked at Nanyang in 2019. He is currently a Post-Doctoral Researcher
Technological University, Singapore, as a Project with the Zhejiang University–University of Illinois
Researcher. From 2019 to 2021, he joined the Sci- at Urbana–Champaign Institute, Zhejiang Univer-
ence and Technology on Antenna and Microwave sity, Haining, China. His current research interests
Laboratory, Nanjing, China, as a Research Fellow. include neuromorphic computing, spiking neural
He is currently an Assistant Professor at Zhejiang networks, and AI chips.
University. He has authored or coauthored more
than 30 refereed papers. His research interests
include machine learning, antennas, metasurfaces, and electromagnetic com-
patibility. He has served as a TPC member for two IEEE conferences. He has
served as a reviewer for six technical journals.

En-Xiao Liu (Senior Member, IEEE) received the

bachelors and master’s degrees from Xi’an Jiaotong
University in 1996 and 1999, respectively, and the
Ph.D. degree in electrical engineering from the
National University of Singapore (NUS) in 2005.
From 1999 to 2001, he was with the North China
Electric Power Design Institute, Beijing, China.
In 2005, he joined the Institute of High-Performance Er-Ping Li (Fellow, IEEE) received the Ph.D. degree
Computing (IHPC), A*STAR, Singapore, where he in electrical engineering from Sheffield Hallam Uni-
is currently a Senior Scientist and the Deputy versity, Sheffield, U.K., in 1992.
Department Director of the Electronics and Photon- Since 1989, he has been working as a Research
ics Department. He is also an Adjunct Associate Professor at the Electrical Fellow, a Principal Research Engineer, an Asso-
and Computer Engineering Department, NUS. He has published more than ciate Professor, and the Technical Director at
120 papers and three book chapters. His research interests are in the areas of the Singapore Research Institute and University.
computational electromagnetics, high-speed electronics, and electromagnetic In 2000, he joined the Singapore A*STAR Research
compatibility (EMC). Institute of High-Performance Computing as a Prin-
Dr. Liu has received the Singapore President’s Technology Award (2019), cipal Scientist and the Director. He is currently a
the ASEAN Outstanding Engineering Achievement Award and IES Prestigious Qiushi Distinguished Chair Professor at the Depart-
Engineering Achievement Award (2019), the IEEE EMC Society Technical ment of Information Science and Electronic Engineering, Zhejiang University,
Achievement Award (2016), and the Best Paper and Best Industry Project China; and the Dean of the Joint Institute of Zhejiang University–University
Awards. He has been serving the IEEE EMC Singapore Chapter as the of Illinois at Urbana–Champaign. His research interests include electrical
Chair and an Executive Committee Member. He has been contributing modeling and design of micro/nano-scale integrated circuits, 3D electronic
regularly to various international conferences in different capacities, such package integration, and nano-plasmonic technology.
as the organizing chair, the technical program chair, an international advi- Dr. Li is a fellow of MIT Electromagnetics Academy, USA. He is the Found-
sory/steering committee member, and the general chair. He is an Associate ing Member of IEEE MTT-RF Nanotechnology Committee. He was a recipient
Editor of IEEE T RANSACTIONS ON E LECTROMAGNETIC C OMPATIBILITY, of the 2015 IEEE Richard Stoddard Award on EMC, the IEEE EMC Technical
IEEE T RANSACTIONS ON S IGNAL AND P OWER I NTEGRITY, and IEEE Achievement Award, the Singapore IES Prestigious Engineering Achievement
T RANSACTIONS ON C OMPONENTS , PACKAGING AND M ANUFACTURING Award, the Changjiang Chair Professorship Award from the Ministry of
T ECHNOLOGY. He was an IEEE EMC Society Distinguished Lecturer. Education in China, and number of best paper awards. He was elected to the
IEEE EMC Distinguished Lecturer in 2007. He has been the general chair and
the technical chair for many international conferences. He was the President
for 2006 International Zurich Symposium on EMC, the Founding General
Chair for Asia–Pacific EMC Symposium, the General Chair for 2008, 2010,
Ning Jin received the B.S. and M.S. degrees 2012, and 2016 APEMC, and the 2010 IEEE Symposium on Electrical Design
in information and electronic engineering from for Advanced Packaging Systems. He has been invited to give numerous
Zhejiang University, Hangzhou, Zhejiang, China, in invited talks and plenary speeches at various international conferences and
1988 and 1991, respectively. forums. He has served as an Associate Editor for the IEEE M ICROWAVE
She is currently a Professor and the Dean of AND W IRELESS C OMPONENTS L ETTERS from 2006 to 2008. He has served
the Information Engineering College, China Jiliang as a Guest Editor for IEEE T RANSACTIONS ON E LECTROMAGNETIC C OM -
University. Her research interests include intelligent PATIBILITY special issues in 2006 and 2010 and IEEE T RANSACTIONS ON
systems, wireless networks, and signal processing. M ICROWAVE T HEORY AND T ECHNIQUES APMC Special Issue in 2010. He is
an Associate Editor for the IEEE T RANSACTIONS ON E LECTROMAGNETIC
C OMPATIBILITY and IEEE T RANSACTIONS ON C OMPONENTS , PACKAGING
AND M ANUFACTURING T ECHNOLOGY .

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