DVL 909

SERVICE GUIDE
ORDER NO.
RRV1896
DVD PLAYER
DV-505
DV-S9
DVD LD PLAYER
DVL-909
CONTENTS
1. CIRCUIT DESCRIPTION ...................................... 2
2. CIRCUIT DESCRIPTIONS
FOR DV-S9 AND DV-09 ............................... 10
3. TEST MODE ....................................................... 13
4. IC INFORMATION .............................................. 22
5. FL INFORMATION .............................................. 47
PIONEER ELECTRONIC CORPORATION 4-1, Meguro 1-Chome, Meguro-ku, Tokyo 153-8654, Japan
PIONEER ELECTRONICS SERVICE, INC. P.O. Box 1760, Long Beach, CA 90801-1760, U.S.A.
PIONEER ELECTRONIC (EUROPE) N.V. Haven 1087, Keetberglaan 1, 9120 Melsele, Belgium
PIONEER ELECTRONICS ASIACENTRE PTE. LTD. 501 Orchard Road, #10-00 Lane Crawford Place, Singapore 0923
c PIONEER ELECTRONIC CORPORATION 1998
T - IZM APR. 1998 Printed in Japan
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2
IC802
DV-505
MB811171622A-100FN
IC601 16M bit SDRAM
PD3381A CODE Buffer
(Video, Audio, Sub-picture,GUI)
IC702 System CPU
HM514800CJ-7 (32 bit RISC)
4M bit DRAM
IC701 VBR Buffer
PD4833A IC603 IC604
VYW1536 TC551001BFL-85 Memory Controller
LSI-11 FLASH
IC301 RAM
DRAM I/F ROM
TLC5540INS CPU
HA Sync (bus arbitor)
A/D I/F
Spindle TA Demod
DV-505, DVL-909, DV-S9
FA OEIC
Motor
CPU
Slider I/F

MPEG2 Sub- GUI
ECC & Video picture
ID Reg. Program Stream SYSTEM
Decoder Decoder Decoder
Spindle DMA (DMUX)
control
SREO SREO
TE
1.1 OVERALL BLOCK DIAGRAM
XSACK XSACK MIX

1. CIRCUIT DESCRIPTION
GEN CD-ROM Sync gen.

CD PCM Video Out
Sub-CPU Sub-code Buffer DAC Y
I/F CD D. OUT
NTSC Copy
/PAL Guard DAC C
encode
DAC Comp.
AV Sync
IC201 controller AC3/MPEG1 Lt
LC78650NE Audio Decoder D/A
CD DSP Rt
CD PCM S/PDIF PCM D-Out
EFM DVD/V-CD
Decoder CD Digital Out AV Decoder AC3 D-Out
IC801 (MPEG2 Decoder)
MB86371
Servo
DSP IC501
PD4889A
Mechanism
Control
CPU IC101
PD4890A
Loading
Motor Display
CPU
Mechanism Key-SW
sense SW & Display
IC601 16M bit SDRAM
Key-SW Display System CPU PD3381A
& Display CPU (32 bit RISC) CODE Buffer
IC702 (Video, Audio, Sub-picture,GUI)
IC101 HM514800CJ-7 IC802
PD4890A MB811171622A-100FN
4M bit DRAM
IC701 VBR Buffer IC602
PD4833A IC603 PDK026A IC604
VYW1536 TC551001BFL-85
LSI-11 GUI Memory Controller
IC301 ROM RAM
ROM
TLC5540INS DRAM I/F
(bus arbitor) CPU
HA Sync I/F
TA A/D Demod
Spindle OEIC
Motor FA
CPU
DV-S9 and DV-09
Slider I/F MPEG2 Sub- GUI

ECC & Video picture
ID Reg. Program Stream SYSTEM
Decoder Decoder Decoder
Spindle DMA (DMUX)

control
SREO SREO
TE 8
GEN XSACK XSACK MIX
CD-ROM Sync gen.
Sub-CPU Sub-code Buffer (OPTICAL)
I/F AV Sync
controller AC3/MPEG1
Audio Decoder (COAXIAL)
S/PDIF
DVD/V-CD Digital
IC201 Out
LC78650NE IC801 AV Decoder
CD DSP MB86371 (MPEG2 Decoder)
CD PCM
EFM
Decoder CD Digital Out
Mechanism IC501
Servo Control PD4889A
DSP CPU
VIDEO OUT Composite

IC952 DRIVER
Loading IC901 M65677FP

Motor PD0259A 10 S-Video
VIDEO DAC FILTER AMP. DRIVER
8 8
DNR ENCODER,
10
COPY GUARD DAC FILTER AMP. DRIVER DRIVER
Mechanism 8
10
sense SW VIDEO DAC FILTER AMP. DRIVER Cb
DRAM ENCODER,
10
COPY GUARD DAC FILTER AMP. DRIVER Cr
IC951
DV-S9 Only M65677FP DRIVER Y
Component
DIRB Video Out
IC861 AUDIO
Digital In CD0015AF 96/24 DAC L ch (Analog)
(OPTICAL) DATA
DIGITAL HIBIT LEGATO S L ch (Analog)
SELECTOR
INTERFACE 96/24 DAC R ch (Analog)
(COAXIAL) RECEIVER IC811 R ch (Analog)
AUDIO
TRANSFORMER Audio Out
AUDIO
AC IN
POWER SUPPLY
3
DV-505, DVL-909, DV-S9
DV-505, DVL-909, DV-S9
DVL-909
IC601
4Mbit DRAM IC702 PD3381A
VBR Buffer HM514800CJ-7 System CPU
IC701 (32bit RISC)
PD4833A
IC603 IC602 IC604
LSI-11
DRAM I/F FLASH GUI
(Bus Arbiter) RAM
ROM ROM
Sync
HA Demod CPU
A/D
TA TA OEIC I/F
SPDL FA FA ECC & ID Reg.
Motor Program Stream
Slider Slider TE DMA
Spindle CD-ROM
GEN
Control Sync gene
For CLD For DVD Sub-code Buffer
Sub-CPU 27M
I/F CD PCM
CD Digital out
16M
16M
CD PCM
CD DSP CD Digital Out
27M
IC 201
LC78650E-P IC 501 IC 813
PD4889A CY2081SL 36M
EFM Decoder -611
Mechanism
Servo DSP Control
CPU
SI, SO, SCK,

SLD POS
XRESET 4
SHAKE
16M
18M
Mecha. DVD TILT ERR
SW
SLD DRV IC101

LOAD/TILT
MOTOR SLD ERR PD0260A2 IC205
LOAD/TILT DRV TC7S02F
M
TURN DRV LD Mechanism Control
X312
M 384 × 48k
LD TILT ERR TILT ERR (18M)
Sel
TURN
MOTOR
TRKG VCXO ERR
IC901
FOCS
LA9430M
IC801 Servo
Control IC IC908
LA9425 LC78625E
(ASP) LD DATA
PSP
DSP
EFM Decode 56
Sel
IC352 Analog L
25 15
4 CA0002AM 14
Analog R
Analog Audio
Phillips Code
ACOM
IC500 IC101
27 10 37 A/D PD6159B PD3212A
IC400 Dual DVP Memory
LA7134M SPDL Cont.
Cont 14-21 65-72 (with DNR) 44-51
VDEM
14M VCXO IC102, IC103

MB81C1501PF
Field Memory
VCXO ERR
4
DV-505, DVL-909, DV-S9
DVD Y Sync Tip

16Mbit SDRAM (IC815 1 )
(from MECHA. CONT. 41 )
Clamp
IC802 CODE Buffer D-EXT ON/OFF H IC620
MB811171622A (Video, Audio, Sub-picture,GUI)
LD Y Y OUT
-100FN LD Y SIGNAL D-Extention Pedestal Sync Tip to
(from MYCB) AMP Circuit Clamp Clamp L
C OUT
MYCB
TRAP
IC 801
MB86371 Memory Controller
BLANKING PLUSE BURST FLAG
(from AV-1 48 ) (from AV-1 47 )
CPU
I/F L
LD C SIGNAL
(from MYCB)
DVD C
System MPEG 2 Sub (IC815 7 ) H
IC620
Decoder Video Picture GUI
(DMUX) Decoder Decoder KEY
MIX
Front Section
FL TUBE
FL A.B.
Copy Gurd
DAC Cont.
NTSC
/PAL DAC
REMOTE
Encode SENSOR
DAC Key
27M AV Sync
Controller
AC3/MPEG1
36M Audio Decoder
DVD/V-CD S/PDIF
AV Decoder
AC-3/PCM Digital
PCM Digital
DVD C.
DVD Y.
SEL IR
DATA
Hi-Bit
Key
PD
IR
X311 2
384 × 44.1k
(16M) 3 SR IN
VCXO Sel IC203
TC74HC157AF
4 CLK SR OUT
8
9 L
Hi-Bit 25 Sel L OUT
14 10
IC202
PD0236AM D/A 5 R
Sel R OUT
6
IC201 JCKB ASSY

16M PD2029AM (L) AC-3
(COAXIAL) /PCM
Digital
OUT
(TOSLINK)
PCM
Digital OUT
AC-3 RF
AC-3 RF OUT
C (DVD)
Y (DVD)
3
4
IC301 33
Y (LD) Y OUT
D/A
CXD2046Q 5
1 IC620
Y/C SEP.
1-8 36
C (LD) C OUT
D/A 15
2
IC620
TC74HC4053AF Comp. OUT
MYCB ASSY
CLDM ASSY
5
DV-505, DVL-909, DV-S9
1.2 EXPLANATION OF EACH MOVEMENT

1.2.1 Sequence Up to Playback
DVD SETUP
MIRR Modulation
Measurement
RF AGC ON
T Servo ON
SLDR Servo ON
LD ON
Sweep UP → Down
F Gain Adj.
T Gain Adj.
Focus Lock
AFB Adj.
(Auto Focus Bias)
Yes
SPDL ACCEL
Layer Det.
ATB ON
Lead-in Search
PLAY
1.2.2 Focus Servo

FE generated in the RF IC is sent to the • FOCUS SERVO
Digital servo IC. OEIC GAIN
PICKUP
For a DVD, the servo is turned on during
54
the transition from “Up” to “Down” of RF PH
3 58 32
the first-order sine wave. For a CD, it B1 5 IC101 IC201 IC501
turns on during the transition from B2 FE
OEIC 6 RFIC 31 35 DIGITAL ADDRESS MECH.
“Down” to “Up” of the first-order sine B3 SERVO IC & CONTROL
7 BUS
wave. B4 LASER
8 13 54
When the servo is turned on, the level of
PH (the envelope of the bright side of RF) 11 12 22 27
increases, and DRF becomes H. The LD SGC
44
kick-brake pulses, such as those for MD
49 26
FOCUS jump, are also output from pin
1 DRF
49 of IC201. FOCUS IC151 FDO
COIL 4
2 DRIVER
• FOCUS LOCK TIMING

CD DVD
LDON
UP
UP
FDO
FE
DRF
(FOK)
6
DV-505, DVL-909, DV-S9
1.2.3 Tracking / Slider Servo

ATB: The tracking balance compensation is • TRACKING / SLIDER SERVO
achieved by outputting the offset from
the TBAL output at pin 46 of the digital PICKUP
servo IC, and by biasing the charge pump TE RF TE
4 26 34
resistor for phase-difference error of B1
RFIC. 5 IC101 IC501
B2 IC201
OEIC 6 RFIC DIGITAL ADDRESS MECH.
The difference is detected by processing &
B3 TBAL SERVO IC CONTROL
TE at pin 34 of IC 201 with an internal 7 BUS
28 46
B4 8
digital equalizer. CP
TDO: In addition to the servo output, the low-

band components, such as the kick-brake
50 47
for jump, are added for TDO output. TDO
26 24
TRKG
COIL 27 IC151
SLDO: The low-band components of TE are
DRIVER SLDO
processed by the internal digital 16 19
equalizer, and deadband is added for 17
SLDO output. The offset voltage for
pickup movement is also included in the M
SLDO output. SLDR
1.2.4 SPINDLE SERVO

• SPDL SERVO
ATC
179
RF IC101 RFO
OEIC 3 50 3 200
RFIC IC301
CLK | 8 bit |
A/D
32 (27M) 10 207
12 IC701
RF LSI II
176
APC
178
AFC
180
IC302 ASC
(1/2) 177
159
41 VCO 161 163 166 167 95
IC201 FPWM
DIGITAL VPWM
FG SERVO
57 31 PPWM
IC271 RPWM
48 (2/2)
SPDO DUTY50
SPDL +
12 V165
SPDL IC161 IC271
SPDO
M DRV 25 (Compatible) (1/2)
13
SPDL -
(Base) FG
For a CD, the RF signal output from pin 32 of the RF IC is converted

to binary in IC201. By comparing the binary value with the reference
CLK (clock), the SPDL ERR signal is output from pin 48.
For a DVD, the SPDL ERR signal is generated from the PWM signal
output from LSI-ΙΙ. Upon receiving this signal via pin 31, IC201
also outputs it from pin 48, switching from the CD SPDL ERR
signal.
7
DV-505, DVL-909, DV-S9
1.2.5 Disc Determination

Determination is achieved by checking the sine wave by sweeping
the lens with the OE IC gain at L and the FSC error amplifier (SGC) Offset compensation
at the default setting. If no sine wave is detected, checking is retried
after switching the OE IC gain to H and increasing the gain of the
FSC error amplifier (SGC). If no sine wave is detected again, it is Lens sweep
regarded as the NO DISC condition.
If one half of the sine wave detected at the first lens sweep is of a
value less than 0.5 V, the OE IC gain is set to H and the peak-to-
peak value of the sine wave is roughly adjusted to 1.8 Vp-p. Checking Yes
By sweeping the lens around the height where the sine wave has the sine wave
been detected, disc determination is performed, and the sine wave
None Less than 0.5V
is finely adjusted to 1.8 Vp-p. Level check
OEIC gain = H
FCS AMP gain up More than 0.5V
Lens sweep
OEIC gain = H
Checking Yes
the sine wave
None Roughly adjust to

1.8Vp-p sine wave
NO DISC
Disc determination
Finely adjust to 1.8Vp-p

sine wave
END
8
DV-505, DVL-909, DV-S9
1.2.6 System Control (DVL-909)
FLPB, KEYB DVD MAIN
102,107,108,111
IC601
SI1,SO1 PD3381A
16
IC101 SCK1,XRDY
PD4890A IC604 IC603 IC602
13
System
Work FLASH GUI
Mode Control Cont.
22 RAM ROM 4M ROM
(FL Cont.)
21
DATA,ADDRESS
MAIN BUS IC801
MB86371
POWER ON
AV-Dec.
Remote XRESET MAD0–MAD7
KEY
Sensor
IC701 IC501 IC201
142 151
26
72
PD4833A PD4889A LC78650E-P
LSI-11 Mech. Cont. Digital
19
65
(DVD) Servo
39
77 8 10
POWER SUPPLY
ASSY
SO1,SI1
DVDP PK
SCK1
19 21
Slider SLDPOS LD/DVD
Position 9 IC101 XLPO Carriage
SW 56 Out position SW
PD0260A2
33
Loading Mech. Cont. XTurn A

SW1–3 55 Turn
Position (CLD) XTurn B A/B SW
35
SW 54
24 25
IC803 IC171
Tilt /
Loading M Tilt / Loading Turn
M
Motor Drive Drive
CLD MAIN
1) Interface between Mode Cont. and System Cont. XRDY
XRDY LT1
13 102
IC101 IC601 SCK
LT1
PD4890A 46 65 PD3381A
SCK1 SI
Mode Control 14 111 System
(FL Cont.) SO1 Cont.
15 107
DATA
SI1
16 108 SO
Timing Chart
If there is no communication for 2 sec.,
Mode Cont. turn off the power and reset.
9
DV-505, DVL-909, DV-S9
2. CIRCUIT DESCRIPTIONS FOR DV-S9 AND DV-09

2.1 VIDEO SIGNAL PROCESSING BLOCK
2.1.1 PD0259A Block (3) Y/C-timing Adjustment
The major purposes of the PD0259A block are; This function changes the output phase of the Y signal with respect
(1) Frame-correlative cyclic digital noise reduction to the Cb and Cr signals in units of the 13.5-MHz clock cycle (approx.
(2) Horizontal and vertical contour compensation 74 ns).
(3) Y/C timing adjustment
(4) Frame freezing (4) Frame Freezing
In response to a command sent from the system control computer
(1) Frame-Correlative Cyclic Digital Noise Reduction by serial transmission, data for one frame are frozen, and the frozen
For eight-bit digital video data input to the PD0259A, noise reduction picture is output.
is performed through subtraction between the data and those of the This function is specific to the DV-S9 and is used only for picture-
corresponding points 1 frame before, delayed for the subtraction by-picture reversing by jog/shuttle operation or “Slow 1” playback
via a 4-bit DRAM by 1 frame. operation.
The noise signal detected as a result is sent to a non-linear circuit. If
the difference is larger than a specific value, it is regarded as “a
change in picture,” and no canceling calculation is made.
This function is the same as that which has been performed in 2.1.2 M65677FP Block
conventional laser-disc players. The only difference is that the input
The M65677FP block functions as an NTSC encoder that converts
video signal here is a DVD digital component signal (4:2:2), while
digital component signals to analog Y, C, Cb and Cr signals. While
it is an LD digital composite signal in conventional laser-disc players.
our popular models other than the DV-S9 use the built-in encoder in
DATA the MB86371 block, an external NTSC encoder is added to the DV-
S9, as it performs digital processing in the PD0259A block.
ON/OFF In addition to NTSC encoding, the M65677FP also performs:

SW (1) D.EXT(DV-S9)/BLACK LVL(DV-09)
(2) C.LEVEL adjustment
Non-linear
circuit
(1) D.EXT(DV-S9)/BLACK LVL(DV-09)
Setup of –7.5 IRE is added to the Y signal. D.EXT(DV-S9)/BLACK
1-frame delay
LVL(DV-09) processing using analog signals in conventional laser
disc players is achieved by using digital signals.
(2) Horizontal and Vertical Contour Compensations (2) C.LEVEL Adjustments

For data after digital noise reduction, horizontal and vertical contour The burst level of the C signal can be varied centering around 40
compensations are made only for the Y-signal. IRE.
Horizontal compensation is performed by detecting edge components Therefore, it is performed for the S-connector and CVBS-connector
from the information of the reference picture elements and those outputs, but not for the color-difference output.
that horizontally proceed and succeed by several pixels, and then This function is also not available if the connected TV receiver has
generating edge-emphasizing components through non-linear no AGC circuit.
processing of the detected components.
Vertical compensation is performed by detecting edge components
from information on the reference picture elements and those which
vertically proceed and succeed by one line, and then generating edge-
emphasizing components through non-linear processing of the
detected components.
These edge-emphasizing components are added to the main-line
digital data to achieve contour compensations.
Vertical edge generation

1H 1H Non-linear
HPF
Delay Delay circuit
Non-linear
BPF
circuit
Horizontal edge generation
Delay
10
DV-505, DVL-909, DV-S9
2.1.3 Analog Video Signal Processing Block

The video signals output from the built-in 10-bit DA converter of
the M65677FP pass through a low-pass filter and amplifier, and are
output from the DVD MAIN Assy and sent to the VOUT Assy.
In the VOUT Assy, analog noise-reduction processing having three
levels (OFF, low, and high) is initially applied only to the Y signal.
This analog noise reduction is the same as that performed by
conventional laser-disc players. The register port output in serial
communication that the PD0259A receives from the system-control
computer is used as the control signal for analog noise reduction.
After analog noise reduction, a CVBS signal is generated by
composing the Y and C signals (no clamping is performed for the C
signal). The timing pulse BF to be used for pedestal clamping is
supplied from the PD0259A. This signal is adjusted within the
PD0259A so that it provides the timing for the burst portions of the
output video signals.
4M DRAM µ-COM µ-COM

×2
Amp.
V DATA V DATA Cb
LPF CLAMP Cb
IC801 H IC901 H IC951
MB86371 V PD0259A V M65677FP
(AV1) (DNR) NTSC Amp. CLAMP Cr
FLD
ENCODER Cr
CLK CLK LPF
CLAMP Y
ANR1
ANR2
Amp.
BF
IC952 Y Analog
LPF CLAMP Y
M65677FP NR
NTSC Amp.
ENCODER C
LPF C
CLAMP CVBS
DVD MAIN ASSY V OUT ASSY
11
DV-505, DVL-909, DV-S9
2.2 DIRB BLOCK (DIRB ASSY) 2.3 96K, 24-Bit, HIBIT LEGATO S
(DV-S9 ONLY) SYSTEM (AUDIO ASSY)
The two major purposes of the DIRB block are the following: All 16-bit and 20-bit sources are converted to 24-bit data by IC101,
(1) Switching between data reproduced from a disc and a data signal which lets a 24-bit data pass through.
in DAC mode As PCM1702P is a 20-bit D/A converter, processing of the upper
(2) Data decoding in external input mode (DAC mode) 20 bits is assigned to it by the shift register.
The lower 4 bits are converted from serial to parallel, then the
(1) Switching Between Data Reproduced from a significance of each bit is converted digital to analog, functioning
Disc and a Data Signal in DAC Mode as a 4-bit D/A converter for the lower 4 bits.
By adding the lower 4 bits to the upper 20 bits in the low-pass &
The signal switching is performed at IC811, sending 3-line data
ADD block, D/A conversion is achieved for 24 bits.
(LRCK, BCK and DATA) to the AUDIO Assy. The switching
control line (DAC MODE) is supplied from the DVD MAIN Assy. Hi Bit
The master clock (MCK) is generated by a crystal on the AUDIO IC101
Assy when reproducing a disc, and by IC861 in DAC mode. MCK
is sent to the AUDIO Assy via RXP.
Legato S
(2) Data Decoding in External Input Mode (DAC IC111
Mode)
Serial to Parallel
When the user selects DAC mode, the DAC MODE port is set to H Shift Register and Significance
and VCO in IC861 starts oscillating. (VCO does not oscillate in TC74HC164AF Conversion
any other modes than DAC mode.) When there is a toss link of an TC74HC163AF
external input or a coaxial digital input, the digital input signal is
sent to IC861 from RXP of CN801, generating 3-line data D/A Converter
corresponding to the input sampling frequency. At the same time, PCM1702P
the master clock (MCK) to be used in DAC mode is also generated.
For a 96kHz input, the MCK frequency is divided by 2 by IC831.
Low-pass
& ADD
When the user selects the internal clock as the system clock, the
clock generated by the crystal on the AUDIO Assy is sent to the
DVD MAIN Assy. When the user selects an external sync as the
system clock, the following parameters are used. Analog Output
16M clock in 18M clock in 16M clock sent to 18M clock sent to
FS(kHz)
the AUDIO Assy the AUDIO Assy the DVD MAIN Assy the DVD MAIN Assy
32 Oscillates Oscillates Crystal 16M clock Crystal 18M clock
44.1 Stops oscillating Oscillates DIR 16M clock Crystal 18M clock
48 Oscillates Stops oscillating Crystal 16M clock DIR 18M clock
96 Oscillates Stops oscillating Crystal 16M clock DIR 18M clock
If there is no external input or locking onto the input digital signal

cannot be achieved, the ERR signal at pin 43 of IC861 is set to H,
and the crystal in the AUDIO Assy immediately starts oscillating.
In such cases, the clock sent to the DVD MAIN Assy will always be
a crystal clock.
IC901 16M Selector
IC902 18M Selector
IC811 Data Selector
IC831
Clock Selector
IC861
IC835
DIR
1/2 Divider
CN801 CN811
12
DV-505, DVL-909, DV-S9
3. TEST MODE
3.1 HOW TO ENTER THE TEST MODE (5) Pause
There is the three following methods in an enters of the test mode. 1. It becomes pause condition by pressing [CX] (0E) key of the
1. Short-circuit the terminals (TP6006 and TP6007) for test mode remote control unit in the play.
entry at the side of the system control IC (IC601) of DVDM ASSY, 2. Pause ON/OFF changes alternately by pressing [PAUSE] (18)
and turn the power on. key in the play.
2. Input [ESC] key and [TEST/RANDOM] key of the test mode
remote control unit in order under the power on condition. (6) Search Address Input Entry
3. Connect a personal computer with the RS232C terminal (CN106), It becomes the address input mode when [+10] key (1F) is pressed.
and input entry command (TE) of test mode from the personal (indication for the most significant digit : > )
computer. Indicate the last address as the initial condition in this time.
Note: FL indication and LED come all to light until key operation Only in case of DVD, addition search (indication for the most
is done when entering the test mode. significant digit : + ) and subtraction search (indication for the most
significant digit : – ) are able to select in order by pressing [+10]
3.2 RELEASE THE TEST MODE key continuously.
The address where input value was added to the present address is
There is the three following methods in a release of the test mode.
make to search with addition search.
1. Turn the power off.
The address where input value was subtracted to the present address
2. Press [ESC] key of the remote control unit. At this time, reset it
is make to search with subtraction search.
for a while except for during the LD and CDV set.
In case of CD is only absolute time search.
3. Connect a personal computer with the RS232C terminal (CN106),
Also address clear and release from the address input mode are able
and input normal mode entry command (NE) from the personal
to perform by 2 steps by pressing [CLEAR] (45) key.
computer.
3.3 THE EXPLANATION OF EACH (7) Search Address Input

Press [0] to [9] keys of the remote control unit.
FUNCTION Set up the address by the hexadecimal number with DVD.
The function that can be operated in the test mode is as the following. When [PROGRAM] (4C) key is pressed in the address input mode,
Use a LD remote control unit in the test mode. input mode changes to hexadecimal number input (Indicates "∗"
mark), and [1] to [6] keys are input as [A] to [F].
At this time, [7], [8], [9] and [0] keys are not accepted.
(1) Door Open/Close
Also the hexadecimal number input and the decimal number input
1. Press [REPEAT A-B] (48) key of the remote control unit. can be changed with toggle.
2. Press [OPEN/CLOSE] key of the player from the stop condition.
(8) Search Practice
(2) Stop
1. Press [CHP/TIM] (13) key of the remote control unit.
1. Press [REPEAT] (44) key of the remote control unit. Practice the on screen no playback (Doesn't demultiplex) after
2. Press [STOP] key of the remote control unit or the player from the search with DVD.
the stop condition. 2. Press [PLAY] (17) key of the remote control unit.
Practice the on screen playback (demultiplex exists) after the
(3) Play 1 (Demultiplex exist which it tries to output search with DVD.
the playback screen)
1. Press [PLAY] (17) key of the remote control unit. (9) Side Change
• CLD rise up at the tracking open condition. However, it becomes This function becomes effective when a set disk is LD.
tracking close when entering the test mode during the play. 1. Change a side on the side A from the side B when pressing [SIDE
• DVD rise up at the tracking close. Playback screen may not A] (4D) key of the remote control unit.
appear because the NAVI information isn't read in the test mode. 2. Change a side on the side B from the side A when pressing [SIDE
B] (4E) key of the remote control unit
(4) Play 2 (Demultiplex is absent which performing
trace only) (10) Tracking Open
1. Press [TV/LDP] (0F) key of the remote control unit. 1. Press [STEP FWD] (54) key of the remote control unit in the play
• It is equal to the play 1 with CLD. condition.
• Perform only tracing with DVD, and there are no video and 2. Switch the open/close by pressing [PLAY] key of the remote
audio output. control unit or the player during the play (CD only).
13
DV-505, DVL-909, DV-S9
(11) Tracking Close (20) Tilt Up

1. Press [STEP RVS] (50) key of the remote control unit in the play A manual moves in the going up direction when [SKIP FWD] (52)
condition. key of the remote control unit is pressed during the play at the time
2. Switch the open/close by pressing [PLAY] key of the remote of tilt off.
control unit or the player during the play (CD only).
(21) Focus Jump +
(12) Slider In Focus jumps in 1 layer from 0 layer when [MULTI FWD] (58) key
1. Press [SCAN RVS] (11) key of the remote control unit in the of the remote control unit is pressed. (DVD only)
tracking off condition.
2. Turn the shuttle of the remote control unit in the REV direction (22) Focus Jump –
(2C to 2F) in the tracking off condition. (DVD only) Focus jumps in 0 layer from 1 layer when [MULTI REV] (55) key
of the remote control unit is pressed. (DVD only)
(13) Slider Out
1. Press [SCAN FWD] (10) key of the remote control unit in the (23) The First And The Second Screen Switching
tracking off condition. Every time [DISPLAY] (43) key of the remote control unit is pressed,
2. Turn the shuttle of the remote control unit in the FWD direction the contents of the version indication part (the bottom right of the
(28 to 2A) in the tracking off condition. (DVD only) screen) change. (Refer to page 17.)
(14) Scan In (24) Screen Display On

1. Press [SCAN RVS] (11) key of the remote control unit in the 1. Press [DISPLAY] (43) key of the remote control unit.
tracking on condition. 2. Display on/off switches every time [PROGRAM] (4C) key of the
2. Turn the shuttle of the remote control unit in the REV direction remote control unit is pressed.
(2C to 2F) in the tracking on condition. • When [DISPLAY] key is pressed in the display on, change the
• DVD can be scanned only in the case of the play 2 (playback part number indication of the microprocessor and revision
without demultiplex). indication.
• Initial state is screen display on and it becomes the part number
(15) Scan Out indication of the microprocessor.
1. Press [SCAN FWD] (10) key of the remote control unit in the
tracking on condition. (25) Screen Display Off
2. Turn the shuttle of the remote control unit in the FWD direction 1. Press [AUDIO] (1E) key of the remote control unit.
(28 to 2A) in the tracking on condition. 2. Display on/off switches every time [PROGRAM] (4C) key of the
• DVD can be scanned only in the case of the play 2 (playback remote control unit is pressed.
without demultiplex).
(26) Background Color Switching
(16) Loading In/Out
1. Change the background color (eight colors) prepared for in
When pressing [SKIP REV] (53) key of the remote control unit in advance every time [2/R] (49) key of the remote control unit is
the open condition, it loads in the clamp direction. Then it loads in pressed in order.
the open direction when pressing [SKIP FWD] (52) key. [Blue→Green→Light blue→Red→Purple→Yellow→
• This function can practice only when it is indicated with "OPEN" Gray→Black→Blue ....]
in FL. 2. Change the background color (eight colors) prepared for in
advance every time [1/L] (4B) key of the remote control unit is
(17) Tilt Neutral pressed in order.
Press [SPEED DOWN] (46) key of the remote control unit. [Blue→Black→Gray→Yellow→Purple→Red→
Light blue→Green→Blue ....]
(18) Tilt Servo On/Off
a. On (27) Video Output Switching
Press [SPEED UP] (47) key of the remote control unit. 1. It becomes component output when pressing [DIGITAL EFFECT]
b. Off (5C) key of the remote control unit.
Press [SKIP REV] (53) key and [SKIP FWD] (52) key of the 2. It becomes composite output when pressing [STILL WITH
remote control unit at the tilt servo on or the tilt neutral. SOUND] (5B) key of the remote control unit.
(19) Tilt Down

A manual moves in the going down direction when [SKIP REV]
(53) key of the remote control unit is pressed during the play at the
time of tilt off.
14
DV-505, DVL-909, DV-S9
3.4 EXPANSION FUNCTION 1 3.5 EXPANSION FUNCTION 2

Set the reception mode of expansion function by pressing [TEST] Set the reception mode of expansion function 2 by pressing [HILITE/
(5E) key of the test mode remote control unit, then expansion function INTRO] (55) key of the remote control unit, then expansion function
is able to execute by pressing the key of [0] to [9]. 2 is able to execute by pressing the key of [0] to [9].
Indication for the most significant digit becomes "T" during the
reception mode of expansion function. (This mode can on and off (1) Forced DVD Setting
with toggle.) In the checker mode, set up the condition that DVD is attached
forcibly except for the result of disc distinction by pressing [HILITE/
(1) LD On INTRO] and [1] keys in order.
Turn the laser diode to on by pressing [TEST] and [1] keys in order. In the no checker mode (normal test mode), once execute the setting
but abandan it soon.
(2) Focus On Therefore, perform the disc distinction again for the safety when
Focus locks by pressing [TEST] and [2] keys in order. rising up the player in this condition.
(3) Focus Sweep (2) Forced CD Setting

Repeat focus sweep by pressing [TEST] and [3] keys in order. In the checker mode, set up the condition that CD is attached forcibly
except for the result of disc distinction by pressing [HILITE/INTRO]
and [3] keys in order.
(4) Spindle FG Servo In the no checker mode (normal test mode), once execute the setting
Rising up the spindle and FG servo becomes on by pressing [TEST] but abandan it soon.
and [5] keys in order. Therefore, perform the disc distinction again for the safety when
rising up the player in this condition.
(5) AGC On/Off
Switch the AGC on and off with toggle by pressing [TEST] and [7] (3) Execute The Disk Distinction
keys in order. In the checker mode, execute the disc distinction result by pressing
[HILITE/INTRO] and [0] keys in order.
(6) Jitter Value Indication.
It becomes the jitter-value indication mode by pressing [TEST] and
[DIG/ANA] keys in order.
(7) DSP coefficient indication of FTS system.

Set up the address (four digits) of the coefficient that it wants to see
by the point of search address input, then real time indicates the
coefficient in OSD by pressing [TEST] and [9] keys in order.
(8) CD Error Rate Indication

Indicate the value in OSD after measuring is completed by pressing
[TEST] and [0] keys in order after set up the measuring time (1 to 8
seconds) by the point of search address input.
3.6 List of Test Mode Function

Key Name of Mode of
Contents of Command Condition
Remote Control Unit Remote Control Unit
Open STOP REPEAT A A8-48
Close OPEN REPEAT A A8-48
Stop PLAY REPEAT B A8-44
Play (DVD is only tracing.) STOP TV/LDP A8-0F
Play (DVD is with decode.) STOP PLAY A8-17
Pause on PLAY CX A8-0E
Pause on/off PLAY/PAUSE PAUSE A8-18
Search address input (0 to 9) 0 to 9 A8-00 to 09
∗Use for other numerical value input
15
DV-505, DVL-909, DV-S9
Key Name of Mode of

Contents of Command Condition
Remote Control Unit Remote Control Unit
Search address input (A to F) During address input PGM+1 to 6
Search address clear During address input CLEAR A8-45
Escape the search input mode Address = 0
Change the search address input mode +10 A8-1F
(Off→absolute address→addition→subtraction→Off)
∗Use for other numerical value input.
Search execution (ignore the wrong address) CHAP/TIME A8-13
Side change (side B→side A) LD SIDE A A8-4D
Side change (side A→side B) LD SIDE B A8-4E
Tracking open PLAY STEP FWD A8-54
Tracking close PLAY STEP REV A8-50
Slider in TR : Off SCAN REV A8-11
Shuttle REV A8-2C to 2F
Low speed scan REV TR : On SCAN REV A8-11
Scan REV (Jump number is variable) TR : On Shuttle REV A8-2C to 2F
Slider out TR : Off SCAN FWD A8-10
Shuttle FWD A8-28 to 2B
Low speed scan FWD TR : On SCAN FWD A8-10
Scan FWD (Jump number is variable) TR : On Shuttle FWD A8-28 to 2B
Loading in STOP SKIP REV A8-53
Loading out STOP SKIP FWD A8-52
Tilt neutral SPEED DOWN A8-46
Tilt servo on SPEED UP A8-47
Tilt servo off Tilt : On/N SKIP REV A8-53
SKIP FWD A8-52
Tilt up PLAY SKIP FWD A8-52
Tilt down PLAY SKIP REV A8-53
LD on TEST + 1 A8-5E + A8-01
Focus on TEST + 2 A8-5E + A8-02
Focus sweep TEST + 3 A8-5E + A8-03
Focus jump + MULTI FWD A8-58
Focus jump – MULTI REV A8-55
Spindle FG on TEST + 5 A8-5E + A8-05
AGC on/off AGC : Off/On TEST + 7 A8-5E + A8-07
Indication of the FTS coefficient After the address four-digit input TEST + 9 A8-5E + A8-09
CD error rate indication PLAY TEST + 0 A8-5E + A8-00
Jitter indication TEST + DIG/ANA A8-5E + A8-0C
Screen indication on/Switching of the first screen and second screen OSD Off/On DISPLAY A8-43
Screen indication off OSD : On AUDIO A8-1E
Screen indication on/off PROGRAM A8-4C
Switching of ID display methods (decimal/hexadecimal) DIG/ANA A8-0C
DISC type designation STOP HILITE/INTRO A8-5A
• Forced designation to DVD +1 +A8-01
• Forced designation to CD +3 +A8-03
• Request for Disk sensing +0 +A8-00
Tray close of disk sense inhibition Checker mode REPEAT A A8-48
Background color (eight colors) switching 2/R A8-49
Background color (eight colors) switching (reverse toggle) 1/L A8-4B
Video : component output DIGITAL EFFECT A8-5C
Video : composite output STILL WITH SOUND A8-5B
16
DV-505, DVL-909, DV-S9
Special Mention Item

(1) Indications for the spindle status are as follows: (4) If you turn the power on while short-circuiting the short-circuit
A/B : Spindle accelerator and brake terminal at the side of the system controller, the player will
FG : FG servo forcibly enter the test mode. If the FL controller is set to Checker
SRV : Rough, velocity/phase servo mode, disc sensing will not be started, even if a disc is loaded.
O_S : Offset addition, rough, velocity/phase servo Disc sensing will also not be performed if the tray is opend/
closed by your pressing [REPEAT A] key while in Checker
(2) The movement of loading in/out starts from the tray open status. mode.
After that, this function is executed unless a play and close However, disc sensing will be started if the [OPEN/CLOSE]
operation are done. key on the player or on the remote control unit is pressed.
(3) There are three methods for entering a search address: (5) If disc-type designation is forcibly executed during a mode other
Absolute address designation than Checker mode, the system controller will abandon disc-
→ Searching for the address entered (indication for the most type designation after setting the mechanism controller.
significant digit :>) Therefore, after startup of the player, disc sensing will be
Additional input performed again for safety.
→ Searching for the address with the current ID number plus If disc-type designation is forcibly executed during Checker
an entered number mode, as disc-type designation is not abandoned, playback will
(indication for the most significant digit :+) be immediately started.
Subtractive input
→ Searching for the address with the current ID number minus (6) A background color change in order of blue → green → light
an entered number(indication for the most significant digit :–) blue → red → purple → yellow → gray → black → with the [2/
The above modes can be changed by pressing [10] key. R] key.
Note : A number for addition or subtraction must be entered in It changes in order of gray → yellow → purple → red → light
hexadecimal. blue → green → blue → black → in the case of the [1/L] key.
(7) In case of PD0260A∗, tilt servo on function may not move with
DVD.
3.7 Test Mode Screen Display (The Second Generation)

Consecutive double-OSD display is supported during test mode. The screen is composed 10 lines with a maximum of 32 characters per line.
It can't be used with the debugging display mode together.
• Screen Composition
Character in bold : Item name
: Information display Remote control code
Address Key code

Tilt error value, Tilt servo status Mechanical position value
Tracking status Slider position
Spindle status Output video system
AV1 classification and
AGC setting Flash ROM size
FL controller version
FTS servo IC information Region setting for the player
C1 error value of CD and DVD Flash ROM version

Internal operation mode of System controller revision
the mechanism control
Disc judgment DVD mechanism controller revision
Pickup AV-1 chip version
CLD mechanism controller revision

First screen display
Caution :
The first screen and second screen switch by
pressing [DISPLAY] key of the remote control FL controller version
unit. GUI-ROM number
It is only a version display part on the lower
right of the screen those contents of display Part No. of flash ROM and system controller
change. Part No. of DVD mechanism controller
ATB : ON/OFF information display and AGC Part No. of CLD mechanism controller
manual establishment display deleted with the
second generation.
Second screen display (at lower right portion of the screen)
17
DV-505, DVL-909, DV-S9
• Description of Each Item on the Display (11) FTS servo IC information

Indications for the following two types of information can be
switched:
(1) Address indication
DSP coefficient indication [KS-[∗∗∗∗] ∗∗∗∗]
The address being traced is displayed in number. Displays the address (four digits) of the specified coefficient
DVD : ID indication (hexadecimal number, 8 digits) and the setting value (four digits) with [TEST] and [9] keys.
[∗∗∗∗∗∗∗∗]
CD/LD (CLV) : A-TIME (min. sec.) [ ∗∗∗∗] Jitter value indication [JT-[ ]∗∗∗∗]
LD (CAV) : FRAME [ ∗∗∗∗∗] Displays the jitter value (four digits) with [TEST] and [DIG/
(Note : For DVDs, decimal-number indication is possible.) ANA] keys.
(2) Code indication of the remote control unit [R-∗∗∗∗] (12) Error rate indication
The code for the key pressed on the remote control unit, which is C1 error value of CD [ER-C1 ∗∗∗∗ ]
received by the FL controller, is displayed while the key is pressed. C1 error value of DVD [ER-∗∗∗∗ ∗∗∗∗]
In the case of the double code, the second code will be displayed.
(13) Internal operation mode of mechanism controller
(3) Key code indication for the main unit [K-∗∗]
[MM-∗∗:∗∗]
The code for the key pressed on the main unit, which is received by
Internal mechanism mode (2 digits) and internal mechanism step (2
the system controller, is displayed while the key is pressed.
digits) of the mechanism controller
Note : For details, see the specifications of the mechanism controller.
(4) Tilt error value, Tilt servo status [TILT-∗:∗∗∗]
Tilt error value : [0] to [F]
(14) Disk sensing [DSC-∗∗∗]
Tilt servo status :
The type of discs loaded is displayed.
Tilt neutral [N]
[DVD], [CD ], [CDV], [LD ], [VCD], [ ]
Tilt servo on [ON]
Tilt servo off [OFF]
(15) Pickup [PU-∗∗∗]
(5) Tracking status [TRKG-∗∗∗] The pickup being operating is displayed.
DVD [DVD]
Tracking on [ON]
CLD [CLD]
Tracking off [OFF]
(16) Destination setting of the FL controller

(6) Spindle status [SPDL-∗∗∗] [F:∗∗∗/∗∗∗]
Spindle accelerator and brake [A/B] Three characters in front represent the type of model:
FG servo [FG] 505: DV-505, S9: DV-S9
Rough, velocity phase servo [SRV] 606 : DV-606D, EDU: for education
Offset addition, rough, velocity phase servo [O_S] 909: DVL-909, K88: DVL-K88.
Three characters that follow represent the destination code.

(7) Mechanism position value [M-∗]
J : /J, K: /KU, /KC, /KU/KC, RAM: /RAM (China)
Position code [0] to [8] RL : /RL, WY: /WY, RD: /RD.
∗ Furthermore DVL-91/KU/CA indicates as L91/K.
(8) Slider position [S-∗∗∗∗]
CD TOC area [IN ] (17) Region setting of the player [REG:∗]
CD active area [CD ] Setting value [1] to [6]
CDV video area [CDV ]
LD active area [LD ]
Side B inside [B IN] (18) Version of the flash ROM [V:∗.∗∗]
(9) AGC setting [AGC-∗∗] (19) Revision of the system controller [S:∗.∗∗∗/∗.∗∗]
AGC on [ON] Revision number of the external ROM part (flash ROM) of the
AGC off [OFF] system controller <Front>
Revision of the internal ROM part of the system controller
<Rear>
(10) Output video system [V-∗∗∗∗]
NTSC system [NTSC]
PAL system [PAL ]
Auto-setting [AUTO]
18
DV-505, DVL-909, DV-S9
Using the Function in Test Mode (The Remote

(20) Revision of the DVD mechanism controller Control Keys to be Used are Indicated in Brackets)
[M:∗.∗∗∗/∗.∗∗∗] (1) Set the CD to trace (playback) state.
Revision number of the external ROM part (flash ROM) of the (2) Set the player to Number input mode by pressing [+10] and
DVD mechanism controller <Front> enter the measurement time in a range of 1 to 5 (sec.).
Revision of the internal ROM (core part) of the DVD mechanism (3) Start measurement by pressing [TEST] + [0]. The SubQ counter
controller <Rear> stops during measurement, but this is not a malfunction. When
the specified measurement time has elapsed, the result is
(21) Revision of the CLD mechanism controller indicated to the right of “ER C1 –” on the screen.
If you skip step 2, the measurement time is set to 5 (sec).
[L:∗.∗∗∗]
(22) Version of the AV-1 chip [AV:∗.∗]

3.8.2 Jitter Value
Overview
(23) Version of the FL controller [F:∗.∗] The jitter values of DVDs and CDs can be displayed on basic models,
such as the DV-505, and those of DVDs can be displayed on DVD/
LD-compatible models, such as the DVL-909.
(24) Control number of the GUI-ROM [GUI:∗∗∗] The displayed value shows a voltage in three-digit decimal as . V.
For example, the indication “0278” means 2.78 V. The larger the
(25) The part number of the flash ROM and system value, the worse the jitter. The worst value is 3.25 V. When playing
controller [S : ∗∗∗∗∗∗/∗∗∗∗∗∗∗] a DVD or a video CD with which the jitter value is extremely high,
mosaics may be seen. As with the error rate, the jitter depends on
Part number of the flash ROM <Front>
the disc and pickup. The jitter value to be displayed has no close
(Example) VYW1536-A → W1536A
correlation with a jitter measuring device, and is to be regarded just
(Example) PD626A9 → 6256A9
for reference.
Reference : When the jitter value is 2.9 V or more with a DVD, or
Part number of the system controller <Rear>
3.0 V or more with a CD (or a video CD), it may cause
(Example) PD3381T1 → 3381T1
a problem (mosaic, audio distortion, etc.) in playback.
(26) Part number of the DVD mechanism controller Using the Function in Test Mode (The Remote
(Example) PD4889A0 → 4889A0
Control Keys to be Used are Indicated in Brackets)
(1) Set the DVD or CD to trace (playback) state with AGC OFF.
(27) Part number of the CLD mechanism controller (2) Press [TEST] and [DIGITAL/ANALOG].
(Example) PD0260A2 → 0260A2 The current jitter value appears to the right of “JT: ” on
the display. The jitter value keeps changing unless any additional
(28) AV1 classification [AV1 : ∗∗∗] key operation is made.
RAM, E/A, S/C
Note : Although a value may be displayed on the screen even with
(29) Flash ROM size [FLSH : ∗∗] AGC ON, this is NOT a jitter value.
The jitter value with AFB ON cannot be displayed (see the
8M : 8M bit, 4M : 4M bit
next section). The jitter value with AFB ON can be obtained
only by directly measuring the voltage at the JV connector
3.8 DESCRIPTIONS OF NEW FUNC- (pin 94) of the servo DSP (LC78650).
TIONS IN TEST MODE
3.8.1 Error Rate
Overview
The error rate of CDs can be measured on basic models, such as the
DV-505, and that of CDs as well as LDs with sub-Q codes can be
measured on DVD/LD-compatible models, such as the DVL-909.
The value is displayed in decimal and indicates the number of C1
errors (including the corrected ones) counted during the specified
measurement time.
An indeterminate measurement result may be caused by a dirty disc,
decentering, surface deflection, birefringence (double reflection),
or a pickup problem (dirty lens, etc.), misadjustments of the pickup,
improper automatic adjustment, or incomplete adjustments. On the
manufacturing line, the value is used for yes/no decision of pickups.
Normally, for a measurement for 5 seconds, the value may be less
than 10 with a clean disc and less than 100 with a disc with some
damage.
19
DV-505, DVL-909, DV-S9
Using the Function in Test Mode

3.8.3 Startup Sequence This function is not assigned to any remote control keys. Only an
The basic flow is shown below. The parentheses indicate a limitation: open/close operation can trigger the function.
“base” represents base models, such as the DV-505 and DV-S9,
and “compatibles” represents DVD-LD compatible models, such as 3.8.6 SGC
the DVL-909.
Overview
(1) Closes the tray. This is a new function to maintain the sine wave related to focus
(2) Runs the tilt servo for 1.5 seconds (compatibles). errors to a certain size so that the sine wave shows 1.8 V for the P-
(3) Detects the peak. to-P value.
(4) Distinguishes the disc. This operation is performed each time after judging disc presence
(5) SGC and distinction in the normal startup process and in Test mode, as
(6) Turns on the focus servo. well. The operation is achieved by switching the FE gain inside the
(7) Turns on the tilt servo (compatibles). RF IC (LA9700) by using the voltage at the SGC connector (pin 22)
(8) Starts the spindle rotation. of the RF IC.
(9) ATB
(10) Measures the MIRR modulation degree. Using the Function in Test Mode
(11) Turns on the tracking servo. This function is not assigned to any remote control keys. Only an
(12) Turns on the slider servo. open/close operation can trigger the function.
(13) Turns on the spindle servo.
(14) Focus AGC 3.8.7 Measurement of MIRR Modulation
(15) Tracking AGC
(16) AFB Degree
(17) Plays AGC (base for CDs) Overview
(18) Plays back. The slice voltage of the RF signal is measured and used in the
calculation to generate the MIRR signal. This operation is made in
∗ For a 2-layer DVD, steps (9) through (16) are repeated for each synchronization with ATB ON/OFF in normal startup and in Test
layer. mode, as well.
∗ When starting up with [TV/LDP] in Test mode, all the steps (1)
to (18) are performed for a DVD, and steps (1) to (10) are
performed for a CD. 3.8.8 AFB (Auto Focus Bias) Function
Overview
Among the first-generation models, this function supports only CDs
with the basic models, such as the DV-7. Among the new models,
3.8.4 Peak Detection this function supports DVDs with all models, but CDs only with the
basic models. The operation is executed only once (once for each
Overview
layer for a 2-layer DVD) after the focus and tracking AGC at startup.
This is a new function to measure the size and location of the sine The operation is accomplished not by centering the focus servo to
wave related to focus errors at the beginning. The measurement is Vref (2.5 V), but by gradually changing the center value for the
performed in the normal startup process and in Test mode, as well. optimum jitter value. Thus, performance with an improper or dirty
If the sine wave is small, the OE IC gain is switched. Only the disc (by fingerprints, etc.), or the temperature characteristics (at 0°C,
judgment for NO DISC is accomplished at this time. The operation 35°C, etc.) will be improved.
is in effect as for judgment for DISC .
OverviewUsing the Function in Test mode
Using the Function in Test Mode (the Remote Control Keys to be Used are
This function is not assigned to any remote control keys. Only an
Indicated in Brackets)
open/close operation can trigger the function.
As the function is to be synchronized with AGC, turn on and off
AFB by pressing [TEST] + [7]. The jitter value measurement cannot
3.8.5 Disc Distinction be made with AFB ON.
Overview
This function is almost the same as that with the first-generation
models. The only difference is as follows: If an error occurs in the
startup sequence and playback cannot be started, startup is retried
after forcibly switching the disc distinction from DVD to CD or
vice verse by a backup process. If startup fails again, it is canceled,
and an error is generated. The types of error that triggers the backup
process for disc distinction are discussed in the next section.
20
DV-505, DVL-909, DV-S9
3.8.9 PLAY AGC (5) Automatic Sequence Errors (Errors 51 to 55)

If any automatic sequence (auto execution command) of the servo
Overview
DSP is not completed, these errors are generated. The causes differ
The SGC voltage is adjusted during playback according to the RF among error numbers. They may be caused by abnormalities in the
signal level. (For details on SGC, see section 3.8.6.) communication line between the mechanism-control computer
Only for CDs in basic models, such as the DV-505 (including the (PD4889A) and the servo DSP or instability of the XABUSY
DV-S9), this adjustment is made only once immediately after AFB connector (pin 38) of the mechanism-control computer.
during startup. In Test mode, it synchronizes with AGC ON/OFF.
The operation is achieved through adjustment in the Servo DSP
(LC78650), and the SGC voltage is output via AUX0 (pin 44). (6) DSP Communication Errors (Errors a1 to a6)
These errors will be generated if the mechanism-control computer
Using the Function in Test Mode cannot properly communicate with the servo DSP. They may be
caused by instability of the XCBUSY connector (pin 8) of the
(the Remote Control Keys to be Used are Indicated
mechanism-control computer, instability of the communication line
in Brackets) between the mechanism-control computer and the servo DSP, or a
As the function is to be synchronized with AGC, turn on and off defect in the servo DSP.
AFB by pressing [TEST] + [7].
(7) DVD Block Noise, etc.
Block noise and momentary picture freeze (∗) with a DVD are not
regarded as errors, but the causes of these symptoms in the Servo
3.9 Additional Descriptions of Error system may be:
(1) A search takes a long time (leading to a search error if it worsens).
Generation (2) Codes cannot be read clearly (leading to a code misread error if
This section describes the major errors of the mechanism-control it worsens).
computer. If the value to the right in the “ER: : e–” indication displayed
on the screen by pressing the ESC and DISP keys of the remote
(1) DISC Distinction Error (Error 38) control in Test mode is greater than 5, the cause may be (1). If
The most common error. The tracking overcurrent error (Error c3), the value is less then 3, the cause may be (2).
Defocus error (Error 33), spindle errors (Errors 41 to 4b), auto
sequence errors (Errors 51 to 55) and code misread errors (71 to 74) (∗) With a specific 2-layer disc with which playback continues from
often lead to this error. layer 1 to 2 or vice versa, the picture may be seen momentarily
stop. This may be attributed to the performance of the player.
Players of other manufacturers have the same symptoms to
(2) Search Errors (Errors 11, 12, 19)
varying degrees.
Almost all cases where playback suddenly stops may involve these
errors. They may be generated because of defects on the disc, or if
the pickup goes too far over the inner periphery with DVD/LD-
compatible models. As with the code misread errors below, they
can also be generated by a dirty disc or bad jitters.
(3) Code Misread Errors (Errors 71 to 74)

Almost all cases where the inserted disc does not start or immediately
stops playing may involve these errors. They may be generated
because of a dirty disc or bad jitters. A bad jitter may be caused by
a dirty disc, decentering, surface deflection, birefringence (double
reflection), or a pickup problem (dirty lens, etc.), misadjustments of
the pickup, improper automatic adjustment, or incomplete
adjustments.
(4) Spindle Errors (Errors 48, 49)

An FG transition timeout (Error 48) may be generated because of
instability of the FG signal or unavailability of spindle drive voltage.
A PLL transition timeout (Error 49) can be generated with a dirty
disc.
21
DV-505, DVL-909, DV-S9
4. IC INFORMATION
• The information shown in the list is basic information and may not correspond exactly to that shown in the schematic diagrams.
• List of IC
PD4890A, PD0260A2, PD0261A2, LA9700M, BA6195FP, LC78650E-P, PD4889A, SRM2B256SLMX70, VYW1536, PD3381A,
MB86371, MB811171622A-100FN, CY2081SL-611, PD2058A
PD4890A (FLKB ASSY : IC101)

• Mode Control IC
• Block Diagram
47 P00
TO0/P30 43 16-bit TIMER/ 44
PORT0 P01-P03
TI0/INTP0/P00 47 EVENT COUNTER 46
31 P04
TO1/P31 42 8-bit TIMER/ 21
PORT1 P10-P17
TI1/P33 40 EVENT COUNTER 1 28
TO2/P32 9
41 8-bit TIMER/ PORT2 P20-P27
TI2/P34 39 EVENT COUNTER 2 16
36
WATCHDOG TIMER PORT3 P30-P37
43
WATCH TIMER 18,19

PORT7 49-51 P70-P74
6-bit UP/DOWN
CI0/INTP3/P03 44
COUNTER 7 P80
PORT8
6 P81
SI0/SB0/P25 11
SERIAL 78K/0 ROM
SO0/SB1/P26 10 1-5
INTERFACE 0 CPU CORE PORT9 78-80
P90-P97
SCK0/P27 9
SI1/P20 16 69,70
PORT10 72-77 P100-P107
SO1/P21 15
SERIAL
SCK1/P22 14
INTERFACE 1
STB/P23 13 61
PORT11 P110-P117
BUSY/P24 12 68
ANI0/P10- 21 53
PORT12 P120-P127
ANI7/P17 28 RAM 60
AVDD 29 A/D CONVERTER

AVSS 20 1-7,
FIP 53-70 FIP0-FIP33
AVREF 30 72-80
CONTROLLER/
DRIVER
INTP0/TI0/P00- 44 INTERRUPT 71 VLOAD
INTP3/CI0/P03 47 CONTROL
17 RESET
BUZ/P36 37 BUZZER OUTPUT 34 X1
SYSTEM
35 X2
CONTROL
CLOCK OUTPUT 31 XT1/P04
PCL/P35 38
CONTROL 32 XT2
8,52 33 48
VDD VSS IC
22
DV-505, DVL-909, DV-S9
• Pin Function
No. Mark Pin Name I/O Function
1 P94 G7
2 P93 G6
3 P92 G5
4 P91 G4 O FL timing output H : ON
5 P90 G3
6 P81 G2
7 P80 G1
8 VDD VCC − Power supply pin
9 P27 (NC)
10 P26 (NC) O Not used
11 P25 (NC)
12 P24 LAMP O DVD lamp ON/OFF H : ON
Communication handshake line with the system controller
13 P23 XREADY O
L :Permit the communication
14 P22 SCK I/O Communication clock output with the system controller
15 P21 SO I/O Communication data output with the system controller
16 P20 SI I Communication data input with the system controller
17 RESET RESET IN I Reset input L : reset
(NC) (DV-505) O Not used
18 P74
SIDE A LED (DVL-909) O SIDE A LED ON/OFF L : ON
19 P73
SIDE B LED (DVL-909) O SIDE B LED ON/OFF L : ON
20 AVss Vss − GND pin
21 P17 POWER ON O SW 5V ON/OFF H : ON
22 P16 RESET OUT O System reset output L : reset
23 P15 (NC)
O Not used
24 P14 (NC)
25 P13 KIN1
I Key input
26 P12 KIN0
27 P11 MS1
I Destination judgement input
28 P10 MS0
29 AVDD AVDD − Power supply pin
30 AVREF AVREF − Reference voltage
31 P04 P04 I Not used
32 XT2 (NC) − Not used
33 VSS VSS − GND pin
34 X1 X1 I
Connect a microprocessor clock
35 X2 X2 −
36 P37 (NC)
38 P35 (NC)
39 P34 P34
I Not used
40 P33 P33
23
DV-505, DVL-909, DV-S9
No. Mark Pin Name I/O Function

41 P32 P32
I Not used
42 P31 P31
43 P30 (NC) I Not used
44 P03 P03 I Not used
45 P02 ON POWER I Switch the STBY/POWER ON at rising edge the FL controller L : STBY
Communication handshake line with the system controller
46 P01 LT I
H : Permit the communication
47 P00 SEL IR I Remote control signal input
48 IC IC − −−−−
FL OFF LED (DV-505) O FL OFF LED ON/OFF L : ON
50 P71
(NC) (DVL-909) O Not used
52 VDD VDD − Power supply pin
53 P127
FL OFF LED (DVL-909) O FL OFF LED ON/OFF H : ON
54 P126 (NC)
55 P125 (NC)
56 P124 (NC)
58 P122 (NC)
59 P121 (NC)
60 P120 (NC)
61 P117 P15
62 P116 P14
63 P115 P13
64 P114 P12
65 P113 P11
O FL segment output H : ON
66 P112 P10
67 P111 P9
68 P110 P8
69 P107 P7
70 P106 P6
71 VLOAD -27V − – 27V input H : ON
72 P105 P5
73 P104 P4
74 P103 P3 O FL segment output H : ON
75 P102 P2
76 P101 P1
77 P100 G11
78 P97 G10
O FL timing output H : ON
79 P96 G9
80 P95 G8
24
DV-505, DVL-909, DV-S9
PD0260A2, PD0261A2 (CLDM ASSY : IC101)(DVL-909 ONLY)

• Mechanism Control IC
• Pin Function
No. Pin Name I/O Function
1 VCC I Power supply pin Apply 5V ± 10%
2 RWC O DSP read/write command signal output "L"= Read "H"= Write
3 XPLAY O Signal output during spindle servo "L"= During servo "H"= During acceleration, brake and stop
4 CLK:SCK3/CQCK O DVP/DSP clock switch "H"= DVP "L"= DSP
5 XCD O LD/CD switch signal output "L= CD "H"= LD
A/D • This signal is A/D converted as the tilt servo control input. Control the tilt motor so that this signal
6 TILT ERR I
becomes 2.5V.
7 TRK BAL ERR I A/D • Tracking balance error signal input This signal is A/D converted as the tracking offset control input.
A/D • This signal is A/D converted as the slider servo control input.
8 SLD ERR I
Control the slider motor so that this signal becomes 2.5V.
A/D • Pickup position detection switch input
9 SLD POS I
Detect the position by reading A/D input value which each switches are resistance divided.
10 FSEQ I Subcode sync. confirmity detection signal input "L"= Not confirmity "H"= Confirmity
11 C DETECT I Spindle over-current detection signal input "L" = Over current "H"= Normal
PWM • Output the tracking offset signal to PWM output, then use for auto tracking offset.
12 TRK BAL DRV O
910 µsec period, tri-state control H, L, Z
Handshake signal for data communication with the DVD mechanism control IC
13 SHAKE I/O
This pin is the bilateral data line and each microprocessor control the Input/Output.
RF correction switch signal output "H"= Gain UP CD, CDV-A:Low, CAV inner circuit gain up, others are
14 RF CORRECTION O
High.
15 SQOUT I Command data input from DSP Read out SUBQ
16 SO3/COIN O Command data output to DVP/DSP
17 SCK3/CQCK O DVP/DSP read/write command clock output Read-in at rising edge
18 SLD OUT O PWM • Slider control signal output 5V= FWD, 0V= REV, 2.5V= STOP 910 µsec period, tri-state control
19 SI1 I Data input from the DVD mechanism control IC
20 SO1 O Serial data output to the DVD mechanism control IC
Clock for serial communication with the DVD mechanism control IC
21 SCK I/O
Becomes input mode without communicate with the DVD mechanism control IC
INT • Tracking error zero cross signal input
22 TRK 0 CRS I
Monitor this signal when searching track count in the miss clamp detection
23 SBSY I Subcode block sync. input
LOAD/TILT control output
24 TILT OUT I/O
PWM output 0V : Tray IN / Tilt DOWN, 5V : Tray OUT / Tilt UP, 2.5V : STOP
25 TURN OUT O Turn drive signal output
26 XPBV I Playback vertical sync. signal input of LD/CDV "L"= During vertical sync.
27 CNVSS I Ground for A/D conversion
28 XRESET I Reset signal input "L"= Reset "H"= Release reset Control with the DVD mechanism control IC.
29 XIN I 9MHz clock oscillation input
30 XOUT O 9MHz clock oscillation output
25
DV-505, DVL-909, DV-S9

31 PHAI O Not used
32 GND I Ground
33 SW1
34 SW3 I Switch input for Loading/Tilt position detection
35 SW2
36 TBCLOCK I Spindle lock signal input "L"= Unlock "H"= Lock
37 FG I Spindle motor FG signal input 16 outputs per rotation Used after dividing by 2 in the microprocessor
38 DATA I Input for Phillips code decoder with built-in mechanism controller
39 XPBH I Playback H-SYNC input for Phillips code decoder
40 XPBV I Playback V-SYNC input for Phillips code decoder
41 DEXT O Control signal output of video dynamic range extension "H"= ON "L"= OFF
Field discrimination signal from DVP "H"= ODD "L"= EVEN (with memory)
42 WFM/VLOCK I
VLOCK signal at clear scan (with no memory)
43 LATMEM O Serial control latch output of memory control IC PD3212A Latches at falling edge.
PD0260A2 : 17MHz PLL control signal output H : Phase comparison L : Free-run
44 XPFR O
PD0261A2 : Not used
PD0260A2 : NTSC/XPAL circuit switching signal output excepting VDEM H : NTSC L : PAL
45 XP/N2 O
PD0261A2 : Not used
PD0260A2 : Control signal output of the High Quality circuit (analog NR)
46 HQ O H : Through the HQ circuit L : Not through
PD0261A2 : Not used
47 THLD I Track jump accelerating / decelerating signal input "L"= Others "H"= During accelerating / decelerating
48 LATDVP O PD6159B serial latch signal output Latches at falling edge.
49 SELTZC O TZC switch signal output "H"= at normal "L"= at CD/DVD disc discrimination
50 DOCINH O Control the clamp pulse and clamp killer circuit by tri-state value
PD0260A2 : NTSC/XPAL circuit switching signal output for VDEM H : NTSC L : PAL
51 XP/N1 O
PD0261A2 : Not used
52 NROFF O Noise reduction control output by VDEM "L"= Normal "H"= Not NR
Disc present/absent detecting signal input by the tilt sum in the DVD P.U. mode
53 DSCDET I
"H"= Absent "L"= Present DEFECT input at LD P.U.
54 XTURNB I Turn switch input "H"= Side A / turn "L"= Side B
55 XTURNA I Turn switch input "H"= Side B / turn "L"= Side A
56 XLPO I LD P.U. out position detecting switch input "H"= LD P.U. active "L"= LD P.U. out position
57 VDET I Use for power abnormal signal input port "L"= Normal "H"= Abnormal
58 XFOK I Focus servo lock signal input "L"= Lock "H"= Unlock Use for lock detection of focus servo
Subcode Q reading OK signal input "L"= NG "H"= OK
59 WRQ I
This pin will be H when subcode Q data passed by CRC check.
60 AC3MUTE O Mute control signal output for AC3 Release MUTE during playback. "L"= Release MUTE "H"= MUTE
61 SQ1 O Analog audio switching signal output 1/L "L"= Squelch OFF "H"= Squelch ON
62 SQ2 O Analog audio switching signal output 2/R "L"= Squelch OFF "H"= Squelch ON
63 XCX O Analog audio CX noise reduction switching signal output "L"= CX ON "H"= CX OFF
64 XANA O Digital / Analog audio switching signal output "L"= Analog "H"= Digital
26
DV-505, DVL-909, DV-S9
LA9700M (DVDM ASSY : IC101)

• RF IC
• Block Diagram
RFOUT
DEPC
DLPC
DEFI
GND
PHC
BHC
RFO
REF
DEF
EQI
PHI
BHI
PH
BH
TC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
50k
REF Scratch Detection
PDRF– 1 48 BPI1
VCC REF VCC
PH BH PH BH
50k
–
REFI 2 47 VCC
+
–
+
50k
80k 26p REF

80k
RFI 3 45k 46 BPO1
80k
–
80k
+
PDRF 4 LIM 45 EQB
1k
3k
REF
PD1 5 LIM PD 44 BPO2
–
+
3k
26p
PD2 6 LIM PD 43 N/C
CP
40k 60k
40k
–
+
–
PD3 7 LIM PD + 42 BPI2
40k
40k 60k
PD4 8 LIM PD 41 N/C
26p
1k
+ 10p REF
PD5 9 –
80k
15k 60k 40 DLAY1
3k
+
–
–
3k
+ +
PD6 10 –
80k 60k
39 DLAY2
REF 15k 10p
LDD 11 REF 38 MIXO1
APC
VCC
LDS 12 37 VCC
+
–
LDON 13 36 MIXI1
AGOF 14 35 MIXI2
20k
10k
+
–
PH/RR 15 34 GND
–
+
REF
QAGC 16 REF
+ 33 MIXO2
10k
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
QPH/BH
DVD/CD
DPD/TE
CPOF
TEBAL
SGC
TES
TESI
RREC
TE
TLP
CP
TEO
TE–
FE
EFMO
27
DV-505, DVL-909, DV-S9
BA6195FP (DVDM ASSY : IC161)

• Spindle Driver
• Block Diagram
OPIN+
OPIN–
MUTE
GND
GND
VCC
NC
NC
NC
NC
NC
NC
25 24 23 22 21 20 19 18 17 16 15 14
NC NC NC NC NC NC
GND TSD GND
Driver mute VCC
IN Level shift
10K 10K
10K
10K
10K 10K
NC NC NC NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13
OPOUT
NC
NC
BIAS
DRIN'
DRIN
NC
NC
NC
NC
NC
DROUT–
DROUT+
• Pin Function
No. Pin Name Function No. Pin Name Function
1 OPOUT OP amp. output pin 14 N.C.
2 N.C. 15 N.C. Non Connection
Non Connection
3 N.C. 16 N.C.
4 BIAS Bias pin 17 VCC Power supply pin
5 DRIN' Driver gain adjustment pin 18 N.C. Non Connection
6 DRIN Driver gain input pin 19 GND
Sub-strait GND pin
7 N.C. 20 GND
9 N.C. Non Connection 22 MUTE Mute pin
11 N.C. 24 OPIN + OP amp. non-inverting input pin
12 DROUT – Driver negative output pin (for input)
25 OPIN – OP amp. inverting input pin
13 DROUT + Driver positive output pin (for input)
28
DV-505, DVL-909, DV-S9
LC78650E-P (DVDM ASSY : IC201)(DVL-909 only)

• Servo DSP LSI
• Block Diagram
FE 35 49 FDO
TE 34 50 TDO
47 SLDO
TILTE 31 8bit Servo 8bit
MPX Processor 48 SPDO
A/D D/A
RF_PH 32 (16×16+32→32) 46 TBAL
RF_BH 33 45 TILTDO
JITT 30 44 AUXO
61 VREF
HFL 63 CMP
26 DRF
Track Counter 55 DVD_CDB
TES 28
1 PP5/SYNC
PP7/EVNT 58 Event Counter
LCD Driver 56 LCDCNTL
PP6/FG 57 FG Counter
SLCIST1,2 36,37
EFMIN 41 25 V_PB
SLC
SLCO1,2 38,39 CLV 24 FAST
EFMOUT 3
79 WRQ
PCKIST1,2 89,90
76 SQOUT
CDFR 93 Frame Synchronous Sub Code
CD-PLL 77 CQCKB
Detection, Protection, Decode
78 RWC
DVDFR 92 Insertion EFM CRC
DVD-PLL Demodulation 19 EMPH
PD01-3 85-87
14 PW
JV 94
12 SBCK
LEFM 2
20 SBSY
PCK 95
13 SFSY
VRPFR 81 For De-Interleave
VCOC 82 Error Detect 16k SRAM
Clock Correction
VPDO 83 11 FSX
Generator C1-Twofold,
XIN 16
C2-Fourfold 4 C2F
XOUT 17 22 EFLG
XTALOUT 10
CSB 60
DOUT 21 DOUT
WRB 62 Supplement/Mute
Command D Attenuate
RDB 61
Interface Deemphasis Filter 7 LRSY
P0-7 65-72
Serial Out 6 ROMCK
BUSYB 75
5 ROMXA
LASER 54
PP0-4 96-100 27,29 TEST1-4

40,52
RESB 59
29
DV-505, DVL-909, DV-S9
• Pin Function
1 PP5/SYNC I/O General-purpose port input/output / DVD sync. signal input
2 LEFM O Output the state that cut and out a signal which was binary-stated value EFM/EFM + with PCK.
3 EFMOUT O Output the state that was binary-stated value EFM/EFM + .
4 C2F O C2 flag output
5 ROMXA O ROMXA data output
6 ROMCK O Shift clock output for ROMXA data output
7 LRSY O L/R clock output for ROMXA data output
8 DVDD2 − 5V power supply
9 VSS − GND
10 XTALOUT O External system clock output
11 FSX O CD 1 frame sync. signal output
12 SBCK I Subcode reading out clock input
13 SFSY O Frame sync. signal output of subcode
14 PW O Subcode P, Q, R, S, T, U, V and W output
15 VSS − GND for oscillation circuit
16 XIN I Connect a crystal resonator (16.9344MHz)
17 XOUT O Connect a crystal resonator
18 DVDD1 − 3.3V power supply of the oscillation circuit
19 EMPH O Monitor the deemphasis
20 SBSY O Sync. signal output of the subcode block
21 DOUT O Output for the digital audio I/F
22 EFLG O Error correction state monitor of the error correction C1 and C2
23 FSEQ O Detection monitor of the CD/DVD frame sync. signal
24 FAST O Playback speed monitor
25 V_PB O Monitor output of the rough servo/CLV control
26 DRF O In focus monitor
27 TEST3 I Test input 3
28 TES I Tracking error signal input
30 JITT I Jitter quantity detecting signal input of EFM/EFM + PLL
31 TILTE I Tilt error signal input
32 RF_PH I RF peak hold signal input
33 RF_BH I RF bottom hold signal input
34 TE I Tracking error signal input
35 FE I Focus error signal input
36 SLCIST1 − Current setting pin 1 of the constant current charge pump for SLC
37 SLCIST2 − Current setting pin 2 of the constant current charge pump for SLC
38 SLCO1 − Control output 1 for SLC
39 SLCO2 − Control output 2 for SLC
41 EFMIN I EFM/EFM + input
42 AVDD − 5V power supply of A/D and D/A for servo
43 AVSS − GND of A/D and D/A for servo
44 AUXO O DA auxiliary output
45 TILTDO O Tilt control signal output
46 TBAL O Tracking balance control signal output
47 SLDO O Sled control signal output
48 SPDO O Spindle control signal output
49 FDO O Focus control signal output
50 TDO O Tracking control signal output
30
DV-505, DVL-909, DV-S9

51 VREF − Reference level of A/D and D/A for servo
53 HFL O Track detection signal output
54 LASER O For laser ON/OFF control
55 DVD_CDB O Disc discrimination result output
56 LCDCNTL O Pickup liquid shutter control signal output
57 PP6/FG I/O General-purpose port input/output / FG signal input
58 PP7/EVNT I/O General-purpose port input/output / Event counter input
59 RESB I Reset input
60 CSB I Chip select input
61 RDB I Internal state reading signal input
62 WRB I Command / data writing signal input
63 DVDD2 − 5V power supply
64 VSS − GND
65 P0
66 P1
67 P2
68 P3
I/O Command / data input/output
69 P4
70 P5
71 P6
72 P7
73 VSS − GND
74 DVDD1 − 3.3V power supply for internal logic
75 BUSYB O Busy signal output of command process
76 SQOUT O Serial output of subcode Q
77 CQCKB I Data read-out shift clock input of subcode Q
78 RWC I Serial output update permission input of subcode Q
79 WRQ O Read out ready monitor of subcode Q
80 VSS − PLL GND for internal system clock
81 VRPFR − VCO oscillation range setting of PLL for internal system clock
82 VCOC
− Connect a PLL filter for internal system clock
83 VPDO
84 DVDD2 − PLL 5V power supply for internal system clock
85 PDO1 − PLL filter connection pin 1 for EFM/EFM + playback
88 VSS − PLL GND for EFM/EFM + playback
89 PCKIST1 − Current setting 1 of PLL constant current charge pump for EFM/EFM + playback
90 PCKIST2 − Current setting 2 of PLL constant current charge pump for EFM/EFM + playback
91 DVDD2 − PLL 5V power supply for EFM/EFM + playback
92 DVDFR − VCO oscillation range setting of PLL for EFM + playback
93 CDFR − VCO oscillation range setting of PLL for EFM playback
94 JV O Jitter monitor of PLL clock for EFM/EFM + playback
95 PCK O Bit clock output for EFM/EFM + playback
96 PP0
97 PP1
98 PP2 I/O General-purpose port input/output
99 PP3
100 PP4
31
DV-505, DVL-909, DV-S9
PD4889A (DVDM ASSY : IC501)

• Mechanism Control IC
• Pin Function
No. Pin Name I/O Function No. Pin Name I/O Function
1 LODDRV I/O Loading motor drive output 33 XDSPRST − Reset pulse for servo DSP "L"
Address strobe of multiplexed address/data
2 DVD/XCD O Clock switch H : DVD , L : CD 34 ASTB O
bus "H"
3 AGOFF O Turn AGC of RF IC to OFF for "H" 35 XRST I CPU reset input "L"
Count data input of error rate Subcode frame sync. input
4 EFLG I 36 SBSY INT
Measureable by using timer 1 and 2. (H : S0+S1 period)
Error rate count area input (EFM frame sync.) Communication handshake of CLD
5 FS X I 37 SHAKE INT
H : C1 , L : C2 mechanism controller "L" (DVL-909 only)
6 P35/PCL − Not used (pull down) 38 XABUSY INT DSP auto sequence busy input "L"
High impedance (input) at DEFECT ON
7 XTOFF I/O 39 XIRQ2 INT LSI-11 interrupt input "L"
"L" output at DEFECT OFF
8 XCBUSY I DVD command reception is possible "L" 40 VDD − Power supply pin
9 VSS − GND 41 X2 −
Connect a ceramic resonator
10 MAD0 42 X1 −
11 MAD1 43 IC (Vpp) − GND
12 MAD2 44 XT2 − Not used
Park position detection of compatible DVD
13 MAD3 45 DVDPPK I
I/O External address / data bus pickup "L" (DVL-909 only)
14 MAD4 46 AVss − GND
15 MAD5 47 LODPOS I Loading and clamp position SW input
16 MAD6 48 SLDPOS I Slider position SW input
17 MAD7 49 DORPOS I Panel position SW input (DV-S9 only)
Acutuator over-current detection input (former
18 MA8 50 XCURDET I
TRDLMT) "L" Servo OFF for 300 ms.
Panel and loading switch of PWM output
19 MA9 51 DR/XLD O
Panel : H , loading : L (DV-S9 only)
20 MA10 O External address bus 52 MON O Spindle motor ON output "H"
21 MA11 53 XCD2X O Not used
22 MA12 54 OEICG O "H" : OEIC gain up to 6dB
23 MA13 55 AVDD − Power supply pin
24 VSS − GND 56 AVREF − Reference power supply pin
25 MA14 57 P_ERR O Not used
O External address bus
26 MA15 58 P21/SO1 − Not used (pull down)
27 DRF I (FOK) Focus OK input 59 P22/XSK1 − Not used (pull down)
(LOCK) EFM servo lock signal
28 V_PB I 60 XCSB O DSP parallel command setting output "L"
"H"/"L"= rough servo / phase servo
29 P62 − Not used (pull down) 61 CLD O CLD circuit block switch (DVL-909 only)
Inputs serial communication output of CLD
30 WRQ I Readable flag of subcode Q 62 LDSO I
mechanism controller (DVL-909 only)
Outputs serial communication input of CLD
31 XRD O CPU read pulse "L" 63 LDSI O
mechanism controller (DVL-909 only)
Inputs serial communication clock output of
32 XWR O CPU write pulse "L" 64 LDSCK I
CLD mechanism controller (DVL-909 only)
32
DV-505, DVL-909, DV-S9
SRM2B256SLMX70 (DVDM ASSY : IC502)

• 256 K SRAM (For Mechanism Control IC)
• Block Diagram
A0 10
A1 9
A2 8
A3 7 Memory-Cell
9 Line 512 Array
A4 6 Decoder
Address Buffer
A5 5 512×64×8
A6 4
A7 3
A8 25
A9 24
64×8
A10 21
A11 23
A12 2 6 64
Row Row Gate
A13 26 Decoder
A14 1
CS
CS 20 Control 8
Logic
OE 22 OE, WE
Control I/O Buffer
WE 27 Logic
14 18 11 12 13 15 16 17 18 19
Vss
VDD
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
• Pin Function
1 A14 15 I/O4
2 A12 16 I/O5
3 A7 17 I/O6 Data input/output
4 A6 18 I/O7
5 A5 19 I/O8
Address input
6 A4 20 CS Chip select
7 A3 21 A10 Address input
8 A2 22 OE Output enable
9 A1 23 A11
10 A0 24 A9
Address input
11 I/O1 25 A8
12 I/O2 Data input/output 26 A13
13 I/O3 27 WE Write enable
14 VSS GND (0V) 28 VDD Power supply (2.7 to 5.5V)
33
DV-505, DVL-909, DV-S9
VYW1536 (DVDM ASSY : IC603)(DV-505 and DVL-909 only)

• Flash ROM
• Block Diagram
RY/BY DQ0-DQ15
15-22,
1
24-31
RY/BY RY/BY
BUFFER
ERASE INPUT/OUTPUT
CIRCUIT BUFFER
WE 43
BYTE 33
CONTROL
RESET 44 CIRCUIT
WRITE
CIRCUIT
CE 12 CHIP ENABLE STB
OUTPUT ENABLE DATA LATCH
OE 14 CIRCUIT
Y DECODER Y GATE
STB ADDRESS LATCH
LOW VCC WRITE/ERASE
DET. CIRCUIT PULSE TIMER 8,388,608
CELL
2-11, X DECODER
A0-A18 34-42 MATRIX
A-1 31
• Pin Function
1 RY/BY Ready / Busy output 23 VCC Power supply (+5.0V ± 10% or ± 5%)
2 A18 24 DQ4
3 A17 25 DQ12
4 A7 26 DQ5
5 A6 27 DQ13 Data input / output
6 A5 28 DQ6
Address input
7 A4 29 DQ14
8 A3 30 DQ7
9 A2 31 DQ15/A-1 Data input/output / address input
10 A1 32 VSS Ground
11 A0 33 BYTE Switch the 8 bit and 16 bit modes
12 CE Chip enable 34 A16
13 VSS Ground 35 A15
14 OE Output enable 36 A14
15 DQ0 37 A13
16 DQ8 38 A12 Address input
17 DQ1 39 A11
18 DQ9 40 A10
Data input/output
19 DQ2 41 A9
20 DQ10 42 A8
21 DQ3 43 WE Write enable
22 DQ11 44 RESET Hardware reset
34
DV-505, DVL-909, DV-S9
PD3381A (DVDM ASSY : IC601)

• System Control CPU
• Block Diagram
PA13/IRQ1/DREQ0/TCLKB
PA12/IRQ0/DACK0/TCLKA
PA9/AH/IRQOUT/ADTRG
PA15/IRQ3/DREQ1
PA11/DPH/TIOCB1
PA14/IRQ2/DACK1
PA1/CS5/RA5/RAS
PA10/DPL/TIOCA1
PA2/CS6/TIOCB0
PA0/CS4/TIOCA0
PA5/WRH(LBS)
PA3/CS7/WAIT
PA4/WRL(WR)
PA8/BREQ
CS1/CASH
PA7/BACK
CS3/CASL
PA6/RD
CS2
CS0
A21
A20
A19
A18
A17
A16
69 68 67 66 65 64 63 62 60 59 58 57 56 55 54 53 51 50 49 48 47 46 45 44 42 41
PORT A ADDRESS
RES 79 39 A15
WDTOVF 78 38 A14
MD2 82 37 A13
MD1 81 36 A12
MD0 80 35 A11
64k PROM / MASK ROM 4kB RAM1
NMI 76 34 A10
33 A9
OSCILLATOR
CK 71 32 A8
ADDRESS
EXTAL 73 30 A7
XTAL 74 29 A6
28 A5
Vpp 77 DIRECT 27 A4
Vcc 15 CPU MEMORY
ACCESS 26 A3
Vcc 43 CONTROLLER 25 A2
Vcc 70 24 A1
Vcc 75 23 A0(HBS)
INTERRUPT USER BREAK BUS STATE
Vcc 83 CONTROLLER CONTROLLER CONTROLLER
Vcc 84 21 AD15
Vcc 99 20 AD14
Vss 3 19 AD13
Vss 12 SERIAL 18 AD12
16BIT
COMMUNICATION
Vss 22 INTERFACE
INTEGRATED 17 AD11
TIMER PULSE UNIT
Vss 31 (×2CHANNEL)
16 AD10
DATA/ADDRESS
Vss 40 14 AD9
Vss 52 PROGRAMABLE
TIMING A/D WATCHDOG 13 AD8
Vss 61 PATTERN CONVERTER TIMER
11 AD7
CONTROLLER
Vss 72 10 AD6
Vss 96 9 AD5
Vss 106 8 AD4
7 AD3
AVref 86 6 AD2
AVcc 85 5 AD1
PORT C PORT B
AVss 91 4 AD0
95 94 93 92 90 89 88 87 2 1 112 111 110 109 108 107 105 104 103 102 101 100 98 97
PC7/AN7
PC6/AN6
PC5/AN5
PC4/AN4
PC3/AN3
PC2/AN2
PC1/AN1
PC0/AN0
PB15/TP15/IRQ7
PB14/TP14/IREQ6
PB13/TP13/IREQ5/SCK1
PB12/TP12/IREQ4/SCK0
PB11/TP11/TxD1
PB10/TP10/RxD1
PB9/TP9/TxD0
PB8/TP8/RxD0
PB7/TP7/TOCXB4/TCLKC
PB6/TP6/TOCXA4/TCLKC
PB5/TP5/TIOCB4
PB4/TP4/TIOCA4
PB3/TP3/TIOCB3
PB2/TP2/TIOCA3
PB1/TP1/TIOCB2
PB0/TP0/TIOCA2
Periphery address bus(24 bit)

Periphery data bus(16 bit)
Internal address bus(24 bit)
Internal upper data(16 bit)
Internal lower data(16 bit)
35
DV-505, DVL-909, DV-S9
• Pin Function
1 PB14/TP14/IRQ6
I/O 16 bit input/output (port B) / Timing pattern output / Interruption request
2 PB15/TP15/IRQ7
3 VSS I Ground
4 AD0
5 AD1
6 AD2
7 AD3
I/O 16 bit bilateral data bus
8 AD4
9 AD5
10 AD6
11 AD7
12 VSS I Ground
13 AD8
14 AD9
15 VCC I Power supply
16 AD10
17 AD11
18 AD12
19 AD13
20 AD14
21 AD15
22 VSS I Ground
23 A0 (HBS) O Address bus output (upper byte strobe signal)
24 A1
25 A2
26 A3
27 A4 O Address bus output
28 A5
29 A6
30 A7
31 VSS I Ground
32 A8
33 A9
34 A10
35 A11
O Address bus output
36 A12
37 A13
38 A14
39 A15
40 VSS I Ground
41 A16
42 A17
36
DV-505, DVL-909, DV-S9

44 A18
45 A19
46 A20
47 A21
48 CS0 O Chip select signal
49 CS1/CASH O Chip select signal / Column address strobe timing signal on the upper side of DRAM
50 CS2 O Chip select signal
51 CS3/CASL O Chip select signal / Column address strobe timing signal on the lower side of DRAM
52 VSS I Ground
16 bit input/output (port A) / Chip select signal /
53 PA0/CS4/TIOCA0 I/O
ITU input capture input/ITU output compare output (channel 0)
54 PA1/CS5/RAS I/O 16 bit input/output (port A) / Chip select signal / Low address strobe timing signal of DRAM
16 bit input/output (port A) / Chip select signal /
55 PA2/CS6/TIOCB0 I/O
56 PA3/CS7/WAIT I/O 16 bit input/output (port A) / Chip select signal / Wait input for bus cycle
57 PA4/WRL (WR) I/O 16 bit input/output (port A) / External lower 8 bit writing (output at writing)
58 PA5/WRH (LBS) I/O 16 bit input/output (port A) / External upperr 8 bit writing (lower byte strobe signal)
59 PA6/RD I/O 16 bit input/output (port A) / External reading out
60 PA7/BACK I/O 16 bit input/output (port A) / Bus claim request acknowledge
61 VSS I Ground
62 PA8/BREQ I/O 16 bit input/output (port A) / Bus claim request
16 bit input/output (port A) / Address hold timing signal / Interruption request output at slave /
63 PA9/AH/IRQOUT/ADTRG I/O
A/D conversion trigger input
16 bit input/output (port A) / Data bus parity on the lower side /
64 PA10/DPL/TIOCA1 I/O
16 bit input/output (port A) / Data bus parity on the upper side /
65 PA11/DPH/TIOCB1 I/O
16 bit input/output (port A) / Interruption request / DMA transfer request reception (channel 0) /
66 PA12/IRQ0/DACK0/TCLKA I/O
ITU timer clock input
16 bit input/output (port A) / Interruption request / DMA transfer request (channel 0) /
67 I/O
PA13/IRQ1/DREQ0/TCLKB ITU timer clock input
68 PA14/IRQ2/DACK1 I/O 16 bit input/output (port A) / Interruption request / DMA transfer request reception (channel 1)
69 PA15/IRQ3/DREQ1 I/O 16 bit input/output (port A) / Interruption request / DMA transfer request (channel 1)
71 CK O System clock output
72 VSS I Ground
73 EXTAL I Crystal oscillator input External clock input
74 XTAL I Crystal oscillator input
76 NMI I Non-maskable interruption input
77 VPP I Power supply of PROM program
78 WDTOVF O Watchdog timer over-flow output
79 RES I Reset input
80 MD0
81 MD1 I Mode setting pins
82 MD2
83 VCC
I Power supply
84 VCC
37
DV-505, DVL-909, DV-S9

85 AVCC I Analog power supply
86 AVREF I Analog reference power supply
87 PC0/AN0
88 PC1/AN1
I 8 bit input (port C) / Analog signal input
89 PC2/AN2
90 PC3/AN3
91 AVSS I Analog Ground
92 PC4/AN4
93 PC5/AN5
I 8 bit input (port C) / Analog signal input
94 PC6/AN6
95 PC7/AN7
96 VSS I Ground
97 PB0/TP0/TIOCA2 16 bit input/output (port B) / Timing pattern output / ITU input capture input/ITU output compare
I/O
98 PB1/TP1/TIOCB2 output (channel 2)

I/O
I/O
104 PB6/TP6/TOCXA4/TCLKC 16 bit input/output (port B) / Timing pattern output / ITU output compare output (channel 4) /
I/O
105 PB7/TP7/TOCXB4/TCLKD ITU timer clock input
106 VSS I Ground

107 PB8/TP8/RXD0 I/O 16 bit input/output (port B) / Timing pattern output / Receive data input (channel 0)
108 PB9/TP9/TXD0 I/O 16 bit input/output (port B) / Timing pattern output / Transmission data output (channel 0)
109 PB10/TP10/RXD1 I/O 16 bit input/output (port B) / Timing pattern output / Receive data input (channel 1)
110 PB11/TP11/TXD1 I/O 16 bit input/output (port B) / Timing pattern output / Transmission data output (channel 1)
16 bit input/output (port B) / Timing pattern output / Interruption request /
111 PB12/TP12/IRQ4/SCK0 I/O
Serial clock input/output (channel 0)
16 bit input/output (port B) / Timing pattern output / Interruption request /
112 PB13/TP13/IRQ5/SCK1 I/O
Serial clock input/output (channel 1)
38
DV-505, DVL-909, DV-S9
MB86371 (DVDM ASSY : IC801)

• MPEG2 Decoder LSI For DVD
• Block Diagram
Exclusive
Parallel port 16Mbit
CPU
Input Signal SDRAM
CPU System Memory

Interface Decoder Block Controller Block
Internal
Bus
Video OSD Sub-

Sync. Decoder picture
Control Block
Block
MIX
Starting
Reset Control Signal
Picture
Signal Block Block
Reset Signal
Whole Control Audio

Block Decoder
Block
NTSC/PAL
Clock Video Encoder
Signal Digital
System System Clock Signal Output
Clock
(Component/
Generation
Clock for video Composite)
Block
27MHz
DAC
Audio Video Output

LPF Clock Clock for audio Block
Generation
VCO Block
Clock
Generation
Block
Audio Output Video Output (Y,C,Comp/Y,Cb,Cr)
39
DV-505, DVL-909, DV-S9
• Pin Function
1 CLKSEL I ON/OFF signal of PLL ("H" : ON, "L" : OFF) 27 VDD − 3.3V power supply
Digital component signal output (MSB)
2 DIGCPN7 O 28 DIGCOMP4
Digital Y signal output (9-bit) (MSB)
3 VSS − GND 29 DIGCOMP3 Digital composite signal output
Digital C signal output
4 DIGCPN6 30 DIGCOMP2 O
5 DIGCPN5 31 DIGCOMP1
Digital composite signal output (LSB)
6 DIGCPN4 Digital component signal output 32 DIGCOMP0
O Digital C signal output (LSB)
Digital Y signal output (9-bit)
7 DIGCPN3 33 DACK O 27 MHz clock output
8 DIGCPN2 34 N.C. − Non connection
9 DIGCPN1 35 VSSA3 − GND (D/A converter)
10 VDD − 3.3V power supply 36 ANAC O Analog color (C) output signal
Digital component signal output (LSB) 3.3V power supply (for built-in D/A converter
11 DIGCPN0 O 37 VDDA3 −
Digital Y signal output (9-bit) (LSB) only)
Cb and Cr discrimination signal at the digital
12 RBSEL O component signal output. 38 VSSA2 − GND (D/A converter)
LSB at the digital Y signal output.
13 XHS O Horizontal sync. output signal 39 ANAY O Analog luminance (Y) output signal
3.3V power supply (for built-in D/A converter
14 XVS O Vertical sync. output signal 40 VDDA2 −
only)
15 VSS − GND 41 VREF I Reference voltage for D/A converter
16 XRESET I LSI reset signal 42 VRO O Internal current setting pin of D/A converter
17 XLDCSYNC I External sync. signal input (LD mode) 43 N.C. − Non connection
KEY signal for LD and OSD overlay
18 KEY O 44 VSSA1 − GND (D/A converter)
(LD mode)
Phase comparison result output signal of
19 PD O 45 ANACOMP O Analog composite output signal
horizontal sync. (LD mode)
Field discrimination signal at the digital signal 3.3V power supply (for built-in D/A converter
20 VFLD O 46 VDDA1 −
output H : even field L : odd field only)
Digital composite signal output (MSB)
21 DIGCOMP9 47 BF O Burst flag signal
Digital C signal output (MSB)
22 DIGCOMP8 48 XBLK O H/V composite blanking signal
O
23 DIGCOMP7 Digital composite signal output 49 N.C. − Non connection
24 DIGCOMP6 Digital C signal output 50 VSS − GND
25 DIGCOMP5 51 TEST0 − Normally, set to "open".
26 VSS − GND 52 TEST1 − "L" status normally
40
DV-505, DVL-909, DV-S9
53 DAIIN I Digital data input of external input (SPDIF) 92 HADRS10 I CPU address bus signal (MSB)
Audio data input of external input
54 CDDATA I 93 HADRS9
(correspond to CD)
Data channel clock input of external input
55 CDLR I 94 HADRS8 I CPU address bus signal
(correspond to CD)
Data clock input of external input
56 CDBCK I 95 HADRS7
(correspond to CD)
57 AODATA3 96 VSS − GND
58 AODATA2 O Audio decode data 97 VDD − 3.3V power supply
59 AODATA1 98 HADRS6
60 VSS − GND 99 HADRS5
CPU address bus signal
61 VDD − 3.3V power supply 100 HADRS4 I
62 AODATA0 O Audio decode data 101 HADRS3
Digital audio interface output
63 AOPCM O 102 HADRS2 CPU address bus signal (LSB)
(compression data)
64 AODAI O Digital audio interface output (decode data) 103 HDATA15 CPU data bus signal (MSB)
65 LRCK O Data channel clock for D/A and digital filter 104 HDATA14
I/O
66 AOMCK O Master clock for D/A and digital filter 105 HDATA13 CPU data bus signal
67 BCK O Bit clock for D/A and digital filter 106 HDATA12
68 ICED1 107 VSS − GND
69 ICED0 Pin for emulator 108 HDATA11
−
70 ICEBRK Normally, set to "open". 109 HDATA10
71 XDSPRST 110 HDATA9
I/O CPU data bus signal
72 VSS − GND 111 HDATA8
73 N.C. − Non connection 112 HDATA7
74 TEST2 113 HDATA6
75 TEST3 114 VDD − 3.3V power supply
− Normally, set to "open".
76 TEST4 115 HDATA5
77 TEST5 116 HDATA4
I/O CPU data bus signal
78 SD7 I Parallel data input 117 HDATA3
79 VDD − 3.3V power supply 118 HDATA2
80 SD6 119 VSS − GND
81 SD5 120 HDATA1 CPU data bus signal
I/O
82 SD4 I Parallel data input 121 HDATA0 CPU data bus signal (LSB)
Bus width selection signal
83 SD3 122 BUSSEL I
(0 : 8-bit bus, 1 : 16-bit bus)
84 SD2 123 XOSDACK I OSD data acknowledge signal
85 VSS − GND 124 XOSDREQ O OSD data request signal
86 SD1 125 HCPUSEL1 CPU selection signal (00 :SPARC,
I Parallel data input I
87 SD0 126 HCPUSEL0 01 :86 system, 10 :68 system, 11 :Reserve)
88 XERR I Error input signal 127 XINT3

89 XSACK I Acknowledge signal 128 XINT2 O Interrupt request signal to the CPU
90 XTEST I Set to "H" at normal use 129 XINT1
91 SREQ O Data request signal 130 VSS − GND
41
DV-505, DVL-909, DV-S9
131 VDD − 3.3V power supply 170 XMDRCAS O CAS signal for SDRAM
Input mask / output enable signal for
132 XINT0 O Interrupt request signal to CPU 171 XMDRDQM1 O
SDRAM
SPARC, 68 system : Ready signal to CPU
133 XEXTRDY O 86 system : Acknowledge (ACK) signal to 172 VSS − GND
CPU
134 HRW I CPU read / write signal 173 XMDRWE O Write enable signal for SDRAM
Input mask / output enable signal for
135 HCLKIN I Host clock input 174 XMDRDQM0 O
SDRAM
136 XHCS I LSI chip select signal 175 MDRDAT8 I/O Data bus signal for SDRAM
SPARC, 68 system : CPU address strobe
137 XHAS I 176 VSS − GND
86 system : CPU address status
138 XHBE3 177 MDRDAT7
I CPU byte enable signal
140 XHBE1 179 MDRDAT6 I/O Data bus signal for SDRAM
142 VSS − GND 181 MDRDAT5
143 MDRADR4 182 VSS − GND
144 MDRADR3 183 VDD − 3.3V power supply
O Address signal for SDRAM
145 MDRADR5 184 MDRDAT11
147 VDD − 3.3V power supply 186 MDRDAT12 I/O Data bus signal for SDRAM
148 VSS − GND 187 MDRDAT3
150 MDRADR1 Address signal for SDRAM 189 VSS − GND
151 MDRADR7 O 190 MDRDAT2
152 MDRADR0 Address signal for SDRAM (LSB) 191 MDRDAT14 Data bus signal for SDRAM
I/O
153 MDRADR8 Address signal for SDRAM 192 MDRDAT1
154 VSS − GND 193 MDRDAT15 Data bus signal for SDRAM (MSB)
155 TEST6 194 MDRDAT0 I/O Data bus signal for SDRAM (LSB)
156 TEST7 195 VSS − GND
− "L" status normally
157 TEST8 196 N.C. − Non connection
158 TEST9 197 ICK27M I System clock input
159 MDRADR10 198 VSS − GND
Address signal for SDRAM
160 MDRADR9 O 199 OCK27M O System clock output
161 MDRADR11 Address signal for SDRAM (MSB) 200 VSSA(VCO) − GND (for VCO only)
162 XMDRCS O Chip select signal for SDRAM 201 VDDA(VCO) − 3.3V power supply (for VCO only)
163 MDRCKE O Clock enable signal for SDRAM 202 ILPF O PLL block inverter output for audio
164 VSS − GND 203 MLPF I PLL block inverter input for audio
165 VDD − 3.3V power supply 204 OLPF O Phase detector output for audio
166 XMDRRAS O RAS signal for SDRAM 205 OVCO I VCO input for audio clock
167 MDRCLK O Clock output signal for SDRAM 206 VSS − GND
168 VSS − GND 207 XPLLRST I PLL section reset signal
169 MDRCLKIN I Clock input signal for SDRAM 208 XSYNCRST I SYNC reset signal
42
DV-505, DVL-909, DV-S9
MB811171622A-100FN (DVDM ASSY : IC802)

• Code Buffer (16M bit SDRAM)
• Block Diagram
CLK 35 Clock To
Bank 1
Buffer Blocks
CKE 34
RAS
Bank 0
CS 18
Control
RAS 17 Command Signal CAS
CAS 16 Decoder Latch
WE
WE 15
DRAM Core
Mode
21-24, 27-32, 20, 19 Address (2,048×256×16)
Register
Buffer/
A0-A11, Register
AP &
Bank Row Address
Select
DQML 14 Column
Address Column Address
DQMU 36
Counter I/O
40,42,43,45,46,48,49
2,3,5,6,8,9,11,12,39,
I/O Data
Buffer/
DQ0-DQ15 Register
1,7,13,25,38,44 4,10,26,41,47,50
VCC/VCCQ VSS/VSSQ
• Pin Function
1 VCC Power supply (+ 3.3V) 26 VSS Ground
2 DQ0 27 A4
Data input/output
3 DQ1 28 A5
4 VSSQ Ground 29 A6 Address input
5 DQ2 30 A7 Row : A0 to A10 , Column : A0 to A7
Data input/output
6 DQ3 31 A8
7 VCCQ Power supply (+ 3.3V) 32 A9
8 DQ4 33 DU Don't use (use for open)
Data input/output
9 DQ5 34 CKE Clock enable
10 VSSQ Ground 35 CLK Clock input
11 DQ6 36 DQMU Input mask / Output enable
Data input/output
12 DQ7 37 DU Don't use (use for open)
13 VCCQ Power supply (+ 3.3V) 38 VCCQ Power supply (+ 3.3V)
14 DQML Input mask / Output enable 39 DQ8
Data input/output
15 WE Write enable 40 DQ9
16 CAS Column address strobe 41 VSSQ Ground
17 RAS Row address strobe 42 DQ10
Data input/output
18 CS Chip select 43 DQ11
19 A11 (BA) Bank select 44 VCCQ Power supply (+ 3.3V)
Address input
20 A10/AP Row : A0 to A10 , Column : A0 to A7 45 DQ12
/ Auto pre-charge enable Data input/output
21 A0 46 DQ13
22 A1 Address input 47 VSSQ Ground
23 A2 Row : A0 to A10 , Column : A0 to A7 48 DQ14
Data input/output
24 A3 49 DQ15
25 VCC Power supply (+ 3.3V) 50 VSS Ground
43
DV-505, DVL-909, DV-S9
CY2081SL-611 (DVDM ASSY : IC813)

• Clock Generate IC
• Block Diagram
XTALIN 3 Refference
Oscillator PLL1 EPROM- 1 CLKA
XTALOUT 4
Configurable
PLL2 Multiplexer 5 CLKB
GND 2 and
PLL3 Drive Logic 6 CLKC
VDD 7
OE/PD/FS/SUSPEND 8
• Pin Function
No. Pin Name Function
1 CLKA Configurable clock output
2 GND Ground
3 XTALIN Reference crystal input or external reference clock input
4 XTALOUT Reference crystal feedback
5 CLKB Configurable clock output
6 CLKC Configurable clock output
7 VDD Voltage supply
Output control pin
8 OE/PD/FS/SUSPEND Either active-High output enable, active-Low power down, CLKA frequency select, or active-Low suspend
input
44
DV-505, DVL-909, DV-S9
PD2058A ( DVDM ASSY : IC901 )(DV-505 and DVL-909 only)

• Digital Signal Processor For Audio
• Block Diagram
TPS16
TPS0
VDDR
VSSR
TES0
TES2
VDD
RST
VSS
1–3,6–11,
45 42–44 13 12 4,31 5,14,34,52
53–60
Coefficient Coefficient Offset RAM

Data RAM RAM ROM 64w×16b
128w×24b 320w×16b 256w×16b Delay RAM
Delay RAM
4096w×16b
Address
Generating
Circuit
Interface bus
Data bus
Work register 35 CKSL
bus
36 PLOFF
24b 16b 32 XI
Temporary 33 XO
Register
Multiply 30 SYNC
Program and add Timing
Serial Data 28,29 ELRI1,ELRI0
Counter Culculator Generation 25,26 EBCI1,EBCI0
Logical Input/Output
24b×16b+43b Circuit
Program Arithmetic Circuit 27 ELRO
ROM Unit(LU) Work Interface Input (2 port) 24 EBCO
1024w×32b Register Circuit Output (3 port)
20 LR
21 WCK
VCO Oscillation 22 FS32
Circuit
23 FS64
46 47 50 48 49 51 18,19 17–15 41 37 40 39 38
CS
IFCD
IFCK
IFDI
IFDO
ACK
SDI1
SDI0
SDO0
SDO2
VDDA
PD
AMPI
AMPO
VSSA
• Pin Function
1 TP8
Test data output pin
2 TP7 O
Normally, use with open.
3 TP6
4 VDD − Power supply pin
5 VSS − Ground pin
6 TP5
7 TP4
8 TP3 Test data output pin
O
9 TP2 Normally, use with open.
10 TP1
11 TP0
45
DV-505, DVL-909, DV-S9

12 VSSR − Ground pin for internal delay RAM (DLRAM)
13 VDDR − Power supply pin for internal delay RAM (DLRAM)
15 SDO2
Serial data output pin
16 SDO1 O
Output data length is able to select the 24-bit or 16-bit by controlling the microprocessor.
17 SDO0
18 SDI1 Serial data input pin
I
19 SDI0 Input data length is able to select the 24-bit or 16-bit by controlling the microprocessor.
20 LR O LR clock output pin (1 fs)
21 WCK O Word clock output pin (2 fs)
22 FS32 O Bit clock output pin (32 fs)
23 FS64 O Bit clock output pin (64 fs)
24 EBC0 I Bit clock input pin Inputs shift clock for SDO0/1/2 data output.
25 EBCI1 Bit clock input pin For SDI1 data input
I
26 EBCI0 Inputs shift clock for SDI0/1 data input. For SDI0 data input
27 ELRO I LR clock input pin Inputs LR clock for SDO0/1/2 data output.
28 ELRI1 LR clock input pin For SDI1 data input
I
29 ELRI0 Inputs LR clock for SDI0/1 data input. For SDI0 data input
Sync. signal input pin Turn the program counter into "0" forcibly by the edge of SYNC signal.
30 SYNC I
Moreover, set the polarity by controlling the microprocessor.
31 VDD − Power supply pin
32 XI I Crystal oscillator connection pin / external clock input pin
33 XO O Crystal oscillator connection pin
35 CKSL I Oscillation clock switch pin L : correspond to 384 fs H : correspond to 512 fs
36 PLOFF I X'tal oscillation mode / VCO oscillation mode switch pin L :built-in VCO oscillation mode H :X'tal oscillation mode
37 PD O Phase comparison data output pin
38 VSSA − Analog ground pin
39 AMPO O Amp. output pin for low-pass filter
40 AMPI I Amp. input pin for low-pass filter
41 VDDA − Analog power supply pin
42 TES0
Test pin
43 TES1 I
Normally, use for "H" or open.
44 TES2
45 RST I Reset signal input pin
46 CS I Chip select signal input pin When CS is L active, data is able to transfer from the microprocessor.
Command or data input mode selection pin from the microprocessor
47 IFCD I
Recognize the command for "H" period and the data for "L" period.
48 IFDI I Microprocessor data input pin Receive the command and data by LSB first.
49 IFDO O Data output pin of data bus (DBUS) Transmit the data of data bus to the microprocessor by LSB first.
50 IFCK I Shift clock input pin for microprocessor data
Acknowledge signal output pin for microprocessor
51 ACK O
When parity of command and data is OK, outputs the acknowledge signal.
53 TP16
54 TP15
55 TP14
56 TP13 Test data output pin
O
57 TP12 Normally, use with open.
58 TP11
59 TP10
60 TP9
46
DV-505, DVL-909, DV-S9
5. FL INFORMATION
VAW1046 (FLKB ASSY : V101)(DV-505 and DVL-909 only)
• FL DISPLAY
1 34
P4
G1
96kHz GUI ANGLE LAST MEMO CONDITION DOLBY P9
P1 TITLE PB CHP / TRK P6 REMAIN TOTAL DIGITAL P7 P8
P6 P5
P3 P10
G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 P13

P1 P2 P11
P12
P14
• ANODE AND GRID ASSIGNMENT

G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11
P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1
P2 ANGLE P2 P2 P2 P2 P2 P2 P2 P2 P2 P2
P3 TITLE P3 P3 P3 P3 P3 P3 P3 P3 P3 P3
P4 LAST MEMO P4 P4 P4 P4 P4 P4 P4 P4 P4 P4
P5 CONDITION P5 P5 P5 P5 P5 P5 P5 P5 P5 P5
P6 P6 P6 P6 P6 P6 P6 P6 P6 P6 P6 P6
P7 CHP/TRK P7 P7 P7 P7 P7 P7 P7 P7 P7 P7
P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8
P9 REMAIN P9 P9 P9 P9 P9 P9 P9 P9 P9 P9
DOLBY
P10 DIGITAL P10 P10 P10 P10 P10 P10 P10 P10 P10 P10
P11 GUI P11 P11 P11 P11 P11 P11 P11 P11 P11 P11
P12 96kHz P12 P12 P12 P12 P12 P12 P12 P12 P12 P12
P13 P13 P13 P13 P13 P13 P13 P13 P13 P13 P13
P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14
P15 TOTAL
• PIN ASSIGNMENT
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Assignment F1 F1 NP P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2
Pin No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Assignment P1 G11 G10 G9 G8 NL NL G7 G6 G5 G4 G3 G2 G1 NP F2 F2
F1, F2 : Filament G1~G11 : Grid P1~P15 : Anode NP : No Pin NL : No Lead
47

DVL 909

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SERVICE GUIDE

Downloaded from www.Manualslib.com manuals search engine

XSACK XSACK MIX

GEN CD-ROM Sync gen.

Slider I/F MPEG2 Sub- GUI

Downloaded from www.Manualslib.com manuals search engine

VIDEO OUT Composite

Loading IC901 M65677FP

SI, SO, SCK,

SLD DRV IC101

14M VCXO IC102, IC103

DVD Y Sync Tip

IC201 JCKB ASSY

1.2 EXPLANATION OF EACH MOVEMENT

1.2.2 Focus Servo

• FOCUS LOCK TIMING

1.2.3 Tracking / Slider Servo

TDO: In addition to the servo output, the low-

1.2.4 SPINDLE SERVO

For a CD, the RF signal output from pin 32 of the RF IC is converted

1.2.5 Disc Determination

None Roughly adjust to

Finely adjust to 1.8Vp-p

1.2.6 System Control (DVL-909)

FLPB, KEYB DVD MAIN

IC701 IC501 IC201

Loading Mech. Cont. XTurn A

1) Interface between Mode Cont. and System Cont. XRDY

2. CIRCUIT DESCRIPTIONS FOR DV-S9 AND DV-09

ON/OFF In addition to NTSC encoding, the M65677FP also performs:

(2) Horizontal and Vertical Contour Compensations (2) C.LEVEL Adjustments

Vertical edge generation

2.1.3 Analog Video Signal Processing Block

4M DRAM µ-COM µ-COM

DVD MAIN ASSY V OUT ASSY

If there is no external input or locking onto the input digital signal

IC901 16M Selector

IC902 18M Selector

IC811 Data Selector

3.3 THE EXPLANATION OF EACH (7) Search Address Input

(11) Tracking Close (20) Tilt Up

(14) Scan In (24) Screen Display On

(19) Tilt Down

3.4 EXPANSION FUNCTION 1 3.5 EXPANSION FUNCTION 2

(3) Focus Sweep (2) Forced CD Setting

(7) DSP coefficient indication of FTS system.

(8) CD Error Rate Indication

3.6 List of Test Mode Function

Key Name of Mode of

Special Mention Item

3.7 Test Mode Screen Display (The Second Generation)

Address Key code

C1 error value of CD and DVD Flash ROM version

CLD mechanism controller revision

• Description of Each Item on the Display (11) FTS servo IC information

(16) Destination setting of the FL controller

Three characters that follow represent the destination code.

Using the Function in Test Mode (The Remote

(22) Version of the AV-1 chip [AV:∗.∗]