7

Building Blocks
of Data Conversion Systems

The design of data conversion systems deals with both architectural issues
and circuit level considerations. The choice of an architecture is influenced
not only by its viability in a given technology but also by the performance of
its constituent building blocks. In fact, the trade-offs that exist at each level of
abstraction often mandate a great deal of iteration between architecture and
circuit design.
In this chapter, we describe the design of building blocks for data ac-
quisition and conversion. These include open-loop amplifiers, operational
amplifiers, and comparators. Issues related to the speed and precision of each
circuit are detailed and the impact of each building block's performance on
that of data conversion systems is discussed.

7.1 AMPLIFIERS
Amplifiers are integral components of analog signal processing systems. In
data acquisition, they are utilized in sampling circuits, subtractors, gain stages,
and pipelined circuits, with each application imposing a different set of re-
quirements on their speed, gain, linearity, noise, dynamic range, and power
dissipation. Here, we study both open-loop and closed-loop amplifiers.
7.1.1 Open-Loop Amplifiers
Open-loop amplifiers have been popular in bipolar technology for two
reasons. First, many bipolar processes do not provide high-speed (vertical)

153
154 Building Blocks of Data Conversion Systems Chap. 7

pnp transistors and hence make it difficult to design high-gain amplifiers

(which usually require high-impedance loads). Thus, only low to moderate
gains are feasible, implying that the benefits resulting from feedback around
amplifiers are quite limited here. Second, open-loop amplifiers generally
exhibit faster settling times than their closed-loop counterparts.
Despite these advantages, open-loop amplifiers must deal with nonide-
alities such as nonlinearity and gain error, which would be suppressed in
closed-loop configurations. Consequently, a variety of correction techniques
have been devised to improve the performance of these amplifiers without
employing global feedback. While linearity is crucial in all circuits, gain er-
ror becomes important only in interstage amplifiers [I] and certain sampling
circuits [2]. In order to understand the linearity issues, we first analyze a
simple bipolar differential pair.

Nonlinearity in a Bipolar Differential Pair. For a simple bipolar

differential pair such as that shown in Figure 7.1 (a), the large-signal output
differential voltage can be expressed as [3]

~d
Vod = RCIEE tanh -'-, (7.1)
2Vr
where V- =kT/q,Rc = RCI = RC2,andtheeffectoffJandbaseandemitter
resistance is neglected. The hyperbolic tangent term in (7.1) approaches a
saturation level of ±l as IVidl exceeds approximately 6VT . Thus, the input

- - - - - - . . - - - Vee _-----4.--... Vee

(a) (b)

Fig. 7.1 (a) Simple bipolar differential pair; (b) emitter-degenerated differ-
ential pair.
Sec. 7.1 Amplifiers 155

linear range is quite limited. For example, since for € « 1, tanh E ~ E- E

3
/3,
(7.1) can be simplified if ~d « 2 VT:

(7.2)

The second term in the parentheses represents nonlinearity in the input/output

characteristic and is greater than 1% of the first term for a Vid as small as
O.35 Vr .
From a small-signal point of view, the gain of the circuit, A v = Vorl / ~d,
can be expressed as

2Rc
Av = --I- ---I
(7.3)
8m l + 8m 2
2Rc ICIlc2
= ------ (7.4)
VT lCI + IC2
2Rc ICIlc2
= -----, (7.5)
VT lEE
suggesting that the gain varies as a function of the differential input voltage
because ICI and lC2 vary. Note that A v also depends on temperature.
The nonlinearity expressed by (7.3) arises because the denominator is a
current-dependent impedance. Therefore, the nonlinearity can be reduced by
either suppressing this dependence in the denominator or creating the same
dependence in the numerator. The first approach leads to emitter degeneration,
and the second to logarithmic loads.

Linearized BipolarDifferentialPair. Figure 7.1 (b) illustrates an emit-

ter-degenerated differential pair. Here, the small-signal gain is

2Rc
Av = g~ II + g;;'2I + 2RE ' (7.6)

indicating that A v becomes less input- and temperature-dependent as 2RE

(= 2REI = 2RE2) becomes much greater than g~: + g,;I.
(This is equivalent
to making IEERE much greater than Vr.) The improvement in linearity,
however, is attained at the cost of lowering the gain or allowing a larger
voltage drop across the collector resistors. The emitter resistors also raise the
input thermal noise and offset voltage.
156 Building Blocks of Data Conversion Systems Chap. 7

Shown in Figure 7.2(a) is a differential pair employing diode-connected

transistors as logarithmic loads. The small-signal gain of this circuit is

(7.7)

(7.8)
~ 1. (7.9)

It follows from (7.9) that the gain of this circuit remains independent of the
bias current-and hence the input voltage-and is close to unity. In practice,
however, nonidealities such as finite {J, finite Early voltage, and degradation
of f3 at low currents limit the usable input range of the circuit to approximately
IOVr.
The performance of the two circuits discussed above can be substantially
improved by combining the two techniques, as depicted in Figure 7.2(b). Here,
the gain can be expressed as

- 8 3
A V -mI
-I
+ R CI + 8 m-I4 + R C2 (7.10)
I '
g~1 + REI + g;;2 + RE2
which for REI = RE2 = RCI = RC2 = R, g,nl = gm3, and 8m2 = 8m4
becomes equal to unity.
In the circuit of Figure 7.2(b), the voltage drop across REI and RE2
severely limits the input and output voltage swings if a high linearity is re-
quired. To alleviate this problem, lEE can be split into two equal current
sources that directly flow from QI and Q2. In such a configuration, shown in
Figure 7.2(c), the current flowing through REI + RE2 is determined only by
the differential input voltage, allowing emitters of Q 1 and Q2 to have voltages
closer to the negative rail.
The circuits of Figure 7.2 suffer from gain error introduced by the finite
(ac) f3 of devices. Starting with (7.10), the reader can easily show that the
gain error is equal to f3 / (fJ + 1). For a typical fJ of 100, this yields a gain
error of 1%.
This error can be significantly reduced by adding resistors with proper
values in series with bases of Q3 and Q4 (Figure 7.3) [I]. Assuming an
infinite Early voltage for all the transistors and noting that the impedance
seen looking into the emitter of Q3 or Q4 is equal to (RB + r1r )/ (fJ + 1),
where RB = RBI = RB2, the reader can show that the small-signal gain of
Sec. 7.1 Amplifiers 157

(a)
-.

-. -. -.
(b)
(b) (c)
Fig. 7.2 (a) Differential pair with logarithmic loads; (b) emitter-degenerated
differential pair with logarithmic loads; (c) circuit of (b) with split
emitter currents.
158 Building Blocks of Data Conversion Systems Chap. 7

r-----.------..-----.--- Vee

Fig.7.3 Differential pair with resistors RBI and R B2 added to correct for
finite fJ.

this circuit is expressed as

RB + rrr
R+---
A - _f3_ f3 + 1 (7.11 )
v - fJ + 1 R + .Iz.: '
13+1
where R = REI = RE2 = Rei = RC2. In order for A v to be identical with
unity,
f3 + I 1
RB =- - R + -r]f. (7.12)
fJ fJ
As an easy, reliable choice, R B ~ R, for which the gain error becomes
proportional to 1/fJ2 rather than 1/fJ.
In addition to the techniques described above, other methods of improv-
ing the linearity and gain error of differential pairs have been proposed [4, 5].
A common drawback of most of these configurations is their limited input and
output voltage swings due to stacked devices and voltage drops across emitter
and collector resistors. This is particularly troublesome for high resolutions
because these voltage drops must be large to ensure high linearity, while the
input and output swings must also be large to provide a wide dynamic range.
For example, when designed for a gain of 2, the circuit of Figure 7.3 requires
±5-V supplies to attain a 2-V swing (a 4- V differential) and 12-bit linearity
and gain precision [I]. The trade-off between the linearity and dynamic range
of such amplifiers makes them less attractive for higher resolutions, especially
if the supply voltage is limited to 5 v.
Sec. 7.1 Amplifiers 159

MOS Differential Pair. The precision techniques described above for

open-loop bipolar circuits do not achieve the same level of performance in
CMOS. For example, consider the CMOS counterpart of Figure 7 .2(a)~ shown
in Figure 7.4(a). If the body of M3 and M4 is connected to ground, the small-
signal gain is

A - (gm3 + gmb3)-1 + (gm4 + gmb4)-1

v - _I -I ' (7.13)
gml +gm2
where gmj denotes the transconductance of Mj and 8mbj represents the small-
signal impedance due to the body effect [3]. The additional term gmbj in this
expression introduces gain error (and nonlinearity) and is difficult to cancel.

...-----e___ VDD

(a) (b)

Fig.7.4 MOS differential pair with diode-connected (a) NMOS and (b)
PMOS loads.

In order to remove the error due to the body effect, the load devices
can be implemented with PMOS transistors, as depicted in Figure 7.4(b),
where A v = (g~~ + g;;l)/(g~: + g';~). However, the gain of this circuit
is not easily defined in modern MOS technologies. To understand why, first
assume M)-M4 are long-channel, square-law devices having equal lengths
and 8m = .J2/D W JLCoxl L. Thus,

(7.14)

where Wl2 = WI = W2 and W34 W3 = =

W4. This equation indicates
that the gain can be precisely set by the ratio (W I 2JLn) / ( W34JLp) . For short-
channel devices, however, carrier velocity saturation is significant and the
160 Building Blocks of Data Conversion Systems Chap. 7

drain current of a MOSFET is approximately equal to

(7.15)

where V sat is the saturation velocity of carriers [6]. The transconductance of

such a device can be expressed as
aID
(7.16)
8m = avos
(7.17)

which is independent of current and device length. Thus, the small-signal

gain of the circuit in Figure 7 .4(b) will be

(7.18)

In a typical technology with L < 1iu», devices are not fully velocity-saturated
but they deviate substantially from square-law behavior. As a result, the actual
gain has a magnitude between J(WI2/-Ln)/(W34/-Lp) and (WI2/-Ln)/(W34/-Lp),
thereby making it difficult to predict its exact value.
Another point of contrast between bipolar and CMOS amplifiers is ev-
ident in follower circuits. While emitter followers are frequently used in
analog (and digital) design, source followers have not been as popular for
several reasons. First, unless wide devices or high-bias currents are used, the
output impedance of a source follower is roughly the same as that of circuits
such as in Figure 7.4, indicating source followers are not efficient drivers.
Second, the gate-source level shift (typically greater than 1 V) often limits the
voltage swings and hence the dynamic range. Third, if the body of a source
follower is tied to a constant potential, the body effect introduces substantial
nonlinearity and gain error.
For these reasons, precision amplification in CMOS technology is often
performed using closed-loop configurations.
7.1.2 Closed-Loop Amplifiers
Closed-loop amplifiers are frequently used in precision processing of
analog signals because negative feedback can yield accurate closed-loop gain
and high linearity. Additionally, negative feedback can provide virtual ground
nodes, a necessity when precise amounts of charge must be transferred from
one capacitor to another. For these reasons, operations such as sampling and
subtraction usually employ closed-loop circuits for precisions above roughly
10 bits.
Sec. 7.1 Amplifiers 161

The precision resulting from negative feedback of course depends on the

gain and linearity of the open-loop circuit. In particular, an important chal-
lenge in the design of closed-loop circuits is achieving a high open-loop gain
while maintaining reasonable speed, voltage swings, and power dissipation.
While traditionally phase margin and unity-gain bandwidth are used to
predict the speed of closed-loop circuits, it is extremely important to realize
that these parameters are small-signal quantities unable to represent the large-
signal behavior of such circuits. Thus, to obtain a more realistic view, the
large-signal time response of the circuit (in a closed loop), including both
slew rate and settling time, must be examined.
Unity-Gain Buffer with Local Feedback. Figure 7.5 shows a BiC-
MOS unity-gain buffer, consisting of a differential pair QI-Q2 with active
load M 1- M2 and an emitter follower Q3 in a local feedback loop. The small-
signal open-loop gain of this circuit is
(7.19)
where gm 12 is the transconductance of Q I and Q2 and r 0 Q2 and r 0 M2 represent
the output impedance of Q2 and M2, respectively. The open-loop input and
output impedance of the amplifier are
(7.20)

ROUl,o ~ rOQ211
roM2
+ _1_. (7.21)
{J +1 gm3
In the closed-loop circuit, the gain is A vc = Avo/(l + Avo), and the equivalent
input and output impedance are Rin,c ~ Rin,o · Avo and Rout,c ~ Rout,o/ Avo·
Thus,
1
Ave ~ 1- (7.22)
gmI2(rOQ2I1roM2)
Rin,c ~ 2{J(rOQ21IrOM2) (7.23)
1
Rout,c ~ -/:I- . (7.24)
pgm12

It follows from the above equations that the buffer achieves a high input
impedance, a low output impedance, and again error of [gm 12(rOQ21IrOM2)]-1
(typically a few tenths of a percent). The maximum input and output voltage
swings are given by the difference between the supply voltage and the sum
of VOS ,2 , VBE .3 , VBE,2 , and the voltage required across current source lEE (as-
suming VOS ,2 + VBE.3 ~ Vos, I). These swings are approximately equal to 2.5
V in a 5- V system.
162 Building Blocks of Data Conversion Systems Chap. 7

...-----...----.---4 Vee

1 - - - -_ _- - 0 V
out

-. -.
(a)

\-.-

t
(b)
Fig.7.5 (a) BiCMOS unity-gain buffer; (b) emitter current of Q3 when the
circuit drives a large load capacitance.

Despite these features, the buffer of Figure 7.5 suffers from a number
of speed-related drawbacks. In addition to a dominant pole at the collector of
Q2, the circuit has nondominant poles at the collector of QJ and emitter of
Q3. The latter is given by the output impedance and the total capacitance seen
at that node and may substantially degrade the settling behavior if the buffer
drives a large load capacitance. Another important effect, often ignored in
small-signal analysis, is the variation ofthis pole during large-signal transients
at the output [7]. Since IF is constant, during transients the emitter current
of Q3 must change to allow the load capacitance to charge or discharge.
For example, during a positive voltage excursion at the output, Q3 carries not
only IF but also the load capacitance current. Figure 7.5(b) depicts the emitter
current of Q3 for both positive and negative voltage excursions, indicating that
the pole magnitude first changes significantly and then requires a long time
to settle to its original value.
Sec. 7.1 Amplifiers 163

In order to overcome this problem, IF can be controlled such that Q3

always carries a relatively constant current; i.e., when the load capacitance
current increases, I F decreases, and vice versa [7]. Shown in Figure 7.6
is a possible implementation of this concept, where amplifier A adjusts I F
according to the difference between the input and output voltages, making I F
an "active pull-down" device. This circuit can also be viewed as two parallel
amplifiers that drive the load in a push-pull fashion. Of course A must be
sufficiently fast so as not to introduce additional settling components at the
output.

. - - - - - -.....------------- Vee

...... - - - -.....- - - 0 Vout

-.
Fig. 7.6 Additional feedback applied to the circuit of Figure 7.5 to maintain
I £3 constant.

The pole formed at the collector of Q2 often does not provide sufficient
roll-off in the gain, causing significant ringing in the step response, especially
for a large load capacitance. To alleviate the problem, this pole can be brought
closer to the origin by adding more capacitance from the collector of Q2 to
ground [Figure 7.7(a)]. Alternatively, pole-splitting techniques [3] such as
that in Figure 7.7(b) can be used to both move this pole further from the
origin and create another dominant pole at the base of Q2.
The topology of Figure 7.5 must be modified if complementary devices
or bipolar transistors are not available. Figure 7.8 shows two variants in
all-npn bipolar and pure CMOS technologies. Since the open-loop gain of
these circuits is about an order of magnitude less than that of Figure 7.5, their
gain error is quite significant. The nonlinearity of the bipolar buffer is also
substantial because its loop gain is relatively small.
164 Building Blocks of Data Conversion Systems Chap. 7

- - - - - . . - - - - - - - - - - - Vee
Dominant
Pole

100------........0 Vout

-. (a)

- - - - -......- - - - - - . -... Vee

Dominant
Pole

-.
(b)
Fig.7.7 Compensation of unity-gain buffer by (a) lowering the magnitude
of the dominant pole and (b) pole splitting.

7.1.3 Operational Amplifiers

The large gain and high linearity that can be achieved in operational
amplifiers often prove crucial in signal processing. For example, many of
the SHA and ADC architectures described in Chapters 3 and 6 require such
amplifiers so as to attain high resolutions.
While op amps traditionally were designed to have a gain of several
hundred thousand and provide a relatively low output impedance (even in
open-loop configuration), they have evolved into different topologies as sup-
ply voltages have scaled down and CMOS devices have become popular in
analog design. Various trade-offs among gain, speed, dynamic range, and
Sec. 7.1 Amplifiers 165

Vee
Re

Q3

Vin Vout

-. (a)
-.
r-----_4--_e_-.. VDO

.....-.--00 Vout

-. (b)
-.
Fig.7.8 Unity-gain buffers in (a) all-npn bipolar and (b) CMOS technolo-
gies.

power dissipation of op amps prohibit an arbitrary choice of any of these

parameters, thereby mandating custom design for every system.
Since dynamic range is a crucial parameter in high-resolution systems-
and is limited by the supply voltage-it cannot be simply compromised for
other parameters. In particular, op amps are usually designed to achieve
maximum input and output voltage swings and low input noise so as to allow
a wide dynamic range. In this respect, low-voltage designs usually avoid
emitter followers or source followers at the output because of the additional
headroom consumed by these circuits. However, such designs cannot drive
low-resistance loads because their open-loop gain falls sharply.
166 Building Blocks of Data Conversion Systems Chap. 7

Another attribute of modem op amps is that their open-loop gain is

commensurate with the maximum allowable gain error of the closed-loop
circuit. Resulting from the trade-offs mentioned above, this choice of gain
assumes that the nonlinearity is also suppressed to sufficiently low levels,
e.g., roughly the same as the gain error. This assumption is reasonable in
most topologies and simplifies the design if the gain error and nonlinearity
are equally important (e.g., in interstage SHAs of pipelined ADCs).
Two-Stage Op Amps. The two-stage topology has been successfully
used in many general-purpose, high-gain op amps [8]. Shown in Fig-
ure 7.9, this configuration consists of a transconductance stage Gml, a volt-
age amplifier A l, and a Miller compensation capacitor Cc placed around the
amplifier. The small-signal open-loop gain of the circuit is

(7.25)

where R, is the resistance seen at the output of Gml and equals the parallel
combination of the output resistance of Gmt and the input resistance of AI.
Since the overall gain is equal to the product of the voltage gain of each stage,
it can be very high. The -3-dB open-loop bandwidth of the circuit is
1
BWo~ . (7.26)
21l" RIA,Cc
It follows from (7.25) and (7.26) that the gain-bandwidth product of the op
amp is
Gml
Avo · BWo ~ -2--· (7.27)
rrCc

Cc

Fig.7.9 Two-stage op amp configuration.

The principal drawback of this architecture stems from the nondominant

pole formed by the output impedance of A I and the load capacitance. This
pole severely degrades the settling behavior because, as mentioned above,
amplifier A I usually employs no source or emitter followers at its output and
hence exhibits a relatively high output impedance. Since G m 1 and A 1 typically
have additional poles, the op amp bandwidth must be drastically reduced so
Sec. 7.1 Amplifiers 167

as to avoid underdamped settling at the output. Furthermore, the feedforward

of signal through Cc gives a zero in the right half-plane, often requiring other
circuit techniques to ensure stability [9, 10].
The two-step nature of this configuration offers an important feature
that can be exploited if maximum dynamic range is the primary concern: the
G m stage can provide a high gain, while amplifier AI is designed for nearly
rail-to-rail output swings [11]. This allocation of gain and voltage swing is
not possible in op amp topologies that provide the entire gain in one stage.
Cascode Op Amps. Since most of the op amps employed in data ac-
quisition systems need not drive resistive loads, they can be designed without
concern for their open-loop output resistance. As such, these op amps can
have a very high output resistance, i.e., designed as transconductance ampli-
fiers. The advantage of this approach is that a relatively high voltage gain can
be obtained in one stage.
Figure 7.10(a) depicts a CMOS cascode op amp with single-ended out-
put [3]. The small-signal open-loop voltage gain of the circuit is equal to
gm12RO, where Ro is the impedance seen at the drain of M4; i.e., Ro ~
(gm4r04ro2)II(gm6r06ros). This gain is typically around a few thousand,
and the circuit offers the linearity and gain error required for resolutions up
to 10 bits [12]. The dominant pole is formed at the output node by the load
capacitance.

VDD

Vb 3

Vb2

Vout

Vb Vb1

(a) (b)

Fig.7.10 (a) Single-ended cascode op amp; (b) fully differential cascode op

amp (common-mode feedback not shown).
168 Building Blocks of Data Conversion Systems Chap. 7

This topology suffers from a number of trade-offs among its gain, dy-
namic range, slew rate, and settling time. Since the circuit employs a stack of
five devices (including the current source), its output voltage swing is quite
limited. Thus, to achieve both a large output swing and a high gain, the devices
must be wide so that their VGS - VTH is minimized and their transconductance
maximized. On the other hand, to attain a high slew rate, the bias currents must
be made large, lowering the open-loop gain unless the transistors are made
longer. The resulting size of the devices yields large input capacitance and
large parasitics at nodes X I-X3 and YI-Y3, thereby reducing the magnitude of
the poles formed at these nodes and degrading the settling characteristics. In
particular, the pole associated with the mirror device M7 typically becomes
the primary nondominant pole, degrading the phase margin and limiting the
unity-gain bandwidth. This pole moves toward the origin as the design max-
imizes the output voltage swing by increasing the width of the transistors. It
can be easily shown that, for a given Vas ,7 , the magnitude of the pole at node
X3 decreases as the drain current and width of M7 increase together.
To alleviate some of these problems, a fully differential topology such
as that of Figure 7.10(b) can be used. In this circuit, as is often said, sig-
nals do not propagate through PMOS devices. This is a relatively accurate
statement because the only signals that appear at nodes X3 and Y3 result from
reverse characteristics of common-gate devices M 5- M 6, i.e., their finite output
impedance. While the parasitic capacitance at these nodes shunts the output
impedance of M7 and Ms (thus producing a pole), the impedance seen looking
into the drain of Ms and M6 has only one pole (even in the presence of load
capacitance). We calculate the impedance looking into the drain of M5 by
noting that
1
Z05 ~ gmS r o 5(r o 711 - ), (7.28)
C7S
where C7 is the total capacitance at the drain of M7. This expression can be
written as gm5 r05
Z05 ~ (gm5rOs r 07) II( c ), (7.29)
7S
suggesting that Z05 is equivalent to the parallel combination of a resistor
equal to gmSrOsr07 and a capacitor equal to C7/(gmSrOS).
Since the load capacitance C L simply appears in parallel with this com-
bination, we can write

(7.30)
Sec. 7.1 Amplifiers 169

It follows from (7.30) that the capacitance at nodes X3 and Y3 is divided by

the intrinsic gain of Ms and M6 and "absorbed" by the load capacitance. In
reality, the approximations made in arriving at (7.28) (e.g., the assumption
that s-sros » 1) ignore some higher-order terms in s that could introduce
pole-zero doublets. But, the effect of these terms is usually negligible.
With the mirror pole removed, the nondominant pole of the circuit in
Figure 7.1O(b) arises at nodes X I and YI and is determined by the transcon-
ductance of M3 and M4 and the total capacitance at these nodes. In a typical
design, this pole is several times higher than the mirror pole of Figure 7.1O(a).
The fully differential topology of Figure 7.10(b) requires a common-
mode feedback network so as to remain in its high-gain region. This subject
is discussed in Section 7.1.5.
The circuit of Figure 7.1 O(b) still suffers from the same dynamic range
trade-offs described for the circuit of Figure 7.1O(a). In order to increase the
input and output swings, the cascode topology can be "folded," as illustrated
in Figure 7.11. Here, the input stage has three stacked devices and the output
stage four, giving larger input and output swings than the circuits of Figure
7.10. However, PMOS devices Ms and M6 are in the signal path, creating a
nondominant pole at the folding points X I and fl. Given by the transconduc-
tance of Ms and M6 and the total capacitance at these nodes, this pole usually
determines the phase margin and maximum bandwidth of the op amp. If M I
and M2 are replaced with a PMOS differential pair with their drains connected
to the source of M7 and Mg, then the pole associated with the folding points
is given by the transconductance of NMOS devices M7 and Ms and the total
capacitance at their source, a potentially higher magnitude than that in Figure
7.11. However, the open-loop gain tends to be lower because of input PMOS
transistors.
The circuits of Figures 7.10 and 7.11 exhibit an interesting trade-off
between their input-referred noise and output voltage swings. In Figure 7.10,
for example, since the contribution of M7 and Ms to the input-referred rms
noise increases with the square root of their transconductance [3] and since
gm ~ 2JD/(Vas - VTH ) , the noise increases if VGS - VTH of these transistors
is minimized to allow a large output swing. Note that the folded cascode
exhibits more noise than the unfolded counterpart because of the contribution
of four devices, M3, M4, M9, and Mlo in Figure 7.11.
The op amp topologies described above can also be implemented in
BiCMOS or complementary bipolar technologies. In particular, the folded-
cascode configuration has a BiCMOS counterpart, shown in Figure 7.12 [7].
In this circuit, the pole at nodes X I and YI is on the order ofthe fr ofthe bipolar
170 Building Blocks of Data Conversion Systems Chap. 7

V
b1
__-Ho----......

.1-----......-. Vb 4

.1-------+1....... Vb 2

Fig.7.11 CMOS differential folded-cascode op amp (common-mode feed-

back not shown).

_--------_..----__e-... VDD
Vb 4 ---.....- - - -..•

Vb 3 ---.....- - - -..•

o
Vin
o - - - - + - - - - - - - t -......

Vb 1----+-- - - - ....

Fig.7.12 BiCMOS folded-cascode differential op amp (common-mode

feedback not shown).

transistors Q I and Q2, yielding a faster settling time than a pure CMOS
implementation.
While bipolar transistors can provide a higher gain and lower noise than
CMOS devices, most BiCMOS op amps still avoid them in the input stage.
Sec. 7.1 Amplifiers 171

The reasons why are as follows. First, the input bias current introduces droop
and offset voltage in switched-capacitor circuits and is difficult to cancel.
Second, if the folded-cascode topology incorporates an npn input pair, it
will inevitably have PMOS devices in the signal path, thus suffering from a
significant nondominant pole and hence long settling times.
7.1.4 Gain Boosting Techniques
The bandwidth limitations of two-stage op amps and the limited gain
achievable in folded-cascode configurations have motivated the invention of
gain-boosting techniques [13, 14]. These techniques are usually applied to
cascade op amps to increase their gain with little degradation in speed.
To understand the principle of gain boosting, consider the cascode circuit
of Figure 7.13(a). Here, if II is an ideal current source, the small-signal gain is
approximately equal to gmlgm2rolr02, i.e., the transconductance of the input
transistor multiplied by the impedance seen at the output node. The output
impedance and hence the gain can be increased by stacking more devices in the
cascade configuration, but at the cost of reduced output swings. Now suppose,
as shown in Figure 7.13(b), M2 is placed in a feedback loop that senses its
drain current and adjusts its gate voltage so as to minimize variations in the
drain current. In other words, if a change in Vout tends to vary Vx through
the output impedance of M2, then Ao varies the gate voltage of M2 in such a
way to minimize the change in Vx. Since the feedback loop senses the output
current, the output impedance of the circuit is boosted by approximately Ao,
yielding Av,boost = AOgmlgm2rOJro2.
It is interesting to note that while in a two-stage op amp the "entire"
signal must propagate through both stages, in the circuit of Figure 7.13(b)
only an error signal is processed by Ao. This in tum means the settling times
are much faster in the latter than in the former. Also, Ao need not have large
output swings or a high slew rate and hence can be optimized for small-signal
gain and bandwidth, providing a high overall gain and fast settling.
The amplifier topology used for Ao depends on the overall gain require-
ment and can be as simple as a common-source stage, as shown in Figure
7.13(c) [14]. In a typical design, the common-source stage, consisting of M3
and 12, boosts the gain by roughly 20 to 50, in essence yielding an overall gain
equal to that of a triple cascode. However, it also limits the output voltage
swing because the drain voltage of MI is equal to Vas,3 (c- VTH ) , whereas
in Figure 7.13(a), it can be as low as VOS , l - VTH , an arbitrarily small value.
Furthermore, Miller multiplication of COD ,3 decreases the magnitude of the
pole at the source of M2, degrading the closed-loop settling behavior of the
op amp.
172 Building Blocks of Data Conversion Systems Chap. 7

Vout

-
.
(a) (b)
-.

Vout

(c)
Fig.7.13 (a) Simple cascode circuit; (b) cascode circuit with gain boosting;
(c) simple implementation of (b).

These drawbacks can be alleviated by employing a folded-cascode cir-

cuit for Ao [13]. Shown in Figure 7.14 is such an arrangement, where a
folded-cascode amplifier with PMOS input boosts the gain of an NMOS cas-
code stage. Note that, with proper design, the drain voltage of M) can be as
low as Vas,) - VTH and the Miller effect at the input of the folded-cascode
amplifier is negligible. The overall gain is boosted by more than two orders
of magnitude [13].
An important issue in the design of gain-boosted op amps is the effect
of the poles of the auxiliary amplifier (Ao in Figure 7.13) upon the settling
behavior of the overall circuit. Bult [13] provides design constraints that
ensure fast settling in typical CMOS technologies.
7.1.5 Common-Mode Feedback
In high-gain, fully differential op amps, the output common-mode level
must be well-defined even if the circuit is used in closed-loop form. For
Sec. 7.1 Amplifiers 173

.----.....-------+-t----....-__. VOO

----oVout

-. -.
Gain-Boosting Amplifier
-.
Core Amplifier

Fig. 7.14 Gain boosting using a folded-cascode amplifier.

example, consider the switched-capacitor circuit in Figure 7.15(a), where

during reset Sl and S2 are on, providing unity-gain differential feedback.
Now suppose the op amp is implemented as a simple differential amplifier, as
shown in Figure 7.15(b). In this circuit, when Sl and ~ are on, Vx and Vy
are not well-defined because 155 must balance I D3 + I D4. Thus, for example,
if Iss is slightly less than ID3 + 104, the output nodes approach V D D , driving
M3 and M4 into linear region, while the feedback simply senses the difference
between Vx and Vy and is therefore unable to correct the eM level. For
this reason, differential op amps usually employ a common-mode feedback
network (C:¥FN) to achieve a stable eM level. We discuss a number of
approaches to realizing these networks.
The principal issue in the design of CMFNs is that they must have a high
differential mode rejection; i.e., they must maintain a constant common-mode
level even for large differential voltage swings. While it might seem that small
variations in the CM level would not lead to any serious problems, in practice
common-mode variations may introduce long settling times in the differential
output. We discuss this point later.
A simple CMFN is shown in the differential amplifier of Figure 7. 16(a),
where transistors Ms-Ms provide common-mode feedback. In this circuit, Ms
and M6 sense the output voltages and produce a eM voltage at their source.
This voltage is applied to M7, setting lD8 such that the output eM voltage is
equal to Voss + Vas? (when the differential output is zero).
174 Building Blocks of Data Conversion Systems Chap. 7

51

C3
C1
o--J
Vin Vout
o--J
C2
C4

52 -.
(a) (b)

Fig. 7.1S (a) Fully-differential switched-capacitor circuit; (b) simple imple-

mentation of op amp in (a).

For small differential swings at Vx and Vy, ID5 + ID6 is relatively

constant and the eM level is fixed. Now suppose the op amp is to produce a
large Vx - Vy (and hence M, and M2 must carry slightly different currents).
Since M5 and M6 have nonlinear I D- VGS characteristics, as M6 begins to turn
off, V p rises, increasing I D8 momentarily. The change in I D8 is drawn from
M I and M2, but not equally, because these transistors have slightly different
transconductances. As a result, a differential settling component appears at the
output solely because the common-mode level has changed. This component
can degrade the overall settling behavior if the response of the CMFN is not
sufficiently fast.
From the above discussion, we conclude that a CMFN must maintain
symmetry even for large differential swings. An example of such a circuit is
depicted in Figure 7.16(b), where equal resistors R) and R2 sense Vx and Vy
and reconstruct the eM level at node P [15]. The resulting voltage adjusts
the drain currents of M3 and M4. In this circuit, since R, and R2 exhibit much
more symmetry (i.e., linearity) than Ms and M6 in Figure 7.16(a), the eM
level remains constant even in the presence of large differential outputs. To
eliminate the loading of RI and R2 on the output nodes, these resistors can be
preceded by source followers.
AnotherCMFN used in MOS op amps is shown in Figure 7.16(c) [16],
where M5 and M6 are biased in the linear region and set the output CM level.
Here, the output eM voltage determines the channel resistance of M5 and M6
and hence the drain current of M) and M2. The total channel resistance is
Sec. 7.1 Amplifiers 175

.----- ----4~. . Voo

•..-- - - - -.... Vb1

I-

-. ~

(a)

VDD VDD
Vb1 Vb1
M3 M4

X Y
R1 R2 -I
4 M2 J-

(b) (c)
Fig. 7.16 Common-mode feedback using (a) source-coupled pair (b) equal
resistors and (c) MOSFETs in the linear region.

(7.31)

(7.32)

- ---------- (7.33)
176 Building Blocks of Data Conversion Systems Chap. 7

In switched-capacitor circuits, the CMFN can employ capacitors to sense

and correct the output common-mode level [17]. Consider the circuit shown
in Figure 7.17(a), where equal capacitors C I and C2 have an initial voltage of
Vo and reproduce a CM level at node P, thus setting the drain current of M7
such that the output CM level is equal to Vo + Vas7 . If the leakage at node
P is negligible, the voltage across C I and C2 remains constant, providing
symmetric feedback even for large differential outputs. In practice, Vo must
be periodically refreshed by means of a separate circuit, e.g., that of Figure
7.17(b). Here, during refresh, CI and C2 are disconnected from the op amp,
charged to a proper voltage, and reconnected to the circuit. In the refresh
mode, the op amp output is not valid, but in many data acquisition systems
op amps often have some idle time that can be used for this purpose.

.----------4t--- VDD

. . . - --------1...... Vb

---I

-. (a)
-.
+ Vo - - Vo+
VCM ~ ~----... "'I---<O"r--o--e VCM
C1 C2

(b)
Fig.7.17 (a) Common-mode feedback using capacitors; (b) refresh circuit.
Sec. 7.2 Comparators 177

Note that in Figure 7.17(a) M7 provides only a fraction ofthe bias current,
with the remaining set by I 55. In other words, the CMFN need not control the
entire bias current of an op amp. This concept can be applied to all CMFNs
and proves useful in optimizing the transient response of the circuit.

7.2 COMPARATORS
The performance of AID converters that employ parallelism to achieve a high
speed strongly depends on that of their constituent comparators. In particu-
lar, flash and two-step architectures require great attention to the constraints
imposed on the overall system by the large number of comparators. Most
such converters utilize voltage comparison, rather than current comparison,
because distributing a voltage to a large number of comparators is easier.
Comparison is in effect a binary phenomenon that produces a logic out-
put of ONE or ZERO depending on the polarity of a given input. Figure 7.18(a)
depicts the input/output characteristic of an ideal comparator, indicating an
abrupt transition (hence infinite gain) at Vin,I - \tin,2 = O. This nonlinear char-
acteristic can be approximated with that of a high-gain amplifier, as shown in
Figure 7.18(b). Here, the slope of the characteristic around Vin, I = Vin,2 is
equal to the small-signal gain of the amplifier in its active region (A v), and
the output reaches a saturation level if I \tin. I - Vin,21 is sufficiently large. Thus,
the circuit generates well-defined logic outputs if I\lin, I - ~n,21 > VH / A V ,
suggesting that the comparison result is reliable only for input differences
greater than V H / A v. In other words, the minimum input that can be resolved
is approximately equal to VH / A v , (The effect of noise is ignored for the
moment.) As a consequence, higher resolutions can be obtained only by
increasing A v because VH, the logical output, cannot be arbitrarily reduced.
Since amplifiers usually exhibit strong trade-offs among their speed, gain, and
power dissipation, a comparator using a high-gain amplifier will also suffer
from the same trade-offs.
Since the amplifiers used in comparators need not be either linear or
closed-loop, they can incorporate positive feedback to attain virtually infinite
gain. However, to avoid unwanted latch-up, the positive-feedback amplifier
must be enabled only at the proper time; i.e., the overall gain of the comparator
must change from a "relatively small value to a very large value upon assertion
of a command.
Figure 7.19 illustrates a typical comparator architecture often utilized in
AID converters. It consists of a preamplifier A 1 and a latch and has two modes
of operation: tracking and latching. In the tracking mode, A I is enabled to
amplify the input difference, hence its output "tracks" the input, while the
178 Building Blocks of Data Conversion Systems Chap. 7

V1n ,1
Vout
V1n ,2
Vout Vout

VHl
(a)
.,
Vin ,1 - Vin ,2
± (b)
..
Vin ,1 - Vin ,2

Fig.7.18 Input/output characteristic of (a) an ideal comparator and (b) a

high-gain amplifier.

latch is disabled. In the latching mode, A I is disabled and the latch is enabled
(strobed) so that the instantaneous output of A 1 is regeneratively amplified
and logic levels are produced at Vout • Note that it is assumed that the clock
edge is sufficiently fast so that the output of A I does not diminish during the
transition from tracking to latching. Also, if the input to the comparator is
constant with time, it is not necessary to disable A 1 in the latching mode.
These issues are further discussed below.

Latch Vout

CK--~--....

Fig.7.19 Typical comparator architecture.

Another advantage of the architecture of Figure 7.19 over a simple high-

gain amplifier is that the strobe signal (C K) can be used to define a sampling
instant at which the polarity of the input difference is stored. As discussed
in Chapter 6, this concept is extensively utilized in flash and folding NO
converters to eliminate the need for front-end sample-and-hold circuits.
The use of a latch to perform sampling and amplification of a voltage
difference entails an important issue related to the output response in the
presence of small inputs: metastability. To explain this issue, we first derive
the time response equations of a simple latch.
Figure 7.20(a) shows a latch comprising two identical single-pole in-
verting amplifiers each with a small-signal gain of -Ao (Ao > 0) and a
Sec. 7.2 Comparators 179

Vy

Ao ,to
(a)

vXYOt••••••
..
l ••
.•.... . .. ..
.. .
Vy •••• ............... ....• :... •.. .
V • ..
y •• ••
• ••1'
••
.
~
t t
(b) (c)
Fig.7.20 (a) A latch comprising two back-to-back amplifiers; (b) time re-
sponse of the latch; (c) time response for different values of VX Yo •

characteristic time constant of TO. For this circuit, we can write:

dVx
'0--
dt
+ Vx = -AoVy (7.34)

dVy
'0--
dt
+ Vy = -AoVx. (7.35)

Subtracting the second equation from the first and rearranging the terms, we
have
d(Vx - Vy)
to dt = -(1 - Ao)(Vx - Vy). (7.36)

If the circuit begins with (Vx - Vy) 1'=0 = VXYO, then

t
Vx - Vy = VXYO exp[(Ao - 1)-].
t'o
(7.37)

For a typical latch, Ao » 1, yielding the important property that the argument
of the exponential function is positive and hence Vx - Vy regenerates rapidly.
180 Building Blocks of Data Conversion Systems Chap. 7

The regeneration time constant is equal to t'o/(Ao - 1). Figure 7.20(b) shows
how the output evolves in time until either of the amplifiers saturates and its
gain goes to zero.
An important aspect of latch design is the time needed to produce logic
levels after the circuit has sampled a small difference. If Vx - Vy is to reach a
certain value VXYI before it is interpreted as a valid logic level, then the time
required for regeneration is

T1 = TO In VXYI • (7.38)
Ao - 1 VXYO

Equation (7.38) indicates that TI is a function of 1:o/(Ao - 1) (and hence the

unity-gain bandwidth ofeach amplifier) as well as the initial voltage difference
VXYo. Thus, the circuit has infinite gain if it is given infinite time. In other
words, if at the sampling instant Vx YO is very small, T, will be quite long. This
phenomenon is called "metastability" and requires great attention whenever a
latch samples a signal that has no timing relationship with the clock. Plotted
in Figure 7.20(c) are the Vx and Vy waveforms with VXYO as a parameter.
Since in most practical cases VXyo is (or can be considered) a random
variable, metastability must be quantified in terms of the probability of its
occurrence. Suppose in a system using a clock of period 2Tc , each latch
is allowed a regeneration time of Tc . Then, a metastable state occurs if a
latch does not produce an output of VXYI within Tc seconds. If the sampled
value VXYO has a uniform distribution between - VXYI and + VXYI, then the
probability of observing a metastable state is [19, 20]
-(Ao - l)Tc
P(TI > Tc ) = exp . (7.39)
1:0

This probability can be lowered by increasing Ao, decreasing 1:0, or pipelining

the comparator output.
Before describing various comparator topologies, we define some of
their performance metrics.
• Resolution is the minimum input difference that yields a correct digital
output. It is limited by the input-referred offset and noise of both the
preamplifier and the latch. We call this minimum input I LSB (also
denoted by VLSB ) .
• Comparison rate is the maximum clock frequency at which the com-
parator can recover from a full-scale overdrive and correctly respond
to a subsequent I-LSB input. This rate is limited by the recovery time
of the preamplifier as well as the regeneration time constant of the
latch.
Sec. 7.2 Comparators 181

• Dynamic range is the ratio of the maximum input swing to the mini-
mum resolvable input.
• Kickback noise is the power of the transient noise observed at the
comparator input due to switching of the amplifier and the latch.
In addition to these, input capacitance, input bias current, and power dis-
sipation are other important parameters that become critical if a large number
of comparators are connected in parallel.
7.2.1 Bipolar Comparators
Figure 7.21 depicts a bipolar implementation of the comparator archi-
tecture shown in Figure 7.19. The preamplifier consists of the differential
pair QI-Q2 and resistors R( and R2, while the latch comprises Q3-Q4 and
shares the same resistors. The differential pair and the latch are controlled
by C K and C K through Qs and Q6, respectively. When C K is high, Qs is
on and the differential pair tracks the input while Q6 is off and the latch is
disabled. When C K goes low, Qs turns off, disabling the input pair, and Q6
turns on, allowing the latch to establish a positive feedback loop and amplify
the difference between Vx and V y regeneratively.
r
p~~·~;;,piiti;;;········· . rL~ich···················

Vin ,2 o - i - - - - - o + - - - - - - ' "

-.
Fig. 7.21 Bipolar implementation of comparator architecture in Figure 7.19.

It is instructive to derive some of the performance metrics of this com-

parator so as to understand its limitations.
The resolution of the comparator depends on both its input offset voltage
and its input-referred noise. The input offset voltage arises from the mismatch
182 Building Blocks of Data Conversion Systems Chap. 7

between nominally identical devices Qt-Q2, RCI-Rc2, and Q3-Q4. Since

mismatch contributions of RCI-Rc2 and Q3-Q4 appear at the output, they are
divided by the voltage gain of the differential pair (gmt2RC, where Rc is the
mean value of Ret and RC2) when referred to the input. For two nominally
identical bipolar transistors, the VBE mismatch can be expressed as [3]
fils
ti. VBE = VT In(1 + - ) (7.40)
Is
ti.A
= VTlo(1 +-:4) (7.41)

!:1A
~VT- (7.42)
A'
where !:1 I s and Is are the standard deviation and mean value of the saturation
current, respectively, and 6.A and A are those of the emitter areas. Equation
(7.42) indicates that if, for example, two transistors have a 10% emitter area
mismatch, then their VBE mismatch is approximately equal to 2.6 mV at room
temperature. Another important observation is that the offset voltage varies
with temperature; i.e., if it is corrected at one temperature, it may manifest
itself at another. We should mention that (7.42) does not include base and
emitter resistance mismatch, errors that become increasingly noticeable as
devices scale down and are biased at relatively high current densities.
The overall input-referred offset can then be written as
A
ti. 12 ~Rc 1 ~A34
Vas = Vrln-- + Vr - -+ VTln - - . (7.43)
A12 Rc gml2 RC A34
The last term in this equation is negligible if gm12RC » 1.
The comparator input-referred noise consists primarily of the thermal
and shot noise of Ql and Q2 and the thermal noise of Rei and RC2 (neglecting
the latch noise). The spectral density of this noise is

v~ 1 8kT
- = 8kT(rb12 + re l2 + -2--) + 2 ' (7.44)
~f gm12 gml2Rc

where rsvi and r e 12 denote base and emitter resistance, respectively, and all
the noise components are assumed to be uncorrelated.
Equations (7.43) and (7.44) reveal a number of trade-offs in the design
of this comparator. First, to reduce the input offset and re l2, the emitter area
of Q1- Q2 must increase, thereby increasing the input capacitance. Second,
to reduce rnz. the emitter width must increase, again raising the input capaci-
tance. Third, to increase gml2, the bias current must increase, thus increasing
Sec. 7.2 Comparators 183

the power dissipation. Finally, if Rc is increased, the time constant at nodes

X and Y increases and so does the voltage drop across RCI and RC2, thus
limiting the input voltage swing. Note that the voltage drop across RCI and
RC2 should not exceed approximately 300 mV if Q3 and Q4 are to remain
out of heavy saturation in the latching mode.
To study the comparison rate of this circuit, we first describe the over-
drive recovery test, often used as the most stressful assessment of comparator
performance. In this test, the input difference toggles between full-scale value
VFS and 1 LSB in consecutive clock cycles, yielding the waveforms depicted
in Figure 7.22. For a large ~ ~n = \lin, I - ltin,2 (or "overdrive"), the input
pair of Figure 7.21 switches completely, steering all of the bias current to one
side and producing a large VXy. When ~ ~n goes from full-scale to 1 LSB,
VXy must "recover" from a large value and become approximately equal to
gml2RC X 1 LSB before the latch is strobed. We note from Figure 7.22 that
overdrive recovery has two extreme cases. In the first case, ~ \.'in goes from
- VFS to + 1 LSB and the output must recover and change polarity. In the
second case, 6. ~n goes from - VFS to -1 LSB and the output must recover
but not change polarity; i.e., it must be free from overshoot. In the first case, if
VXy has not changed its polarity before the latch is activated, the latched out-
put will regenerate to its previous value; Le., the comparator tends to follow
residues left from the previous cycle. This phenomenon is called "hysteresis"
and results from insufficient time allowed for overdrive recovery.

CK

Fig. 7.22 Comparator overdrive test.

From the above discussion, we conclude that, in order for a comparator

to respond correctly in an overdrive recovery test, the minimum clock period
must allow two phenomena to complete: overdrive recovery in the preampli-
184 Building Blocks of Data Conversion Systems Chap. 7

fier and generation of logic levels after the latch is strobed. In the circuit of
Figure 7.21, the preamplifier overdrive recovery can be expressed as

VXY,ov = gml2 RC VLSB

-I (7.45)
+(Vcc - IEERc - gmI2 Rc VLSB) exp - - ,
sec;
where COy is the average capacitance at nodes X and Y during overdrive
recovery (consisting of the collector-base and collector-substrate capacitance
of Q 1- Q4 and the base-emitter junction capacitance of Q3 and Q4). The
regeneration can be expressed as

(gm34RC - l)t
VXY,reg = VXYO exp
Creg
, (7.46)

where VXYO is the difference between Vx and Vy when regeneration begins

and Creg is the average capacitance at nodes X and Y during regeneration
(consisting of COy and the base-emitter diffusion capacitance of Q3 and Q4)
[19].
The dynamic range of the comparator is given by the ratio of the max-
imum input swing and VLSB and can be calculated by noting that the input
common-mode level Vin,CM is limited as follows:

(7.47)

where VSE E is the minimum voltage required across the current source lEE
and it is assumed that lEE Rc :::: 300 mV so that Q 1 and Q2 do not saturate
heavily when the input common-mode level reaches Vee.
Another important property of comparators is their kickback noise. Fig-
ure 7.23 illustrates how this noise is generated. Suppose the circuit is in the
latching mode; i.e., the input pair is off. In the transition to tracking, C K
goes high and turns Qs on, pulling current from Q I and Q2. However, since
Q 1 and Q2 are initially off, this current first flows through their base-emitter
junction, giving rise to a large current spike at Vin,1 and ~n,2. The magni-
tude of this current is approximately equal to half lEE before Q 1 and Q2
tum on and provide current gain. The duration of this spike depends on
the time constant at the input and may extend from one cycle to the next,
thereby corrupting the analog input. For example, if lEE = 200 ~A, in a
flash ADC with 256 comparators the kickback noise amplitude may reach
tens of milliamperes. This noise can take a long time to decay to below
1 LSB.
Sec. 7.2 Comparators 185

(a)

•
(b)
Fig. 7.23 Generation of kickback noise in a bipolar comparator.

The comparator of Figure 7.21 exhibits a nonlinear input capacitance as

a function of the input difference, as illustrated in Figure 7.24. If \.'in, I is more
negative than ~n,2 by several VT, QI is off and the input capacitance is equal
to Cjc , I + Cje, I (for input frequencies much less than IT of transistors, so that
the impedance seen at the emitter of Q2 is small). As Vin, I approaches Vin ,2,
QI turns on, introducing a base-emitter diffusion capacitance CD = g,nTF,
where iF is the base transit time. If "1n,1 exceeds Vin,2 by several VT, Q2
turns off and Q) operates as an emitter follower. In this region, the input
capacitance is approximately equal to Cjc, I plus a small fraction of Cje , I + CD
and increases with \lin, I because Cjc, I experiences less reverse bias. In a flash
AID converter, for a given input voltage most of the comparators operate
in either region 1 or 3, with only a few in region 2. As a result, the con-
verter's input capacitance arises primarily from Cjc and Cje of the transistors
(and interconnect capacitance). The variation of input capacitance with the in-
put voltage causes input-dependent delay and hence harmonic distortion
(Chapter 6).
186 Building Blocks of Data Conversion Systems Chap. 7

-.
(a) (b)

Fig.7.24 (a) Input stage of a bipolar comparator; (b) small-signal input

capacitance versus input differential voltage.

Another important parameter of the comparator of Figure 7.21 IS Its

input bias current. In the tracking mode, this current varies between zero
and lEE / fJ as the input difference changes, and in the latching mode it is
zero. As discussed in Chapter 6, in a flash converter, the input bias current
of comparators introduces a nonlinear variation in the reference ladder tap
voltages.
The limitations described above for the comparator of Figure 7.21 can
be significantly relaxed through the use of circuit techniques. In particular, the
input differential pair can be preceded with another stage to suppress kickback
noise and provide more gain, while the latch can employ emitter followers to
enhance the regeneration speed and allow larger voltage swings.
Shown in Figure 7.25 is a comparator circuit often utilized in flash ADCs
[18]. It consists of an input stage, a switched differential pair, and a latch
comprising Q9-Q12. The input stage serves the following purposes: (1)
it suppresses the kickback noise to acceptably low levels; (2) it provides a
relatively high gain, thereby lowering the offset contributed by the latch and

Fig.7.25 Improved bipolar comparator design.

Sec. 7.2 Comparators 187

improving metastability behavior; (3) it exhibits less input capacitance and

less feedthrough from one input to the other; (4) its input bias current is rela-
tively constant and can be canceled if necessary. These merits are attained at
the cost of larger power dissipation, complexity, and some reduction in small-
signal bandwidth. Note that the input offset voltage of the input stage is
higher than that of a simple differential pair because the VBE mismatch of Q)-
Q4 appears directly at the input. By the same token, the input noise is larger
as well.
The emitter followers Ql) and QI2 used in the latch section of Figure
7.25 improve the performance in several ways. First, they reduce the loading
effect of the parasitic capacitances of Q9 and Q 10 on nodes X and Y, thus en-
hancing both the small-signal bandwidth and the regeneration speed. Second,
they allow larger voltage swings at nodes X and Y because, unlike the circuit
of Figure 7.21, the regenerative pair does not enter saturation for swings as
large as VBE • Third, they provide a low output impedance for driving the
following stage.
In order to increase the input dynamic range, emitter followers Q J and
Q2 can be removed from the input stage, and the maximum voltage drop
across R) and R2 can be limited to a few hundred millivolts. In this way, the
input common-mode level can vary between Vee and VBE + VI EEl, yielding
a wider input range. The input offset and noise will be less as well. Such a
circuit, however, exhibits larger analog input feedthrough and variable input
bias current.
Several variants ofthe comparator circuit shown in Figure 7.25 have been
proposed [19, 21, 22]. Particularly interesting is the "high-level clocking"
approach used to reduce the kickback noise [19, 21]. In this circuit, illustrated
in simplified form in Figure 7.26, rather than turning off the input differential
pair, the clock simply steers the current from cascode devices QS-Q6 to the
latch Q3-Q4. Thus, when C K is high, the circuit is in the tracking mode,
and when C K goes low, the circuit enters the latching mode. Note that even
though the input pair is never disabled, the latch is not disturbed by the analog
input after C K goes low because the current steered to the latch is relatively
independent of the analog input voltage. This is important if the clock is to
define a sampling instant in an ADC with no front-end SHA.
In this circuit, the input pair does not switch and the kickback noise
results only from the transients at nodes A and B due to the switching of
Qs-Qs. Adding a resistor between A and B decreases the amplitude of these
transients and improves the recovery at these nodes. The resistor must be
roughly an order of magnitude greater than R 1 and R2 so that it does not
reduce the gain significantly.
188 Building Blocks of Data Conversion Systems Chap. 7

x y .......---__...l--_

CK --+-----1 ~--t__. . CK

Vin ,2 °--- - - - -+-O- - ---'

-.
Fig.7.26 Comparator with high-level clocking.

7.2.2 CMOS Comparators

While the techniques described above substantially improve the per-
formance of bipolar comparators, they do not necessarily yield a high perfor-
mance if directly applied to the design of CMOS comparators. This is because
CMOS devices generally exhibit much smaller transconductance and larger
offset than bipolar transistors, thus demanding different design style and cir-
cuit topologies.
In order to understand the issues related to CMOS comparator design,
let us examine a simple comparator circuit, such as that of Figure 7.27, and
compare its performance metrics with those of the bipolar comparators de-
scribed above. This circuit consists of a differential pair M )-M2 and a latch
pair Ms-M6, both sharing the cross-coupled load M3-M4. In the tracking
mode, C K is low, the input pair is enabled, and M9 is on, preventing M3
and M4 from latch-up. At the same time, Ms is off, disabling M« and M6.
To perform sampling and latching, C K goes high, disabling the input pair,
turning off M9, and enabling M« and M6. Subsequently, M3-M6 amplify VXY
to rail-to-raillevels.
Transistor M9 plays two important roles in the circuit. First, it controls
the gain in the tracking mode by providing a resistive path between nodesX
and Y. The reader can easily show that the gain of the circuit consisting of
Sec. 7.2 Comparators 189

Mg
X---- - -..... Y

Vin ,1 00----+------+-_
Vin,2o---J ......- - - - -......- - - - . . -.. CK

Fig.7.27 Simple CMOS comparator.

M 1-M4 and M9 is equal to

gml2Ron,g
A v= , (7.48)
2 - gm34Ron,9
where Ron,9 is the on-resistance of Mg. As a safe choice, gm34Ron,9 ~ I,
yielding Av ~ gmI2Ron,9.
The second role of M9 is to improve the recovery at nodes X and Y
when the circuit goes from latching to tracking mode. As M« turns on, it
experiences a large Vas because either X or Y is at the supply potential.
The resulting current pulls X and Y together and rapidly drives VXY to near
zero.
We now calculate the performance metrics of this comparator. The input
offset voltage arises from mismatches in nominally identical devices M)-M2,
M3-M4, and M5-M6. For a simple MOS differential pair, the input offset
voltage is
1 ~W ~L
Vos = i(VGS - VTH)(w - T) + 6. VTH , (7.49)

where ~ W / W and ~L/ L represent the relative mismatch in the width and
length of the devices, respectively [3]. This should be compared with (7.41),
where the offset has a logarithmic dependence on dimension mismatch and
no counterpart for tJ. VT H • More importantly, in (7.42) the relative dimension
190 Building Blocks of Data Conversion Systems Chap. 7

mismatches are multiplied by Vr (~26 mY at room temperature), whereas in

(7.49) they are multiplied by Vas - VTH (typically greater than 0.5 V).
In the circuit of Figure 7.27, the offset resulting from the mismatch
between M3 and M4 is multiplied by gm34/8m12 when referred to the input.
Similarly, the offset of Ms and M6 is multiplied by 8mS6/8m 12, where gmS6 is
the transconductance of Ms and M6 at the moment they turn on. Note that
when C K goes high and Mg turns on, Ms and M6 experience a Vas - VT H of
several volts and hence, from (7.49), exhibit a large offset voltage. Since the
preamplifier gain is usually less than 5, the offset contribution of the latch is
quite significant.
To calculate the input-referred thermal noise in the tracking mode, note
that the noise contribution of M3 and M4 at X and Y can be written as

V;34 = 4kT-4- 8m 34 Ron.9 . (7.50)

tJ.f 38m34 2 - 8m34 Ron,9
This noise and that due to Ron,9 are divided by A~ when referred to the input.
Thus, the total input thermal noise is

v2
_n = 4kT(-4 2 - 2g m
34R
on,
9
+ 2
4 4
+ --). (7.51)
t1f 3 gml2 R on,9 8 m 12 R on,9 3g m 12
The above observations reveal a number of trade-offs in the circuit of
Figure 7.27. To minimize the noise and offset contribution of M3-M6, the
transconductance of M I and M2 must increase-at the cost of higher input
capacitance or smaller common-mode range-or the transconductance of M3-
M6 must decrease, slowing down the regeneration at nodes X and Y.
The comparison rate of this circuit is determined by overdrive recovery
at X and Y and the regeneration speed of M3-M6, both of which are typically
slower than those of bipolar comparators. The recovery time constant at nodes
X and Y is roughly equal to
(7.52)
where Ctot represents the total parasitic capacitance seen at each of the nodes
X and Y. To decrease t'rec, R on,9 must decrease, which in turn reduces A v •
The regeneration time constant of the latch is
Clot
t'reg ~ . (7.53)
gm34 + 8m56
Note that if M3-M6 are made wider to increase 8m34 + gm56, then C tot also
increases. Thus, t'reg can be considered relatively constant for a given tech-
nology.
Sec. 7.2 Comparators 191

The input common-mode range of this circuit is given by VD D - Vas, 34 +

VTHN - VoS,12 - VI S5, where VI 55 is the minimum voltage required across
I SSe It is seen that M.-M4 must be sized and biased such that their gate-source
voltage does not limit the input range excessively.
The input capacitance of this comparator varies as a function of the input
difference in a manner similar to that shown in Figure 7.24(b) for bipolar
comparators. However, since a MOS differential pair typically requires more
than 1 V of differential input to completely steer the tail current to one side,
the comparator input capacitance is relatively constant for most of the input
range.
The kickback noise produced at the input of the comparator shown in
Figure 7.27 arises from two sources: (1) transients at X and Y when Vx and
Vy are regeneratively amplified to approach the rails, as well as when X and
Yare pulled together by M9; (2) transients at P when this node goes from low
to high, and vice versa. The first type of transients couple to the gate of M I
and M2 through COD,. and C oD,2 , and the second through Cas, I and C as ,2 .
The large offsets of MOS devices generally limit the resolution of cir-
cuits such as that in Figure 7.27 to approximately 6 bits. As a result, CMOS
ADCs with resolutions of 8 bits and above usually employ offset cancellation
techniques to reduce the minimum resolvable input voltage. This is in con-
trast with bipolar comparators, which are used with no offset cancellation for
resolutions as high as 10 bits.
The design of offset-canceled comparators is described in Chapter 8.
7.2.3 BiCMOS Comparators
The availability of both bipolar and CMOS devices in BiCMOS tech-
nologies makes it possible to design comparators with more relaxed speed-
power or speed-resolution trade-offs than pure bipolar or CMOS comparators.
The speed-power trade-off can be improved through the use of bipolar tran-
sistors in the signal path by turning them on only when required, thus saving
power [23]. The speed-resolution trade-off can be eased by applying offset
cancellation to bipolar transistors and hence achieve smaller offsets than that
attained in either bipolar or CMOS comparators [25].
In order to reduce the power dissipation, the design of comparators can
be based on the concept of "charge steering." Originally used in CMOS
memory sense amplifiers [24], this concept has evolved from current-steering
circuits by replacing resistors with capacitors and currents with charge. We
describe this evolution by first considering the bipolar comparator of Figure
7.21, repeated in Figure 7.28(a). In this circuit, the mode of operation is
controlled by steering the tail current lEE between the input pair Q 1- Q2 and
192 Building Blocks of Data Conversion Systems Chap. 7

the latch Q3-Q4. The tail current is constant, thus giving a continuous power
dissipation of lEE Vee, and the voltage at output nodes X and Y is established
by the flow of lEE through RI or R2.

------~Vcc

(a)

.....-.4.-----.-.._-... Vee

(b)
Fig.7.28 (a) Current-steering comparator; (b) charge-steering comparator.

Now consider the circuit shown in Figure 7.28(b), where CI and C2

function as load devices and the pairs QI-Q2 and Q3-Q4 are activated by
charge packets Sq, and tJ.Q2. This circuit has three modes of operation:
precharge, input sampling, and regeneration. A typical comparison proceeds
as follows. First, nodes X and Yare precharged to Vee. Next, a charge packet,
6.q), is drawn from Q I and Q2, biasing these transistors for a short period of
time and producing an amplified version of the input difference across C I and
C2. Subsequently, a charge packet, ~Q2, is pulled from Q3 and Q4, activating
the latch momentarily and amplifying VXY regeneratively.
Sec. 7.2 Comparators 193

The charge-steering comparator can be viewed as a "discrete-time" ver-

sion of the current-steering configuration; i.e., it operates with short pulses of
current rather than a continuous bias. As a consequence, it can dissipate less
power even at high frequencies.
The dynamic power dissipation of the circuit is given by the value of
tlql and tlq2 and the comparison rate. The minimum value of these charge
packets is determined by the required gain and output voltage swings, which
themselves depend on CI and C2. These capacitors must be large enough to
suppress the charge injection mismatch of Sl and S2.
In order to better understand the behavior of this comparator, we perform
a simple calculation to estimate the small-signal gain of the input differential
pair. Consider the circuit shown in Figure 7.29(a), where M I , M2, and C»
constitute a "charge pump," pulling charge from Q I and Q2 when C K goes
low. Let us assume that the input common-mode level remains close to Vee
and the on-resistance of M I, Ron, I, is relatively constant. Using the equivalent
circuit shown in Figure 7.29(b), we can write
Vee - VBE -t
lp(t)~ exp--- (7.54)
Ron, I Ron, I C P

where variations in VBE are neglected with respect to Vee. Since the bias cur-
rent of Q I and Q2 varies during the amplification mode, the transconductance
of these devices must be expressed as a function of time:
lp(t)
gm(t) = 2V (7.55)
r
Vee - VBE -t
- exp--- (7.56)
2R on, I VT Ron,. C p
where Vin,) - Vin,2 is assumed to be small so that lei ~ lei at all time. The
final differential output voltage is therefore equal to
gm(t)(~n,1 - v,» d t,
1
00
VXy = o C
(7.57)

where C = C. = C2. If Vin,1 - Vin,2 is constant, then it follows form (7.56)

and (7.57) that the small-signal gain is

VXYoo Vee - VBE Ce

-----= (7.58)
~n,1 - Vin,2 2VT C'
where VXYoo is the final value of VXy. For example, if Vee - VBE ~ 4 V,
Vr = 26 mY, and C» = 0.5 C, then the gain is roughly equal to 38.
194 Building Blocks of Data Conversion Systems Chap. 7

R on ,1

rep
-=
(a) (b)

Fig. 7.29 (a) Simplified charge-steering amplifier; (b) equivalent circuit

of (a).

While a power efficient configuration, the circuit of Figure 7.28(b) is

typically quite slower than that in Figure 7.28(a). Several reasons account
for this difference. First, the delays required between the clock edges that
turn off St and S2 and produce ~ql and 6.Q2 impose an upper bound on the
conversion rate. Second, CI and C2 slow down the regeneration at nodes X
and Y. Third, the clocks controlling SI, S2, and the charge packets typically
need rail-to-rail swings and hence suffer from longer transition times than
C K and C K in Figure 7.28(a), which usually require only a few hundred
millivolts of swing.
For the simple charge pump circuit shown in Figure 7.29, the amount of
charge drawn from the differential pair depends on the input common-mode
level, making the gain and output voltage swings have the same dependence.
If the variation in the common-mode level is comparable with Vee - VBE ,
then the charge pump circuit must be modified so that it operates as a constant
current source during pumping.
The precharge and sampling modes in a charge-steering comparator can
be converted to a single tracking mode if the input differential pair is replaced
with MOS switches, as depicted in Figure 7.30(a). Here, the input is sam-
pled on Cl and C2 and subsequently amplified by the latch. However, if
I Vin, 1 - Vin,21 exceeds roughly 0.7 V, the base-collector junction of Q I or Q2
is forward-biased, drawing current from the inputs. To avoid this problem, the
base of each transistor can be capacitively coupled to the collector of the other,
as depicted in Figure 7.30(b) [23]. In this circuit, first the input difference is
Chap. 7 References 195

sampled on C3 and C4, then the collectors of QI and Q2 are released from
Vee, and finally the latch is activated by a charge packet drawn from QI and
Q2. Note that the loop gain of the latch is attenuated by the voltage division
due to C4 and the input capacitance of QI (and C3 and the input capacitance
of Q2).

(a)

r----I..----- -..._-_4 Vee

(b)
Fig. 7.30 Charge-steeringcomparatorwithoutprechargecycle. (b)Modified
version of (a) allowing large Vin,I - Vin,2°

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