Ripes: A Visual Computer Architecture Simulator

Morten B. Petersen
morten_bp@live.dk
2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE) | 978-1-6654-0001-5/21/$31.00 ©2021 IEEE | DOI: 10.1109/WCAE53984.2021.9707149

Figure 1: The Ripes simulator, showing a five-stage pipeline processor model.

ABSTRACT 1 INTRODUCTION
Ripes is a visual computer architecture simulator built around the Ripes [1] is an open-source visual computer architecture simulator
RISC-V ISA. The main feature of Ripes is its tight integration of suitable for teaching the fundamentals of computer architecture.
a built-in assembler, compiler support, and cache simulator, all This is achieved through a focus on visualization-assisted simu-
centered around a visual microarchitecture simulator. Several mi- lation, wherein Ripes visualizes the processor datapath, register
croarchitectural models are provided to explore the evolutions of a and cache accessing, and instruction memory, which all update
typical processor pipeline, such as the different iterations of pro- during execution, to reflect the state of the computing system. In
cessors when going from a single-cycle model to a classic RISC visualizing the processor, we provide an interactive visualization
five-stage pipeline. This paper details the core features of Ripes, the which allows the user to investigate all signal values in the datapath
design decisions behind them, as well as thoughts on how Ripes during execution. As we shall see, Ripes is easily extendable with
may fit into a larger ecosystem by joining the growing movement either new processor models, ISA extensions, or completely new
around open hardware toolchains. Ripes is an actively maintained ISAs, but for the moment only contains processor models built for
open-source project and is at the time of writing used in teaching the RISC-V ISA [2]. The style of visualization as well as the set of
at various universities, as well as in nonacademic settings. available processors was heavily inspired by Computer Organization
and Design [3]. At the time of writing, Ripes has seen widespread
ACM Reference Format:
Morten B. Petersen. 2021. Ripes: A Visual Computer Architecture Simula- adoption in universities through use in undergraduate computer
tor. In Proceedings of WCAE ’21: IEEE Workshop on Computer Architecture architecture courses.
Education (WCAE ’21). ACM, New York, NY, USA, 8 pages. If considering only the base requirements for an instruction set
simulator—loading a program, stepping through program execu-
Permission to make digital or hard copies of all or part of this work for personal or tion, and showing register state—computer architecture educational
classroom use is granted without fee provided that copies are not made or distributed are abundant. However, learning about computer architecture is
for profit or commercial advantage and that copies bear this notice and the full citation
on the first page. Copyrights for components of this work owned by others than the oftentimes not simply a matter of understanding the base build-
author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or ing blocks of a processor, but also of how one may realize such a
republish, to post on servers or to redistribute to lists, requires prior specific permission
and/or a fee. Request permissions from permissions@acm.org.
system through digital design. In this, we would expect a student
WCAE ’21, June 17, 2021, Online to implement parts of a computing system in a hardware descrip-
© 2021 Copyright held by the owner/author(s). Publication rights licensed to ACM. tion language (HDL) to eventually run it on a field-programmable

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WCAE ’21, June 17, 2021, Online M.B. Petersen

gate array (FPGA). This is where a big discrepancy between simple text-based output, or through tabulated data. As such, the concept
instruction set simulators and actual course requirements starts of visual simulators in computer architecture education is certainly
to show. We want to not just have an architectural simulator, but not new. The style and extent of the visualization which previous
rather a microarchitectural simulator, showing the intricacies of simulators provide can usually be classified into two categories,
the datapath as well as the connectivity between the components each of which is linked to the implementation style of the simulator.
within it. Having this, the user does not have to suffice with a Some simulators only show either parts of the datapath or an
simulator that, for instance, just states that it implements, i.e., for- abstract visualization of the hardware, such as KScalar [8] or Edu-
warding, and therefore we observe an improvement of the cycles MIPS64 [9]. Such simulators typically only emulate a given archi-
per instruction (CPI) as compared to the base case. Instead, with a tecture, given that they implement some software model of the
visual microarchitectural simulator we can visualize the forwarding architecture. A benefit of such simulators is typically that they are
unit, how it controls multiplexers across the datapath, where these highly configurable, allowing for a large design space exploration
multiplexers get their operands from, and so forth. while achieving good performance. While not particularly built
As we shall see, datapath visualization is not a new concept. with visualization in mind, SimpleScalar [10] is a classic example of
Rather, the novelty and utility of Ripes lies is in its ability to merge this architecture. However, given that they do not implement the
many of the existing capabilities of educational simulators into a actual circuit structure, such simulators typically do not care about
modern package that rethinks the look-and-feel of the simulator. showing fine-grained circuit details, such as multiplexers or logic
Ripes focuses on having a simple and self-explanatory user interface gates.
(UI) for anyone familiar with the basics of computer architecture. Other simulators, such as MipsIt [11], WebMips [12], and WebRISC-
Which is of great value for teaching, as many other tools provide V [13], attempt to more closely mimic the digital circuit that results
only a command-line interface or a complicated UI that feels like it from their processor models, by basing the simulator on some form
is written for the author rather than the person who is intended to of HDL or a fine-grained software model, and progresses simula-
use it. tion state on a clock-level. However, their visualization is typically
The Ripes project started in 2016 as an instruction set simulator not inferred from the underlying hardware structure, but instead
for a course on computer architecture. The first major release, in coupled to some predefined image, thus not allowing for changes in
2018, provided a visualization of a five-stage pipeline alongside an circuit structure to be reflected. Contrary to this, processor models
integrated assembler. Later, an overhaul of the underlying simula- in Ripes are based on the description of actual hardware structures,
tion framework allowed for the inclusion of additional processor wherein the visualization is generated from the described hardware.
models. Since then, new features have been added such as an im- To the best of the authors’ knowledge, many universities tend
proved disassembler, compiler support, and cache simulation. While, to forego visual simulators and strictly rely on instruction set sim-
as we shall see, Ripes is fairly capable, it is not intended as a replace- ulators. This could be due to multiple reasons, such as that many
ment for simulators typically targeting research or functional use, visual simulators have been left unmaintained and no longer either
such as QEMU [4], Spike [5], or gem5 [6], due to the complexities fit a curriculum or simply do not run out-of-the-box on modern
and performance implications associated with a visual simulator. systems, that a curriculum tends more towards low-level software
This paper is organized as follows. Section 2 presents an overview development rather than considering the implementation details of
of educational computer architecture simulators, both visual and processors, or simply due to the preferences of the educator. In such
non visual. Section 3 presents the core features available within cases, instruction set simulators are typically employed, commonly
Ripes as well as the underlying design decisions. Section 4 presents providing built-in assemblers, as well as good support for a variety
VSRTL, a spin-off project from Ripes that serves as a framework of instruction set extensions and system calls. Popular GUI-based
for describing, simulating, and visualizing digital circuits. Section 5 instruction set simulators for educational use are MARS [14] and
surveys feedback provided by educators who use Ripes in teaching. SPIM [15] for MIPS, and RARS [16] and Venus [17] for RISC-V.
Finally, Section 6 reflects on the short and long-term goals for the
project.
The features presented in this work are based on Ripes version 3 FEATURES
2.2, scheduled for release Q2/Q3 of 2021. Ripes consists of three main tabs: the editor, processor and memory
tabs. Each of these tabs intends to be as distinct from each other in
what they show and configure, to simplify the UI and to shorten the
2 RELATED WORK learning curve of learning the features available in the simulator.
The use of simulators has long been a key component in computer In the processor tab (Figure 1), we display an animated datapath
architecture education, with simulators existing for teaching many of the current processor, alongside its registers. In the editor tab
parts of the field, such as the fundamentals of processor design or (Figure 2) we provide a side-by-side view of the input program
memory- and device subsystems [7]. When considering simulators and the corresponding executable counterpart. In the memory tab
specifically targeted at teaching about the fundamental aspects (Figure 3), we display a scrollable view of the entire address space of
of how a processor works, what distinguishes simulators can be the program, alongside a configurable and visual cache simulator.
summarized as their approach to informing a user about the state Processor models in Ripes intend to mimic the structure of real-
of the underlying architecture, while a program is executing. Ap- world hardware. As such, progressing the simulator state equates to
proaches are typically either by providing an accurate visualization clocking the processor once. A user may also autoclock, clocking the
of a simulated datapath, an abstract representation of the processor, processor with some fixed frequency, or run, clocking the processor

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Ripes: A Visual Computer Architecture Simulator WCAE ’21, June 17, 2021, Online

1 2

Figure 2: The editor tab. (1) A source editor for either assembly or C code. (2) objdump-style view of the disassembled version
of the compiled source code. (3) Any instruction which is present in a pipeline stage is highlighted, and the abbreviated stage
name is indicated. (4) Breakpoints may be placed in the disassembled executable.

without updating the visualized datapath, in an attempt to execute for the implemented designs. Currently, the following processor
the processor as fast as possible on the given host machine. models are available:
Ripes is written in C++ and based on the Qt library [18]. By doing (1) Single cycle,
so, we ensure cross-platform compatibility alongside a native and (2) Five-stage without forwarding, without hz(d/r)1 ,
modern ”look-and-feel”. The following sections will detail some (3) Five-stage without hz(d/r), with forwarding ,
of the distinguishing features of Ripes. We will go over how Ripes (4) Five-stage with hz(d/r), without forwarding ,
visualizes both the datapath as well as the currently executing code, (5) Five-stage with forwarding, with hz(d/r) ,
the set of available processor models, how to describe an input (6) Six-stage dual-issue (arith./control flow + arith./memory) .
program, as well as the integrated cache simulator.
While model (1) essentially implements an instruction set sim-
ulator, it crucially also introduces the base building blocks of the
3.1 Animated Datapath processor datapath that are present in all subsequent models. Mod-
In visualizing the processor datapath, we aim to not only show the els (2–4) are used to show that it is insufficient to just place registers
static structure of the design, but also various dynamic aspects. An in between the different parts of a single-cycle design, and expect a
example is an indication of which input of a multiplexer is currently correct and performant processor. Specifically, these processors re-
being selected on its output. While simple, this aids in figuring out quire user-scheduled code if they are to execute a program without
where in the pipeline a register value is being acquired from, as unintended side effects, resulting from the lack of ability to detect
shown in Figure 1. and resolve hazards in the datapath (models (2, 3)), or to avoid a
During execution, the user can observe which instruction is CPI penalty from not having implemented forwarding (model (4)).
present in each stage during a given cycle. When a nop is inserted Model (5) merges the features of models (3, 4) and includes both
due to a hazard in the pipeline, the reason for this insertion is an- forwarding and hazard detection/resolution. This design point rep-
notated (whether due to a flush or stall). To indicate where in the resents a classic five-stage RISC pipeline. After reaching a five-stage
program the processor currently resides, a small view of the instruc- in-order pipeline, courses typically diverge on what they teach next.
tion memory is provided as well. The stages that an instruction However, in general, they cover the design of architectures that ex-
resides in are also annotated, which serves to illustrate that the ploit instruction-level parallelism (ILP) beyond pipelining. Designs
same instruction may be in-flight at multiple points in the pipeline. further exploiting ILP are many, and it is the intention to intro-
Such a case is seen in Figure 1, bottom right, with the addi x10 duce new models to Ripes in the future that illustrate the variety
x10 1 instruction at address 0x8 being present in both the IF and of the design space. Currently, model (6) provides an example of
WB stages. a statically-scheduled superscalar processor. Through this model,
we can show how processors may achieve a CPI < 1, and provide
a stepping stone towards more advanced architectures, such as
3.2 Processor Models dynamically-scheduled superscalars.
A key feature of Ripes is the availability of multiple processor mod- Each processor defines at minimum two different layouts which
els with distinct features. The processor models of Ripes have been it may be instantiated with. The goal of this is allow the user to tailor
influenced by the typical sequence of design iterations which one is the visual complexity of the datapath to a suitable level. This is only
exposed to in an undergraduate course that teaches a RISC pipeline.
Specifically, the sequence taught in [3] was the main inspiration 1 Hazard detection and resolution.

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WCAE ’21, June 17, 2021, Online M.B. Petersen

Figure 3: The memory tab. (1): Scrollable memory viewer. (2): Cache configuration and statistics. (3): Cache visualization based
on the current cache configuration. The highlighted yellow rows- and columns shows cache indexing. Blue highlighting indi-
cates dirty cache block. Red highlighting indicates a cache miss (current access). (4): Plot showing hitrate over time generated
from the cache access trace.

a visual difference—the underlying hardware remains the same. 3.5 Disassembled Code Viewer
Figure 1 shows the five-stage model using the ”extended” layout. In Ripes, we present the user-provided source code next to a dis-
Instantiated using its ”simple” layout, the forwarding, hazard, and assembled version of the executable code that the input program
control units will be hidden. Such selective visualization may also assembled or compiled to (Figure 2.2). The executable code is pre-
be seen in books, to improve readability. sented in similar style to an objdump, which helps in navigating
between the input program and its executable counterpart. This
3.3 Reversible Simulation presentation is inspired by Compiler Explorer [21], a popular tool
for exploring the compilation of high-level languages to a variety
Learning about pipelining oftentimes involves analysis of why
of target ISAs. Applying this form of side-by-side presentation of
and how hazards were detected and resolved, as well as in which
the source and output program for assembly code, the user gains
situations forwarding kicks in. Triggering these situations will be
insight into assembler and linker tasks such as pseudo-instruction
done by the user writing some code that triggers the given situation.
translation, symbol resolution, and relocation.
When progressing to the point of interest in a program, after having
During execution, the instructions that are present in each stage
analyzed the state of the datapath in the given cycle, we oftentimes
of the processor are highlighted within the output (disassembled)
would like to go back in time to analyze the sequence of events that
program (Figure 2.3). This representation provides a program-focused
led up to the situation of interest. To avoid resimulating the entire
(as compared to datapath-focused) visualization of how different
program, Ripes can undo clock cycles, allowing the user to easily
parts of the program may reside in different parts of the processor
investigate the state of the datapath in the cycles preceding and
simultaneously, decorating the output program with a visualization
following the event of interest.
of how ILP is being exploited by the selected processor.
Finally, breakpoints may be placed anywhere in the executable
3.4 Integrated Assembler code segment (Figure 2.4). A breakpoint is triggered when an in-
To avoid the need for a third-party program to write and assemble struction enters the first stage of the processor model.
programs, Ripes includes a built-in assembler. The implementation
of the assembler infrastructure in Ripes has been inspired by the 3.6 Cache Simulation
use of TableGen [19] in LLVM [20]. Here, only instruction meta- Any course on computer organization will naturally involve a seg-
information is specified, namely the instruction fields, their types, ment on the memory hierarchy, and particularly caches. Typically,
widths, and positions within the instruction word. This information we consider the effect of different cache geometries and policies
is used to generate the assembler itself, alongside pattern match on performance metrics such as cache hit rate. To accompany this,
structures for an accompanying disassembler. The editor, as seen in Ripes implements a cache simulator that hooks into the memory
Figure 2, also leverages this information to generate an assembler- access trace of the processor model (Figure 3).
guided syntax helper and syntax highlighter. From a developer’s Cache geometry can be configured in terms of lines, ways, and
point of view, this organization allows for easy implementation blocks alongside configuring the replacement policy, as well as
of custom ISA extensions or support for entirely new ISAs within write hit- and miss policy (Figure 3.2). Based on the cache geometry
Ripes. and access trace, a visualization of the current state of the cache

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Ripes: A Visual Computer Architecture Simulator WCAE ’21, June 17, 2021, Online

is drawn (Figure 3.3). To show how the cache is currently being library routines3 . The inclusion of this is intentional—showing the
indexed, the line and block indices are highlighted in yellow. In the entire executable segment provides insight into what programming
intersection of these, an access is either colored green or red, based at a higher level of abstraction implies, such as the inclusion of
on whether the access was a hit or miss. When configured in write- startup code before entering main alongside any standard library
back mode, dirty blocks are highlighted in dark blue. Importantly, functions that have been referenced.
changes to the cache visualization are performed in conjunction
with clocking (or reversing) the processor, updating every cycle. 4 VISUAL SIMULATION OF REGISTER
During execution, the cache simulator gathers a trace of the TRANSFER LOGIC (RTL)
number of cache hits, misses, reads, writes, and writebacks. Ripes
One of the main goals of Ripes is to be able to show an accurate
provides built-in plotting of the ratio between any combination of
representation of all of the hardware structures that are included
these values, to illustrate their evolution over time. Figure 3.4 shows
in a processor design. In doing so, we want to describe processor
a plot of hits over total accesses, i.e., hit ratio of a given program.
models in an HDL rather than through software models, to capture
At the time of writing, only first-level instruction and data caches
the semantics of a real circuit. In early versions of Ripes, a circuit
are simulated. The current cache simulation mainly focuses on
and its visualization were described separately. These two compo-
teaching about the cache geometry itself as well as how the cache
nents then had to be manually stitched together to form the visual
is indexed. Presumably, once a user gains an understanding of how
simulator. It was quickly found that this was an unsustainable way
different cache design parameters influence cache indexing, it is
of describing circuits and their visualizations when new processor
redundant to visualize further levels of the cache hierarchy. As
models need to be added.
future work, we intend to provide the option of configuring a non
The need for a combined description, simulation, and visualiza-
visualized 𝑁 -level cache hierarchy, each with the configuration
tion framework eventually led to a spin-off project, called VSRTL.
options of Figure 3.2, alongside specification of timing parameters
VSRTL [22] (Visual Simulation of Register Transfer Logic) is a
and cache unification. This would allow for greater insight into the
framework for describing and visualizing cycle-accurate simula-
statistical properties and differences between different levels of the
tions of digital circuits. VSTRL is structured into two main compo-
cache hierarchy, and more closely approximate the characteristics
nents; VSRTL Core, a simple strutural HDL and simulator imple-
of real-world systems.
mented as a domain specific language (DSL) in C++, and VSRTL
Graphics, which implements circuit traversal, place and route, and
3.7 Compiler Support visualization.
After working with assembly-level programming to explore inter- The overarching goal of extracting all circuit-simulation logic
esting situations in the pipeline, a user may want to raise the level from Ripes is that Ripes should be an environment for visualiz-
of abstraction of which they describe their code. Some use cases ing and experimenting with a processor model. With VSRTL, we
could be that we want to describe a program which performs some can take an arbitrary processor model, insert it into a well-defined
intricate cache access patterns that would be tedious to describe in interface, and let Ripes be an environment for controlling and vi-
assembly, or that we are interested in investigating the instructions sualizing the computing system by hooking into this model. It
per cycle (IPC) of large programs for different processor models. could be argued that such an organization would benefit from the
To facilitate this, Ripes supports the compilation and simulation of use of a processor description language (PDL) [23] for describing
C-language programs. processor models. Indeed, using such a language would provide
Configuring and using C in Ripes is designed to be as easy as a generated compiler, ISA simulator, as well as a synthesizeable
possible; a user only has to provide a toolchain compatible with description of the processor. However, Ripes requires RTL-level
their target processor model and point Ripes to the location of this. control of the hardware structure of the processor model, given
After this, the user is taken out of the loop. Based on the currently our need to present a visualization that directly correlates with
selected processor model and its supported base ISA and ISA exten- the level of abstraction typically shown in educational material.
sions, Ripes will generate -mabi and -march compiler arguments, Furthermore, use of a PDL would still leave a need for a visual
ensuring invocation of the compiler backend that targets the cur- simulation of the described circuit.
rent processor. The editor may be set to ”C input type” (Figure 2), VSRTL Graphics has deliberately been made fully independent of
applying C syntax highlighting to the source code. Upon building, VSRTL Core wherein VSRTL Graphics defines an interface that an
Ripes generates a compile command and invokes the compiler to underlying simulator must implement. The intention of this is that
build a statically linked ELF file, which is then loaded into simulator VSRTL Graphics may be applied to other, more mature, hardware
memory. From here, the simulation proceeds as any other assembly- description and simulation languages.
level program. With an executable loaded, the disassembly view of The appeal of VSRTL lies in its ability to merge features across
the editor contains more information than one would expect to see design automation and educational tools. While most EDA tools
in Compiler Explorer—which shows only the compiled output of the provide a visualization of a circuit in the form of a schematic view
user-provided code—given that we are displaying what essentially pre- or post-synthesis, these are static visualizations—static, in that
is an objdump of the entire executable segment of the program2 . the visualization is not being modified during simulation of the
This extra information is mostly due to the inclusion of C standard
3A user may modify the compiler- and linker arguments, changing i.e., optimization
level, or disable static linking of the C standard library if they wish to produce a bare
2 only the .text segment is disassembled. executable with custom startup code.

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WCAE ’21, June 17, 2021, Online M.B. Petersen

class Foo : public Component {

Foo(...) {
a >> mux->get(MyEnum::A);
b >> mux->get(MyEnum::B);
sel >> mux->select;
mux->out >> reg->in;
out << [=] {
return reg->out.v() +
(mux->out.v() % 2);
};
}
SUBCOMPONENT(mux, EMux<MyEnum, 32>));
SUBCOMPONENT(reg, Register<32>);
INPUTPORT(a, 32);
INPUTPORT(b, 32);
INPUTPORT_ENUM(sel, MyEnum);
OUTPUTPORT(out, 32);
}; (b) For each port in the design, a label can be (c) Wires are highlighted upon selection.
displayed to show the current value of the port. Hovering over a wire displays its name
(a) Circuit description example, showing The value is displayed in a selectable radix, or (opcode) and value in the radix of the
port and subcomponent instantiation and as an enumerated value (if available). source port (0x0d).
connection.

Figure 4: VSRTL circuit description and visualization.

circuit. With VSRTL, we can visualize a circuit at an appropriate The benefit of this is, that the names of the enumerated type are
level of abstraction, and change the state of this to reflect values in exposed through the VSRTL Graphics interface, such that a user
the underlying simulator. can view a signal value not only in some radix but also decoded
The following sections detail VSRTL Core, VSRTL Graphics, as as the enumerated name (Figure 4b shows a ctrl port of the ALU
well as how VSRTL integrates into Ripes. component having a value corresponding to an enumerated ADD
value).
4.1 Circuit Description and Simulation An important feature in VSRTL Core is the ability for the sim-
VSRTL Core is a small HDL built as a DSL in C++. VSRTL Core is ulator to step back in time by undoing clock cycles. This feature
fully independent of VSRTL Graphics and only depends on the C++ was implemented as a response to the need for going back and
standard library. As such, circuits described in VSRTL core can be forward in time (cycles) when investigating an interesting situation
compiled and executed as stand-alone programs. in the visualized datapath, as described earlier. To support this, the
An example circuit description in VSRTL Core is shown in Fig- simulator stores a transaction trace for all sequential elements of
ure 4a. The syntax shares features with other HDLs, especially the circuit (memories and registers). Specifically, for each cycle,
SystemC [24]. A component is declared as a C++ class, inherit- we push onto a stack whether a write took place, write address,
ing from the Component class. Given this, VSRTL also supports and write width alongside the evicted value at the given address.
inheritance and generic (templated) components. A component Having this, undoing a clock cycle implies that for each sequential
may define its input and output ports as well as instantiate sub- element, a transaction is popped off this stack, reverted, and lastly,
components. Circuit interconnection and functionality are defined the entire circuit is re-propagating.
within the constructor. The >> operator connects ports together,
whereas the << operator defines a propagation function for a port. 4.2 Circuit Visualization
A propagation function defines a combinational black-box, which VSRTL Graphics is a library for visualizing and interacting with a
will not be visualized. Only a single clock signal is available, which digital circuit simulator, interacting with a simulator through a well-
is both global and implicit. defined interface. This interface requires the underlying simulator
Key to VSRTL Core is that component ports implement the ob- to expose functionality for traversing the circuit structure, clocking,
server pattern, allowing other entities to subscribe to being notified force updates to memory structures, give hints about component
when the value present on the port changes. This is used by VSRTL types, and expose the signals and ports of components. Components
Graphics to trigger updates in the circuit visualization. in VSRTL Graphics will register themselves as observers on the
Circuits may be described at arbitrary levels of abstraction, based underlying simulator ports, thus creating a link from circuit state
on the use of propagation functions. The implication of this is, changes to visualization state changes. A component is drawn based
that a design may be described such that only the parts which are on the underlying simulator component type hint, examples of
desired to be visualized are described in detail. Any combinational which are a register, arithmetic unit, or multiplexers. Components
functionality which is not required to be visualized may simply that contain subcomponents may be expanded, to expose their
be abstracted away as a propagation function. In the context of internal components, allowing for an arbitrary amount of visualized
processor designs, this could for instance be a control unit. subcomponents. Port-to-port connections are visualized as wires in
VSRTL Core supports enumerated signal types, which is particu- the datapath. To aid in navigating the wires of a datapath, clicking
larly useful when defining signals for control ports (Figure 4a shows a wire will highlight it, and when hovering over it, a tooltip will
a multiplexer being interfaced using an enumerated type MyEnum). display the name of the signal, as well as its current value (Figure 4c).

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Ripes: A Visual Computer Architecture Simulator WCAE ’21, June 17, 2021, Online

VSRTL Graphics implements a simple place-and-route routine it is hard to determine the exact number of universities that use
for managing the layout of an indexed circuit. However, a user may Ripes in teaching, it is estimated that the number is currently in
also manually scale, place, hide or show components and wires to the 10’s of universities. This estimate is based on a search of openly
create a custom layout. This is the case for the layout of Figure 1, available course material as well as redirects to the Ripes GitHub
which has been modified to look as identical as possible to diagrams page from internal university webpages.
seen in the literature. The layout of a design is serializable and may
be stored and reloaded from a file—this is how we can have multiple 6 FUTURE WORK
different layouts for the same processor model. During the time where Ripes has been in used, new features have
been continuously added to better support the needs of educators
4.3 VSRTL in Ripes as well as students, based on feedback from both of these groups.
Every processor model in Ripes inherits from a single base class. The current capabilities of Ripes are arguably limited to only a
This class defines the interface which makes a processor compatible subset of computer architecture education, typically some fraction
with the Ripes environment. As such, any processor model fulfilling of an undergraduate course. In the following section, we explore
this interface can leverage the environment provided by Ripes. Some future plans for the application—both short-term tasks as well as
of the key interface functions are: longer-term projects.
• Expose ISA and ISA extensions for Ripes to instantiate
6.1 Short Term
an appropriate assembler, to display register names, and to
control compiler invocation. 6.1.1 I/O. At the time of writing, work on implementing memory-
• Expose pipeline stage information including the number mapped I/O has begun, and support for this is planned to be shipped
of stages, stage names, instruction address of each stage, and with Ripes version 2.2. This is a feature that has been requested
whether the stage is valid. by multiple educators and users and should help Ripes to apply
• Force register or program counter values to initialize or to a larger subset of learning about embedded systems. Planned
modify the state of the processor. peripherals include buttons, switches, LED matrices, and simple
• Register a system call handler, allowing the processor to display adapters.
pass control to Ripes, for printing, file access, etc. 6.1.2 Multiple ISAs. As we have seen, Ripes is already built to be
Upon selecting a new processor model, Ripes reinitializes many ISA agnostic; all ISA-specific information displayed and used in the
parts of the user interface based on the provided information. When program is gathered based on the ISA which a processor announces
loading a new program, the processor is reset through VSRTL (re- that it implements. As such, adding new RISC-like ISAs is mostly a
setting all sequential elements), a system call handler is registered matter of gathering the required ISA meta-information and modi-
to the processor based on its ISA, the program is then written into fying the decode and control units of the current processor models.
simulator memory, and finally, the program counter is modified to Whether this is relevant, time will tell. At the time of writing, many
the entry point of the program. universities that previously taught MIPS—mainly due to its open
architecture—are switching to a RISC-V-based curriculum, and we
5 EVALUATION can only expect this trend to continue as RISC-V gains a stronger
foothold in both academia and industry.
In conjunction with the preparation of this work, various educators
who use Ripes in teaching were asked to share their thoughts on 6.2 Long Term
the simulator. The following section summarizes their feedback.
In general, it can be said that Ripes is appreciated for its simple In the light of many of the educational computer architecture simu-
user interface and presentation of the datapath structure as well lators who have come and gone through the years, it is worthwhile
as it working out-of-the-box on all major operating systems. Ripes to consider the efforts required for Ripes to avoid a similar fate.
is mainly being used as a basis for performing lab assignments, These projects typically go stale due to a lack of maintenance from
examples of this being: the few authors who wrote the simulator. The obvious answer is,
therefore, that a simulator may stay relevant and useful if it be-
• Writing RISC-V assembly to understand why user-scheduled comes an integral part of an open-source ecosystem wherein a
code is required for the ”early evolutions” of a pipelined larger group of people have a stake and interest in maintaining
processor (using the five-stage models without hazard detec- the relevance of the ecosystem. With Ripes targeting RISC-V, we
tion/resolution), are already benefiting from the current interest in not only RISC-V
• Writing RISC-V assembly to understand how forwarding itself but the general notion of open-source hardware.
is implemented in the datapath as well as the performance However, a surefire way to discourage active participation by the
improvements that it provides (using the five-stage model), open-source community is if a project relies on some proprietary
• Writing RISC-V or C programs for describing different cache functionality that is already available through an open-source coun-
stride patterns, execute these across different cache geome- terpart. This is currently the case with VSRTLs (and by extension,
tries and policies, to reason about any observed performance Ripes’) reliance on processor models being described in a custom
differences. HDL.
Some educators use Ripes during lecturing, to illustrate the evo- Recent times have seen increased efforts from academia and
lution of the pipeline as well as to run example programs. While industry alike to develop viable open-source alternatives to the

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WCAE ’21, June 17, 2021, Online M.B. Petersen

typically closed-source hardware toolchains of the major FPGA and [8] J. C. Moure, D. I. Rexachs, and E. Luque, “The kscalar simulator,” J. Educ.
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FPGA synthesis tools [26]. This provides an opportunity for simu- [9] D. Patti, A. Spadaccini, M. Palesi, F. Fazzino, and V. Catania, “Supporting under-
lators as well—particularly through the efforts to create a unified graduate computer architecture students using a visual mips64 cpu simulator,”
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intermediate representation (IR) for hardware [27, 28]. Not only are [10] T. Austin, E. Larson, and D. Ernst, “Simplescalar: an infrastructure for computer
IRs typically simpler to parse, they are also arguably simpler to sim- system modeling,” Computer, vol. 35, no. 2, pp. 59–67, 2002.
ulate, as compared to a high-level HDL. For educational tools such [11] M. Brorsson, “Mipsit: a simulation and development environment using animation
for computer architecture education,” in Proceedings of the 2002 workshop on
as Ripes, we then only need to simulate a circuit at an appropriate Computer architecture education: Held in conjunction with the 29th International
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structure is still preserved. Having an IR representation facilitates [12] I. Branovic, R. Giorgi, and E. Martinelli, “Webmips: a new web-based mips simu-
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[13] R. Giorgi and G. Mariotti, “Webrisc-v: A web-based education-oriented
observer access, undoing clock cycles, and circuit traversal, whilst risc-v pipeline simulation environment,” in Proceedings of the Workshop
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the end, being able to apply the visualization and simulation tech- Association for Computing Machinery, 2019. [Online]. Available: https:
//doi.org/10.1145/3338698.3338894
niques of VSRTL on circuits described in more powerful HDLs will [14] K. Vollmar and P. Sanderson, “Mars: an education-oriented mips assembly lan-
allow for the inclusion of more complex processor models, such guage simulator,” in Proceedings of the 37th SIGCSE technical symposium on Com-
as dynamically-scheduled out-of-order models, which currently puter science education, 2006, pp. 239–243.
[15] J. Larus, “Spim: A mips32 simulator,” http://pages.cs.wisc.edu/~larus/SPIM/spim.
would be tedious to describe and verify through VSRTL Core. html.
[16] B. Landers, “Rars - risc-v assembler and runtime simulator,” https://github.com/
TheThirdOne/rars.
7 CONCLUSION [17] K. Vakil, “Venus risc-v simulator,” http://www.kvakil.me/venus/.
[18] “The qt company,” https://www.qt.io/, 2021.
This work has presented Ripes, a visual computer architecture [19] LLVM, “Tablegen,” https://llvm.org/docs/TableGen/, 2021.
simulator based on the RISC-V ISA. Through the visualization of [20] C. Lattner and V. Adve, “Llvm: A compilation framework for lifelong program
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piler support, we have described how Ripes may integrate into a [21] M. Godbolt, “Compiler explorer,” https://godbolt.org/, 2017.
[22] M. B. Petersen, “Vsrtl: Visual simulation of register transfer logic,” https://github.
typical curriculum on computer architecture education. Many of com/mortbopet/VSRTL, 2021.
these features were made possible by the VSRTL project, which [23] P. Mishra and N. Dutt, Processor description languages. Elsevier, 2011.
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other open-source projects and engagement of the open-source and K. Asanović, “Chisel: constructing hardware in a scala embedded language,”
community, Ripes will continue to grow as well as remain a rele- in DAC Design Automation Conference 2012. IEEE, 2012, pp. 1212–1221.
[26] C. Wolf, “Yosys open synthesis suite,” http://www.clifford.at/yosys/.
vant teaching resource. And in doing so, ultimately make learning [27] A. Izraelevitz, J. Koenig, P. Li, R. Lin, A. Wang, A. Magyar, D. Kim, C. Schmidt,
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ACKNOWLEDGMENTS ACM SIGPLAN Conference on Programming Language Design and Implementation,
2020, pp. 258–271.
Thank you to Juan Antonio Maestro (Nebrija University), Matthias
König (FH Bielefeld), Yiwei Li (Tsinghua University), Luc Claesen
(Hasselt University), and Martin Schoeberl (Technical University of
Denmark), for providing feedback on their use of Ripes in teaching.

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