Hawassa University Daye Campus

Department of Computer Science

Microprocessor and Assembly Language Individual Assignment

Name ID

Petros Niguse...................................NaScR/2039/13

Submission date : 15/05/2023

Submitted to : Roba Bareto(MSc)

Contents page

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1. Concept of virtual memory, cache memory and FPU................1

1.1 virtual memory

1.2 cache memory

1.3 Floating point unit

2 Difference between register and memory

2.1 Microprocessor Registers

2.2 Memory

2.3 The Summary for CPU registers and Memory

5. Types of register indirect addressing language

5.1 Interms of size

5.2 Interms of operations

6. List of the 8/16/32 bit registers that are used for register addressing

6.1 8 bit Registers

6.2 16 bit Registers

6.3 32 bit Registers

7. super scalar of architecture of a Pentium processor.

7.1 Superscalar Processor Architecture of pentium Processor

7.2 Features of Superscalar Processor

8. clock period of a clock frequency of 1 Ghz

9. Storing datas in 2-byte word

10. Implementation of different instruction

1) What is the concept of virtual memory, cache memory and FPU (Floating
point unit) of a microprocessor?

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 ¡) Virtual Memory
❖ Virtual memory, or virtual storage is a memory management technique that
provides an "idealized abstraction of the storage resources that are actually
available on a given machine", which "creates the illusion to users of a very large
(main) memory".

● It is a concept used in some large computer systems that permit the user to
construct programs as though a large memory space were available, equal to the
totality of auxiliary memory.

❖ To explain it briefly, Virtual Memory is a computer concept where the main

memory is broken up into a series of individual pages. Those pages can be moved
in memory as a unit, or they can even be moved to secondary storage to make
room in main memory for new data.

● In essence, virtual memory allows a computer to use more RAM than it has
available.

Virtual Memory diagram

❖ Virtual
memory
combines active RAM and inactive memory on DASD to form a large range of
contiguous addresses.

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● The computer's operating system maps memory addresses used by a program,
called virtual addresses, into physical addresses in computer memory.

The primary benefits of virtual memory include

➢ Freeing applications from having to manage a shared memory space,

➢ Ability to share memory used by libraries between processes,

➢ Increased security due to memory isolation, and being able to conceptually use
more memory than might be physically available,

➢ Using the technique of paging or segmentation.

¡¡) Cache Memory

❖ Cache Memory is fastest small memory placed between the CPU and main
memory and it is more accessible to the processor, and able to increase efficiency, because
it's physically close to the processor.

➫ Cache memory is sometimes called CPU memory because it is typically integrated directly
into the CPU chip or placed on a separate chip that has a separate bus interconnect with the
CPU.

Cache Memory Diagram

❖ It acts as a temporary storage area that the computer's processor can retrieve data from
easily and is more readily available to the processor than the computer's main memory source.

➫ Its speed approaches the speed os CPU's Components , i.e it operates between 10 to 100
times faster than RAM, requiring only a few nanoseconds to respond to a CPU request, so that
it is expensive.

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❖ The fundamental idea of cache organization is that by keeping the most
frequently accessed instructions and data in the fast cache memory, the average
memory access time will approach the access time of the cache.

Types of cache memory

There are three general cache memory types or levels:

➢ Level 1 cache, or primary cache, is extremely fast but relatively small, and is usually
embedded in the processor chip as CPU cache.

➢ Level 2 cache, or secondary cache, is often more capacious than L1. L2 cache may be
embedded on the CPU, or it can be on a separate chip or coprocessor and have a high-speed
alternative system bus connecting the cache and CPU.

➢ Level 3 (L3) cache is specialized memory developed to improve the performance of L1 and
L2.

¡¡¡) Floating Point Unit

❖ A floating point unit is an integrated circuit which handles all mathematical operations that
have anything to do with floating point numbers or fractions.

➢ It is a dedicated logic unit specifically designed to work on floating point numbers.

❖ The FPU performs simple mathematical tasks which include addition, subtraction, division,
multiplication and square root.

Older FPUs process transcendental functions like exponential and trigonometric calculations
but these can be expensive and complicated to implement, so in modern FPUs, these are done
via software library routines.

➢ Not all computer systems have hardware FPU and those that do not have FPU can emulate
its functions in multiple ways such as:

➛ In an operating system as inherent functions.

➛ It can be emulated in the CPU as a microcode or microprogram.

➛ Or in user code; typically this is what is called as software emulation.

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2) Differentiate register and memory of microprocessor.

2.1) Microprocessor Registers

❖ A processor register (CPU register) is one of a small set of data holding places that are part
of the computer processor.

➤ A register may hold an instruction, a storage address, or any kind of data (such as a bit
sequence or individual characters).

❖ When a processor needs to work with data, it typically retrieves the necessary information from
memory and stores it in a register so that it can be manipulated more quickly.

➤ Processors have a number of registers and we can classify the processors based on the
structure of these registers and how the processor uses them. Popular processor designs can be
broadly divided into two categories:

🔹Complex Instruction Set Computers (CISC) and

🔹Reduced Instruction Set Computers (RISC).

➢ The Pentium Registers

The pentium register is categorized under CISC and has Ten 32-bit and Six 16-bit registers.It
includes the following.

❖ Data Registers

• Four 32-bit registers (EAX, EBX, ECX, EDX); or Four 16-bit registers (AX, BX, CX, DX); or Eight 8-
bit registers (AH, AL, BH, BL, CH, CL, DH, DL).

❖ Pointer Registers

The pointer registers are mainly used to maintain the stack. It can be used either as 16- or 32-
bit registers. Pointer registers includes:- Stack pointer(SP), and Base Pointer(BP).

❖ Index Registers

The index registers play a special role in string processing instructions. Index registers includes:-
Source Index(SI) and Destination Index(DI).

❖ Control Registers

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This group of registers consists of two 32-bit registers:

▸ the instruction pointer register and ▸the flags register.

❖ Segment Registers

◎ The code segment (CS) , Data segment (DS), Stack segment (SS) ,Extra Segment(ES), FS, and
GS are segment registers.

2.2) Memory

➢ Any system which processes digital data needs a facility for storing the unprocessed, partially
processed, and completely processed data. Memory is a subsystem of such digital processing system
which can store all the mentioned data.

➢ There are four primary Memory Technologies used today in memory hierarchy

1) DRAM( Dynamic Random Access Memory )

In the dynamic RAM, the data is stored in the form of a charge on the capacitor.

The name of the hardware that is used in a computer's main memory is dynamic random access
memory (DRAM).

It is less costly than SRAM, although it is substantially slower.

2) SRAM( Static Random Access Memory )

Static RAM cells are basically flip flops that can stay in a given state (i.e. store a bit) as long as the power
to the circuit is not interrupted.

Levels close to the Processors (cahes) use SRAM.

It is the fastest and expensive.

3) Flash Memory

This non volatile memomory is secondary memory in personal mobile devices.

It is type of Electrically Erasable Programmable Read Only Memory(EEPROM).

4) Magnetic Disk

It is the largest and slowest level in the hierarchy in servers.

It is type of sequential memories, by which memory locations are organized in a sequence(one after the
other) and the reading/writing from such memories is a sequential process.

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 ❖ The Summary for CPU registers and Memory

CPU Register Memory

Registers are small units of storage within a Memory, on the other hand, refers to the larger
processor that are used to store data that the storage area on a computer that stores both data
processor is currently working on or about to work and programs that are not currently in use by the
with. processor.

Registers are located within the processor itself. Memory is located outside the processor and it is
accessed by CPU using d/t techniques.

Registers are much faster to access but have Memory is slower but can store more data.
smaller storage capacity.

5) Discuss deferent types of register indirect addressing language Size,

operation

❖ Register indirect addressing mode is a type of addressing mode where the

memory location (offset) is not mentioned directly in the instruction.

✔️In this mode, an instruction specifies a register, and the processor uses the
content of that register as a memory address to access the data.

❖ There are different types of Register indirect addressing mode includes:-

1) Basic Register Indirect Addressing: This addressing mode uses a single

register to hold the memory address. The size of the register and the operand
depends on the processor architecture.

2) Auto-Increment/Decrement Register Indirect Addressing: In this addressing

mode, the value in the register is incremented or decremented by a fixed amount
after each access. This allows for easy access to a sequence of memory locations.
The size of the register and the increment/decrement amount depend on the
architecture.

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3) Scaled Register Indirect Addressing: This addressing mode is used in
architectures with complex addressing modes. It involves multiplying the content
of the register by a scaling factor before accessing the memory location.

✔️The size of the operand depends on the architecture and the type of data being
accessed. For example, in a 32-bit architecture, the size of the operand might be
32 bits for a 32-bit integer, or it could be 64 bits for a double-precision floating-
point number.

✔️In terms of operation, register indirect addressing modes allow for more
flexible and efficient memory access than direct addressing modes. They also
allow for easier implementation of data structures such as arrays and linked lists.
However, their complexity can make them harder to understand and debug
compared to simpler addressing modes.

6) List the 8/16/32 bit registers that are used for register addressing?

Processors have a number of registers, used for register addressing, those are:-

✔️8 bit Registers

❖ General registers such as Accumulator, Base addressing register, Counter loop

operations and Data I/O operation registers can be accessed as full 16 bits or as
the high byte only or low byte only Which are 8-bits.

AL,AH,BL,BH,CL,CH,DL and DH

✔️16 bit Registers

It includes various kinds of registers, such as

❖ General Registers :- AX,BX,CX &DX

❖ Pointer Registers :- SP(Stack Pointer), BP(Base Pointer) & IP(Instruction Pointer)

❖ Index Registers :- SI(Source Index) & DI(Destination Index)

❖ Segment Registers :- CS(Code segment), DS(Data Segment), SS(Stack Segment) &

ES(Extra Segment).

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✔️32 bit Registers are EAX,EBX,ECX & ECX

❖ Those Registers are also explained in question number two above.

7) Define super scalar of architecture of a Pentium processor.

What is Superscalar Processor?

❖ It is a type of microprocessor that is used to implement a type of parallelism known as instruction-

level parallelism in a single processor to execute more than one instruction.

❖ A scalar processor executes single instruction for each clock cycle; a superscalar processor can
execute more than one instruction during a clock cycle.

➢ The design techniques of superscalar normally comprise parallel register renaming, parallel
instruction decoding, out-of-order executions & speculative execution.

❖ The Intel Pentium processor superscalar pipelined architecture means the CPU executes a minimum
of two or above instructions for each cycle. This processor is widely used in personal computers. Intel
Pentium processor devices are normally built for online use, cloud computing, & collaboration.

✔️Superscalar Processor Architecture of pentium Processor

➢ The superscalar processor is equipped with several processing units for handling various instructions
in parallel in every processing stage.

Superscalar Processor
Architecture Diagram

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❖ In the above architecture diagram, a processor is used with two execution units where one is used for
integer & other one is used for the operations of floating point. The instruction fetch unit (IFU) is
capable of instructions reading at a time & stores them within the instruction queue.

✔️ Features of Superscalar Processor

➣ Superscalar architecture is a parallel computing technique utilized in various processors.

➣ In a superscalar computer, the CPU manages several instruction pipelines to perform numerous
instructions simultaneously during a clock cycle.

➣ Superscalar architectures include all pipelining features although there are several instructions
executing simultaneously within the same pipeline.

➣ Superscalar design methods normally comprise parallel register renaming, parallel instruction
decoding, speculative execution & out-of-order execution.

➣ So, these methods are normally used with complementing design methods like caching, pipelining,
branch prediction & multi-core in recent microprocessor designs.

8) What is clock period of a clock frequency of 1 Ghz?

❖ The clock periodClock period

is defined as=the
1 / length
Clock frequency
of time taken by one clock cycle and it
is given by :-

So, a clock frequency of 1 GHz yields a clock period of ?

=> Clock period = 1 / Clock frequency

=> Clock period = 1 / 1*109Hz, but Hz=1/S or S-1 Where S= Second.

=> Clock period = 1*10-9S= 1ns

❖ Therefore, the length of time taken by one clock cycle of a clock frequency of 1
Ghz is 1 nanosecond.

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9) Suppose memory bytes 1-5 have the following contents

Address Contents
1 01101010

2 11011101

3 00010001

4 11111111

5 01010101

Assume that a word is 2 byte; what are the contents in (Hex)

-the word of memory address of 2?

- the word of memory address of 3?

- what is bit 7 of byte 2?

❖ Memory is devided in to bytes. So, Words(2_byte) & Double Words(4_byte)

must be split across multiple bytes.

✔️Therefore, there are two ways to store words and double words.

#1) Little-endian byte ordering :- least significant byte is stored at lowest address.

#2) Big-endian byte ordering :- most significant byte is stored at lowest address.

❖ Using those rules...

¡) the contents of word of memory address of 2 is :-

=> 11011101 00010001

=> 1101110100010001 ( binary form)

=> DD11 ( in Hexadecimal form)

¡¡) the contents of word of memory address of 3 is :-

=> 00010001 11111111

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=> 0001000111111111 (binary form)

=> 11FF ( in Hexadecimal form)

¡¡¡) what is bit 7 of byte 2?

=> byte 2 = 11011101

=> 1716051413120110

bit 0 = 1 bit 3 = 1 bit 6 = 1

bit 1= 0 bit 4 = 1 bit 7 = 1

bit 2 = 1 bit 5 = 0

Therefore, bit 7 of byte 2 is 1.

10. The processor has only 4 instructions (Conditional branch, Add, LDW,
SDW). The processor has 16-bit 8 registers and 256B Memory. The ISA is a
fixed-length ISA and it has 16 bits.
You need to implement, BR, ADD, LDW and SDW. Architectural states, you
need to implement PC, Registers, Memory, and 3-bit CC (NZP).

✔️To solve this problem, we need to implement the following instructions along
with the architectural states such as :

❖ Conditional branch (BR) - This instruction allows for conditional branching

based on the state of the 3-bit condition code register (CC). The BR instruction has
a 9-bit signed offset field that specifies the number of instructions to skip over if
the branch is not taken.

❖ Add (ADD) - This instruction adds the contents of two registers and stores the
result in a third register.

❖ Load word (LDW) - This instruction loads a 16-bit value from memory into a
register. It has a 3-bit field for selecting the destination register and a 9-bit field
for specifying the memory address to load the value from.

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❖ SDW - The processor reads the source register and the memory address fields
from the instruction. The 16-bit value stored in the source register is stored at the
corresponding memory address.

✔️For architectural states, we need to implement the following:

1. PC (program counter) - This register keeps track of the current instruction

being executed. It is incremented by one after each instruction execution.

2. Registers - There are eight general-purpose registers, R0-R7, each with a size of
16 bits.

3. Memory - The processor has a 256-byte addressable memory. Each address

contains a 16-bit value.

4. Condition code register (CC) - This is a 3-bit register that stores the status of the
previous arithmetic operation. The bits represent negative (N), zero (Z), and
positive (P) conditions respectively.

✔️The implementation of each instruction can be as follows:

1. BR - The processor reads the offset from the instruction and checks the
condition code bits. If they match the specified condition, the program counter is
updated with the current PC plus the offset shifted left by 1. Otherwise, the
program counter is simply incremented by one.

2. ADD - The processor reads the three register fields from the instruction and
performs the addition. The result is stored in the destination register. If any
overflow occurs, the condition code bits are set accordingly.

3. LDW - The processor reads the destination register and the memory address
fields from the instruction. The 16-bit value stored at the corresponding memory
address is loaded into the destination register.

4. SDW - The processor reads the source register and the memory address fields
from the instruction. The 16-bit value stored in the source register is stored at the
corresponding memory address.

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✔️Using the above requirements we can solve the problem as follows.

ADD

ADD DR, SR1, SR2

ADD DR, SR1, imm5

Operation

if (bit[5] == 0) DR = SR1+SR2;

else DR = SR1 + SEXT(imm5);

setcc();

BR

BRn Label

BRp Label

BRz Label

BRnzp Label

if (n And N) or (z and Z) or (p and P))

pc = pc* + LSHF(SEXT(pcoffset9),1)

pc* is current pc+2;

LDW

LDW DR, BaseR, offset

DR=MEM[BaseR+LSHR(SEXT(offset6),1];

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Set cc();

STW

STW SR, BaseR, offset6

MEM[Base + LSHF(SEXT(offset6), 1)] = SR;

Initial PC value The program starts at 0x10. The instructions are a subset of LC3-B ISA.

REFERENCES

1. Introduction to Assembly Language Programming For Pentium and RISC

Processors book

2. GeeksforGeeks.com

3.http://byjus.com

4.techtarget.com

5.chegg.com

6.elprocus.com

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