INTRODUCTION TO

COMPUTING

The 8051 Microcontroller and Embedded

Systems: Using Assembly and C
Mazidi, Mazidi and McKinlay

Chung-Ping Young
楊中平

Home Automation, Networking, and Entertainment Lab

Dept. of Computer Science and Information Engineering
National Cheng Kung University, TAIWAN
 ‰ Numbering and coding systems
OUTLINES
‰ Digital primer
‰ Inside the computer

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 ‰ Human beings use base 10 (decimal)
NUMBERING
AND CODING
arithmetic
SYSTEMS ¾ There are 10 distinct symbols, 0, 1, 2, …,
9
Decimal and ‰ Computers use base 2 (binary) system
Binary Number ¾ There are only 0 and 1
Systems
¾ These two binary digits are commonly
referred to as bits

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 ‰ Divide the decimal number by 2
NUMBERING
AND CODING
repeatedly
SYSTEMS ‰ Keep track of the remainders
‰ Continue this process until the quotient
Converting becomes zero
from Decimal
‰ Write the remainders in reverse order
to Binary
to obtain the binary number
Ex. Convert 2510 to binary
Quotient Remainder
25/2 = 12 1 LSB (least significant bit)
12/2 = 6 0
6/2 = 3 0
3/2 = 1 1
1/2 = 0 1 MSB (most significant bit)
Therefore 2510 = 110012
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 ‰ Know the weight of each bit in a binary
NUMBERING number
AND CODING
‰ Add them together to get its decimal
SYSTEMS
equivalent
Converting Ex. Convert 110012 to decimal
from Binary to Weight: 24 23 22 21 20
Decimal Digits: 1 1 0 0 1
Sum: 16 + 8+ 0+ 0+ 1 = 2510

‰ Use the concept of weight to convert a

decimal number to a binary directly
Ex. Convert 3910 to binary
32 + 0 + 0 + 4 + 2 + 1 = 39
Therefore, 3910 = 1001112
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 ‰ Base 16, the
NUMBERING
AND CODING
hexadecimal system, Decimal Binary Hex

SYSTEMS is used as a 0 0000 0

1 0001 1
convenient 2 0010 2
Hexadecimal representation of 3 0011 3
4 0100 4
System binary numbers 5 0101 5
¾ ex. 6 0110 6
7 0111 7
It is much easier to 8 1000 8
represent a string of 0s 9 1001 9
and 1s such as 10 1010 A
100010010110 as its 11 1011 B
hexadecimal equivalent of 12 1100 C
896H 13 1101 D
14 1110 E
15 1111 F

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 ‰ To represent a binary number as its
NUMBERING equivalent hexadecimal number
AND CODING
¾ Start from the right and group 4 bits at a
SYSTEMS
time, replacing each 4-bit binary number
with its hex equivalent
Converting
between Binary Ex. Represent binary 100111110101 in hex
and Hex 1001 1111 0101
= 9 F 5

‰ To convert from hex to binary

¾ Each hex digit is replaced with its 4-bit
binary equivalent
Ex. Convert hex 29B to binary
2 9 B
= 0010 1001 1011
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 ‰ Convert to binary first and then
NUMBERING
AND CODING
convert to hex
SYSTEMS ‰ Convert directly from decimal to hex
by repeated division, keeping track of
Converting the remainders
from Decimal
to Hex Ex. Convert 4510 to hex
32 16 8 4 2 1
1 0 1 1 0 1 32 + 8 + 4 + 1 = 45
4510 = 0010 11012 = 2D16
Ex. Convert 62910 to hex
512 256 128 64 32 16 8 4 2 1
1 0 0 1 1 1 0 1 0 1
62910 = 512+64+32+16+4+1 = 0010 0111 01012 = 27516

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 ‰ Convert from hex to binary and then to
NUMBERING
AND CODING
decimal
SYSTEMS ‰ Convert directly from hex to decimal
by summing the weight of all digits
Converting
from Hex to Ex. 6B216 = 0110 1011 00102
1024 512 256 128 64 32 16 8 4 2 1
Decimal
1 1 0 1 0 1 1 0 0 1 0
1024 + 512 + 128 + 32 + 16 + 2 = 171410

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 ‰ Adding the digits together from the
NUMBERING
AND CODING
least significant digits
SYSTEMS ¾ If the result is less than 16, write that digit
as the sum for that position
Addition of Hex ¾ If it is greater than 16, subtract 16 from it
Numbers to get the digit and carry 1 to the next
digit
Ex. Perform hex addition: 23D9 + 94BE

23D9 LSD: 9 + 14 = 23 23 – 16 = 7 w/ carry

+ 94BE 1 + 13 + 11 = 25 25 – 16 = 9 w/ carry
B897 1 + 3+4=8
MSD: 2 + 9=B

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 ‰ If the second digit is greater than the
NUMBERING
AND CODING
first, borrow 16 from the preceding
SYSTEMS digit
Ex. Perform hex subtraction: 59F – 2B8
Subtraction of
Hex Numbers 59F LSD: 15 – 8 = 7
– 2B8 9 + 16 – 11 = 14 = E16
2E7 5–1–2=2

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 ‰ The ASCII (pronounced “ask-E”) code
NUMBERING assigns binary patterns for
AND CODING ¾ Numbers 0 to 9
SYSTEMS ¾ All the letters of English alphabet,
uppercase and lowercase
ASCII Code ¾ Many control codes and punctuation
marks
‰ The ASCII system uses 7 bits to
represent each code
Hex Symbol Hex Symbol
Selected ASCII codes 41 A 61 a
42 B 62 b
43 C 63 c
44 D 64 d
... ... ... …
59 Y 79 y
5A Z 7A z
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 ‰ Two voltage levels can be represented
DIGITAL
PRIMER
as the two digits 0 and 1
‰ Signals in digital electronics have two
Binary Logic distinct voltage levels with built-in
tolerances for variations in the voltage
‰ A valid digital signal should be within
either of the two shaded areas
5
4 Logic 1
3
2
1
Logic 0
0

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 ‰ AND gate
DIGITAL
PRIMER

Logic Gates

Computer Science Illuminated, Dale and Lewis

‰ OR gate

Computer Science Illuminated, Dale and Lewis

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 ‰ Tri-state buffer
DIGITAL
PRIMER ‰ Inverter

Logic Gates
(cont’)

Computer Science Illuminated, Dale and Lewis

‰ XOR gate

Computer Science Illuminated, Dale and Lewis

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 ‰ NAND gate
DIGITAL
PRIMER

Logic Gates
(cont’)
Computer Science Illuminated, Dale and Lewis

‰ NOR gate

Computer Science Illuminated, Dale and Lewis

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 DIGITAL
PRIMER Half adder

Logic Design
Using Gates

Full adder

Digital Design, Mano

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 DIGITAL
PRIMER
4-bit adder
Logic Design
Using Gates
(cont’)

Digital Design, Mano

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 ‰ Decoders
DIGITAL
PRIMER ¾ Decoders are widely used for address
decoding in computer design
Logic Design Address Decoders
Using Gates
(cont’)

Address decoder for 9 (10012) Address decoder for 5 (01012)

The output will be 1 if and The output will be 1 if and
only if the input is 10012 only if the input is 01012

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 ‰ Flip-flops
DIGITAL
PRIMER ¾ Flip-flops are frequently used to store data

Logic Design
Using Gates
(cont’)
Digital Design, Mano

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 ‰ The unit of data size
INSIDE THE
COMPUTER ¾ Bit : a binary digit that can have the value
0 or 1
Important ¾ Byte : 8 bits
Terminology ¾ Nibble : half of a bye, or 4 bits
¾ Word : two bytes, or 16 bits
‰ The terms used to describe amounts of
memory in IBM PCs and compatibles
¾ Kilobyte (K): 210 bytes
¾ Megabyte (M) : 220 bytes, over 1 million
¾ Gigabyte (G) : 230 bytes, over 1 billion
¾ Terabyte (T) : 240 bytes, over 1 trillion

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 ‰ CPU (Central Processing Unit)
INSIDE THE ¾ Execute information stored in memory
COMPUTER ‰ I/O (Input/output) devices
¾ Provide a means of communicating with
Internal CPU
Organization of ‰ Memory
Computers ¾ RAM (Random Access Memory) –
temporary storage of programs that
computer is running
ƒ The data is lost when computer is off
¾ ROM (Read Only Memory) – contains
programs and information essential to
operation of the computer
ƒ The information cannot be changed by use,
and is not lost when power is off
– It is called nonvolatile memory

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 INSIDE THE
COMPUTER

Internal Address bus

Organization of
Computers Memory
Peripherals
(cont’) CPU (monitor,
(RAM, ROM)
printer, etc.)

Data bus

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 ‰ The CPU is connected to memory and
INSIDE THE
COMPUTER
I/O through strips of wire called a bus
¾ Carries information from place to place
Internal ƒ Address bus
Organization of ƒ Data bus
ƒ Control bus
Computers
(cont’)
Address bus

RAM ROM Printer Disk Monitor Keyboard

CPU

Data bus
Read/
Write
Control bus

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 ‰ Address bus
INSIDE THE
¾ For a device (memory or I/O) to be
COMPUTER recognized by the CPU, it must be
assigned an address
Internal ƒ The address assigned to a given device must
Organization of be unique
Computers ƒ The CPU puts the address on the address bus,
(cont’) and the decoding circuitry finds the device
‰ Data bus
¾ The CPU either gets data from the device
or sends data to it
‰ Control bus
¾ Provides read or write signals to the
device to indicate if the CPU is asking for
information or sending it information

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 ‰ The more data buses available, the
INSIDE THE
COMPUTER
better the CPU
¾ Think of data buses as highway lanes
More about ‰ More data buses mean a more
Data Bus expensive CPU and computer
¾ The average size of data buses in CPUs
varies between 8 and 64
‰ Data buses are bidirectional
¾ To receive or send data
‰ The processing power of a computer is
related to the size of its buses

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 ‰ The more address buses available, the
INSIDE THE larger the number of devices that can
COMPUTER be addressed
More about ‰ The number of locations with which a
Address Bus CPU can communicate is always equal
to 2x, where x is the address lines,
regardless of the size of the data bus
¾ ex. a CPU with 24 address lines and 16
data lines can provide a total of 224 or 16M
bytes of addressable memory
¾ Each location can have a maximum of 1
byte of data, since all general-purpose
CPUs are byte addressable
‰ The address bus is unidirectional

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 ‰ For the CPU to process information,
INSIDE THE the data must be stored in RAM or
COMPUTER ROM, which are referred to as primary
memory
CPU’s Relation ‰ ROM provides information that is fixed
to RAM and and permanent
ROM ¾ Tables or initialization program
‰ RAM stores information that is not
permanent and can change with time
¾ Various versions of OS and application
packages
¾ CPU gets information to be processed
ƒ first form RAM (or ROM)
ƒ if it is not there, then seeks it from a mass
storage device, called secondary memory, and
transfers the information to RAM

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 ‰ Registers
INSIDE THE
COMPUTER ¾ The CPU uses registers to store
information temporarily
Inside CPUs ƒ Values to be processed
ƒ Address of value to be fetched from memory
¾ In general, the more and bigger the
registers, the better the CPU
ƒ Registers can be 8-, 16-, 32-, or 64-bit
ƒ The disadvantage of more and bigger registers
is the increased cost of such a CPU

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 Address Bus
INSIDE THE
COMPUTER Program Counter

Inside CPUs
(cont’)
Instruction Register

Control Bus Data Bus

Flags ALU
Instruction decoder,
timing, and control

Internal Register A
buses
Register B
Register C
Register D

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 ‰ ALU (arithmetic/logic unit)
INSIDE THE
¾ Performs arithmetic functions such as add,
COMPUTER subtract, multiply, and divide, and logic
functions such as AND, OR, and NOT
Inside CPUs
(cont’)
‰ Program counter
¾ Points to the address of the next
instruction to be executed
ƒ As each instruction is executed, the program
counter is incremented to point to the address
of the next instruction to be executed
‰ Instruction decoder
¾ Interprets the instruction fetched into the
CPU
ƒ A CPU capable of understanding more
instructions requires more transistors to design

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 Ex. A CPU has registers A, B, C, and D and it has an 8-bit
INSIDE THE data bus and a 16-bit address bus. The CPU can access
COMPUTER memory from addresses 0000 to FFFFH
Assume that the code for the CPU to move a value to
Internal register A is B0H and the code for adding a value to
Working of register A is 04H
Computers The action to be performed by the CPU is to put 21H into
register A, and then add to register A values 42H and 12H

...

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 Ex. (cont’)
INSIDE THE Action Code Data
COMPUTER Move value 21H into reg. A B0H 21H
Add value 42H to reg. A 04H 42H
Internal Add value 12H to reg. A 04H 12H
Working of
Mem. addr. Contents of memory address
Computers 1400 (B0) code for moving a value to register A
(cont’) 1401 (21) value to be moved
1402 (04) code for adding a value to register A
1403 (42) value to be added
1404 (04) code for adding a value to register A
1405 (12) value to be added
1406 (F4) code for halt

...

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 Ex. (cont’)
INSIDE THE The actions performed by CPU are as follows:
COMPUTER 1. The program counter is set to the value 1400H,
indicating the address of the first instruction code to
Internal be executed
Working of 2.
Computers ¾ The CPU puts 1400H on address bus and sends it
(cont’) out
ƒ The memory circuitry finds the location
¾ The CPU activates the READ signal, indicating to
memory that it wants the byte at location 1400H
以動畫表示 ƒ This causes the contents of memory location
1400H, which is B0, to be put on the data bus and
brought into the CPU
...

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 Ex. (cont’)
INSIDE THE 3.
COMPUTER ¾ The CPU decodes the instruction B0
¾ The CPU commands its controller circuitry to bring
Internal into register A of the CPU the byte in the next
Working of memory location
Computers ƒ The value 21H goes into register A
(cont’) ¾ The program counter points to the address of the
next instruction to be executed, which is 1402H
ƒ Address 1402 is sent out on the address bus to
fetch the next instruction

...

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 Ex. (cont’)
INSIDE THE 4.
COMPUTER ¾ From memory location 1402H it fetches code 04H
¾ After decoding, the CPU knows that it must add to
Internal the contents of register A the byte sitting at the
Working of next address (1403)
Computers ¾ After the CPU brings the value (42H), it provides
(cont’) the contents of register A along with this value to
the ALU to perform the addition
ƒ It then takes the result of the addition from the
ALU’s output and puts it in register A
ƒ The program counter becomes 1404, the address
of the next instruction

...

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 Ex. (cont’)
INSIDE THE 5.
COMPUTER ¾ Address 1404H is put on the address bus and the
code is fetched into the CPU, decoded, and
Internal executed
Working of ƒ This code is again adding a value to register A
Computers ƒ The program counter is updated to 1406H
(cont’) 6.
¾ The contents of address 1406 are fetched in and
executed
¾ This HALT instruction tells the CPU to stop
incrementing the program counter and asking for
the next instruction

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 8051 MICROCONTROLLERS

The 8051 Microcontroller and Embedded

Systems: Using Assembly and C
Mazidi, Mazidi and McKinlay

Chung-Ping Young
楊中平

Home Automation, Networking, and Entertainment Lab

Dept. of Computer Science and Information Engineering
National Cheng Kung University, TAIWAN
 ‰ Microcontrollers and embedded
OUTLINES
processors
‰ Overview of the 8051 family

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 ‰ General-purpose microprocessors
MICRO-
CONTROLLERS
contains
AND ¾ No RAM
EMBEDDED ¾ No ROM
PROCESSORS ¾ No I/O ports

Microcontroller
‰ Microcontroller has
vs. General- ¾ CPU (microprocessor)
Purpose ¾ RAM
Microprocessor ¾ ROM
¾ I/O ports
¾ Timer
¾ ADC and other peripherals

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 Data bus
MICRO- General-
purpose
CONTROLLERS Micro-
Processor I/O Serial
AND RAM ROM
Port
Timer COM
Port
EMBEDDED
PROCESSORS CPU
Address bus

Microcontroller
vs. General-
Purpose Microcontroller
Microprocessor CPU RAM ROM
(cont’)

Serial
I/O Timer COM
Port

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 ‰ General-purpose microprocessors
MICRO-
¾ Must add RAM, ROM, I/O ports, and
CONTROLLERS timers externally to make them functional
AND ¾ Make the system bulkier and much more
EMBEDDED expensive
PROCESSORS ¾ Have the advantage of versatility on the
amount of RAM, ROM, and I/O ports
Microcontroller ‰ Microcontroller
vs. General- ¾ The fixed amount of on-chip ROM, RAM,
Purpose and number of I/O ports makes them ideal
Microprocessor for many applications in which cost and
(cont’) space are critical
¾ In many applications, the space it takes,
the power it consumes, and the price per
unit are much more critical considerations
than the computing power

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 ‰ An embedded product uses a
MICRO- microprocessor (or microcontroller) to
CONTROLLERS do one task and one task only
AND
¾ There is only one application software that
EMBEDDED
is typically burned into ROM
PROCESSORS
‰ A PC, in contrast with the embedded
Microcontrollers system, can be used for any number of
for Embedded applications
Systems ¾ It has RAM memory and an operating
system that loads a variety of applications
into RAM and lets the CPU run them
¾ A PC contains or is connected to various
embedded products
ƒ Each one peripheral has a microcontroller inside
it that performs only one task

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 ‰ Home
MICRO- ¾ Appliances, intercom, telephones, security systems,
CONTROLLERS garage door openers, answering machines, fax
AND machines, home computers, TVs, cable TV tuner,
VCR, camcorder, remote controls, video games,
EMBEDDED cellular phones, musical instruments, sewing
PROCESSORS machines, lighting control, paging, camera, pinball
machines, toys, exercise equipment
Microcontrollers ‰ Office
for Embedded ¾ Telephones, computers, security systems, fax
Systems machines, microwave, copier, laser printer, color
printer, paging
(cont’)
‰ Auto
¾ Trip computer, engine control, air bag, ABS,
instrumentation, security system, transmission
control, entertainment, climate control, cellular
phone, keyless entry

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 ‰ Many manufactures of general-purpose
MICRO- microprocessors have targeted their
CONTROLLERS microprocessor for the high end of the
AND
embedded market
EMBEDDED
¾ There are times that a microcontroller is
PROCESSORS
inadequate for the task
x86 PC ‰ When a company targets a general-
Embedded purpose microprocessor for the
Applications embedded market, it optimizes the
processor used for embedded systems
‰ Very often the terms embedded
processor and microcontroller are used
interchangeably

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 ‰ One of the most critical needs of an
MICRO- embedded system is to decrease
CONTROLLERS power consumption and space
AND
EMBEDDED ‰ In high-performance embedded
PROCESSORS processors, the trend is to integrate
more functions on the CPU chip and let
x86 PC designer decide which features he/she
Embedded wants to use
Applications ‰ In many cases using x86 PCs for the
(cont’)
high-end embedded applications
¾ Saves money and shortens development
time
ƒ A vast library of software already written
ƒ Windows is a widely used and well understood
platform
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 ‰ 8-bit microcontrollers
MICRO-
CONTROLLERS ¾ Motorola’s 6811
AND ¾ Intel’s 8051
EMBEDDED ¾ Zilog’s Z8
PROCESSORS ¾ Microchip’s PIC

Choosing a ‰ There are also 16-bit and 32-bit

Microcontroller microcontrollers made by various chip
makers

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 ‰ Meeting the computing needs of the
MICRO-
CONTROLLERS
task at hand efficiently and cost
AND effectively
EMBEDDED ¾ Speed
PROCESSORS ¾ Packaging
¾ Power consumption
Criteria for
¾ The amount of RAM and ROM on chip
Choosing a
Microcontroller ¾ The number of I/O pins and the timer on
chip
¾ How easy to upgrade to higher-
performance or lower power-consumption
versions
¾ Cost per unit

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 ‰ Availability of software development
MICRO- tools, such as compilers, assemblers,
CONTROLLERS and debuggers
AND
EMBEDDED ‰ Wide availability and reliable sources
PROCESSORS of the microcontroller
¾ The 8051 family has the largest number of
Criteria for diversified (multiple source) suppliers
Choosing a ƒ Intel (original)
ƒ Atmel
Microcontroller
(cont’) ƒ Philips/Signetics
ƒ AMD
ƒ Infineon (formerly Siemens)
ƒ Matra
ƒ Dallas Semiconductor/Maxim

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 ‰ Intel introduced 8051, referred as MCS-
OVERVIEW OF 51, in 1981
8051 FAMILY ¾ The 8051 is an 8-bit processor
ƒ The CPU can work on only 8 bits of data at a
time
8051
Microcontroller ¾ The 8051 had
ƒ 128 bytes of RAM
ƒ 4K bytes of on-chip ROM
ƒ Two timers
ƒ One serial port
ƒ Four I/O ports, each 8 bits wide
ƒ 6 interrupt sources
‰ The 8051 became widely popular after
allowing other manufactures to make
and market any flavor of the 8051, but
remaining code-compatible
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 External
Interrupts
OVERVIEW OF
8051 FAMILY

Counter Inputs
On-chip
Interrupt ROM On-chip Etc.
Control Timer 0
8051 for code RAM Timer 1
Microcontroller
(cont’)
CPU

OSC Bus I/O Serial

Control Ports Port

P0 P1 P2 P3 TXD RXD

Address/Data

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 ‰ The 8051 is a subset of the 8052
OVERVIEW OF
8051 FAMILY ‰ The 8031 is a ROM-less 8051
¾ Add external ROM to it
8051 Family ¾ You lose two ports, and leave only 2 ports
for I/O operations

Feature 8051 8052 8031

ROM (on-chip program
4K 8K 0K
space in bytes)
RAM (bytes) 128 256 128
Timers 2 3 2
I/O pins 32 32 32
Serial port 1 1 1
Interrupt sources 6 8 6

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 ‰ 8751 microcontroller
OVERVIEW OF
8051 FAMILY ¾ UV-EPROM
ƒ PROM burner
Various 8051 ƒ UV-EPROM eraser takes 20 min to erase
Microcontrollers ‰ AT89C51 from Atmel Corporation
¾ Flash (erase before write)
ƒ ROM burner that supports flash
ƒ A separate eraser is not needed
‰ DS89C4x0 from Dallas Semiconductor,
now part of Maxim Corp.
¾ Flash
ƒ Comes with on-chip loader, loading program to
on-chip flash via PC COM port

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 ‰ DS5000 from Dallas Semiconductor
OVERVIEW OF
8051 FAMILY ¾ NV-RAM (changed one byte at a time),
RTC (real-time clock)
Various 8051 ƒ Also comes with on-chip loader
Microcontrollers ‰ OTP (one-time-programmable) version
(cont’) of 8051
‰ 8051 family from Philips
¾ ADC, DAC, extended I/O, and both OTP
and flash

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 8051 ASSEMBLY
LANGUAGE
PROGRAMMING

The 8051 Microcontroller and Embedded

Systems: Using Assembly and C
Mazidi, Mazidi and McKinlay

Chung-Ping Young
楊中平

Home Automation, Networking, and Entertainment Lab

Dept. of Computer Science and Information Engineering
National Cheng Kung University, TAIWAN
 ‰ Register are used to store information
INSIDE THE
8051
temporarily, while the information
could be
Registers ¾ a byte of data to be processed, or
¾ an address pointing to the data to be
fetched
‰ The vast majority of 8051 register are
8-bit registers
¾ There is only one data type, 8 bits

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 ‰ The 8 bits of a register are shown from
INSIDE THE
8051
MSB D7 to the LSB D0
¾ With an 8-bit data type, any data larger
Registers than 8 bits must be broken into 8-bit
(cont’) chunks before it is processed
most least
significant bit significant bit

D7 D6 D5 D4 D3 D2 D1 D0

8 bit Registers

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 ‰ The most widely used registers
INSIDE THE
8051 ¾ A (Accumulator)
ƒ For all arithmetic and logic instructions
Registers ¾ B, R0, R1, R2, R3, R4, R5, R6, R7
(cont’) ¾ DPTR (data pointer), and PC (program
counter)
A
B
R0 DPTR DPH DPL
R1
R2
PC PC (Program counter)
R3
R4
R5
R6
R7

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 MOV destination, source ;copy source to dest.
INSIDE THE ¾ The instruction tells the CPU to move (in reality,
8051 COPY) the source operand to the destination
operand
MOV “#” signifies that it is a value
Instruction
MOV A,#55H ;load value 55H into reg. A
MOV R0,A ;copy contents of A into R0
;(now A=R0=55H)
MOV R1,A ;copy contents of A into R1
;(now A=R0=R1=55H)
MOV R2,A ;copy contents of A into R2
;(now A=R0=R1=R2=55H)
MOV R3,#95H ;load value 95H into R3
;(now R3=95H)
MOV A,R3 ;copy contents of R3 into A
;now A=R3=95H

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 ‰ Notes on programming
INSIDE THE ¾ Value (proceeded with #) can be loaded
8051 directly to registers A, B, or R0 – R7
ƒ MOV A, #23H
MOV ƒ MOV R5, #0F9H If it’s not preceded with #,
Instruction Add a 0 to indicate that
it means to load from a
memory location
(cont’) F is a hex number and
not a letter

¾ If values 0 to F moved into an 8-bit

register, the rest of the bits are assumed
all zeros
ƒ “MOV A, #5”, the result will be A=05; i.e., A
= 00000101 in binary
¾ Moving a value that is too large into a
register will cause an error
ƒ MOV A, #7F2H ; ILLEGAL: 7F2H>8 bits (FFH)
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 ADD A, source ;ADD the source operand
INSIDE THE ;to the accumulator
8051 ¾ The ADD instruction tells the CPU to add the source
byte to register A and put the result in register A
ADD ¾ Source operand can be either a register or
immediate data, but the destination must always
Instruction be register A
ƒ “ADD R4, A” and “ADD R2, #12H” are invalid
since A must be the destination of any arithmetic
operation
MOV A, #25H ;load 25H into A
MOV R2, #34H ;load 34H into R2
ADD A, R2 ;add R2 to Accumulator
There are always ;(A = A + R2)
many ways to write
the same program, MOV A, #25H ;load one operand
depending on the ;into A (A=25H)
registers used ADD A, #34H ;add the second
;operand 34H to A
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 ‰ In the early days of the computer,
8051 programmers coded in machine language,
ASSEMBLY consisting of 0s and 1s
PROGRAMMING ¾ Tedious, slow and prone to error
‰ Assembly languages, which provided
Structure of
mnemonics for the machine code instructions,
Assembly
plus other features, were developed
Language
¾ An Assembly language program consist of a series
of lines of Assembly language instructions
‰ Assembly language is referred to as a low-
level language
¾ It deals directly with the internal structure of the
CPU

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 ‰ Assembly language instruction includes
8051 ¾ a mnemonic (abbreviation easy to remember)
ASSEMBLY ƒ the commands to the CPU, telling it what those
PROGRAMMING to do with those items
¾ optionally followed by one or two operands
Structure of ƒ the data items being manipulated
Assembly
‰ A given Assembly language program is
Language
a series of statements, or lines
¾ Assembly language instructions
ƒ Tell the CPU what to do
¾ Directives (or pseudo-instructions)
ƒ Give directions to the assembler

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 ‰ An Assembly language instruction
8051
ASSEMBLY consists of four fields:
PROGRAMMING [label:] Mnemonic [operands] [;comment]

ORG 0H ;start(origin) at location

Structure of 0
MOV R5, #25H ;load 25H into R5
Assembly MOV R7, #34H ;load 34H into R7
Directives do not
Language MOV A, #0 ;load 0 into generate
A any machine
ADD A, R5 ;add contentscode
ofandR5aretoused
A
;now A = A + only
R5 by the assembler
Mnemonics ADD A, R7 ;add contents of R7 to A
produce ;now A = A + R7
opcodes ADD A, #12H ;add to A value 12H
;now A = A + 12H
HERE: SJMP HERE ;stay in this loop
END ;endComments
of asm may
source file
be at the end of a
The label field allows line or on a line by themselves
the program to refer to a The assembler ignores comments
line of code by name
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 ‰ The step of Assembly language
ASSEMBLING
AND RUNNING
program are outlines as follows:
AN 8051 1) First we use an editor to type a program,
PROGRAM many excellent editors or word
processors are available that can be used
to create and/or edit the program
ƒ Notice that the editor must be able to produce
an ASCII file
ƒ For many assemblers, the file names follow
the usual DOS conventions, but the source file
has the extension “asm“ or “src”, depending
on which assembly you are using

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 2) The “asm” source file containing the
ASSEMBLING program code created in step 1 is fed to
AND RUNNING an 8051 assembler
AN 8051 ƒ The assembler converts the instructions into
PROGRAM machine code
(cont’) ƒ The assembler will produce an object file and
a list file
ƒ The extension for the object file is “obj” while
the extension for the list file is “lst”
3) Assembler require a third step called
linking
ƒ The linker program takes one or more object
code files and produce an absolute object file
with the extension “abs”
ƒ This abs file is used by 8051 trainers that
have a monitor program

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 4) Next the “abs” file is fed into a program
ASSEMBLING called “OH” (object to hex converter)
AND RUNNING which creates a file with extension “hex”
AN 8051 that is ready to burn into ROM
PROGRAM ƒ This program comes with all 8051 assemblers
(cont’)
ƒ Recent Windows-based assemblers combine
step 2 through 4 into one step

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 EDITOR
PROGRAM
ASSEMBLING myfile.asm
AND RUNNING
AN 8051 ASSEMBLER
PROGRAM PROGRAM
myfile.lst
Other obj files
Steps to Create myfile.obj

a Program LINKER
PROGRAM

myfile.abs

OH
PROGRAM

myfile.hex
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 ‰ The lst (list) file, which is optional, is
ASSEMBLING
AND RUNNING
very useful to the programmer
AN 8051 ¾ It lists all the opcodes and addresses as
PROGRAM well as errors that the assembler detected
¾ The programmer uses the lst file to find
lst File the syntax errors or debug
1 0000 ORG 0H ;start (origin) at 0
2 0000 7D25 MOV R5,#25H ;load 25H into R5
3 0002 7F34 MOV R7,#34H ;load 34H into R7
4 0004 7400 MOV A,#0 ;load 0 into A
5 0006 2D ADD A,R5 ;add contents of R5 to A
;now A = A + R5
6 0007 2F ADD A,R7 ;add contents of R7 to A
;now A = A + R7
7 0008 2412 ADD A,#12H ;add to A value 12H
;now A = A + 12H
8 000A 80EF HERE: SJMP HERE;stay in this loop
9 000C END ;end of asm source file
address
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 ‰ The program counter points to the
PROGRAM
COUNTER AND
address of the next instruction to be
ROM SPACE executed
¾ As the CPU fetches the opcode from the
Program program ROM, the program counter is
Counter increasing to point to the next instruction
‰ The program counter is 16 bits wide
¾ This means that it can access program
addresses 0000 to FFFFH, a total of 64K
bytes of code

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 ‰ All 8051 members start at memory
PROGRAM
COUNTER AND
address 0000 when they’re powered
ROM SPACE up
¾ Program Counter has the value of 0000
Power up ¾ The first opcode is burned into ROM
address 0000H, since this is where the
8051 looks for the first instruction when it
is booted
¾ We achieve this by the ORG statement in
the source program

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 ‰ Examine the list file and how the code
PROGRAM is placed in ROM
COUNTER AND 1 0000 ORG 0H ;start (origin) at 0

ROM SPACE
2 0000 7D25 MOV R5,#25H ;load 25H into R5
3 0002 7F34 MOV R7,#34H ;load 34H into R7
4 0004 7400 MOV A,#0 ;load 0 into A
5 0006 2D ADD A,R5 ;add contents of R5 to A
Placing Code in ;now A = A + R5
6 0007 2F ADD A,R7 ;add contents of R7 to A
ROM ;now A = A + R7
7 0008 2412 ADD A,#12H ;add to A value 12H
;now A = A + 12H
8 000A 80EF HERE: SJMP HERE ;stay in this loop
9 000C END ;end of asm source file

ROM Address Machine Language Assembly Language

0000 7D25 MOV R5, #25H
0002 7F34 MOV R7, #34H
0004 7400 MOV A, #0
0006 2D ADD A, R5
0007 2F ADD A, R7
0008 2412 ADD A, #12H
000A 80EF HERE: SJMP HERE

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 ‰ After the program is burned into ROM,
PROGRAM
COUNTER AND
the opcode and operand are placed in
ROM SPACE ROM memory location starting at 0000
ROM contents
Address Code
Placing Code in
0000 7D
ROM 0001 25
(cont’) 0002 7F
0003 34
0004 74
0005 00
0006 2D
0007 2F
0008 24
0009 12
000A 80
000B FE

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 ‰ A step-by-step description of the
PROGRAM
COUNTER AND
action of the 8051 upon applying
ROM SPACE power on it
1. When 8051 is powered up, the PC has
Executing 0000 and starts to fetch the first opcode
Program from location 0000 of program ROM
ƒ Upon executing the opcode 7D, the CPU
fetches the value 25 and places it in R5
ƒ Now one instruction is finished, and then the
PC is incremented to point to 0002, containing
opcode 7F
2. Upon executing the opcode 7F, the value
34H is moved into R7
ƒ The PC is incremented to 0004

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 ‰ (cont’)
PROGRAM
COUNTER AND 3. The instruction at location 0004 is
ROM SPACE executed and now PC = 0006
4. After the execution of the 1-byte
Executing instruction at location 0006, PC = 0007
Program 5. Upon execution of this 1-byte instruction
(cont’) at 0007, PC is incremented to 0008
ƒ This process goes on until all the instructions
are fetched and executed
ƒ The fact that program counter points at the
next instruction to be executed explains some
microprocessors call it the instruction pointer

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 ‰ No member of 8051 family can access
PROGRAM
COUNTER AND
more than 64K bytes of opcode
ROM SPACE ¾ The program counter is a 16-bit register

ROM Memory Byte Byte Byte

Map in 8051 0000 0000 0000

Family
0FFF
8751
AT89C51 3FFF
DS89C420/30

7FFF
DS5000-32

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 ‰ 8051 microcontroller has only one data
8051 DATA
TYPES AND
type - 8 bits
DIRECTIVES ¾ The size of each register is also 8 bits
¾ It is the job of the programmer to break
Data Type down data larger than 8 bits (00 to FFH,
or 0 to 255 in decimal)
¾ The data types can be positive or negative

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 ‰ The DB directive is the most widely
8051 DATA
TYPES AND
used data directive in the assembler
DIRECTIVES ¾ It is used to define the 8-bit data
¾ When DB is used to define data, the
Assembler numbers can be in decimal, binary, hex,
The “D” after the decimal
Directives ASCII formats number is optional, but using
“B” (binary) and “H”
ORG 500H (hexadecimal) for the others is
required
DATA1: DB 28 ;DECIMAL (1C in Hex)
DATA2: DB 00110101B ;BINARY (35 in Hex)
DATA3: DB 39H ;HEX
The Assembler will ORG 510H Place ASCII in quotation marks
convert the numbers DATA4: DB “2591” The;ASCII
AssemblerNUMBERS
will assign ASCII
into hex code for the numbers or characters
ORG 518H
DATA6: DB “My name is Joe”
Define ASCII strings larger ;ASCII CHARACTERS
than two characters

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 ‰ ORG (origin)
8051 DATA ¾ The ORG directive is used to indicate the
TYPES AND beginning of the address
DIRECTIVES ¾ The number that comes after ORG can be
either in hex and decimal
Assembler ƒ If the number is not followed by H, it is decimal
Directives and the assembler will convert it to hex
(cont’) ‰ END
¾ This indicates to the assembler the end of
the source (asm) file
¾ The END directive is the last line of an
8051 program
ƒ Mean that in the code anything after the END
directive is ignored by the assembler

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 ‰ EQU (equate)
8051 DATA
TYPES AND ¾ This is used to define a constant without
DIRECTIVES occupying a memory location
¾ The EQU directive does not set aside
Assembler storage for a data item but associates a
directives constant value with a data label
(cont’) ƒ When the label appears in the program, its
constant value will be substituted for the label

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 ‰ EQU (equate) (cont’)
8051 DATA
TYPES AND ¾ Assume that there is a constant used in
DIRECTIVES many different places in the program, and
the programmer wants to change its value
Assembler throughout
ƒ By the use of EQU, one can change it once and
directives
the assembler will change all of its occurrences
(cont’)
Use EQU for the
counter constant

COUNT EQU 25
... ....
MOV R3, #COUNT

The constant is used to

load the R3 register

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 ‰ The program status word (PSW)
FLAG BITS AND
PSW REGISTER
register, also referred to as the flag
register, is an 8 bit register
Program Status ¾ Only 6 bits are used
Word ƒ These four are CY (carry), AC (auxiliary carry), P
(parity), and OV (overflow)
– They are called conditional flags, meaning
that they indicate some conditions that
resulted after an instruction was executed
ƒ The PSW3 and PSW4 are designed as RS0 and
RS1, and are used to change the bank
¾ The two unused bits are user-definable

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 CY AC F0 RS1 RS0 OV -- P
FLAG BITS AND A carry from D3 to D4
CY PSW.7 Carry flag.
PSW REGISTER
AC PSW.6 Auxiliary carry flag. Carry out from the d7 bit
-- PSW.5 Available to the user for general purpose
Program Status RS1 PSW.4 Register Bank selector bit 1.
Word (cont’) RS0 PSW.3 Register Bank selector bit 0.
OV PSW.2 Overflow flag.
Reflect the number of 1s
The result of -- PSW.1 User definable bit. in register A
signed number P PSW.0 Parity flag. Set/cleared by hardware each
operation is too instruction cycle to indicate an odd/even
large, causing number of 1 bits in the accumulator.
the high-order
bit to overflow RS1 RS0 Register Bank Address
into the sign bit
0 0 0 00H – 07H
0 1 1 08H – 0FH
1 0 2 10H – 17H
1 1 3 18H – 1FH

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 Instructions that affect flag bits
FLAG BITS AND Instruction CY OV AC
PSW REGISTER ADD X X X
ADDC X X X

ADD SUBB X X X
MUL 0 X
Instruction And DIV 0 X
PSW DA X
RPC X
PLC X
SETB C 1
CLR C 0
CPL C X
ANL C, bit X
ANL C, /bit X
ORL C, bit X
ORL C, /bit X
MOV C, bit X
CJNE X

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 ‰ The flag bits affected by the ADD
FLAG BITS AND
PSW REGISTER
instruction are CY, P, AC, and OV
Example 2-2

ADD Show the status of the CY, AC and P flag after the addition of 38H
and 2FH in the following instructions.
Instruction And
PSW MOV A, #38H
(cont’) ADD A, #2FH ;after the addition A=67H, CY=0
Solution:
38 00111000
+ 2F 00101111
67 01100111
CY = 0 since there is no carry beyond the D7 bit
AC = 1 since there is a carry from the D3 to the D4 bi
P = 1 since the accumulator has an odd number of 1s (it has five 1s)
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 Example 2-3
FLAG BITS AND
Show the status of the CY, AC and P flag after the addition of 9CH
PSW REGISTER and 64H in the following instructions.
MOV A, #9CH
ADD ADD A, #64H ;after the addition A=00H, CY=1
Instruction And
Solution:
PSW
(cont’) 9C 10011100
+ 64 01100100
100 00000000
CY = 1 since there is a carry beyond the D7 bit
AC = 1 since there is a carry from the D3 to the D4 bi
P = 0 since the accumulator has an even number of 1s (it has zero 1s)

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 Example 2-4
FLAG BITS AND
Show the status of the CY, AC and P flag after the addition of 88H
PSW REGISTER and 93H in the following instructions.
MOV A, #88H
ADD
ADD A, #93H ;after the addition A=1BH, CY=1
Instruction And
PSW Solution:
(cont’) 88 10001000
+ 93 10010011
11B 00011011
CY = 1 since there is a carry beyond the D7 bit
AC = 0 since there is no carry from the D3 to the D4 bi
P = 0 since the accumulator has an even number of 1s (it has four 1s)

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 ‰ There are 128 bytes of RAM in the
REGISTER 8051
BANKS AND
¾ Assigned addresses 00 to 7FH
STACK
‰ The 128 bytes are divided into three
RAM Memory different groups as follows:
Space 1) A total of 32 bytes from locations 00 to
Allocation 1F hex are set aside for register banks
and the stack
2) A total of 16 bytes from locations 20H to
2FH are set aside for bit-addressable
read/write memory
3) A total of 80 bytes from locations 30H to
7FH are used for read and write storage,
called scratch pad

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 RAM Allocation in 8051

8051 7F

REGISTER Scratch pad RAM

BANKS AND 30
STACK 2F
Bit-Addressable RAM

RAM Memory 20
Space 1F
Allocation
Register Bank 3
18
(cont’) 17 Register Bank 2
10
0F
Register Bank 1 (stack)
08
07
Register Bank 0

00

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 ‰ These 32 bytes are divided into 4
8051
REGISTER
banks of registers in which each bank
BANKS AND has 8 registers, R0-R7
STACK ¾ RAM location from 0 to 7 are set aside for
bank 0 of R0-R7 where R0 is RAM location
Register Banks 0, R1 is RAM location 1, R2 is RAM
location 2, and so on, until memory
location 7 which belongs to R7 of bank 0
¾ It is much easier to refer to these RAM
locations with names such as R0, R1, and
so on, than by their memory locations
‰ Register bank 0 is the default when
8051 is powered up

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 8051 Register banks and their RAM address
REGISTER Bank 3
Bank 0 Bank 1 Bank 2
BANKS AND
STACK 7 R7 F R7 17 R7 1F R7

6 R6 E R6 16 R6 1E R6

Register Banks 5 R5 D R5 15 R5 1D R5

(cont’) 4 R4 C R4 14 R4 1C R4

3 R3 B R3 13 R3 1B R3

2 R2 A R2 12 R2 1A R2

1 R1 9 R1 11 R1 19 R1

0 R0 8 R0 10 R0 18 R0

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 ‰ We can switch to other banks by use
8051
REGISTER
of the PSW register
BANKS AND ¾ Bits D4 and D3 of the PSW are used to
STACK select the desired register bank
¾ Use the bit-addressable instructions SETB
Register Banks and CLR to access PSW.4 and PSW.3
(cont’)
PSW bank selection
RS1(PSW.4) RS0(PSW.3)
Bank 0 0 0
Bank 1 0 1
Bank 2 1 0
Bank 3 1 1

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 Example 2-5
8051
MOV R0, #99H ;load R0 with 99H
REGISTER MOV R1, #85H ;load R1 with 85H
BANKS AND
STACK
Example 2-6

Register Banks MOV 00, #99H ;RAM location 00H has 99H
MOV 01, #85H ;RAM location 01H has 85H
(cont’)

Example 2-7
SETB PSW.4 ;select bank 2
MOV R0, #99H ;RAM location 10H has 99H
MOV R1, #85H ;RAM location 11H has 85H

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 ‰ The stack is a section of RAM used by
8051 the CPU to store information
REGISTER temporarily
BANKS AND
¾ This information could be data or an
STACK
address
Stack ‰ The register used to access the stack
is called the SP (stack pointer) register
¾ The stack pointer in the 8051 is only 8 bit
wide, which means that it can take value
of 00 to FFH
¾ When the 8051 is powered up, the SP
register contains value 07
ƒ RAM location 08 is the first location begin used
for the stack by the 8051

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 ‰ The storing of a CPU register in the
8051
stack is called a PUSH
REGISTER
BANKS AND ¾ SP is pointing to the last used location of
STACK the stack
¾ As we push data onto the stack, the SP is
Stack incremented by one
(cont’) ƒ This is different from many microprocessors
‰ Loading the contents of the stack back
into a CPU register is called a POP
¾ With every pop, the top byte of the stack
is copied to the register specified by the
instruction and the stack pointer is
decremented once

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 Example 2-8
8051
Show the stack and stack pointer from the following. Assume the
REGISTER default stack area.
BANKS AND MOV R6, #25H
STACK MOV R1, #12H
MOV R4, #0F3H
PUSH 6
Pushing onto PUSH 1
Stack PUSH 4
Solution:
After PUSH 6 After PUSH 1 After PUSH 4
0B 0B 0B 0B
0A 0A 0A 0A F3
09 09 09 12 09 12
08 08 25 08 25 08 25
Start SP = 07 SP = 08 SP = 09 SP = 0A

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 Example 2-9
8051
Examining the stack, show the contents of the register and SP after
REGISTER execution of the following instructions. All value are in hex.
BANKS AND POP 3 ; POP stack into R3
STACK POP 5 ; POP stack into R5
POP 2 ; POP stack into R2

Popping From Solution:

Stack
After POP 3 After POP 5 After POP 2
0B 54 0B 0B 0B
0A F9 0A F9 0A 0A
09 76 09 76 09 76 09
08 6C 08 6C 08 6C 08 6C
Start SP = 0B SP = 0A SP = 09 SP = 08
Because locations 20-2FH of RAM are reserved
for bit-addressable memory, so we can change the
SP to other RAM location by using the instruction
“MOV SP, #XX”
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 ‰ The CPU also uses the stack to save
8051
REGISTER
the address of the instruction just
BANKS AND below the CALL instruction
STACK ¾ This is how the CPU knows where to
resume when it returns from the called
CALL subroutine
Instruction And
Stack

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 ‰ The reason of incrementing SP after
8051
REGISTER
push is
BANKS AND ¾ Make sure that the stack is growing
STACK toward RAM location 7FH, from lower to
upper addresses
Incrementing ¾ Ensure that the stack will not reach the
Stack Pointer bottom of RAM and consequently run out
of stack space
¾ If the stack pointer were decremented
after push
ƒ We would be using RAM locations 7, 6, 5, etc.
which belong to R7 to R0 of bank 0, the default
register bank

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 ‰ When 8051 is powered up, register
8051
REGISTER
bank 1 and the stack are using the
BANKS AND same memory space
STACK ¾ We can reallocate another section of RAM
to the stack
Stack and Bank
1 Conflict

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 Example 2-10
8051 Examining the stack, show the contents of the register and SP after
REGISTER execution of the following instructions. All value are in hex.
BANKS AND MOV SP, #5FH ;make RAM location 60H
STACK
;first stack location
MOV R2, #25H
MOV R1, #12H

Stack And Bank

MOV R4, #0F3H
PUSH 2
1 Conflict PUSH 1
(cont’) PUSH 4

Solution:
After PUSH 2 After PUSH 1 After PUSH 4
63 63 63 63
62 62 62 62 F3
61 61 61 12 61 12
60 60 25 60 25 60 25
Start SP = 5F SP = 60 SP = 61 SP = 62

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 JUMP, LOOP AND CALL
INSTRUCTIONS

The 8051 Microcontroller and Embedded

Systems: Using Assembly and C
Mazidi, Mazidi and McKinlay

Chung-Ping Young
楊中平

Home Automation, Networking, and Entertainment Lab

Dept. of Computer Science and Information Engineering
National Cheng Kung University, TAIWAN
 ‰ Repeating a sequence of instructions a
LOOP AND certain number of times is called a
JUMP loop
INSTRUCTIONS
¾ Loop action is performed by
DJNZ reg, Label
Looping
ƒ The register is decremented
ƒ If it is not zero, it jumps to the target address
referred to by the label
A loop can be repeated a ƒ Prior to the start of loop the register is loaded
maximum of 255 times, if with the counter for the number of repetitions
R2 is FFH
ƒ Counter can be R0 – R7 or RAM location
;This program adds value 3 to the ACC ten times
MOV A,#0 ;A=0, clear ACC
MOV R2,#10 ;load counter R2=10
AGAIN: ADD A,#03 ;add 03 to ACC
DJNZ R2,AGAIN ;repeat until R2=0,10 times
MOV R5,A ;save A in R5

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 ‰ If we want to repeat an action more
LOOP AND
JUMP
times than 256, we use a loop inside a
INSTRUCTIONS loop, which is called nested loop
¾ We use multiple registers to hold the
Nested Loop count

Write a program to (a) load the accumulator with the value 55H, and
(b) complement the ACC 700 times

MOV A,#55H ;A=55H

MOV R3,#10 ;R3=10, outer loop count
NEXT: MOV R2,#70 ;R2=70, inner loop count
AGAIN: CPL A ;complement A register
DJNZ R2,AGAIN ;repeat it 70 times
DJNZ R3,NEXT

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 ‰ Jump only if a certain condition is met
LOOP AND JZ label ;jump if A=0
JUMP MOV A,R0 ;A=R0
INSTRUCTIONS JZ OVER ;jump if A = 0
MOV A,R1 ;A=R1
JZ OVER ;jump if A = 0
Conditional ...
Jumps OVER: Can be used only for register A,
not any other register

Determine if R5 contains the value 0. If so, put 55H in it.

MOV A,R5 ;copy R5 to A
JNZ NEXT ;jump if A is not zero
MOV R5,#55H
NEXT: ...

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 ‰ (cont’)
LOOP AND JNC label ;jump if no carry, CY=0
JUMP ¾ If CY = 0, the CPU starts to fetch and execute
INSTRUCTIONS instruction from the address of the label
¾ If CY = 1, it will not jump but will execute the next
Conditional instruction below JNC
Jumps Find the sum of the values 79H, F5H, E2H. Put the sum in registers
(cont’) R0 (low byte) and R5 (high byte).
MOV R5,#0
MOV A,#0 ;A=0
MOV R5,A ;clear R5
ADD A,#79H ;A=0+79H=79H
; JNC N_1 ;if CY=0, add next number
; INC R5 ;if CY=1, increment R5
N_1: ADD A,#0F5H ;A=79+F5=6E and CY=1
JNC N_2 ;jump if CY=0
INC R5 ;if CY=1,increment R5 (R5=1)
N_2: ADD A,#0E2H ;A=6E+E2=50 and CY=1
JNC OVER ;jump if CY=0
INC R5 ;if CY=1, increment 5
OVER: MOV R0,A ;now R0=50H, and R5=02
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 8051 conditional jump instructions
LOOP AND Instructions Actions
JUMP JZ Jump if A ＝ 0
INSTRUCTIONS JNZ Jump if A ≠ 0
DJNZ Decrement and Jump if A ≠ 0
Conditional CJNE A,byte Jump if A ≠ byte
Jump if byte ≠ #data
Jumps CJNE reg,#data
(cont’) JC Jump if CY ＝ 1
JNC Jump if CY ＝ 0
JB Jump if bit ＝ 1
JNB Jump if bit ＝ 0
JBC Jump if bit ＝ 1 and clear bit

‰ All conditional jumps are short jumps

¾ The address of the target must within
-128 to +127 bytes of the contents of PC

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 The unconditional jump is a jump in
‰
LOOP AND which control is transferred
JUMP unconditionally to the target location
INSTRUCTIONS
LJMP (long jump)
Unconditional ¾ 3-byte instruction
Jumps ƒ First byte is the opcode
ƒ Second and third bytes represent the 16-bit
target address
– Any memory location from 0000 to FFFFH
SJMP (short jump)
¾ 2-byte instruction
ƒ First byte is the opcode
ƒ Second byte is the relative target address
– 00 to FFH (forward +127 and backward
-128 bytes from the current PC)

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 ‰ To calculate the target address of a
LOOP AND
JUMP
short jump (SJMP, JNC, JZ, DJNZ, etc.)
INSTRUCTIONS ¾ The second byte is added to the PC of the
instruction immediately below the jump
Calculating ‰ If the target address is more than -128
Short Jump to +127 bytes from the address below
Address
the short jump instruction
¾ The assembler will generate an error
stating the jump is out of range

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 Line PC Opcode Mnemonic Operand
LOOP AND 01 0000 ORG 0000
JUMP 02 0000 7800 MOV R0,#0
03 0002 7455 MOV A,#55H
INSTRUCTIONS 04 0004 6003 JZ NEXT
05 0006 08 INC R0
Calculating 06 0007 04
+ AGAIN: INC A
07 0008 04 INC A
Short Jump 08 0009 2477 NEXT: ADD A,#77H
Address 09 000B 5005 JNC OVER
(cont’) 10 000D E4 CLR A
11 000E F8 MOV R0,A
12 000F F9
+ MOV R1,A
13 0010 FA MOV R2,A
14 0011 FB MOV R3,A
15 0012 2B OVER: ADD A,R3
16 0013 50F2 JNC AGAIN
17 0015 80FE + HERE: SJMP HERE
18 0017 END

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 ‰ Call instruction is used to call subroutine
CALL
¾ Subroutines are often used to perform tasks
INSTRUCTIONS that need to be performed frequently
¾ This makes a program more structured in
addition to saving memory space
LCALL (long call)
¾ 3-byte instruction
ƒ First byte is the opcode
ƒ Second and third bytes are used for address of
target subroutine
– Subroutine is located anywhere within 64K
byte address space
ACALL (absolute call)
¾ 2-byte instruction
ƒ 11 bits are used for address within 2K-byte range

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 ‰ When a subroutine is called, control is
CALL
INSTRUCTIONS
transferred to that subroutine, the
processor
LCALL ¾ Saves on the stack the the address of the
instruction immediately below the LCALL
¾ Begins to fetch instructions form the new
location
‰ After finishing execution of the
subroutine
¾ The instruction RET transfers control back
to the caller
ƒ Every subroutine needs RET as the last
instruction

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 ORG 0
BACK: MOV A,#55H ;load A with 55H
CALL MOV P1,A ;send 55H to port 1
INSTRUCTIONS LCALL
MOV
DELAY
A,#0AAH
;time
;load
delay
A with AA (in hex)
MOV P1,A ;send AAH to port 1
LCALL LCALL
SJMP
DELAY
BACK ;keep doing this indefinitely
(cont’) Upon executing “LCALL DELAY”,
the address of instruction below it,
The counter R5 is set to “MOV A,#0AAH” is pushed onto
FFH; so loop is repeated stack, and the 8051 starts to execute
255 times.
at 300H.
;---------- this is delay subroutine ------------
ORG 300H ;put DELAY at address 300H
DELAY: MOV R5,#0FFH ;R5=255 (FF in hex), counter
AGAIN: DJNZ R5,AGAIN ;stay here until R5 become 0
RET ;return to caller (when R5 =0)
END ;end of asm file
When R5 becomes 0, control falls to the
The amount of time delay depends RET which pops the address from the stack
on the frequency of the 8051 into the PC and resumes executing the
instructions after the CALL.
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 001 0000 ORG 0
002 0000 7455 BACK: MOV A,#55H ;load A with 55H
CALL 003 0002 F590 MOV P1,A ;send 55H to p1
INSTRUCTIONS 004
005
0004
0007
120300
74AA
LCALL DELAY
MOV A,#0AAH
;time
;load
delay
A with AAH
006 0009 F590 MOV P1,A ;send AAH to p1
CALL 007
008
000B
000E
120300
80F0
LCALL DELAY
SJMP BACK ;keep doing this
Instruction and 009 0010
Stack 010
011
0010
0300
;-------this is the delay subroutine------
ORG 300H
012 0300 DELAY:
013 0300 7DFF MOV R5,#0FFH ;R5=255
014 0302 DDFE AGAIN: DJNZ R5,AGAIN ;stay here
015 0304 22 RET ;return to caller
016 0305 END ;end of asm file

Stack frame after the first LCALL

0A
09 00 Low byte goes first
and high byte is last
08 07
SP = 09
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 01 0000 ORG 0
02 0000 7455 BACK: MOV A,#55H ;load A with 55H
03 0002 F590 MOV P1,A ;send 55H to p1
CALL 04 0004 7C99 MOV R4,#99H
05 0006 7D67 MOV R5,#67H
INSTRUCTIONS 06 0008 120300 LCALL DELAY ;time delay
07 000B 74AA MOV A,#0AAH ;load A with AA
08 000D F590 MOV P1,A ;send AAH to p1
Use PUSH/POP 09 000F 120300 LCALL DELAY
in Subroutine
10 0012 80EC SJMP BACK ;keeping doing
this
11 0014 ;-------this is the delay subroutine------
12 0300 ORG 300H
13 0300 C004 DELAY: PUSH 4 ;push R4
14 0302 C005 PUSH 5 ;push R5
Normally, the 15 0304 7CFF MOV R4,#0FFH;R4=FFH
number of PUSH 16 0306 7DFF NEXT: MOV R5,#0FFH;R5=FFH
and POP 17 0308 DDFE AGAIN: DJNZ R5,AGAIN
instructions must 18 030A DCFA DJNZ R4,NEXT
19 030C D005 POP 5 ;POP into R5
always match in any
20 030E D004 POP 4 ;POP into R4
called subroutine 21 0310 22 RET ;return to caller
22 0311 After first LCALL After PUSH 4
END After of
;end PUSH 5 file
asm
0B 0B 0B 67 R5
0A 0A 99 R4 0A 99 R4
09 00 PCH 09 00 PCH 09 00 PCH
Department08of Computer
0B PCLScience
08 and 0B Information
PCL 08 Engineering
0B PCL
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 ;MAIN program calling subroutines
ORG 0
CALL MAIN: LCALL SUBR_1 It is common to have one
INSTRUCTIONS LCALL
LCALL
SUBR_2
SUBR_3
main program and many
subroutines that are called
from the main program
Calling
HERE: SJMP HERE
;-----------end of MAIN
Subroutines SUBR_1: ...
... This allows you to make
RET each subroutine into a
;-----------end of subroutine1 separate module
- Each module can be
SUBR_2: ...
... tested separately and then
RET brought together with
;-----------end of subroutine2 main program
- In a large program, the
SUBR_3: ... module can be assigned to
... different programmers
RET
;-----------end of subroutine3
END ;end of the asm file

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 ‰ The only difference between ACALL
CALL
and LCALL is
INSTRUCTIONS
¾ The target address for LCALL can be
ACALL anywhere within the 64K byte address
¾ The target address of ACALL must be
within a 2K-byte range
‰ The use of ACALL instead of LCALL
can save a number of bytes of
program ROM space

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 ORG 0
CALL BACK: MOV
MOV
A,#55H
P1,A
;load
;send
A with
55H to
55H
port 1
INSTRUCTIONS LCALL DELAY ;time delay
MOV A,#0AAH ;load A with AA (in hex)
MOV P1,A ;send AAH to port 1
ACALL LCALL DELAY
(cont’) SJMP BACK ;keep doing this indefinitely
...
END ;end of asm file

A rewritten program which is more efficiently

ORG 0
MOV A,#55H ;load A with 55H
BACK: MOV P1,A ;send 55H to port 1
ACALL DELAY ;time delay
CPL A ;complement reg A
SJMP BACK ;keep doing this indefinitely
...
END ;end of asm file

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 ‰ CPU executing an instruction takes a
TIME DELAY
FOR VARIOUS
certain number of clock cycles
8051 CHIPS ¾ These are referred as to as machine cycles
‰ The length of machine cycle depends
on the frequency of the crystal
oscillator connected to 8051
‰ In original 8051, one machine cycle
lasts 12 oscillator periods
Find the period of the machine cycle for 11.0592 MHz crystal
frequency

Solution:
11.0592/12 = 921.6 kHz;
machine cycle is 1/921.6 kHz = 1.085μs

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 For 8051 system of 11.0592 MHz, find how long it takes to execute
TIME DELAY each instruction.
(a) MOV R3,#55 (b) DEC R3 (c) DJNZ R2 target
FOR VARIOUS (d) LJMP (e) SJMP (f) NOP (g) MUL AB
8051 CHIPS
(cont’) Solution:
Machine cycles Time to execute
(a) 1 1x1.085μs ＝ 1.085μs
(b) 1 1x1.085μs ＝ 1.085μs
(c) 2 2x1.085μs ＝ 2.17μs
(d) 2 2x1.085μs ＝ 2.17μs
(e) 2 2x1.085μs ＝ 2.17μs
(f) 1 1x1.085μs ＝ 1.085μs
(g) 4 4x1.085μs ＝ 4.34μs

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 Find the size of the delay in following program, if the crystal
TIME DELAY frequency is 11.0592MHz.
FOR VARIOUS
8051 CHIPS MOV A,#55H
AGAIN: MOV P1,A
ACALL DELAY
Delay CPL A
Calculation SJMP AGAIN A simple way to short jump
to itself in order to keep the
;---time delay-------
DELAY: MOV R3,#200 microcontroller busy
HERE: DJNZ R3,HERE HERE: SJMP HERE
RET We can use the following:
SJMP $
Solution:
Machine cycle
DELAY: MOV R3,#200 1
HERE: DJNZ R3,HERE 2
RET 2
Therefore, [(200x2)+1+2]x1.085μs ＝ 436.255μs.

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 Find the size of the delay in following program, if the crystal
TIME DELAY frequency is 11.0592MHz.
FOR VARIOUS
8051 CHIPS Machine Cycle
DELAY: MOV R3,#250 1
HERE: NOP 1
Increasing NOP 1
Delay Using NOP 1
NOP 1
NOP DJNZ R3,HERE 2
RET 2

Solution:
The time delay inside HERE loop is
[250(1+1+1+1+2)]x1.085μs ＝ 1627.5μs.
Adding the two instructions outside loop we
have 1627.5μs + 3 x 1.085μs ＝ 1630.755μs

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 Find the size of the delay in following program, if the crystal
TIME DELAY frequency is 11.0592MHz.
FOR VARIOUS Machine Cycle
8051 CHIPS DELAY: MOV R2,#200 1
Notice in nested loop,
AGAIN: MOV R3,#250 1
as in all other time
Large Delay HERE: NOP
NOP
1
1
delay loops, the time
Using Nested DJNZ R3,HERE 2
is approximate since
we have ignored the
Loop DJNZ R2,AGAIN 2
first and last
RET 2
instructions in the
subroutine.
Solution:
For HERE loop, we have (4x250)x1.085μs＝1085μs.
For AGAIN loop repeats HERE loop 200 times, so
we have 200x1085μs＝217000μs. But “MOV
R3,#250” and “DJNZ R2,AGAIN” at the start and
end of the AGAIN loop add (3x200x1.805)=651μs.
As a result we have 217000+651=217651μs.

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 ‰ Two factors can affect the accuracy of
TIME DELAY the delay
FOR VARIOUS
¾ Crystal frequency
8051 CHIPS
ƒ The duration of the clock period of the machine
cycle is a function of this crystal frequency
Delay ¾ 8051 design
Calculation for ƒ The original machine cycle duration was set at
Other 8051 12 clocks
ƒ Advances in both IC technology and CPU
design in recent years have made the 1-clock
machine cycle a common feature
Clocks per machine cycle for various 8051 versions
Chip/Maker Clocks per Machine Cycle
AT89C51 Atmel 12
P89C54X2 Philips 6
DS5000 Dallas Semi 4
DS89C420/30/40/50 Dallas Semi 1
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 Find the period of the machine cycle (MC) for various versions of
TIME DELAY 8051, if XTAL=11.0592 MHz.
(a) AT89C51 (b) P89C54X2 (c) DS5000 (d) DS89C4x0
FOR VARIOUS
8051 CHIPS Solution:
(a) 11.0592MHz/12 = 921.6kHz;
MC is 1/921.6kHz = 1.085μs ＝ 1085ns
Delay (b) 11.0592MHz/6 = 1.8432MHz;
MC is 1/1.8432MHz = 0.5425μs ＝ 542ns
Calculation for (c) 11.0592MHz/4 = 2.7648MHz ;
Other 8051 MC is 1/2.7648MHz = 0.36μs ＝ 360ns
(cont’) (d) 11.0592MHz/1 = 11.0592MHz;
MC is 1/11.0592MHz = 0.0904μs ＝ 90ns

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 Instruction 8051 DSC89C4x0
MOV R3,#55 1 2
TIME DELAY DEC R3 1 1
FOR VARIOUS DJNZ R2 target 2 4
LJMP 2 3
8051 CHIPS SJMP 2 3
NOP 1 1
Delay MUL AB 4 9
Calculation for For an AT8051 and DSC89C4x0 system of 11.0592 MHz, find how
Other 8051 long it takes to execute each instruction.
(a) MOV R3,#55 (b) DEC R3 (c) DJNZ R2 target
(cont’) (d) LJMP (e) SJMP (f) NOP (g) MUL AB

Solution:
AT8051 DS89C4x0
(a) 1¯1085ns ＝ 1085ns 2¯90ns = 180ns
(b) 1¯1085ns ＝ 1085ns 1¯90ns = 90ns
(c) 2¯1085ns ＝ 2170ns 4¯90ns = 360ns
(d) 2¯1085ns ＝ 2170ns 3¯90ns = 270ns
(e) 2¯1085ns ＝ 2170ns 3¯90ns = 270ns
(f) 1¯1085ns ＝ 1085ns 1¯90ns = 90ns
(g) 4¯1085ns ＝ 4340ns 9¯90ns = 810ns
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 I/O PORT
PROGRAMMING

The 8051 Microcontroller and Embedded

Systems: Using Assembly and C
Mazidi, Mazidi and McKinlay

Chung-Ping Young
楊中平

Home Automation, Networking, and Entertainment Lab

Dept. of Computer Science and Information Engineering
National Cheng Kung University, TAIWAN
 Provides
+5V supply
I/O voltage to
PROGRAMMING 8051 Pin Diagram the chip
P1.0 1 40 Vcc
A total of 32 P1.1 2 39 P0.0 (AD0)
pins are set P1.2 3 38 P0.1 (AD1)
P1.3 4 37 P0.2 (AD2)
aside for the P1 P1.4 5 36 P0.3 (AD3)
four ports P0, P1.5 6 35 P0.4 (AD4) P0
P1.6 7 34 P0.5 (AD5)
P1, P2, P3, P1.7 8 8051 33 P0.6 (AD6)
where each RST 9 32 P0.7 (AD7)
port takes 8 (RXD) P3.0 10
(8031) 31 -EA/VPP
(TXD) P3.1 30 ALE/PROG
pins (-INT0) P3.2
11
12
(89420) 29 -PSEN
(-INT1) P3.3 13 28 P2.7 (A15)
P3 (T0) P3.4 14 27 P2.6 (A14)
(T1) P3.5 15 26 P2.5 (A13)
(-WR) P3.6 16 25 P2.4 (A12)
(-RD )P3.7 17 24 P2.3 (A11) P2
XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)
Grond

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 ‰ The four 8-bit I/O ports P0, P1, P2 and
I/O
PROGRAMMING
P3 each uses 8 pins
‰ All the ports upon RESET are
I/O Port Pins configured as input, ready to be used
as input ports
¾ When the first 0 is written to a port, it
becomes an output
P1.0
P1.1
1
2
40
39
Vcc
P0.0(AD0)
¾ To reconfigure it as an input, a 1 must be
sent to the port
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6
P1.7
7
8
34
33
32
P0.5(AD5)
P0.6(AD6) ƒ To use any of these ports as an input port, it
RST 9 P0.7(AD7)
(RXD)P3.0
(TXD)P3.1
10
8051 31
11(8031)30
-EA/VPP
ALE/PROG must be programmed
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

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 ‰ It can be used for input or output,
I/O
PROGRAMMING
each pin must be connected externally
to a 10K ohm pull-up resistor
Port 0 ¾ This is due to the fact that P0 is an open
drain, unlike P1, P2, and P3
ƒ Open drain is a term used for MOS chips in the
same way that open collector is used for TTL
chips
Vcc
P1.0
P1.1
1
2
40
39
Vcc
P0.0(AD0) 10 K
P1.2
P1.3
3
4
38
37
P0.1(AD1)
P0.2(AD2) P0.X
P1.4 5 36 P0.3(AD3) P0.0
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5) P0.1
33 P0.6(AD6)

Port 0
P1.7 8 P0.2
RST 9 32
8051 31 P0.7(AD7) 8051
(RXD)P3.0 10 -EA/VPP P0.3
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2 12 29 -PSEN P0.4
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14) P0.5
(T1)P3.5 15 26 P2.5(A13) P0.6
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11) P0.7
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

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 The following code will continuously send out to port 0 the
I/O alternating value 55H and AAH
PROGRAMMING BACK: MOV A,#55H
MOV P0,A
Port 0 ACALL DELAY
(cont’) MOV A,#0AAH
MOV P0,A
ACALL DELAY
SJMP BACK

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

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 ‰ In order to make port 0 an input, the
I/O port must be programmed by writing 1
PROGRAMMING
to all the bits
Port 0 as Input Port 0 is configured first as an input port by writing 1s to it, and then
data is received from that port and sent to P1
MOV A,#0FFH ;A=FF hex
MOV P0,A ;make P0 an i/p port
;by writing it all 1s
BACK: MOV A,P0 ;get data from P0
P1.0 1 40 Vcc
P1.1
P1.2
2
3
39
38
P0.0(AD0)
P0.1(AD1)
MOV P1,A ;send it to port 1
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3) SJMP BACK ;keep doing it
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

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 ‰ Port 0 is also designated as AD0-AD7,
I/O
PROGRAMMING
allowing it to be used for both address
and data
Dual Role of ¾ When connecting an 8051/31 to an
Port 0 external memory, port 0 provides both
address and data

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

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 ‰ Port 1 can be used as input or output
I/O
PROGRAMMING ¾ In contrast to port 0, this port does not
need any pull-up resistors since it already
Port 1 has pull-up resistors internally
¾ Upon reset, port 1 is configured as an
input port
The following code will continuously send out to port 0 the
alternating value 55H and AAH
P1.0 1 40 Vcc
P1.1
P1.2
2
3
39
38
P0.0(AD0)
P0.1(AD1)
MOV A,#55H
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3) BACK: MOV P1,A
P1.5 6 35 P0.4(AD4)
P1.6
P1.7
7
8
34
33
P0.5(AD5)
P0.6(AD6)
ACALL DELAY
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP CPL A
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2
(INT1)P3.3
12
13
29
28
-PSEN
P2.7(A15)
SJMP BACK
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

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 ‰ To make port 1 an input port, it must
I/O
PROGRAMMING
be programmed as such by writing 1
to all its bits
Port 1 as Input Port 1 is configured first as an input port by writing 1s to it, then data
is received from that port and saved in R7 and R5
MOV A,#0FFH ;A=FF hex
MOV P1,A ;make P1 an input port
;by writing it all 1s
MOV A,P1 ;get data from P1
P1.0 1 40 Vcc
P1.1 2
3
39
38
P0.0(AD0)
P0.1(AD1)
MOV R7,A ;save it to in reg R7
P1.2
4 37 P0.2(AD2)
P1.3
P1.4 5 36 P0.3(AD3) ACALL DELAY ;wait
P1.5 6 35 P0.4(AD4)
P1.6
P1.7
7
8
34
33
P0.5(AD5)
P0.6(AD6)
MOV A,P1 ;another data from P1
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP MOV R5,A ;save it to in reg R5
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

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 ‰ Port 2 can be used as input or output
I/O
PROGRAMMING ¾ Just like P1, port 2 does not need any pull-
up resistors since it already has pull-up
Port 2 resistors internally
¾ Upon reset, port 2 is configured as an input
port

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

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 ‰ To make port 2 an input port, it must
I/O
PROGRAMMING
be programmed as such by writing 1 to
all its bits
Port 2 as Input ‰ In many 8051-based system, P2 is used
or Dual Role as simple I/O
‰ In 8031-based systems, port 2 must be
used along with P0 to provide the 16-
P1.0
P1.1
P1.2
1
2
3
40
39
38
Vcc
P0.0(AD0)
P0.1(AD1)
bit address for the external memory
P1.3 4 37 P0.2(AD2)
P1.4
P1.5
P1.6
5
6
7
36
35
34
P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
¾ Port 2 is also designated as A8 – A15,
indicating its dual function
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031)30 ALE/PROG

Port 0 provides the lower 8 bits via A0 – A7

(INT0)P3.2 12 29 -PSEN
(INT1)P3.3
(T0)P3.4
13
14
28
27
P2.7(A15)
P2.6(A14) ¾
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

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 ‰ Port 3 can be used as input or output
I/O
PROGRAMMING ¾ Port 3 does not need any pull-up resistors
¾ Port 3 is configured as an input port upon
Port 3 reset, this is not the way it is most
commonly used

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2 12 29 -PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

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 ‰ Port 3 has the additional function of
I/O
PROGRAMMING
providing some extremely important
signals
Port 3 P3 Bit Function Pin
Serial
(cont’) P3.0 RxD 10 communications
P3.1 TxD 11
External
P3.2 INT0 12 interrupts
P3.3 INT1 13
P1.0 1
2
40
39
Vcc
P0.0(AD0) P3.4 T0 14 Timers
P1.1
P1.2 3 38 P0.1(AD1)
37
P3.5 T1 15
P1.3 4 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5) Read/Write signals
P1.7
RST
8
9
33
32
8051 31
P0.6(AD6)
P0.7(AD7) P3.6 WR 16 of external memories
(RXD)P3.0 10 -EA/VPP
(TXD)P3.1
(INT0)P3.2
(INT1)P3.3
11(8031)30
12 29
28
ALE/PROG
-PSEN
P2.7(A15)
P3.7 RD 17
13
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5
(WR)P3.6
15
16
26
25
P2.5(A13)
P2.4(A12) In systems based on 8751, 89C51 or
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10) DS89C4x0, pins 3.6 and 3.7 are used for I/O
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8) while the rest of the pins in port 3 are
normally used in the alternate function role
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 Write a program for the DS89C420 to toggle all the bits of P0, P1,
and P2 every 1/4 of a second
I/O ORG 0
PROGRAMMING BACK: MOV A,#55H
MOV P0,A
MOV P1,A
Port 3 MOV P2,A
ACALL QSDELAY ;Quarter of a second
(cont’) MOV A,#0AAH
MOV P0,A
MOV P1,A
MOV P2,A
ACALL QSDELAY
P1.0 1 40 Vcc SJMP BACK
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1) QSDELAY: Delay
P1.3 4 37 P0.2(AD2)
P1.4
P1.5
5
6
36
35
P0.3(AD3)
P0.4(AD4)
MOV R5,#11 = 11 × 248 × 255 × 4 MC × 90 ns
P1.6
P1.7
7
8
34
33
P0.5(AD5)
P0.6(AD6)
H3: MOV R4,#248 = 250,430 µs
RST 9 32 P0.7(AD7)
(RXD)P3.0 10
8051 31 -EA/VPP H2: MOV R3,#255
(TXD)P3.1 11(8031)30 ALE/PROG
(INT0)P3.2
(INT1)P3.3
12 29
28
-PSEN
P2.7(A15)
H1: DJNZ R3,H1 ;4 MC for DS89C4x0
13
(T0)P3.4
(T1)P3.5
14
15
27
26
P2.6(A14)
P2.5(A13)
DJNZ R4,H2
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11) DJNZ R5,H3
XTAL2 18 23 P2.2(A10)
XTAL1
GND
19
20
22
21
P2.1(A9)
P2.0(A8)
RET
END
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 The entire 8 bits of Port 1 are accessed
BACK: MOV A,#55H
I/O MOV P1,A
PROGRAMMING ACALL
MOV
DELAY
A,#0AAH
MOV P1,A
Different ways ACALL
SJMP
DELAY
BACK
of Accessing
Entire 8 Bits Rewrite the code in a more efficient manner by accessing the port
directly without going through the accumulator
BACK: MOV P1,#55H
ACALL DELAY
MOV P1,#0AAH
ACALL DELAY
SJMP BACK

Another way of doing the same thing

MOV A,#55H
BACK: MOV P1,A
ACALL DELAY
CPL A
SJMP BACK
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 ‰ Sometimes we need to access only 1
I/O BIT
MANIPULATION
or 2 bits of the port
PROGRAMMING BACK: CPL
ACALL
P1.2
DELAY
;complement P1.2

SJMP BACK
I/O Ports
and Bit ;another variation of the above program
AGAIN: SETB P1.2 ;set only P1.2
Addressability ACALL DELAY
CLR P1.2 ;clear only P1.2
ACALL DELAY
SJMP AGAIN P0 P1 P2 P3 Port Bit
P0.0 P1.0 P2.0 P3.0 D0
P0.1 P1.1 P2.1 P3.1 D1
P0.2 P1.2 P2.2 P3.2 D2
P0.3 P1.3 P2.3 P3.3 D3
P0.4 P1.4 P2.4 P3.4 D4
P0.5 P1.5 P2.5 P3.5 D5
P0.6 P1.6 P2.6 P3.6 D6
P0.7 P1.7 P2.7 P3.7 D7

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 Example 4-2
Write the following programs.
I/O BIT Create a square wave of 50% duty cycle on bit 0 of port 1.
MANIPULATION Solution:
PROGRAMMING The 50% duty cycle means that the “on” and “off” state (or the high
and low portion of the pulse) have the same length. Therefore,
I/O Ports we toggle P1.0 with a time delay in between each state.
and Bit HERE: SETB P1.0 ;set to high bit 0 of port 1
LCALL DELAY ;call the delay subroutine
Addressability CLR P1.0 ;P1.0=0
(cont’) LCALL DELAY
SJMP HERE ;keep doing it
Another way to write the above program is:
HERE: CPL P1.0 ;set to high bit 0 of port 1
LCALL DELAY ;call the delay subroutine
SJMP HERE ;keep doing it
8051

P1.0

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 ‰ Instructions that are used for signal-bit
I/O BIT
operations are as following
MANIPULATION
PROGRAMMING Single-Bit Instructions
Instruction Function
I/O Ports SETB bit Set the bit (bit = 1)
and Bit CLR bit Clear the bit (bit = 0)
Addressability CPL bit Complement the bit (bit = NOT bit)
(cont’) JB bit, target Jump to target if bit = 1 (jump if bit)
JNB bit, target Jump to target if bit = 0 (jump if no bit)
JBC bit, target Jump to target if bit = 1, clear bit
(jump if bit, then clear)

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 ‰ The JNB and JB instructions are widely
I/O BIT used single-bit operations
MANIPULATION ¾ They allow you to monitor a bit and make
PROGRAMMING a decision depending on whether it’s 0 or 1
¾ These two instructions can be used for any
Checking an bits of I/O ports 0, 1, 2, and 3
Input Bit ƒ Port 3 is typically not used for any I/O, either
single-bit or byte-wise

Instructions for Reading an Input Port

Mnemonic Examples Description

MOV A,PX MOV A,P2 Bring into A the data at P2 pins
JNB PX.Y, .. JNB P2.1,TARGET Jump if pin P2.1 is low
JB PX.Y, .. JB P1.3,TARGET Jump if pin P1.3 is high
MOV C,PX.Y MOV C,P2.4 Copy status of pin P2.4 to CY

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 Example 4-3
I/O BIT
Write a program to perform the following:
MANIPULATION (a) Keep monitoring the P1.2 bit until it becomes high
PROGRAMMING (b) When P1.2 becomes high, write value 45H to port 0
(c) Send a high-to-low (H-to-L) pulse to P2.3
Solution:
Checking an SETB P1.2 ;make P1.2 an input
Input Bit MOV A,#45H ;A=45H
(cont’) AGAIN: JNB P1.2,AGAIN ; get out when P1.2=1
MOV P0,A ;issue A to P0
SETB P2.3 ;make P2.3 high
CLR P2.3 ;make P2.3 low for H-to-L

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 Example 4-4
I/O BIT
Assume that bit P2.3 is an input and represents the condition of an
MANIPULATION oven. If it goes high, it means that the oven is hot. Monitor the bit
PROGRAMMING continuously. Whenever it goes high, send a high-to-low pulse to port
P1.5 to turn on a buzzer.
Solution:
Checking an
HERE: JNB P2.3,HERE ;keep monitoring for high
Input Bit SETB P1.5 ;set bit P1.5=1
(cont’) CLR P1.5 ;make high-to-low
SJMP HERE ;keep repeating

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 Example 4-5
I/O BIT
A switch is connected to pin P1.7. Write a program to check the status
MANIPULATION of SW and perform the following:
PROGRAMMING (a) If SW=0, send letter ‘N’ to P2
(b) If SW=1, send letter ‘Y’ to P2

Checking an Solution:
Input Bit
SETB P1.7 ;make P1.7 an input
AGAIN: JB P1.2,OVER ;jump if P1.7=1
(cont’)
MOV P2,#’N’ ;SW=0, issue ‘N’ to P2
SJMP AGAIN ;keep monitoring
OVER: MOV P2,#’Y’ ;SW=1, issue ‘Y’ to P2
SJMP AGAIN ;keep monitoring

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 Example 4-6
I/O BIT
A switch is connected to pin P1.7. Write a program to check the status
MANIPULATION of SW and perform the following:
PROGRAMMING (a) If SW=0, send letter ‘N’ to P2
(b) If SW=1, send letter ‘Y’ to P2
Use the carry flag to check the switch status.
Reading Single Solution:
Bit into Carry SETB P1.7 ;make P1.7 an input
Flag AGAIN: MOV C,P1.2 ;read SW status into CF
JC OVER ;jump if SW=1
MOV P2,#’N’ ;SW=0, issue ‘N’ to P2
SJMP AGAIN ;keep monitoring
OVER: MOV P2,#’Y’ ;SW=1, issue ‘Y’ to P2
SJMP AGAIN ;keep monitoring

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 Example 4-7
I/O BIT
A switch is connected to pin P1.0 and an LED to pin P2.7. Write a
MANIPULATION program to get the status of the switch and send it to the LED
PROGRAMMING
Solution:
SETB P1.7 ;make P1.7 an input
Reading Single AGAIN: MOV C,P1.0 ;read SW status into CF
Bit into Carry MOV P2.7,C ;send SW status to LED
Flag SJMP AGAIN ;keep repeating
(cont’)

The instruction
‘MOV
P2.7,P1.0’ is
wrong , since such
However ‘MOV an instruction does
P2,P1’ is a valid not exist
instruction

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 ‰ In reading a port
I/O BIT ¾ Some instructions read the status of port
MANIPULATION pins
PROGRAMMING ¾ Others read the status of an internal port
latch
Reading Input ‰ Therefore, when reading ports there
Pins vs. Port are two possibilities:
Latch ¾ Read the status of the input pin
¾ Read the internal latch of the output port
‰ Confusion between them is a major
source of errors in 8051 programming
¾ Especially where external hardware is
concerned

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 ‰ Some instructions read the contents of
READING
INPUT PINS VS.
an internal port latch instead of
PORT LATCH reading the status of an external pin
¾ For example, look at the ANL P1,A
Reading Latch instruction and the sequence of actions is
for Output Port executed as follow
1. It reads the internal latch of the port and
brings that data into the CPU
2. This data is ANDed with the contents of
register A
3. The result is rewritten back to the port latch
4. The port pin data is changed and now has the
same value as port latch

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 ‰ Read-Modify-Write
READING
¾ The instructions read the port latch
INPUT PINS VS.
normally read a value, perform an
PORT LATCH operation then rewrite it back to the port
latch
Reading Latch Instructions Reading a latch (Read-Modify-Write)
for Output Port Mnemonics Example
(cont’) ANL PX ANL P1,A
ORL PX ORL P2,A
XRL PX XRL P0,A
JBC PX.Y,TARGET JBC P1.1,TARGET
CPL PX.Y CPL P1.2
INC PX INC P1
DEC PX DEC P2
DJNZ PX.Y,TARGET DJNZ P1,TARGET
MOV PX.Y,C MOV P1.2,C
CLR PX.Y CLR P2.3 Note: x is 0, 1, 2,
SETB PX.Y SETB P2.3 or 3 for P0 – P3

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 ‰ The ports in 8051 can be accessed by
I/O BIT
MANIPULATION the Read-modify-write technique
PROGRAMMING ¾ This feature saves many lines of code by
combining in a single instruction all three
Read-modify- actions
write Feature 1. Reading the port
2. Modifying it
3. Writing to the port
MOV P1,#55H ;P1=01010101
AGAIN: XRL P1,#0FFH ;EX-OR P1 with 1111 1111
ACALL DELAY
SJMP BACK

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